From 09966a66ffd08a04306c754ce20420d05109771a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 20 Feb 2021 11:51:41 -0800 Subject: [PATCH] [RISCV] Add an additional remw test to rv64m-exhaustive-w-insts.ll. NFC This adds the IR for this C code int32_t foo(uint16_t x, int16_t y) { x %= y; return x; } Note the dividend is unsigned and the divisor is signed. C type promotion rules will extend them and use a 32-bit srem and the function returns a 32-bit result. We fail to use remw for this case. The zero extended input has enough sign bits, but we won't consider (i64 AssertZext X, i16) in the sexti32 isel pattern. We also end up with a extra shifts to zero upper bits on the result. computeKnownBits knew the result was positive before type legalization and allowed the SIGN_EXTEND to become ZERO_EXTEND. But after promoting to i64 we no longer know that bit 31 (and all bits above it) should be 0. --- llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll index e2bd2cbb30d3..a60714f5e8f7 100644 --- a/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll +++ b/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll @@ -1110,6 +1110,19 @@ define signext i16 @sext_remw_sext_sext_i16(i16 signext %a, i16 signext %b) noun ret i16 %1 } +define signext i32 @sext_i32_remw_zext_sext_i16(i16 zeroext %0, i16 signext %1) nounwind { +; RV64IM-LABEL: sext_i32_remw_zext_sext_i16: +; RV64IM: # %bb.0: +; RV64IM-NEXT: rem a0, a0, a1 +; RV64IM-NEXT: slli a0, a0, 32 +; RV64IM-NEXT: srli a0, a0, 32 +; RV64IM-NEXT: ret + %3 = sext i16 %1 to i32 + %4 = zext i16 %0 to i32 + %5 = srem i32 %4, %3 + ret i32 %5 +} + define i32 @aext_remuw_aext_aext(i32 %a, i32 %b) nounwind { ; RV64IM-LABEL: aext_remuw_aext_aext: ; RV64IM: # %bb.0: -- GitLab