From 14fc82a1df40cdf09e969ae2b5f172d474e25d4a Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Fri, 4 Aug 2017 16:44:06 +0000 Subject: [PATCH] [AArch64] Fix an assertion for pre-index generation with unscaled loads/stores. Differential Revision: https://reviews.llvm.org/D36248 PR34035 llvm-svn: 310066 --- .../AArch64/AArch64LoadStoreOptimizer.cpp | 19 ++- .../AArch64/arm64-ldst-unscaled-pre-post.mir | 115 ++++++++++++++++++ 2 files changed, 132 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index 8681b4b4a365..34584901b8a2 100644 --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -388,6 +388,10 @@ static unsigned isMatchingStore(MachineInstr &LoadInst, } static unsigned getPreIndexedOpcode(unsigned Opc) { + // FIXME: We don't currently support creating pre-indexed loads/stores when + // the load or store is the unscaled version. If we decide to perform such an + // optimization in the future the cases for the unscaled loads/stores will + // need to be added here. switch (Opc) { default: llvm_unreachable("Opcode has no pre-indexed equivalent!"); @@ -451,32 +455,42 @@ static unsigned getPostIndexedOpcode(unsigned Opc) { default: llvm_unreachable("Opcode has no post-indexed wise equivalent!"); case AArch64::STRSui: + case AArch64::STURSi: return AArch64::STRSpost; case AArch64::STRDui: + case AArch64::STURDi: return AArch64::STRDpost; case AArch64::STRQui: + case AArch64::STURQi: return AArch64::STRQpost; case AArch64::STRBBui: return AArch64::STRBBpost; case AArch64::STRHHui: return AArch64::STRHHpost; case AArch64::STRWui: + case AArch64::STURWi: return AArch64::STRWpost; case AArch64::STRXui: + case AArch64::STURXi: return AArch64::STRXpost; case AArch64::LDRSui: + case AArch64::LDURSi: return AArch64::LDRSpost; case AArch64::LDRDui: + case AArch64::LDURDi: return AArch64::LDRDpost; case AArch64::LDRQui: + case AArch64::LDURQi: return AArch64::LDRQpost; case AArch64::LDRBBui: return AArch64::LDRBBpost; case AArch64::LDRHHui: return AArch64::LDRHHpost; case AArch64::LDRWui: + case AArch64::LDURWi: return AArch64::LDRWpost; case AArch64::LDRXui: + case AArch64::LDURXi: return AArch64::LDRXpost; case AArch64::LDRSWui: return AArch64::LDRSWpost; @@ -1694,8 +1708,9 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB, ++NumPostFolded; break; } - // Don't know how to handle pre/post-index versions, so move to the next - // instruction. + + // Don't know how to handle unscaled pre/post-index versions below, so + // move to the next instruction. if (TII->isUnscaledLdSt(Opc)) { ++MBBI; break; diff --git a/llvm/test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir b/llvm/test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir new file mode 100644 index 000000000000..dacaf4966d07 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-ldst-unscaled-pre-post.mir @@ -0,0 +1,115 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s +--- +# CHECK-LABEL: name: test_LDURSi_post +# CHECK: LDRSpost %x0, -4 +name: test_LDURSi_post +body: | + bb.0.entry: + liveins: %x0 + + %s0 = LDURSi %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_LDURDi_post +# CHECK: LDRDpost %x0, -4 +name: test_LDURDi_post +body: | + bb.0.entry: + liveins: %x0 + + %d0 = LDURDi %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_LDURQi_post +# CHECK: LDRQpost %x0, -4 +name: test_LDURQi_post +body: | + bb.0.entry: + liveins: %x0 + + %q0 = LDURQi %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_LDURWi_post +# CHECK: LDRWpost %x0, -4 +name: test_LDURWi_post +body: | + bb.0.entry: + liveins: %x0 + + %w1 = LDURWi %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_LDURXi_post +# CHECK: %x1 = LDRXpost %x0, -4 +name: test_LDURXi_post +body: | + bb.0.entry: + liveins: %x0 + + %x1 = LDURXi %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_STURSi_post +# CHECK: STRSpost %s0, %x0, -4 +name: test_STURSi_post +body: | + bb.0.entry: + liveins: %x0 + + %s0 = FMOVS0 + STURSi %s0, %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_STURDi_post +# CHECK: STRDpost %d0, %x0, -4 +name: test_STURDi_post +body: | + bb.0.entry: + liveins: %x0 + + %d0 = FMOVD0 + STURDi %d0, %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_STURQi_post +# CHECK: STRQpost %q0, %x0, -4 +name: test_STURQi_post +body: | + bb.0.entry: + liveins: %x0 + + %q0 = MOVIv4i32 0, 0 + STURQi %q0, %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_STURWi_post +# CHECK: STRWpost %wzr, %x0, -4 +name: test_STURWi_post +body: | + bb.0.entry: + liveins: %x0 + + STURWi %wzr, %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... +# CHECK-LABEL: name: test_STURXi_post +# CHECK: STRXpost %xzr, %x0, -4 +name: test_STURXi_post +body: | + bb.0.entry: + liveins: %x0 + + STURXi %xzr, %x0, 0 + %x0 = SUBXri %x0, 4, 0 + RET_ReallyLR implicit %x0 +... -- GitLab