From 4db0960420b748870117969041d50a7465d785c7 Mon Sep 17 00:00:00 2001
From: Tim Renouf <tpr.llvm@botech.co.uk>
Date: Tue, 27 Mar 2018 21:14:04 +0000
Subject: [PATCH] [CodeGen] Fixed unreachable with -print-machineinstrs and
 custom pseudo source value

Summary:
Rev 327580 "[CodeGen] Use MIR syntax for MachineMemOperand printing"
broke -print-machineinstrs for us on AMDGPU, because we have custom
pseudo source values, and MIR serialization does not implement that.

This commit at least restores the functionality of -print-machineinstrs,
even if it does not properly implement the missing MIR serialization
functionality.

Differential Revision: https://reviews.llvm.org/D44871

Change-Id: I44961c0b90bf6d48c01484ed7a4e466fd300db66
llvm-svn: 328668
---
 llvm/lib/CodeGen/MachineOperand.cpp             |  7 ++++++-
 .../CodeGen/AMDGPU/print-mir-custom-pseudo.ll   | 17 +++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/print-mir-custom-pseudo.ll

diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 13bcc7a4fe4c..654a831506d6 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -1100,7 +1100,12 @@ void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
       break;
     case PseudoSourceValue::TargetCustom:
-      llvm_unreachable("TargetCustom pseudo source values are not supported");
+      // FIXME: This is not necessarily the correct MIR serialization format for
+      // a custom pseudo source value, but at least it allows
+      // -print-machineinstrs to work on a target with custom pseudo source
+      // values.
+      OS << "custom ";
+      PVal->printCustom(OS);
       break;
     }
   }
diff --git a/llvm/test/CodeGen/AMDGPU/print-mir-custom-pseudo.ll b/llvm/test/CodeGen/AMDGPU/print-mir-custom-pseudo.ll
new file mode 100644
index 000000000000..8746d4e71201
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/print-mir-custom-pseudo.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=fiji -print-after=isel -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=SI %s
+
+; This checks that the -print-after of MIR containing a target custom pseudo
+; value works correctly.
+
+; SI: TargetCustom
+
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
+target triple = "amdgcn--amdpal"
+
+define dllexport amdgpu_ps <2 x float> @_amdgpu_ps_main(i32 inreg, i32 inreg, i32 inreg, i32 inreg, <2 x float>, <2 x float>, <2 x float>, <3 x float>, <2 x float>, <2 x float>, <2 x float>, float, float, float, float, float, i32, i32, i32, i32) local_unnamed_addr {
+.entry:
+  %res = call <2 x float> @llvm.amdgcn.image.sample.l.v2f32.v4f32.v8i32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 3, i1 false, i1 false, i1 false, i1 false, i1 false)
+  ret <2 x float> %res
+}
+
+declare <2 x float> @llvm.amdgcn.image.sample.l.v2f32.v4f32.v8i32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1)
-- 
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