From 71b9afb053d9a8eb9baf3a52f82acdf9efba1c55 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 10 May 2008 06:46:49 +0000 Subject: [PATCH] When transforming a vector_shuffle to a load, the base address must not be an undef. llvm-svn: 50940 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 ++ llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll | 10 ++++++++++ 2 files changed, 12 insertions(+) create mode 100644 llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d2d76671e949..307aeae1b22c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -6283,6 +6283,8 @@ static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask, return false; if (!Base) { Base = Elt.Val; + if (Base->getOpcode() == ISD::UNDEF) + return false; continue; } if (Elt.getOpcode() == ISD::UNDEF) diff --git a/llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll b/llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll new file mode 100644 index 000000000000..9bcd1f374dd6 --- /dev/null +++ b/llvm/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 + +define fastcc void @glgVectorFloatConversion() nounwind { + %tmp12745 = load <4 x float>* null, align 16 ; <<4 x float>> [#uses=1] + %tmp12773 = insertelement <4 x float> %tmp12745, float 1.000000e+00, i32 1 ; <<4 x float>> [#uses=1] + %tmp12774 = insertelement <4 x float> %tmp12773, float 0.000000e+00, i32 2 ; <<4 x float>> [#uses=1] + %tmp12775 = insertelement <4 x float> %tmp12774, float 1.000000e+00, i32 3 ; <<4 x float>> [#uses=1] + store <4 x float> %tmp12775, <4 x float>* null, align 16 + unreachable +} -- GitLab