From 9bd9fef446dddf498ad91034956ff6f73f1f16ec Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 10 Jul 2018 16:08:28 +0000 Subject: [PATCH] [X86] Add srem/udiv/urem by constant tests Match the tests in combine-sdiv.ll llvm-svn: 336694 --- llvm/test/CodeGen/X86/combine-srem.ll | 73 ++++++++++++++++++++++ llvm/test/CodeGen/X86/combine-udiv.ll | 78 ++++++++++++++++++++++++ llvm/test/CodeGen/X86/combine-urem.ll | 88 +++++++++++++++++++++++++++ 3 files changed, 239 insertions(+) diff --git a/llvm/test/CodeGen/X86/combine-srem.ll b/llvm/test/CodeGen/X86/combine-srem.ll index e4d1df6f14d2..df5ddb1c4ecf 100644 --- a/llvm/test/CodeGen/X86/combine-srem.ll +++ b/llvm/test/CodeGen/X86/combine-srem.ll @@ -27,6 +27,79 @@ define <4 x i32> @combine_vec_srem_by_one(<4 x i32> %x) { ret <4 x i32> %1 } +; fold (srem x, -1) -> 0 +define i32 @combine_srem_by_negone(i32 %x) { +; CHECK-LABEL: combine_srem_by_negone: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq + %1 = srem i32 %x, -1 + ret i32 %1 +} + +define <4 x i32> @combine_vec_srem_by_negone(<4 x i32> %x) { +; SSE-LABEL: combine_vec_srem_by_negone: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm0, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: combine_vec_srem_by_negone: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = srem <4 x i32> %x, + ret <4 x i32> %1 +} + +; TODO fold (srem x, INT_MIN) +define i32 @combine_srem_by_minsigned(i32 %x) { +; CHECK-LABEL: combine_srem_by_minsigned: +; CHECK: # %bb.0: +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: sarl $31, %eax +; CHECK-NEXT: shrl %eax +; CHECK-NEXT: addl %edi, %eax +; CHECK-NEXT: andl $-2147483648, %eax # imm = 0x80000000 +; CHECK-NEXT: subl %eax, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq + %1 = srem i32 %x, -2147483648 + ret i32 %1 +} + +define <4 x i32> @combine_vec_srem_by_minsigned(<4 x i32> %x) { +; SSE-LABEL: combine_vec_srem_by_minsigned: +; SSE: # %bb.0: +; SSE-NEXT: movdqa %xmm0, %xmm1 +; SSE-NEXT: psrad $31, %xmm1 +; SSE-NEXT: psrld $1, %xmm1 +; SSE-NEXT: paddd %xmm0, %xmm1 +; SSE-NEXT: pand {{.*}}(%rip), %xmm1 +; SSE-NEXT: psubd %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: combine_vec_srem_by_minsigned: +; AVX1: # %bb.0: +; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 +; AVX1-NEXT: vpsrld $1, %xmm1, %xmm1 +; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1 +; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: combine_vec_srem_by_minsigned: +; AVX2: # %bb.0: +; AVX2-NEXT: vpsrad $31, %xmm0, %xmm1 +; AVX2-NEXT: vpsrld $1, %xmm1, %xmm1 +; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648] +; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %1 = srem <4 x i32> %x, + ret <4 x i32> %1 +} + ; TODO fold (srem x, x) -> 0 define i32 @combine_srem_dupe(i32 %x) { ; CHECK-LABEL: combine_srem_dupe: diff --git a/llvm/test/CodeGen/X86/combine-udiv.ll b/llvm/test/CodeGen/X86/combine-udiv.ll index 3b9b6617a743..3b636bf38e5d 100644 --- a/llvm/test/CodeGen/X86/combine-udiv.ll +++ b/llvm/test/CodeGen/X86/combine-udiv.ll @@ -21,6 +21,84 @@ define <4 x i32> @combine_vec_udiv_by_one(<4 x i32> %x) { ret <4 x i32> %1 } +; TODO fold (udiv x, -1) -> select((icmp eq x, -1), 1, 0) +define i32 @combine_udiv_by_negone(i32 %x) { +; CHECK-LABEL: combine_udiv_by_negone: +; CHECK: # %bb.0: +; CHECK-NEXT: movl %edi, %ecx +; CHECK-NEXT: movq %rcx, %rax +; CHECK-NEXT: shlq $31, %rax +; CHECK-NEXT: addq %rcx, %rax +; CHECK-NEXT: shrq $63, %rax +; CHECK-NEXT: # kill: def $eax killed $eax killed $rax +; CHECK-NEXT: retq + %1 = udiv i32 %x, -1 + ret i32 %1 +} + +define <4 x i32> @combine_vec_udiv_by_negone(<4 x i32> %x) { +; SSE-LABEL: combine_vec_udiv_by_negone: +; SSE: # %bb.0: +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483649,2147483649,2147483649,2147483649] +; SSE-NEXT: pmuludq %xmm2, %xmm1 +; SSE-NEXT: pmuludq %xmm2, %xmm0 +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] +; SSE-NEXT: psrld $31, %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: combine_vec_udiv_by_negone: +; AVX1: # %bb.0: +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2147483649,2147483649,2147483649,2147483649] +; AVX1-NEXT: vpmuludq %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] +; AVX1-NEXT: vpsrld $31, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: combine_vec_udiv_by_negone: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483649,2147483649,2147483649,2147483649] +; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] +; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] +; AVX2-NEXT: vpmuludq %xmm2, %xmm3, %xmm2 +; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3] +; AVX2-NEXT: vpsrld $31, %xmm0, %xmm0 +; AVX2-NEXT: retq + %1 = udiv <4 x i32> %x, + ret <4 x i32> %1 +} + +; fold (udiv x, INT_MIN) -> (srl x, 31) +define i32 @combine_udiv_by_minsigned(i32 %x) { +; CHECK-LABEL: combine_udiv_by_minsigned: +; CHECK: # %bb.0: +; CHECK-NEXT: shrl $31, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq + %1 = udiv i32 %x, -2147483648 + ret i32 %1 +} + +define <4 x i32> @combine_vec_udiv_by_minsigned(<4 x i32> %x) { +; SSE-LABEL: combine_vec_udiv_by_minsigned: +; SSE: # %bb.0: +; SSE-NEXT: psrld $31, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: combine_vec_udiv_by_minsigned: +; AVX: # %bb.0: +; AVX-NEXT: vpsrld $31, %xmm0, %xmm0 +; AVX-NEXT: retq + %1 = udiv <4 x i32> %x, + ret <4 x i32> %1 +} + ; TODO fold (udiv x, x) -> 1 define i32 @combine_udiv_dupe(i32 %x) { ; CHECK-LABEL: combine_udiv_dupe: diff --git a/llvm/test/CodeGen/X86/combine-urem.ll b/llvm/test/CodeGen/X86/combine-urem.ll index 91b853979f90..1ab9d523f3bb 100644 --- a/llvm/test/CodeGen/X86/combine-urem.ll +++ b/llvm/test/CodeGen/X86/combine-urem.ll @@ -27,6 +27,94 @@ define <4 x i32> @combine_vec_urem_by_one(<4 x i32> %x) { ret <4 x i32> %1 } +; TODO fold (urem x, -1) -> select((icmp eq x, -1), 0, x) +define i32 @combine_urem_by_negone(i32 %x) { +; CHECK-LABEL: combine_urem_by_negone: +; CHECK: # %bb.0: +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: movq %rax, %rcx +; CHECK-NEXT: shlq $31, %rcx +; CHECK-NEXT: addq %rax, %rcx +; CHECK-NEXT: sarq $63, %rcx +; CHECK-NEXT: subl %ecx, %edi +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq + %1 = urem i32 %x, -1 + ret i32 %1 +} + +define <4 x i32> @combine_vec_urem_by_negone(<4 x i32> %x) { +; SSE-LABEL: combine_vec_urem_by_negone: +; SSE: # %bb.0: +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483649,2147483649,2147483649,2147483649] +; SSE-NEXT: pmuludq %xmm2, %xmm1 +; SSE-NEXT: pmuludq %xmm0, %xmm2 +; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] +; SSE-NEXT: psrad $31, %xmm2 +; SSE-NEXT: psubd %xmm2, %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: combine_vec_urem_by_negone: +; AVX1: # %bb.0: +; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3] +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2147483649,2147483649,2147483649,2147483649] +; AVX1-NEXT: vpmuludq %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] +; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] +; AVX1-NEXT: vpsrad $31, %xmm1, %xmm1 +; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: combine_vec_urem_by_negone: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483649,2147483649,2147483649,2147483649] +; AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3] +; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] +; AVX2-NEXT: vpmuludq %xmm2, %xmm3, %xmm2 +; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm1 +; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] +; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3] +; AVX2-NEXT: vpsrad $31, %xmm1, %xmm1 +; AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %1 = urem <4 x i32> %x, + ret <4 x i32> %1 +} + +; fold (urem x, INT_MIN) -> (and x, ~INT_MIN) +define i32 @combine_urem_by_minsigned(i32 %x) { +; CHECK-LABEL: combine_urem_by_minsigned: +; CHECK: # %bb.0: +; CHECK-NEXT: andl $2147483647, %edi # imm = 0x7FFFFFFF +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: retq + %1 = urem i32 %x, -2147483648 + ret i32 %1 +} + +define <4 x i32> @combine_vec_urem_by_minsigned(<4 x i32> %x) { +; SSE-LABEL: combine_vec_urem_by_minsigned: +; SSE: # %bb.0: +; SSE-NEXT: andps {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: combine_vec_urem_by_minsigned: +; AVX1: # %bb.0: +; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: combine_vec_urem_by_minsigned: +; AVX2: # %bb.0: +; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647] +; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq + %1 = urem <4 x i32> %x, + ret <4 x i32> %1 +} + ; TODO fold (urem x, x) -> 0 define i32 @combine_urem_dupe(i32 %x) { ; CHECK-LABEL: combine_urem_dupe: -- GitLab