The exp parameter is the condition. The c parameter is - the expected comparision value. If it is equal to 1 (true), the condition is + the expected comparison value. If it is equal to 1 (true), the condition is likely to be true, in other case condition is likely to be false. For example:
- This file demotes all registers to memory references. It is intented to be + This file demotes all registers to memory references. It is intended to be the inverse of -mem2reg. By converting to load instructions, the only values live across basic blocks are alloca instructions and load instructions before diff --git a/llvm/docs/SourceLevelDebugging.html b/llvm/docs/SourceLevelDebugging.html index 88522781cc4d723d1bb994b2e5ae0970466f5f03..918383bc21302f4aa807014eaab1bbe9ecb9fd9a 100644 --- a/llvm/docs/SourceLevelDebugging.html +++ b/llvm/docs/SourceLevelDebugging.html @@ -2712,7 +2712,7 @@ HashData[hash_data_count] has address attributes: DW_AT_low_pc, DW_AT_high_pc, DW_AT_ranges or DW_AT_entry_pc. It also contains DW_TAG_variable DIEs that have a DW_OP_addr in the location (global and static variables). All global and static variables - should be included, including those scoped withing functions and classes. For + should be included, including those scoped within functions and classes. For example using the following code:
diff --git a/llvm/docs/index.rst b/llvm/docs/index.rst
index ca31efaf17428332359a6449bf37b76af01bcc9f..53d3e7c01b7c2572aa2bd26a91e57f766e5d68af 100644
--- a/llvm/docs/index.rst
+++ b/llvm/docs/index.rst
@@ -13,7 +13,7 @@ industrial strength compilers to specialized JIT applications to small
research projects.
Similarly, documentation is broken down into several high-level groupings
-targetted at different audiences:
+targeted at different audiences:
* **Design & Overview**
diff --git a/llvm/examples/ExceptionDemo/ExceptionDemo.cpp b/llvm/examples/ExceptionDemo/ExceptionDemo.cpp
index cf078bb3f54346308776115d2d1e8082768431c3..0702baeb975149d0b83b3a2c6400259ed2cda155 100644
--- a/llvm/examples/ExceptionDemo/ExceptionDemo.cpp
+++ b/llvm/examples/ExceptionDemo/ExceptionDemo.cpp
@@ -1257,7 +1257,7 @@ llvm::Function *createCatchWrappedInvokeFunction(llvm::Module &module,
// FIXME: Redundant storage which, beyond utilizing value of
// caughtResultStore for unwindException storage, may be alleviated
- // alltogether with a block rearrangement
+ // altogether with a block rearrangement
builder.CreateStore(caughtResult, caughtResultStorage);
builder.CreateStore(unwindException, exceptionStorage);
builder.CreateStore(ourExceptionThrownState, exceptionCaughtFlag);
diff --git a/llvm/include/llvm-c/Core.h b/llvm/include/llvm-c/Core.h
index 87bf070a051fcaa678f75265312b97067899f79b..17f036d613bf59955091e4bbbfbb87177ac9074b 100644
--- a/llvm/include/llvm-c/Core.h
+++ b/llvm/include/llvm-c/Core.h
@@ -2115,7 +2115,7 @@ LLVMBasicBlockRef LLVMGetInstructionParent(LLVMValueRef Inst);
LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst);
/**
- * Obtain the instruction that occured before this one.
+ * Obtain the instruction that occurred before this one.
*
* If the instruction is the first instruction in a basic block, NULL
* will be returned.
diff --git a/llvm/include/llvm/Analysis/BlockFrequencyImpl.h b/llvm/include/llvm/Analysis/BlockFrequencyImpl.h
index 6f2ccfb19901557b98519a3ee00399f8c8be5697..5168ab78729bc39f5703da8d4cd1d5b1ffd02917 100644
--- a/llvm/include/llvm/Analysis/BlockFrequencyImpl.h
+++ b/llvm/include/llvm/Analysis/BlockFrequencyImpl.h
@@ -217,7 +217,7 @@ class BlockFrequencyImpl {
divBlockFreq(BB, BranchProbability(Numerator, EntryFreq));
}
- /// doLoop - Propagate block frequency down throught the loop.
+ /// doLoop - Propagate block frequency down through the loop.
void doLoop(BlockT *Head, BlockT *Tail) {
DEBUG(dbgs() << "doLoop(" << getBlockName(Head) << ", "
<< getBlockName(Tail) << ")\n");
diff --git a/llvm/include/llvm/Analysis/DIBuilder.h b/llvm/include/llvm/Analysis/DIBuilder.h
index 4bb321bfd4a087651a08c925d49c4207919408f1..35fd0d089a5e5682ff3de6db047dc727431f4824 100644
--- a/llvm/include/llvm/Analysis/DIBuilder.h
+++ b/llvm/include/llvm/Analysis/DIBuilder.h
@@ -177,7 +177,7 @@ namespace llvm {
/// @param OffsetInBits Member offset.
/// @param Flags Flags to encode member attribute, e.g. private
/// @param Ty Parent type.
- /// @param PropertyName Name of the Objective C property assoicated with
+ /// @param PropertyName Name of the Objective C property associated with
/// this ivar.
/// @param GetterName Name of the Objective C property getter selector.
/// @param SetterName Name of the Objective C property setter selector.
diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
index 7c2864fb4a98556099e823a0d131e4eaaeeadd1b..e380650eea1202185c2cbb63128f133b18918683 100644
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -582,7 +582,7 @@ namespace ISD {
// TRAP - Trapping instruction
TRAP,
- // DEBUGTRAP - Trap intented to get the attention of a debugger.
+ // DEBUGTRAP - Trap intended to get the attention of a debugger.
DEBUGTRAP,
// PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index dcf72c794189ce2ea7b6051671311e6d6b3a78bc..968cc56d5cff187a02ce68d81bb484863f452f93 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -230,7 +230,7 @@ namespace llvm {
///
LoopDependencies LoopRegs;
- /// DbgValues - Remember instruction that preceeds DBG_VALUE.
+ /// DbgValues - Remember instruction that precedes DBG_VALUE.
/// These are generated by buildSchedGraph but persist so they can be
/// referenced when emitting the final schedule.
typedef std::vector >
diff --git a/llvm/include/llvm/CodeGen/SlotIndexes.h b/llvm/include/llvm/CodeGen/SlotIndexes.h
index 02d64c95a8f0be7cb01704d49ba4566581c6bcab..c7fa512d0eccd336cd3b168a2d4c784f3f5aba7b 100644
--- a/llvm/include/llvm/CodeGen/SlotIndexes.h
+++ b/llvm/include/llvm/CodeGen/SlotIndexes.h
@@ -576,7 +576,7 @@ namespace llvm {
nextItr = getIndexAfter(mi).listEntry();
prevItr = prior(nextItr);
} else {
- // Insert mi's index immediately after the preceeding instruction.
+ // Insert mi's index immediately after the preceding instruction.
prevItr = getIndexBefore(mi).listEntry();
nextItr = llvm::next(prevItr);
}
diff --git a/llvm/include/llvm/Instructions.h b/llvm/include/llvm/Instructions.h
index 7d82fdaa7a115e08466fddb6780292db46c90816..f5a48cd47e0952dff18b50bc7d05c673aa79b2db 100644
--- a/llvm/include/llvm/Instructions.h
+++ b/llvm/include/llvm/Instructions.h
@@ -2239,7 +2239,7 @@ public:
/// getNumClauses - Get the number of clauses for this landing pad.
unsigned getNumClauses() const { return getNumOperands() - 1; }
- /// reserveClauses - Grow the size of the operand list to accomodate the new
+ /// reserveClauses - Grow the size of the operand list to accommodate the new
/// number of clauses.
void reserveClauses(unsigned Size) { growOperands(Size); }
diff --git a/llvm/include/llvm/Object/Binary.h b/llvm/include/llvm/Object/Binary.h
index 77a08d597c4df534d1978b0c554bfc4f4bdce969..befe812a369242ff9a6a1ab4d46248d5deaedba8 100644
--- a/llvm/include/llvm/Object/Binary.h
+++ b/llvm/include/llvm/Object/Binary.h
@@ -90,7 +90,7 @@ public:
/// @brief Create a Binary from Source, autodetecting the file type.
///
-/// @param Source The data to create the Binary from. Ownership is transfered
+/// @param Source The data to create the Binary from. Ownership is transferred
/// to Result if successful. If an error is returned, Source is destroyed
/// by createBinary before returning.
/// @param Result A pointer to the resulting Binary if no error occured.
diff --git a/llvm/include/llvm/Object/ELF.h b/llvm/include/llvm/Object/ELF.h
index e493f5bd9296db1cebee3653db4081f385abb9d7..4e6f50d97a318592fd309bb7fbed8c781496a8fe 100644
--- a/llvm/include/llvm/Object/ELF.h
+++ b/llvm/include/llvm/Object/ELF.h
@@ -217,7 +217,7 @@ struct Elf_Verdef_Impl {
}
};
-/// Elf_Verdaux: This is the structure of auxilary data in the SHT_GNU_verdef
+/// Elf_Verdaux: This is the structure of auxiliary data in the SHT_GNU_verdef
/// section (.gnu.version_d). This structure is identical for ELF32 and ELF64.
template
struct Elf_Verdaux_Impl {
diff --git a/llvm/include/llvm/Support/IntegersSubset.h b/llvm/include/llvm/Support/IntegersSubset.h
index 7f903cc8a004a0e5afd55bf5cce51a5bf034395c..ac4eb97a3ad52dc68c55b4234b2bb359c99ed164 100644
--- a/llvm/include/llvm/Support/IntegersSubset.h
+++ b/llvm/include/llvm/Support/IntegersSubset.h
@@ -102,7 +102,7 @@ public:
return (const APInt&)ConstantIntVal->getValue();
}
- // Propogate APInt operators.
+ // Propagate APInt operators.
// Note, that
// /,/=,>>,>>= are not implemented in APInt.
// <<= is implemented for unsigned RHS, but not implemented for APInt RHS.
diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp
index 615a7e6b7e31a72be14ecc534d416c6c84dc7bbd..a6bf4a86a9a57883ee28617cc03387509a182d15 100644
--- a/llvm/lib/Analysis/InlineCost.cpp
+++ b/llvm/lib/Analysis/InlineCost.cpp
@@ -178,7 +178,7 @@ bool CallAnalyzer::lookupSROAArgAndCost(
/// \brief Disable SROA for the candidate marked by this cost iterator.
///
-/// This markes the candidate as no longer viable for SROA, and adds the cost
+/// This marks the candidate as no longer viable for SROA, and adds the cost
/// savings associated with it back into the inline cost measurement.
void CallAnalyzer::disableSROA(DenseMap::iterator CostIt) {
// If we're no longer able to perform SROA we need to undo its cost savings
diff --git a/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp b/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
index f80b4f8cdf2c84ee59f8e6c8f38b024af38ed688..21ab7a8d38281b2fe783ec27eaa91beee21bdcef 100644
--- a/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
+++ b/llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
@@ -906,7 +906,7 @@ getNonLocalPointerDepFromBB(const PHITransAddr &Pointer,
if (!Pair.second) {
if (CacheInfo->Size < Loc.Size) {
// The query's Size is greater than the cached one. Throw out the
- // cached data and procede with the query at the greater size.
+ // cached data and proceed with the query at the greater size.
CacheInfo->Pair = BBSkipFirstBlockPair();
CacheInfo->Size = Loc.Size;
for (NonLocalDepInfo::iterator DI = CacheInfo->NonLocalDeps.begin(),
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index b49c65f3706e22766a245dce4900ddcb2437b0e5..886812be5faa58a76bfb0af8590b45ff3fd47ace 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -1838,7 +1838,7 @@ static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow) {
/// Compute the result of "n choose k", the binomial coefficient. If an
/// intermediate computation overflows, Overflow will be set and the return will
-/// be garbage. Overflow is not cleared on absense of overflow.
+/// be garbage. Overflow is not cleared on absence of overflow.
static uint64_t Choose(uint64_t n, uint64_t k, bool &Overflow) {
// We use the multiplicative formula:
// n(n-1)(n-2)...(n-(k-1)) / k(k-1)(k-2)...1 .
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index edfebe1b6c7e27290d00509e90b69bd32654aded..fb65bb7f3fab8b92de24f659b99a1f1099059951 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -1466,7 +1466,7 @@ static MachineBasicBlock *findFalseBlock(MachineBasicBlock *BB,
}
/// findHoistingInsertPosAndDeps - Find the location to move common instructions
-/// in successors to. The location is ususally just before the terminator,
+/// in successors to. The location is usually just before the terminator,
/// however if the terminator is a conditional branch and its previous
/// instruction is the flag setting instruction, the previous instruction is
/// the preferred location. This function also gathers uses and defs of the
diff --git a/llvm/lib/CodeGen/CodePlacementOpt.cpp b/llvm/lib/CodeGen/CodePlacementOpt.cpp
index c13c05e26a20e6329c15a08ac8ec44c012b85ac4..99233dfc2e3c08aacdcef2876a94d5baca441133 100644
--- a/llvm/lib/CodeGen/CodePlacementOpt.cpp
+++ b/llvm/lib/CodeGen/CodePlacementOpt.cpp
@@ -201,7 +201,7 @@ bool CodePlacementOpt::EliminateUnconditionalJumpsToTop(MachineFunction &MF,
// fallthrough edge.
if (!Prior->isSuccessor(End))
goto next_pred;
- // Otherwise we can stop scanning and procede to move the blocks.
+ // Otherwise we can stop scanning and proceed to move the blocks.
break;
}
// If we hit a switch or something complicated, don't move anything
diff --git a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
index 9cec59030a0bf60dda23a91d12bf9b0f254c92c1..a9de1c7490f12e7a21ca5404b00c74b689d65700 100644
--- a/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
@@ -228,7 +228,7 @@ void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
unsigned Count) {
// Update liveness.
- // Proceding upwards, registers that are defed but not used in this
+ // Proceeding upwards, registers that are defed but not used in this
// instruction are now dead.
if (!TII->isPredicated(MI)) {
diff --git a/llvm/lib/CodeGen/ExecutionDepsFix.cpp b/llvm/lib/CodeGen/ExecutionDepsFix.cpp
index 9237f7efc2984d7b13a818bdd33b3f4cd544ec35..fee8e47b832cb47f5607ac74fcc5c05499a0c6a1 100644
--- a/llvm/lib/CodeGen/ExecutionDepsFix.cpp
+++ b/llvm/lib/CodeGen/ExecutionDepsFix.cpp
@@ -59,7 +59,7 @@ struct DomainValue {
// Pointer to the next DomainValue in a chain. When two DomainValues are
// merged, Victim.Next is set to point to Victor, so old DomainValue
- // references can be updated by folowing the chain.
+ // references can be updated by following the chain.
DomainValue *Next;
// Twiddleable instructions using or defining these registers.
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index 5ba68517b7a1f62a822eb7fe64e98f41500ead8b..9ca0ad2e241618b0038d61d841b0b2e62d4ff924 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -11,7 +11,7 @@
// structure and branch probability estimates.
//
// The pass strives to preserve the structure of the CFG (that is, retain
-// a topological ordering of basic blocks) in the absense of a *strong* signal
+// a topological ordering of basic blocks) in the absence of a *strong* signal
// to the contrary from probabilities. However, within the CFG structure, it
// attempts to choose an ordering which favors placing more likely sequences of
// blocks adjacent to each other.
@@ -180,7 +180,7 @@ class MachineBlockPlacement : public MachineFunctionPass {
/// \brief Allocator and owner of BlockChain structures.
///
/// We build BlockChains lazily by merging together high probability BB
- /// sequences acording to the "Algo2" in the paper mentioned at the top of
+ /// sequences according to the "Algo2" in the paper mentioned at the top of
/// the file. To reduce malloc traffic, we allocate them using this slab-like
/// allocator, and destroy them after the pass completes.
SpecificBumpPtrAllocator ChainAllocator;
@@ -329,7 +329,7 @@ MachineBasicBlock *MachineBlockPlacement::selectBestSuccessor(
// the MBPI analysis, we manually compute probabilities using the edge
// weights. This is suboptimal as it means that the somewhat subtle
// definition of edge weight semantics is encoded here as well. We should
- // improve the MBPI interface to effeciently support query patterns such as
+ // improve the MBPI interface to efficiently support query patterns such as
// this.
uint32_t BestWeight = 0;
uint32_t WeightScale = 0;
@@ -1053,7 +1053,7 @@ namespace {
///
/// A separate pass to compute interesting statistics for evaluating block
/// placement. This is separate from the actual placement pass so that they can
-/// be computed in the absense of any placement transformations or when using
+/// be computed in the absence of any placement transformations or when using
/// alternative placement strategies.
class MachineBlockPlacementStats : public MachineFunctionPass {
/// \brief A handle to the branch probability pass.
diff --git a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
index ff0136e08cd9a90e43b3a1b6a4ef6cdf982cc889..2695163aae56add4ef69af4feeb9b6be0cb76471 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
@@ -50,7 +50,7 @@ ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) :
const TargetMachine &tm = (*IS->MF).getTarget();
ResourcesModel = tm.getInstrInfo()->CreateTargetScheduleState(&tm,NULL);
- // This hard requirment could be relaxed, but for now
+ // This hard requirement could be relaxed, but for now
// do not let it procede.
assert (ResourcesModel && "Unimplemented CreateTargetScheduleState.");
@@ -353,7 +353,7 @@ signed ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned RCId) {
}
/// Estimates change in reg pressure from this SU.
-/// It is acheived by trivial tracking of defined
+/// It is achieved by trivial tracking of defined
/// and used vregs in dependent instructions.
/// The RawPressure flag makes this function to ignore
/// existing reg file sizes, and report raw def/use
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 305d03a2419e3454690e11ea4a09ccb376e742c7..ab3ce48aacbd7bdd36f71e29af7d77a1fd66df0b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -844,7 +844,7 @@ void SelectionDAGBuilder::clear() {
}
/// clearDanglingDebugInfo - Clear the dangling debug information
-/// map. This function is seperated from the clear so that debug
+/// map. This function is separated from the clear so that debug
/// information that is dangling in a basic block can be properly
/// resolved in a different basic block. This allows the
/// SelectionDAG to resolve dangling debug information attached
@@ -2810,7 +2810,7 @@ void SelectionDAGBuilder::visitExtractElement(const User &I) {
}
// Utility for visitShuffleVector - Return true if every element in Mask,
-// begining from position Pos and ending in Pos+Size, falls within the
+// beginning from position Pos and ending in Pos+Size, falls within the
// specified sequential range [L, L+Pos). or is undef.
static bool isSequentialInRange(const SmallVectorImpl &Mask,
unsigned Pos, unsigned Size, int Low) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index dbf959b9b6fa2dfa39a91c4cda7f1a7af9de22f1..d0fde6f01d6d87f3a3863c7d21b1938eddd56e97 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -340,7 +340,7 @@ public:
void clear();
/// clearDanglingDebugInfo - Clear the dangling debug information
- /// map. This function is seperated from the clear so that debug
+ /// map. This function is separated from the clear so that debug
/// information that is dangling in a basic block can be properly
/// resolved in a different basic block. This allows the
/// SelectionDAG to resolve dangling debug information attached
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 56b17198cd96e6030cb2f98518dab83bebd43daf..a54b5b1a8d7c46f529ae22560120f8f6b6c75d1d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2008,7 +2008,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
}
}
- // Make sure we're not loosing bits from the constant.
+ // Make sure we're not losing bits from the constant.
if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
index bd6d287a91e58e729d9bc44adfd4a4b668c628d2..c38ca696f27bd731bc9be64d804a5e0b49db4da4 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
@@ -145,7 +145,7 @@ protected:
// in the relocation list where it's stored.
typedef SmallVector RelocationList;
// Relocations to sections already loaded. Indexed by SectionID which is the
- // source of the address. The target where the address will be writen is
+ // source of the address. The target where the address will be written is
// SectionID/Offset in the relocation itself.
DenseMap Relocations;
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp
index 26f35b77567fc101819da3bc695b33d26d0502b2..7be86fdba6d7990539fdba7ebb8e4ea06d5aff15 100644
--- a/llvm/lib/MC/MCParser/AsmParser.cpp
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp
@@ -472,7 +472,7 @@ bool AsmParser::EnterIncludeFile(const std::string &Filename) {
}
/// Process the specified .incbin file by seaching for it in the include paths
-/// then just emiting the byte contents of the file to the streamer. This
+/// then just emitting the byte contents of the file to the streamer. This
/// returns true on failure.
bool AsmParser::ProcessIncbinFile(const std::string &Filename) {
std::string IncludedFile;
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index cf7d07c1d3a18f8c2e2a11a7ab1193f4055ddac9..8ffb5752c895151bddf908d1a62ddd2f7bb3f5b6 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -2698,7 +2698,7 @@ defm STRHT : AI3strT<0b1011, "strht">;
multiclass arm_ldst_mult {
// IA is the default, so no need for an explicit suffix on the
- // mnemonic here. Without it is the cannonical spelling.
+ // mnemonic here. Without it is the canonical spelling.
def IA :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
@@ -3412,7 +3412,7 @@ class AsMul1I64 opcod, dag oops, dag iops, InstrItinClass itin,
// FIXME: The v5 pseudos are only necessary for the additional Constraint
// property. Remove them when it's possible to add those properties
-// on an individual MachineInstr, not just an instuction description.
+// on an individual MachineInstr, not just an instruction description.
let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
(ins GPRnopc:$Rn, GPRnopc:$Rm),
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index ce6785a29813a388428cc8c7c23d8346dacf5123..66daa1cb693d23b5205be37927522dbbbe44d4af 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -1403,7 +1403,7 @@ def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
// For round-trip assembly/disassembly, we have to handle a CPS instruction
// without any iflags. That's not, strictly speaking, valid syntax, but it's
-// a useful extention and assembles to defined behaviour (the insn does
+// a useful extension and assembles to defined behaviour (the insn does
// nothing).
def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 86985d20ded99712310fb6fe41396de00bab1550..2fae489371dacdd770a64be571adb663afbf5689 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6789,8 +6789,8 @@ processInstruction(MCInst &Inst,
case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
}
- unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
- if (Ammount == 32) Ammount = 0;
+ unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
+ if (Amount == 32) Amount = 0;
TmpInst.setOpcode(newOpc);
TmpInst.addOperand(Inst.getOperand(0)); // Rd
if (isNarrow)
@@ -6798,7 +6798,7 @@ processInstruction(MCInst &Inst,
Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
TmpInst.addOperand(Inst.getOperand(1)); // Rn
if (newOpc != ARM::t2RRX)
- TmpInst.addOperand(MCOperand::CreateImm(Ammount));
+ TmpInst.addOperand(MCOperand::CreateImm(Amount));
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
TmpInst.addOperand(Inst.getOperand(4));
if (!isNarrow)
@@ -7400,7 +7400,7 @@ MatchAndEmitInstruction(SMLoc IDLoc,
return Error(IDLoc, "invalid instruction",
((ARMOperand*)Operands[0])->getLocRange());
case Match_ConversionFail:
- // The converter function will have already emited a diagnostic.
+ // The converter function will have already emitted a diagnostic.
return true;
case Match_RequiresNotITBlock:
return Error(IDLoc, "flag setting instruction only valid outside IT block");
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index c31cf43a11e34aaa527faa4628655c9bfe74ed74..1357cc54e6ed0019730dde81cd9ba8ee74e9de23 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -491,7 +491,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) {
TII->get(Hexagon::NEG), CountReg).addReg(CountReg1);
}
- // Add the Loop instruction to the begining of the loop.
+ // Add the Loop instruction to the beginning of the loop.
BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg);
} else {
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 1fa1d10009ef6104e76ba2492344b28b45b49938..7505617221e9a97ef581ad78a4c8bd2260130d2d 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -508,7 +508,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// Build a sequence of copy-to-reg nodes chained together with token
// chain and flag operands which copy the outgoing args into registers.
- // The InFlag in necessary since all emited instructions must be
+ // The InFlag in necessary since all emitted instructions must be
// stuck together.
SDValue InFlag;
if (!isTailCall) {
@@ -528,7 +528,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// than necessary, because it means that each store effectively depends
// on every argument instead of just those arguments it would clobber.
//
- // Do not flag preceeding copytoreg stuff together with the following stuff.
+ // Do not flag preceding copytoreg stuff together with the following stuff.
InFlag = SDValue();
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
diff --git a/llvm/lib/Target/Hexagon/HexagonImmediates.td b/llvm/lib/Target/Hexagon/HexagonImmediates.td
index e78bb790ae7d3cf88cbddbbffaa34d91f58fdb34..18692c4dcc5ec02a4e27bc91e5375a07fa9f5a47 100644
--- a/llvm/lib/Target/Hexagon/HexagonImmediates.td
+++ b/llvm/lib/Target/Hexagon/HexagonImmediates.td
@@ -371,7 +371,7 @@ def s4_3ImmPred : PatLeaf<(i32 imm), [{
def u64ImmPred : PatLeaf<(i64 imm), [{
// immS16 predicate - True if the immediate fits in a 16-bit sign extended
// field.
- // Adding "N ||" to supress gcc unused warning.
+ // Adding "N ||" to suppress gcc unused warning.
return (N || true);
}]>;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index 8eb6868fc70d439e33891328888cad5362bfd74d..16448004a8c6d9cbbd483c3e4a26bab0c61b702e 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -3029,7 +3029,7 @@ def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
(i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
subreg_loreg))))))>;
-// We want to prevent emiting pnot's as much as possible.
+// We want to prevent emitting pnot's as much as possible.
// Map brcond with an unsupported setcc to a JMP_cNot.
def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
bb:$offset),
diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
index 051fc1971e741521d434dac258699555b979b657..c93b56debe51577f0fb813ecc6f7f87bbc8e571d 100644
--- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -9,9 +9,9 @@
//
// This implements NewValueJump pass in Hexagon.
// Ideally, we should merge this as a Peephole pass prior to register
-// allocation, but becuase we have a spill in between the feeder and new value
+// allocation, but because we have a spill in between the feeder and new value
// jump instructions, we are forced to write after register allocation.
-// Having said that, we should re-attempt to pull this ealier at some piont
+// Having said that, we should re-attempt to pull this earlier at some point
// in future.
// The basic approach looks for sequence of predicated jump, compare instruciton
diff --git a/llvm/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp b/llvm/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
index 66a00e12dd09a45c77005dbeca0694940214156c..2468f0b86f8817760ea5909838d778a191261c4c 100644
--- a/llvm/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
@@ -1,4 +1,4 @@
-//===- HexagonRemoveExtendArgs.cpp - Remove unecessary argument sign extends =//
+//===- HexagonRemoveExtendArgs.cpp - Remove unnecessary argument sign extends //
//
// The LLVM Compiler Infrastructure
//
diff --git a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
index 76b839b2127f31b1f892f24772e53fbeec9fe87b..3d8a6f918ff68f25adb47e29dc1c66cb00b45b5d 100644
--- a/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
+++ b/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.h
@@ -16,7 +16,7 @@
#include "llvm/MC/MCInstPrinter.h"
namespace llvm {
-// These enumeration declarations were orignally in MipsInstrInfo.h but
+// These enumeration declarations were originally in MipsInstrInfo.h but
// had to be moved here to avoid circular dependencies between
// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
namespace Mips {
diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 8784737d33ea576931dc7bab3f8c9f8c8c41bbef..62f7cdea3c0382aec1a91b5a4064c823cb785a3e 100644
--- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -190,7 +190,7 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
// We emit only the last instruction here.
//
// GNU linker requires that the first two instructions appear at the beginning
- // of a funtion and no instructions be inserted before or between them.
+ // of a function and no instructions be inserted before or between them.
// The two instructions are emitted during lowering to MC layer in order to
// avoid any reordering.
//
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 1ed206b2c745f55a02141c205a84b873dce80671..8a410b872925e4b27dbda5180e142a2e79511bb0 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -846,7 +846,7 @@ multiclass FPCONTRACT32 {
[(set Float32Regs:$dst, (fadd
(fmul Float32Regs:$a, Float32Regs:$b),
Float32Regs:$c))]>, Requires<[Pred]>;
- // This is to WAR a wierd bug in Tablegen that does not automatically
+ // This is to WAR a weird bug in Tablegen that does not automatically
// generate the following permutated rule rrr2 from the above rrr.
// So we explicitly add it here. This happens to FMA32 only.
// See the comments at FMAD32 and FMA32 for more information.
diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp
index ed1707da13d8b71a96c4846945d32d3950267ef5..711ee41699e5a046015df03fbb15a01c9b8902c2 100644
--- a/llvm/lib/Target/X86/X86FloatingPoint.cpp
+++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp
@@ -130,7 +130,7 @@ namespace {
// The hardware keeps track of how many FP registers are live, so we have
// to model that exactly. Usually, each live register corresponds to an
// FP register, but when dealing with calls, returns, and inline
- // assembly, it is sometimes neccesary to have live scratch registers.
+ // assembly, it is sometimes necessary to have live scratch registers.
unsigned Stack[8]; // FP Registers in each stack slot...
unsigned StackTop; // The current top of the FP stack.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8d0e843e256a597f31711add0b695c93191a0374..4baa1a6bbbcfb913852568c19902fa4f0b039763 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3191,7 +3191,7 @@ static bool isUndefOrEqual(int Val, int CmpVal) {
return false;
}
-/// isSequentialOrUndefInRange - Return true if every element in Mask, begining
+/// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
/// from position Pos and ending in Pos+Size, falls within the specified
/// sequential range (L, L+Pos]. or is undef.
static bool isSequentialOrUndefInRange(ArrayRef Mask,
@@ -6333,7 +6333,7 @@ SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
if (NumElems == 4)
- // If we don't care about the second element, procede to use movss.
+ // If we don't care about the second element, proceed to use movss.
if (SVOp->getMaskElt(1) != -1)
return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
}
diff --git a/llvm/lib/Target/X86/X86VZeroUpper.cpp b/llvm/lib/Target/X86/X86VZeroUpper.cpp
index 65271dbaed70874874bdc18da1b2a8e098c7d59a..e4f567ffd5d9a59f5d823527df7883344dd20841 100644
--- a/llvm/lib/Target/X86/X86VZeroUpper.cpp
+++ b/llvm/lib/Target/X86/X86VZeroUpper.cpp
@@ -205,7 +205,7 @@ bool VZeroUpperInserter::processBasicBlock(MachineFunction &MF,
}
- // The entry MBB for the function may set the inital state to dirty if
+ // The entry MBB for the function may set the initial state to dirty if
// the function receives any YMM incoming arguments
if (MBB == MF.begin()) {
EntryState = ST_CLEAN;
diff --git a/llvm/lib/Transforms/IPO/Inliner.cpp b/llvm/lib/Transforms/IPO/Inliner.cpp
index 29a82189054a50edeecc1c1ec1482c9a6253cec8..712888aee9e58ef752f3fdfb19717182bc7161de 100644
--- a/llvm/lib/Transforms/IPO/Inliner.cpp
+++ b/llvm/lib/Transforms/IPO/Inliner.cpp
@@ -36,7 +36,7 @@ STATISTIC(NumCallsDeleted, "Number of call sites deleted, not inlined");
STATISTIC(NumDeleted, "Number of functions deleted because all callers found");
STATISTIC(NumMergedAllocas, "Number of allocas merged together");
-// This weirdly named statistic tracks the number of times that, when attemting
+// This weirdly named statistic tracks the number of times that, when attempting
// to inline a function A into B, we analyze the callers of B in order to see
// if those would be more profitable and blocked inline steps.
STATISTIC(NumCallerCallersAnalyzed, "Number of caller-callers analyzed");
diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index c69abcb6409d3dd57c06e020f8a12c093cbd37a8..94c229a8e2440da07c098ec18102cd6a1bd81b9e 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -2194,7 +2194,7 @@ LSRInstance::FindUseWithSimilarFormula(const Formula &OrigF,
return &LU;
// This is the formula where all the registers and symbols matched;
// there aren't going to be any others. Since we declined it, we
- // can skip the rest of the formulae and procede to the next LSRUse.
+ // can skip the rest of the formulae and proceed to the next LSRUse.
break;
}
}
diff --git a/llvm/lib/Transforms/Scalar/ObjCARC.cpp b/llvm/lib/Transforms/Scalar/ObjCARC.cpp
index 9eb103914149610b0995b05ce622ac9e26e937fd..d89996a1ff64fb795ef0c60cde2b61f13b91653b 100644
--- a/llvm/lib/Transforms/Scalar/ObjCARC.cpp
+++ b/llvm/lib/Transforms/Scalar/ObjCARC.cpp
@@ -812,7 +812,7 @@ ObjCARCAliasAnalysis::getModRefInfo(ImmutableCallSite CS, const Location &Loc) {
case IC_FusedRetainAutorelease:
case IC_FusedRetainAutoreleaseRV:
// These functions don't access any memory visible to the compiler.
- // Note that this doesn't include objc_retainBlock, becuase it updates
+ // Note that this doesn't include objc_retainBlock, because it updates
// pointers when it copies block data.
return NoModRef;
default:
diff --git a/llvm/lib/Transforms/Scalar/Reassociate.cpp b/llvm/lib/Transforms/Scalar/Reassociate.cpp
index 0da70b37615328197b5547e998e80858c77913ff..d036c6654c78c279791703554aaea0831c974e7f 100644
--- a/llvm/lib/Transforms/Scalar/Reassociate.cpp
+++ b/llvm/lib/Transforms/Scalar/Reassociate.cpp
@@ -1164,7 +1164,7 @@ bool Reassociate::collectMultiplyFactors(SmallVectorImpl &Ops,
++Count;
if (Count == 1)
continue;
- // Move an even number of occurences to Factors.
+ // Move an even number of occurrences to Factors.
Count &= ~1U;
Idx -= Count;
FactorPowerSum += Count;
diff --git a/llvm/lib/Transforms/Scalar/Reg2Mem.cpp b/llvm/lib/Transforms/Scalar/Reg2Mem.cpp
index 47afc770bb0c12d0c104ef41b9a692d17c1d8ef1..98b0d5f6d570207b10720bf154d6c90ec7fc89df 100644
--- a/llvm/lib/Transforms/Scalar/Reg2Mem.cpp
+++ b/llvm/lib/Transforms/Scalar/Reg2Mem.cpp
@@ -7,7 +7,7 @@
//
//===----------------------------------------------------------------------===//
//
-// This file demotes all registers to memory references. It is intented to be
+// This file demotes all registers to memory references. It is intended to be
// the inverse of PromoteMemoryToRegister. By converting to loads, the only
// values live across basic blocks are allocas and loads before phi nodes.
// It is intended that this should make CFG hacking much easier.
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 3c6793f3ad05783e0ecd515acacfacd0b1e6200f..b08f8e21a04ec1919cd5903f1e14d5fe26957089 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -706,7 +706,7 @@ bool llvm::EliminateDuplicatePHINodes(BasicBlock *BB) {
CollisionMap[PN] = Old;
break;
}
- // Procede to the next PHI in the list.
+ // Proceed to the next PHI in the list.
OtherPN = I->second;
}
}
diff --git a/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp b/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
index 7672726cb33da9245a0a9054df82cdade3708838..67e17f4ca8e892cdb094cf0bc05b2afa0f3fe067 100644
--- a/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
+++ b/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
@@ -131,7 +131,7 @@ static void ConnectProlog(Loop *L, Value *TripCount, unsigned Count,
/// There are two value maps that are defined and used. VMap is
/// for the values in the current loop instance. LVMap contains
/// the values from the last loop instance. We need the LVMap values
-/// to update the inital values for the current loop instance.
+/// to update the initial values for the current loop instance.
///
static void CloneLoopBlocks(Loop *L,
bool FirstCopy,
diff --git a/llvm/lib/VMCore/Verifier.cpp b/llvm/lib/VMCore/Verifier.cpp
index d9a535c9d8629be36499492b7b460fb73f9a2ab1..477b81dc67f5e002216caa39f2a28229c885833e 100644
--- a/llvm/lib/VMCore/Verifier.cpp
+++ b/llvm/lib/VMCore/Verifier.cpp
@@ -1723,7 +1723,7 @@ bool Verifier::VerifyIntrinsicType(Type *Ty,
}
case IITDescriptor::Argument:
- // Two cases here - If this is the second occurrance of an argument, verify
+ // Two cases here - If this is the second occurrence of an argument, verify
// that the later instance matches the previous instance.
if (D.getArgumentNumber() < ArgTys.size())
return Ty != ArgTys[D.getArgumentNumber()];
diff --git a/llvm/unittests/ADT/HashingTest.cpp b/llvm/unittests/ADT/HashingTest.cpp
index b148f144513c2d967338146b11ed9018fec9be59..1b3d0617a5e3de55a1a524ed390ee6d59699e4cb 100644
--- a/llvm/unittests/ADT/HashingTest.cpp
+++ b/llvm/unittests/ADT/HashingTest.cpp
@@ -345,7 +345,7 @@ TEST(HashingTest, HashCombineBasicTest) {
EXPECT_EQ(hash_combine_range(arr1, arr1 + 6),
hash_combine(i1, i2, i3, i4, i5, i6));
- // Hashing a sequence of heterogenous types which *happen* to all produce the
+ // Hashing a sequence of heterogeneous types which *happen* to all produce the
// same data for hashing produces the same as a range-based hash of the
// fundamental values.
const size_t s1 = 1024, s2 = 8888, s3 = 9000000;
diff --git a/llvm/unittests/VMCore/PassManagerTest.cpp b/llvm/unittests/VMCore/PassManagerTest.cpp
index af845b0ca4215812f16548b22853f5ded73518a7..60d33c19c337e8ba3b2cbd383b2932f5f086954b 100644
--- a/llvm/unittests/VMCore/PassManagerTest.cpp
+++ b/llvm/unittests/VMCore/PassManagerTest.cpp
@@ -324,7 +324,7 @@ namespace llvm {
Passes.run(M);
// Some passes must be rerun because a pass that modified the
- // module/function was run inbetween
+ // module/function was run in between
EXPECT_EQ(2, mNDM->run);
EXPECT_EQ(1, mNDNM->run);
EXPECT_EQ(1, mNDM2->run);
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 887f01bdfa9f76ce06e18265135571cb3632e783..81bf9edad66a17b438f84e38c8fbc12c6ba9e171 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -110,7 +110,7 @@ void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
if (CoveredBySubRegs && !ExplicitSubRegs.empty())
ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
- // Add ad hoc alias links. This is a symmetric relationship betwen two
+ // Add ad hoc alias links. This is a symmetric relationship between two
// registers, so build a symmetric graph by adding links in both ends.
std::vector Aliases = TheDef->getValueAsListOfDefs("Aliases");
for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
@@ -312,7 +312,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
// dsub_2 -> ssub_0
//
// We pick the latter composition because another register may have [dsub_0,
- // dsub_1, dsub_2] subregs without neccessarily having a qsub_1 subreg. The
+ // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
// dsub_2 -> ssub_0 composition can be shared.
while (!Indices.empty() && !Orphans.empty()) {
CodeGenSubRegIndex *Idx = Indices.pop_back_val();
@@ -919,7 +919,7 @@ void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
RC.SubClasses |= SubRC->SubClasses;
}
- // Sweep up missed clique members. They will be immediately preceeding RC.
+ // Sweep up missed clique members. They will be immediately preceding RC.
for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
RC.SubClasses.set(s - 1);
}
diff --git a/llvm/utils/llvm-build/llvmbuild/main.py b/llvm/utils/llvm-build/llvmbuild/main.py
index baecc6d899651704693af85f05d12bc83c33a77f..27d23d0855d17e83d674515e53de2137ae131a44 100644
--- a/llvm/utils/llvm-build/llvmbuild/main.py
+++ b/llvm/utils/llvm-build/llvmbuild/main.py
@@ -55,7 +55,7 @@ def make_install_dir(path):
Create the given directory path for installation, including any parents.
"""
- # os.makedirs considers it an error to be called with an existant path.
+ # os.makedirs considers it an error to be called with an existent path.
if not os.path.exists(path):
os.makedirs(path)