From c0b6cb1e47fca851e4158729b1e4c81abd26028e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 28 Dec 2017 19:46:06 +0000 Subject: [PATCH] [X86] Use ISD::CONCAT_VECTORS when splitting 256-bit loads in combineLoad. llvm-svn: 321537 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 08cf57b4209a..fc18c24048e5 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -34057,9 +34057,7 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG, Load1.getValue(1), Load2.getValue(1)); - SDValue NewVec = DAG.getUNDEF(RegVT); - NewVec = insert128BitVector(NewVec, Load1, 0, DAG, dl); - NewVec = insert128BitVector(NewVec, Load2, NumElems / 2, DAG, dl); + SDValue NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Load1, Load2); return DCI.CombineTo(N, NewVec, TF, true); } -- GitLab