[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
For strided accesses the loop vectorizer seems to prefer creating a vector induction variable with a start value of the form <i32 0, i32 1, i32 2, ...>. This value will be incremented each loop iteration by a splat constant equal to the length of the vector. Within the loop, arithmetic using splat values will be done on this vector induction variable to produce indices for a vector GEP. This pass attempts to dig through the arithmetic back to the phi to create a new scalar induction variable and a stride. We push all of the arithmetic out of the loop by folding it into the start, step, and stride values. Then we create a scalar GEP to use as the base pointer for a strided load or store using the computed stride. Loop strength reduce will run after this pass and can do some cleanups to the scalar GEP and induction variable. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D107790
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- llvm/include/llvm/IR/IntrinsicsRISCV.td 11 additions, 0 deletionsllvm/include/llvm/IR/IntrinsicsRISCV.td
- llvm/lib/Target/RISCV/CMakeLists.txt 2 additions, 0 deletionsllvm/lib/Target/RISCV/CMakeLists.txt
- llvm/lib/Target/RISCV/RISCV.h 3 additions, 0 deletionsllvm/lib/Target/RISCV/RISCV.h
- llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp 475 additions, 0 deletionsllvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
- llvm/lib/Target/RISCV/RISCVISelLowering.cpp 139 additions, 0 deletionsllvm/lib/Target/RISCV/RISCVISelLowering.cpp
- llvm/lib/Target/RISCV/RISCVISelLowering.h 3 additions, 0 deletionsllvm/lib/Target/RISCV/RISCVISelLowering.h
- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp 4 additions, 0 deletionsllvm/lib/Target/RISCV/RISCVTargetMachine.cpp
- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h 3 additions, 21 deletionsllvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
- llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-negative.ll 155 additions, 0 deletions...Gen/RISCV/rvv/fixed-vector-strided-load-store-negative.ll
- llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll 831 additions, 0 deletions...test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
- llvm/tools/opt/opt.cpp 4 additions, 3 deletionsllvm/tools/opt/opt.cpp
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