llvm-svn: 36260

llvm-svn: 36259

llvm-svn: 36258

llvm-svn: 36257

llvm-svn: 36256

llvm-svn: 36255

llvm-svn: 36254

llvm-svn: 36252

llvm-svn: 36251

llvm-svn: 36250

llvm-svn: 36249

llvm-svn: 36248

llvm-svn: 36247

llvm-svn: 36246

llvm-svn: 36245

single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244

llvm-svn: 36243

llvm-svn: 36242

llvm-svn: 36241

llvm-svn: 36240

llvm-svn: 36239

llvm-svn: 36238

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070416/047971.html

llvm-svn: 36236

llvm-svn: 36235

llvm-svn: 36234

llvm-svn: 36233

Be more careful when inserting reused instructions.  This fixes CodeGen/Generic/2007-04-17-lsr-crash.ll

llvm-svn: 36231

llvm-svn: 36230

llvm-svn: 36227

wrong operand.

llvm-svn: 36223

llvm-svn: 36222

This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll

llvm-svn: 36221

llvm-svn: 36220

llvm-svn: 36219

long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.

llvm-svn: 36218

llvm-svn: 36217

llvm-svn: 36216

llvm-svn: 36215

llvm-svn: 36214

llvm-svn: 36213