Turn llvm::SpecialCaseList into a simple class that parses text files in
a specified format and knows nothing about LLVM IR. Move this class into
LLVMSupport library. Implement two users of this class:
  * DFSanABIList in DFSan instrumentation pass.
  * SanitizerBlacklist in Clang CodeGen library.
The latter will be modified to use actual source-level information from frontend
(source file names) instead of unstable LLVM IR things (LLVM Module identifier).

Remove dependency edge from ClangCodeGen/ClangDriver to LLVMTransformUtils.

No functionality change.

llvm-svn: 212643

llvm-svn: 212642

It is a good idea, it's slightly clearer and simpler. Unfortunately
the headline news is: we save one line!

llvm-svn: 212641

Do this if the truncate is free and the select is legal.

llvm-svn: 212640

See http://llvm.org/bugs/show_bug.cgi?id=20260 for more details.

llvm-svn: 212639

Storing will generally be immediately preceded by rounding from an f32
or f64, so make sure to match those patterns directly to convert into the
FPR16 register class directly rather than going through the integer GPRs.

This also eliminates an extra step in the convert-from-f64 path
which was first converting to f32 and then to f16 from there.

rdar://17594379

llvm-svn: 212638

llvm-svn: 212637

llvm-svn: 212636

llvm-svn: 212635

This lets us experiment with 512-bit vectorization without passing
force-vector-width manually.

The code generated for a simple integer memset loop is properly vectorized.
Disassembly is still broken for it though :(.

llvm-svn: 212634

This is a follow up to r212492. There should be no functional difference, but
this patch makes it clear that SrcVT must be an i1/i8/16/i32 and DestVT must be
an i8/i16/i32/i64.

rdar://17516686

llvm-svn: 212633

llvm-svn: 212632

gcc supports this behavior and it is pervasively used inside the Linux
kernel.

Note that both gcc and clang will reject code that attempts to do this
in a C++ language mode.

This fixes PR17998.

llvm-svn: 212631

The current strategy for host allocation is to choose a random
address and attempt to allocate there, eventually failing if the
allocation cannot be satisfied.

The C standard only guarantees that RAND_MAX >= 32767, so for
platforms that use a very small RAND_MAX allocations will fail
with very high probability.  On such platforms (Windows is one),
you can reproduce this trivially by running lldb, typing "expr (3)"
and then hitting enter you see a failure.  Failures generally
happen with a frequency of about 1 failure every 5 evaluations.

There is no good reason that allocations need to look like "real"
pointers, so this patch changes the allocation scheme to simply
jump straight to the end and grab a free chunk of memory.

Reviewed By: Sean Callanan

Differential Revision: http://reviews.llvm.org/D4300

llvm-svn: 212630

In PR20059 ( http://llvm.org/pr20059 ), instcombine eliminates shuffles that are necessary before performing an operation that can trap (srem).

This patch calls isSafeToSpeculativelyExecute() and bails out of the optimization in SimplifyVectorOp() if needed.

Differential Revision: http://reviews.llvm.org/D4424

llvm-svn: 212629

The getopt library has a structure called option (lowercase).  We
have a structure called Option (uppercase).  previously the two
structures had exactly the same definitions, and we were doing a
C-style cast of an Option* to an option*.  C-style casts don't
bother to warn you when you cast to unrelated types, but in the
original OptionValidator patch I modified the definition of Option.

This patch fixes the errors by building an array of option
structures and filling it out the correct way before passing it to
the getopt library.

This also fixes one other source of test failures: an uninitialized
read that occurs due to not initializing a field of the
OptionDefinition.

Reviewed By: Todd Fiala

Differential Revision: http://reviews.llvm.org/D4425

llvm-svn: 212628

This reverts commit ec7c94f8e6860968d384b578e5564a9c55c80b4a and
re-enables OptionValidators.

llvm-svn: 212627

Summary: This is a pre-requisite for supporting the mips-img-linux-gnu triple in clang.

Differential Revision: http://reviews.llvm.org/D4435

llvm-svn: 212626

Differential Revision: http://reviews.llvm.org/D4434

llvm-svn: 212625

llvm-svn: 212624

llvm-svn: 212622

llvm-svn: 212621

The clang -cc1as options are nearly a strict subset of -cc1. Instead of
duplicating the definitions and documentation, let's go ahead and share the
definitions in a similar way the current handling of combined driver and
frontend flags, eliminating some of the vestigial legacy surrounding the
assembler subcommand.

llvm-svn: 212620

Summary:
This removes the need to pass -mnan=2008 explicitly to be able to compile
the test-suite for MIPS32r6/MIPS64r6.

Differential Revision: http://reviews.llvm.org/D4433

llvm-svn: 212619

Summary:
While debugging another issue, I noticed that Mips currently specifies that the
count leading zero builtins are undefined when the input is zero. The
architecture specifications say that the clz and dclz instructions write 32 or
64 respectively when given zero.

This doesn't fix any bugs that I'm aware of but it may improve optimisation in
some cases.

Differential Revision: http://reviews.llvm.org/D4431

llvm-svn: 212618

Before:
  (aaaaaaaaaa->*
   bbbbbbb)(aaaaaaaaaaaaaaaaaaaaaaaaaaa(aaaaaaaaaaaaaaaaaaaaaaaaaaa));

After:
  (aaaaaaaaaa->*bbbbbbb)(
      aaaaaaaaaaaaaaaaaaaaaaaaaaa(aaaaaaaaaaaaaaaaaaaaaaaaaaa));

llvm-svn: 212617

Some of those loops were pretty monstrous.

llvm-svn: 212616

I want to use it in lld, but while I'm here I'll update LLVM uses.

llvm-svn: 212615

not widening the input type to the node sufficiently to let the ext take
place in a register.

This would in turn result in a mysterious bitcast assertion failure
downstream. First change here is to add back the helpful assert I had in
an earlier version of the code to catch this immediately.

Next change is to add support to the type legalization to detect when we
have widened the operand either too little or too much (for whatever
reason) and find a size-matched legal vector type to convert it to
first. This can also fail so we get a new fallback path, but that seems
OK.

With this, we no longer crash on vec_cast2.ll when using widening. I've
also added the CHECK lines for the zero-extend cases here. We still need
to support sign-extend and trunc (or something) to get plausible code
for the other two thirds of this test which is one of the regression
tests that showed the most scalarization when widening was
force-enabled. Slowly closing in on widening being a viable legalization
strategy without it resorting to scalarization at every turn. =]

llvm-svn: 212614

llvm-svn: 212613

fix the release builds with Werror.

llvm-svn: 212612

Turns out my trick of using the same masks for SSE4.1 and AVX2 didn't work out
as we have to blend two vectors. While there remove unecessary cross-lane moves
from the shuffles so the backend can lower it to palignr instead of vperm.

Fixes PR20118, a miscompilation of vector sdiv by constant on AVX2.

llvm-svn: 212611

vector types to be legal and a ZERO_EXTEND node is encountered.

When we use widening to legalize vector types, extend nodes are a real
challenge. Either the input or output is likely to be legal, but in many
cases not both. As a consequence, we don't really have any way to
represent this situation and the prior code in the widening legalization
framework would just scalarize the extend operation completely.

This patch introduces a new DAG node to represent doing a zero extend of
a vector "in register". The core of the idea is to allow legal but
different vector types in the input and output. The output vector must
have fewer lanes but wider elements. The operation is defined to zero
extend the low elements of the input to the size of the output elements,
and drop all of the high elements which don't have a corresponding lane
in the output vector.

It also includes generic expansion of this node in terms of blending
a zero vector into the high elements of the vector and bitcasting
across. This in turn yields extremely nice code for x86 SSE2 when we use
the new widening legalization logic in conjunction with the new shuffle
lowering logic.

There is still more to do here. We need to support sign extension, any
extension, and potentially int-to-float conversions. My current plan is
to continue using similar synthetic nodes to model each of these
transitions with generic lowering code for each one.

However, with this patch LLVM already reaches performance parity with
GCC for the core C loops of the x264 code (assuming you disable the
hand-written assembly versions) when compiling for SSE2 and SSE3
architectures and enabling the new widening and lowering logic for
vectors.

Differential Revision: http://reviews.llvm.org/D4405

llvm-svn: 212610

llvm-svn: 212609

Summary: This bug caused SingleSource/Regression/C/uint64_to_float and SingleSource/UnitTests/2002-05-02-CastTest3 to fail (among others).

Differential Revision: http://reviews.llvm.org/D4388

llvm-svn: 212608

Summary:
It seems we accidentally read the wrong column of the table MIPS64r6 spec
and used the names for c.cond.fmt instead of cmp.cond.fmt.

Differential Revision: http://reviews.llvm.org/D4387

llvm-svn: 212607

This should restore GCC hosts (which happen to put the bad stuff into
the pointer) and MSan, etc.

llvm-svn: 212606

[mips][mips64r6] Use JALR for indirect branches instead of JR (which is not available on MIPS32r6/MIPS64r6)

Summary:
This completes the change to use JALR instead of JR on MIPS32r6/MIPS64r6.

Reviewers: jkolek, vmedic, zoran.jovanovic, dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4269

llvm-svn: 212605

Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.

Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise

On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.

Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.

The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').

Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().

Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4268

llvm-svn: 212604

Summary:
This patch re-uses the implementation of 'llvm-mc -show-inst' and makes it
available to llc as 'llc -asm-show-inst'.

This is necessary to test parts of MIPS32r6/MIPS64r6 without resorting to
'llc -filetype=obj' tests. For example, on MIPS32r2 and earlier we use the
'jr $rs' instruction for indirect branches and returns. On MIPS32r6, we no
longer have 'jr $rs' and use 'jalr $zero, $rs' instead. The catch is that,
on MIPS32r6, 'jr $rs' is an alias for 'jalr $zero, $rs' and is the preferred
way of writing this instruction. As a result, all MIPS ISA's emit 'jr $rs' in
their assembly output and the assembler encodes this to different opcodes
according to the ISA.

Using this option, we can check that the MCInst really is a JR or a JALR by
matching the emitted comment. This removes the need for a 'llc -filetype=obj'
test.

Reviewers: rafael, dsanders

Reviewed By: dsanders

Subscribers: zoran.jovanovic, llvm-commits

Differential Revision: http://reviews.llvm.org/D4267

llvm-svn: 212603