Makefile.rules

#===-- Makefile.rules - Common make rules for LLVM ---------*- Makefile -*--===#
#
#                     The LLVM Compiler Infrastructure
#
# This file is distributed under the University of Illinois Open Source
# License. See LICENSE.TXT for details.
#
#===------------------------------------------------------------------------===#
#
# This file is included by all of the LLVM makefiles.  For details on how to use
# it properly, please see the document MakefileGuide.html in the docs directory.
#
#===-----------------------------------------------------------------------====#

################################################################################
# TARGETS: Define standard targets that can be invoked
################################################################################

#--------------------------------------------------------------------
# Define the various target sets
#--------------------------------------------------------------------
RecursiveTargets := all clean clean-all install uninstall install-bytecode \
                    unitcheck
LocalTargets     := all-local clean-local clean-all-local check-local \
                    install-local printvars uninstall-local \
		    install-bytecode-local
TopLevelTargets  := check dist dist-check dist-clean dist-gzip dist-bzip2 \
                    dist-zip unittests
UserTargets      := $(RecursiveTargets) $(LocalTargets) $(TopLevelTargets)
InternalTargets  := preconditions distdir dist-hook

################################################################################
# INITIALIZATION: Basic things the makefile needs
################################################################################

#--------------------------------------------------------------------
# Set the VPATH so that we can find source files.
#--------------------------------------------------------------------
VPATH=$(PROJ_SRC_DIR)

#--------------------------------------------------------------------
# Reset the list of suffixes we know how to build.
#--------------------------------------------------------------------
.SUFFIXES:
.SUFFIXES: .c .cpp .cc .h .hpp .o .a .bc .td .ps .dot .ll .m .mm
.SUFFIXES: $(SHLIBEXT) $(SUFFIXES)

#--------------------------------------------------------------------
# Mark all of these targets as phony to avoid implicit rule search
#--------------------------------------------------------------------
.PHONY: $(UserTargets) $(InternalTargets)

#--------------------------------------------------------------------
# Make sure all the user-target rules are double colon rules and
# they are defined first.
#--------------------------------------------------------------------

$(UserTargets)::

################################################################################
# PRECONDITIONS: that which must be built/checked first
################################################################################

SrcMakefiles       := $(filter %Makefile %Makefile.tests,\
                      $(wildcard $(PROJ_SRC_DIR)/Makefile*))
ObjMakefiles       := $(subst $(PROJ_SRC_DIR),$(PROJ_OBJ_DIR),$(SrcMakefiles))
ConfigureScript    := $(PROJ_SRC_ROOT)/configure
ConfigStatusScript := $(PROJ_OBJ_ROOT)/config.status
MakefileConfigIn   := $(strip $(wildcard $(PROJ_SRC_ROOT)/Makefile.config.in))
MakefileCommonIn   := $(strip $(wildcard $(PROJ_SRC_ROOT)/Makefile.common.in))
MakefileConfig     := $(PROJ_OBJ_ROOT)/Makefile.config
MakefileCommon     := $(PROJ_OBJ_ROOT)/Makefile.common
PreConditions      := $(ConfigStatusScript) $(ObjMakefiles)
ifneq ($(MakefileCommonIn),)
PreConditions      += $(MakefileCommon)
endif

ifneq ($(MakefileConfigIn),)
PreConditions      += $(MakefileConfig)
endif

preconditions: $(PreConditions)

#------------------------------------------------------------------------
# Make sure the BUILT_SOURCES are built first
#------------------------------------------------------------------------
$(filter-out clean clean-local,$(UserTargets)):: $(BUILT_SOURCES)

clean-all-local::
ifneq ($(strip $(BUILT_SOURCES)),)
	-$(Verb) $(RM) -f $(BUILT_SOURCES)
endif

ifneq ($(PROJ_OBJ_ROOT),$(PROJ_SRC_ROOT))
spotless:
	$(Verb) if test -x config.status ; then \
	  $(EchoCmd) Wiping out $(PROJ_OBJ_ROOT) ; \
	  $(MKDIR) .spotless.save ; \
	  $(MV) config.status .spotless.save ; \
	  $(MV) mklib  .spotless.save ; \
	  $(MV) projects  .spotless.save ; \
	  $(RM) -rf * ; \
	  $(MV) .spotless.save/config.status . ; \
	  $(MV) .spotless.save/mklib . ; \
	  $(MV) .spotless.save/projects . ; \
	  $(RM) -rf .spotless.save ; \
	  $(EchoCmd) Rebuilding configuration of $(PROJ_OBJ_ROOT) ; \
	  $(ConfigStatusScript) --recheck $(ConfigureScriptFLAGS) && \
	  $(ConfigStatusScript) ; \
	else \
	  $(EchoCmd) "make spotless" can only be run from $(PROJ_OBJ_ROOT); \
	fi
else
spotless:
	$(EchoCmd) "spotless target not supported for objdir == srcdir"
endif

$(BUILT_SOURCES) : $(ObjMakefiles)

#------------------------------------------------------------------------
# Make sure we're not using a stale configuration
#------------------------------------------------------------------------
reconfigure:
	$(Echo) Reconfiguring $(PROJ_OBJ_ROOT)
	$(Verb) cd $(PROJ_OBJ_ROOT) && \
	  if test -w $(PROJ_OBJ_ROOT)/config.cache ; then \
	    $(RM) $(PROJ_OBJ_ROOT)/config.cache ; \
	  fi ; \
	  $(ConfigStatusScript) --recheck $(ConfigureScriptFLAGS) && \
	  $(ConfigStatusScript)

.PRECIOUS: $(ConfigStatusScript)
$(ConfigStatusScript): $(ConfigureScript)
	$(Echo) Reconfiguring with $<
	$(Verb) cd $(PROJ_OBJ_ROOT) && \
	  if test -w $(PROJ_OBJ_ROOT)/config.cache ; then \
	    $(RM) $(PROJ_OBJ_ROOT)/config.cache ; \
	  fi ; \
	  $(ConfigStatusScript) --recheck $(ConfigureScriptFLAGS) && \
	  $(ConfigStatusScript)

#------------------------------------------------------------------------
# Make sure the configuration makefile is up to date
#------------------------------------------------------------------------
ifneq ($(MakefileConfigIn),)
$(MakefileConfig): $(MakefileConfigIn) $(ConfigStatusScript)
	$(Echo) Regenerating $@
	$(Verb) cd $(PROJ_OBJ_ROOT) ; $(ConfigStatusScript) Makefile.config
endif

ifneq ($(MakefileCommonIn),)
$(MakefileCommon): $(MakefileCommonIn) $(ConfigStatusScript)
	$(Echo) Regenerating $@
	$(Verb) cd $(PROJ_OBJ_ROOT) ; $(ConfigStatusScript) Makefile.common
endif

#------------------------------------------------------------------------
# If the Makefile in the source tree has been updated, copy it over into the
# build tree. But, only do this if the source and object makefiles differ
#------------------------------------------------------------------------
ifndef PROJ_MAKEFILE
PROJ_MAKEFILE := $(PROJ_SRC_DIR)/Makefile
endif

ifneq ($(PROJ_OBJ_DIR),$(PROJ_SRC_DIR))

Makefile: $(PROJ_MAKEFILE) $(ExtraMakefiles)
	$(Echo) "Updating Makefile"
	$(Verb) $(MKDIR) $(@D)
	$(Verb) $(CP) -f $< $@

# Copy the Makefile.* files unless we're in the root directory which avoids
# the copying of Makefile.config.in or other things that should be explicitly
# taken care of.
$(PROJ_OBJ_DIR)/Makefile% : $(PROJ_MAKEFILE)%
	@case '$?' in \
          *Makefile.rules) ;; \
          *.in) ;; \
          *) $(EchoCmd) "Updating $(@F)" ; \
	     $(MKDIR) $(@D) ; \
	     $(CP) -f $< $@ ;; \
	esac

endif

#------------------------------------------------------------------------
# Set up the basic dependencies
#------------------------------------------------------------------------
$(UserTargets):: $(PreConditions)

all:: all-local
clean:: clean-local
clean-all:: clean-local clean-all-local
install:: install-local
uninstall:: uninstall-local
install-local:: all-local
install-bytecode:: install-bytecode-local

###############################################################################
# LLVMC: Provide rules for compiling llvmc-based driver