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//===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the "Instituto Nokia de Tecnologia" and
// is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the ARM instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
let Namespace = "ARM";
dag OperandList = ops;
let AsmString = asmstr;
let Pattern = pattern;
}
def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
def SDT_ARMRetFlag : SDTypeProfile<0, 0, []>;
def retflag : SDNode<"ARMISD::RET_FLAG", SDT_ARMRetFlag,
[SDNPHasChain, SDNPOptInFlag]>;
def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
[(callseq_end imm:$amt)]>;
def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>;
def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldr $dst, [$addr]",
[(set IntRegs:$dst, (load IntRegs:$addr))]>;
def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
"str $src, [$addr]",
[(store IntRegs:$src, IntRegs:$addr)]>;
def mov : InstARM<(ops IntRegs:$dst, IntRegs:$b),
"mov $dst, $b", []>;