diff --git a/llvm/lib/Target/AArch64/AArch64InstrNEON.td b/llvm/lib/Target/AArch64/AArch64InstrNEON.td
index cf105c20dc983100adc032eb43c4a1ea13cc05d4..f1cb122eefe4cac694378cc7880a376ba67058fe 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrNEON.td
@@ -473,10 +473,6 @@ multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
   def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
-  def : Pat<(v2f64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
-            (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
-  def : Pat<(v4f32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
-            (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 
   // Allow to match BSL instruction pattern with non-constant operand
   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
diff --git a/llvm/test/CodeGen/AArch64/neon-bsl.ll b/llvm/test/CodeGen/AArch64/neon-bsl.ll
index b0a148cd9e576574ae0135cdd2b924cf04c99a58..6bd923dc2ccaeca5cc737360c5e43358bdea7d1e 100644
--- a/llvm/test/CodeGen/AArch64/neon-bsl.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bsl.ll
@@ -220,14 +220,3 @@ entry:
   ret <2 x double> %vbsl3.i
 }
 
-define <2 x double> @bsl2xf64(<2 x i1> %v1, <2 x double> %v2, <2 x double> %v3) {
-;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-  %1 = select <2 x i1> %v1, <2 x double> %v2, <2 x double> %v3
-  ret <2 x double> %1
-}
-
-define <4 x float> @bsl4xf32(<4 x i1> %v1, <4 x float> %v2, <4 x float> %v3) {
-;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-  %1 = select <4 x i1> %v1, <4 x float> %v2, <4 x float> %v3
-  ret <4 x float> %1
-}