From 2bfa8ed045d3aad76c3a694f273a4a5beb47d94f Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Thu, 21 Oct 2010 20:49:13 +0000 Subject: [PATCH] Move the encoding logic for Q registers into getMachineOpValue(). llvm-svn: 117060 --- llvm/lib/Target/ARM/ARMBaseInfo.h | 48 ++++++++++++------------ llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 13 ++++++- 2 files changed, 36 insertions(+), 25 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMBaseInfo.h b/llvm/lib/Target/ARM/ARMBaseInfo.h index 17a65be458d8..2da7be25a139 100644 --- a/llvm/lib/Target/ARM/ARMBaseInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInfo.h @@ -132,37 +132,37 @@ inline static unsigned getARMRegisterNumbering(unsigned Reg) { default: llvm_unreachable("Unknown ARM register!"); case R0: case S0: case D0: case Q0: return 0; - case R1: case S1: case D1: return 1; - case R2: case S2: case D2: case Q1: return 2; - case R3: case S3: case D3: return 3; - case R4: case S4: case D4: case Q2: return 4; - case R5: case S5: case D5: return 5; - case R6: case S6: case D6: case Q3: return 6; - case R7: case S7: case D7: return 7; - case R8: case S8: case D8: case Q4: return 8; - case R9: case S9: case D9: return 9; - case R10: case S10: case D10: case Q5: return 10; - case R11: case S11: case D11: return 11; - case R12: case S12: case D12: case Q6: return 12; - case SP: case S13: case D13: return 13; - case LR: case S14: case D14: case Q7: return 14; - case PC: case S15: case D15: return 15; - - case S16: case D16: case Q8: return 16; + case R1: case S1: case D1: case Q1: return 1; + case R2: case S2: case D2: case Q2: return 2; + case R3: case S3: case D3: case Q3: return 3; + case R4: case S4: case D4: case Q4: return 4; + case R5: case S5: case D5: case Q5: return 5; + case R6: case S6: case D6: case Q6: return 6; + case R7: case S7: case D7: case Q7: return 7; + case R8: case S8: case D8: case Q8: return 8; + case R9: case S9: case D9: case Q9: return 9; + case R10: case S10: case D10: case Q10: return 10; + case R11: case S11: case D11: case Q11: return 11; + case R12: case S12: case D12: case Q12: return 12; + case SP: case S13: case D13: case Q13: return 13; + case LR: case S14: case D14: case Q14: return 14; + case PC: case S15: case D15: case Q15: return 15; + + case S16: case D16: return 16; case S17: case D17: return 17; - case S18: case D18: case Q9: return 18; + case S18: case D18: return 18; case S19: case D19: return 19; - case S20: case D20: case Q10: return 20; + case S20: case D20: return 20; case S21: case D21: return 21; - case S22: case D22: case Q11: return 22; + case S22: case D22: return 22; case S23: case D23: return 23; - case S24: case D24: case Q12: return 24; + case S24: case D24: return 24; case S25: case D25: return 25; - case S26: case D26: case Q13: return 26; + case S26: case D26: return 26; case S27: case D27: return 27; - case S28: case D28: case Q14: return 28; + case S28: case D28: return 28; case S29: case D29: return 29; - case S30: case D30: case Q15: return 30; + case S30: case D30: return 30; case S31: case D31: return 31; } } diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index 6132d6df7f31..ea7789c073c2 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -143,7 +143,18 @@ EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind, unsigned ARMMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO) const { if (MO.isReg()) { - return getARMRegisterNumbering(MO.getReg()); + unsigned regno = getARMRegisterNumbering(MO.getReg()); + + // Q registers are encodes as 2x their register number. + switch (MO.getReg()) { + case ARM::Q0: case ARM::Q1: case ARM::Q2: case ARM::Q3: + case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: + case ARM::Q8: case ARM::Q9: case ARM::Q10: case ARM::Q11: + case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15: + return 2 * regno; + default: + return regno; + } } else if (MO.isImm()) { return static_cast(MO.getImm()); } else if (MO.isFPImm()) { -- GitLab