From 34946dfd79501077b0837aec8f23aed3dd0e63e1 Mon Sep 17 00:00:00 2001
From: Kai Nacke <kai@redstar.de>
Date: Wed, 8 Jan 2020 14:26:12 -0500
Subject: [PATCH] [SystemZ] Add implementation for the intrinsic
 llvm.read_register

This change implements the llvm intrinsic llvm.read_register for
the SystemZ platform which returns the value of the specified
register
(http://llvm.org/docs/LangRef.html#llvm-read-register-and-llvm-write-register-intrinsics).
This implementation returns the value of the stack register, and
can be extended to return the value of other registers. The
implementation for this intrinsic exists on various other platforms
including Power, x86, ARM, etc. but missing on SystemZ.

Reviewers: uweigand

Differential Revision: https://reviews.llvm.org/D73378
---
 llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 13 +++++++++++++
 llvm/lib/Target/SystemZ/SystemZISelLowering.h   |  3 +++
 llvm/test/CodeGen/SystemZ/stackpointer.ll       | 15 +++++++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 llvm/test/CodeGen/SystemZ/stackpointer.ll

diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 19a1b790e473..362bf19963d9 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1193,6 +1193,19 @@ SystemZTargetLowering::getRegForInlineAsmConstraint(
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
 
+// FIXME? Maybe this could be a TableGen attribute on some registers and
+// this table could be generated automatically from RegInfo.
+Register SystemZTargetLowering::getRegisterByName(const char *RegName, LLT VT,
+                                                  const MachineFunction &MF) const {
+
+  Register Reg = StringSwitch<Register>(RegName)
+                   .Case("r15", SystemZ::R15D)
+                   .Default(0);
+  if (Reg)
+    return Reg;
+  report_fatal_error("Invalid register name global variable");
+}
+
 void SystemZTargetLowering::
 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                              std::vector<SDValue> &Ops,
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 5371bc17f872..5fd65f51b7b0 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -473,6 +473,9 @@ public:
     return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
   }
 
+  Register getRegisterByName(const char *RegName, LLT VT,
+                             const MachineFunction &MF) const override;
+
   /// If a physical register, this returns the register that receives the
   /// exception address on entry to an EH pad.
   unsigned
diff --git a/llvm/test/CodeGen/SystemZ/stackpointer.ll b/llvm/test/CodeGen/SystemZ/stackpointer.ll
new file mode 100644
index 000000000000..94d23b90e1da
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/stackpointer.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+define i8* @get_stack() nounwind {
+entry:
+; CHECK-LABEL: get_stack:
+; CHECK: lgr %r2, %r15
+; CHECK-NEXT: br %r14
+        %0 = call i64 @llvm.read_register.i64(metadata !0)
+        %1 = inttoptr i64 %0 to i8*
+  ret i8* %1
+}
+
+declare i64 @llvm.read_register.i64(metadata) nounwind
+
+!0 = !{!"r15"}
-- 
GitLab