From 3d1d4a3d125cb96cc2227d86ac85a09581da9606 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Mon, 10 Oct 2005 16:51:40 +0000
Subject: [PATCH] Add ISD::ADD to MaskedValueIsZero

llvm-svn: 23685
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 60bb6c6795d1..f15ce5784c6c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -215,6 +215,14 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
       return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
     }
     return false;
+  case ISD::ADD:
+    // (add X, Y) & C == 0 iff (X&C)&(Y&C) == 0 and all bits are low bits.
+    if ((Mask&(Mask+1)) == 0) {  // All low bits
+      if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
+          MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
+        return true;
+    }
+    break;
   case ISD::SUB:
     if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
       // We know that the top bits of C-X are clear if X contains less bits
-- 
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