From 3db4952357b70469930d1463a99a17894074784c Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 22 Dec 2009 21:48:20 +0000 Subject: [PATCH] Allow explicit %reg0 operands beyond what the .td file describes. ARM uses these to indicate predicates. llvm-svn: 91922 --- llvm/lib/CodeGen/MachineVerifier.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 917d0535b2b8..959269f85f2f 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -553,7 +553,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { report("Explicit operand marked as implicit", MO, MONum); } } else { - if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic()) + // ARM adds %reg0 operands to indicate predicates. We'll allow that. + if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg()) report("Extra explicit operand on non-variadic instruction", MO, MONum); } -- GitLab