From 62f65edc32a61164f119ecb433477071b621004e Mon Sep 17 00:00:00 2001
From: Dale Johannesen <dalej@apple.com>
Date: Thu, 11 Oct 2007 20:58:37 +0000
Subject: [PATCH] Add missing argument to PALIGNR

llvm-svn: 42874
---
 llvm/lib/Target/X86/X86InstrSSE.td | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index f2795fff743e..bbcc7530d592 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -2598,14 +2598,14 @@ defm PSIGND      : SS3I_binop_rm_int_32<0x09, "psignd",
 let isTwoAddress = 1 in {
   def PALIGNR64rr  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
                            (ins VR64:$src1, VR64:$src2, i16imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR64:$dst,
                              (int_x86_ssse3_palign_r
                               VR64:$src1, VR64:$src2,
                               imm:$src3))]>;
   def PALIGNR64rm  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
                            (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR64:$dst,
                              (int_x86_ssse3_palign_r
                               VR64:$src1,
@@ -2614,14 +2614,14 @@ let isTwoAddress = 1 in {
 
   def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
                            (ins VR128:$src1, VR128:$src2, i32imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR128:$dst,
                              (int_x86_ssse3_palign_r_128
                               VR128:$src1, VR128:$src2,
                               imm:$src3))]>, OpSize;
   def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
                            (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR128:$dst,
                              (int_x86_ssse3_palign_r_128
                               VR128:$src1,
-- 
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