diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index ffcf48bf98dbf94d916b7393ba0b29f120aa0b83..aec4a314f0744b3fb17dbc33e1392cc15f280c7e 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -48,16 +48,15 @@ class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
 class LLBaseMM<string opstr, RegisterOperand RO> :
   InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
-  let DecoderMethod = "DecodeMem";
+  let DecoderMethod = "DecodeMemMMImm12";
   let mayLoad = 1;
 }
 
 class SCBaseMM<string opstr, RegisterOperand RO> :
-  InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
+  InstSE<(outs), (ins RO:$rt, mem_mm_12:$addr),
          !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
-  let DecoderMethod = "DecodeMem";
+  let DecoderMethod = "DecodeMemMMImm12";
   let mayStore = 1;
-  let Constraints = "$rt = $dst";
 }
 
 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
diff --git a/llvm/test/MC/Disassembler/Mips/micromips.txt b/llvm/test/MC/Disassembler/Mips/micromips.txt
index 91d06162a189cfaf893f00890f0a29cb2d5055eb..1458ce2ed4b35d1992b06f608e64e6cbde3f46a9 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips.txt
@@ -288,3 +288,9 @@
 
 # CHECK: tnei $9, 17767
 0x41 0x89 0x45 0x67
+
+# CHECK: ll $2, 8($4)
+0x60 0x44 0x30 0x08
+
+# CHECK: sc $2, 8($4)
+0x60 0x44 0xb0 0x08
diff --git a/llvm/test/MC/Disassembler/Mips/micromips_le.txt b/llvm/test/MC/Disassembler/Mips/micromips_le.txt
index f32eb38c1496fff21f53dc5891c709174825c4f7..bdfe88eaffbf275b82587751c810c214152eafa5 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips_le.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips_le.txt
@@ -288,3 +288,9 @@
 
 # CHECK: tnei $9, 17767
 0x89 0x41 0x67 0x45
+
+# CHECK: ll $2, 8($4)
+0x44 0x60 0x08 0x30
+
+# CHECK: sc $2, 8($4)
+0x44 0x60 0x08 0xb0