diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
index 057104999d36d5aaca36bd79399f16f7b35a69a0..729ffb56ff3416be76ef7ba4649c423a1db40bdd 100644
--- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
@@ -816,9 +816,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     Tmp2 = SelectExpr(N.getOperand(1));
     Tmp3 = SelectExpr(N.getOperand(2));
     if (N.getOperand(0).getValueType() == MVT::f32)
-      BuildMI(BB, PPC::FSELS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+      Opc = N.getOperand(0).getValueType() == MVT::f32 ?
+        PPC::FSELSS : PPC::FSELSD;
     else
-      BuildMI(BB, PPC::FSELD, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+      Opc = N.getOperand(0).getValueType() == MVT::f64 ?
+        PPC::FSELDD : PPC::FSELDS;
+    BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
     return Result;
   case PPCISD::FCFID:
     Tmp1 = SelectExpr(N.getOperand(0));
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 4721d3e02a9f981a534f431f554c678439cccb2c..3a92d085b76cfb8f45b63e7d28927a6f9835e47a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -752,18 +752,21 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
     CodeGenMap[Op.getValue(1)] = Result.getValue(1);
     return SDOperand(Result.Val, Op.ResNo);
   }      
-  case PPCISD::FSEL:
-    if (N->getValueType(0) == MVT::f32)
-      CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32,
-                           Select(N->getOperand(0)),
-                           Select(N->getOperand(1)),
-                           Select(N->getOperand(2)));
-    else
-      CurDAG->SelectNodeTo(N, PPC::FSELD, MVT::f64,
-                           Select(N->getOperand(0)),
-                           Select(N->getOperand(1)),
-                           Select(N->getOperand(2)));
+  case PPCISD::FSEL: {
+    unsigned Opc;
+    if (N->getValueType(0) == MVT::f32) {
+      Opc = N->getOperand(0).getValueType() == MVT::f32 ?
+              PPC::FSELSS : PPC::FSELSD;
+    } else {
+      Opc = N->getOperand(0).getValueType() == MVT::f64 ?
+              PPC::FSELDD : PPC::FSELDS;
+    }
+    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0),
+                         Select(N->getOperand(0)),
+                         Select(N->getOperand(1)),
+                         Select(N->getOperand(2)));
     return SDOperand(N, 0);
+  }
   case PPCISD::FCFID:
     CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0),
                          Select(N->getOperand(0)));
diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
index bc4278c24b1606d5e87d13301c88b7b99df83cdc..c4bb8a627c46447ddc4980ac68f3f16ec526c1b3 100644
--- a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
@@ -791,15 +791,24 @@ def FNMSUBS : AForm_1<59, 30,
                     (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
                     "fnmsubs $FRT, $FRA, $FRC, $FRB",
                     []>;
-// FSEL is artificially split into 4 and 8-byte forms.
-def FSELD : AForm_1<63, 23,
-                    (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
-                    "fsel $FRT, $FRA, $FRC, $FRB",
-                    []>;
-def FSELS : AForm_1<63, 23,
-                    (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
-                    "fsel $FRT, $FRA, $FRC, $FRB",
-                    []>;
+// FSEL is artificially split into 4 and 8-byte forms for the comparison type
+// and 4/8 byte forms for the result and operand type..
+def FSELDD : AForm_1<63, 23,
+                     (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+                     "fsel $FRT, $FRA, $FRC, $FRB",
+                     []>;
+def FSELSS : AForm_1<63, 23,
+                     (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+                     "fsel $FRT, $FRA, $FRC, $FRB",
+                     []>;
+def FSELDS : AForm_1<63, 23,  // result Double, comparison Single
+                     (ops F8RC:$FRT, F4RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+                     "fsel $FRT, $FRA, $FRC, $FRB",
+                     []>;
+def FSELSD : AForm_1<63, 23,  // result Single, comparison Double
+                     (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+                     "fsel $FRT, $FRA, $FRC, $FRB",
+                     []>;
 def FADD  : AForm_2<63, 21,
                     (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
                     "fadd $FRT, $FRA, $FRB",