From b93850f370c83e253bc279a112b6ea4000ca21c6 Mon Sep 17 00:00:00 2001 From: Howard Hinnant Date: Tue, 5 Oct 2010 17:22:28 +0000 Subject: [PATCH] A compiler writer's guide to , minor update llvm-svn: 115633 --- libcxx/www/atomic_design.html | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/libcxx/www/atomic_design.html b/libcxx/www/atomic_design.html index fa2b2708a315..0750b733c1f5 100644 --- a/libcxx/www/atomic_design.html +++ b/libcxx/www/atomic_design.html @@ -377,11 +377,17 @@ for the detailed definitions of each of these orderings).

On some platforms, the compiler vendor can offer some or even all of the above intrinsics at one or more weaker levels of memory synchronization. This might -lead for example to not issuing an mfense instruction on the x86. If -the compiler does not offer any given operation, at any given memory ordering +lead for example to not issuing an mfense instruction on the x86. +

+ +

+If the compiler does not offer any given operation, at any given memory ordering level, the library will automatically attempt to call the next highest memory ordering operation. This continues up to seq_cst, and if that doesn't -exist, then the library takes over and does the job with a mutex. +exist, then the library takes over and does the job with a mutex. This +is a compile-time search & selection operation. At run time, the +application will only see the few inlined assembly instructions for the selected +intrinsic.

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