From c37a2f13c48019eccbf009e29f2347a1ab5fa23b Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Fri, 9 Sep 2005 18:17:41 +0000
Subject: [PATCH] Teach the code generator that rlwimi is commutable if the
 rotate amount is zero.  This lets the register allocator elide some copies in
 some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll

llvm-svn: 23292
---
 llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp  | 32 +++++++++++++++++++++
 llvm/lib/Target/PowerPC/PPC32InstrInfo.h    |  4 +++
 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td |  3 +-
 3 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp b/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
index 50ad423cf7cf..3ec78e3456bb 100644
--- a/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
@@ -76,3 +76,35 @@ bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
   }
   return false;
 }
+
+// commuteInstruction - We can commute rlwimi instructions, but only if the
+// rotate amt is zero.  We also have to munge the immediates a bit.
+MachineInstr *PPC32InstrInfo::commuteInstruction(MachineInstr *MI) const {
+  // Normal instructions can be commuted the obvious way.
+  if (MI->getOpcode() != PPC::RLWIMI)
+    return TargetInstrInfo::commuteInstruction(MI);
+  
+  // Cannot commute if it has a non-zero rotate count.
+  if (MI->getOperand(3).getImmedValue() != 0)
+    return 0;
+  
+  // If we have a zero rotate count, we have:
+  //   M = mask(MB,ME)
+  //   Op0 = (Op1 & ~M) | (Op2 & M)
+  // Change this to:
+  //   M = mask((ME+1)&31, (MB-1)&31)
+  //   Op0 = (Op2 & ~M) | (Op1 & M)
+
+  // Swap op1/op2
+  unsigned Reg1 = MI->getOperand(1).getReg();
+  unsigned Reg2 = MI->getOperand(2).getReg();
+  MI->SetMachineOperandReg(2, Reg1);
+  MI->SetMachineOperandReg(1, Reg2);
+  
+  // Swap the mask around.
+  unsigned MB = MI->getOperand(4).getImmedValue();
+  unsigned ME = MI->getOperand(5).getImmedValue();
+  MI->getOperand(4).setImmedValue((ME+1) & 31);
+  MI->getOperand(5).setImmedValue((MB-1) & 31);
+  return MI;
+}
diff --git a/llvm/lib/Target/PowerPC/PPC32InstrInfo.h b/llvm/lib/Target/PowerPC/PPC32InstrInfo.h
index 35bab982f0d4..bbc0be4cd56f 100644
--- a/llvm/lib/Target/PowerPC/PPC32InstrInfo.h
+++ b/llvm/lib/Target/PowerPC/PPC32InstrInfo.h
@@ -38,6 +38,10 @@ public:
                            unsigned& sourceReg,
                            unsigned& destReg) const;
 
+  // commuteInstruction - We can commute rlwimi instructions, but only if the
+  // rotate amt is zero.  We also have to munge the immediates a bit.
+  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+  
   static unsigned invertPPCBranchOpcode(unsigned Opcode) {
     switch (Opcode) {
     default: assert(0 && "Unknown PPC branch opcode!");
diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
index 33c52441f0bd..96a8ea7bcee7 100644
--- a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
@@ -733,7 +733,8 @@ def FSUBS : AForm_2<59, 20,
 
 // M-Form instructions.  rotate and mask instructions.
 //
-let isTwoAddress = 1 in {
+let isTwoAddress = 1, isCommutable = 1 in {
+// RLWIMI can be commuted if the rotate amount is zero.
 def RLWIMI : MForm_2<20,
                      (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 
                       u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;
-- 
GitLab