From e5b8234685261d5f26a450669a9a5e1ca88c1490 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 12 Aug 2003 05:19:49 +0000 Subject: [PATCH] Fix emission of instructions that directly reference MBBs llvm-svn: 7771 --- .../tools/TableGen/InstrSelectorEmitter.cpp | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/llvm/support/tools/TableGen/InstrSelectorEmitter.cpp b/llvm/support/tools/TableGen/InstrSelectorEmitter.cpp index 9bc50cee7151..28c7de114037 100644 --- a/llvm/support/tools/TableGen/InstrSelectorEmitter.cpp +++ b/llvm/support/tools/TableGen/InstrSelectorEmitter.cpp @@ -1205,15 +1205,21 @@ void InstrSelectorEmitter::run(std::ostream &OS) { if (P->getResult()) OS << ", NewReg"; OS << ")"; - for (unsigned i = 0, e = Operands.size(); i != e; ++i) - if (Operands[i].first->isLeaf()) { - Record *RV = Operands[i].first->getValueRecord(); + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + TreePatternNode *Op = Operands[i].first; + if (Op->isLeaf()) { + Record *RV = Op->getValueRecord(); assert(RV->isSubClassOf("RegisterClass") && "Only handles registers here so far!"); OS << ".addReg(" << Operands[i].second << "->Val)"; - } else { + } else if (Op->getOperator()->getName() == "imm") { OS << ".addZImm(" << Operands[i].second << "->Val)"; + } else if (Op->getOperator()->getName() == "basicblock") { + OS << ".addMBB(" << Operands[i].second << "->Val)"; + } else { + assert(0 && "Unknown value type!"); } + } OS << ";\n"; break; case Pattern::Expander: { -- GitLab