From f694c10c8ed9c81868b58ff7406d00be355cdaf2 Mon Sep 17 00:00:00 2001 From: Vincent Lejeune Date: Thu, 14 Feb 2013 16:55:01 +0000 Subject: [PATCH] R600: Do not fold modifier/litterals in vector inst This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard llvm-svn: 175180 --- llvm/lib/Target/R600/AMDILISelDAGToDAG.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/R600/AMDILISelDAGToDAG.cpp b/llvm/lib/Target/R600/AMDILISelDAGToDAG.cpp index a88e8c7fc64d..b125ba87ed13 100644 --- a/llvm/lib/Target/R600/AMDILISelDAGToDAG.cpp +++ b/llvm/lib/Target/R600/AMDILISelDAGToDAG.cpp @@ -218,7 +218,9 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) { continue; } } else { - if (!TII->isALUInstr(Use->getMachineOpcode())) { + if (!TII->isALUInstr(Use->getMachineOpcode()) || + (TII->get(Use->getMachineOpcode()).TSFlags & + R600_InstFlag::VECTOR)) { continue; } @@ -261,7 +263,8 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) { if (ST.device()->getGeneration() <= AMDGPUDeviceInfo::HD6XXX) { const R600InstrInfo *TII = static_cast(TM.getInstrInfo()); - if (Result && Result->isMachineOpcode() + if (Result && Result->isMachineOpcode() && + !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR) && TII->isALUInstr(Result->getMachineOpcode())) { // Fold FNEG/FABS/CONST_ADDRESS // TODO: Isel can generate multiple MachineInst, we need to recursively -- GitLab