- Oct 11, 2013
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Quentin Colombet authored
other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> llvm-svn: 192471
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Shankar Easwaran authored
There are aliases for --start-group/--end-group options represented by -( and -) respectively in the command line. This change adds and improves the test for the alias options to be tested. Looks like users use this option widely than explicitly using --start-group/--end-group. llvm-svn: 192470
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Ed Maste authored
Just pass a Target* into ObjectFileELF::GetImageInfoAddress so that it can do the extra dereference necessary on MIPS, instead of passing a flag back to the caller. Review: http://llvm-reviews.chandlerc.com/D1899 llvm-svn: 192469
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Fariborz Jahanian authored
migration, the typedef has annotations. // rdar://15200602 llvm-svn: 192468
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Ed Maste authored
llvm-svn: 192467
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Daniel Malea authored
llvm-svn: 192466
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Hans Wennborg authored
llvm-svn: 192465
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Rafael Espindola authored
llvm-svn: 192464
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Rafael Espindola authored
llvm-svn: 192463
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Ed Maste authored
llvm-svn: 192462
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Renato Golin authored
llvm-svn: 192460
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Amara Emerson authored
llvm-svn: 192458
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Matthias Braun authored
llvm-svn: 192455
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Matthias Braun authored
llvm-svn: 192454
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Sergey Matveev authored
llvm-svn: 192453
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Dmitry Vyukov authored
llvm-svn: 192452
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Matheus Almeida authored
llvm-svn: 192451
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Matheus Almeida authored
llvm-svn: 192450
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Matheus Almeida authored
llvm-svn: 192449
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Dmitry Vyukov authored
Currently data-race-test unittests fail with the following false positive: WARNING: ThreadSanitizer: data race (pid=20365) Write of size 8 at 0x7da000008050 by thread T54: #0 close tsan_interceptors.cc:1483 (racecheck_unittest-linux-amd64-O0+0x0000000eb34a) #1 NegativeTests_epoll::Worker2() unittest/posix_tests.cc:1148 (racecheck_unittest-linux-amd64-O0+0x0000000cc6b1) #2 MyThread::ThreadBody(MyThread*) unittest/./thread_wrappers_pthread.h:367 (racecheck_unittest-linux-amd64-O0+0x000000097500) Previous read of size 8 at 0x7da000008050 by thread T49: #0 epoll_ctl tsan_interceptors.cc:1646 (racecheck_unittest-linux-amd64-O0+0x0000000e9fee) #1 NegativeTests_epoll::Worker1() unittest/posix_tests.cc:1140 (racecheck_unittest-linux-amd64-O0+0x0000000cc5b5) #2 MyThread::ThreadBody(MyThread*) unittest/./thread_wrappers_pthread.h:367 (racecheck_unittest-linux-amd64-O0+0x000000097500) llvm-svn: 192448
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Matheus Almeida authored
INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192447
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Matheus Almeida authored
llvm-svn: 192446
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Justin Holewinski authored
[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc Fixes PR17529 llvm-svn: 192445
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Justin Holewinski authored
Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom comments for implicit defs For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers, while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be emitted as a true PTX register name. Other targets can use this to customize the output of implicit def comments. Fixes PR17519 llvm-svn: 192444
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Sergey Matveev authored
llvm-svn: 192443
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Sergey Matveev authored
Add a test. llvm-svn: 192442
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Alexey Samsonov authored
llvm-svn: 192441
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Amara Emerson authored
llvm-svn: 192440
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Robert Lytton authored
llvm-svn: 192439
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Daniel Sanders authored
[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) llvm-svn: 192438
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Robert Lytton authored
llvm-svn: 192437
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Robert Lytton authored
Incorrect handling of 'double' and 'long long int' llvm-svn: 192436
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Daniel Sanders authored
llvm-svn: 192435
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Robert Lytton authored
llvm-svn: 192434
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Robert Lytton authored
llvm-svn: 192433
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Robert Lytton authored
When a ConstantExpr which uses a thread local is part of a PHI node instruction, the insruction that replaces the ConstantExpr must be inserted in the predecessor block, in front of the terminator instruction. If the predecessor block has multiple successors, the edge is first split. llvm-svn: 192432
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Robert Lytton authored
llvm-svn: 192431
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Daniel Sanders authored
llvm-svn: 192430
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Daniel Sanders authored
[mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) llvm-svn: 192429
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Alexey Samsonov authored
[Sanitizer] Simplify StackTrace::FastUnwindStack interface and fix a bug with one-frame stack traces llvm-svn: 192428
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