llvm-svn: 175652

llvm-svn: 175651

llvm-svn: 175650

diagnose attributes on alias declarations, using directives, and attribute
declarations.

llvm-svn: 175649

llvm-svn: 175648

llvm-svn: 175647

loads. On FreeBSD, add PROT_READ page protection flag before flushing
cache.

llvm-svn: 175646

Performance is the same, but LiveRangeUpdater has a more flexible
interface.

llvm-svn: 175645

Adding new segments to large LiveIntervals can be expensive because the
LiveRange objects after the insertion point may need to be moved left or
right. This can cause quadratic behavior when adding a large number of
segments to a live range.

The LiveRangeUpdater class allows the LIveInterval to be in a temporary
invalid state while segments are being added. It maintains an internal
gap in the LiveInterval when it is shrinking, and it has a spill area
for new segments when the LiveInterval is growing.

The behavior is similar to the existing mergeIntervalRanges() function,
except it allocates less memory for the spill area, and the algorithm is
turned inside out so the loop is driven by the clients.

llvm-svn: 175644

Adding support for absolute relocations.  This occurs in ELF files when a relocation is given with no name and an undefined section.  The relocation is applied with an address of zero.

llvm-svn: 175643

- When extloading from a vector with non-byte-addressable element, e.g.
  <4 x i1>, the current logic breaks. Extend the current logic to
  fix the case where the element type is not byte-addressable by loading
  all bytes, bit-extracting/packing each element.

llvm-svn: 175642

llvm-svn: 175641

It is useful to be able to create temporary LiveRange object whose
members are filled in later.

llvm-svn: 175639

llvm-svn: 175638

llvm-svn: 175637

llvm-svn: 175636

The PPC backend doesn't handle these correctly.  This patch uses logic
similar to that in the X86 and ARM backends to track these arguments
properly.

llvm-svn: 175635

Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.

llvm-svn: 175634

Sorry, I didn't cover +Asserts, by accident. :(

llvm-svn: 175633

During lowering of a BUILD_VECTOR, we look for opportunities to use a
vector splat.  When the splatted value fits in 5 signed bits, a single
splat does the job.  When it doesn't fit in 5 bits but does fit in 6,
and is an even value, we can splat on half the value and add the result
to itself.

This last optimization hasn't been working recently because of improved
constant folding.  To circumvent this, create a pseudo VADD_SPLAT that
can be expanded during instruction selection.

llvm-svn: 175632

[ASan] Delete asan/dynamic dir and temporarily move the interposers declarations to asan_intercepted_functions.h
Now that we have only one dependency on asan_intercepted_functions.h, we can unite that code with the interceptors declarations in asan_interceptors.cc and get rid of asan_intercepted_functions.h

llvm-svn: 175631

Now correctly indents (again):
a = a + "a"
        "a"
        "a";

llvm-svn: 175630

llvm-svn: 175629

We now indent the following correctly:
1. some + "literal" /* comment */
          "literal";
2. breaking string literals after which we have another string literal.

llvm-svn: 175628

llvm-svn: 175627

llvm-svn: 175626

llvm-svn: 175625

    
* Fixed a comment typo
* Changed 'autogen' to 'generated-tests'
* Made the clean target not fail if the 'generated-tests' directory
  doesn't already exist.

llvm-svn: 175624

llvm-svn: 175623

llvm-svn: 175622

llvm-svn: 175621

If the code author decides to put empty lines anywhere into the code we
should treat them equally, i.e. reduce them to the configured
MaxEmptyLinesToKeep.

With this change, we e.g. keep the newline in:
SomeType ST = {
  // First value
  a,

  // Second value
  b
};

llvm-svn: 175620

 sext <4 x i1> to <4 x i64>
 sext <4 x i8> to <4 x i64>
 sext <4 x i16> to <4 x i64>
 
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
 (sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
 
 The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
 The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.

I also added a cost of this operations to the AVX costs table.

llvm-svn: 175619

llvm-svn: 175618

llvm-svn: 175617

It is possible that frame pointer is not found in the
callee saved info, thus FramePtrSpillFI may be incorrect
if we don't check the result of hasFP(MF).

Besides, if we enable the stack coloring algorithm, there
will be an assertion to ensure the slot is live.  But in
the test case, %var1 is not live in the prologue of the
function, and we will get the assertion failure.

Note: There is similar code in ARMFrameLowering.cpp.
llvm-svn: 175616

llvm-svn: 175615

llvm-svn: 175614

An alternative strategy to calculating the break on demand when hitting
a token that would need to be broken would be to put all possible breaks
inside the token into the optimizer.

Currently only supports breaking at spaces; more break points to come.

llvm-svn: 175613

llvm-svn: 175610