- Apr 26, 2013
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Ulrich Weigand authored
PowerPC: Fix encoding of stfsu and stfdu instructions When testing the asm parser, I noticed wrong encodings for the above instructions (wrong sub-opcodes). Note that apparently the compiler currently never generates pre-inc instructions for floating point types for some reason ... Tests will be added together with the asm parser. llvm-svn: 180607
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Ulrich Weigand authored
PowerPC: Fix encoding of rldimi and rldcl instructions When testing the asm parser, I noticed wrong encodings for the above instructions (wrong operand name in rldimi, wrong form and sub-opcode for rldcl). Tests will be added together with the asm parser. llvm-svn: 180606
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Ulrich Weigand authored
PowerPC: Support PC-relative fixup_ppc_brcond14. When testing the asm parser, I ran into an error when using a conditional branch to an external symbol (this doesn't occur in compiler-generated code) due to missing support in PPCELFObjectWriter::getRelocTypeInner. llvm-svn: 180605
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Benjamin Kramer authored
llvm-svn: 180604
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Richard Smith authored
llvm-svn: 180603
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Sergey Matveev authored
llvm-svn: 180602
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Rafael Espindola authored
On a 32 bit build this moves LinkageSpecDecl from 52 to 48 bytes. llvm-svn: 180601
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Benjamin Kramer authored
llvm-svn: 180600
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Sergey Matveev authored
llvm-svn: 180599
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Joerg Sonnenberger authored
llvm-svn: 180598
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Benjamin Kramer authored
This already helps SSE2 x86 a lot because it lacks an efficient way to represent a vector select. The long term goal is to enable the backend to match a canonicalized pattern into a single instruction (e.g. vabs or pabs). llvm-svn: 180597
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David Blaikie authored
llvm-svn: 180594
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Nadav Rotem authored
LoopVectorizer: Calculate the number of pointers to disambiguate at runtime based on the numbers of reads and writes. llvm-svn: 180593
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Michael Gottesman authored
Thanks Chandler! llvm-svn: 180592
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Rafael Espindola authored
Original commit message: Fix a case in linkage computation that should check for single line extern "C". llvm-svn: 180591
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Michael Gottesman authored
Revert "[objc-arc] Added ImpreciseAutoreleaseSet to track autorelease calls that were once autoreleaseRV instructions." This reverts commit r180222. I think this might tie in with a different problem which will require a different approach potentially. I am reverting this in the case I need to go down that second path. My apologies for the noise. = /. llvm-svn: 180590
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Michael Gottesman authored
Updated GettingStarted.rst so that it references utils/git-svn for git-svnup instead of catting it into the documentation itself. llvm-svn: 180589
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Enrico Granata authored
llvm-svn: 180588
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Michael Gottesman authored
It makes more sense to have git-svnup here than catting said file in the documentation (where we should rather point users to this directory). I included git-svnrevert as an additional gift to the community. I will update the documentation in a second commit later today. git-svnrevert takes in a git hash for a commit, looks up the svn revision for said commit and then creates the normal git revert commit message with the one liner message, except instead of saying Revert "<<<INSERT ONELINER HERE>>>" This reverts commit <<<INSERT GITHASH HERE>>> It says: Revert "<<<INSERT ONELINER HERE>>>" This reverts commit r<<<INSERT SVN REVISION HERE>>> so git hashes will not escape into our svn logs (which just look unseemly). llvm-svn: 180587
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Rafael Espindola authored
Thanks to Bill Wendling for the original testcase. llvm-svn: 180586
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Ted Kremenek authored
llvm-svn: 180585
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Jack Carter authored
Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
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Bill Wendling authored
llvm-svn: 180583
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Anna Zaks authored
llvm-svn: 180582
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Matt Kopec authored
Patch by Ashok Thirumurthi. llvm-svn: 180581
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- Apr 25, 2013
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Fariborz Jahanian authored
patch -n r180198. When reporting on missing property accessor implementation in categories, do not report when they are declared in primary class, class's protocol, or one of it super classes or in of the other categories. // rdar://13713098 llvm-svn: 180580
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Anna Zaks authored
llvm-svn: 180579
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Michael Liao authored
Pattern has source location by itself. After adding a trivial method to retrieve it, it's unnecessary to pair a source location for CHECK-NOT patterns. One thing revised after this is the diagnostic info is more accurate by pointing to the start of the CHECK-NOT pattern instead of the end of the CHECK-NOT pattern. E.g. diagnostic message previously looks like <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:16: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ is changed to <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:12: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ llvm-svn: 180578
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Preston Gurd authored
Expunge all remaining traces and use of live variable information. llvm-svn: 180577
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Arnold Schwaighofer authored
Reflect this in the cost model. I observed this in MiBench/consumer-lame. radar://13354716 llvm-svn: 180576
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Andrew Kaylor authored
llvm-svn: 180575
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Chris Lattner authored
llvm-svn: 180574
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Preston Gurd authored
latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573
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Ashok Thirumurthi authored
- Adds unique enums for ymm registers to the ABI and the POSIX register context. - Reworks the register context data structures to support a union of FXSAVE and XSAVE --- Allows the same code base to deal with the FPU independent of the availability of AVX. - Determine if AVX is supported by attempting to read XSAVE using ptrace. --- Support an extended register set for avx registers if available. - Provide a mechanism to assemble/parse register halves into a single ymm buffer for use with RegisterValue. --- Reworked Read/WriteRegister routines to read/write/parse ymm registers. Adds tests for ymm register write with read-back, and expressions involving ymm registers. - Tests vary depending on the availability of an avx register set. Thanks to Daniel and Matt for their reviews. llvm-svn: 180572
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Rafael Espindola authored
When we find a friend declaration we have to skip transparent contexts for doing lookups, but we should not skip them when inserting the new decl if the lookup found nothing. Fixes PR15841. llvm-svn: 180571
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Nadav Rotem authored
llvm-svn: 180570
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Reid Kleckner authored
Summary: This is modelled on the Mach-O linker options implementation and should support a Clang implementation of #pragma comment(lib/linker). Reviewers: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D724 llvm-svn: 180569
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Rafael Espindola authored
Patch by Kai Nacke. This matches the gnu as output. llvm-svn: 180568
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Sean Callanan authored
interpreter. They are a legacy from when the IR interpreter didn't work with materialized values but rather got values directly from ClangExpressionDeclMap. Also updated the #includes for IRInterpreter accordingly. llvm-svn: 180565
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Michael Liao authored
llvm-svn: 180564
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