This commit caused -Woverloaded-virtual warnings. The two new
TargetTransformInfo::getIntImmCost functions were only added to the superclass,
and to the X86 subclass. The other targets were not updated, and the
warning highlighted this by pointing out that e.g. ARMTTI::getIntImmCost was
hiding the two new getIntImmCost variants.

We could pacify the warning by adding "using TargetTransformInfo::getIntImmCost"
to the various subclasses, or turning it off, but I suspect that it's wrong to
leave the functions unimplemnted in those targets. The default implementations
return TCC_Free, which I don't think is right e.g. for ARM.

llvm-svn: 200058

Previously, string literals were ignored in all logical expressions.  This
reduces it to only ignore in logical and expressions.

assert(0 && "error"); // No warning
assert(0 || "error"); // Warn

Fixes PR17565

llvm-svn: 200056

This will be extended as we fix issues in the current implementation.

llvm-svn: 200054

Rename "ec" to "EC", and rename some iterators.

Then fix whitespace using clang-format-diff.

(As requested in http://llvm-reviews.chandlerc.com/D2559)

Differential Revision: http://llvm-reviews.chandlerc.com/D2594

llvm-svn: 200053

llvm-svn: 200052

This patch uses a common MipsTargetSteamer interface for both 
MipsAsmPrinter and MipsAsmParser for recording default and commandline
driven directives that affect ELF header flags.

It has been noted that the .ll tests affected by this patch belong in
test/Codegen/Mips. I will move them in a separate patch.

Also, a number of directives do not get expressed by AsmPrinter in the 
resultant .s assembly such as setting the correct ASI. I have noted this
in the tests and they will be addressed in later patches.

llvm-svn: 200051

llvm-svn: 200050

Patch by Andrew MacPherson.

llvm-svn: 200049

llvm-svn: 200048

it later in GDBRemoteCommunication::StartDebugserverProcess and report
an error.
<rdar://problem/15820813> 

llvm-svn: 200047

The i8 type is not registered with any register class.
This causes a segmentation fault in MachineLICM::getRegisterClassIDAndCost.

The code selects the first type associated with register class FPR8,
which happens to be i8.
It uses this type (i8) to get the representative class pointer, which is 0.
It then uses this pointer to access a field, resulting in segmentation fault.

Since i8 type is not being used for printing any neon instruction
we can safely remove it.

llvm-svn: 200046

allow this, and we should warn on it, but it turns out that people were already
relying on this.

We should introduce a -Wgcc-compat warning for this if the attributes are known
to GCC, but we don't currently track enough information about attributes to do
so reliably.

llvm-svn: 200045

llvm-svn: 200044

It was redundant (since ARM mode is the default) and misleading since
(e.g.) Cortex-A15 would not satisfy the #ifdef but would be in ARM
mode regardless.

llvm-svn: 200043

llvm-svn: 200042

Adds a getSemanticSpelling function to semantic attribute subclasses which have a meaningful semantic spelling. Adds a sibling function to parsed attribtues (via AttributeList) for getting the semantic spelling, if one were to exist. This can be used for cleaner code that deals directly with the semantic spellings (such as the MSInheritance attribute).

llvm-svn: 200041

This allows llvm-ar to mmap the input files only once.

llvm-svn: 200040

llvm-svn: 200039

This change does not affect anything because everybody seems to be using
Object/COFF.h instead. But the definition is not for PE32 but for PE32+,
so fix it anyway.

llvm-svn: 200038

llvm-svn: 200037

Replace tablegen uses of EVT with MVT. Add isOverloaded() to MVT to facilitate. Remove TGValueTypes.cpp since its unused now (and may have been before).

llvm-svn: 200036

remains ARM mode only, supporting thumb requires explicit it prefixes
for the predicted adds/subs and adjusting the offset computation for the
different block sizes.

llvm-svn: 200035

Retry commit r200022 with a fix for the build bot errors. Constant expressions
have (unlike instructions) module scope use lists and therefore may have users
in different functions. The fix is to simply ignore these out-of-function uses.

llvm-svn: 200034

DAGCombiner::GatherAllAliases, which is only used when AA used is enabled
during DAGCombine, had a fundamentally incorrect assumption for which this
change compensates. GatherAllAliases, which is used to find aliasing
predecessor chain nodes (so that a better chain can be selected for a load or
store to enable subsequent optimizations) assumed that walking up the chain
would always catch all possibly-aliasing loads and stores. This is not true: To
really find all aliases, we also need to search for aliases through the value
operand of a store, etc.  Consider the following situation:

  Token1 = ...
  L1 = load Token1, %52
  S1 = store Token1, L1, %51
  L2 = load Token1, %52+8
  S2 = store Token1, L2, %51+8
  Token2 = Token(S1, S2)
  L3 = load Token2, %53
  S3 = store Token2, L3, %52
  L4 = load Token2, %53+8
  S4 = store Token2, L4, %52+8

If we search for aliases of S3 (which loads address %52), and we look only
through the chain, then we'll miss the trivial dependence on L1 (which loads
from %52). We then might change all loads and stores to use Token1 as their
chain operand, which could result in copying %53 into %52 before copying
%52 into %51 (which should happen first).

The problem is, however, that searching for such data dependencies can become
expensive, and the cost is not directly related to the chain depth. Instead,
we'll rule out such configurations by insisting that we've visited all chain
users (except for users of the original chain, which is not necessary).  When
doing this, we need to look through nodes we don't care about (otherwise,
things like register copies will interfere with trivial use cases).

Unfortunately, I don't have a small test case for this problem. Creating the
underlying situation is not hard (a pair of memcpys will do it), but arranging
for the default instruction schedule to be incorrect is very fragile.

This unbreaks self hosting on PPC64 when using
-mllvm -combiner-global-alias-analysis -mllvm -combiner-alias-analysis.

llvm-svn: 200033

Since Visual Studio 2012 is the minimum version of MSVC we support, the old-style visualizers are being removed. Adding a Natvis replacement for the debugging visualizers.

llvm-svn: 200032

might have a smaller size as compared to the stand-alone type of the base class.
This is possible when the derived class is packed and hence might have smaller
alignment requirement than the base class.

Differential Revision: http://llvm-reviews.chandlerc.com/D2599

llvm-svn: 200031

We don't want to lose attributes when a function decl without them is merged
with a function decl that has them.
PR2382

llvm-svn: 200030

This is the first patch to support PE32+ format, which is the image format
to use 64 bit address space on Windows/x86-64.

llvm-svn: 200029

PR18600.

llvm-svn: 200028

<rdar://problem/15611947>

llvm-svn: 200027

This reverts commit r200022 to unbreak the build bots.

llvm-svn: 200024

These transformations obviously won't work for indexed (pre/post-inc) loads and
stores. In practice, I'm not sure there is any benefit to enabling them for
indexed nodes because other transformations that these might enable likely also
won't handle indexed nodes.

I don't have an in-tree test case that hits this problem, but an upcoming bug
fix will make it much more likely.

llvm-svn: 200023

This pass identifies expensive constants to hoist and coalesces them to
better prepare it for SelectionDAG-based code generation. This works around the
limitations of the basic-block-at-a-time approach.

First it scans all instructions for integer constants and calculates its
cost. If the constant can be folded into the instruction (the cost is
TCC_Free) or the cost is just a simple operation (TCC_BASIC), then we don't
consider it expensive and leave it alone. This is the default behavior and
the default implementation of getIntImmCost will always return TCC_Free.

If the cost is more than TCC_BASIC, then the integer constant can't be folded
into the instruction and it might be beneficial to hoist the constant.
Similar constants are coalesced to reduce register pressure and
materialization code.

When a constant is hoisted, it is also hidden behind a bitcast to force it to
be live-out of the basic block. Otherwise the constant would be just
duplicated and each basic block would have its own copy in the SelectionDAG.
The SelectionDAG recognizes such constants as opaque and doesn't perform
certain transformations on them, which would create a new expensive constant.

This optimization is only applied to integer constants in instructions and
simple (this means not nested) constant cast experessions. For example:
%0 = load i64* inttoptr (i64 big_constant to i64*)

Reviewed by Eric

llvm-svn: 200022

llvm-svn: 200021

llvm-svn: 200020

llvm-svn: 200019

Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

llvm-svn: 200018

This enables IO error reports in both the child and server processes.

The scheme still isn't entirely satisfactory and output is jumbled but it beats
having no output at all. This will hopefully unblock ARM support (PR18057).

llvm-svn: 200017

llvm-svn: 200016

otherwise races are suppressed due to "same stack"

llvm-svn: 200015