llvm-svn: 27423

llvm-svn: 27422

llvm-svn: 27421

llvm-svn: 27420

llvm-svn: 27419

llvm-svn: 27418

llvm-svn: 27417

llvm-svn: 27416

llvm-svn: 27415

llvm-svn: 27414

Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.

llvm-svn: 27413

llvm-svn: 27412

__builtin_ia32_psrldqi128.

llvm-svn: 27411

llvm-svn: 27410

llvm-svn: 27409

llvm-svn: 27405

This, along with the previous dag combiner fix, fixes
CodeGen/Alpha/2006-04-04-zextload.ll

llvm-svn: 27403

legal.

llvm-svn: 27402

llvm-svn: 27401

handle all 4 PPC vector types.   This simplifies the matching code and allows
us to eliminate a bunch of patterns.  This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.

llvm-svn: 27400

  promoted/expanded (e.g. SCALAR_TO_VECTOR from i8/i16 on PPC).
* Add support for targets to request that VECTOR_SHUFFLE nodes be promoted
  to a canonical type, for example, we only want v16i8 shuffles on PPC.
* Move isShuffleLegal out of TLI into Legalize.
* Teach isShuffleLegal to allow shuffles that need to be promoted.

llvm-svn: 27399

llvm-svn: 27398

llvm-svn: 27397

llvm-svn: 27395

llvm-svn: 27393

llvm-svn: 27392

llvm-svn: 27391

promoted to, if they desire.

llvm-svn: 27389

llvm-svn: 27388

llvm-svn: 27387

llvm-svn: 27386

llvm-svn: 27385

llvm-svn: 27384

llvm-svn: 27383

Use movhpd to: store upper f64 extracted from v2f64.

llvm-svn: 27382

more than the OS keeps the stack aligned.

llvm-svn: 27381

llvm-svn: 27380

llvm-svn: 27379

llvm-svn: 27378

- Some bug fixes and naming inconsistency fixes.

llvm-svn: 27377