'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'.
With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here).

Patch by David Nadlinger!
Differential Revision: http://llvm-reviews.chandlerc.com/D429

llvm-svn: 178427

llvm-svn: 178426

Nobody says "the developer's list" or "commits archive"; they always say
"llvmdev" or "llvm-commits". It makes sense for our documentation to
at least make that association explicitly.

llvm-svn: 178425

Order them roughly by "which one should a newbie join first".

llvm-svn: 178424

llvm-svn: 178423

llvm-svn: 178422

llvm-svn: 178421

llvm-svn: 178420

llvm-svn: 178419

functions for the NVPTX target.

llvm-svn: 178418

llvm-svn: 178417

specific code paths.

This allows us to write code like:

  if (__nvvm_reflect("FOO"))
    // Do something
  else
    // Do something else

and compile into a library, then give "FOO" a value at kernel
compile-time so the check becomes a no-op.

llvm-svn: 178416

Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.

llvm-svn: 178415

gcc provides -mfprnd and -mno-fprnd for controlling the fprnd target
feature; support these options as well.

llvm-svn: 178414

No functionality change.

llvm-svn: 178413

Post-Inc can occur as a binary call (the infamous dummy int argument), but it's
not really a binary operator.

Fixes PR15628.

llvm-svn: 178412

they are probably trivial.  This means that we
don't confuse Clang about whether a class is
trivially copy constructible.  It can figure
that out itself as long as we don't explicitly
feed it the constructors.

If the class is trivially copy-constructible,
this can change the ABI that Clang uses to call
functions that return that class (e.g., by making
the object be returned in a register), so this
is quite important for correctness.

<rdar://problem/13457741>

llvm-svn: 178411

ASTContexts that will not stay around.  Before, we
did this in a very half-hearted way.  Now we maintain
work queues of all Decls that need to be completed
before the source ASTContext can go away; we then
expunge their origins completely.

<rdar://problem/13511875>

llvm-svn: 178410

  rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2),
     only useful when c1=c2
  rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2))
  rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2
  rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2

 It reduces an application's size (in terms of # of instructions) by 8.9%.
 Reviwed by Pete Cooper. Thanks a lot!

 rdar://13212115  

llvm-svn: 178409

llvm-svn: 178408

llvm-svn: 178407

Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.

llvm-svn: 178406

llvm-svn: 178405

derived class MipsSETargetLowering.

We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16
doesn't have support for multipy-add/sub instructions.

llvm-svn: 178404

The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.

llvm-svn: 178403

No functionality change.

llvm-svn: 178402

Evaluating a C++ new expression now includes generating an intermediate
ExplodedNode, and this node could very well represent a previously-
reachable state in the ExplodedGraph. If so, we can short-circuit the
rest of the evaluation.

Caught by the assertion a few lines later.

<rdar://problem/13510065>

llvm-svn: 178401

Sample output:
  #0 void construct(pointer __p, llvm::ImutAVLTree<llvm::ImutContainerInfo<clang::ento::BugType *> > *const &__val)
  #1 void push_back(const value_type &__x)
  #2 void destroy()
  #3 void release()
  #4 void ~ImmutableSet()

llvm-svn: 178400

manipulating the diagnostics engine.

<rdar://problem/13508470>

llvm-svn: 178399

llvm-svn: 178398

llvm-svn: 178397

llvm-svn: 178396

llvm-svn: 178395

instructions.

llvm-svn: 178394

called in several places in ScheduleDAGRRList.cpp.

llvm-svn: 178393

to handle accumulator registers.

llvm-svn: 178392

callee-saved scan.

The code makes use of register's scavenger's capability to spill multiple
registers.

llvm-svn: 178391

registers.

llvm-svn: 178390

(and using the new syntax for printing :-)

llvm-svn: 178389

+ Refactoring.

llvm-svn: 178388