Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic

llvm-svn: 131714

packet output from "log enable gdb-remote packets". This should help people
track down and see what is going wrong more easily when you have log output
that includes GDB remote packets.

llvm-svn: 131713

llvm-svn: 131711

This is the first of a series of patches that attempt to simplify handling of 
stack frame objects. 

llvm-svn: 131710

llvm-svn: 131709

llvm-svn: 131708

breaks it for you (or if the LanguageRuntime plugins break the build on your
machine), please let me know and I'll revert.

Also, link to CoreServices and Carbon on Mac. Yep, LLDB needs these ancient
frameworks.

llvm-svn: 131707

llvm-svn: 131706

similarly for stores. Now "make check" passes with the MachineVerifier forced
on with the VerifyCoalescing option!

llvm-svn: 131705

Mac OS X Process plugin from the build.

I'm surprised no one caught this earlier. Am I the only one who builds with
the makefiles on Mac?

llvm-svn: 131704

llvm-svn: 131703

llvm-svn: 131702

llvm-svn: 131701

llvm-svn: 131700

llvm-svn: 131699

llvm-svn: 131698

Replace python static settings of compiler flags with invocation of
python-config.

Signed-off-by: Johnny Chen <johnny.chen@apple.com>
llvm-svn: 131697

Removed ifdeffed out functions and added the implementation of
WriteRegister for x86_64 architecture.

Signed-off-by: Johnny Chen <johnny.chen@apple.com>
llvm-svn: 131696

Host.cpp was missing Error.h and the implementation of
LaunchProcess. Once againg I have added a "fake" implementation
waiting for a real one.

Fixed the call GetAddressRange to reflect the new interface in
DynamicLoaderLinuxDYLD.cpp.

Added string.h to ARM_DWARF_Registers.cpp that is needed for ::memset.

Signed-off-by: Johnny Chen <johnny.chen@apple.com>
llvm-svn: 131695

llvm-svn: 131694

llvm-svn: 131693

template case.

llvm-svn: 131692

llvm-svn: 131691

llvm-svn: 131689

foo:
bar = foo
.quad bar

Avoid producing it. Fixes PR9951.

llvm-svn: 131687

llvm-svn: 131686

llvm-svn: 131685

Seriously, I have no idea how you guys managed to build LLDB before.

llvm-svn: 131684

* Remove unnecessary arguments now that ForceExpAbs is a method.
* Use ForceExpAbs in EmitAbsValue.

llvm-svn: 131683

Fixes rdar://9218925
Fixes PR9601

llvm-svn: 131682

llvm-svn: 131681

Add TestCallStdStringFunction.py which calls std::string member functions while stopped on a breakpoint.

llvm-svn: 131680

llvm-svn: 131679

the root if there is only one such node. This leaves only 2 verifier failures in
the entire test suite when running "make check".

llvm-svn: 131677

Fix up this test to use explicit triples (Win64 passes a different number of arguments in registers).

llvm-svn: 131676

text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

llvm-svn: 131674

Reapply r131605. This time with a fix, which is to use NoFolder.

llvm-svn: 131673

llvm-svn: 131672

llvm-svn: 131671

llvm-svn: 131670