diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index c609ee6174db2effc25098aad3e7b2be96c322b9..6884e0001c8ce5710ce2e4e660aee6e434ddbf03 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -288,7 +288,7 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
 
 // Conditional code operand for conditional branches and conditional moves.
 // No AlwaysVal value.
-def ccop : ImmutablePredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
+def ccop : PredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
   let PrintMethod = "printPredicateOperand";
 }
 
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 4ffde0a97faa82482364e80c4ecdaeccfefd9264..fe189784009f66f78d372a2daba3ecce13171d96 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -272,8 +272,8 @@ def memrix : Operand<iPTR> {   // memri where the imm is shifted 2 bits.
 
 // PowerPC Predicate operand.  20 = (0<<5)|20 = always, CR0 is a dummy reg
 // that doesn't matter.
-def pred : ImmutablePredicateOperand<OtherVT, (ops imm, CRRC),
-                                              (ops (i32 20), CR0)> {
+def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
+                                     (ops (i32 20), CR0)> {
   let PrintMethod = "printPredicateOperand";
 }