From fa620fc8e28ef1895a009994d6e838e3ddbcb32a Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 11 Feb 2020 13:37:44 +0000 Subject: [PATCH 001/142] [X86] combineConcatVectorOps - reuse IsSplat and remove duplicate code. NFC. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index b0187eb72920..f5a101196d09 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -45931,6 +45931,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT, return getZeroVector(VT, Subtarget, DAG, DL); SDValue Op0 = Ops[0]; + bool IsSplat = llvm::all_of(Ops, [&Op0](SDValue Op) { return Op == Op0; }); // Fold subvector loads into one. // If needed, look through bitcasts to get to the load. @@ -45947,7 +45948,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT, } // Repeated subvectors. - if (llvm::all_of(Ops, [Op0](SDValue Op) { return Op == Op0; })) { + if (IsSplat) { // If this broadcast/subv_broadcast is inserted into both halves, use a // larger broadcast/subv_broadcast. if (Op0.getOpcode() == X86ISD::VBROADCAST || @@ -45970,8 +45971,6 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT, return DAG.getNode(X86ISD::VBROADCAST, DL, VT, Op0.getOperand(0)); } - bool IsSplat = llvm::all_of(Ops, [&Op0](SDValue Op) { return Op == Op0; }); - // Repeated opcode. // TODO - combineX86ShufflesRecursively should handle shuffle concatenation // but it currently struggles with different vector widths. -- GitLab From 592f35481aa5e43162f09edeaac9f27773991714 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 11 Feb 2020 14:47:53 +0100 Subject: [PATCH 002/142] [libc++] Disable a filesystem test that uses debug mode with the macOS system libc++ The system libc++.dylib doesn't support the debug mode, so this test can't be supported. As a fly-by fix, we also specify more stringently that only the macOS system library is unsupported in other tests using the debug mode. --- .../filesystems/class.path/path.itr/iterator_db.pass.cpp | 3 +++ .../thread/futures/futures.promise/set_exception.pass.cpp | 4 ++-- .../futures.promise/set_exception_at_thread_exit.pass.cpp | 4 ++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/libcxx/test/libcxx/input.output/filesystems/class.path/path.itr/iterator_db.pass.cpp b/libcxx/test/libcxx/input.output/filesystems/class.path/path.itr/iterator_db.pass.cpp index 2729e59029bc..d5df253603c1 100644 --- a/libcxx/test/libcxx/input.output/filesystems/class.path/path.itr/iterator_db.pass.cpp +++ b/libcxx/test/libcxx/input.output/filesystems/class.path/path.itr/iterator_db.pass.cpp @@ -11,6 +11,9 @@ // MODULES_DEFINES: _LIBCPP_DEBUG=0 +// This test requires debug mode, which the library on macOS doesn't have. +// UNSUPPORTED: with_system_cxx_lib=macosx + // // class path diff --git a/libcxx/test/libcxx/thread/futures/futures.promise/set_exception.pass.cpp b/libcxx/test/libcxx/thread/futures/futures.promise/set_exception.pass.cpp index b3621a4e697d..37ef0d1f04be 100644 --- a/libcxx/test/libcxx/thread/futures/futures.promise/set_exception.pass.cpp +++ b/libcxx/test/libcxx/thread/futures/futures.promise/set_exception.pass.cpp @@ -12,8 +12,8 @@ // MODULES_DEFINES: _LIBCPP_DEBUG=0 -// Can't test the system lib because this test enables debug mode -// UNSUPPORTED: with_system_cxx_lib +// This test requires debug mode, which the library on macOS doesn't have. +// UNSUPPORTED: with_system_cxx_lib=macosx // diff --git a/libcxx/test/libcxx/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp b/libcxx/test/libcxx/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp index 49a41362db9a..54778777056c 100644 --- a/libcxx/test/libcxx/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp +++ b/libcxx/test/libcxx/thread/futures/futures.promise/set_exception_at_thread_exit.pass.cpp @@ -12,8 +12,8 @@ // MODULES_DEFINES: _LIBCPP_DEBUG=0 -// Can't test the system lib because this test enables debug mode -// UNSUPPORTED: with_system_cxx_lib +// This test requires debug mode, which the library on macOS doesn't have. +// UNSUPPORTED: with_system_cxx_lib=macosx // -- GitLab From 98c940bf515831420b8b53489dd4f9a4fc8a40ad Mon Sep 17 00:00:00 2001 From: Jan Kratochvil Date: Tue, 11 Feb 2020 14:54:23 +0100 Subject: [PATCH 003/142] [NFC] [lldb] Remove unused declaration ObjectFileELF::GetSectionIndexByType declaration without definition was added by commit 17220c188635721e948cf02d2b6ad36b267ea393. --- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h index 3b273896cb59..d3f620385d97 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h @@ -328,9 +328,6 @@ private: /// section index 0 is never valid). lldb::user_id_t GetSectionIndexByName(const char *name); - // Returns the ID of the first section that has the given type. - lldb::user_id_t GetSectionIndexByType(unsigned type); - /// Returns the section header with the given id or NULL. const ELFSectionHeaderInfo *GetSectionHeaderByIndex(lldb::user_id_t id); -- GitLab From 890d5e2dd232f43842d8a9025e639027946d81f4 Mon Sep 17 00:00:00 2001 From: Stephan Herhut Date: Tue, 11 Feb 2020 10:20:55 +0100 Subject: [PATCH 004/142] [MLIR][GPU] Disallow llvm tanh intrinsics when lowering to NVVM/ROCm. Summary: The lowering to NVVM and ROCm handles tanh operations differently by mapping them to NVVM/ROCm specific intrinsics. This conflicts with the lowering to LLVM, which uses the default llvm intrinsic. This change declares the LLVM intrinsics to be illegal, hence disallowing the correspondign rewrite. Differential Revision: https://reviews.llvm.org/D74389 --- .../GPUCommon/OpToFuncCallLowering.h | 18 ++++++++++++++++++ .../GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 2 ++ .../GPUToROCDL/LowerGpuOpsToROCDLOps.cpp | 5 +++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h b/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h index 570f956ee4e9..059bdfb1661f 100644 --- a/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h +++ b/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h @@ -95,6 +95,24 @@ private: const std::string f64Func; }; +namespace gpu { +/// Returns a predicate to be used with addDynamicallyLegalOp. The predicate +/// returns false for calls to the provided intrinsics and true otherwise. +inline std::function +filterIllegalLLVMIntrinsics(ArrayRef intrinsics, MLIRContext *ctx) { + SmallVector illegalIds(intrinsics.begin(), intrinsics.end()); + return [illegalIds](Operation *op) -> bool { + LLVM::CallOp callOp = dyn_cast(op); + if (!callOp || !callOp.callee()) + return true; + StringRef callee = callOp.callee().getValue(); + return !llvm::any_of(illegalIds, [callee](StringRef intrinsic) { + return callee.equals(intrinsic); + }); + }; +} +} // namespace gpu + } // namespace mlir #endif // MLIR_CONVERSION_GPUCOMMON_OPTOFUNCCALLLOWERING_H_ diff --git a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp index 09fbd3095168..d9f37dbf0d8c 100644 --- a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp +++ b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp @@ -695,6 +695,8 @@ public: target.addIllegalOp(); target.addLegalDialect(); target.addLegalDialect(); + target.addDynamicallyLegalOp( + gpu::filterIllegalLLVMIntrinsics({"tanh", "tanhf"}, m.getContext())); // TODO(csigg): Remove once we support replacing non-root ops. target.addLegalOp(); if (failed(applyPartialConversion(m, target, patterns, &converter))) diff --git a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp index d74fcdbf0507..0fd8be01f15a 100644 --- a/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp +++ b/mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp @@ -65,8 +65,9 @@ public: target.addLegalDialect(); target.addIllegalOp(); - target.addDynamicallyLegalOp( - [&](FuncOp op) { return converter.isSignatureLegal(op.getType()); }); + target.addDynamicallyLegalOp( + gpu::filterIllegalLLVMIntrinsics({"tanh", "tanhf"}, m.getContext())); + target.addIllegalOp(); if (failed(applyPartialConversion(m, target, patterns, &converter))) signalPassFailure(); } -- GitLab From d4df372559adb0ba3c652e85817a50db707c9858 Mon Sep 17 00:00:00 2001 From: Sam McCall Date: Mon, 10 Feb 2020 11:52:42 +0100 Subject: [PATCH 005/142] [clangd] Expose completion range in code completion results (C++ API) Summary: Informative only, useful for positioning UI, interacting with other sources of completion etc. As requested by an embedder of clangd. Reviewers: usaxena95 Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D74305 --- clang-tools-extra/clangd/CodeComplete.cpp | 1 + clang-tools-extra/clangd/CodeComplete.h | 5 ++++ .../clangd/unittests/CodeCompleteTests.cpp | 23 +++++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/clang-tools-extra/clangd/CodeComplete.cpp b/clang-tools-extra/clangd/CodeComplete.cpp index 4d4d15b0efae..6fc6c5d21c24 100644 --- a/clang-tools-extra/clangd/CodeComplete.cpp +++ b/clang-tools-extra/clangd/CodeComplete.cpp @@ -1473,6 +1473,7 @@ private: } Output.HasMore = Incomplete; Output.Context = CCContextKind; + Output.CompletionRange = ReplacedRange; return Output; } diff --git a/clang-tools-extra/clangd/CodeComplete.h b/clang-tools-extra/clangd/CodeComplete.h index fd01dfd80b0e..3b3dca3ee8c5 100644 --- a/clang-tools-extra/clangd/CodeComplete.h +++ b/clang-tools-extra/clangd/CodeComplete.h @@ -216,6 +216,11 @@ struct CodeCompleteResult { std::vector Completions; bool HasMore = false; CodeCompletionContext::Kind Context = CodeCompletionContext::CCC_Other; + // The text that is being directly completed. + // Example: foo.pb^ -> foo.push_back() + // ~~ + // Typically matches the textEdit.range of Completions, but not guaranteed to. + llvm::Optional CompletionRange; // Usually the source will be parsed with a real C++ parser. // But heuristics may be used instead if e.g. the preamble is not ready. bool RanParser = true; diff --git a/clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp b/clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp index 8863d9f278d7..67b8abb722be 100644 --- a/clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp +++ b/clang-tools-extra/clangd/unittests/CodeCompleteTests.cpp @@ -2134,6 +2134,7 @@ TEST(GuessCompletionPrefix, Filters) { "some text [[scope::more::]][[identif]]^ier", "some text [[scope::]][[mor]]^e::identifier", "weird case foo::[[::bar::]][[baz]]^", + "/* [[]][[]]^ */", }) { Annotations F(Case); auto Offset = cantFail(positionToOffset(F.code(), F.point())); @@ -2675,6 +2676,28 @@ TEST(CompletionTest, NoCrashWithIncompleteLambda) { EXPECT_THAT(Signatures, Contains(Sig("x() -> auto"))); } +TEST(CompletionTest, CompletionRange) { + const char *WithRange = "auto x = [[abc]]^"; + auto Completions = completions(WithRange); + EXPECT_EQ(Completions.CompletionRange, Annotations(WithRange).range()); + Completions = completionsNoCompile(WithRange); + EXPECT_EQ(Completions.CompletionRange, Annotations(WithRange).range()); + + const char *EmptyRange = "auto x = [[]]^"; + Completions = completions(EmptyRange); + EXPECT_EQ(Completions.CompletionRange, Annotations(EmptyRange).range()); + Completions = completionsNoCompile(EmptyRange); + EXPECT_EQ(Completions.CompletionRange, Annotations(EmptyRange).range()); + + // Sema doesn't trigger at all here, while the no-sema completion runs + // heuristics as normal and reports a range. It'd be nice to be consistent. + const char *NoCompletion = "/* [[]]^ */"; + Completions = completions(NoCompletion); + EXPECT_EQ(Completions.CompletionRange, llvm::None); + Completions = completionsNoCompile(NoCompletion); + EXPECT_EQ(Completions.CompletionRange, Annotations(NoCompletion).range()); +} + TEST(NoCompileCompletionTest, Basic) { auto Results = completionsNoCompile(R"cpp( void func() { -- GitLab From 42f8b915eb72364cc5e84adf58a2c2d4947e8b10 Mon Sep 17 00:00:00 2001 From: Kadir Cetinkaya Date: Tue, 11 Feb 2020 15:26:15 +0100 Subject: [PATCH 006/142] Revert "[DSE] Add first version of MemorySSA-backed DSE (Bottom up walk)." This reverts commit d0c4d4fe0929098a98d9fb20c5e5e19d71341517. Revert "[DSE,MSSA] Move more passing test cases from todo to simple.ll." This reverts commit 02266e64bb6dacf76f3aa510df4b59f66d834b1f. Revert "[DSE,MSSA] Adjust mda-with-dbg-values.ll to MSSA backed DSE." This reverts commit 74f03e4ff0c1f11c29102329af95f7d9782426dc. --- .../Scalar/DeadStoreElimination.cpp | 538 +----------------- .../MSSA/2011-09-06-EndOfFunction.ll | 1 - .../MSSA/OverwriteStoreBegin.ll | 1 - .../MSSA/OverwriteStoreEnd.ll | 1 - .../DeadStoreElimination/MSSA/atomic.ll | 1 - .../DeadStoreElimination/MSSA/calloc-store.ll | 2 - .../DeadStoreElimination/MSSA/fence-todo.ll | 50 -- .../DeadStoreElimination/MSSA/fence.ll | 48 ++ .../DeadStoreElimination/MSSA/free.ll | 2 - .../DeadStoreElimination/MSSA/inst-limits.ll | 9 +- .../DeadStoreElimination/MSSA/lifetime.ll | 2 - .../MSSA/mda-with-dbg-values.ll | 20 +- .../MSSA/memcpy-complete-overwrite.ll | 2 - .../MSSA/memintrinsics.ll | 1 - .../MSSA/memoryssa-scan-limit.ll | 72 --- .../MSSA/memset-and-memcpy.ll | 9 +- .../MSSA/memset-missing-debugloc.ll | 1 - .../MSSA/merge-stores-big-endian.ll | 1 - .../DeadStoreElimination/MSSA/merge-stores.ll | 1 - .../MSSA/multiblock-captures.ll | 7 +- .../MSSA/multiblock-exceptions.ll | 1 - .../MSSA/multiblock-loops.ll | 114 +--- .../MSSA/multiblock-memoryphis.ll | 70 --- .../MSSA/multiblock-partial.ll | 3 +- .../MSSA/multiblock-simple.ll | 41 +- .../MSSA/operand-bundles.ll | 1 - .../DeadStoreElimination/MSSA/simple-todo.ll | 159 +++++- .../DeadStoreElimination/MSSA/simple.ll | 167 +----- 28 files changed, 259 insertions(+), 1066 deletions(-) delete mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll delete mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/memoryssa-scan-limit.ll diff --git a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp index e039d97139db..f56a4c5f8920 100644 --- a/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp +++ b/llvm/lib/Transforms/Scalar/DeadStoreElimination.cpp @@ -29,10 +29,7 @@ #include "llvm/Analysis/MemoryBuiltins.h" #include "llvm/Analysis/MemoryDependenceAnalysis.h" #include "llvm/Analysis/MemoryLocation.h" -#include "llvm/Analysis/MemorySSA.h" -#include "llvm/Analysis/MemorySSAUpdater.h" #include "llvm/Analysis/OrderedBasicBlock.h" -#include "llvm/Analysis/PostDominators.h" #include "llvm/Analysis/TargetLibraryInfo.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/IR/Argument.h" @@ -43,7 +40,6 @@ #include "llvm/IR/DataLayout.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/Function.h" -#include "llvm/IR/InstIterator.h" #include "llvm/IR/InstrTypes.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" @@ -91,20 +87,11 @@ EnablePartialStoreMerging("enable-dse-partial-store-merging", cl::init(true), cl::Hidden, cl::desc("Enable partial store merging in DSE")); +// Temporary dummy option for tests. static cl::opt EnableMemorySSA("enable-dse-memoryssa", cl::init(false), cl::Hidden, cl::desc("Use the new MemorySSA-backed DSE.")); -static cl::opt - MemorySSAScanLimit("dse-memoryssa-scanlimit", cl::init(100), cl::Hidden, - cl::desc("The number of memory instructions to scan for " - "dead store elimination (default = 100)")); - -static cl::opt MemorySSADefsPerBlockLimit( - "dse-memoryssa-defs-per-block-limit", cl::init(5000), cl::Hidden, - cl::desc("The number of MemoryDefs we consider as candidates to eliminated " - "other stores per basic block (default = 5000)")); - //===----------------------------------------------------------------------===// // Helper functions //===----------------------------------------------------------------------===// @@ -1367,490 +1354,22 @@ static bool eliminateDeadStores(Function &F, AliasAnalysis *AA, return MadeChange; } -namespace { -//============================================================================= -// MemorySSA backed dead store elimination. -// -// The code below implements dead store elimination using MemorySSA. It uses -// the following general approach: given a MemoryDef, walk upwards to find -// clobbering MemoryDefs that may be killed by the starting def. Then check -// that there are no uses that may read the location of the original MemoryDef -// in between both MemoryDefs. A bit more concretely: -// -// For all MemoryDefs StartDef: -// 1. Get the next dominating clobbering MemoryDef (DomAccess) by walking -// upwards. -// 2. Check that there are no reads between DomAccess and the StartDef by -// checking all uses starting at DomAccess and walking until we see StartDef. -// 3. For each found DomDef, check that: -// 1. There are no barrier instructions between DomDef and StartDef (like -// throws or stores with ordering constraints). -// 2. StartDef is executed whenever DomDef is executed. -// 3. StartDef completely overwrites DomDef. -// 4. Erase DomDef from the function and MemorySSA. - -// Returns true if \p M is an intrisnic that does not read or write memory. -bool isNoopIntrinsic(MemoryUseOrDef *M) { - if (const IntrinsicInst *II = dyn_cast(M->getMemoryInst())) { - switch (II->getIntrinsicID()) { - case Intrinsic::lifetime_start: - case Intrinsic::lifetime_end: - case Intrinsic::invariant_end: - case Intrinsic::launder_invariant_group: - case Intrinsic::assume: - return true; - case Intrinsic::dbg_addr: - case Intrinsic::dbg_declare: - case Intrinsic::dbg_label: - case Intrinsic::dbg_value: - llvm_unreachable("Intrinsic should not be modeled in MemorySSA"); - default: - return false; - } - } - return false; -} - -// Check if we can ignore \p D for DSE. -bool canSkipDef(MemoryDef *D, bool DefVisibleToCaller) { - Instruction *DI = D->getMemoryInst(); - // Calls that only access inaccessible memory cannot read or write any memory - // locations we consider for elimination. - if (auto CS = CallSite(DI)) - if (CS.onlyAccessesInaccessibleMemory()) - return true; - - // We can eliminate stores to locations not visible to the caller across - // throwing instructions. - if (DI->mayThrow() && !DefVisibleToCaller) - return true; - - // We can remove the dead stores, irrespective of the fence and its ordering - // (release/acquire/seq_cst). Fences only constraints the ordering of - // already visible stores, it does not make a store visible to other - // threads. So, skipping over a fence does not change a store from being - // dead. - if (isa(DI)) - return true; - - // Skip intrinsics that do not really read or modify memory. - if (isNoopIntrinsic(D)) - return true; - - return false; -} - -struct DSEState { - Function &F; - AliasAnalysis &AA; - MemorySSA &MSSA; - DominatorTree &DT; - PostDominatorTree &PDT; - const TargetLibraryInfo &TLI; - - // All MemoryDefs that potentially could kill other MemDefs. - SmallVector MemDefs; - // Any that should be skipped as they are already deleted - SmallPtrSet SkipStores; - // Keep track of all of the objects that are invisible to the caller until the - // function returns. - SmallPtrSet InvisibleToCaller; - // Keep track of blocks with throwing instructions not modeled in MemorySSA. - SmallPtrSet ThrowingBlocks; - - DSEState(Function &F, AliasAnalysis &AA, MemorySSA &MSSA, DominatorTree &DT, - PostDominatorTree &PDT, const TargetLibraryInfo &TLI) - : F(F), AA(AA), MSSA(MSSA), DT(DT), PDT(PDT), TLI(TLI) {} - - static DSEState get(Function &F, AliasAnalysis &AA, MemorySSA &MSSA, - DominatorTree &DT, PostDominatorTree &PDT, - const TargetLibraryInfo &TLI) { - DSEState State(F, AA, MSSA, DT, PDT, TLI); - // Collect blocks with throwing instructions not modeled in MemorySSA and - // alloc-like objects. - for (Instruction &I : instructions(F)) { - if (I.mayThrow() && !MSSA.getMemoryAccess(&I)) - State.ThrowingBlocks.insert(I.getParent()); - - auto *MD = dyn_cast_or_null(MSSA.getMemoryAccess(&I)); - if (MD && State.MemDefs.size() < MemorySSADefsPerBlockLimit && - hasAnalyzableMemoryWrite(&I, TLI) && isRemovable(&I)) - State.MemDefs.push_back(MD); - - // Track alloca and alloca-like objects. Here we care about objects not - // visible to the caller during function execution. Alloca objects are - // invalid in the caller, for alloca-like objects we ensure that they are - // not captured throughout the function. - if (isa(&I) || - (isAllocLikeFn(&I, &TLI) && !PointerMayBeCaptured(&I, false, true))) - State.InvisibleToCaller.insert(&I); - } - // Treat byval or inalloca arguments the same as Allocas, stores to them are - // dead at the end of the function. - for (Argument &AI : F.args()) - if (AI.hasByValOrInAllocaAttr()) - State.InvisibleToCaller.insert(&AI); - return State; - } - - Optional getLocForWriteEx(Instruction *I) const { - if (!I->mayWriteToMemory()) - return None; - - if (auto *MTI = dyn_cast(I)) - return {MemoryLocation::getForDest(MTI)}; - - if (auto CS = CallSite(I)) { - if (Function *F = CS.getCalledFunction()) { - StringRef FnName = F->getName(); - if (TLI.has(LibFunc_strcpy) && FnName == TLI.getName(LibFunc_strcpy)) - return {MemoryLocation(CS.getArgument(0))}; - if (TLI.has(LibFunc_strncpy) && FnName == TLI.getName(LibFunc_strncpy)) - return {MemoryLocation(CS.getArgument(0))}; - if (TLI.has(LibFunc_strcat) && FnName == TLI.getName(LibFunc_strcat)) - return {MemoryLocation(CS.getArgument(0))}; - if (TLI.has(LibFunc_strncat) && FnName == TLI.getName(LibFunc_strncat)) - return {MemoryLocation(CS.getArgument(0))}; - } - return None; - } - - return MemoryLocation::getOrNone(I); - } - - /// Returns true if \p Use completely overwrites \p DefLoc. - bool isCompleteOverwrite(MemoryLocation DefLoc, Instruction *UseInst) const { - // UseInst has a MemoryDef associated in MemorySSA. It's possible for a - // MemoryDef to not write to memory, e.g. a volatile load is modeled as a - // MemoryDef. - if (!UseInst->mayWriteToMemory()) - return false; - - if (auto CS = CallSite(UseInst)) - if (CS.onlyAccessesInaccessibleMemory()) - return false; - - ModRefInfo MR = AA.getModRefInfo(UseInst, DefLoc); - // If necessary, perform additional analysis. - if (isModSet(MR)) - MR = AA.callCapturesBefore(UseInst, DefLoc, &DT); - - Optional UseLoc = getLocForWriteEx(UseInst); - return isModSet(MR) && isMustSet(MR) && - UseLoc->Size.getValue() >= DefLoc.Size.getValue(); - } - - /// Returns true if \p Use may read from \p DefLoc. - bool isReadClobber(MemoryLocation DefLoc, Instruction *UseInst) const { - if (!UseInst->mayReadFromMemory()) - return false; - - if (auto CS = CallSite(UseInst)) - if (CS.onlyAccessesInaccessibleMemory()) - return false; - - ModRefInfo MR = AA.getModRefInfo(UseInst, DefLoc); - // If necessary, perform additional analysis. - if (isRefSet(MR)) - MR = AA.callCapturesBefore(UseInst, DefLoc, &DT); - return isRefSet(MR); - } - - // Find a MemoryDef writing to \p DefLoc and dominating \p Current, with no - // read access in between or return None otherwise. The returned value may not - // (completely) overwrite \p DefLoc. Currently we bail out when we encounter - // any of the following - // * An aliasing MemoryUse (read). - // * A MemoryPHI. - Optional getDomMemoryDef(MemoryDef *KillingDef, - MemoryAccess *Current, - MemoryLocation DefLoc, - bool DefVisibleToCaller, - int &ScanLimit) const { - MemoryDef *DomDef; - MemoryAccess *StartDef = Current; - bool StepAgain; - LLVM_DEBUG(dbgs() << " trying to get dominating access for " << *Current - << "\n"); - // Find the next clobbering Mod access for DefLoc, starting at Current. - do { - StepAgain = false; - // Reached TOP. - if (MSSA.isLiveOnEntryDef(Current)) - return None; - - MemoryUseOrDef *CurrentUD = dyn_cast(Current); - if (!CurrentUD) - return None; - - // Look for access that clobber DefLoc. - MemoryAccess *DomAccess = - MSSA.getSkipSelfWalker()->getClobberingMemoryAccess( - CurrentUD->getDefiningAccess(), DefLoc); - DomDef = dyn_cast(DomAccess); - if (!DomDef || MSSA.isLiveOnEntryDef(DomDef)) - return None; - - // Check if we can skip DomDef for DSE. We also require the KillingDef - // execute whenever DomDef executes and use post-dominance to ensure that. - if (canSkipDef(DomDef, DefVisibleToCaller) || - !PDT.dominates(KillingDef->getBlock(), DomDef->getBlock())) { - StepAgain = true; - Current = DomDef; - } - - } while (StepAgain); - - LLVM_DEBUG(dbgs() << " Checking for reads of " << *DomDef << " (" - << *DomDef->getMemoryInst() << ")\n"); - - SmallSetVector WorkList; - auto PushMemUses = [&WorkList](MemoryAccess *Acc) { - for (Use &U : Acc->uses()) - WorkList.insert(cast(U.getUser())); - }; - PushMemUses(DomDef); - - // Check if DomDef may be read. - for (unsigned I = 0; I < WorkList.size(); I++) { - MemoryAccess *UseAccess = WorkList[I]; - - LLVM_DEBUG(dbgs() << " Checking use " << *UseAccess); - if (--ScanLimit == 0) { - LLVM_DEBUG(dbgs() << " ... hit scan limit\n"); - return None; - } - - // Bail out on MemoryPhis for now. - if (isa(UseAccess)) { - LLVM_DEBUG(dbgs() << " ... hit MemoryPhi\n"); - return None; - } - - Instruction *UseInst = cast(UseAccess)->getMemoryInst(); - LLVM_DEBUG(dbgs() << " (" << *UseInst << ")\n"); - - if (isNoopIntrinsic(cast(UseAccess))) { - PushMemUses(UseAccess); - continue; - } - - // Uses which may read the original MemoryDef mean we cannot eliminate the - // original MD. Stop walk. - if (isReadClobber(DefLoc, UseInst)) { - LLVM_DEBUG(dbgs() << " ... found read clobber\n"); - return None; - } - - if (StartDef == UseAccess) - continue; - - // Check all uses for MemoryDefs, except for defs completely overwriting - // the original location. Otherwise we have to check uses of *all* - // MemoryDefs we discover, including non-aliasing ones. Otherwise we might - // miss cases like the following - // 1 = Def(LoE) ; <----- DomDef stores [0,1] - // 2 = Def(1) ; (2, 1) = NoAlias, stores [2,3] - // Use(2) ; MayAlias 2 *and* 1, loads [0, 3]. - // (The Use points to the *first* Def it may alias) - // 3 = Def(1) ; <---- Current (3, 2) = NoAlias, (3,1) = MayAlias, - // stores [0,1] - if (MemoryDef *UseDef = dyn_cast(UseAccess)) { - if (!isCompleteOverwrite(DefLoc, UseInst)) - PushMemUses(UseDef); - } - } - - // No aliasing MemoryUses of DomDef found, DomDef is potentially dead. - return {DomDef}; - } - - // Delete dead memory defs - void deleteDeadInstruction(Instruction *SI) { - MemorySSAUpdater Updater(&MSSA); - SmallVector NowDeadInsts; - NowDeadInsts.push_back(SI); - --NumFastOther; - - while (!NowDeadInsts.empty()) { - Instruction *DeadInst = NowDeadInsts.pop_back_val(); - ++NumFastOther; - - // Try to preserve debug information attached to the dead instruction. - salvageDebugInfo(*DeadInst); - - // Remove the Instruction from MSSA. - if (MemoryAccess *MA = MSSA.getMemoryAccess(DeadInst)) { - Updater.removeMemoryAccess(MA); - if (MemoryDef *MD = dyn_cast(MA)) { - SkipStores.insert(MD); - } - } - - // Remove its operands - for (Use &O : DeadInst->operands()) - if (Instruction *OpI = dyn_cast(O)) { - O = nullptr; - if (isInstructionTriviallyDead(OpI, &TLI)) - NowDeadInsts.push_back(OpI); - } - - DeadInst->eraseFromParent(); - } - } - - // Check for any extra throws between SI and NI that block DSE. This only - // checks extra maythrows (those that aren't MemoryDef's). MemoryDef that may - // throw are handled during the walk from one def to the next. - bool mayThrowBetween(Instruction *SI, Instruction *NI, - const Value *SILocUnd) const { - // First see if we can ignore it by using the fact that SI is an - // alloca/alloca like object that is not visible to the caller during - // execution of the function. - if (SILocUnd && InvisibleToCaller.count(SILocUnd)) - return false; - - if (SI->getParent() == NI->getParent()) - return ThrowingBlocks.find(SI->getParent()) != ThrowingBlocks.end(); - return !ThrowingBlocks.empty(); - } - - // Check if \p NI acts as a DSE barrier for \p SI. The following instructions - // act as barriers: - // * A memory instruction that may throw and \p SI accesses a non-stack - // object. - // * Atomic stores stronger that monotonic. - bool isDSEBarrier(Instruction *SI, MemoryLocation &SILoc, - const Value *SILocUnd, Instruction *NI, - MemoryLocation &NILoc) const { - // If NI may throw it acts as a barrier, unless we are to an alloca/alloca - // like object that does not escape. - if (NI->mayThrow() && !InvisibleToCaller.count(SILocUnd)) - return true; - - if (NI->isAtomic()) { - if (auto *NSI = dyn_cast(NI)) { - if (isStrongerThanMonotonic(NSI->getOrdering())) - return true; - } else - llvm_unreachable( - "Other instructions should be modeled/skipped in MemorySSA"); - } - - return false; - } -}; - -bool eliminateDeadStoresMemorySSA(Function &F, AliasAnalysis &AA, - MemorySSA &MSSA, DominatorTree &DT, - PostDominatorTree &PDT, - const TargetLibraryInfo &TLI) { - const DataLayout &DL = F.getParent()->getDataLayout(); - bool MadeChange = false; - - DSEState State = DSEState::get(F, AA, MSSA, DT, PDT, TLI); - // For each store: - for (unsigned I = 0; I < State.MemDefs.size(); I++) { - MemoryDef *Current = State.MemDefs[I]; - if (State.SkipStores.count(Current)) - continue; - Instruction *SI = cast(Current)->getMemoryInst(); - auto MaybeSILoc = State.getLocForWriteEx(SI); - if (!MaybeSILoc) { - LLVM_DEBUG(dbgs() << "Failed to find analyzable write location for " - << *SI << "\n"); - continue; - } - MemoryLocation SILoc = *MaybeSILoc; - assert(SILoc.Ptr && "SILoc should not be null"); - const Value *SILocUnd = GetUnderlyingObject(SILoc.Ptr, DL); - Instruction *DefObj = - const_cast(dyn_cast(SILocUnd)); - bool DefVisibleToCaller = !State.InvisibleToCaller.count(SILocUnd); - if (DefObj && ((isAllocLikeFn(DefObj, &TLI) && - !PointerMayBeCapturedBefore(DefObj, false, true, SI, &DT)))) - DefVisibleToCaller = false; - - LLVM_DEBUG(dbgs() << "Trying to eliminate MemoryDefs killed by " << *SI - << "\n"); - - int ScanLimit = MemorySSAScanLimit; - MemoryDef *StartDef = Current; - // Walk MemorySSA upward to find MemoryDefs that might be killed by SI. - while (Optional Next = State.getDomMemoryDef( - StartDef, Current, SILoc, DefVisibleToCaller, ScanLimit)) { - MemoryAccess *DomAccess = *Next; - LLVM_DEBUG(dbgs() << " Checking if we can kill " << *DomAccess << "\n"); - MemoryDef *NextDef = dyn_cast(DomAccess); - Instruction *NI = NextDef->getMemoryInst(); - LLVM_DEBUG(dbgs() << " def " << *NI << "\n"); - - if (!hasAnalyzableMemoryWrite(NI, TLI)) - break; - MemoryLocation NILoc = *State.getLocForWriteEx(NI); - // Check for anything that looks like it will be a barrier to further - // removal - if (State.isDSEBarrier(SI, SILoc, SILocUnd, NI, NILoc)) { - LLVM_DEBUG(dbgs() << " stop, barrier\n"); - break; - } - - // Before we try to remove anything, check for any extra throwing - // instructions that block us from DSEing - if (State.mayThrowBetween(SI, NI, SILocUnd)) { - LLVM_DEBUG(dbgs() << " stop, may throw!\n"); - break; - } - - // Check if NI overwrites SI. - int64_t InstWriteOffset, DepWriteOffset; - InstOverlapIntervalsTy IOL; - OverwriteResult OR = isOverwrite(SILoc, NILoc, DL, TLI, DepWriteOffset, - InstWriteOffset, NI, IOL, AA, &F); - - if (OR == OW_Complete) { - LLVM_DEBUG(dbgs() << "DSE: Remove Dead Store:\n DEAD: " << *NI - << "\n KILLER: " << *SI << '\n'); - State.deleteDeadInstruction(NI); - ++NumFastStores; - MadeChange = true; - } else - Current = NextDef; - } - } - - return MadeChange; -} -} // end anonymous namespace - //===----------------------------------------------------------------------===// // DSE Pass //===----------------------------------------------------------------------===// PreservedAnalyses DSEPass::run(Function &F, FunctionAnalysisManager &AM) { - AliasAnalysis &AA = AM.getResult(F); - const TargetLibraryInfo &TLI = AM.getResult(F); - DominatorTree &DT = AM.getResult(F); - - if (EnableMemorySSA) { - MemorySSA &MSSA = AM.getResult(F).getMSSA(); - PostDominatorTree &PDT = AM.getResult(F); - - if (!eliminateDeadStoresMemorySSA(F, AA, MSSA, DT, PDT, TLI)) - return PreservedAnalyses::all(); - } else { - MemoryDependenceResults &MD = AM.getResult(F); + AliasAnalysis *AA = &AM.getResult(F); + DominatorTree *DT = &AM.getResult(F); + MemoryDependenceResults *MD = &AM.getResult(F); + const TargetLibraryInfo *TLI = &AM.getResult(F); - if (!eliminateDeadStores(F, &AA, &MD, &DT, &TLI)) - return PreservedAnalyses::all(); - } + if (!eliminateDeadStores(F, AA, MD, DT, TLI)) + return PreservedAnalyses::all(); PreservedAnalyses PA; PA.preserveSet(); PA.preserve(); - if (EnableMemorySSA) - PA.preserve(); - else - PA.preserve(); + PA.preserve(); return PA; } @@ -1869,42 +1388,25 @@ public: if (skipFunction(F)) return false; - AliasAnalysis &AA = getAnalysis().getAAResults(); - DominatorTree &DT = getAnalysis().getDomTree(); - const TargetLibraryInfo &TLI = - getAnalysis().getTLI(F); - - if (EnableMemorySSA) { - MemorySSA &MSSA = getAnalysis().getMSSA(); - PostDominatorTree &PDT = - getAnalysis().getPostDomTree(); - - return eliminateDeadStoresMemorySSA(F, AA, MSSA, DT, PDT, TLI); - } else { - MemoryDependenceResults &MD = - getAnalysis().getMemDep(); + DominatorTree *DT = &getAnalysis().getDomTree(); + AliasAnalysis *AA = &getAnalysis().getAAResults(); + MemoryDependenceResults *MD = + &getAnalysis().getMemDep(); + const TargetLibraryInfo *TLI = + &getAnalysis().getTLI(F); - return eliminateDeadStores(F, &AA, &MD, &DT, &TLI); - } + return eliminateDeadStores(F, AA, MD, DT, TLI); } void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); + AU.addRequired(); AU.addRequired(); + AU.addRequired(); AU.addRequired(); - AU.addPreserved(); - AU.addRequired(); AU.addPreserved(); - - if (EnableMemorySSA) { - AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); - AU.addPreserved(); - } else { - AU.addRequired(); - AU.addPreserved(); - } + AU.addPreserved(); + AU.addPreserved(); } }; @@ -1915,10 +1417,8 @@ char DSELegacyPass::ID = 0; INITIALIZE_PASS_BEGIN(DSELegacyPass, "dse", "Dead Store Elimination", false, false) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) -INITIALIZE_PASS_DEPENDENCY(PostDominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) INITIALIZE_PASS_DEPENDENCY(GlobalsAAWrapperPass) -INITIALIZE_PASS_DEPENDENCY(MemorySSAWrapperPass) INITIALIZE_PASS_DEPENDENCY(MemoryDependenceWrapperPass) INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass) INITIALIZE_PASS_END(DSELegacyPass, "dse", "Dead Store Elimination", false, diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll index 0d84e9cf9d51..b9a0ea76d7fb 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/2011-09-06-EndOfFunction.ll @@ -1,4 +1,3 @@ -; XFAIL: * ; RUN: opt -dse -enable-dse-memoryssa -S < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreBegin.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreBegin.ll index 1028c8ed47f6..a7278d56e04c 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreBegin.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreBegin.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; XFAIL: * ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s define void @write4to7(i32* nocapture %p) { diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreEnd.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreEnd.ll index 0711855532fe..d8791aa5e930 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreEnd.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/OverwriteStoreEnd.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; XFAIL: * ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll index 9558033b37c7..b21183c1ac2b 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/atomic.ll @@ -1,4 +1,3 @@ -; XFAIL: * ; RUN: opt -basicaa -dse -enable-dse-memoryssa -S < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/calloc-store.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/calloc-store.ll index 397c5947ae5c..19ebaa93e7d3 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/calloc-store.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/calloc-store.ll @@ -1,5 +1,3 @@ -; XFAIL: * - ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s declare noalias i8* @calloc(i64, i64) diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll deleted file mode 100644 index 4ee295821e22..000000000000 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/fence-todo.ll +++ /dev/null @@ -1,50 +0,0 @@ -; XFAIL: * - -; RUN: opt -S -basicaa -dse -enable-dse-memoryssa < %s | FileCheck %s - -; We DSE stack alloc'ed and byval locations, in the presence of fences. -; Fence does not make an otherwise thread local store visible. -; Right now the DSE in presence of fence is only done in end blocks (with no successors), -; but the same logic applies to other basic blocks as well. -; The store to %addr.i can be removed since it is a byval attribute -define void @test3(i32* byval %addr.i) { -; CHECK-LABEL: @test3 -; CHECK-NOT: store -; CHECK: fence -; CHECK: ret - store i32 5, i32* %addr.i, align 4 - fence release - ret void -} - -declare void @foo(i8* nocapture %p) - -declare noalias i8* @malloc(i32) - -; DSE of stores in locations allocated through library calls. -define void @test_nocapture() { -; CHECK-LABEL: @test_nocapture -; CHECK: malloc -; CHECK: foo -; CHECK-NOT: store -; CHECK: fence - %m = call i8* @malloc(i32 24) - call void @foo(i8* %m) - store i8 4, i8* %m - fence release - ret void -} - - -; This is a full fence, but it does not make a thread local store visible. -; We can DSE the store in presence of the fence. -define void @fence_seq_cst() { -; CHECK-LABEL: @fence_seq_cst -; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: ret void - %P1 = alloca i32 - store i32 0, i32* %P1, align 4 - fence seq_cst - store i32 4, i32* %P1, align 4 - ret void -} diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/fence.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/fence.ll index b22fc9c92004..9b43d376b295 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/fence.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/fence.ll @@ -46,3 +46,51 @@ define void @test2(i32* %addr.i) { store i32 5, i32* %addr.i, align 4 ret void } + +; We DSE stack alloc'ed and byval locations, in the presence of fences. +; Fence does not make an otherwise thread local store visible. +; Right now the DSE in presence of fence is only done in end blocks (with no successors), +; but the same logic applies to other basic blocks as well. +; The store to %addr.i can be removed since it is a byval attribute +define void @test3(i32* byval %addr.i) { +; CHECK-LABEL: @test3 +; CHECK-NOT: store +; CHECK: fence +; CHECK: ret + store i32 5, i32* %addr.i, align 4 + fence release + ret void +} + +declare void @foo(i8* nocapture %p) + +declare noalias i8* @malloc(i32) + +; DSE of stores in locations allocated through library calls. +define void @test_nocapture() { +; CHECK-LABEL: @test_nocapture +; CHECK: malloc +; CHECK: foo +; CHECK-NOT: store +; CHECK: fence + %m = call i8* @malloc(i32 24) + call void @foo(i8* %m) + store i8 4, i8* %m + fence release + ret void +} + + +; This is a full fence, but it does not make a thread local store visible. +; We can DSE the store in presence of the fence. +define void @fence_seq_cst() { +; CHECK-LABEL: @fence_seq_cst +; CHECK-NEXT: fence seq_cst +; CHECK-NEXT: ret void + %P1 = alloca i32 + store i32 0, i32* %P1, align 4 + fence seq_cst + store i32 4, i32* %P1, align 4 + ret void +} + diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/free.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/free.ll index a6e47d7bb107..a9a32348cb6b 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/free.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/free.ll @@ -1,5 +1,3 @@ -; XFAIL: * - ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s target datalayout = "e-p:64:64:64" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/inst-limits.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/inst-limits.ll index 638571f6f417..78fe292d0cf5 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/inst-limits.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/inst-limits.ll @@ -1,9 +1,10 @@ ; RUN: opt -S -dse -enable-dse-memoryssa < %s | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" -; This test is not relevant for DSE with MemorySSA. Non-memory instructions -; are ignored anyways. The limits for the MemorySSA traversal are tested in -; llvm/test/Transforms/DeadStoreElimination/MSSA/memoryssa-scan-limit.ll +; If there are two stores to the same location, DSE should be able to remove +; the first store if the two stores are separated by no more than 98 +; instructions. The existence of debug intrinsics between the stores should +; not affect this instruction limit. @x = global i32 0, align 4 @@ -128,7 +129,7 @@ entry: define i32 @test_outside_limit() { entry: ; The first store; later there is a second store to the same location - ; CHECK-NOT: store i32 1, i32* @x, align 4 + ; CHECK: store i32 1, i32* @x, align 4 store i32 1, i32* @x, align 4 ; Insert 99 dummy instructions between the two stores; this is diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/lifetime.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/lifetime.ll index e4d4722677a7..3b3f4d498e9f 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/lifetime.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/lifetime.ll @@ -1,5 +1,3 @@ -; XFAIL: * - ; RUN: opt -S -basicaa -dse -enable-dse-memoryssa < %s | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/mda-with-dbg-values.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/mda-with-dbg-values.ll index 06bcc346a435..52e2ecdc7290 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/mda-with-dbg-values.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/mda-with-dbg-values.ll @@ -1,12 +1,13 @@ -; RUN: opt -S -dse -enable-dse-memoryssa -dse-memoryssa-scanlimit=2 < %s | FileCheck %s -; RUN: opt -S -strip-debug -dse -enable-dse-memoryssa -dse-memoryssa-scanlimit=2 < %s | FileCheck %s +; RUN: opt -S -dse -enable-dse-memoryssa -memdep-block-scan-limit=3 < %s | FileCheck %s +; RUN: opt -S -strip-debug -dse -enable-dse-memoryssa -memdep-block-scan-limit=3 < %s | FileCheck %s -; Test case to check that DSE gets the same result even if we have a dbg value -; between the memcpy. +; Test case to check that the memory dependency analysis gets the same +; result even if we have a dbg value between the memcpy and +; store. The memory dependency is then used by DSE to remove the store. -; This test case is less relevant for the MemorySSA backed version of DSE, as -; debug values are not modeled in MemorySSA and are skipped regardless of the -; exploration limit. +; We use -memdep-block-scan-limit=3 to be able to create a small test case. +; Without it, we would need to squeeze in 100 instructions since the default +; limit is 100. target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -19,11 +20,6 @@ entry: %i = alloca i8, align 1 store i8 1, i8* %i, align 1, !dbg !19 call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 - call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 - call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 - call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 - call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 - call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !17, metadata !DIExpression()), !dbg !18 %0 = bitcast [1 x i8]* @g to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %i, i8* %0, i64 1, i1 false), !dbg !20 br label %bb2 diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/memcpy-complete-overwrite.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/memcpy-complete-overwrite.ll index 931597265e41..38cb8a38511b 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/memcpy-complete-overwrite.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/memcpy-complete-overwrite.ll @@ -1,6 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py - -; XFAIL: * ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s ; RUN: opt < %s -aa-pipeline=basic-aa -passes=dse -enable-dse-memoryssa -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/memintrinsics.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/memintrinsics.ll index c22ad19198b4..51c45c32d8c5 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/memintrinsics.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/memintrinsics.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; XFAIL: * ; RUN: opt -S -dse -enable-dse-memoryssa < %s | FileCheck %s declare void @llvm.memcpy.p0i8.p0i8.i8(i8* nocapture, i8* nocapture, i8, i1) nounwind diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/memoryssa-scan-limit.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/memoryssa-scan-limit.ll deleted file mode 100644 index 43a9f0c92f1b..000000000000 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/memoryssa-scan-limit.ll +++ /dev/null @@ -1,72 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck --check-prefix=NO-LIMIT %s -; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -dse-memoryssa-scanlimit=0 -S | FileCheck --check-prefix=LIMIT-0 %s -; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -dse-memoryssa-scanlimit=3 -S | FileCheck --check-prefix=LIMIT-3 %s -; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -dse-memoryssa-scanlimit=4 -S | FileCheck --check-prefix=LIMIT-4 %s - -target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" - - -define void @test2(i32* noalias %P, i32* noalias %Q, i32* noalias %R) { -; -; NO-LIMIT-LABEL: @test2( -; NO-LIMIT-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] -; NO-LIMIT: bb1: -; NO-LIMIT-NEXT: br label [[BB3:%.*]] -; NO-LIMIT: bb2: -; NO-LIMIT-NEXT: br label [[BB3]] -; NO-LIMIT: bb3: -; NO-LIMIT-NEXT: store i32 0, i32* [[Q:%.*]] -; NO-LIMIT-NEXT: store i32 0, i32* [[R:%.*]] -; NO-LIMIT-NEXT: store i32 0, i32* [[P:%.*]] -; NO-LIMIT-NEXT: ret void -; -; LIMIT-0-LABEL: @test2( -; LIMIT-0-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] -; LIMIT-0: bb1: -; LIMIT-0-NEXT: br label [[BB3:%.*]] -; LIMIT-0: bb2: -; LIMIT-0-NEXT: br label [[BB3]] -; LIMIT-0: bb3: -; LIMIT-0-NEXT: store i32 0, i32* [[Q:%.*]] -; LIMIT-0-NEXT: store i32 0, i32* [[R:%.*]] -; LIMIT-0-NEXT: store i32 0, i32* [[P:%.*]] -; LIMIT-0-NEXT: ret void -; -; LIMIT-3-LABEL: @test2( -; LIMIT-3-NEXT: store i32 1, i32* [[P:%.*]] -; LIMIT-3-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] -; LIMIT-3: bb1: -; LIMIT-3-NEXT: br label [[BB3:%.*]] -; LIMIT-3: bb2: -; LIMIT-3-NEXT: br label [[BB3]] -; LIMIT-3: bb3: -; LIMIT-3-NEXT: store i32 0, i32* [[Q:%.*]] -; LIMIT-3-NEXT: store i32 0, i32* [[R:%.*]] -; LIMIT-3-NEXT: store i32 0, i32* [[P]] -; LIMIT-3-NEXT: ret void -; -; LIMIT-4-LABEL: @test2( -; LIMIT-4-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] -; LIMIT-4: bb1: -; LIMIT-4-NEXT: br label [[BB3:%.*]] -; LIMIT-4: bb2: -; LIMIT-4-NEXT: br label [[BB3]] -; LIMIT-4: bb3: -; LIMIT-4-NEXT: store i32 0, i32* [[Q:%.*]] -; LIMIT-4-NEXT: store i32 0, i32* [[R:%.*]] -; LIMIT-4-NEXT: store i32 0, i32* [[P:%.*]] -; LIMIT-4-NEXT: ret void -; - store i32 1, i32* %P - br i1 true, label %bb1, label %bb2 -bb1: - br label %bb3 -bb2: - br label %bb3 -bb3: - store i32 0, i32* %Q - store i32 0, i32* %R - store i32 0, i32* %P - ret void -} diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/memset-and-memcpy.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/memset-and-memcpy.ll index c142ea6cf8de..be4574e54cb1 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/memset-and-memcpy.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/memset-and-memcpy.ll @@ -59,7 +59,8 @@ define void @test17_atomic_weaker_2(i8* %P, i8* noalias %Q) nounwind ssp { ; Should not delete the volatile memset. define void @test17v(i8* %P, i8* %Q) nounwind ssp { ; CHECK-LABEL: @test17v( -; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[P:%.*]], i8* [[Q:%.*]], i64 12, i1 false) +; CHECK-NEXT: tail call void @llvm.memset.p0i8.i64(i8* [[P:%.*]], i8 42, i64 8, i1 true) +; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[P]], i8* [[Q:%.*]], i64 12, i1 false) ; CHECK-NEXT: ret void ; tail call void @llvm.memset.p0i8.i64(i8* %P, i8 42, i64 8, i1 true) @@ -73,7 +74,8 @@ define void @test17v(i8* %P, i8* %Q) nounwind ssp { ; Previously this was not allowed (PR8728), also discussed in PR11763. define void @test18(i8* %P, i8* %Q, i8* %R) nounwind ssp { ; CHECK-LABEL: @test18( -; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[P:%.*]], i8* [[R:%.*]], i64 12, i1 false) +; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[P:%.*]], i8* [[Q:%.*]], i64 12, i1 false) +; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[P]], i8* [[R:%.*]], i64 12, i1 false) ; CHECK-NEXT: ret void ; tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %P, i8* %Q, i64 12, i1 false) @@ -83,7 +85,8 @@ define void @test18(i8* %P, i8* %Q, i8* %R) nounwind ssp { define void @test18_atomic(i8* %P, i8* %Q, i8* %R) nounwind ssp { ; CHECK-LABEL: @test18_atomic( -; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 [[P:%.*]], i8* align 1 [[R:%.*]], i64 12, i32 1) +; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 [[P:%.*]], i8* align 1 [[Q:%.*]], i64 12, i32 1) +; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 [[P]], i8* align 1 [[R:%.*]], i64 12, i32 1) ; CHECK-NEXT: ret void ; tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %P, i8* align 1 %Q, i64 12, i32 1) diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/memset-missing-debugloc.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/memset-missing-debugloc.ll index d1aaab9a3d49..11d155c5fc1e 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/memset-missing-debugloc.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/memset-missing-debugloc.ll @@ -1,7 +1,6 @@ ; Test that the getelementptr generated when the dse pass determines that ; a memset can be shortened has the debugloc carried over from the memset. -; XFAIL: * ; RUN: opt -S -march=native -dse -enable-dse-memoryssa < %s| FileCheck %s ; CHECK: bitcast [5 x i64]* %{{[a-zA-Z_][a-zA-Z0-9_]*}} to i8*, !dbg ; CHECK-NEXT: %{{[0-9]+}} = getelementptr inbounds i8, i8* %0, i64 32, !dbg ![[DBG:[0-9]+]] diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores-big-endian.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores-big-endian.ll index 055f117c4b5c..8acc29f3f62e 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores-big-endian.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores-big-endian.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; XFAIL: * ; RUN: opt -dse -enable-dse-memoryssa -enable-dse-partial-store-merging -S < %s | FileCheck %s target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll index b09904e5a27d..feb1f31c99dd 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/merge-stores.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; XFAIL: * ; RUN: opt -dse -enable-dse-memoryssa -enable-dse-partial-store-merging -S < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-captures.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-captures.ll index c1f739234196..7caf48148156 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-captures.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-captures.ll @@ -25,6 +25,7 @@ define i8* @test_return_captures_1() { define i8* @test_return_captures_2() { ; CHECK-LABEL: @test_return_captures_2( ; CHECK-NEXT: [[M:%.*]] = call i8* @malloc(i64 24) +; CHECK-NEXT: store i8 0, i8* [[M]] ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: ; CHECK-NEXT: store i8 1, i8* [[M]] @@ -90,6 +91,7 @@ exit: define i8* @test_malloc_capture_3() { ; CHECK-LABEL: @test_malloc_capture_3( ; CHECK-NEXT: [[M:%.*]] = call i8* @malloc(i64 24) +; CHECK-NEXT: store i8 0, i8* [[M]] ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: ; CHECK-NEXT: store i8 1, i8* [[M]] @@ -189,6 +191,7 @@ exit: define i8* @test_malloc_capture_7() { ; CHECK-LABEL: @test_malloc_capture_7( ; CHECK-NEXT: [[M:%.*]] = call i8* @malloc(i64 24) +; CHECK-NEXT: store i8 0, i8* [[M]] ; CHECK-NEXT: call void @may_throw() ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: @@ -212,10 +215,10 @@ exit: define void @test_alloca_nocapture_1() { ; CHECK-LABEL: @test_alloca_nocapture_1( ; CHECK-NEXT: [[M:%.*]] = alloca i8 +; CHECK-NEXT: store i8 0, i8* [[M]] ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: -; CHECK-NEXT: store i8 1, i8* [[M]] ; CHECK-NEXT: ret void ; %m = alloca i8 @@ -237,7 +240,6 @@ define void @test_alloca_capture_1() { ; CHECK-NEXT: call void @capture(i8* [[M]]) ; CHECK-NEXT: br label [[EXIT:%.*]] ; CHECK: exit: -; CHECK-NEXT: store i8 1, i8* [[M]] ; CHECK-NEXT: ret void ; %m = alloca i8 @@ -260,7 +262,6 @@ define void @test_alloca_capture_2(%S1* %E) { ; CHECK: exit: ; CHECK-NEXT: [[F_PTR:%.*]] = getelementptr [[S1:%.*]], %S1* [[E:%.*]], i32 0, i32 0 ; CHECK-NEXT: store i8* [[M]], i8** [[F_PTR]] -; CHECK-NEXT: store i8 1, i8* [[M]] ; CHECK-NEXT: ret void ; %m = alloca i8 diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-exceptions.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-exceptions.ll index a719e273e227..41d4d019cb94 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-exceptions.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-exceptions.ll @@ -30,7 +30,6 @@ define void @test12(i32* %p) personality i32 (...)* @__CxxFrameHandler3 { ; CHECK-NEXT: [[C1:%.*]] = cleanuppad within none [] ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: -; CHECK-NEXT: store i32 40, i32* [[SV]] ; CHECK-NEXT: ret void ; block1: diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-loops.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-loops.ll index 1ec4434fb20a..bcf75e3860da 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-loops.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-loops.ll @@ -111,6 +111,7 @@ define void @test_loop(i32 %N, i32* noalias nocapture readonly %A, i32* noalias ; CHECK: for.body4.lr.ph: ; CHECK-NEXT: [[I_028:%.*]] = phi i32 [ [[INC11:%.*]], [[FOR_COND_CLEANUP3:%.*]] ], [ 0, [[FOR_BODY4_LR_PH_PREHEADER]] ] ; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i32 [[I_028]] +; CHECK-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 ; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[I_028]], [[N]] ; CHECK-NEXT: br label [[FOR_BODY4:%.*]] ; CHECK: for.body4: @@ -169,116 +170,3 @@ for.cond.cleanup3: ; preds = %for.body4 %exitcond29 = icmp eq i32 %inc11, %N br i1 %exitcond29, label %for.cond.cleanup, label %for.body4.lr.ph } - -declare i1 @cond() readnone - -; TODO: We can eliminate the store in for.header, but we currently hit a MemoryPhi. -define void @loop_multiple_def_uses(i32* noalias %P) { -; CHECK-LABEL: @loop_multiple_def_uses( -; CHECK-NEXT: entry: -; CHECK-NEXT: br label [[FOR_HEADER:%.*]] -; CHECK: for.header: -; CHECK-NEXT: store i32 1, i32* [[P:%.*]], align 4 -; CHECK-NEXT: [[C1:%.*]] = call i1 @cond() -; CHECK-NEXT: br i1 [[C1]], label [[FOR_BODY:%.*]], label [[END:%.*]] -; CHECK: for.body: -; CHECK-NEXT: store i32 1, i32* [[P]], align 4 -; CHECK-NEXT: [[LV:%.*]] = load i32, i32* [[P]] -; CHECK-NEXT: br label [[FOR_HEADER]] -; CHECK: end: -; CHECK-NEXT: store i32 3, i32* [[P]], align 4 -; CHECK-NEXT: ret void -; -entry: - br label %for.header - -for.header: - store i32 1, i32* %P, align 4 - %c1 = call i1 @cond() - br i1 %c1, label %for.body, label %end - -for.body: - store i32 1, i32* %P, align 4 - %lv = load i32, i32* %P - br label %for.header - -end: - store i32 3, i32* %P, align 4 - ret void -} - -; We cannot eliminate the store in for.header, as it is only partially -; overwritten in for.body and read afterwards. -define void @loop_multiple_def_uses_partial_write(i32* noalias %p) { -; CHECK-LABEL: @loop_multiple_def_uses_partial_write( -; CHECK-NEXT: entry: -; CHECK-NEXT: br label [[FOR_HEADER:%.*]] -; CHECK: for.header: -; CHECK-NEXT: store i32 1239491, i32* [[P:%.*]], align 4 -; CHECK-NEXT: [[C1:%.*]] = call i1 @cond() -; CHECK-NEXT: br i1 [[C1]], label [[FOR_BODY:%.*]], label [[END:%.*]] -; CHECK: for.body: -; CHECK-NEXT: [[C:%.*]] = bitcast i32* [[P]] to i8* -; CHECK-NEXT: store i8 1, i8* [[C]], align 4 -; CHECK-NEXT: [[LV:%.*]] = load i32, i32* [[P]] -; CHECK-NEXT: br label [[FOR_HEADER]] -; CHECK: end: -; CHECK-NEXT: store i32 3, i32* [[P]], align 4 -; CHECK-NEXT: ret void -; -entry: - br label %for.header - -for.header: - store i32 1239491, i32* %p, align 4 - %c1 = call i1 @cond() - br i1 %c1, label %for.body, label %end - -for.body: - %c = bitcast i32* %p to i8* - store i8 1, i8* %c, align 4 - %lv = load i32, i32* %p - br label %for.header - -end: - store i32 3, i32* %p, align 4 - ret void -} - -; We cannot eliminate the store in for.header, as the location is not overwritten -; in for.body and read afterwards. -define void @loop_multiple_def_uses_mayalias_write(i32* %p, i32* %q) { - -; CHECK-LABEL: @loop_multiple_def_uses_mayalias_write( -; CHECK-NEXT: entry: -; CHECK-NEXT: br label [[FOR_HEADER:%.*]] -; CHECK: for.header: -; CHECK-NEXT: store i32 1239491, i32* [[P:%.*]], align 4 -; CHECK-NEXT: [[C1:%.*]] = call i1 @cond() -; CHECK-NEXT: br i1 [[C1]], label [[FOR_BODY:%.*]], label [[END:%.*]] -; CHECK: for.body: -; CHECK-NEXT: store i32 1, i32* [[Q:%.*]], align 4 -; CHECK-NEXT: [[LV:%.*]] = load i32, i32* [[P]] -; CHECK-NEXT: br label [[FOR_HEADER]] -; CHECK: end: -; CHECK-NEXT: store i32 3, i32* [[P]], align 4 -; CHECK-NEXT: ret void -; -entry: - br label %for.header - -for.header: - store i32 1239491, i32* %p, align 4 - %c1 = call i1 @cond() - br i1 %c1, label %for.body, label %end - -for.body: - store i32 1, i32* %q, align 4 - %lv = load i32, i32* %p - br label %for.header - -end: - store i32 3, i32* %p, align 4 - ret void -} - diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memoryphis.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memoryphis.ll index ce34986ff4e3..ddfc4d43d51a 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memoryphis.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-memoryphis.ll @@ -103,73 +103,3 @@ bb3: store i8 1, i8* %P2 ret void } - -declare void @hoge() - -; Check a function with a MemoryPhi with 3 incoming values. -define void @widget(i32* %Ptr, i1 %c1, i1 %c2, i32 %v1, i32 %v2, i32 %v3) { -; CHECK-LABEL: @widget( -; CHECK-NEXT: bb: -; CHECK-NEXT: tail call void @hoge() -; CHECK-NEXT: br i1 [[C1:%.*]], label [[BB3:%.*]], label [[BB1:%.*]] -; CHECK: bb1: -; CHECK-NEXT: br i1 [[C2:%.*]], label [[BB2:%.*]], label [[BB3]] -; CHECK: bb2: -; CHECK-NEXT: store i32 -1, i32* [[PTR:%.*]], align 4 -; CHECK-NEXT: br label [[BB3]] -; CHECK: bb3: -; CHECK-NEXT: br label [[BB4:%.*]] -; CHECK: bb4: -; CHECK-NEXT: switch i32 [[V1:%.*]], label [[BB8:%.*]] [ -; CHECK-NEXT: i32 0, label [[BB5:%.*]] -; CHECK-NEXT: i32 1, label [[BB6:%.*]] -; CHECK-NEXT: i32 2, label [[BB7:%.*]] -; CHECK-NEXT: ] -; CHECK: bb5: -; CHECK-NEXT: store i32 0, i32* [[PTR]], align 4 -; CHECK-NEXT: br label [[BB8]] -; CHECK: bb6: -; CHECK-NEXT: store i32 1, i32* [[PTR]], align 4 -; CHECK-NEXT: br label [[BB8]] -; CHECK: bb7: -; CHECK-NEXT: store i32 2, i32* [[PTR]], align 4 -; CHECK-NEXT: br label [[BB8]] -; CHECK: bb8: -; CHECK-NEXT: br label [[BB4]] -; -bb: - tail call void @hoge() - br i1 %c1, label %bb3, label %bb1 - -bb1: ; preds = %bb - br i1 %c2, label %bb2, label %bb3 - -bb2: ; preds = %bb1 - store i32 -1, i32* %Ptr, align 4 - br label %bb3 - -bb3: ; preds = %bb2, %bb1, %bb - br label %bb4 - -bb4: ; preds = %bb8, %bb3 - switch i32 %v1, label %bb8 [ - i32 0, label %bb5 - i32 1, label %bb6 - i32 2, label %bb7 - ] - -bb5: ; preds = %bb4 - store i32 0, i32* %Ptr, align 4 - br label %bb8 - -bb6: ; preds = %bb4 - store i32 1, i32* %Ptr, align 4 - br label %bb8 - -bb7: ; preds = %bb4 - store i32 2, i32* %Ptr, align 4 - br label %bb8 - -bb8: ; preds = %bb7, %bb6, %bb5, %bb4 - br label %bb4 -} diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-partial.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-partial.ll index cbd7dae56da1..17bd8a6fcc87 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-partial.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-partial.ll @@ -32,13 +32,14 @@ bb3: define void @second_store_bigger(i32* noalias %P) { ; CHECK-LABEL: @second_store_bigger( +; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK: bb1: ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: bb2: ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb3: -; CHECK-NEXT: [[P_I64:%.*]] = bitcast i32* [[P:%.*]] to i64* +; CHECK-NEXT: [[P_I64:%.*]] = bitcast i32* [[P]] to i64* ; CHECK-NEXT: store i64 0, i64* [[P_I64]] ; CHECK-NEXT: ret void ; diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-simple.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-simple.ll index 520a6eaccf09..2b0227751b2a 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-simple.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/multiblock-simple.ll @@ -6,13 +6,14 @@ target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" define void @test2(i32* noalias %P) { ; CHECK-LABEL: @test2( +; CHECK-NEXT: store i32 1, i32* [[P:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK: bb1: ; CHECK-NEXT: br label [[BB3:%.*]] ; CHECK: bb2: ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb3: -; CHECK-NEXT: store i32 0, i32* [[P:%.*]] +; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: ret void ; store i32 1, i32* %P @@ -52,6 +53,7 @@ bb3: define void @test7(i32* noalias %P, i32* noalias %Q) { ; CHECK-LABEL: @test7( +; CHECK-NEXT: store i32 1, i32* [[Q:%.*]] ; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] ; CHECK: bb1: ; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[P:%.*]] @@ -59,7 +61,7 @@ define void @test7(i32* noalias %P, i32* noalias %Q) { ; CHECK: bb2: ; CHECK-NEXT: br label [[BB3]] ; CHECK: bb3: -; CHECK-NEXT: store i32 0, i32* [[Q:%.*]] +; CHECK-NEXT: store i32 0, i32* [[Q]] ; CHECK-NEXT: store i32 0, i32* [[P]] ; CHECK-NEXT: ret void ; @@ -112,38 +114,3 @@ bb3: store i32 0, i32* %P ret void } - -; We cannot eliminate `store i32 0, i32* %P`, as it is read by the later load. -; Make sure that we check the uses of `store i32 1, i32* %P.1 which does not -; alias %P. Note that uses point to the *first* def that may alias. -define void @overlapping_read(i32* %P) { -; CHECK-LABEL: @overlapping_read( -; CHECK-NEXT: store i32 0, i32* [[P:%.*]] -; CHECK-NEXT: [[P_1:%.*]] = getelementptr i32, i32* [[P]], i32 1 -; CHECK-NEXT: store i32 1, i32* [[P_1]] -; CHECK-NEXT: [[P_64:%.*]] = bitcast i32* [[P]] to i64* -; CHECK-NEXT: [[LV:%.*]] = load i64, i64* [[P_64]] -; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB2:%.*]] -; CHECK: bb1: -; CHECK-NEXT: br label [[BB3:%.*]] -; CHECK: bb2: -; CHECK-NEXT: ret void -; CHECK: bb3: -; CHECK-NEXT: store i32 2, i32* [[P]] -; CHECK-NEXT: ret void -; - store i32 0, i32* %P - %P.1 = getelementptr i32, i32* %P, i32 1 - store i32 1, i32* %P.1 - - %P.64 = bitcast i32* %P to i64* - %lv = load i64, i64* %P.64 - br i1 true, label %bb1, label %bb2 -bb1: - br label %bb3 -bb2: - ret void -bb3: - store i32 2, i32* %P - ret void -} diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/operand-bundles.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/operand-bundles.ll index 3a59286c53f2..9e88651bdb2e 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/operand-bundles.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/operand-bundles.ll @@ -1,4 +1,3 @@ -; XFAIL: * ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s declare noalias i8* @malloc(i64) "malloc-like" diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/simple-todo.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/simple-todo.ll index d0a3cef71a7e..b96cc9f33c20 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/simple-todo.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/simple-todo.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; XFAIL: * ; RUN: opt < %s -basicaa -dse -enable-dse-memoryssa -S | FileCheck %s ; RUN: opt < %s -aa-pipeline=basic-aa -passes=dse -enable-dse-memoryssa -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" @@ -10,6 +9,19 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) n declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind declare void @llvm.init.trampoline(i8*, i8*, i8*) +; PR8576 - Should delete store of 10 even though p/q are may aliases. +define void @test2(i32 *%p, i32 *%q) { +; CHECK-LABEL: @test2( +; CHECK-NEXT: store i32 20, i32* [[Q:%.*]], align 4 +; CHECK-NEXT: store i32 30, i32* [[P:%.*]], align 4 +; CHECK-NEXT: ret void +; + store i32 10, i32* %p, align 4 + store i32 20, i32* %q, align 4 + store i32 30, i32* %p, align 4 + ret void +} + define void @test5(i32* %Q) { ; CHECK-LABEL: @test5( ; CHECK-NEXT: [[A:%.*]] = load volatile i32, i32* [[Q:%.*]] @@ -20,6 +32,62 @@ define void @test5(i32* %Q) { ret void } +; Should delete store of 10 even though memset is a may-store to P (P and Q may +; alias). +define void @test6(i32 *%p, i8 *%q) { +; CHECK-LABEL: @test6( +; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[Q:%.*]], i8 42, i64 900, i1 false) +; CHECK-NEXT: store i32 30, i32* [[P:%.*]], align 4 +; CHECK-NEXT: ret void +; + store i32 10, i32* %p, align 4 ;; dead. + call void @llvm.memset.p0i8.i64(i8* %q, i8 42, i64 900, i1 false) + store i32 30, i32* %p, align 4 + ret void +} + +; Should delete store of 10 even though memset is a may-store to P (P and Q may +; alias). +define void @test6_atomic(i32* align 4 %p, i8* align 4 %q) { +; CHECK-LABEL: @test6_atomic( +; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 4 [[Q:%.*]], i8 42, i64 900, i32 4) +; CHECK-NEXT: store atomic i32 30, i32* [[P:%.*]] unordered, align 4 +; CHECK-NEXT: ret void +; + store atomic i32 10, i32* %p unordered, align 4 ;; dead. + call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 4 %q, i8 42, i64 900, i32 4) + store atomic i32 30, i32* %p unordered, align 4 + ret void +} + +; Should delete store of 10 even though memcpy is a may-store to P (P and Q may +; alias). +define void @test7(i32 *%p, i8 *%q, i8* noalias %r) { +; CHECK-LABEL: @test7( +; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[Q:%.*]], i8* [[R:%.*]], i64 900, i1 false) +; CHECK-NEXT: store i32 30, i32* [[P:%.*]], align 4 +; CHECK-NEXT: ret void +; + store i32 10, i32* %p, align 4 ;; dead. + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %q, i8* %r, i64 900, i1 false) + store i32 30, i32* %p, align 4 + ret void +} + +; Should delete store of 10 even though memcpy is a may-store to P (P and Q may +; alias). +define void @test7_atomic(i32* align 4 %p, i8* align 4 %q, i8* noalias align 4 %r) { +; CHECK-LABEL: @test7_atomic( +; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 4 [[Q:%.*]], i8* align 4 [[R:%.*]], i64 900, i32 4) +; CHECK-NEXT: store atomic i32 30, i32* [[P:%.*]] unordered, align 4 +; CHECK-NEXT: ret void +; + store atomic i32 10, i32* %p unordered, align 4 ;; dead. + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 4 %q, i8* align 4 %r, i64 900, i32 4) + store atomic i32 30, i32* %p unordered, align 4 + ret void +} + ; Do not delete stores that are only partially killed. define i32 @test8() { ; CHECK-LABEL: @test8( @@ -90,6 +158,46 @@ define void @test12({ i32, i32 }* %x) nounwind { } +; %P doesn't escape, the DEAD instructions should be removed. +declare void @test13f() +define i32* @test13() { +; CHECK-LABEL: @test13( +; CHECK-NEXT: [[PTR:%.*]] = tail call i8* @malloc(i32 4) +; CHECK-NEXT: [[P:%.*]] = bitcast i8* [[PTR]] to i32* +; CHECK-NEXT: call void @test13f() +; CHECK-NEXT: store i32 0, i32* [[P]] +; CHECK-NEXT: ret i32* [[P]] +; + %ptr = tail call i8* @malloc(i32 4) + %P = bitcast i8* %ptr to i32* + %DEAD = load i32, i32* %P + %DEAD2 = add i32 %DEAD, 1 + store i32 %DEAD2, i32* %P + call void @test13f( ) + store i32 0, i32* %P + ret i32* %P +} + +define i32 addrspace(1)* @test13_addrspacecast() { +; CHECK-LABEL: @test13_addrspacecast( +; CHECK-NEXT: [[P:%.*]] = tail call i8* @malloc(i32 4) +; CHECK-NEXT: [[P_BC:%.*]] = bitcast i8* [[P]] to i32* +; CHECK-NEXT: [[P:%.*]] = addrspacecast i32* [[P_BC]] to i32 addrspace(1)* +; CHECK-NEXT: call void @test13f() +; CHECK-NEXT: store i32 0, i32 addrspace(1)* [[P]] +; CHECK-NEXT: ret i32 addrspace(1)* [[P]] +; + %p = tail call i8* @malloc(i32 4) + %p.bc = bitcast i8* %p to i32* + %P = addrspacecast i32* %p.bc to i32 addrspace(1)* + %DEAD = load i32, i32 addrspace(1)* %P + %DEAD2 = add i32 %DEAD, 1 + store i32 %DEAD2, i32 addrspace(1)* %P + call void @test13f( ) + store i32 0, i32 addrspace(1)* %P + ret i32 addrspace(1)* %P +} + declare noalias i8* @malloc(i32) declare noalias i8* @calloc(i32, i32) @@ -133,6 +241,26 @@ define void @test22(i1 %i, i32 %k, i32 %m) nounwind { ret void } +; Make sure same sized store to later element is deleted +define void @test24([2 x i32]* %a, i32 %b, i32 %c) nounwind { +; CHECK-LABEL: @test24( +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A:%.*]], i64 0, i64 0 +; CHECK-NEXT: store i32 [[B:%.*]], i32* [[TMP1]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 1 +; CHECK-NEXT: store i32 [[C:%.*]], i32* [[TMP2]], align 4 +; CHECK-NEXT: ret void +; + %1 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 0 + store i32 0, i32* %1, align 4 + %2 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 1 + store i32 0, i32* %2, align 4 + %3 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 0 + store i32 %b, i32* %3, align 4 + %4 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 1 + store i32 %c, i32* %4, align 4 + ret void +} + ; Remove redundant store if loaded value is in another block. define i32 @test26(i1 %c, i32* %p) { ; CHECK-LABEL: @test26( @@ -183,6 +311,35 @@ bb3: declare void @unknown_func() +; Don't remove redundant store because of unknown call. +define i32 @test30(i1 %c, i32* %p, i32 %i) { +; CHECK-LABEL: @test30( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P:%.*]], align 4 +; CHECK-NEXT: br i1 [[C:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] +; CHECK: bb1: +; CHECK-NEXT: br label [[BB3:%.*]] +; CHECK: bb2: +; CHECK-NEXT: call void @unknown_func() +; CHECK-NEXT: br label [[BB3]] +; CHECK: bb3: +; CHECK-NEXT: store i32 [[V]], i32* [[P]], align 4 +; CHECK-NEXT: ret i32 0 +; +entry: + %v = load i32, i32* %p, align 4 + br i1 %c, label %bb1, label %bb2 +bb1: + br label %bb3 +bb2: + ; Might overwrite value at %p + call void @unknown_func() + br label %bb3 +bb3: + store i32 %v, i32* %p, align 4 + ret i32 0 +} + ; Remove redundant store if loaded value is in another block inside a loop. define i32 @test31(i1 %c, i32* %p, i32 %i) { ; CHECK-LABEL: @test31( diff --git a/llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll b/llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll index ef05504b30f8..b2c66f299459 100644 --- a/llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll +++ b/llvm/test/Transforms/DeadStoreElimination/MSSA/simple.ll @@ -50,76 +50,6 @@ define void @test4(i32* %Q) { ret void } -; PR8576 - Should delete store of 10 even though p/q are may aliases. -define void @test2(i32 *%p, i32 *%q) { -; CHECK-LABEL: @test2( -; CHECK-NEXT: store i32 20, i32* [[Q:%.*]], align 4 -; CHECK-NEXT: store i32 30, i32* [[P:%.*]], align 4 -; CHECK-NEXT: ret void -; - store i32 10, i32* %p, align 4 - store i32 20, i32* %q, align 4 - store i32 30, i32* %p, align 4 - ret void -} - -; Should delete store of 10 even though memset is a may-store to P (P and Q may -; alias). -define void @test6(i32 *%p, i8 *%q) { -; CHECK-LABEL: @test6( -; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[Q:%.*]], i8 42, i64 900, i1 false) -; CHECK-NEXT: store i32 30, i32* [[P:%.*]], align 4 -; CHECK-NEXT: ret void -; - store i32 10, i32* %p, align 4 ;; dead. - call void @llvm.memset.p0i8.i64(i8* %q, i8 42, i64 900, i1 false) - store i32 30, i32* %p, align 4 - ret void -} - -; Should delete store of 10 even though memset is a may-store to P (P and Q may -; alias). -define void @test6_atomic(i32* align 4 %p, i8* align 4 %q) { -; CHECK-LABEL: @test6_atomic( -; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 4 [[Q:%.*]], i8 42, i64 900, i32 4) -; CHECK-NEXT: store atomic i32 30, i32* [[P:%.*]] unordered, align 4 -; CHECK-NEXT: ret void -; - store atomic i32 10, i32* %p unordered, align 4 ;; dead. - call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 4 %q, i8 42, i64 900, i32 4) - store atomic i32 30, i32* %p unordered, align 4 - ret void -} - -; Should delete store of 10 even though memcpy is a may-store to P (P and Q may -; alias). -define void @test7(i32 *%p, i8 *%q, i8* noalias %r) { -; CHECK-LABEL: @test7( -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[Q:%.*]], i8* [[R:%.*]], i64 900, i1 false) -; CHECK-NEXT: store i32 30, i32* [[P:%.*]], align 4 -; CHECK-NEXT: ret void -; - store i32 10, i32* %p, align 4 ;; dead. - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %q, i8* %r, i64 900, i1 false) - store i32 30, i32* %p, align 4 - ret void -} - -; Should delete store of 10 even though memcpy is a may-store to P (P and Q may -; alias). -define void @test7_atomic(i32* align 4 %p, i8* align 4 %q, i8* noalias align 4 %r) { -; CHECK-LABEL: @test7_atomic( -; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 4 [[Q:%.*]], i8* align 4 [[R:%.*]], i64 900, i32 4) -; CHECK-NEXT: store atomic i32 30, i32* [[P:%.*]] unordered, align 4 -; CHECK-NEXT: ret void -; - store atomic i32 10, i32* %p unordered, align 4 ;; dead. - call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 4 %q, i8* align 4 %r, i64 900, i32 4) - store atomic i32 30, i32* %p unordered, align 4 - ret void -} - - ; va_arg has fuzzy dependence, the store shouldn't be zapped. define double @test10(i8* %X) { ; CHECK-LABEL: @test10( @@ -134,46 +64,6 @@ define double @test10(i8* %X) { ret double %tmp.0 } -; %P doesn't escape, the DEAD instructions should be removed. -declare void @test13f() -define i32* @test13() { -; CHECK-LABEL: @test13( -; CHECK-NEXT: [[PTR:%.*]] = tail call i8* @malloc(i32 4) -; CHECK-NEXT: [[P:%.*]] = bitcast i8* [[PTR]] to i32* -; CHECK-NEXT: call void @test13f() -; CHECK-NEXT: store i32 0, i32* [[P]] -; CHECK-NEXT: ret i32* [[P]] -; - %ptr = tail call i8* @malloc(i32 4) - %P = bitcast i8* %ptr to i32* - %DEAD = load i32, i32* %P - %DEAD2 = add i32 %DEAD, 1 - store i32 %DEAD2, i32* %P - call void @test13f( ) - store i32 0, i32* %P - ret i32* %P -} - -define i32 addrspace(1)* @test13_addrspacecast() { -; CHECK-LABEL: @test13_addrspacecast( -; CHECK-NEXT: [[P:%.*]] = tail call i8* @malloc(i32 4) -; CHECK-NEXT: [[P_BC:%.*]] = bitcast i8* [[P]] to i32* -; CHECK-NEXT: [[P:%.*]] = addrspacecast i32* [[P_BC]] to i32 addrspace(1)* -; CHECK-NEXT: call void @test13f() -; CHECK-NEXT: store i32 0, i32 addrspace(1)* [[P]] -; CHECK-NEXT: ret i32 addrspace(1)* [[P]] -; - %p = tail call i8* @malloc(i32 4) - %p.bc = bitcast i8* %p to i32* - %P = addrspacecast i32* %p.bc to i32 addrspace(1)* - %DEAD = load i32, i32 addrspace(1)* %P - %DEAD2 = add i32 %DEAD, 1 - store i32 %DEAD2, i32 addrspace(1)* %P - call void @test13f( ) - store i32 0, i32 addrspace(1)* %P - ret i32 addrspace(1)* %P -} - declare noalias i8* @malloc(i32) declare noalias i8* @calloc(i32, i32) @@ -218,26 +108,6 @@ define noalias i8* @test23() nounwind uwtable ssp { ret i8* %call } -; Make sure same sized store to later element is deleted -define void @test24([2 x i32]* %a, i32 %b, i32 %c) nounwind { -; CHECK-LABEL: @test24( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A:%.*]], i64 0, i64 0 -; CHECK-NEXT: store i32 [[B:%.*]], i32* [[TMP1]], align 4 -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[A]], i64 0, i64 1 -; CHECK-NEXT: store i32 [[C:%.*]], i32* [[TMP2]], align 4 -; CHECK-NEXT: ret void -; - %1 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 0 - store i32 0, i32* %1, align 4 - %2 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 1 - store i32 0, i32* %2, align 4 - %3 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 0 - store i32 %b, i32* %3, align 4 - %4 = getelementptr inbounds [2 x i32], [2 x i32]* %a, i64 0, i64 1 - store i32 %c, i32* %4, align 4 - ret void -} - ; Check another case like PR13547 where strdup is not like malloc. define i8* @test25(i8* %p) nounwind { ; CHECK-LABEL: @test25( @@ -317,35 +187,6 @@ bb3: declare void @unknown_func() -; Don't remove redundant store because of unknown call. -define i32 @test30(i1 %c, i32* %p, i32 %i) { -; CHECK-LABEL: @test30( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[P:%.*]], align 4 -; CHECK-NEXT: br i1 [[C:%.*]], label [[BB1:%.*]], label [[BB2:%.*]] -; CHECK: bb1: -; CHECK-NEXT: br label [[BB3:%.*]] -; CHECK: bb2: -; CHECK-NEXT: call void @unknown_func() -; CHECK-NEXT: br label [[BB3]] -; CHECK: bb3: -; CHECK-NEXT: store i32 [[V]], i32* [[P]], align 4 -; CHECK-NEXT: ret i32 0 -; -entry: - %v = load i32, i32* %p, align 4 - br i1 %c, label %bb1, label %bb2 -bb1: - br label %bb3 -bb2: - ; Might overwrite value at %p - call void @unknown_func() - br label %bb3 -bb3: - store i32 %v, i32* %p, align 4 - ret i32 0 -} - ; Don't remove redundant store in a loop with a may-alias store. define i32 @test32(i1 %c, i32* %p, i32 %i) { ; CHECK-LABEL: @test32( @@ -453,7 +294,8 @@ define void @test37_atomic(i8* %P, i8* %Q, i8* %R) { ; The memmove is dead, because memcpy arguments cannot overlap. define void @test38(i8* %P, i8* %Q, i8* %R) { ; CHECK-LABEL: @test38( -; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[P:%.*]], i8* [[R:%.*]], i64 12, i1 false) +; CHECK-NEXT: tail call void @llvm.memmove.p0i8.p0i8.i64(i8* [[P:%.*]], i8* [[Q:%.*]], i64 12, i1 false) +; CHECK-NEXT: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[P]], i8* [[R:%.*]], i64 12, i1 false) ; CHECK-NEXT: ret void ; @@ -465,7 +307,8 @@ define void @test38(i8* %P, i8* %Q, i8* %R) { ; The memmove is dead, because memcpy arguments cannot overlap. define void @test38_atomic(i8* %P, i8* %Q, i8* %R) { ; CHECK-LABEL: @test38_atomic( -; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 [[P:%.*]], i8* align 1 [[R:%.*]], i64 12, i32 1) +; CHECK-NEXT: tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 [[P:%.*]], i8* align 1 [[Q:%.*]], i64 12, i32 1) +; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 [[P]], i8* align 1 [[R:%.*]], i64 12, i32 1) ; CHECK-NEXT: ret void ; @@ -536,9 +379,7 @@ declare void @free(i8* nocapture) define void @test41(i32* noalias %P) { ; CHECK-LABEL: @test41( ; CHECK-NEXT: [[P2:%.*]] = bitcast i32* [[P:%.*]] to i8* -; CHECK-NEXT: store i32 1, i32* [[P]] ; CHECK-NEXT: call void @unknown_func() -; CHECK-NEXT: store i32 2, i32* [[P]] ; CHECK-NEXT: call void @free(i8* [[P2]]) ; CHECK-NEXT: ret void ; -- GitLab From db875f66554455f4957881d373987472b3071f65 Mon Sep 17 00:00:00 2001 From: Andrew Wei Date: Tue, 11 Feb 2020 22:42:45 +0800 Subject: [PATCH 007/142] [RISCV] Optimize seteq/setne pattern expansions for better code size ADDI(C.ADDI) may achieve better code size than XORI, since XORI has no C extension. This patch transforms two patterns and gets almost equivalent results. Differential Revision: https://reviews.llvm.org/D71774 --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 28 ++++++++++-- llvm/test/CodeGen/RISCV/i32-icmp.ll | 61 ++++++++++++++++++++++++- llvm/test/CodeGen/RISCV/setcc-logic.ll | 8 ++-- 3 files changed, 87 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 565fbdcfde69..71ab423cbbc9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -144,6 +144,20 @@ def simm12 : Operand, ImmLeaf(Imm);}]> { let OperandNamespace = "RISCVOp"; } +// A 12-bit signed immediate plus one where the imm range will be -2047~2048. +def simm12_plus1 : Operand, ImmLeaf(Imm) && Imm != -2048) || Imm == 2048;}]> { + let ParserMatchClass = SImmAsmOperand<12>; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeSImmOperand<12>"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048; + return MCOp.isBareSymbolRef(); + }]; +} + // A 13-bit signed immediate where the least significant bit is zero. def simm13_lsb0 : Operand { let ParserMatchClass = SImmAsmOperand<13, "Lsb0">; @@ -296,6 +310,12 @@ def HI20 : SDNodeXFormgetValueType(0)); }]>; +// Return the negation of an immediate value. +def NegImm : SDNodeXFormgetTargetConstant(-N->getSExtValue(), SDLoc(N), + N->getValueType(0)); +}]>; + //===----------------------------------------------------------------------===// // Instruction Formats //===----------------------------------------------------------------------===// @@ -857,12 +877,12 @@ def : PatGprSimm12; // handled by a RISC-V instruction. def : Pat<(seteq GPR:$rs1, 0), (SLTIU GPR:$rs1, 1)>; def : Pat<(seteq GPR:$rs1, GPR:$rs2), (SLTIU (XOR GPR:$rs1, GPR:$rs2), 1)>; -def : Pat<(seteq GPR:$rs1, simm12:$imm12), - (SLTIU (XORI GPR:$rs1, simm12:$imm12), 1)>; +def : Pat<(seteq GPR:$rs1, simm12_plus1:$imm12), + (SLTIU (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)), 1)>; def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>; def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>; -def : Pat<(setne GPR:$rs1, simm12:$imm12), - (SLTU X0, (XORI GPR:$rs1, simm12:$imm12))>; +def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12), + (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>; def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>; def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>; diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll index 04b1eeaad21a..34557696cc57 100644 --- a/llvm/test/CodeGen/RISCV/i32-icmp.ll +++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll @@ -19,7 +19,7 @@ define i32 @icmp_eq(i32 %a, i32 %b) nounwind { define i32 @icmp_eq_constant(i32 %a) nounwind { ; RV32I-LABEL: icmp_eq_constant: ; RV32I: # %bb.0: -; RV32I-NEXT: xori a0, a0, 42 +; RV32I-NEXT: addi a0, a0, -42 ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: ret %1 = icmp eq i32 %a, 42 @@ -27,6 +27,40 @@ define i32 @icmp_eq_constant(i32 %a) nounwind { ret i32 %2 } +define i32 @icmp_eq_constant_2048(i32 %a) nounwind { +; RV32I-LABEL: icmp_eq_constant_2048: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a0, a0, -2048 +; RV32I-NEXT: seqz a0, a0 +; RV32I-NEXT: ret + %1 = icmp eq i32 %a, 2048 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_eq_constant_neg_2048(i32 %a) nounwind { +; RV32I-LABEL: icmp_eq_constant_neg_2048: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a1, zero, -2048 +; RV32I-NEXT: xor a0, a0, a1 +; RV32I-NEXT: seqz a0, a0 +; RV32I-NEXT: ret + %1 = icmp eq i32 %a, -2048 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_eq_constant_neg_2047(i32 %a) nounwind { +; RV32I-LABEL: icmp_eq_constant_neg_2047: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a0, a0, 2047 +; RV32I-NEXT: seqz a0, a0 +; RV32I-NEXT: ret + %1 = icmp eq i32 %a, -2047 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + define i32 @icmp_eqz(i32 %a) nounwind { ; RV32I-LABEL: icmp_eqz: ; RV32I: # %bb.0: @@ -51,7 +85,7 @@ define i32 @icmp_ne(i32 %a, i32 %b) nounwind { define i32 @icmp_ne_constant(i32 %a) nounwind { ; RV32I-LABEL: icmp_ne_constant: ; RV32I: # %bb.0: -; RV32I-NEXT: xori a0, a0, 42 +; RV32I-NEXT: addi a0, a0, -42 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: ret %1 = icmp ne i32 %a, 42 @@ -59,6 +93,29 @@ define i32 @icmp_ne_constant(i32 %a) nounwind { ret i32 %2 } +define i32 @icmp_ne_constant_2048(i32 %a) nounwind { +; RV32I-LABEL: icmp_ne_constant_2048: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a0, a0, -2048 +; RV32I-NEXT: snez a0, a0 +; RV32I-NEXT: ret + %1 = icmp ne i32 %a, 2048 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + +define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind { +; RV32I-LABEL: icmp_ne_constant_neg_2048: +; RV32I: # %bb.0: +; RV32I-NEXT: addi a1, zero, -2048 +; RV32I-NEXT: xor a0, a0, a1 +; RV32I-NEXT: snez a0, a0 +; RV32I-NEXT: ret + %1 = icmp ne i32 %a, -2048 + %2 = zext i1 %1 to i32 + ret i32 %2 +} + define i32 @icmp_nez(i32 %a) nounwind { ; RV32I-LABEL: icmp_nez: ; RV32I: # %bb.0: diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll index 0c29bf505234..dfaee187db9c 100644 --- a/llvm/test/CodeGen/RISCV/setcc-logic.ll +++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll @@ -102,9 +102,9 @@ define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind { define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind { ; RV32I-LABEL: and_icmps_const_not1bit_diff: ; RV32I: # %bb.0: -; RV32I-NEXT: xori a1, a0, 44 +; RV32I-NEXT: addi a1, a0, -44 ; RV32I-NEXT: snez a1, a1 -; RV32I-NEXT: xori a0, a0, 92 +; RV32I-NEXT: addi a0, a0, -92 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: ret @@ -113,9 +113,9 @@ define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 -; RV64I-NEXT: xori a1, a0, 44 +; RV64I-NEXT: addi a1, a0, -44 ; RV64I-NEXT: snez a1, a1 -; RV64I-NEXT: xori a0, a0, 92 +; RV64I-NEXT: addi a0, a0, -92 ; RV64I-NEXT: snez a0, a0 ; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret -- GitLab From 7ef45f45f6721af4942f0e0bc38329e236b468cd Mon Sep 17 00:00:00 2001 From: Richard Smith Date: Mon, 10 Feb 2020 07:22:51 -0800 Subject: [PATCH 008/142] P1957R2: conversion from a pointer to bool is considered narrowing. This is being implemented somewhat speculatively, to match GCC's behavior. --- clang/lib/Sema/SemaOverload.cpp | 5 ++--- .../CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp | 14 ++++++++++++-- .../dcl.init/dcl.init.list/p7-cxx11-nowarn.cpp | 4 ---- 3 files changed, 14 insertions(+), 9 deletions(-) diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 003d9bb3a97d..1e838fd75130 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -328,9 +328,8 @@ NarrowingKind StandardConversionSequence::getNarrowingKind( goto FloatingIntegralConversion; if (FromType->isIntegralOrUnscopedEnumerationType()) goto IntegralConversion; - // Boolean conversions can be from pointers and pointers to members - // [conv.bool], and those aren't considered narrowing conversions. - return NK_Not_Narrowing; + // -- from a pointer type or pointer-to-member type to bool, or + return NK_Type_Narrowing; // -- from a floating-point type to an integer type, or // diff --git a/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp index 4436cb0aac60..eac9ac0e8279 100644 --- a/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp +++ b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp @@ -180,9 +180,9 @@ void shrink_int() { Agg b2 = {1}; // OK Agg b3 = {-1}; // expected-error {{ cannot be narrowed }} expected-note {{silence}} - // Conversions from pointers to booleans aren't narrowing conversions. + // Conversions from pointers to booleans are narrowing conversions. Agg* ptr = &b1; - Agg b = {ptr}; // OK + Agg b = {ptr}; // expected-error {{ cannot be narrowed }} expected-note {{silence}} Agg ce1 = { Convert(100000) }; // expected-error {{constant expression evaluates to 100000 which cannot be narrowed to type 'short'}} expected-note {{silence}} expected-warning {{changes value from 100000 to -31072}} Agg ce2 = { ConvertVar() }; // expected-error {{non-constant-expression cannot be narrowed from type 'short' to 'char'}} expected-note {{silence}} @@ -240,3 +240,13 @@ void test_narrowed(Value vi, Value vd) { int &ir = check_narrowed(vd); float &fr = check_narrowed(vi); } + +// * from a pointer type or a pointer-to-member type to bool. +void P1957R2(void *a, int *b, Agg *c, int Agg::*d) { + Agg ta = {a}; // expected-error {{cannot be narrowed}} expected-note {{}} + Agg tb = {b}; // expected-error {{cannot be narrowed}} expected-note {{}} + Agg tc = {c}; // expected-error {{cannot be narrowed}} expected-note {{}} + Agg td = {d}; // expected-error {{cannot be narrowed}} expected-note {{}} +} +template struct BoolParam {}; +BoolParam<&P1957R2> bp; // expected-error {{not allowed in a converted constant expression}} diff --git a/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-cxx11-nowarn.cpp b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-cxx11-nowarn.cpp index d4d8198d4fc8..d701ec964605 100644 --- a/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-cxx11-nowarn.cpp +++ b/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-cxx11-nowarn.cpp @@ -163,10 +163,6 @@ void shrink_int() { Agg b2 = {1}; // OK Agg b3 = {-1}; // expected-warning {{ cannot be narrowed }} expected-note {{silence}} - // Conversions from pointers to booleans aren't narrowing conversions. - Agg* ptr = &b1; - Agg b = {ptr}; // OK - Agg ce1 = { Convert(100000) }; // expected-warning {{constant expression evaluates to 100000 which cannot be narrowed to type 'short'}} expected-note {{silence}} expected-warning {{changes value from 100000 to -31072}} Agg ce2 = { ConvertVar() }; // expected-warning {{non-constant-expression cannot be narrowed from type 'short' to 'char'}} expected-note {{silence}} } -- GitLab From 9ce6dc9872be4081fb98f6161c28581e1cbbe7dc Mon Sep 17 00:00:00 2001 From: Richard Smith Date: Tue, 11 Feb 2020 06:09:18 -0800 Subject: [PATCH 009/142] CWG1423: don't permit implicit conversion of nullptr_t to bool. The C++ rules briefly allowed this, but the rule changed nearly 10 years ago and we never updated our implementation to match. However, we've warned on this by default for a long time, and no other compiler accepts (even as an extension). --- clang/include/clang/Sema/Overload.h | 18 +++++++++++++++++ clang/lib/Sema/SemaInit.cpp | 25 ++++++++++++++++++++---- clang/lib/Sema/SemaOverload.cpp | 15 +++++++++++--- clang/test/CXX/drs/dr14xx.cpp | 9 +++++++++ clang/test/CXX/drs/dr6xx.cpp | 4 ++-- clang/test/CXX/expr/expr.const/p3-0x.cpp | 2 +- clang/test/CodeGenCXX/nullptr.cpp | 2 +- clang/test/SemaCXX/conversion.cpp | 16 +++++++-------- clang/test/SemaCXX/nullptr.cpp | 2 +- clang/www/cxx_dr_status.html | 6 +++--- 10 files changed, 75 insertions(+), 24 deletions(-) diff --git a/clang/include/clang/Sema/Overload.h b/clang/include/clang/Sema/Overload.h index a274102ceb11..f1a8b98e5efd 100644 --- a/clang/include/clang/Sema/Overload.h +++ b/clang/include/clang/Sema/Overload.h @@ -677,6 +677,24 @@ class Sema; StdInitializerListElement = V; } + /// Form an "implicit" conversion sequence from nullptr_t to bool, for a + /// direct-initialization of a bool object from nullptr_t. + static ImplicitConversionSequence getNullptrToBool(QualType SourceType, + QualType DestType, + bool NeedLValToRVal) { + ImplicitConversionSequence ICS; + ICS.setStandard(); + ICS.Standard.setAsIdentityConversion(); + ICS.Standard.setFromType(SourceType); + if (NeedLValToRVal) + ICS.Standard.First = ICK_Lvalue_To_Rvalue; + ICS.Standard.setToType(0, SourceType); + ICS.Standard.Second = ICK_Boolean_Conversion; + ICS.Standard.setToType(1, DestType); + ICS.Standard.setToType(2, DestType); + return ICS; + } + // The result of a comparison between implicit conversion // sequences. Use Sema::CompareImplicitConversionSequences to // actually perform the comparison. diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index 61b7c166239f..61bb1f053ce2 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -4420,16 +4420,20 @@ static void TryListInitialization(Sema &S, // direct-list-initialization and copy-initialization otherwise. // We can't use InitListChecker for this, because it always performs // copy-initialization. This only matters if we might use an 'explicit' - // conversion operator, so we only need to handle the cases where the source - // is of record type. - if (InitList->getInit(0)->getType()->isRecordType()) { + // conversion operator, or for the special case conversion of nullptr_t to + // bool, so we only need to handle those cases. + // + // FIXME: Why not do this in all cases? + Expr *Init = InitList->getInit(0); + if (Init->getType()->isRecordType() || + (Init->getType()->isNullPtrType() && DestType->isBooleanType())) { InitializationKind SubKind = Kind.getKind() == InitializationKind::IK_DirectList ? InitializationKind::CreateDirect(Kind.getLocation(), InitList->getLBraceLoc(), InitList->getRBraceLoc()) : Kind; - Expr *SubInit[1] = { InitList->getInit(0) }; + Expr *SubInit[1] = { Init }; Sequence.InitializeFrom(S, Entity, SubKind, SubInit, /*TopLevelOfInitList*/true, TreatUnavailableAsInvalid); @@ -5854,6 +5858,19 @@ void InitializationSequence::InitializeFrom(Sema &S, return; } + // - Otherwise, if the initialization is direct-initialization, the source + // type is std::nullptr_t, and the destination type is bool, the initial + // value of the object being initialized is false. + if (!SourceType.isNull() && SourceType->isNullPtrType() && + DestType->isBooleanType() && + Kind.getKind() == InitializationKind::IK_Direct) { + AddConversionSequenceStep( + ImplicitConversionSequence::getNullptrToBool(SourceType, DestType, + Initializer->isGLValue()), + DestType); + return; + } + // - Otherwise, the initial value of the object being initialized is the // (possibly converted) value of the initializer expression. Standard // conversions (Clause 4) will be used, if necessary, to convert the diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 1e838fd75130..a10b7cd76482 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -230,7 +230,6 @@ bool StandardConversionSequence::isPointerConversionToBool() const { getFromType()->isMemberPointerType() || getFromType()->isObjCObjectPointerType() || getFromType()->isBlockPointerType() || - getFromType()->isNullPtrType() || First == ICK_Array_To_Pointer || First == ICK_Function_To_Pointer)) return true; @@ -1847,8 +1846,7 @@ static bool IsStandardConversion(Sema &S, Expr* From, QualType ToType, (FromType->isArithmeticType() || FromType->isAnyPointerType() || FromType->isBlockPointerType() || - FromType->isMemberPointerType() || - FromType->isNullPtrType())) { + FromType->isMemberPointerType())) { // Boolean conversions (C++ 4.12). SCS.Second = ICK_Boolean_Conversion; FromType = S.Context.BoolTy; @@ -5437,6 +5435,17 @@ Sema::PerformObjectArgumentInitialization(Expr *From, /// expression From to bool (C++0x [conv]p3). static ImplicitConversionSequence TryContextuallyConvertToBool(Sema &S, Expr *From) { + // C++ [dcl.init]/17.8: + // - Otherwise, if the initialization is direct-initialization, the source + // type is std::nullptr_t, and the destination type is bool, the initial + // value of the object being initialized is false. + if (From->getType()->isNullPtrType()) + return ImplicitConversionSequence::getNullptrToBool(From->getType(), + S.Context.BoolTy, + From->isGLValue()); + + // All other direct-initialization of bool is equivalent to an implicit + // conversion to bool in which explicit conversions are permitted. return TryImplicitConversion(S, From, S.Context.BoolTy, /*SuppressUserConversions=*/false, AllowedExplicit::Conversions, diff --git a/clang/test/CXX/drs/dr14xx.cpp b/clang/test/CXX/drs/dr14xx.cpp index 52129844c418..d55427f5de8c 100644 --- a/clang/test/CXX/drs/dr14xx.cpp +++ b/clang/test/CXX/drs/dr14xx.cpp @@ -8,6 +8,15 @@ // expected-no-diagnostics #endif +namespace dr1423 { // dr1423: 11 +#if __cplusplus >= 201103L + bool b1 = nullptr; // expected-error {{cannot initialize}} + bool b2(nullptr); // expected-warning {{implicit conversion of nullptr constant to 'bool'}} + bool b3 = {nullptr}; // expected-error {{cannot initialize}} + bool b4{nullptr}; // expected-warning {{implicit conversion of nullptr constant to 'bool'}} +#endif +} + // dr1425: na abi namespace dr1460 { // dr1460: 3.5 diff --git a/clang/test/CXX/drs/dr6xx.cpp b/clang/test/CXX/drs/dr6xx.cpp index 7a0adb5fe406..4c4ed7767ecd 100644 --- a/clang/test/CXX/drs/dr6xx.cpp +++ b/clang/test/CXX/drs/dr6xx.cpp @@ -585,10 +585,10 @@ namespace dr652 { // dr652: yes // dr653 FIXME: add codegen test #if __cplusplus >= 201103L -namespace dr654 { // dr654: yes +namespace dr654 { // dr654: sup 1423 void f() { if (nullptr) {} // expected-warning {{implicit conversion of nullptr constant to 'bool'}} - bool b = nullptr; // expected-warning {{implicit conversion of nullptr constant to 'bool'}} + bool b = nullptr; // expected-error {{cannot initialize a variable of type 'bool' with an rvalue of type 'nullptr_t'}} if (nullptr == 0) {} if (nullptr != 0) {} if (nullptr <= 0) {} // expected-error {{invalid operands}} diff --git a/clang/test/CXX/expr/expr.const/p3-0x.cpp b/clang/test/CXX/expr/expr.const/p3-0x.cpp index 731e0c312fa1..8daca7a565f3 100644 --- a/clang/test/CXX/expr/expr.const/p3-0x.cpp +++ b/clang/test/CXX/expr/expr.const/p3-0x.cpp @@ -95,7 +95,7 @@ Val add_noexcept; using Int = A<1.0>; // expected-error {{conversion from 'double' to 'unsigned char' is not allowed in a converted constant expression}} enum B : bool { True = &a, // expected-error {{conversion from 'bool (*)(int)' to 'bool' is not allowed in a converted constant expression}} - False = nullptr // expected-error {{conversion from 'nullptr_t' to 'bool' is not allowed in a converted constant expression}} + False = 0.0, // expected-error {{conversion from 'double' to 'bool' is not allowed in a converted constant expression}} }; void c() { // Note, promoted type of switch is 'int'. diff --git a/clang/test/CodeGenCXX/nullptr.cpp b/clang/test/CodeGenCXX/nullptr.cpp index 823c0d7d18a7..ab47282569fd 100644 --- a/clang/test/CodeGenCXX/nullptr.cpp +++ b/clang/test/CodeGenCXX/nullptr.cpp @@ -32,7 +32,7 @@ union U { // CHECK: load // CHECK-NOT: load // CHECK: ret i1 false -bool pr23833_a(U &u) { return u.b; } +bool pr23833_a(U &u) { return bool(u.b); } // CHECK-LABEL: define {{.*}}pr23833_b // CHECK: store diff --git a/clang/test/SemaCXX/conversion.cpp b/clang/test/SemaCXX/conversion.cpp index dcd64fa2ec8a..67bfdf5532b5 100644 --- a/clang/test/SemaCXX/conversion.cpp +++ b/clang/test/SemaCXX/conversion.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin -fsyntax-only -Wconversion -std=c++11 -verify %s -// RUN: %clang_cc1 -triple x86_64-apple-darwin -fsyntax-only -Wconversion -std=c++11 %s 2>&1 | FileCheck %s +// RUN: not %clang_cc1 -triple x86_64-apple-darwin -fsyntax-only -Wconversion -std=c++11 %s 2>&1 | FileCheck %s #include @@ -129,9 +129,9 @@ namespace test6 { namespace test7 { bool fun() { - bool x = nullptr; // expected-warning {{implicit conversion of nullptr constant to 'bool'}} + bool x = nullptr; // expected-error {{cannot initialize}} if (nullptr) {} // expected-warning {{implicit conversion of nullptr constant to 'bool'}} - return nullptr; // expected-warning {{implicit conversion of nullptr constant to 'bool'}} + return nullptr; // expected-error {{cannot initialize}} } } @@ -198,14 +198,12 @@ namespace test8 { } } -// Don't warn on a nullptr to bool conversion when the nullptr is the return -// type of a function. namespace test9 { typedef decltype(nullptr) nullptr_t; nullptr_t EXIT(); bool test() { - return EXIT(); + return EXIT(); // expected-error {{cannot initialize}} } } @@ -273,10 +271,10 @@ void function1(const char* str) { CHECK13(check_str_null_13(str)); } -bool some_bool_function(bool); +bool some_bool_function(bool); // expected-note {{no known conversion}} void function2() { - CHECK13(some_bool_function(nullptr)); // expected-warning{{implicit conversion of nullptr constant to 'bool'}} - CHECK13(some_bool_function(NULL)); // expected-warning{{implicit conversion of NULL constant to 'bool'}} + CHECK13(some_bool_function(nullptr)); // expected-error {{no matching function}} + CHECK13(some_bool_function(NULL)); // expected-warning {{implicit conversion of NULL constant to 'bool'}} } #define run_check_nullptr_13(str) \ diff --git a/clang/test/SemaCXX/nullptr.cpp b/clang/test/SemaCXX/nullptr.cpp index 9a092910b6f9..23ea383c3e87 100644 --- a/clang/test/SemaCXX/nullptr.cpp +++ b/clang/test/SemaCXX/nullptr.cpp @@ -25,7 +25,7 @@ nullptr_t f(nullptr_t null) pf = null; void (A::*pmf)() = nullptr; pmf = null; - bool b = nullptr; + bool b = nullptr; // expected-error {{cannot initialize}} // Can't convert nullptr to integral implicitly. uintptr_t i = nullptr; // expected-error {{cannot initialize}} diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index d4c6175a8c1b..3e9210f861ab 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -1504,7 +1504,7 @@ accessible? 244 CD1 Destructor lookup - Partial + Clang 11 245 @@ -3967,7 +3967,7 @@ and POD class 654 CD1 Conversions to and from nullptr_t - Yes + Superseded by 1423 655 @@ -8353,7 +8353,7 @@ and POD class 1423 CD3 Convertibility of nullptr to bool - Unknown + Clang 11 1424 -- GitLab From b04885a55c2aa4666a420a5638db75bee9a44fa0 Mon Sep 17 00:00:00 2001 From: Joonsoo Jeon Date: Tue, 11 Feb 2020 09:38:14 -0500 Subject: [PATCH 010/142] [mlir][ods] Added RankedIntElementsAttr class Defines a tablegen class RankedIntElementsAttr. This is an integer version of RankedFloatElementsAttr. Differential Revision: https://reviews.llvm.org/D73764 --- mlir/include/mlir/IR/OpBase.td | 20 +++++++++++ mlir/test/IR/attribute.mlir | 50 ++++++++++++++++++++++++++++ mlir/test/lib/TestDialect/TestOps.td | 7 ++++ 3 files changed, 77 insertions(+) diff --git a/mlir/include/mlir/IR/OpBase.td b/mlir/include/mlir/IR/OpBase.td index c610e0b4e911..d73b7ba9bb71 100644 --- a/mlir/include/mlir/IR/OpBase.td +++ b/mlir/include/mlir/IR/OpBase.td @@ -1040,6 +1040,26 @@ class IntElementsAttr : ElementsAttrBase< def I32ElementsAttr : IntElementsAttr<32>; def I64ElementsAttr : IntElementsAttr<64>; +// A `width`-bit integer elements attribute. The attribute should be ranked and +// has a shape as specified in `dims`. +class RankedIntElementsAttr dims> : IntElementsAttr { + // Check that this has the specified shape. + let predicate = And<[ + IntElementsAttr.predicate, + CPred<"$_self.cast().getType().getShape() == " + "ArrayRef({" # StrJoinInt.result # "})">]>; + + let description = width # "-bit int elements attribute of shape [" # + StrJoinInt.result # "]"; + + let constBuilderCall = "DenseIntElementsAttr::get(" + "RankedTensorType::get({" # StrJoinInt.result # + "}, $_builder.getIntegerType(" # width # ")), makeArrayRef($0))"; +} + +class RankedI32ElementsAttr dims> : RankedIntElementsAttr<32, dims>; +class RankedI64ElementsAttr dims> : RankedIntElementsAttr<64, dims>; + class FloatElementsAttr : ElementsAttrBase< CPred<"$_self.isa() &&" "$_self.cast().getType()." diff --git a/mlir/test/IR/attribute.mlir b/mlir/test/IR/attribute.mlir index 318837d30cc9..c0ee566738e3 100644 --- a/mlir/test/IR/attribute.mlir +++ b/mlir/test/IR/attribute.mlir @@ -243,3 +243,53 @@ func @fn() { return } // expected-error @+1 {{referencing to a 'FuncOp' symbol}} "test.symbol_ref_attr"() {symbol = @foo} : () -> () + +// ----- + +//===----------------------------------------------------------------------===// +// Test IntElementsAttr +//===----------------------------------------------------------------------===// + +func @correct_type_pass() { + "test.int_elements_attr"() { + // CHECK: matrix_i64_attr = dense<6> : tensor<4x8xi64> + // CHECK: vector_i32_attr = dense<5> : tensor<2xi32> + matrix_i64_attr = dense<6> : tensor<4x8xi64>, + vector_i32_attr = dense<5> : tensor<2xi32> + } : () -> () + return +} + +// ----- + +func @wrong_element_type_fail() { + // expected-error @+1 {{failed to satisfy constraint: 32-bit int elements attribute of shape [2]}} + "test.int_elements_attr"() { + matrix_i64_attr = dense<6> : tensor<4x8xi64>, + vector_i32_attr = dense<5> : tensor<2xi64> + } : () -> () + return +} + +// ----- + +func @wrong_shape_fail() { + // expected-error @+1 {{failed to satisfy constraint: 64-bit int elements attribute of shape [4, 8]}} + "test.int_elements_attr"() { + matrix_i64_attr = dense<6> : tensor<4xi64>, + vector_i32_attr = dense<5> : tensor<2xi32> + } : () -> () + return +} + +// ----- + +func @wrong_shape_fail() { + // expected-error @+1 {{failed to satisfy constraint: 32-bit int elements attribute of shape [2]}} + "test.int_elements_attr"() { + matrix_i64_attr = dense<6> : tensor<4x8xi64>, + vector_i32_attr = dense<5> : tensor + } : () -> () + return +} + diff --git a/mlir/test/lib/TestDialect/TestOps.td b/mlir/test/lib/TestDialect/TestOps.td index de7f1875ef05..48adf2dd1585 100644 --- a/mlir/test/lib/TestDialect/TestOps.td +++ b/mlir/test/lib/TestDialect/TestOps.td @@ -204,6 +204,13 @@ def UpdateFloatElementsAttr : Pat< ConstantAttr, "{5.0f, 6.0f}">:$f32attr, $f64attr)>; +def IntElementsAttrOp : TEST_Op<"int_elements_attr"> { + let arguments = (ins + RankedI32ElementsAttr<[2]>:$vector_i32_attr, + RankedI64ElementsAttr<[4, 8]>:$matrix_i64_attr + ); +} + //===----------------------------------------------------------------------===// // Test Attribute Constraints //===----------------------------------------------------------------------===// -- GitLab From 9a3740c33919287fd9aa4e0c6f761619e84c62a7 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 11 Feb 2020 09:35:52 -0500 Subject: [PATCH 011/142] [OPENMP50]Add restrictions for memory order clauses in atomic directive. Added restrictions for atomic directive. 1. If atomic-clause is read then memory-order-clause must not be acq_rel or release. 2. If atomic-clause is write then memory-order-clause must not be acq_rel or acquire. 3. If atomic-clause is update or not present then memory-order-clause must not be acq_rel or acquire. --- .../clang/Basic/DiagnosticSemaKinds.td | 2 + clang/lib/Sema/SemaOpenMP.cpp | 22 +++++ clang/test/OpenMP/atomic_ast_print.cpp | 80 +++++++++---------- clang/test/OpenMP/atomic_messages.cpp | 38 ++++----- clang/test/OpenMP/atomic_read_codegen.c | 7 +- clang/test/OpenMP/atomic_update_codegen.cpp | 20 +++-- clang/test/OpenMP/atomic_write_codegen.c | 15 ++-- 7 files changed, 102 insertions(+), 82 deletions(-) diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 450075f2e927..9e4e89e61031 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -9697,6 +9697,8 @@ def err_omp_atomic_several_clauses : Error< "directive '#pragma omp atomic' cannot contain more than one 'read', 'write', 'update' or 'capture' clause">; def err_omp_several_mem_order_clauses : Error< "directive '#pragma omp %0' cannot contain more than one %select{'seq_cst', |}1'acq_rel', 'acquire' or 'release' clause">; +def err_omp_atomic_incompatible_mem_order_clause : Error< + "directive '#pragma omp atomic%select{ %0|}1' cannot be used with '%2' clause">; def note_omp_previous_mem_order_clause : Note< "'%0' clause used here">; def err_omp_target_contains_not_only_teams : Error< diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 2e3c75fed370..313c9791bf87 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -8968,6 +8968,28 @@ StmtResult Sema::ActOnOpenMPAtomicDirective(ArrayRef Clauses, } } } + // OpenMP 5.0, 2.17.7 atomic Construct, Restrictions + // If atomic-clause is read then memory-order-clause must not be acq_rel or + // release. + // If atomic-clause is write then memory-order-clause must not be acq_rel or + // acquire. + // If atomic-clause is update or not present then memory-order-clause must not + // be acq_rel or acquire. + if ((AtomicKind == OMPC_read && + (MemOrderKind == OMPC_acq_rel || MemOrderKind == OMPC_release)) || + ((AtomicKind == OMPC_write || AtomicKind == OMPC_update || + AtomicKind == OMPC_unknown) && + (MemOrderKind == OMPC_acq_rel || MemOrderKind == OMPC_acquire))) { + SourceLocation Loc = AtomicKindLoc; + if (AtomicKind == OMPC_unknown) + Loc = StartLoc; + Diag(Loc, diag::err_omp_atomic_incompatible_mem_order_clause) + << getOpenMPClauseName(AtomicKind) + << (AtomicKind == OMPC_unknown ? 1 : 0) + << getOpenMPClauseName(MemOrderKind); + Diag(MemOrderLoc, diag::note_omp_previous_mem_order_clause) + << getOpenMPClauseName(MemOrderKind); + } Stmt *Body = CS->getCapturedStmt(); if (auto *EWC = dyn_cast(Body)) diff --git a/clang/test/OpenMP/atomic_ast_print.cpp b/clang/test/OpenMP/atomic_ast_print.cpp index 4dd64a75f2c9..f3f2883d2368 100644 --- a/clang/test/OpenMP/atomic_ast_print.cpp +++ b/clang/test/OpenMP/atomic_ast_print.cpp @@ -44,13 +44,13 @@ T foo(T argc) { a = b; b++; } -#pragma omp atomic acq_rel +#pragma omp atomic a++; -#pragma omp atomic read acq_rel +#pragma omp atomic read a = argc; -#pragma omp atomic acq_rel write +#pragma omp atomic write a = argc + argc; -#pragma omp atomic update acq_rel +#pragma omp atomic update a = a + argc; #pragma omp atomic acq_rel capture a = b++; @@ -59,13 +59,13 @@ T foo(T argc) { a = b; b++; } -#pragma omp atomic acquire +#pragma omp atomic a++; #pragma omp atomic read acquire a = argc; -#pragma omp atomic acquire write +#pragma omp atomic write a = argc + argc; -#pragma omp atomic update acquire +#pragma omp atomic update a = a + argc; #pragma omp atomic acquire capture a = b++; @@ -76,7 +76,7 @@ T foo(T argc) { } #pragma omp atomic release a++; -#pragma omp atomic read release +#pragma omp atomic read a = argc; #pragma omp atomic release write a = argc + argc; @@ -123,13 +123,13 @@ T foo(T argc) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } -// CHECK-NEXT: #pragma omp atomic acq_rel +// CHECK-NEXT: #pragma omp atomic // CHECK-NEXT: a++; -// CHECK-NEXT: #pragma omp atomic read acq_rel +// CHECK-NEXT: #pragma omp atomic read // CHECK-NEXT: a = argc; -// CHECK-NEXT: #pragma omp atomic acq_rel write +// CHECK-NEXT: #pragma omp atomic write // CHECK-NEXT: a = argc + argc; -// CHECK-NEXT: #pragma omp atomic update acq_rel +// CHECK-NEXT: #pragma omp atomic update // CHECK-NEXT: a = a + argc; // CHECK-NEXT: #pragma omp atomic acq_rel capture // CHECK-NEXT: a = b++; @@ -138,13 +138,13 @@ T foo(T argc) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } -// CHECK-NEXT: #pragma omp atomic acquire +// CHECK-NEXT: #pragma omp atomic // CHECK-NEXT: a++; // CHECK-NEXT: #pragma omp atomic read acquire // CHECK-NEXT: a = argc; -// CHECK-NEXT: #pragma omp atomic acquire write +// CHECK-NEXT: #pragma omp atomic write // CHECK-NEXT: a = argc + argc; -// CHECK-NEXT: #pragma omp atomic update acquire +// CHECK-NEXT: #pragma omp atomic update // CHECK-NEXT: a = a + argc; // CHECK-NEXT: #pragma omp atomic acquire capture // CHECK-NEXT: a = b++; @@ -155,7 +155,7 @@ T foo(T argc) { // CHECK-NEXT: } // CHECK-NEXT: #pragma omp atomic release // CHECK-NEXT: a++; -// CHECK-NEXT: #pragma omp atomic read release +// CHECK-NEXT: #pragma omp atomic read // CHECK-NEXT: a = argc; // CHECK-NEXT: #pragma omp atomic release write // CHECK-NEXT: a = argc + argc; @@ -199,13 +199,13 @@ T foo(T argc) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } -// CHECK-NEXT: #pragma omp atomic acq_rel +// CHECK-NEXT: #pragma omp atomic // CHECK-NEXT: a++; -// CHECK-NEXT: #pragma omp atomic read acq_rel +// CHECK-NEXT: #pragma omp atomic read // CHECK-NEXT: a = argc; -// CHECK-NEXT: #pragma omp atomic acq_rel write +// CHECK-NEXT: #pragma omp atomic write // CHECK-NEXT: a = argc + argc; -// CHECK-NEXT: #pragma omp atomic update acq_rel +// CHECK-NEXT: #pragma omp atomic update // CHECK-NEXT: a = a + argc; // CHECK-NEXT: #pragma omp atomic acq_rel capture // CHECK-NEXT: a = b++; @@ -214,13 +214,13 @@ T foo(T argc) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } -// CHECK-NEXT: #pragma omp atomic acquire +// CHECK-NEXT: #pragma omp atomic // CHECK-NEXT: a++; // CHECK-NEXT: #pragma omp atomic read acquire // CHECK-NEXT: a = argc; -// CHECK-NEXT: #pragma omp atomic acquire write +// CHECK-NEXT: #pragma omp atomic write // CHECK-NEXT: a = argc + argc; -// CHECK-NEXT: #pragma omp atomic update acquire +// CHECK-NEXT: #pragma omp atomic update // CHECK-NEXT: a = a + argc; // CHECK-NEXT: #pragma omp atomic acquire capture // CHECK-NEXT: a = b++; @@ -231,7 +231,7 @@ T foo(T argc) { // CHECK-NEXT: } // CHECK-NEXT: #pragma omp atomic release // CHECK-NEXT: a++; -// CHECK-NEXT: #pragma omp atomic read release +// CHECK-NEXT: #pragma omp atomic read // CHECK-NEXT: a = argc; // CHECK-NEXT: #pragma omp atomic release write // CHECK-NEXT: a = argc + argc; @@ -279,13 +279,13 @@ int main(int argc, char **argv) { a = b; b++; } -#pragma omp atomic acq_rel +#pragma omp atomic a++; -#pragma omp atomic read acq_rel +#pragma omp atomic read a = argc; -#pragma omp atomic acq_rel write +#pragma omp atomic write a = argc + argc; -#pragma omp atomic update acq_rel +#pragma omp atomic update a = a + argc; #pragma omp atomic acq_rel capture a = b++; @@ -294,13 +294,13 @@ int main(int argc, char **argv) { a = b; b++; } -#pragma omp atomic acquire +#pragma omp atomic a++; #pragma omp atomic read acquire a = argc; -#pragma omp atomic acquire write +#pragma omp atomic write a = argc + argc; -#pragma omp atomic update acquire +#pragma omp atomic update a = a + argc; #pragma omp atomic acquire capture a = b++; @@ -311,7 +311,7 @@ int main(int argc, char **argv) { } #pragma omp atomic release a++; -#pragma omp atomic read release +#pragma omp atomic read a = argc; #pragma omp atomic release write a = argc + argc; @@ -354,13 +354,13 @@ int main(int argc, char **argv) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } - // CHECK-NEXT: #pragma omp atomic acq_rel + // CHECK-NEXT: #pragma omp atomic // CHECK-NEXT: a++; - // CHECK-NEXT: #pragma omp atomic read acq_rel + // CHECK-NEXT: #pragma omp atomic read // CHECK-NEXT: a = argc; - // CHECK-NEXT: #pragma omp atomic acq_rel write + // CHECK-NEXT: #pragma omp atomic write // CHECK-NEXT: a = argc + argc; - // CHECK-NEXT: #pragma omp atomic update acq_rel + // CHECK-NEXT: #pragma omp atomic update // CHECK-NEXT: a = a + argc; // CHECK-NEXT: #pragma omp atomic acq_rel capture // CHECK-NEXT: a = b++; @@ -369,13 +369,13 @@ int main(int argc, char **argv) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } - // CHECK-NEXT: #pragma omp atomic acquire + // CHECK-NEXT: #pragma omp atomic // CHECK-NEXT: a++; // CHECK-NEXT: #pragma omp atomic read acquire // CHECK-NEXT: a = argc; - // CHECK-NEXT: #pragma omp atomic acquire write + // CHECK-NEXT: #pragma omp atomic write // CHECK-NEXT: a = argc + argc; - // CHECK-NEXT: #pragma omp atomic update acquire + // CHECK-NEXT: #pragma omp atomic update // CHECK-NEXT: a = a + argc; // CHECK-NEXT: #pragma omp atomic acquire capture // CHECK-NEXT: a = b++; @@ -386,7 +386,7 @@ int main(int argc, char **argv) { // CHECK-NEXT: } // CHECK-NEXT: #pragma omp atomic release // CHECK-NEXT: a++; - // CHECK-NEXT: #pragma omp atomic read release + // CHECK-NEXT: #pragma omp atomic read // CHECK-NEXT: a = argc; // CHECK-NEXT: #pragma omp atomic release write // CHECK-NEXT: a = argc + argc; diff --git a/clang/test/OpenMP/atomic_messages.cpp b/clang/test/OpenMP/atomic_messages.cpp index d595689e4d15..af5fc90b35a3 100644 --- a/clang/test/OpenMP/atomic_messages.cpp +++ b/clang/test/OpenMP/atomic_messages.cpp @@ -728,16 +728,16 @@ int seq_cst() { template T acq_rel() { T a = 0, b = 0; -// omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} +// omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic' cannot be used with 'acq_rel' clause}} omp50-note@+1 {{'acq_rel' clause used here}} #pragma omp atomic acq_rel // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; -// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'acq_rel' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} -#pragma omp atomic acq_rel seq_cst - a += b; +// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'acq_rel' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} omp50-error@+1 2 {{directive '#pragma omp atomic read' cannot be used with 'acq_rel' clause}} omp50-note@+1 2 {{'acq_rel' clause used here}} +#pragma omp atomic read acq_rel seq_cst + a = b; -// omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} +// omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic update' cannot be used with 'acq_rel' clause}} omp50-note@+1 {{'acq_rel' clause used here}} #pragma omp atomic update acq_rel // expected-error@+2 {{the statement for 'atomic update' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} @@ -749,16 +749,16 @@ T acq_rel() { int acq_rel() { int a = 0, b = 0; // Test for atomic acq_rel -// omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} -#pragma omp atomic acq_rel - // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} +// omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic write' cannot be used with 'acq_rel' clause}} omp50-note@+1 {{'acq_rel' clause used here}} +#pragma omp atomic acq_rel write + // expected-error@+2 {{the statement for 'atomic write' must be an expression statement of form 'x = expr;', where x is a lvalue expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; // omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} #pragma omp atomic seq_cst acq_rel a += b; -// omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} +// omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic update' cannot be used with 'acq_rel' clause}} omp50-note@+1 {{'acq_rel' clause used here}} #pragma omp atomic update acq_rel // expected-error@+2 {{the statement for 'atomic update' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} @@ -770,16 +770,16 @@ int acq_rel() { template T acquire() { T a = 0, b = 0; -// omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} +// omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic' cannot be used with 'acquire' clause}} omp50-note@+1 {{'acquire' clause used here}} #pragma omp atomic acquire // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; -// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'acquire' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} +// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'acquire' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} omp50-error@+1 2 {{directive '#pragma omp atomic' cannot be used with 'acquire' clause}} omp50-note@+1 2 {{'acquire' clause used here}} #pragma omp atomic acquire seq_cst a += b; -// omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} +// omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic update' cannot be used with 'acquire' clause}} omp50-note@+1 {{'acquire' clause used here}} #pragma omp atomic update acquire // expected-error@+2 {{the statement for 'atomic update' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} @@ -791,16 +791,16 @@ T acquire() { int acquire() { int a = 0, b = 0; // Test for atomic acquire -// omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} -#pragma omp atomic acquire - // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} +// omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic write' cannot be used with 'acquire' clause}} omp50-note@+1 {{'acquire' clause used here}} +#pragma omp atomic write acquire + // expected-error@+2 {{the statement for 'atomic write' must be an expression statement of form 'x = expr;', where x is a lvalue expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; // omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} #pragma omp atomic seq_cst acquire a += b; -// omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} +// omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic update' cannot be used with 'acquire' clause}} omp50-note@+1 {{'acquire' clause used here}} #pragma omp atomic update acquire // expected-error@+2 {{the statement for 'atomic update' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} @@ -833,9 +833,9 @@ T release() { int release() { int a = 0, b = 0; // Test for atomic release -// omp45-error@+1 {{unexpected OpenMP clause 'release' in directive '#pragma omp atomic'}} -#pragma omp atomic release - // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} +// omp45-error@+1 {{unexpected OpenMP clause 'release' in directive '#pragma omp atomic'}} omp50-error@+1 {{directive '#pragma omp atomic read' cannot be used with 'release' clause}} omp50-note@+1 {{'release' clause used here}} +#pragma omp atomic read release + // expected-error@+2 {{the statement for 'atomic read' must be an expression statement of form 'v = x;', where v and x are both lvalue expressions with scalar type}} // expected-note@+1 {{expected an expression statement}} ; // omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'release' in directive '#pragma omp atomic'}} diff --git a/clang/test/OpenMP/atomic_read_codegen.c b/clang/test/OpenMP/atomic_read_codegen.c index 814975e38ea2..8d49115bc603 100644 --- a/clang/test/OpenMP/atomic_read_codegen.c +++ b/clang/test/OpenMP/atomic_read_codegen.c @@ -312,7 +312,7 @@ int main() { // CHECK: [[SHL:%.+]] = shl i64 [[LD]], 40 // CHECK: [[ASHR:%.+]] = ashr i64 [[SHL]], 57 // CHECK: store x86_fp80 -#pragma omp atomic read release +#pragma omp atomic read ldv = bfx4.b; // CHECK: [[LD:%.+]] = load atomic i8, i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @bfx4_packed, i32 0, i32 0, i64 2) acquire // CHECK: store i8 [[LD]], i8* [[LDTEMP:%.+]] @@ -323,14 +323,13 @@ int main() { // CHECK: store x86_fp80 #pragma omp atomic read acquire ldv = bfx4_packed.b; -// CHECK: [[LD:%.+]] = load atomic i64, i64* bitcast (<2 x float>* @{{.+}} to i64*) acquire +// CHECK: [[LD:%.+]] = load atomic i64, i64* bitcast (<2 x float>* @{{.+}} to i64*) monotonic // CHECK: [[BITCAST:%.+]] = bitcast <2 x float>* [[LDTEMP:%.+]] to i64* // CHECK: store i64 [[LD]], i64* [[BITCAST]] // CHECK: [[LD:%.+]] = load <2 x float>, <2 x float>* [[LDTEMP]] // CHECK: extractelement <2 x float> [[LD]] -// CHECK: call{{.*}} @__kmpc_flush( // CHECK: store i64 -#pragma omp atomic read acq_rel +#pragma omp atomic read ulv = float2x.x; // CHECK: call{{.*}} i{{[0-9]+}} @llvm.read_register // CHECK: call{{.*}} @__kmpc_flush( diff --git a/clang/test/OpenMP/atomic_update_codegen.cpp b/clang/test/OpenMP/atomic_update_codegen.cpp index fb900753898c..7913dc1ce69f 100644 --- a/clang/test/OpenMP/atomic_update_codegen.cpp +++ b/clang/test/OpenMP/atomic_update_codegen.cpp @@ -812,7 +812,7 @@ int main() { #pragma omp atomic update bfx4_packed.a -= ldv; // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} -// CHECK: [[PREV_VALUE:%.+]] = load atomic i64, i64* bitcast (%struct.BitFields4* @{{.+}} to i64*) acquire +// CHECK: [[PREV_VALUE:%.+]] = load atomic i64, i64* bitcast (%struct.BitFields4* @{{.+}} to i64*) monotonic // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD_BF_VALUE:%.+]] = phi i64 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] @@ -831,15 +831,15 @@ int main() { // CHECK: [[VAL:%.+]] = or i64 [[BF_CLEAR]], [[BF_VALUE]] // CHECK: store i64 [[VAL]], i64* [[TEMP1]] // CHECK: [[NEW_BF_VALUE:%.+]] = load i64, i64* [[TEMP1]] -// CHECK: [[RES:%.+]] = cmpxchg i64* bitcast (%struct.BitFields4* @{{.+}} to i64*), i64 [[OLD_BF_VALUE]], i64 [[NEW_BF_VALUE]] acquire acquire +// CHECK: [[RES:%.+]] = cmpxchg i64* bitcast (%struct.BitFields4* @{{.+}} to i64*), i64 [[OLD_BF_VALUE]], i64 [[NEW_BF_VALUE]] monotonic monotonic // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i64, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -#pragma omp atomic acquire +#pragma omp atomic bfx4.b /= ldv; // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} -// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2) acquire +// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2) monotonic // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] @@ -861,17 +861,16 @@ int main() { // CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]] // CHECK: store i8 %{{.+}}, i8* [[BITCAST1]] // CHECK: [[NEW_BF_VALUE:%.+]] = load i8, i8* [[BITCAST1]] -// CHECK: [[RES:%.+]] = cmpxchg i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] acq_rel acquire +// CHECK: [[RES:%.+]] = cmpxchg i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -// CHECK: call{{.*}} @__kmpc_flush( -#pragma omp atomic update acq_rel +#pragma omp atomic update bfx4_packed.b += ldv; // CHECK: load i64, i64* // CHECK: [[EXPR:%.+]] = uitofp i64 %{{.+}} to float -// CHECK: [[I64VAL:%.+]] = load atomic i64, i64* bitcast (<2 x float>* [[DEST:@.+]] to i64*) acquire +// CHECK: [[I64VAL:%.+]] = load atomic i64, i64* bitcast (<2 x float>* [[DEST:@.+]] to i64*) monotonic // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD_I64:%.+]] = phi i64 [ [[I64VAL]], %{{.+}} ], [ [[FAILED_I64_OLD_VAL:%.+]], %[[CONT]] ] @@ -886,13 +885,12 @@ int main() { // CHECK: [[NEW_VEC_VAL:%.+]] = insertelement <2 x float> [[VEC_VAL]], float [[VEC_ITEM_VAL]], i64 0 // CHECK: store <2 x float> [[NEW_VEC_VAL]], <2 x float>* [[TEMP]] // CHECK: [[NEW_I64:%.+]] = load i64, i64* [[BITCAST]] -// CHECK: [[RES:%.+]] = cmpxchg i64* bitcast (<2 x float>* [[DEST]] to i64*), i64 [[OLD_I64]], i64 [[NEW_I64]] acq_rel acquire +// CHECK: [[RES:%.+]] = cmpxchg i64* bitcast (<2 x float>* [[DEST]] to i64*), i64 [[OLD_I64]], i64 [[NEW_I64]] monotonic monotonic // CHECK: [[FAILED_I64_OLD_VAL:%.+]] = extractvalue { i64, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -// CHECK: call{{.*}} @__kmpc_flush( -#pragma omp atomic acq_rel +#pragma omp atomic float2x.x = ulv - float2x.x; // CHECK: [[EXPR:%.+]] = load double, double* @{{.+}}, // CHECK: [[OLD_VAL:%.+]] = call i32 @llvm.read_register.i32([[REG:metadata ![0-9]+]]) diff --git a/clang/test/OpenMP/atomic_write_codegen.c b/clang/test/OpenMP/atomic_write_codegen.c index f8a74e8c6edd..053f46d55246 100644 --- a/clang/test/OpenMP/atomic_write_codegen.c +++ b/clang/test/OpenMP/atomic_write_codegen.c @@ -88,7 +88,7 @@ int main() { __imag(civ) = 1; // CHECK: load i8, i8* // CHECK: store atomic i8{{.*}}monotonic -#pragma omp atomic write acquire +#pragma omp atomic write bx = bv; // CHECK: load i8, i8* // CHECK: store atomic i8{{.*}}release @@ -470,7 +470,7 @@ int main() { bfx4.b = ldv; // CHECK: load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[NEW_VAL:%.+]] = fptosi x86_fp80 %{{.+}} to i64 -// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2) acquire +// CHECK: [[PREV_VALUE:%.+]] = load atomic i8, i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2) monotonic // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD_BF_VALUE:%.+]] = phi i8 [ [[PREV_VALUE]], %[[EXIT]] ], [ [[FAILED_OLD_VAL:%.+]], %[[CONT]] ] @@ -481,16 +481,16 @@ int main() { // CHECK: or i8 [[BF_CLEAR]], [[BF_VALUE]] // CHECK: store i8 %{{.+}}, i8* [[LDTEMP:%.+]] // CHECK: [[NEW_BF_VALUE:%.+]] = load i8, i8* [[LDTEMP]] -// CHECK: [[RES:%.+]] = cmpxchg i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] acquire acquire +// CHECK: [[RES:%.+]] = cmpxchg i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2), i8 [[OLD_BF_VALUE]], i8 [[NEW_BF_VALUE]] monotonic monotonic // CHECK: [[FAILED_OLD_VAL]] = extractvalue { i8, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -#pragma omp atomic write acquire +#pragma omp atomic write bfx4_packed.b = ldv; // CHECK: load i64, i64* // CHECK: [[VEC_ITEM_VAL:%.+]] = uitofp i64 %{{.+}} to float -// CHECK: [[I64VAL:%.+]] = load atomic i64, i64* bitcast (<2 x float>* [[DEST:@.+]] to i64*) acquire +// CHECK: [[I64VAL:%.+]] = load atomic i64, i64* bitcast (<2 x float>* [[DEST:@.+]] to i64*) monotonic // CHECK: br label %[[CONT:.+]] // CHECK: [[CONT]] // CHECK: [[OLD_I64:%.+]] = phi i64 [ [[I64VAL]], %{{.+}} ], [ [[FAILED_I64_OLD_VAL:%.+]], %[[CONT]] ] @@ -500,13 +500,12 @@ int main() { // CHECK: [[NEW_VEC_VAL:%.+]] = insertelement <2 x float> [[VEC_VAL]], float [[VEC_ITEM_VAL]], i64 0 // CHECK: store <2 x float> [[NEW_VEC_VAL]], <2 x float>* [[LDTEMP]] // CHECK: [[NEW_I64:%.+]] = load i64, i64* [[BITCAST]] -// CHECK: [[RES:%.+]] = cmpxchg i64* bitcast (<2 x float>* [[DEST]] to i64*), i64 [[OLD_I64]], i64 [[NEW_I64]] acq_rel acquire +// CHECK: [[RES:%.+]] = cmpxchg i64* bitcast (<2 x float>* [[DEST]] to i64*), i64 [[OLD_I64]], i64 [[NEW_I64]] monotonic monotonic // CHECK: [[FAILED_I64_OLD_VAL:%.+]] = extractvalue { i64, i1 } [[RES]], 0 // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -// CHECK: call{{.*}} @__kmpc_flush( -#pragma omp atomic write acq_rel +#pragma omp atomic write float2x.x = ulv; // CHECK: call i32 @llvm.read_register.i32( // CHECK: sitofp i32 %{{.+}} to double -- GitLab From faace365088a2a3a4cb1050a9facfc34a7a56577 Mon Sep 17 00:00:00 2001 From: Alexandre Ganea Date: Tue, 11 Feb 2020 10:17:15 -0500 Subject: [PATCH 012/142] [Clang][Driver] After default -fintegrated-cc1, make llvm::report_fatal_error() generate preprocessed source + reproducer.sh again. Added a test for #pragma clang __debug llvm_fatal_error to test for the original issue. Added llvm::sys::Process::Exit() and replaced ::exit() in places where it was appropriate. This new function would call the current CrashRecoveryContext if one is running on the same thread; or call ::exit() otherwise. Fixes PR44705. Differential Revision: https://reviews.llvm.org/D73742 --- clang/test/Driver/crash-report.c | 8 +++++ clang/tools/driver/cc1_main.cpp | 3 +- clang/tools/driver/cc1as_main.cpp | 3 +- .../llvm/Support/CrashRecoveryContext.h | 5 ++++ llvm/include/llvm/Support/Process.h | 6 ++++ llvm/lib/Support/CrashRecoveryContext.cpp | 30 +++++++++++++++---- llvm/lib/Support/ErrorHandling.cpp | 3 +- llvm/lib/Support/Process.cpp | 10 ++++++- 8 files changed, 59 insertions(+), 9 deletions(-) diff --git a/clang/test/Driver/crash-report.c b/clang/test/Driver/crash-report.c index 3a77a21c62b4..ceb16cb6e18a 100644 --- a/clang/test/Driver/crash-report.c +++ b/clang/test/Driver/crash-report.c @@ -21,12 +21,20 @@ // RUN: cat %t/crash-report-*.c | FileCheck --check-prefix=CHECKSRC %s // RUN: cat %t/crash-report-*.sh | FileCheck --check-prefix=CHECKSH %s +// RUN: env TMPDIR=%t TEMP=%t TMP=%t RC_DEBUG_OPTIONS=1 \ +// RUN: CC_PRINT_HEADERS=1 CC_LOG_DIAGNOSTICS=1 \ +// RUN: not %clang %s @%t.rsp -DFATAL 2>&1 | FileCheck %s +// RUN: cat %t/crash-report-*.c | FileCheck --check-prefix=CHECKSRC %s +// RUN: cat %t/crash-report-*.sh | FileCheck --check-prefix=CHECKSH %s + // REQUIRES: crash-recovery #ifdef PARSER #pragma clang __debug parser_crash #elif CRASH #pragma clang __debug crash +#elif FATAL +#pragma clang __debug llvm_fatal_error #endif // CHECK: Preprocessed source(s) and associated run script(s) are located at: diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp index b551e9f4cf82..6d1a67f2a4fa 100644 --- a/clang/tools/driver/cc1_main.cpp +++ b/clang/tools/driver/cc1_main.cpp @@ -36,6 +36,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Path.h" +#include "llvm/Support/Process.h" #include "llvm/Support/Signals.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetSelect.h" @@ -69,7 +70,7 @@ static void LLVMErrorHandler(void *UserData, const std::string &Message, // We cannot recover from llvm errors. When reporting a fatal error, exit // with status 70 to generate crash diagnostics. For BSD systems this is // defined as an internal software error. Otherwise, exit with status 1. - exit(GenCrashDiag ? 70 : 1); + llvm::sys::Process::Exit(GenCrashDiag ? 70 : 1); } #ifdef CLANG_HAVE_RLIMITS diff --git a/clang/tools/driver/cc1as_main.cpp b/clang/tools/driver/cc1as_main.cpp index ce390b9f3b17..110f1dc70223 100644 --- a/clang/tools/driver/cc1as_main.cpp +++ b/clang/tools/driver/cc1as_main.cpp @@ -46,6 +46,7 @@ #include "llvm/Support/Host.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/Path.h" +#include "llvm/Support/Process.h" #include "llvm/Support/Signals.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TargetRegistry.h" @@ -555,7 +556,7 @@ static void LLVMErrorHandler(void *UserData, const std::string &Message, Diags.Report(diag::err_fe_error_backend) << Message; // We cannot recover from llvm errors. - exit(1); + sys::Process::Exit(1); } int cc1as_main(ArrayRef Argv, const char *Argv0, void *MainAddr) { diff --git a/llvm/include/llvm/Support/CrashRecoveryContext.h b/llvm/include/llvm/Support/CrashRecoveryContext.h index beeb855c7c58..61a1bd405a4d 100644 --- a/llvm/include/llvm/Support/CrashRecoveryContext.h +++ b/llvm/include/llvm/Support/CrashRecoveryContext.h @@ -97,6 +97,11 @@ public: return RunSafelyOnThread([&]() { Fn(UserData); }, RequestedStackSize); } + /// Explicitly trigger a crash recovery in the current process, and + /// return failure from RunSafely(). This function does not return. + LLVM_ATTRIBUTE_NORETURN + void HandleExit(int RetCode); + /// In case of a crash, this is the crash identifier. int RetCode = 0; diff --git a/llvm/include/llvm/Support/Process.h b/llvm/include/llvm/Support/Process.h index 9444e165e142..bb5c33dfb38d 100644 --- a/llvm/include/llvm/Support/Process.h +++ b/llvm/include/llvm/Support/Process.h @@ -201,6 +201,12 @@ public: /// Get the result of a process wide random number generator. The /// generator will be automatically seeded in non-deterministic fashion. static unsigned GetRandomNumber(); + + /// Equivalent to ::exit(), except when running inside a CrashRecoveryContext. + /// In that case, the control flow will resume after RunSafely(), like for a + /// crash, rather than exiting the current process. + LLVM_ATTRIBUTE_NORETURN + static void Exit(int RetCode); }; } diff --git a/llvm/lib/Support/CrashRecoveryContext.cpp b/llvm/lib/Support/CrashRecoveryContext.cpp index 0cc2d4059fe9..f708da773f4c 100644 --- a/llvm/lib/Support/CrashRecoveryContext.cpp +++ b/llvm/lib/Support/CrashRecoveryContext.cpp @@ -14,9 +14,6 @@ #include "llvm/Support/ThreadLocal.h" #include #include -#ifdef _WIN32 -#include // for GetExceptionInformation -#endif #if LLVM_ON_UNIX #include // EX_IOERR #endif @@ -178,6 +175,9 @@ CrashRecoveryContext::unregisterCleanup(CrashRecoveryContextCleanup *cleanup) { } #if defined(_MSC_VER) + +#include // for GetExceptionInformation + // If _MSC_VER is defined, we must have SEH. Use it if it's available. It's way // better than VEH. Vectored exception handling catches all exceptions happening // on the thread with installed exception handlers, so it can interfere with @@ -203,6 +203,8 @@ static int ExceptionFilter(_EXCEPTION_POINTERS *Except) { } int RetCode = (int)Except->ExceptionRecord->ExceptionCode; + if ((RetCode & 0xF0000000) == 0xE0000000) + RetCode &= ~0xF0000000; // this crash was generated by sys::Process::Exit // Handle the crash const_cast(CRCI)->HandleCrash( @@ -280,10 +282,13 @@ static LONG CALLBACK ExceptionHandler(PEXCEPTION_POINTERS ExceptionInfo) // TODO: We can capture the stack backtrace here and store it on the // implementation if we so choose. + int RetCode = (int)ExceptionInfo->ExceptionRecord->ExceptionCode; + if ((RetCode & 0xF0000000) == 0xE0000000) + RetCode &= ~0xF0000000; // this crash was generated by sys::Process::Exit + // Handle the crash const_cast(CRCI)->HandleCrash( - (int)ExceptionInfo->ExceptionRecord->ExceptionCode, - reinterpret_cast(ExceptionInfo)); + RetCode, reinterpret_cast(ExceptionInfo)); // Note that we don't actually get here because HandleCrash calls // longjmp, which means the HandleCrash function never returns. @@ -416,6 +421,21 @@ bool CrashRecoveryContext::RunSafely(function_ref Fn) { #endif // !_MSC_VER +LLVM_ATTRIBUTE_NORETURN +void CrashRecoveryContext::HandleExit(int RetCode) { +#if defined(_WIN32) + // SEH and VEH + ::RaiseException(0xE0000000 | RetCode, 0, 0, NULL); +#else + // On Unix we don't need to raise an exception, we go directly to + // HandleCrash(), then longjmp will unwind the stack for us. + CrashRecoveryContextImpl *CRCI = (CrashRecoveryContextImpl *)Impl; + assert(CRCI && "Crash recovery context never initialized!"); + CRCI->HandleCrash(RetCode, 0 /*no sig num*/); +#endif + llvm_unreachable("Most likely setjmp wasn't called!"); +} + // FIXME: Portability. static void setThreadBackgroundPriority() { #ifdef __APPLE__ diff --git a/llvm/lib/Support/ErrorHandling.cpp b/llvm/lib/Support/ErrorHandling.cpp index 0f13f7a536f1..a9463024c420 100644 --- a/llvm/lib/Support/ErrorHandling.cpp +++ b/llvm/lib/Support/ErrorHandling.cpp @@ -19,6 +19,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Errc.h" #include "llvm/Support/Error.h" +#include "llvm/Support/Process.h" #include "llvm/Support/Signals.h" #include "llvm/Support/Threading.h" #include "llvm/Support/WindowsError.h" @@ -122,7 +123,7 @@ void llvm::report_fatal_error(const Twine &Reason, bool GenCrashDiag) { // files registered with RemoveFileOnSignal. sys::RunInterruptHandlers(); - exit(1); + sys::Process::Exit(1); } void llvm::install_bad_alloc_error_handler(fatal_error_handler_t handler, diff --git a/llvm/lib/Support/Process.cpp b/llvm/lib/Support/Process.cpp index 0b2d41bcdeca..9e6e233b26ac 100644 --- a/llvm/lib/Support/Process.cpp +++ b/llvm/lib/Support/Process.cpp @@ -13,8 +13,9 @@ #include "llvm/Support/Process.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/Config/llvm-config.h" #include "llvm/Config/config.h" +#include "llvm/Config/llvm-config.h" +#include "llvm/Support/CrashRecoveryContext.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" #include "llvm/Support/Program.h" @@ -88,6 +89,13 @@ static bool coreFilesPrevented = !LLVM_ENABLE_CRASH_DUMPS; bool Process::AreCoreFilesPrevented() { return coreFilesPrevented; } +LLVM_ATTRIBUTE_NORETURN +void Process::Exit(int RetCode) { + if (CrashRecoveryContext *CRC = CrashRecoveryContext::GetCurrent()) + CRC->HandleExit(RetCode); + ::exit(RetCode); +} + // Include the platform-specific parts of this class. #ifdef LLVM_ON_UNIX #include "Unix/Process.inc" -- GitLab From 6b0ed508fa3947ec1f3a1bd87a08b598e98423e3 Mon Sep 17 00:00:00 2001 From: Sjoerd Meijer Date: Tue, 11 Feb 2020 15:14:54 +0000 Subject: [PATCH 013/142] [ARM][MVE] Tail-Predication: recognise (again) active lanes IR pattern A small IR change in calculating the active lanes resulted in no longer recognising tail-predication. Now recognise both an 'add' and 'or' in the expression that calculates the active lanes. Differential Revision: https://reviews.llvm.org/D74394 --- llvm/lib/Target/ARM/MVETailPredication.cpp | 11 ++++++++--- .../Thumb2/LowOverheadLoops/basic-tail-pred.ll | 4 ++-- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/ARM/MVETailPredication.cpp b/llvm/lib/Target/ARM/MVETailPredication.cpp index 151385de7850..9b8c437c053b 100644 --- a/llvm/lib/Target/ARM/MVETailPredication.cpp +++ b/llvm/lib/Target/ARM/MVETailPredication.cpp @@ -260,13 +260,18 @@ bool MVETailPredication::isTailPredicate(TripCountPattern &TCP) { // %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, // <4 x i32> undef, // <4 x i32> zeroinitializer - // %induction = add <4 x i32> %broadcast.splat, + // %induction = [add|or] <4 x i32> %broadcast.splat, // %pred = icmp ule <4 x i32> %induction, %broadcast.splat11 - + // + // Please note that the 'or' is equivalent to the 'and' here, this relies on + // BroadcastSplat being the IV which we know is a phi with 0 start and Lanes + // increment, which is all being checked below. Instruction *BroadcastSplat = nullptr; Constant *Const = nullptr; if (!match(TCP.Induction, - m_Add(m_Instruction(BroadcastSplat), m_Constant(Const)))) + m_Add(m_Instruction(BroadcastSplat), m_Constant(Const))) && + !match(TCP.Induction, + m_Or(m_Instruction(BroadcastSplat), m_Constant(Const)))) return false; // Check that we're adding <0, 1, 2, 3... diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll index 257d950c60fb..ad7920007267 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/basic-tail-pred.ll @@ -32,7 +32,7 @@ vector.body: ; preds = %vector.body, %vecto %tmp14 = phi i32 [ %tmp13, %vector.ph ], [ %tmp15, %vector.body ] %broadcast.splatinsert = insertelement <16 x i32> undef, i32 %index, i32 0 %broadcast.splat = shufflevector <16 x i32> %broadcast.splatinsert, <16 x i32> undef, <16 x i32> zeroinitializer - %induction = add <16 x i32> %broadcast.splat, + %induction = or <16 x i32> %broadcast.splat, %tmp = getelementptr inbounds i8, i8* %a, i32 %index %tmp1 = icmp ule <16 x i32> %induction, %broadcast.splat11 %tmp2 = bitcast i8* %tmp to <16 x i8>* @@ -137,7 +137,7 @@ vector.body: ; preds = %vector.body, %vecto %tmp14 = phi i32 [ %tmp13, %vector.ph ], [ %tmp15, %vector.body ] %broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0 %broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer - %induction = add <4 x i32> %broadcast.splat, + %induction = or <4 x i32> %broadcast.splat, %tmp = getelementptr inbounds i32, i32* %a, i32 %index %tmp1 = icmp ule <4 x i32> %induction, %broadcast.splat11 %tmp2 = bitcast i32* %tmp to <4 x i32>* -- GitLab From aadb635e04854220064b77cc10d0e6772f5492fd Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Tue, 11 Feb 2020 15:06:59 +0000 Subject: [PATCH 014/142] [SCCP] Remove forcedconstant, go to overdefined instead This patch removes forcedconstant to simplify things for the move to ValueLattice, which includes constant ranges, but no forced constants. This patch removes forcedconstant and changes ResolvedUndefsIn to mark instructions with unknown operands as overdefined. This means we do not do simplifications based on undef directly in SCCP any longer, but this seems to hardly come up in practice (see stats below), presumably because InstCombine & others take care of most of the relevant folds already. It is still beneficial to keep ResolvedUndefIn, as it allows us delaying going to overdefined until we propagated all known information. I also built MultiSource, SPEC2000 and SPEC2006 and compared sccp.IPNumInstRemoved and sccp.NumInstRemoved. It looks like the impact is quite low: Tests: 244 Same hash: 238 (filtered out) Remaining: 6 Metric: sccp.IPNumInstRemoved Program base patch diff test-suite...arks/VersaBench/dbms/dbms.test 4.00 3.00 -25.0% test-suite...TimberWolfMC/timberwolfmc.test 38.00 34.00 -10.5% test-suite...006/453.povray/453.povray.test 158.00 155.00 -1.9% test-suite.../CINT2000/176.gcc/176.gcc.test 668.00 668.00 0.0% test-suite.../CINT2006/403.gcc/403.gcc.test 1209.00 1209.00 0.0% test-suite...arks/mafft/pairlocalalign.test 76.00 76.00 0.0% Tests: 244 Same hash: 238 (filtered out) Remaining: 6 Metric: sccp.NumInstRemoved Program base patch diff test-suite...arks/mafft/pairlocalalign.test 185.00 175.00 -5.4% test-suite.../CINT2006/403.gcc/403.gcc.test 2059.00 2056.00 -0.1% test-suite.../CINT2000/176.gcc/176.gcc.test 2358.00 2357.00 -0.0% test-suite...006/453.povray/453.povray.test 317.00 317.00 0.0% test-suite...TimberWolfMC/timberwolfmc.test 12.00 12.00 0.0% Reviewers: davide, efriedma, mssimpso Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D61314 --- llvm/lib/Transforms/Scalar/SCCP.cpp | 248 ++---------------- .../test/Transforms/IPConstantProp/PR16052.ll | 9 +- .../test/Transforms/IPConstantProp/PR26044.ll | 6 +- .../Transforms/SCCP/2006-12-19-UndefBug.ll | 12 +- llvm/test/Transforms/SCCP/apint-bigint2.ll | 24 +- llvm/test/Transforms/SCCP/apint-ipsccp3.ll | 40 ++- llvm/test/Transforms/SCCP/apint-select.ll | 30 ++- .../Transforms/SCCP/ip-constant-ranges.ll | 10 +- llvm/test/Transforms/SCCP/ipsccp-basic.ll | 34 ++- llvm/test/Transforms/SCCP/logical-nuke.ll | 28 +- .../Transforms/SCCP/switch-multiple-undef.ll | 26 +- llvm/test/Transforms/SCCP/ub-shift.ll | 53 ++-- llvm/test/Transforms/SCCP/undef-resolve.ll | 156 ++++++++--- 13 files changed, 330 insertions(+), 346 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/SCCP.cpp b/llvm/lib/Transforms/Scalar/SCCP.cpp index 34f18ec7c121..3e6697e91b9e 100644 --- a/llvm/lib/Transforms/Scalar/SCCP.cpp +++ b/llvm/lib/Transforms/Scalar/SCCP.cpp @@ -85,19 +85,13 @@ class LatticeVal { /// constant - This LLVM Value has a specific constant value. constant, - /// forcedconstant - This LLVM Value was thought to be undef until - /// ResolvedUndefsIn. This is treated just like 'constant', but if merged - /// with another (different) constant, it goes to overdefined, instead of - /// asserting. - forcedconstant, - /// overdefined - This instruction is not known to be constant, and we know /// it has a value. overdefined }; /// Val: This stores the current lattice value along with the Constant* for - /// the constant if this is a 'constant' or 'forcedconstant' value. + /// the constant if this is a 'constant' value. PointerIntPair Val; LatticeValueTy getLatticeValue() const { @@ -109,9 +103,7 @@ public: bool isUnknown() const { return getLatticeValue() == unknown; } - bool isConstant() const { - return getLatticeValue() == constant || getLatticeValue() == forcedconstant; - } + bool isConstant() const { return getLatticeValue() == constant; } bool isOverdefined() const { return getLatticeValue() == overdefined; } @@ -131,26 +123,15 @@ public: /// markConstant - Return true if this is a change in status. bool markConstant(Constant *V) { - if (getLatticeValue() == constant) { // Constant but not forcedconstant. + if (getLatticeValue() == constant) { // Constant assert(getConstant() == V && "Marking constant with different value"); return false; } - if (isUnknown()) { - Val.setInt(constant); - assert(V && "Marking constant with NULL"); - Val.setPointer(V); - } else { - assert(getLatticeValue() == forcedconstant && - "Cannot move from overdefined to constant!"); - // Stay at forcedconstant if the constant is the same. - if (V == getConstant()) return false; - - // Otherwise, we go to overdefined. Assumptions made based on the - // forced value are possibly wrong. Assuming this is another constant - // could expose a contradiction. - Val.setInt(overdefined); - } + assert(isUnknown()); + Val.setInt(constant); + assert(V && "Marking constant with NULL"); + Val.setPointer(V); return true; } @@ -170,12 +151,6 @@ public: return nullptr; } - void markForcedConstant(Constant *V) { - assert(isUnknown() && "Can't force a defined value!"); - Val.setInt(forcedconstant); - Val.setPointer(V); - } - ValueLatticeElement toValueLattice() const { if (isOverdefined()) return ValueLatticeElement::getOverdefined(); @@ -421,7 +396,7 @@ public: } private: - // pushToWorkList - Helper for markConstant/markForcedConstant/markOverdefined + // pushToWorkList - Helper for markConstant/markOverdefined void pushToWorkList(LatticeVal &IV, Value *V) { if (IV.isOverdefined()) return OverdefinedInstWorkList.push_back(V); @@ -443,14 +418,6 @@ private: return markConstant(ValueState[V], V, C); } - void markForcedConstant(Value *V, Constant *C) { - assert(!V->getType()->isStructTy() && "structs should use mergeInValue"); - LatticeVal &IV = ValueState[V]; - IV.markForcedConstant(C); - LLVM_DEBUG(dbgs() << "markForcedConstant: " << *C << ": " << *V << '\n'); - pushToWorkList(IV, V); - } - // markOverdefined - Make a value be marked as "overdefined". If the // value is not already overdefined, add it to the overdefined instruction // work list so that the users of the instruction are updated later. @@ -1032,8 +999,10 @@ void SCCPSolver::visitBinaryOperator(Instruction &I) { } // If something is undef, wait for it to resolve. - if (!V1State.isOverdefined() && !V2State.isOverdefined()) + if (!V1State.isOverdefined() && !V2State.isOverdefined()) { + return; + } // Otherwise, one of our operands is overdefined. Try to produce something // better than overdefined with some tricks. @@ -1449,10 +1418,8 @@ void SCCPSolver::Solve() { /// constraints on the condition of the branch, as that would impact other users /// of the value. /// -/// This scan also checks for values that use undefs, whose results are actually -/// defined. For example, 'zext i8 undef to i32' should produce all zeros -/// conservatively, as "(zext i8 X -> i32) & 0xFF00" must always return zero, -/// even if X isn't defined. +/// This scan also checks for values that use undefs. It conservatively marks +/// them as overdefined. bool SCCPSolver::ResolvedUndefsIn(Function &F) { for (BasicBlock &BB : F) { if (!BBExecutable.count(&BB)) @@ -1475,7 +1442,6 @@ bool SCCPSolver::ResolvedUndefsIn(Function &F) { // tracked as precisely as their operands. if (isa(I) || isa(I)) continue; - // Send the results of everything else to overdefined. We could be // more precise than this but it isn't worth bothering. for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { @@ -1495,195 +1461,13 @@ bool SCCPSolver::ResolvedUndefsIn(Function &F) { // 2. It could be constant-foldable. // Because of the way we solve return values, tracked calls must // never be marked overdefined in ResolvedUndefsIn. - if (CallSite CS = CallSite(&I)) { + if (CallSite CS = CallSite(&I)) if (Function *F = CS.getCalledFunction()) if (TrackedRetVals.count(F)) continue; - // If the call is constant-foldable, we mark it overdefined because - // we do not know what return values are valid. - markOverdefined(&I); - return true; - } - - // extractvalue is safe; check here because the argument is a struct. - if (isa(I)) - continue; - - // Compute the operand LatticeVals, for convenience below. - // Anything taking a struct is conservatively assumed to require - // overdefined markings. - if (I.getOperand(0)->getType()->isStructTy()) { - markOverdefined(&I); - return true; - } - LatticeVal Op0LV = getValueState(I.getOperand(0)); - LatticeVal Op1LV; - if (I.getNumOperands() == 2) { - if (I.getOperand(1)->getType()->isStructTy()) { - markOverdefined(&I); - return true; - } - - Op1LV = getValueState(I.getOperand(1)); - } - // If this is an instructions whose result is defined even if the input is - // not fully defined, propagate the information. - Type *ITy = I.getType(); - switch (I.getOpcode()) { - case Instruction::Add: - case Instruction::Sub: - case Instruction::Trunc: - case Instruction::FPTrunc: - case Instruction::BitCast: - break; // Any undef -> undef - case Instruction::FSub: - case Instruction::FAdd: - case Instruction::FMul: - case Instruction::FDiv: - case Instruction::FRem: - // Floating-point binary operation: be conservative. - if (Op0LV.isUnknown() && Op1LV.isUnknown()) - markForcedConstant(&I, Constant::getNullValue(ITy)); - else - markOverdefined(&I); - return true; - case Instruction::FNeg: - break; // fneg undef -> undef - case Instruction::ZExt: - case Instruction::SExt: - case Instruction::FPToUI: - case Instruction::FPToSI: - case Instruction::FPExt: - case Instruction::PtrToInt: - case Instruction::IntToPtr: - case Instruction::SIToFP: - case Instruction::UIToFP: - // undef -> 0; some outputs are impossible - markForcedConstant(&I, Constant::getNullValue(ITy)); - return true; - case Instruction::Mul: - case Instruction::And: - // Both operands undef -> undef - if (Op0LV.isUnknown() && Op1LV.isUnknown()) - break; - // undef * X -> 0. X could be zero. - // undef & X -> 0. X could be zero. - markForcedConstant(&I, Constant::getNullValue(ITy)); - return true; - case Instruction::Or: - // Both operands undef -> undef - if (Op0LV.isUnknown() && Op1LV.isUnknown()) - break; - // undef | X -> -1. X could be -1. - markForcedConstant(&I, Constant::getAllOnesValue(ITy)); - return true; - case Instruction::Xor: - // undef ^ undef -> 0; strictly speaking, this is not strictly - // necessary, but we try to be nice to people who expect this - // behavior in simple cases - if (Op0LV.isUnknown() && Op1LV.isUnknown()) { - markForcedConstant(&I, Constant::getNullValue(ITy)); - return true; - } - // undef ^ X -> undef - break; - case Instruction::SDiv: - case Instruction::UDiv: - case Instruction::SRem: - case Instruction::URem: - // X / undef -> undef. No change. - // X % undef -> undef. No change. - if (Op1LV.isUnknown()) break; - - // X / 0 -> undef. No change. - // X % 0 -> undef. No change. - if (Op1LV.isConstant() && Op1LV.getConstant()->isZeroValue()) - break; - - // undef / X -> 0. X could be maxint. - // undef % X -> 0. X could be 1. - markForcedConstant(&I, Constant::getNullValue(ITy)); - return true; - case Instruction::AShr: - // X >>a undef -> undef. - if (Op1LV.isUnknown()) break; - - // Shifting by the bitwidth or more is undefined. - if (Op1LV.isConstant()) { - if (auto *ShiftAmt = Op1LV.getConstantInt()) - if (ShiftAmt->getLimitedValue() >= - ShiftAmt->getType()->getScalarSizeInBits()) - break; - } - - // undef >>a X -> 0 - markForcedConstant(&I, Constant::getNullValue(ITy)); - return true; - case Instruction::LShr: - case Instruction::Shl: - // X << undef -> undef. - // X >> undef -> undef. - if (Op1LV.isUnknown()) break; - - // Shifting by the bitwidth or more is undefined. - if (Op1LV.isConstant()) { - if (auto *ShiftAmt = Op1LV.getConstantInt()) - if (ShiftAmt->getLimitedValue() >= - ShiftAmt->getType()->getScalarSizeInBits()) - break; - } - - // undef << X -> 0 - // undef >> X -> 0 - markForcedConstant(&I, Constant::getNullValue(ITy)); - return true; - case Instruction::Select: - Op1LV = getValueState(I.getOperand(1)); - // undef ? X : Y -> X or Y. There could be commonality between X/Y. - if (Op0LV.isUnknown()) { - if (!Op1LV.isConstant()) // Pick the constant one if there is any. - Op1LV = getValueState(I.getOperand(2)); - } else if (Op1LV.isUnknown()) { - // c ? undef : undef -> undef. No change. - Op1LV = getValueState(I.getOperand(2)); - if (Op1LV.isUnknown()) - break; - // Otherwise, c ? undef : x -> x. - } else { - // Leave Op1LV as Operand(1)'s LatticeValue. - } - - if (Op1LV.isConstant()) - markForcedConstant(&I, Op1LV.getConstant()); - else - markOverdefined(&I); - return true; - case Instruction::Load: - // A load here means one of two things: a load of undef from a global, - // a load from an unknown pointer. Either way, having it return undef - // is okay. - break; - case Instruction::ICmp: - // X == undef -> undef. Other comparisons get more complicated. - Op0LV = getValueState(I.getOperand(0)); - Op1LV = getValueState(I.getOperand(1)); - - if ((Op0LV.isUnknown() || Op1LV.isUnknown()) && - cast(&I)->isEquality()) - break; - markOverdefined(&I); - return true; - case Instruction::Call: - case Instruction::Invoke: - case Instruction::CallBr: - llvm_unreachable("Call-like instructions should have be handled early"); - default: - // If we don't know what should happen here, conservatively mark it - // overdefined. - markOverdefined(&I); - return true; - } + markOverdefined(&I); + return true; } // Check to see if we have a branch or switch on an undefined value. If so diff --git a/llvm/test/Transforms/IPConstantProp/PR16052.ll b/llvm/test/Transforms/IPConstantProp/PR16052.ll index 451693f1c90c..a16067fe278a 100644 --- a/llvm/test/Transforms/IPConstantProp/PR16052.ll +++ b/llvm/test/Transforms/IPConstantProp/PR16052.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes ; RUN: opt < %s -S -ipsccp | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" @@ -7,7 +7,9 @@ target triple = "x86_64-unknown-linux-gnu" define i64 @fn2() { ; CHECK-LABEL: define {{[^@]+}}@fn2() ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL2:%.*]] = call i64 @fn1(i64 undef) +; CHECK-NEXT: [[CONV:%.*]] = sext i32 undef to i64 +; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 8, [[CONV]] +; CHECK-NEXT: [[CALL2:%.*]] = call i64 @fn1(i64 [[DIV]]) ; CHECK-NEXT: ret i64 [[CALL2]] ; entry: @@ -21,7 +23,8 @@ define internal i64 @fn1(i64 %p1) { ; CHECK-LABEL: define {{[^@]+}}@fn1 ; CHECK-SAME: (i64 [[P1:%.*]]) ; CHECK-NEXT: entry: -; CHECK-NEXT: [[COND:%.*]] = select i1 undef, i64 undef, i64 undef +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i64 [[P1]], 0 +; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 [[P1]], i64 [[P1]] ; CHECK-NEXT: ret i64 [[COND]] ; entry: diff --git a/llvm/test/Transforms/IPConstantProp/PR26044.ll b/llvm/test/Transforms/IPConstantProp/PR26044.ll index eeb5b87e0a28..8b4f2590b9f8 100644 --- a/llvm/test/Transforms/IPConstantProp/PR26044.ll +++ b/llvm/test/Transforms/IPConstantProp/PR26044.ll @@ -11,7 +11,8 @@ define void @fn2(i32* %P) { ; CHECK: for.cond1: ; CHECK-NEXT: br i1 false, label [[IF_END]], label [[IF_END]] ; CHECK: if.end: -; CHECK-NEXT: [[CALL:%.*]] = call i32 @fn1(i32 undef) +; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* null, align 4 +; CHECK-NEXT: [[CALL:%.*]] = call i32 @fn1(i32 [[TMP0]]) ; CHECK-NEXT: store i32 [[CALL]], i32* [[P]] ; CHECK-NEXT: br label [[FOR_COND1:%.*]] ; @@ -33,7 +34,8 @@ define internal i32 @fn1(i32 %p1) { ; CHECK-LABEL: define {{[^@]+}}@fn1 ; CHECK-SAME: (i32 [[P1:%.*]]) ; CHECK-NEXT: entry: -; CHECK-NEXT: [[COND:%.*]] = select i1 undef, i32 undef, i32 undef +; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[P1]], 0 +; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 [[P1]], i32 [[P1]] ; CHECK-NEXT: ret i32 [[COND]] ; entry: diff --git a/llvm/test/Transforms/SCCP/2006-12-19-UndefBug.ll b/llvm/test/Transforms/SCCP/2006-12-19-UndefBug.ll index ede1a32c5f7a..4bd096e0a656 100644 --- a/llvm/test/Transforms/SCCP/2006-12-19-UndefBug.ll +++ b/llvm/test/Transforms/SCCP/2006-12-19-UndefBug.ll @@ -1,8 +1,12 @@ -; RUN: opt < %s -sccp -S | \ -; RUN: grep "ret i1 false" +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -sccp -S | FileCheck %s define i1 @foo() { - %X = and i1 false, undef ; [#uses=1] - ret i1 %X +; CHECK-LABEL: @foo( +; CHECK-NEXT: [[X:%.*]] = and i1 false, undef +; CHECK-NEXT: ret i1 [[X]] +; + %X = and i1 false, undef ; [#uses=1] + ret i1 %X } diff --git a/llvm/test/Transforms/SCCP/apint-bigint2.ll b/llvm/test/Transforms/SCCP/apint-bigint2.ll index 5277d9fa5c6e..7d75240a0d8e 100644 --- a/llvm/test/Transforms/SCCP/apint-bigint2.ll +++ b/llvm/test/Transforms/SCCP/apint-bigint2.ll @@ -18,7 +18,13 @@ define i101 @array() { } ; CHECK-LABEL: @large_aggregate -; CHECK-NEXT: ret i101 undef +; CHECK-NEXT: %B = load i101, i101* undef +; CHECK-NEXT: %D = and i101 %B, 1 +; CHECK-NEXT: %DD = or i101 %D, 1 +; CHECK-NEXT: %G = getelementptr i101, i101* getelementptr inbounds ([6 x i101], [6 x i101]* @Y, i32 0, i32 5), i101 %DD +; CHECK-NEXT: %L3 = load i101, i101* %G +; CHECK-NEXT: ret i101 %L3 +; define i101 @large_aggregate() { %B = load i101, i101* undef %D = and i101 %B, 1 @@ -29,6 +35,22 @@ define i101 @large_aggregate() { ret i101 %L3 } +; CHECK-LABEL: define i101 @large_aggregate_2() { +; CHECK-NEXT: %D = and i101 undef, 1 +; CHECK-NEXT: %DD = or i101 %D, 1 +; CHECK-NEXT: %G = getelementptr i101, i101* getelementptr inbounds ([6 x i101], [6 x i101]* @Y, i32 0, i32 5), i101 %DD +; CHECK-NEXT: %L3 = load i101, i101* %G +; CHECK-NEXT: ret i101 %L3 +; +define i101 @large_aggregate_2() { + %D = and i101 undef, 1 + %DD = or i101 %D, 1 + %F = getelementptr [6 x i101], [6 x i101]* @Y, i32 0, i32 5 + %G = getelementptr i101, i101* %F, i101 %DD + %L3 = load i101, i101* %G + ret i101 %L3 +} + ; CHECK-LABEL: @index_too_large ; CHECK-NEXT: store i101* getelementptr (i101, i101* getelementptr ([6 x i101], [6 x i101]* @Y, i32 0, i32 -1), i101 9224497936761618431), i101** undef ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/SCCP/apint-ipsccp3.ll b/llvm/test/Transforms/SCCP/apint-ipsccp3.ll index c99ae5820b2d..4ba1f8db30ba 100644 --- a/llvm/test/Transforms/SCCP/apint-ipsccp3.ll +++ b/llvm/test/Transforms/SCCP/apint-ipsccp3.ll @@ -1,23 +1,39 @@ -; RUN: opt < %s -ipsccp -S | not grep global +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -ipsccp -S | FileCheck %s @G = internal global i66 undef - define void @foo() { - %X = load i66, i66* @G - store i66 %X, i66* @G - ret void +; CHECK-LABEL: @foo( +; CHECK-NEXT: [[X:%.*]] = load i66, i66* @G +; CHECK-NEXT: store i66 [[X]], i66* @G +; CHECK-NEXT: ret void +; + %X = load i66, i66* @G + store i66 %X, i66* @G + ret void } define i66 @bar() { - %V = load i66, i66* @G - %C = icmp eq i66 %V, 17 - br i1 %C, label %T, label %F +; CHECK-LABEL: @bar( +; CHECK-NEXT: [[V:%.*]] = load i66, i66* @G +; CHECK-NEXT: [[C:%.*]] = icmp eq i66 [[V]], 17 +; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] +; CHECK: T: +; CHECK-NEXT: store i66 17, i66* @G +; CHECK-NEXT: ret i66 17 +; CHECK: F: +; CHECK-NEXT: store i66 123, i66* @G +; CHECK-NEXT: ret i66 0 +; + %V = load i66, i66* @G + %C = icmp eq i66 %V, 17 + br i1 %C, label %T, label %F T: - store i66 17, i66* @G - ret i66 %V + store i66 17, i66* @G + ret i66 %V F: - store i66 123, i66* @G - ret i66 0 + store i66 123, i66* @G + ret i66 0 } diff --git a/llvm/test/Transforms/SCCP/apint-select.ll b/llvm/test/Transforms/SCCP/apint-select.ll index 893331ea9867..d797c7a4d43c 100644 --- a/llvm/test/Transforms/SCCP/apint-select.ll +++ b/llvm/test/Transforms/SCCP/apint-select.ll @@ -1,21 +1,29 @@ -; RUN: opt < %s -sccp -S | not grep select +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -sccp -S | FileCheck %s @A = constant i32 10 define i712 @test1() { - %P = getelementptr i32, i32* @A, i32 0 - %B = ptrtoint i32* %P to i64 - %BB = and i64 %B, undef - %C = icmp sge i64 %BB, 0 - %X = select i1 %C, i712 0, i712 1 - ret i712 %X +; CHECK-LABEL: @test1( +; CHECK-NEXT: [[BB:%.*]] = and i64 ptrtoint (i32* @A to i64), undef +; CHECK-NEXT: [[C:%.*]] = icmp sge i64 [[BB]], 0 +; CHECK-NEXT: [[X:%.*]] = select i1 [[C]], i712 0, i712 1 +; CHECK-NEXT: ret i712 [[X]] +; + %P = getelementptr i32, i32* @A, i32 0 + %B = ptrtoint i32* %P to i64 + %BB = and i64 %B, undef + %C = icmp sge i64 %BB, 0 + %X = select i1 %C, i712 0, i712 1 + ret i712 %X } define i712 @test2(i1 %C) { - %X = select i1 %C, i712 0, i712 undef - ret i712 %X +; CHECK-LABEL: @test2( +; CHECK-NEXT: ret i712 0 +; + %X = select i1 %C, i712 0, i712 undef + ret i712 %X } - - diff --git a/llvm/test/Transforms/SCCP/ip-constant-ranges.ll b/llvm/test/Transforms/SCCP/ip-constant-ranges.ll index 426e3279661f..08de8dba4046 100644 --- a/llvm/test/Transforms/SCCP/ip-constant-ranges.ll +++ b/llvm/test/Transforms/SCCP/ip-constant-ranges.ll @@ -141,10 +141,12 @@ define double @test_struct({ double, double } %test) { ; Constant range for %x is [47, 302) ; CHECK-LABEL: @f5 ; CHECK-NEXT: entry: -; CHECK-NEXT: %cmp = icmp sgt i32 %x, undef -; CHECK-NEXT: %res1 = select i1 %cmp, i32 1, i32 2 -; CHECK-NEXT: %res = add i32 %res1, 3 -; CHECK-NEXT: ret i32 %res +; CHECK-NEXT: %cmp = icmp sgt i32 %x, undef +; CHECK-NEXT: %cmp2 = icmp ne i32 undef, %x +; CHECK-NEXT: %res1 = select i1 %cmp, i32 1, i32 2 +; CHECK-NEXT: %res2 = select i1 %cmp2, i32 3, i32 4 +; CHECK-NEXT: %res = add i32 %res1, %res2 +; CHECK-NEXT: ret i32 %res define internal i32 @f5(i32 %x) { entry: %cmp = icmp sgt i32 %x, undef diff --git a/llvm/test/Transforms/SCCP/ipsccp-basic.ll b/llvm/test/Transforms/SCCP/ipsccp-basic.ll index b1660b545652..795a73f1d907 100644 --- a/llvm/test/Transforms/SCCP/ipsccp-basic.ll +++ b/llvm/test/Transforms/SCCP/ipsccp-basic.ll @@ -56,7 +56,9 @@ define void @test3a() { ret void } ; CHECK-LABEL: define void @test3a( -; CHECK-NEXT: ret void +; CHECK-NEXT: %X = load i32, i32* @G +; CHECK-NEXT: store i32 %X, i32* @G +; CHECK-NEXT: ret void define i32 @test3b() { @@ -71,9 +73,17 @@ F: ret i32 0 } ; CHECK-LABEL: define i32 @test3b( -; CHECK-NOT: store -; CHECK: ret i32 0 +; CHECK-NEXT: %V = load i32, i32* @G +; CHECK-NEXT: %C = icmp eq i32 %V, 17 +; CHECK-NEXT: br i1 %C, label %T, label %F + +; CHECK-LABEL: T: +; CHECK-NEXT: store i32 17, i32* @G +; CHECK-NEXT: ret i32 17 +; CHECK-LABEL: F: +; CHECK-NEXT: store i32 123, i32* @G +; CHECK-NEXT: ret i32 0 ;;======================== test4 @@ -226,8 +236,11 @@ define i32 @test10a() nounwind { entry: %call = call i32 @test10b(i32 undef) ret i32 %call + ; CHECK-LABEL: define i32 @test10a( -; CHECK: ret i32 0 +; CHECK-NEXT: entry: +; CHECK-NEXT: %call = call i32 @test10b(i32 undef) +; CHECK-NEXT: ret i32 %call } define internal i32 @test10b(i32 %x) nounwind { @@ -235,7 +248,9 @@ entry: %r = and i32 %x, 1 ret i32 %r ; CHECK-LABEL: define internal i32 @test10b( -; CHECK: ret i32 undef +; CHECK-NEXT: entry: +; CHECK-NEXT: %r = and i32 undef, 1 +; CHECK-NEXT: ret i32 %r } ;;======================== test11 @@ -244,7 +259,8 @@ define i64 @test11a() { %xor = xor i64 undef, undef ret i64 %xor ; CHECK-LABEL: define i64 @test11a -; CHECK: ret i64 0 +; CHECK-NEXT: %xor = xor i64 undef, undef +; CHECK-NEXT: ret i64 %xor } define i64 @test11b() { @@ -252,9 +268,9 @@ define i64 @test11b() { %call2 = call i64 @llvm.ctpop.i64(i64 %call1) ret i64 %call2 ; CHECK-LABEL: define i64 @test11b -; CHECK: %[[call1:.*]] = call i64 @test11a() -; CHECK-NOT: call i64 @llvm.ctpop.i64 -; CHECK-NEXT: ret i64 0 +; CHECK-NEXT: [[call1:%.*]] = call i64 @test11a() +; CHECK-NEXT: [[call2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[call1]]) +; CHECK-NEXT: ret i64 [[call2]] } declare i64 @llvm.ctpop.i64(i64) diff --git a/llvm/test/Transforms/SCCP/logical-nuke.ll b/llvm/test/Transforms/SCCP/logical-nuke.ll index 6ca16de4489b..5152e126e8fa 100644 --- a/llvm/test/Transforms/SCCP/logical-nuke.ll +++ b/llvm/test/Transforms/SCCP/logical-nuke.ll @@ -1,39 +1,47 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -sccp -S | FileCheck %s ; Test that SCCP has basic knowledge of when and/or/mul nuke overdefined values. -; CHECK-LABEL: test -; CHECK: ret i32 0 define i32 @test(i32 %X) { +; CHECK-LABEL: @test( +; CHECK-NEXT: ret i32 0 +; %Y = and i32 %X, 0 ret i32 %Y } -; CHECK-LABEL: test2 -; CHECK: ret i32 -1 define i32 @test2(i32 %X) { +; CHECK-LABEL: @test2( +; CHECK-NEXT: ret i32 -1 +; %Y = or i32 -1, %X ret i32 %Y } -; CHECK-LABEL: test3 -; CHECK: ret i32 0 define i32 @test3(i32 %X) { +; CHECK-LABEL: @test3( +; CHECK-NEXT: [[Y:%.*]] = and i32 undef, [[X:%.*]] +; CHECK-NEXT: ret i32 [[Y]] +; %Y = and i32 undef, %X ret i32 %Y } -; CHECK-LABEL: test4 -; CHECK: ret i32 -1 define i32 @test4(i32 %X) { +; CHECK-LABEL: @test4( +; CHECK-NEXT: [[Y:%.*]] = or i32 [[X:%.*]], undef +; CHECK-NEXT: ret i32 [[Y]] +; %Y = or i32 %X, undef ret i32 %Y } ; X * 0 = 0 even if X is overdefined. -; CHECK-LABEL: test5 -; CHECK: ret i32 0 define i32 @test5(i32 %foo) { +; CHECK-LABEL: @test5( +; CHECK-NEXT: ret i32 0 +; %patatino = mul i32 %foo, 0 ret i32 %patatino } diff --git a/llvm/test/Transforms/SCCP/switch-multiple-undef.ll b/llvm/test/Transforms/SCCP/switch-multiple-undef.ll index 027c9c0c9ba7..df99e4eee7d2 100644 --- a/llvm/test/Transforms/SCCP/switch-multiple-undef.ll +++ b/llvm/test/Transforms/SCCP/switch-multiple-undef.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -ipsccp < %s | FileCheck %s declare void @foo() @@ -5,9 +6,25 @@ declare void @goo() declare void @patatino() define void @test1(i32 %t) { +; CHECK-LABEL: @test1( +; CHECK-NEXT: [[CHOICE:%.*]] = icmp eq i32 undef, -1 +; CHECK-NEXT: switch i1 [[CHOICE]], label [[FIRST:%.*]] [ +; CHECK-NEXT: i1 false, label [[SECOND:%.*]] +; CHECK-NEXT: i1 true, label [[THIRD:%.*]] +; CHECK-NEXT: ] +; CHECK: first: +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: ret void +; CHECK: second: +; CHECK-NEXT: call void @goo() +; CHECK-NEXT: ret void +; CHECK: third: +; CHECK-NEXT: call void @patatino() +; CHECK-NEXT: ret void +; %choice = icmp eq i32 undef, -1 switch i1 %choice, label %first [i1 0, label %second - i1 1, label %third] + i1 1, label %third] first: call void @foo() ret void @@ -18,10 +35,3 @@ third: call void @patatino() ret void } - -; CHECK: define void @test1(i32 %t) { -; CHECK-NEXT: br label %second -; CHECK: second: -; CHECK-NEXT: call void @goo() -; CHECK-NEXT: ret void -; CHECK-NEXT: } diff --git a/llvm/test/Transforms/SCCP/ub-shift.ll b/llvm/test/Transforms/SCCP/ub-shift.ll index 3fb2d97457d9..6e15d6b2bccd 100644 --- a/llvm/test/Transforms/SCCP/ub-shift.ll +++ b/llvm/test/Transforms/SCCP/ub-shift.ll @@ -1,68 +1,89 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -sccp -S | FileCheck %s -; CHECK-LABEL: shift_undef_64 define void @shift_undef_64(i64* %p) { +; CHECK-LABEL: @shift_undef_64( +; CHECK-NEXT: [[R1:%.*]] = lshr i64 -1, 4294967296 +; CHECK-NEXT: store i64 [[R1]], i64* [[P:%.*]] +; CHECK-NEXT: [[R2:%.*]] = ashr i64 -1, 4294967297 +; CHECK-NEXT: store i64 [[R2]], i64* [[P]] +; CHECK-NEXT: [[R3:%.*]] = shl i64 -1, 4294967298 +; CHECK-NEXT: store i64 [[R3]], i64* [[P]] +; CHECK-NEXT: ret void +; %r1 = lshr i64 -1, 4294967296 ; 2^32 - ; CHECK: store i64 undef store i64 %r1, i64* %p %r2 = ashr i64 -1, 4294967297 ; 2^32 + 1 - ; CHECK: store i64 undef store i64 %r2, i64* %p %r3 = shl i64 -1, 4294967298 ; 2^32 + 2 - ; CHECK: store i64 undef store i64 %r3, i64* %p ret void } -; CHECK-LABEL: shift_undef_65 define void @shift_undef_65(i65* %p) { +; CHECK-LABEL: @shift_undef_65( +; CHECK-NEXT: [[R1:%.*]] = lshr i65 2, -18446744073709551615 +; CHECK-NEXT: store i65 [[R1]], i65* [[P:%.*]] +; CHECK-NEXT: [[R2:%.*]] = ashr i65 4, -18446744073709551615 +; CHECK-NEXT: store i65 [[R2]], i65* [[P]] +; CHECK-NEXT: [[R3:%.*]] = shl i65 1, -18446744073709551615 +; CHECK-NEXT: store i65 [[R3]], i65* [[P]] +; CHECK-NEXT: ret void +; %r1 = lshr i65 2, 18446744073709551617 - ; CHECK: store i65 undef store i65 %r1, i65* %p %r2 = ashr i65 4, 18446744073709551617 - ; CHECK: store i65 undef store i65 %r2, i65* %p %r3 = shl i65 1, 18446744073709551617 - ; CHECK: store i65 undef store i65 %r3, i65* %p ret void } -; CHECK-LABEL: shift_undef_256 define void @shift_undef_256(i256* %p) { +; CHECK-LABEL: @shift_undef_256( +; CHECK-NEXT: [[R1:%.*]] = lshr i256 2, 18446744073709551617 +; CHECK-NEXT: store i256 [[R1]], i256* [[P:%.*]] +; CHECK-NEXT: [[R2:%.*]] = ashr i256 4, 18446744073709551618 +; CHECK-NEXT: store i256 [[R2]], i256* [[P]] +; CHECK-NEXT: [[R3:%.*]] = shl i256 1, 18446744073709551619 +; CHECK-NEXT: store i256 [[R3]], i256* [[P]] +; CHECK-NEXT: ret void +; %r1 = lshr i256 2, 18446744073709551617 - ; CHECK: store i256 undef store i256 %r1, i256* %p %r2 = ashr i256 4, 18446744073709551618 - ; CHECK: store i256 undef store i256 %r2, i256* %p %r3 = shl i256 1, 18446744073709551619 - ; CHECK: store i256 undef store i256 %r3, i256* %p ret void } -; CHECK-LABEL: shift_undef_511 define void @shift_undef_511(i511* %p) { +; CHECK-LABEL: @shift_undef_511( +; CHECK-NEXT: [[R1:%.*]] = lshr i511 -1, 1208925819614629174706276 +; CHECK-NEXT: store i511 [[R1]], i511* [[P:%.*]] +; CHECK-NEXT: [[R2:%.*]] = ashr i511 -2, 1208925819614629174706200 +; CHECK-NEXT: store i511 [[R2]], i511* [[P]] +; CHECK-NEXT: [[R3:%.*]] = shl i511 -3, 1208925819614629174706180 +; CHECK-NEXT: store i511 [[R3]], i511* [[P]] +; CHECK-NEXT: ret void +; %r1 = lshr i511 -1, 1208925819614629174706276 ; 2^80 + 100 - ; CHECK: store i511 undef store i511 %r1, i511* %p %r2 = ashr i511 -2, 1208925819614629174706200 - ; CHECK: store i511 undef store i511 %r2, i511* %p %r3 = shl i511 -3, 1208925819614629174706180 - ; CHECK: store i511 undef store i511 %r3, i511* %p ret void diff --git a/llvm/test/Transforms/SCCP/undef-resolve.ll b/llvm/test/Transforms/SCCP/undef-resolve.ll index 7fdcd556dae6..e2a4268596f4 100644 --- a/llvm/test/Transforms/SCCP/undef-resolve.ll +++ b/llvm/test/Transforms/SCCP/undef-resolve.ll @@ -1,12 +1,15 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -sccp -S < %s | FileCheck %s ; PR6940 define double @test1() { +; CHECK-LABEL: @test1( +; CHECK-NEXT: [[T:%.*]] = sitofp i32 undef to double +; CHECK-NEXT: ret double [[T]] +; %t = sitofp i32 undef to double ret double %t -; CHECK-LABEL: @test1( -; CHECK: ret double 0.0 } @@ -14,6 +17,72 @@ define double @test1() { ; Check that lots of stuff doesn't get turned into undef. define i32 @test2() nounwind readnone ssp { ; CHECK-LABEL: @test2( +; CHECK-NEXT: init: +; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER:%.*]] +; CHECK: control.outer.loopexit.us-lcssa: +; CHECK-NEXT: br label [[CONTROL_OUTER_LOOPEXIT:%.*]] +; CHECK: control.outer.loopexit: +; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER_BACKEDGE:%.*]] +; CHECK: control.outer.outer: +; CHECK-NEXT: [[SWITCHCOND_0_PH_PH:%.*]] = phi i32 [ 2, [[INIT:%.*]] ], [ 3, [[CONTROL_OUTER_OUTER_BACKEDGE]] ] +; CHECK-NEXT: [[I_0_PH_PH:%.*]] = phi i32 [ undef, [[INIT]] ], [ [[I_0_PH_PH_BE:%.*]], [[CONTROL_OUTER_OUTER_BACKEDGE]] ] +; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[I_0_PH_PH]], 0 +; CHECK-NEXT: br i1 [[TMP4]], label [[CONTROL_OUTER_OUTER_SPLIT_US:%.*]], label [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE:%.*]] +; CHECK: control.outer.outer.control.outer.outer.split_crit_edge: +; CHECK-NEXT: br label [[CONTROL_OUTER:%.*]] +; CHECK: control.outer.outer.split.us: +; CHECK-NEXT: br label [[CONTROL_OUTER_US:%.*]] +; CHECK: control.outer.us: +; CHECK-NEXT: [[A_0_PH_US:%.*]] = phi i32 [ [[SWITCHCOND_0_US:%.*]], [[BB3_US:%.*]] ], [ 4, [[CONTROL_OUTER_OUTER_SPLIT_US]] ] +; CHECK-NEXT: [[SWITCHCOND_0_PH_US:%.*]] = phi i32 [ [[A_0_PH_US]], [[BB3_US]] ], [ [[SWITCHCOND_0_PH_PH]], [[CONTROL_OUTER_OUTER_SPLIT_US]] ] +; CHECK-NEXT: br label [[CONTROL_US:%.*]] +; CHECK: bb3.us: +; CHECK-NEXT: br label [[CONTROL_OUTER_US]] +; CHECK: bb0.us: +; CHECK-NEXT: br label [[CONTROL_US]] +; CHECK: control.us: +; CHECK-NEXT: [[SWITCHCOND_0_US]] = phi i32 [ [[A_0_PH_US]], [[BB0_US:%.*]] ], [ [[SWITCHCOND_0_PH_US]], [[CONTROL_OUTER_US]] ] +; CHECK-NEXT: switch i32 [[SWITCHCOND_0_US]], label [[CONTROL_OUTER_LOOPEXIT_US_LCSSA_US:%.*]] [ +; CHECK-NEXT: i32 0, label [[BB0_US]] +; CHECK-NEXT: i32 1, label [[BB1_US_LCSSA_US:%.*]] +; CHECK-NEXT: i32 3, label [[BB3_US]] +; CHECK-NEXT: i32 4, label [[BB4_US_LCSSA_US:%.*]] +; CHECK-NEXT: ] +; CHECK: control.outer.loopexit.us-lcssa.us: +; CHECK-NEXT: br label [[CONTROL_OUTER_LOOPEXIT]] +; CHECK: bb1.us-lcssa.us: +; CHECK-NEXT: br label [[BB1:%.*]] +; CHECK: bb4.us-lcssa.us: +; CHECK-NEXT: br label [[BB4:%.*]] +; CHECK: control.outer: +; CHECK-NEXT: [[A_0_PH:%.*]] = phi i32 [ [[NEXTID17:%.*]], [[BB3:%.*]] ], [ 4, [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE]] ] +; CHECK-NEXT: [[SWITCHCOND_0_PH:%.*]] = phi i32 [ 0, [[BB3]] ], [ [[SWITCHCOND_0_PH_PH]], [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE]] ] +; CHECK-NEXT: br label [[CONTROL:%.*]] +; CHECK: control: +; CHECK-NEXT: [[SWITCHCOND_0:%.*]] = phi i32 [ [[A_0_PH]], [[BB0:%.*]] ], [ [[SWITCHCOND_0_PH]], [[CONTROL_OUTER]] ] +; CHECK-NEXT: switch i32 [[SWITCHCOND_0]], label [[CONTROL_OUTER_LOOPEXIT_US_LCSSA:%.*]] [ +; CHECK-NEXT: i32 0, label [[BB0]] +; CHECK-NEXT: i32 1, label [[BB1_US_LCSSA:%.*]] +; CHECK-NEXT: i32 3, label [[BB3]] +; CHECK-NEXT: i32 4, label [[BB4_US_LCSSA:%.*]] +; CHECK-NEXT: ] +; CHECK: bb4.us-lcssa: +; CHECK-NEXT: br label [[BB4]] +; CHECK: bb4: +; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER_BACKEDGE]] +; CHECK: control.outer.outer.backedge: +; CHECK-NEXT: [[I_0_PH_PH_BE]] = phi i32 [ 1, [[BB4]] ], [ 0, [[CONTROL_OUTER_LOOPEXIT]] ] +; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER]] +; CHECK: bb3: +; CHECK-NEXT: [[NEXTID17]] = add i32 [[SWITCHCOND_0]], -2 +; CHECK-NEXT: br label [[CONTROL_OUTER]] +; CHECK: bb0: +; CHECK-NEXT: br label [[CONTROL]] +; CHECK: bb1.us-lcssa: +; CHECK-NEXT: br label [[BB1]] +; CHECK: bb1: +; CHECK-NEXT: ret i32 0 +; init: br label %control.outer.outer @@ -46,16 +115,13 @@ bb3.us: ; preds = %control.us bb0.us: ; preds = %control.us br label %control.us -; CHECK: control.us: ; preds = %bb0.us, %control.outer.us -; CHECK-NEXT: %switchCond.0.us = phi i32 -; CHECK-NEXT: switch i32 %switchCond.0.us control.us: ; preds = %bb0.us, %control.outer.us %switchCond.0.us = phi i32 [ %A.0.ph.us, %bb0.us ], [ %switchCond.0.ph.us, %control.outer.us ] ; [#uses=2] switch i32 %switchCond.0.us, label %control.outer.loopexit.us-lcssa.us [ - i32 0, label %bb0.us - i32 1, label %bb1.us-lcssa.us - i32 3, label %bb3.us - i32 4, label %bb4.us-lcssa.us + i32 0, label %bb0.us + i32 1, label %bb1.us-lcssa.us + i32 3, label %bb3.us + i32 4, label %bb4.us-lcssa.us ] control.outer.loopexit.us-lcssa.us: ; preds = %control.us @@ -75,10 +141,10 @@ control.outer: ; preds = %bb3, %control.outer control: ; preds = %bb0, %control.outer %switchCond.0 = phi i32 [ %A.0.ph, %bb0 ], [ %switchCond.0.ph, %control.outer ] ; [#uses=2] switch i32 %switchCond.0, label %control.outer.loopexit.us-lcssa [ - i32 0, label %bb0 - i32 1, label %bb1.us-lcssa - i32 3, label %bb3 - i32 4, label %bb4.us-lcssa + i32 0, label %bb0 + i32 1, label %bb1.us-lcssa + i32 3, label %bb3 + i32 4, label %bb4.us-lcssa ] bb4.us-lcssa: ; preds = %control @@ -108,83 +174,105 @@ bb1: ; preds = %bb1.us-lcssa, %bb1. ; Make sure SCCP honors the xor "idiom" ; rdar://9956541 define i32 @test3() { +; CHECK-LABEL: @test3( +; CHECK-NEXT: [[T:%.*]] = xor i32 undef, undef +; CHECK-NEXT: ret i32 [[T]] +; %t = xor i32 undef, undef ret i32 %t -; CHECK-LABEL: @test3( -; CHECK: ret i32 0 } ; Be conservative with FP ops define double @test4(double %x) { +; CHECK-LABEL: @test4( +; CHECK-NEXT: [[T:%.*]] = fadd double [[X:%.*]], undef +; CHECK-NEXT: ret double [[T]] +; %t = fadd double %x, undef ret double %t -; CHECK-LABEL: @test4( -; CHECK: fadd double %x, undef } ; Make sure casts produce a possible value define i32 @test5() { +; CHECK-LABEL: @test5( +; CHECK-NEXT: [[T:%.*]] = sext i8 undef to i32 +; CHECK-NEXT: ret i32 [[T]] +; %t = sext i8 undef to i32 ret i32 %t -; CHECK-LABEL: @test5( -; CHECK: ret i32 0 } ; Make sure ashr produces a possible value define i32 @test6() { +; CHECK-LABEL: @test6( +; CHECK-NEXT: [[T:%.*]] = ashr i32 undef, 31 +; CHECK-NEXT: ret i32 [[T]] +; %t = ashr i32 undef, 31 ret i32 %t -; CHECK-LABEL: @test6( -; CHECK: ret i32 0 } ; Make sure lshr produces a possible value define i32 @test7() { +; CHECK-LABEL: @test7( +; CHECK-NEXT: [[T:%.*]] = lshr i32 undef, 31 +; CHECK-NEXT: ret i32 [[T]] +; %t = lshr i32 undef, 31 ret i32 %t -; CHECK-LABEL: @test7( -; CHECK: ret i32 0 } ; icmp eq with undef simplifies to undef define i1 @test8() { +; CHECK-LABEL: @test8( +; CHECK-NEXT: [[T:%.*]] = icmp eq i32 undef, -1 +; CHECK-NEXT: ret i1 [[T]] +; %t = icmp eq i32 undef, -1 ret i1 %t -; CHECK-LABEL: @test8( -; CHECK: ret i1 undef } ; Make sure we don't conclude that relational comparisons simplify to undef define i1 @test9() { +; CHECK-LABEL: @test9( +; CHECK-NEXT: [[T:%.*]] = icmp ugt i32 undef, -1 +; CHECK-NEXT: ret i1 [[T]] +; %t = icmp ugt i32 undef, -1 ret i1 %t -; CHECK-LABEL: @test9( -; CHECK: icmp ugt } ; Make sure we handle extractvalue -define i64 @test10() { +define i64 @test10() { +; CHECK-LABEL: @test10( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[E:%.*]] = extractvalue { i64, i64 } undef, 1 +; CHECK-NEXT: ret i64 [[E]] +; entry: %e = extractvalue { i64, i64 } undef, 1 ret i64 %e -; CHECK-LABEL: @test10( -; CHECK: ret i64 undef } @GV = external global i32 define i32 @test11(i1 %tobool) { +; CHECK-LABEL: @test11( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SHR4:%.*]] = ashr i32 undef, zext (i1 icmp eq (i32* bitcast (i32 (i1)* @test11 to i32*), i32* @GV) to i32) +; CHECK-NEXT: ret i32 [[SHR4]] +; entry: %shr4 = ashr i32 undef, zext (i1 icmp eq (i32* bitcast (i32 (i1)* @test11 to i32*), i32* @GV) to i32) ret i32 %shr4 -; CHECK-LABEL: @test11( -; CHECK: ret i32 0 } ; Test unary ops define double @test12(double %x) { +; CHECK-LABEL: @test12( +; CHECK-NEXT: [[T:%.*]] = fneg double undef +; CHECK-NEXT: ret double [[T]] +; %t = fneg double undef ret double %t -; CHECK-LABEL: @test12( -; CHECK: double undef } -- GitLab From dd11c8fb0d07b346b8eaba5a023d58203c367041 Mon Sep 17 00:00:00 2001 From: Justin Lebar Date: Mon, 10 Feb 2020 19:38:44 -0800 Subject: [PATCH 015/142] Fix SFINAE in JSON.h constructor. Summary: This used std::enable_if without referencing ::type. Changed to use std::enable_if_t. Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74381 --- llvm/include/llvm/Support/JSON.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/include/llvm/Support/JSON.h b/llvm/include/llvm/Support/JSON.h index f0bab51ad4d9..ad746b62c2a3 100644 --- a/llvm/include/llvm/Support/JSON.h +++ b/llvm/include/llvm/Support/JSON.h @@ -354,7 +354,7 @@ public: } // Serializable types: with a toJSON(const T&)->Value function, found by ADL. template ::value>, Value * = nullptr> Value(const T &V) : Value(toJSON(V)) {} -- GitLab From fb45968e6285127a18d4d046613b62f125339576 Mon Sep 17 00:00:00 2001 From: Justin Lebar Date: Mon, 10 Feb 2020 15:49:14 -0800 Subject: [PATCH 016/142] Use C++14-style return type deduction in LLVM. Summary: Simplifies the C++11-style "-> decltype(...)" return-type deduction. Note that you have to be careful about whether the function return type is `auto` or `decltype(auto)`. The difference is that bare `auto` strips const and reference, just like lambda return type deduction. In some cases that's what we want (or more likely, we know that the return type is a value type), but whenever we're wrapping a templated function which might return a reference, we need to be sure that the return type is decltype(auto). No functional change. Subscribers: dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74383 --- llvm/include/llvm/ADT/STLExtras.h | 97 +++++++------------ llvm/include/llvm/ADT/fallible_iterator.h | 6 +- llvm/include/llvm/DebugInfo/PDB/PDBSymbol.h | 6 +- llvm/include/llvm/ExecutionEngine/Orc/Core.h | 2 +- .../ExecutionEngine/Orc/ThreadSafeModule.h | 7 +- llvm/include/llvm/Support/Casting.h | 6 +- llvm/include/llvm/Support/Errno.h | 4 +- .../llvm-exegesis/lib/SnippetGenerator.cpp | 3 +- llvm/unittests/ADT/STLExtrasTest.cpp | 4 +- llvm/unittests/Support/FormatVariadicTest.cpp | 4 +- .../gtest/internal/custom/raw-ostream.h | 3 +- 11 files changed, 49 insertions(+), 93 deletions(-) diff --git a/llvm/include/llvm/ADT/STLExtras.h b/llvm/include/llvm/ADT/STLExtras.h index b61dab2459d1..172ef2bef2ae 100644 --- a/llvm/include/llvm/ADT/STLExtras.h +++ b/llvm/include/llvm/ADT/STLExtras.h @@ -146,16 +146,14 @@ namespace adl_detail { using std::begin; template -auto adl_begin(ContainerTy &&container) - -> decltype(begin(std::forward(container))) { +decltype(auto) adl_begin(ContainerTy &&container) { return begin(std::forward(container)); } using std::end; template -auto adl_end(ContainerTy &&container) - -> decltype(end(std::forward(container))) { +decltype(auto) adl_end(ContainerTy &&container) { return end(std::forward(container)); } @@ -170,14 +168,12 @@ void adl_swap(T &&lhs, T &&rhs) noexcept(noexcept(swap(std::declval(), } // end namespace adl_detail template -auto adl_begin(ContainerTy &&container) - -> decltype(adl_detail::adl_begin(std::forward(container))) { +decltype(auto) adl_begin(ContainerTy &&container) { return adl_detail::adl_begin(std::forward(container)); } template -auto adl_end(ContainerTy &&container) - -> decltype(adl_detail::adl_end(std::forward(container))) { +decltype(auto) adl_end(ContainerTy &&container) { return adl_detail::adl_end(std::forward(container)); } @@ -195,9 +191,7 @@ constexpr bool empty(const T &RangeOrContainer) { /// Return a range covering \p RangeOrContainer with the first N elements /// excluded. -template -auto drop_begin(T &&RangeOrContainer, size_t N) -> - iterator_range { +template auto drop_begin(T &&RangeOrContainer, size_t N) { return make_range(std::next(adl_begin(RangeOrContainer), N), adl_end(RangeOrContainer)); } @@ -233,9 +227,7 @@ inline mapped_iterator map_iterator(ItTy I, FuncTy F) { } template -auto map_range(ContainerTy &&C, FuncTy F) - -> decltype(make_range(map_iterator(C.begin(), F), - map_iterator(C.end(), F))) { +auto map_range(ContainerTy &&C, FuncTy F) { return make_range(map_iterator(C.begin(), F), map_iterator(C.end(), F)); } @@ -262,9 +254,9 @@ struct has_rbegin : has_rbegin_impl::type> { // Returns an iterator_range over the given container which iterates in reverse. // Note that the container must have rbegin()/rend() methods for this to work. template -auto reverse(ContainerTy &&C, - typename std::enable_if::value>::type * = - nullptr) -> decltype(make_range(C.rbegin(), C.rend())) { +auto reverse( + ContainerTy &&C, + typename std::enable_if::value>::type * = nullptr) { return make_range(C.rbegin(), C.rend()); } @@ -278,11 +270,9 @@ std::reverse_iterator make_reverse_iterator(IteratorTy It) { // Note that the container must have begin()/end() methods which return // bidirectional iterators for this to work. template -auto reverse( - ContainerTy &&C, - typename std::enable_if::value>::type * = nullptr) - -> decltype(make_range(llvm::make_reverse_iterator(std::end(C)), - llvm::make_reverse_iterator(std::begin(C)))) { +auto reverse(ContainerTy &&C, + typename std::enable_if::value>::type * = + nullptr) { return make_range(llvm::make_reverse_iterator(std::end(C)), llvm::make_reverse_iterator(std::begin(C))); } @@ -680,9 +670,8 @@ static Iter next_or_end(const Iter &I, const Iter &End) { } template -static auto deref_or_none(const Iter &I, const Iter &End) - -> llvm::Optional::type>::type> { +static auto deref_or_none(const Iter &I, const Iter &End) -> llvm::Optional< + std::remove_const_t>> { if (I == End) return None; return *I; @@ -983,8 +972,7 @@ struct on_first { FuncTy func; template - auto operator()(const T &lhs, const T &rhs) const - -> decltype(func(lhs.first, rhs.first)) { + decltype(auto) operator()(const T &lhs, const T &rhs) const { return func(lhs.first, rhs.first); } }; @@ -1164,8 +1152,7 @@ auto size(R &&Range, typename std::enable_if< std::is_same::iterator_category, std::random_access_iterator_tag>::value, - void>::type * = nullptr) - -> decltype(std::distance(Range.begin(), Range.end())) { + void>::type * = nullptr) { return std::distance(Range.begin(), Range.end()); } @@ -1199,27 +1186,26 @@ bool none_of(R &&Range, UnaryPredicate P) { /// Provide wrappers to std::find which take ranges instead of having to pass /// begin/end explicitly. -template -auto find(R &&Range, const T &Val) -> decltype(adl_begin(Range)) { +template auto find(R &&Range, const T &Val) { return std::find(adl_begin(Range), adl_end(Range), Val); } /// Provide wrappers to std::find_if which take ranges instead of having to pass /// begin/end explicitly. template -auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range)) { +auto find_if(R &&Range, UnaryPredicate P) { return std::find_if(adl_begin(Range), adl_end(Range), P); } template -auto find_if_not(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range)) { +auto find_if_not(R &&Range, UnaryPredicate P) { return std::find_if_not(adl_begin(Range), adl_end(Range), P); } /// Provide wrappers to std::remove_if which take ranges instead of having to /// pass begin/end explicitly. template -auto remove_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range)) { +auto remove_if(R &&Range, UnaryPredicate P) { return std::remove_if(adl_begin(Range), adl_end(Range), P); } @@ -1244,17 +1230,14 @@ bool is_contained(R &&Range, const E &Element) { /// Wrapper function around std::count to count the number of times an element /// \p Element occurs in the given range \p Range. -template -auto count(R &&Range, const E &Element) -> - typename std::iterator_traits::difference_type { +template auto count(R &&Range, const E &Element) { return std::count(adl_begin(Range), adl_end(Range), Element); } /// Wrapper function around std::count_if to count the number of times an /// element satisfying a given predicate occurs in a range. template -auto count_if(R &&Range, UnaryPredicate P) -> - typename std::iterator_traits::difference_type { +auto count_if(R &&Range, UnaryPredicate P) { return std::count_if(adl_begin(Range), adl_end(Range), P); } @@ -1268,36 +1251,32 @@ OutputIt transform(R &&Range, OutputIt d_first, UnaryPredicate P) { /// Provide wrappers to std::partition which take ranges instead of having to /// pass begin/end explicitly. template -auto partition(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range)) { +auto partition(R &&Range, UnaryPredicate P) { return std::partition(adl_begin(Range), adl_end(Range), P); } /// Provide wrappers to std::lower_bound which take ranges instead of having to /// pass begin/end explicitly. -template -auto lower_bound(R &&Range, T &&Value) -> decltype(adl_begin(Range)) { +template auto lower_bound(R &&Range, T &&Value) { return std::lower_bound(adl_begin(Range), adl_end(Range), std::forward(Value)); } template -auto lower_bound(R &&Range, T &&Value, Compare C) - -> decltype(adl_begin(Range)) { +auto lower_bound(R &&Range, T &&Value, Compare C) { return std::lower_bound(adl_begin(Range), adl_end(Range), std::forward(Value), C); } /// Provide wrappers to std::upper_bound which take ranges instead of having to /// pass begin/end explicitly. -template -auto upper_bound(R &&Range, T &&Value) -> decltype(adl_begin(Range)) { +template auto upper_bound(R &&Range, T &&Value) { return std::upper_bound(adl_begin(Range), adl_end(Range), std::forward(Value)); } template -auto upper_bound(R &&Range, T &&Value, Compare C) - -> decltype(adl_begin(Range)) { +auto upper_bound(R &&Range, T &&Value, Compare C) { return std::upper_bound(adl_begin(Range), adl_end(Range), std::forward(Value), C); } @@ -1316,7 +1295,7 @@ void stable_sort(R &&Range, Compare C) { /// Requires that C is always true below some limit, and always false above it. template ()))> -auto partition_point(R &&Range, Predicate P) -> decltype(adl_begin(Range)) { +auto partition_point(R &&Range, Predicate P) { return std::partition_point(adl_begin(Range), adl_end(Range), P); } @@ -1393,8 +1372,7 @@ template struct deref { // Could be further improved to cope with non-derivable functors and // non-binary functors (should be a variadic template member function // operator()). - template - auto operator()(A &lhs, B &rhs) const -> decltype(func(*lhs, *rhs)) { + template auto operator()(A &lhs, B &rhs) const { assert(lhs); assert(rhs); return func(*lhs, *rhs); @@ -1515,8 +1493,7 @@ template detail::enumerator enumerate(R &&TheRange) { namespace detail { template -auto apply_tuple_impl(F &&f, Tuple &&t, std::index_sequence) - -> decltype(std::forward(f)(std::get(std::forward(t))...)) { +decltype(auto) apply_tuple_impl(F &&f, Tuple &&t, std::index_sequence) { return std::forward(f)(std::get(std::forward(t))...); } @@ -1526,10 +1503,7 @@ auto apply_tuple_impl(F &&f, Tuple &&t, std::index_sequence) /// tuple variadically to f as if by calling f(a1, a2, ..., an) and /// return the result. template -auto apply_tuple(F &&f, Tuple &&t) -> decltype(detail::apply_tuple_impl( - std::forward(f), std::forward(t), - std::make_index_sequence< - std::tuple_size::type>::value>{})) { +decltype(auto) apply_tuple(F &&f, Tuple &&t) { using Indices = std::make_index_sequence< std::tuple_size::type>::value>; @@ -1573,15 +1547,12 @@ bool hasNItemsOrMore( /// Returns a raw pointer that represents the same address as the argument. /// -/// The late bound return should be removed once we move to C++14 to better -/// align with the C++20 declaration. Also, this implementation can be removed -/// once we move to C++20 where it's defined as std::to_addres() +/// This implementation can be removed once we move to C++20 where it's defined +/// as std::to_addres(). /// /// The std::pointer_traits<>::to_address(p) variations of these overloads has /// not been implemented. -template auto to_address(const Ptr &P) -> decltype(P.operator->()) { - return P.operator->(); -} +template auto to_address(const Ptr &P) { return P.operator->(); } template constexpr T *to_address(T *P) { return P; } } // end namespace llvm diff --git a/llvm/include/llvm/ADT/fallible_iterator.h b/llvm/include/llvm/ADT/fallible_iterator.h index 6501ad2233cd..62396ddfe8ad 100644 --- a/llvm/include/llvm/ADT/fallible_iterator.h +++ b/llvm/include/llvm/ADT/fallible_iterator.h @@ -96,12 +96,10 @@ public: } /// Forward dereference to the underlying iterator. - auto operator*() -> decltype(*std::declval()) { return *I; } + decltype(auto) operator*() { return *I; } /// Forward const dereference to the underlying iterator. - auto operator*() const -> decltype(*std::declval()) { - return *I; - } + decltype(auto) operator*() const { return *I; } /// Forward structure dereference to the underlying iterator (if the /// underlying iterator supports it). diff --git a/llvm/include/llvm/DebugInfo/PDB/PDBSymbol.h b/llvm/include/llvm/DebugInfo/PDB/PDBSymbol.h index 0d95a2467556..2982146f960c 100644 --- a/llvm/include/llvm/DebugInfo/PDB/PDBSymbol.h +++ b/llvm/include/llvm/DebugInfo/PDB/PDBSymbol.h @@ -17,13 +17,11 @@ #include "llvm/Support/Casting.h" #define FORWARD_SYMBOL_METHOD(MethodName) \ - auto MethodName() const->decltype(RawSymbol->MethodName()) { \ - return RawSymbol->MethodName(); \ - } + decltype(auto) MethodName() const { return RawSymbol->MethodName(); } #define FORWARD_CONCRETE_SYMBOL_ID_METHOD_WITH_NAME(ConcreteType, PrivateName, \ PublicName) \ - auto PublicName##Id() const->decltype(RawSymbol->PrivateName##Id()) { \ + decltype(auto) PublicName##Id() const { \ return RawSymbol->PrivateName##Id(); \ } \ std::unique_ptr PublicName() const { \ diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h index ecba454887b3..9113ccf459b0 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h @@ -1079,7 +1079,7 @@ public: std::shared_ptr getSymbolStringPool() const { return SSP; } /// Run the given lambda with the session mutex locked. - template auto runSessionLocked(Func &&F) -> decltype(F()) { + template decltype(auto) runSessionLocked(Func &&F) { std::lock_guard Lock(SessionMutex); return F(); } diff --git a/llvm/include/llvm/ExecutionEngine/Orc/ThreadSafeModule.h b/llvm/include/llvm/ExecutionEngine/Orc/ThreadSafeModule.h index 2347faed37a2..58c96737e580 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/ThreadSafeModule.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/ThreadSafeModule.h @@ -130,8 +130,7 @@ public: /// Locks the associated ThreadSafeContext and calls the given function /// on the contained Module. - template - auto withModuleDo(Func &&F) -> decltype(F(std::declval())) { + template decltype(auto) withModuleDo(Func &&F) { assert(M && "Can not call on null module"); auto Lock = TSCtx.getLock(); return F(*M); @@ -139,9 +138,7 @@ public: /// Locks the associated ThreadSafeContext and calls the given function /// on the contained Module. - template - auto withModuleDo(Func &&F) const - -> decltype(F(std::declval())) { + template decltype(auto) withModuleDo(Func &&F) const { auto Lock = TSCtx.getLock(); return F(*M); } diff --git a/llvm/include/llvm/Support/Casting.h b/llvm/include/llvm/Support/Casting.h index 46bdedb04cfe..ae7e9fd81219 100644 --- a/llvm/include/llvm/Support/Casting.h +++ b/llvm/include/llvm/Support/Casting.h @@ -382,8 +382,7 @@ LLVM_NODISCARD inline auto unique_dyn_cast(std::unique_ptr &Val) } template -LLVM_NODISCARD inline auto unique_dyn_cast(std::unique_ptr &&Val) - -> decltype(cast(Val)) { +LLVM_NODISCARD inline auto unique_dyn_cast(std::unique_ptr &&Val) { return unique_dyn_cast(Val); } @@ -398,8 +397,7 @@ LLVM_NODISCARD inline auto unique_dyn_cast_or_null(std::unique_ptr &Val) } template -LLVM_NODISCARD inline auto unique_dyn_cast_or_null(std::unique_ptr &&Val) - -> decltype(cast(Val)) { +LLVM_NODISCARD inline auto unique_dyn_cast_or_null(std::unique_ptr &&Val) { return unique_dyn_cast_or_null(Val); } diff --git a/llvm/include/llvm/Support/Errno.h b/llvm/include/llvm/Support/Errno.h index aedb5fb292b8..dc3b3322ed98 100644 --- a/llvm/include/llvm/Support/Errno.h +++ b/llvm/include/llvm/Support/Errno.h @@ -30,8 +30,8 @@ std::string StrError(); std::string StrError(int errnum); template -inline auto RetryAfterSignal(const FailT &Fail, const Fun &F, - const Args &... As) -> decltype(F(As...)) { +inline decltype(auto) RetryAfterSignal(const FailT &Fail, const Fun &F, + const Args &... As) { decltype(F(As...)) Res; do { errno = 0; diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp index 21932f416aa7..84ef4c63598a 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -177,8 +177,7 @@ size_t randomIndex(size_t Max) { return Distribution(randomGenerator()); } -template -static auto randomElement(const C &Container) -> decltype(Container[0]) { +template static decltype(auto) randomElement(const C &Container) { assert(!Container.empty() && "Can't pick a random element from an empty container)"); return Container[randomIndex(Container.size() - 1)]; diff --git a/llvm/unittests/ADT/STLExtrasTest.cpp b/llvm/unittests/ADT/STLExtrasTest.cpp index d0220e309fef..a2bcd9e5c72c 100644 --- a/llvm/unittests/ADT/STLExtrasTest.cpp +++ b/llvm/unittests/ADT/STLExtrasTest.cpp @@ -221,9 +221,7 @@ class apply_variadic { static StringRef apply_one(StringRef S) { return S.drop_back(); } public: - template - auto operator()(Ts &&... Items) - -> decltype(std::make_tuple(apply_one(Items)...)) { + template auto operator()(Ts &&... Items) { return std::make_tuple(apply_one(Items)...); } }; diff --git a/llvm/unittests/Support/FormatVariadicTest.cpp b/llvm/unittests/Support/FormatVariadicTest.cpp index a4e8826ecf4e..e3754fbd1bf0 100644 --- a/llvm/unittests/Support/FormatVariadicTest.cpp +++ b/llvm/unittests/Support/FormatVariadicTest.cpp @@ -487,9 +487,7 @@ struct format_tuple { const char *Fmt; explicit format_tuple(const char *Fmt) : Fmt(Fmt) {} - template - auto operator()(Ts &&... Values) const - -> decltype(formatv(Fmt, std::forward(Values)...)) { + template auto operator()(Ts &&... Values) const { return formatv(Fmt, std::forward(Values)...); } }; diff --git a/llvm/utils/unittest/googletest/include/gtest/internal/custom/raw-ostream.h b/llvm/utils/unittest/googletest/include/gtest/internal/custom/raw-ostream.h index 72f23184abd5..cff78f5c33f6 100644 --- a/llvm/utils/unittest/googletest/include/gtest/internal/custom/raw-ostream.h +++ b/llvm/utils/unittest/googletest/include/gtest/internal/custom/raw-ostream.h @@ -31,8 +31,7 @@ template struct StreamSwitch { // printable() returns a version of its argument that can be streamed into a // std::ostream. This may be the argument itself, or some other representation. -template -auto printable(const T &V) -> decltype(StreamSwitch::printable(V)) { +template decltype(auto) printable(const T &V) { // We delegate to the trait, to allow partial specialization. return StreamSwitch::printable(V); } -- GitLab From 0311e28e9cc01a244faa774b8cab337b45404fa9 Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Mon, 10 Feb 2020 21:08:23 +0100 Subject: [PATCH 017/142] [SystemZ] Bugfix in emitSelect() When more than one SelectPseudo instruction is handled a new MBB is returned. This must not be done if that would result in leaving an undhandled isel pseudo behind in the original MBB. Fixes https://bugs.llvm.org/show_bug.cgi?id=44849. Review: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D74352 --- .../Target/SystemZ/SystemZISelLowering.cpp | 5 ++- llvm/test/CodeGen/SystemZ/multiselect-02.mir | 43 +++++++++++++++++++ 2 files changed, 46 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/SystemZ/multiselect-02.mir diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 362bf19963d9..8cb01709e9e7 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -6886,8 +6886,6 @@ SystemZTargetLowering::emitSelect(MachineInstr &MI, for (MachineBasicBlock::iterator NextMIIt = std::next(MachineBasicBlock::iterator(MI)); NextMIIt != MBB->end(); ++NextMIIt) { - if (NextMIIt->definesRegister(SystemZ::CC)) - break; if (isSelectPseudo(*NextMIIt)) { assert(NextMIIt->getOperand(3).getImm() == CCValid && "Bad CCValid operands since CC was not redefined."); @@ -6898,6 +6896,9 @@ SystemZTargetLowering::emitSelect(MachineInstr &MI, } break; } + if (NextMIIt->definesRegister(SystemZ::CC) || + NextMIIt->usesCustomInsertionHook()) + break; bool User = false; for (auto SelMI : Selects) if (NextMIIt->readsVirtualRegister(SelMI->getOperand(0).getReg())) { diff --git a/llvm/test/CodeGen/SystemZ/multiselect-02.mir b/llvm/test/CodeGen/SystemZ/multiselect-02.mir new file mode 100644 index 000000000000..fc8aa0ad538f --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/multiselect-02.mir @@ -0,0 +1,43 @@ +# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z10 -run-pass=finalize-isel -o - %s \ +# RUN: | FileCheck %s +# +# Test that an instruction (ZEXT128) that uses custom insertion gets treated +# correctly also when it lies between two Select instructions that could +# potentially be handled together. +# +# CHECK-LABEL: bb.0.entry: +# CHECK-NOT: ZEXT128 + +--- | + declare void @bar(i32) + define i32 @fun() { entry: ret i32 0 } +--- +name: fun +body: | + bb.0.entry: + %1:addr64bit = IMPLICIT_DEF + %0:gr32bit = LLC %1, 0, $noreg :: (load 1 from `i8* undef`) + CHI killed %0, 0, implicit-def $cc + %2:gr32bit = LHI 2 + %3:gr32bit = LHI 8 + %4:gr32bit = Select32 killed %3, killed %2, 14, 8, implicit $cc + %5:gr32bit = LHI 128 + %7:gr64bit = IMPLICIT_DEF + %6:gr64bit = INSERT_SUBREG %7, killed %5, %subreg.subreg_l32 + %8:gr128bit = ZEXT128 killed %6 + %10:addr64bit = IMPLICIT_DEF + %9:gr128bit = DL %8, %10, 0, $noreg :: (load 4 from `i64* undef` + 4) + %11:gr32bit = COPY %9.subreg_l32 + %12:gr64bit = LGHI 2 + %13:gr64bit = LGHI 8 + %14:gr64bit = Select64 killed %13, killed %12, 14, 8, implicit $cc + CR %4, %11, implicit-def $cc + %15:gr32bit = Select32 %11, %4, 14, 4, implicit $cc + ADJCALLSTACKDOWN 0, 0 + $r2d = COPY %14 + CallBRASL @bar, $r2d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc + ADJCALLSTACKUP 0, 0 + $r2l = COPY %15 + Return implicit $r2l + +... -- GitLab From 8d5bf0422bc3c8cc7017602375122f7bfea70dab Mon Sep 17 00:00:00 2001 From: Eric Astor Date: Tue, 11 Feb 2020 09:18:08 -0500 Subject: [PATCH 018/142] [ms] [llvm-ml] Add support for attempted register parsing Summary: Add a new method (tryParseRegister) that attempts to parse a register specification. MASM allows the use of IFDEF , as well as IFDEF . To accommodate this, we make it possible to check whether a register specification can be parsed at the current location, without failing the entire parse if it can't. Reviewers: thakis Reviewed By: thakis Tags: #llvm Differential Revision: https://reviews.llvm.org/D73486 --- .../llvm/MC/MCParser/MCTargetAsmParser.h | 8 ++ .../AArch64/AsmParser/AArch64AsmParser.cpp | 10 +- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 111 ++++++++++++------ .../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 10 ++ .../lib/Target/AVR/AsmParser/AVRAsmParser.cpp | 26 +++- .../lib/Target/BPF/AsmParser/BPFAsmParser.cpp | 14 ++- .../Hexagon/AsmParser/HexagonAsmParser.cpp | 30 +++-- .../Target/Lanai/AsmParser/LanaiAsmParser.cpp | 34 +++++- .../MSP430/AsmParser/MSP430AsmParser.cpp | 23 +++- .../Target/Mips/AsmParser/MipsAsmParser.cpp | 13 +- .../Target/PowerPC/AsmParser/PPCAsmParser.cpp | 14 ++- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 16 ++- .../Target/Sparc/AsmParser/SparcAsmParser.cpp | 17 ++- .../SystemZ/AsmParser/SystemZAsmParser.cpp | 52 ++++++-- .../AsmParser/WebAssemblyAsmParser.cpp | 5 + .../lib/Target/X86/AsmParser/X86AsmParser.cpp | 71 +++++++++-- 16 files changed, 367 insertions(+), 87 deletions(-) diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h index 6e4821cbc7b9..9ce1890916e9 100644 --- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h +++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h @@ -376,6 +376,14 @@ public: virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0; + /// tryParseRegister - parse one register if possible + /// + /// Check whether a register specification can be parsed at the current + /// location, without failing the entire parse if it can't. Must not consume + /// tokens if the parse fails. + virtual OperandMatchResultTy + tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0; + /// ParseInstruction - Parse one assembly instruction. /// /// The parser is positioned following the instruction name. The target diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index fb09cc247a1a..55b09096bb95 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -260,6 +260,8 @@ public: bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseDirective(AsmToken DirectiveID) override; unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; @@ -2245,10 +2247,16 @@ static unsigned matchSVEPredicateVectorRegName(StringRef Name) { bool AArch64AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success; +} + +OperandMatchResultTy AArch64AsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { StartLoc = getLoc(); auto Res = tryParseScalarRegister(RegNo); EndLoc = SMLoc::getFromPointer(getLoc().getPointer() - 1); - return Res != MatchOperand_Success; + return Res; } // Matches a register name or register alias previously defined by '.req' diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 8c1f63e4ca86..3ef493bcb156 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1065,17 +1065,20 @@ private: bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1); - bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, - unsigned& RegNum, unsigned& RegWidth); - unsigned ParseRegularReg(RegisterKind &RegKind, - unsigned &RegNum, - unsigned &RegWidth); - unsigned ParseSpecialReg(RegisterKind &RegKind, - unsigned &RegNum, - unsigned &RegWidth); - unsigned ParseRegList(RegisterKind &RegKind, - unsigned &RegNum, - unsigned &RegWidth); + bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, + unsigned &RegNum, unsigned &RegWidth, + bool RestoreOnFailure = false); + bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, + unsigned &RegNum, unsigned &RegWidth, + SmallVectorImpl &Tokens); + unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum, + unsigned &RegWidth, + SmallVectorImpl &Tokens); + unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum, + unsigned &RegWidth, + SmallVectorImpl &Tokens); + unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum, + unsigned &RegWidth, SmallVectorImpl &Tokens); bool ParseRegRange(unsigned& Num, unsigned& Width); unsigned getRegularReg(RegisterKind RegKind, unsigned RegNum, @@ -1233,8 +1236,12 @@ public: bool isForcedSDWA() const { return ForcedSDWA; } ArrayRef getMatchedVariants() const; - std::unique_ptr parseRegister(); + std::unique_ptr parseRegister(bool RestoreOnFailure = false); + bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, + bool RestoreOnFailure); bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; unsigned checkTargetMatchPredicate(MCInst &Inst) override; unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; @@ -1987,7 +1994,7 @@ static unsigned getSpecialRegForName(StringRef RegName) { } bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, - SMLoc &EndLoc) { + SMLoc &EndLoc, bool RestoreOnFailure) { auto R = parseRegister(); if (!R) return true; assert(R->isReg()); @@ -1997,6 +2004,25 @@ bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, return false; } +bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) { + return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false); +} + +OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { + bool Result = + ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true); + bool PendingErrors = getParser().hasPendingError(); + getParser().clearPendingErrors(); + if (PendingErrors) + return MatchOperand_ParseFail; + if (Result) + return MatchOperand_NoMatch; + return MatchOperand_Success; +} + bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth, RegisterKind RegKind, unsigned Reg1) { switch (RegKind) { @@ -2173,31 +2199,31 @@ AMDGPUAsmParser::ParseRegRange(unsigned& Num, unsigned& Width) { return true; } -unsigned -AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind, - unsigned &RegNum, - unsigned &RegWidth) { +unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind, + unsigned &RegNum, unsigned &RegWidth, + SmallVectorImpl &Tokens) { assert(isToken(AsmToken::Identifier)); unsigned Reg = getSpecialRegForName(getTokenStr()); if (Reg) { RegNum = 0; RegWidth = 1; RegKind = IS_SPECIAL; + Tokens.push_back(getToken()); lex(); // skip register name } return Reg; } -unsigned -AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind, - unsigned &RegNum, - unsigned &RegWidth) { +unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind, + unsigned &RegNum, unsigned &RegWidth, + SmallVectorImpl &Tokens) { assert(isToken(AsmToken::Identifier)); StringRef RegName = getTokenStr(); const RegInfo *RI = getRegularRegInfo(RegName); if (!RI) return AMDGPU::NoRegister; + Tokens.push_back(getToken()); lex(); // skip register name RegKind = RI->Kind; @@ -2216,10 +2242,9 @@ AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind, return getRegularReg(RegKind, RegNum, RegWidth); } -unsigned -AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, - unsigned &RegNum, - unsigned &RegWidth) { +unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum, + unsigned &RegWidth, + SmallVectorImpl &Tokens) { unsigned Reg = AMDGPU::NoRegister; if (!trySkipToken(AsmToken::LBrac)) @@ -2236,7 +2261,8 @@ AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, RegisterKind NextRegKind; unsigned NextReg, NextRegNum, NextRegWidth; - if (!ParseAMDGPURegister(NextRegKind, NextReg, NextRegNum, NextRegWidth)) + if (!ParseAMDGPURegister(NextRegKind, NextReg, NextRegNum, NextRegWidth, + Tokens)) return AMDGPU::NoRegister; if (NextRegWidth != 1) return AMDGPU::NoRegister; @@ -2255,24 +2281,40 @@ AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, return Reg; } -bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, - unsigned &Reg, - unsigned &RegNum, - unsigned &RegWidth) { +bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, + unsigned &RegNum, unsigned &RegWidth, + SmallVectorImpl &Tokens) { Reg = AMDGPU::NoRegister; if (isToken(AsmToken::Identifier)) { - Reg = ParseSpecialReg(RegKind, RegNum, RegWidth); + Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens); if (Reg == AMDGPU::NoRegister) - Reg = ParseRegularReg(RegKind, RegNum, RegWidth); + Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens); } else { - Reg = ParseRegList(RegKind, RegNum, RegWidth); + Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens); } const MCRegisterInfo *TRI = getContext().getRegisterInfo(); return Reg != AMDGPU::NoRegister && subtargetHasRegister(*TRI, Reg); } +bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, + unsigned &RegNum, unsigned &RegWidth, + bool RestoreOnFailure) { + Reg = AMDGPU::NoRegister; + + SmallVector Tokens; + if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) { + if (RestoreOnFailure) { + while (!Tokens.empty()) { + getLexer().UnLex(Tokens.pop_back_val()); + } + } + return true; + } + return false; +} + Optional AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) { switch (RegKind) { @@ -2321,7 +2363,8 @@ bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind, return true; } -std::unique_ptr AMDGPUAsmParser::parseRegister() { +std::unique_ptr +AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) { const auto &Tok = Parser.getTok(); SMLoc StartLoc = Tok.getLoc(); SMLoc EndLoc = Tok.getEndLoc(); diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 8921eb7306bb..e4f375c6f043 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -628,6 +628,8 @@ public: // Implementation of the MCTargetAsmParser interface: bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; bool ParseDirective(AsmToken DirectiveID) override; @@ -3885,6 +3887,14 @@ bool ARMAsmParser::ParseRegister(unsigned &RegNo, return (RegNo == (unsigned)-1); } +OperandMatchResultTy ARMAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { + if (ParseRegister(RegNo, StartLoc, EndLoc)) + return MatchOperand_NoMatch; + return MatchOperand_Success; +} + /// Try to parse a register name. The token must be an Identifier when called, /// and if it is a register name the token is eaten and the register number is /// returned. Otherwise return -1. diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp index fc34583ae573..9d0dee8cc293 100644 --- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp +++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp @@ -53,6 +53,8 @@ class AVRAsmParser : public MCTargetAsmParser { bool MatchingInlineAsm) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -64,7 +66,7 @@ class AVRAsmParser : public MCTargetAsmParser { bool parseOperand(OperandVector &Operands); int parseRegisterName(unsigned (*matchFn)(StringRef)); int parseRegisterName(); - int parseRegister(); + int parseRegister(bool RestoreOnFailure = false); bool tryParseRegisterOperand(OperandVector &Operands); bool tryParseExpression(OperandVector &Operands); bool tryParseRelocExpression(OperandVector &Operands); @@ -359,19 +361,25 @@ int AVRAsmParser::parseRegisterName() { return RegNum; } -int AVRAsmParser::parseRegister() { +int AVRAsmParser::parseRegister(bool RestoreOnFailure) { int RegNum = AVR::NoRegister; if (Parser.getTok().is(AsmToken::Identifier)) { // Check for register pair syntax if (Parser.getLexer().peekTok().is(AsmToken::Colon)) { + AsmToken HighTok = Parser.getTok(); Parser.Lex(); + AsmToken ColonTok = Parser.getTok(); Parser.Lex(); // Eat high (odd) register and colon if (Parser.getTok().is(AsmToken::Identifier)) { // Convert lower (even) register to DREG RegNum = toDREG(parseRegisterName()); } + if (RegNum == AVR::NoRegister && RestoreOnFailure) { + getLexer().UnLex(std::move(ColonTok)); + getLexer().UnLex(std::move(HighTok)); + } } else { RegNum = parseRegisterName(); } @@ -580,12 +588,24 @@ AVRAsmParser::parseMemriOperand(OperandVector &Operands) { bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { StartLoc = Parser.getTok().getLoc(); - RegNo = parseRegister(); + RegNo = parseRegister(/*RestoreOnFailure=*/false); EndLoc = Parser.getTok().getLoc(); return (RegNo == AVR::NoRegister); } +OperandMatchResultTy AVRAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { + StartLoc = Parser.getTok().getLoc(); + RegNo = parseRegister(/*RestoreOnFailure=*/true); + EndLoc = Parser.getTok().getLoc(); + + if (RegNo == AVR::NoRegister) + return MatchOperand_NoMatch; + return MatchOperand_Success; +} + void AVRAsmParser::eatComma() { if (getLexer().is(AsmToken::Comma)) { Parser.Lex(); diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp index 1f5d5025bc7b..dbcb156a43fd 100644 --- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp +++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp @@ -39,6 +39,8 @@ class BPFAsmParser : public MCTargetAsmParser { bool MatchingInlineAsm) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -322,6 +324,14 @@ bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool BPFAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) + return Error(StartLoc, "invalid register name"); + return false; +} + +OperandMatchResultTy BPFAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { const AsmToken &Tok = getParser().getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); @@ -330,10 +340,10 @@ bool BPFAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, if (!MatchRegisterName(Name)) { getParser().Lex(); // Eat identifier token. - return false; + return MatchOperand_Success; } - return Error(StartLoc, "invalid register name"); + return MatchOperand_NoMatch; } OperandMatchResultTy diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 5976a811c978..ae19b138b0c7 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -116,6 +116,8 @@ class HexagonAsmParser : public MCTargetAsmParser { bool ParseDirectiveFalign(unsigned Size, SMLoc L); bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseDirectiveSubsection(SMLoc L); bool ParseDirectiveComm(bool IsLocal, SMLoc L); bool RegisterMatchesArch(unsigned MatchNum) const; @@ -964,6 +966,12 @@ bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious, bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success; +} + +OperandMatchResultTy HexagonAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { MCAsmLexer &Lexer = getLexer(); StartLoc = getLexer().getLoc(); SmallVector Lookahead; @@ -998,8 +1006,8 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, RegNo = DotReg; EndLoc = Lexer.getLoc(); if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) - return true; - return false; + return MatchOperand_NoMatch; + return MatchOperand_Success; } else { RegNo = DotReg; size_t First = RawString.find('.'); @@ -1007,28 +1015,26 @@ bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString)); EndLoc = Lexer.getLoc(); if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) - return true; - return false; + return MatchOperand_NoMatch; + return MatchOperand_Success; } } std::pair ColonSplit = StringRef(FullString).split(':'); unsigned ColonReg = matchRegister(ColonSplit.first.lower()); if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) { do { - Lexer.UnLex(Lookahead.back()); - Lookahead.pop_back(); - } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon)); + Lexer.UnLex(Lookahead.pop_back_val()); + } while (!Lookahead.empty() && !Lexer.is(AsmToken::Colon)); RegNo = ColonReg; EndLoc = Lexer.getLoc(); if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc)) - return true; - return false; + return MatchOperand_NoMatch; + return MatchOperand_Success; } while (!Lookahead.empty()) { - Lexer.UnLex(Lookahead.back()); - Lookahead.pop_back(); + Lexer.UnLex(Lookahead.pop_back_val()); } - return true; + return MatchOperand_NoMatch; } bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) { diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp index 8b8504978c75..9028f4ad93d9 100644 --- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp +++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp @@ -47,7 +47,7 @@ struct LanaiOperand; class LanaiAsmParser : public MCTargetAsmParser { // Parse operands - std::unique_ptr parseRegister(); + std::unique_ptr parseRegister(bool RestoreOnFailure = false); std::unique_ptr parseImmediate(); @@ -67,6 +67,8 @@ class LanaiAsmParser : public MCTargetAsmParser { SMLoc NameLoc, OperandVector &Operands) override; bool ParseRegister(unsigned &RegNum, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -687,21 +689,30 @@ bool LanaiAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, // backwards compatible with GCC and the different ways inline assembly is // handled. // TODO: see if there isn't a better way to do this. -std::unique_ptr LanaiAsmParser::parseRegister() { +std::unique_ptr +LanaiAsmParser::parseRegister(bool RestoreOnFailure) { SMLoc Start = Parser.getTok().getLoc(); SMLoc End = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + Optional PercentTok; unsigned RegNum; // Eat the '%'. - if (Lexer.getKind() == AsmToken::Percent) + if (Lexer.getKind() == AsmToken::Percent) { + PercentTok = Parser.getTok(); Parser.Lex(); + } if (Lexer.getKind() == AsmToken::Identifier) { RegNum = MatchRegisterName(Lexer.getTok().getIdentifier()); - if (RegNum == 0) + if (RegNum == 0) { + if (PercentTok.hasValue() && RestoreOnFailure) + Lexer.UnLex(PercentTok.getValue()); return nullptr; + } Parser.Lex(); // Eat identifier token return LanaiOperand::createReg(RegNum, Start, End); } + if (PercentTok.hasValue() && RestoreOnFailure) + Lexer.UnLex(PercentTok.getValue()); return nullptr; } @@ -710,12 +721,25 @@ bool LanaiAsmParser::ParseRegister(unsigned &RegNum, SMLoc &StartLoc, const AsmToken &Tok = getParser().getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); - std::unique_ptr Op = parseRegister(); + std::unique_ptr Op = parseRegister(/*RestoreOnFailure=*/false); if (Op != nullptr) RegNum = Op->getReg(); return (Op == nullptr); } +OperandMatchResultTy LanaiAsmParser::tryParseRegister(unsigned &RegNum, + SMLoc &StartLoc, + SMLoc &EndLoc) { + const AsmToken &Tok = getParser().getTok(); + StartLoc = Tok.getLoc(); + EndLoc = Tok.getEndLoc(); + std::unique_ptr Op = parseRegister(/*RestoreOnFailure=*/true); + if (Op == nullptr) + return MatchOperand_NoMatch; + RegNum = Op->getReg(); + return MatchOperand_Success; +} + std::unique_ptr LanaiAsmParser::parseIdentifier() { SMLoc Start = Parser.getTok().getLoc(); SMLoc End = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp index 0995e80a0a09..daa1fb4b52cf 100644 --- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp +++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp @@ -46,6 +46,8 @@ class MSP430AsmParser : public MCTargetAsmParser { bool MatchingInlineAsm) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -288,13 +290,28 @@ static unsigned MatchRegisterAltName(StringRef Name); bool MSP430AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + switch (tryParseRegister(RegNo, StartLoc, EndLoc)) { + case MatchOperand_ParseFail: + return Error(StartLoc, "invalid register name"); + case MatchOperand_Success: + return false; + case MatchOperand_NoMatch: + return true; + } + + llvm_unreachable("unknown match result type"); +} + +OperandMatchResultTy MSP430AsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { if (getLexer().getKind() == AsmToken::Identifier) { auto Name = getLexer().getTok().getIdentifier().lower(); RegNo = MatchRegisterName(Name); if (RegNo == MSP430::NoRegister) { RegNo = MatchRegisterAltName(Name); if (RegNo == MSP430::NoRegister) - return true; + return MatchOperand_NoMatch; } AsmToken const &T = getParser().getTok(); @@ -302,10 +319,10 @@ bool MSP430AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, EndLoc = T.getEndLoc(); getLexer().Lex(); // eat register token - return false; + return MatchOperand_Success; } - return Error(StartLoc, "invalid register name"); + return MatchOperand_ParseFail; } bool MSP430AsmParser::parseJccInstruction(ParseInstructionInfo &Info, diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index e467ed36938b..21b8d503741e 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -179,6 +179,8 @@ class MipsAsmParser : public MCTargetAsmParser { /// Parse a register as used in CFI directives bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool parseParenSuffix(StringRef Name, OperandVector &Operands); @@ -6202,6 +6204,12 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success; +} + +OperandMatchResultTy MipsAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { SmallVector, 1> Operands; OperandMatchResultTy ResTy = parseAnyRegister(Operands); if (ResTy == MatchOperand_Success) { @@ -6219,11 +6227,12 @@ bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, RegNo = isGP64bit() ? Operand.getGPR64Reg() : Operand.getGPR32Reg(); } - return (RegNo == (unsigned)-1); + return (RegNo == (unsigned)-1) ? MatchOperand_NoMatch + : MatchOperand_Success; } assert(Operands.size() == 0); - return (RegNo == (unsigned)-1); + return (RegNo == (unsigned)-1) ? MatchOperand_NoMatch : MatchOperand_Success; } bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp index ed98852088e7..7859b13ecfaa 100644 --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -109,6 +109,8 @@ class PPCAsmParser : public MCTargetAsmParser { bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; const MCExpr *ExtractModifierFromExpr(const MCExpr *E, PPCMCExpr::VariantKind &Variant); @@ -1221,14 +1223,22 @@ bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { bool PPCAsmParser:: ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) + return TokError("invalid register name"); + return false; +} + +OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { const AsmToken &Tok = getParser().getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); RegNo = 0; int64_t IntVal; if (MatchRegisterName(RegNo, IntVal)) - return TokError("invalid register name"); - return false; + return MatchOperand_NoMatch; + return MatchOperand_Success; } /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 0160c86950a8..3e72eb096850 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -74,6 +74,8 @@ class RISCVAsmParser : public MCTargetAsmParser { bool MatchingInlineAsm) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -1025,17 +1027,25 @@ static bool matchRegisterNameHelper(bool IsRV32E, Register &RegNo, bool RISCVAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) + return Error(StartLoc, "invalid register name"); + return false; +} + +OperandMatchResultTy RISCVAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { const AsmToken &Tok = getParser().getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); RegNo = 0; StringRef Name = getLexer().getTok().getIdentifier(); - if (matchRegisterNameHelper(isRV32E(), (Register&)RegNo, Name)) - return Error(StartLoc, "invalid register name"); + if (matchRegisterNameHelper(isRV32E(), (Register &)RegNo, Name)) + return MatchOperand_NoMatch; getParser().Lex(); // Eat identifier token. - return false; + return MatchOperand_Success; } OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands, diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 2d3137f38821..dc75f5ccf973 100644 --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -68,6 +68,8 @@ class SparcAsmParser : public MCTargetAsmParser { uint64_t &ErrorInfo, bool MatchingInlineAsm) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; bool ParseDirective(AsmToken DirectiveID) override; @@ -630,20 +632,29 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool SparcAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) + return Error(StartLoc, "invalid register name"); + return false; +} + +OperandMatchResultTy SparcAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { const AsmToken &Tok = Parser.getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); RegNo = 0; if (getLexer().getKind() != AsmToken::Percent) - return false; + return MatchOperand_Success; Parser.Lex(); unsigned regKind = SparcOperand::rk_None; if (matchRegisterName(Tok, RegNo, regKind)) { Parser.Lex(); - return false; + return MatchOperand_Success; } - return Error(StartLoc, "invalid register name"); + getLexer().UnLex(Tok); + return MatchOperand_NoMatch; } static void applyMnemonicAliases(StringRef &Mnemonic, diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp index 607266d552a6..00fdb9e846d6 100644 --- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -405,7 +405,7 @@ private: SMLoc StartLoc, EndLoc; }; - bool parseRegister(Register &Reg); + bool parseRegister(Register &Reg, bool RestoreOnFailure = false); bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, bool IsAddress = false); @@ -449,6 +449,10 @@ public: // Override MCTargetAsmParser. bool ParseDirective(AsmToken DirectiveID) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, + bool RestoreOnFailure); + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, @@ -691,27 +695,37 @@ void SystemZOperand::print(raw_ostream &OS) const { } // Parse one register of the form %. -bool SystemZAsmParser::parseRegister(Register &Reg) { +bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) { Reg.StartLoc = Parser.getTok().getLoc(); // Eat the % prefix. if (Parser.getTok().isNot(AsmToken::Percent)) return Error(Parser.getTok().getLoc(), "register expected"); + const AsmToken &PercentTok = Parser.getTok(); Parser.Lex(); // Expect a register name. - if (Parser.getTok().isNot(AsmToken::Identifier)) + if (Parser.getTok().isNot(AsmToken::Identifier)) { + if (RestoreOnFailure) + getLexer().UnLex(PercentTok); return Error(Reg.StartLoc, "invalid register"); + } // Check that there's a prefix. StringRef Name = Parser.getTok().getString(); - if (Name.size() < 2) + if (Name.size() < 2) { + if (RestoreOnFailure) + getLexer().UnLex(PercentTok); return Error(Reg.StartLoc, "invalid register"); + } char Prefix = Name[0]; // Treat the rest of the register name as a register number. - if (Name.substr(1).getAsInteger(10, Reg.Num)) + if (Name.substr(1).getAsInteger(10, Reg.Num)) { + if (RestoreOnFailure) + getLexer().UnLex(PercentTok); return Error(Reg.StartLoc, "invalid register"); + } // Look for valid combinations of prefix and number. if (Prefix == 'r' && Reg.Num < 16) @@ -724,8 +738,11 @@ bool SystemZAsmParser::parseRegister(Register &Reg) { Reg.Group = RegAR; else if (Prefix == 'c' && Reg.Num < 16) Reg.Group = RegCR; - else + else { + if (RestoreOnFailure) + getLexer().UnLex(PercentTok); return Error(Reg.StartLoc, "invalid register"); + } Reg.EndLoc = Parser.getTok().getLoc(); Parser.Lex(); @@ -1124,9 +1141,9 @@ bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) { } bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, - SMLoc &EndLoc) { + SMLoc &EndLoc, bool RestoreOnFailure) { Register Reg; - if (parseRegister(Reg)) + if (parseRegister(Reg, RestoreOnFailure)) return true; if (Reg.Group == RegGR) RegNo = SystemZMC::GR64Regs[Reg.Num]; @@ -1143,6 +1160,25 @@ bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, return false; } +bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) { + return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false); +} + +OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { + bool Result = + ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true); + bool PendingErrors = getParser().hasPendingError(); + getParser().clearPendingErrors(); + if (PendingErrors) + return MatchOperand_ParseFail; + if (Result) + return MatchOperand_NoMatch; + return MatchOperand_Success; +} + bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { diff --git a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp index a46bf0649ac7..edd20900d810 100644 --- a/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp +++ b/llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp @@ -214,6 +214,11 @@ public: SMLoc & /*EndLoc*/) override { llvm_unreachable("ParseRegister is not implemented."); } + OperandMatchResultTy tryParseRegister(unsigned & /*RegNo*/, + SMLoc & /*StartLoc*/, + SMLoc & /*EndLoc*/) override { + llvm_unreachable("tryParseRegister is not implemented."); + } bool error(const Twine &Msg, const AsmToken &Tok) { return Parser.Error(Tok.getLoc(), Msg + Tok.getString()); diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index d37d812df485..ea4d23d03f29 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -858,6 +858,9 @@ private: return nullptr; } + bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, + bool RestoreOnFailure); + std::unique_ptr DefaultMemSIOperand(SMLoc Loc); std::unique_ptr DefaultMemDIOperand(SMLoc Loc); bool IsSIReg(unsigned Reg); @@ -1023,6 +1026,8 @@ public: } bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override; @@ -1129,22 +1134,36 @@ static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, return checkScale(Scale, ErrMsg); } -bool X86AsmParser::ParseRegister(unsigned &RegNo, - SMLoc &StartLoc, SMLoc &EndLoc) { +bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc, bool RestoreOnFailure) { MCAsmParser &Parser = getParser(); + MCAsmLexer &Lexer = getLexer(); RegNo = 0; + + SmallVector Tokens; + auto OnFailure = [RestoreOnFailure, &Lexer, &Tokens]() { + if (RestoreOnFailure) { + while (!Tokens.empty()) { + Lexer.UnLex(Tokens.pop_back_val()); + } + } + }; + const AsmToken &PercentTok = Parser.getTok(); StartLoc = PercentTok.getLoc(); // If we encounter a %, ignore it. This code handles registers with and // without the prefix, unprefixed registers can occur in cfi directives. - if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent)) + if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent)) { + Tokens.push_back(PercentTok); Parser.Lex(); // Eat percent token. + } const AsmToken &Tok = Parser.getTok(); EndLoc = Tok.getEndLoc(); if (Tok.isNot(AsmToken::Identifier)) { + OnFailure(); if (isParsingIntelSyntax()) return true; return Error(StartLoc, "invalid register name", SMRange(StartLoc, EndLoc)); @@ -1173,7 +1192,10 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, X86II::isX86_64NonExtLowByteReg(RegNo) || X86II::isX86_64ExtendedReg(RegNo)) { StringRef RegName = Tok.getString(); - Parser.Lex(); // Eat register name. + OnFailure(); + if (!RestoreOnFailure) { + Parser.Lex(); // Eat register name. + } return Error(StartLoc, "register %" + RegName + " is only available in 64-bit mode", SMRange(StartLoc, EndLoc)); @@ -1182,17 +1204,21 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens. if (RegNo == X86::ST0) { + Tokens.push_back(Tok); Parser.Lex(); // Eat 'st' // Check to see if we have '(4)' after %st. - if (getLexer().isNot(AsmToken::LParen)) + if (Lexer.isNot(AsmToken::LParen)) return false; // Lex the paren. - getParser().Lex(); + Tokens.push_back(Parser.getTok()); + Parser.Lex(); const AsmToken &IntTok = Parser.getTok(); - if (IntTok.isNot(AsmToken::Integer)) + if (IntTok.isNot(AsmToken::Integer)) { + OnFailure(); return Error(IntTok.getLoc(), "expected stack index"); + } switch (IntTok.getIntVal()) { case 0: RegNo = X86::ST0; break; case 1: RegNo = X86::ST1; break; @@ -1202,11 +1228,18 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, case 5: RegNo = X86::ST5; break; case 6: RegNo = X86::ST6; break; case 7: RegNo = X86::ST7; break; - default: return Error(IntTok.getLoc(), "invalid stack index"); + default: + OnFailure(); + return Error(IntTok.getLoc(), "invalid stack index"); } - if (getParser().Lex().isNot(AsmToken::RParen)) + // Lex IntTok + Tokens.push_back(IntTok); + Parser.Lex(); + if (Lexer.isNot(AsmToken::RParen)) { + OnFailure(); return Error(Parser.getTok().getLoc(), "expected ')'"); + } EndLoc = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat ')' @@ -1250,6 +1283,7 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, } if (RegNo == 0) { + OnFailure(); if (isParsingIntelSyntax()) return true; return Error(StartLoc, "invalid register name", SMRange(StartLoc, EndLoc)); @@ -1259,6 +1293,25 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo, return false; } +bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) { + return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false); +} + +OperandMatchResultTy X86AsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { + bool Result = + ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true); + bool PendingErrors = getParser().hasPendingError(); + getParser().clearPendingErrors(); + if (PendingErrors) + return MatchOperand_ParseFail; + if (Result) + return MatchOperand_NoMatch; + return MatchOperand_Success; +} + std::unique_ptr X86AsmParser::DefaultMemSIOperand(SMLoc Loc) { bool Parse32 = is32BitMode() || Code16GCC; unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI); -- GitLab From 47f7df89461e3fd9aa1c78f12741603365f903fe Mon Sep 17 00:00:00 2001 From: James Henderson Date: Tue, 11 Feb 2020 16:10:56 +0000 Subject: [PATCH 019/142] [test][DebugInfo][NFC] Fix line endings --- .../X86/debug_line_invalid.test | 372 +++++++++--------- 1 file changed, 186 insertions(+), 186 deletions(-) diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_line_invalid.test b/llvm/test/tools/llvm-dwarfdump/X86/debug_line_invalid.test index 73efb39cbdb3..f8005d4003a6 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_line_invalid.test +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_line_invalid.test @@ -1,186 +1,186 @@ -## Test the different error cases in the debug line parsing and how they prevent -## or don't prevent further dumping of section contents. - -## Show that a bad length stops parsing of the section. -# RUN: llvm-mc -triple x86_64-pc-linux %S/Inputs/debug_line_reserved_length.s -filetype=obj -o %t-reserved.o -# RUN: llvm-dwarfdump -debug-line %t-reserved.o 2> %t-reserved.err \ -# RUN: | FileCheck %s --check-prefixes=FIRST,FATAL -# RUN: FileCheck %s --input-file=%t-reserved.err --check-prefix=RESERVED -# RUN: llvm-dwarfdump -debug-line %t-reserved.o -verbose 2> %t-reserved-verbose.err \ -# RUN: | FileCheck %s --check-prefixes=FIRST,FATAL -# RUN: FileCheck %s --input-file=%t-reserved-verbose.err --check-prefix=RESERVED - -## We only produce warnings for malformed tables after the specified unit if -## parsing can continue. -# RUN: llvm-dwarfdump -debug-line=0 %t-reserved.o 2> %t-reserved-off-first.err \ -# RUN: | FileCheck %s --check-prefixes=FIRST,NOLATER -# RUN: FileCheck %s --input-file=%t-reserved-off-first.err --check-prefix=RESERVED - -## Stop looking for the specified unit, if a fatally-bad prologue is detected. -# RUN: llvm-dwarfdump -debug-line=0x4b %t-reserved.o 2> %t-reserved-off-last.err \ -# RUN: | FileCheck %s --check-prefixes=NOFIRST,NOLATER -# RUN: FileCheck %s --input-file=%t-reserved-off-last.err --check-prefix=RESERVED - -## Show that non-fatal errors do not prevent parsing the rest of the section. -# RUN: llvm-mc -triple x86_64-pc-linux %S/Inputs/debug_line_malformed.s -filetype=obj -o %t-malformed.o -# RUN: llvm-dwarfdump -debug-line %t-malformed.o 2> %t-malformed.err \ -# RUN: | FileCheck %s --check-prefixes=FIRST,NONFATAL,LAST --implicit-check-not='debug_line[{{.*}}]' -# RUN: FileCheck %s --input-file=%t-malformed.err --check-prefixes=ALL,OTHER -# RUN: llvm-dwarfdump -debug-line %t-malformed.o -verbose 2> %t-malformed-verbose.err \ -# RUN: | FileCheck %s --check-prefixes=FIRST,NONFATAL,LAST --implicit-check-not='debug_line[{{.*}}]' -# RUN: FileCheck %s --input-file=%t-malformed-verbose.err --check-prefixes=ALL,OTHER - -## We should still produce warnings for malformed tables after the specified unit. -# RUN: llvm-dwarfdump -debug-line=0 %t-malformed.o 2> %t-malformed-off-first.err \ -# RUN: | FileCheck %s --check-prefixes=FIRST,NOLATER -# RUN: FileCheck %s --input-file=%t-malformed-off-first.err --check-prefix=ALL - -## Don't stop looking for the later unit if non-fatal issues are found. -# RUN: llvm-dwarfdump -debug-line=0x332 %t-malformed.o 2> %t-malformed-off-last.err \ -# RUN: | FileCheck %s --check-prefix=LAST --implicit-check-not='debug_line[{{.*}}]' -# RUN: FileCheck %s --input-file=%t-malformed-off-last.err --check-prefix=ALL - -# FIRST: debug_line[0x00000000] -# FIRST: 0x000000000badbeef {{.*}} end_sequence -# NOFIRST-NOT: debug_line[0x00000000] -# NOFIRST-NOT: 0x000000000badbeef {{.*}} end_sequence -# NOLATER-NOT: debug_line[{{.*}}] -# NOLATER-NOT: end_sequence - -## For fatal issues, the following table(s) should not be dumped. -# FATAL: debug_line[0x00000048] -# FATAL-NEXT: Line table prologue -# FATAL-NEXT: total_length: 0xfffffffe -# FATAL-NOT: debug_line - -## For non-fatal issues, the table data should be dumped. -## Case 1: Version 0 table. -# NONFATAL: debug_line[0x00000048] -# NONFATAL-NEXT: Line table prologue -# NONFATAL-NOT: Address - -## Case 2: Version 1 table. -# NONFATAL: debug_line[0x0000004e] -# NONFATAL-NEXT: Line table prologue -# NONFATAL-NOT: Address - -## Case 3: Malformed directory format with no path component. -# NONFATAL: debug_line[0x00000054] -# NONFATAL-NEXT: Line table prologue -# NONFATAL-NOT: include_directories -# NONFATAL-NOT: file_names -# NONFATAL: 0x8877665544332211 {{.*}} end_sequence - -## Case 4: Prologue with length shorter than parsed. -# NONFATAL: debug_line[0x00000081] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: file_names[ 2]: -# NONFATAL-NEXT: name: "file2" -# NONFATAL-NEXT: dir_index: 1 -# NONFATAL-NEXT: mod_time: 0x00000002 -# NONFATAL-NEXT: length: 0x00000006 -# NONFATAL: 0x1122334455667788 {{.*}} 0 end_sequence{{$}} - -## Case 5: Prologue with length longer than parsed. -# NONFATAL: debug_line[0x000000c8] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: file_names[ 2]: -# NONFATAL-NEXT: name: "file2" -# NONFATAL-NEXT: dir_index: 1 -# NONFATAL-NEXT: mod_time: 0x00000002 -# NONFATAL-NEXT: length: 0x00000003 -# NONFATAL-NOT: file_names -# NONFATAL: 0x1111222233334444 {{.*}} is_stmt end_sequence - -## Case 6: Extended opcode with incorrect length versus expected. -# NONFATAL: debug_line[0x00000111] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: 0x00000000abbadaba {{.*}} end_sequence -# NONFATAL: 0x00000000babb1e45 {{.*}} 10 is_stmt prologue_end end_sequence{{$}} - -## Case 7: No end of sequence. -# NONFATAL: debug_line[0x0000016c] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: 0x00000000deadfade {{.*}} is_stmt -# NONFATAL-NOT: end_sequence - -## Case 8: Very short prologue length for V5 (ends during parameters). -# NONFATAL: debug_line[0x000001b2] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: standard_opcode_lengths[DW_LNS_set_isa] = 1 -# NONFATAL-NEXT: include_directories[ 0] = "/tmp" -# NONFATAL-NEXT: file_names[ 0]: -# NONFATAL-NEXT: name: "xyz" -# NONFATAL: 0x0000000000000000 1 0 1 0 0 is_stmt end_sequence -# NONFATAL: 0x0000babb1ebabb1e {{.*}} end_sequence - -## Case 9: V5 prologue ends during file table. -# NONFATAL: debug_line[0x000001ee] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: include_directories[ 0] = "/tmp" -# NONFATAL-NEXT: file_names[ 0]: -# NONFATAL-NEXT: name: "xyz" -# NONFATAL-NEXT: dir_index: 1 -# NONFATAL: 0x0000000000000000 {{.*}} epilogue_begin -# NONFATAL: 0x00000ab4acadab4a {{.*}} end_sequence - -## Case 10: V5 prologue ends during directory table. -# NONFATAL: debug_line[0x0000022f] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: include_directories[ 0] = "/tmp" -# NONFATAL-NEXT: file_names[ 0]: -# NONFATAL-NEXT: name: "xyz" -# NONFATAL: 0x0000000000000002 2 0 1 0 0 is_stmt{{$}} -# NONFATAL: 0x4444333322221111 {{.*}} end_sequence - -## Case 11: V5 invalid MD5 hash form when there is still data to be read. -# NONFATAL: debug_line[0x0000026b] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: include_directories[ 0] = "/tmp" -# NONFATAL-NOT: file_names -# NONFATAL-NOT: is_stmt -# NONFATAL: 0x1234123412341234 {{.*}} end_sequence - -## Case 12: V5 invalid MD5 hash form when data beyond the prologue length has -## been read before the MD5 problem is identified. -# NONFATAL: debug_line[0x000002ae] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: include_directories[ 0] = "/tmp" -# NONFATAL-NOT: file_names -# NONFATAL: 0x0000000000000000 {{.*}} epilogue_begin -# NONFATAL: 0x4321432143214321 {{.*}} is_stmt end_sequence - -## Case 13: V5 invalid directory content description has unsupported form. -# NONFATAL: debug_line[0x000002ec] -# NONFATAL-NEXT: Line table prologue -# NONFATAL: include_directories[ 0] = "/foo" -# NONFATAL-NOT: include_directories -# NONFATAL-NOT: file_names -# NONFATAL: 0xaaaabbbbccccdddd {{.*}} is_stmt end_sequence - -# LAST: debug_line[0x00000332] -# LAST: 0x00000000cafebabe {{.*}} end_sequence - -# RESERVED: warning: parsing line table prologue at offset 0x00000048 unsupported reserved unit length found of value 0xfffffffe - -# ALL-NOT: warning: -# ALL: warning: parsing line table prologue at offset 0x00000048 found unsupported version 0x00 -# ALL-NEXT: warning: parsing line table prologue at offset 0x0000004e found unsupported version 0x01 -# ALL-NEXT: warning: parsing line table prologue at 0x00000054 found an invalid directory or file table description at 0x00000073 -# ALL-NEXT: warning: failed to parse entry content descriptions because no path was found -# ALL-NEXT: warning: parsing line table prologue at 0x00000081 should have ended at 0x000000b9 but it ended at 0x000000ba -# ALL-NEXT: warning: parsing line table prologue at 0x000000c8 should have ended at 0x00000103 but it ended at 0x00000102 -# OTHER-NEXT: warning: unexpected line op length at offset 0x00000158 expected 0x02 found 0x01 -# OTHER-NEXT: warning: unexpected line op length at offset 0x0000015c expected 0x01 found 0x02 -# OTHER-NEXT: warning: last sequence in debug line table at offset 0x0000016c is not terminated -# ALL-NEXT: warning: parsing line table prologue at 0x000001b2 should have ended at 0x000001ce but it ended at 0x000001e1 -# ALL-NEXT: warning: parsing line table prologue at 0x000001ee should have ended at 0x00000219 but it ended at 0x00000220 -# ALL-NEXT: warning: parsing line table prologue at 0x0000022f should have ended at 0x00000251 but it ended at 0x0000025e -# ALL-NEXT: warning: parsing line table prologue at 0x0000026b found an invalid directory or file table description at 0x0000029f -# ALL-NEXT: warning: failed to parse file entry because the MD5 hash is invalid -# ALL-NEXT: warning: parsing line table prologue at 0x000002ae found an invalid directory or file table description at 0x000002e0 -# ALL-NEXT: warning: failed to parse file entry because the MD5 hash is invalid -# ALL-NEXT: warning: parsing line table prologue at 0x000002ae should have ended at 0x000002d9 but it ended at 0x000002e0 -# ALL-NEXT: warning: parsing line table prologue at 0x000002ec found an invalid directory or file table description at 0x00000315 -# ALL-NEXT: warning: failed to parse directory entry because skipping the form value failed. -# ALL-NOT: warning: +## Test the different error cases in the debug line parsing and how they prevent +## or don't prevent further dumping of section contents. + +## Show that a bad length stops parsing of the section. +# RUN: llvm-mc -triple x86_64-pc-linux %S/Inputs/debug_line_reserved_length.s -filetype=obj -o %t-reserved.o +# RUN: llvm-dwarfdump -debug-line %t-reserved.o 2> %t-reserved.err \ +# RUN: | FileCheck %s --check-prefixes=FIRST,FATAL +# RUN: FileCheck %s --input-file=%t-reserved.err --check-prefix=RESERVED +# RUN: llvm-dwarfdump -debug-line %t-reserved.o -verbose 2> %t-reserved-verbose.err \ +# RUN: | FileCheck %s --check-prefixes=FIRST,FATAL +# RUN: FileCheck %s --input-file=%t-reserved-verbose.err --check-prefix=RESERVED + +## We only produce warnings for malformed tables after the specified unit if +## parsing can continue. +# RUN: llvm-dwarfdump -debug-line=0 %t-reserved.o 2> %t-reserved-off-first.err \ +# RUN: | FileCheck %s --check-prefixes=FIRST,NOLATER +# RUN: FileCheck %s --input-file=%t-reserved-off-first.err --check-prefix=RESERVED + +## Stop looking for the specified unit, if a fatally-bad prologue is detected. +# RUN: llvm-dwarfdump -debug-line=0x4b %t-reserved.o 2> %t-reserved-off-last.err \ +# RUN: | FileCheck %s --check-prefixes=NOFIRST,NOLATER +# RUN: FileCheck %s --input-file=%t-reserved-off-last.err --check-prefix=RESERVED + +## Show that non-fatal errors do not prevent parsing the rest of the section. +# RUN: llvm-mc -triple x86_64-pc-linux %S/Inputs/debug_line_malformed.s -filetype=obj -o %t-malformed.o +# RUN: llvm-dwarfdump -debug-line %t-malformed.o 2> %t-malformed.err \ +# RUN: | FileCheck %s --check-prefixes=FIRST,NONFATAL,LAST --implicit-check-not='debug_line[{{.*}}]' +# RUN: FileCheck %s --input-file=%t-malformed.err --check-prefixes=ALL,OTHER +# RUN: llvm-dwarfdump -debug-line %t-malformed.o -verbose 2> %t-malformed-verbose.err \ +# RUN: | FileCheck %s --check-prefixes=FIRST,NONFATAL,LAST --implicit-check-not='debug_line[{{.*}}]' +# RUN: FileCheck %s --input-file=%t-malformed-verbose.err --check-prefixes=ALL,OTHER + +## We should still produce warnings for malformed tables after the specified unit. +# RUN: llvm-dwarfdump -debug-line=0 %t-malformed.o 2> %t-malformed-off-first.err \ +# RUN: | FileCheck %s --check-prefixes=FIRST,NOLATER +# RUN: FileCheck %s --input-file=%t-malformed-off-first.err --check-prefix=ALL + +## Don't stop looking for the later unit if non-fatal issues are found. +# RUN: llvm-dwarfdump -debug-line=0x332 %t-malformed.o 2> %t-malformed-off-last.err \ +# RUN: | FileCheck %s --check-prefix=LAST --implicit-check-not='debug_line[{{.*}}]' +# RUN: FileCheck %s --input-file=%t-malformed-off-last.err --check-prefix=ALL + +# FIRST: debug_line[0x00000000] +# FIRST: 0x000000000badbeef {{.*}} end_sequence +# NOFIRST-NOT: debug_line[0x00000000] +# NOFIRST-NOT: 0x000000000badbeef {{.*}} end_sequence +# NOLATER-NOT: debug_line[{{.*}}] +# NOLATER-NOT: end_sequence + +## For fatal issues, the following table(s) should not be dumped. +# FATAL: debug_line[0x00000048] +# FATAL-NEXT: Line table prologue +# FATAL-NEXT: total_length: 0xfffffffe +# FATAL-NOT: debug_line + +## For non-fatal issues, the table data should be dumped. +## Case 1: Version 0 table. +# NONFATAL: debug_line[0x00000048] +# NONFATAL-NEXT: Line table prologue +# NONFATAL-NOT: Address + +## Case 2: Version 1 table. +# NONFATAL: debug_line[0x0000004e] +# NONFATAL-NEXT: Line table prologue +# NONFATAL-NOT: Address + +## Case 3: Malformed directory format with no path component. +# NONFATAL: debug_line[0x00000054] +# NONFATAL-NEXT: Line table prologue +# NONFATAL-NOT: include_directories +# NONFATAL-NOT: file_names +# NONFATAL: 0x8877665544332211 {{.*}} end_sequence + +## Case 4: Prologue with length shorter than parsed. +# NONFATAL: debug_line[0x00000081] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: file_names[ 2]: +# NONFATAL-NEXT: name: "file2" +# NONFATAL-NEXT: dir_index: 1 +# NONFATAL-NEXT: mod_time: 0x00000002 +# NONFATAL-NEXT: length: 0x00000006 +# NONFATAL: 0x1122334455667788 {{.*}} 0 end_sequence{{$}} + +## Case 5: Prologue with length longer than parsed. +# NONFATAL: debug_line[0x000000c8] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: file_names[ 2]: +# NONFATAL-NEXT: name: "file2" +# NONFATAL-NEXT: dir_index: 1 +# NONFATAL-NEXT: mod_time: 0x00000002 +# NONFATAL-NEXT: length: 0x00000003 +# NONFATAL-NOT: file_names +# NONFATAL: 0x1111222233334444 {{.*}} is_stmt end_sequence + +## Case 6: Extended opcode with incorrect length versus expected. +# NONFATAL: debug_line[0x00000111] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: 0x00000000abbadaba {{.*}} end_sequence +# NONFATAL: 0x00000000babb1e45 {{.*}} 10 is_stmt prologue_end end_sequence{{$}} + +## Case 7: No end of sequence. +# NONFATAL: debug_line[0x0000016c] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: 0x00000000deadfade {{.*}} is_stmt +# NONFATAL-NOT: end_sequence + +## Case 8: Very short prologue length for V5 (ends during parameters). +# NONFATAL: debug_line[0x000001b2] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: standard_opcode_lengths[DW_LNS_set_isa] = 1 +# NONFATAL-NEXT: include_directories[ 0] = "/tmp" +# NONFATAL-NEXT: file_names[ 0]: +# NONFATAL-NEXT: name: "xyz" +# NONFATAL: 0x0000000000000000 1 0 1 0 0 is_stmt end_sequence +# NONFATAL: 0x0000babb1ebabb1e {{.*}} end_sequence + +## Case 9: V5 prologue ends during file table. +# NONFATAL: debug_line[0x000001ee] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: include_directories[ 0] = "/tmp" +# NONFATAL-NEXT: file_names[ 0]: +# NONFATAL-NEXT: name: "xyz" +# NONFATAL-NEXT: dir_index: 1 +# NONFATAL: 0x0000000000000000 {{.*}} epilogue_begin +# NONFATAL: 0x00000ab4acadab4a {{.*}} end_sequence + +## Case 10: V5 prologue ends during directory table. +# NONFATAL: debug_line[0x0000022f] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: include_directories[ 0] = "/tmp" +# NONFATAL-NEXT: file_names[ 0]: +# NONFATAL-NEXT: name: "xyz" +# NONFATAL: 0x0000000000000002 2 0 1 0 0 is_stmt{{$}} +# NONFATAL: 0x4444333322221111 {{.*}} end_sequence + +## Case 11: V5 invalid MD5 hash form when there is still data to be read. +# NONFATAL: debug_line[0x0000026b] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: include_directories[ 0] = "/tmp" +# NONFATAL-NOT: file_names +# NONFATAL-NOT: is_stmt +# NONFATAL: 0x1234123412341234 {{.*}} end_sequence + +## Case 12: V5 invalid MD5 hash form when data beyond the prologue length has +## been read before the MD5 problem is identified. +# NONFATAL: debug_line[0x000002ae] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: include_directories[ 0] = "/tmp" +# NONFATAL-NOT: file_names +# NONFATAL: 0x0000000000000000 {{.*}} epilogue_begin +# NONFATAL: 0x4321432143214321 {{.*}} is_stmt end_sequence + +## Case 13: V5 invalid directory content description has unsupported form. +# NONFATAL: debug_line[0x000002ec] +# NONFATAL-NEXT: Line table prologue +# NONFATAL: include_directories[ 0] = "/foo" +# NONFATAL-NOT: include_directories +# NONFATAL-NOT: file_names +# NONFATAL: 0xaaaabbbbccccdddd {{.*}} is_stmt end_sequence + +# LAST: debug_line[0x00000332] +# LAST: 0x00000000cafebabe {{.*}} end_sequence + +# RESERVED: warning: parsing line table prologue at offset 0x00000048 unsupported reserved unit length found of value 0xfffffffe + +# ALL-NOT: warning: +# ALL: warning: parsing line table prologue at offset 0x00000048 found unsupported version 0x00 +# ALL-NEXT: warning: parsing line table prologue at offset 0x0000004e found unsupported version 0x01 +# ALL-NEXT: warning: parsing line table prologue at 0x00000054 found an invalid directory or file table description at 0x00000073 +# ALL-NEXT: warning: failed to parse entry content descriptions because no path was found +# ALL-NEXT: warning: parsing line table prologue at 0x00000081 should have ended at 0x000000b9 but it ended at 0x000000ba +# ALL-NEXT: warning: parsing line table prologue at 0x000000c8 should have ended at 0x00000103 but it ended at 0x00000102 +# OTHER-NEXT: warning: unexpected line op length at offset 0x00000158 expected 0x02 found 0x01 +# OTHER-NEXT: warning: unexpected line op length at offset 0x0000015c expected 0x01 found 0x02 +# OTHER-NEXT: warning: last sequence in debug line table at offset 0x0000016c is not terminated +# ALL-NEXT: warning: parsing line table prologue at 0x000001b2 should have ended at 0x000001ce but it ended at 0x000001e1 +# ALL-NEXT: warning: parsing line table prologue at 0x000001ee should have ended at 0x00000219 but it ended at 0x00000220 +# ALL-NEXT: warning: parsing line table prologue at 0x0000022f should have ended at 0x00000251 but it ended at 0x0000025e +# ALL-NEXT: warning: parsing line table prologue at 0x0000026b found an invalid directory or file table description at 0x0000029f +# ALL-NEXT: warning: failed to parse file entry because the MD5 hash is invalid +# ALL-NEXT: warning: parsing line table prologue at 0x000002ae found an invalid directory or file table description at 0x000002e0 +# ALL-NEXT: warning: failed to parse file entry because the MD5 hash is invalid +# ALL-NEXT: warning: parsing line table prologue at 0x000002ae should have ended at 0x000002d9 but it ended at 0x000002e0 +# ALL-NEXT: warning: parsing line table prologue at 0x000002ec found an invalid directory or file table description at 0x00000315 +# ALL-NEXT: warning: failed to parse directory entry because skipping the form value failed. +# ALL-NOT: warning: -- GitLab From 37f46650c3866c06c6108740fd15a34ebcb6a404 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Tue, 11 Feb 2020 17:11:00 +0100 Subject: [PATCH 020/142] [libc++] Make sure that vector copy-construction is disabled for non-copyable types The Standard requires the value_type of the vector to be Cpp17CopyInsertable in order for copy-construction to be enabled: http://eel.is/c++draft/container.requirements#tab:container.req rdar://problem/56674564 Differential Revision: https://reviews.llvm.org/D74251 --- libcxx/include/memory | 2 +- .../vector.cons/copy.move_only.fail.cpp | 28 +++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 libcxx/test/std/containers/sequences/vector/vector.cons/copy.move_only.fail.cpp diff --git a/libcxx/include/memory b/libcxx/include/memory index 34c3e0c0d8d1..821f371eb0b0 100644 --- a/libcxx/include/memory +++ b/libcxx/include/memory @@ -1695,7 +1695,7 @@ struct _LIBCPP_TEMPLATE_VIS allocator_traits static typename enable_if < - is_trivially_move_constructible<_DestTp>::value && + is_trivially_copy_constructible<_DestTp>::value && is_same<_RawSourceTp, _RawDestTp>::value && (__is_default_allocator::value || !__has_construct::value), diff --git a/libcxx/test/std/containers/sequences/vector/vector.cons/copy.move_only.fail.cpp b/libcxx/test/std/containers/sequences/vector/vector.cons/copy.move_only.fail.cpp new file mode 100644 index 000000000000..b38f24c3be25 --- /dev/null +++ b/libcxx/test/std/containers/sequences/vector/vector.cons/copy.move_only.fail.cpp @@ -0,0 +1,28 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Make sure that a std::vector containing move-only types can't be copied. + +// UNSUPPORTED: c++98, c++03 +// REQUIRES: verify-support + +#include + +struct move_only +{ + move_only() = default; + move_only(move_only&&) = default; + move_only& operator=(move_only&&) = default; +}; + +int main(int, char**) +{ + std::vector v; + std::vector copy = v; // expected-error@memory:* {{call to implicitly-deleted copy constructor of 'move_only'}} + return 0; +} -- GitLab From 5eb19bf4a2b0c29a8d4d48dfb0276f096eff9bec Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Thu, 6 Feb 2020 21:16:10 +0100 Subject: [PATCH 021/142] [X86CmovConversion] Make heuristic for optimized cmov depth more conservative (PR44539) Fix/workaround for https://bugs.llvm.org/show_bug.cgi?id=44539. As discussed there, this pass makes some overly optimistic assumptions, as it does not have access to actual branch weights. This patch makes the computation of the depth of the optimized cmov more conservative, by assuming a distribution of 75/25 rather than 50/50 and placing the weights to get the more conservative result (larger depth). The fully conservative choice would be std::max(TrueOpDepth, FalseOpDepth), but that would break at least one existing test (which may or may not be an issue in practice). Differential Revision: https://reviews.llvm.org/D74155 --- llvm/lib/Target/X86/X86CmovConversion.cpp | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/X86/X86CmovConversion.cpp b/llvm/lib/Target/X86/X86CmovConversion.cpp index fe43bf4cbbce..fe5cb3ae2bf6 100644 --- a/llvm/lib/Target/X86/X86CmovConversion.cpp +++ b/llvm/lib/Target/X86/X86CmovConversion.cpp @@ -364,12 +364,13 @@ bool X86CmovConverterPass::collectCmovCandidates( /// \param TrueOpDepth depth cost of CMOV true value operand. /// \param FalseOpDepth depth cost of CMOV false value operand. static unsigned getDepthOfOptCmov(unsigned TrueOpDepth, unsigned FalseOpDepth) { - //===--------------------------------------------------------------------===// - // With no info about branch weight, we assume 50% for each value operand. - // Thus, depth of optimized CMOV instruction is the rounded up average of - // its True-Operand-Value-Depth and False-Operand-Value-Depth. - //===--------------------------------------------------------------------===// - return (TrueOpDepth + FalseOpDepth + 1) / 2; + // The depth of the result after branch conversion is + // TrueOpDepth * TrueOpProbability + FalseOpDepth * FalseOpProbability. + // As we have no info about branch weight, we assume 75% for one and 25% for + // the other, and pick the result with the largest resulting depth. + return std::max( + divideCeil(TrueOpDepth * 3 + FalseOpDepth, 4), + divideCeil(FalseOpDepth * 3 + TrueOpDepth, 4)); } bool X86CmovConverterPass::checkForProfitableCmovCandidates( -- GitLab From 509bac030a43b5e54d217a44f134805038f22a48 Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Tue, 11 Feb 2020 11:28:10 -0500 Subject: [PATCH 022/142] [SystemZ] Fix new test case for expensive checks. It needs 'tracksRegLiveness: true' to pass the machine verifier. --- llvm/test/CodeGen/SystemZ/multiselect-02.mir | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/test/CodeGen/SystemZ/multiselect-02.mir b/llvm/test/CodeGen/SystemZ/multiselect-02.mir index fc8aa0ad538f..abb6a01c9eb5 100644 --- a/llvm/test/CodeGen/SystemZ/multiselect-02.mir +++ b/llvm/test/CodeGen/SystemZ/multiselect-02.mir @@ -13,6 +13,7 @@ define i32 @fun() { entry: ret i32 0 } --- name: fun +tracksRegLiveness: true body: | bb.0.entry: %1:addr64bit = IMPLICIT_DEF -- GitLab From 515e19ae7b5f8be51686def4b7a64e917125d8e0 Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Tue, 11 Feb 2020 08:29:16 -0800 Subject: [PATCH 023/142] Fix errors/warnings in scudo build. --- compiler-rt/lib/scudo/standalone/size_class_map.h | 6 +++--- compiler-rt/lib/scudo/standalone/tsd_shared.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/size_class_map.h b/compiler-rt/lib/scudo/standalone/size_class_map.h index 46f53ae51fba..151f4f95f541 100644 --- a/compiler-rt/lib/scudo/standalone/size_class_map.h +++ b/compiler-rt/lib/scudo/standalone/size_class_map.h @@ -24,7 +24,7 @@ inline uptr scaledLog2(uptr Size, uptr ZeroLog, uptr LogBits) { template struct SizeClassMapBase { static u32 getMaxCachedHint(uptr Size) { - DCHECK_LE(Size, MaxSize); + DCHECK_LE(Size, (1UL << Config::MaxSizeLog) + Chunk::getHeaderSize()); DCHECK_NE(Size, 0); u32 N; // Force a 32-bit division if the template parameters allow for it. @@ -119,9 +119,9 @@ class TableSizeClassMap : public SizeClassMapBase { constexpr static u8 computeClassId(uptr Size) { for (uptr i = 0; i != ClassesSize; ++i) { if (Size <= Config::Classes[i]) - return i + 1; + return static_cast(i + 1); } - return -1; + return static_cast(-1); } constexpr static uptr getTableSize() { diff --git a/compiler-rt/lib/scudo/standalone/tsd_shared.h b/compiler-rt/lib/scudo/standalone/tsd_shared.h index 1626732c70f4..cf5453d20208 100644 --- a/compiler-rt/lib/scudo/standalone/tsd_shared.h +++ b/compiler-rt/lib/scudo/standalone/tsd_shared.h @@ -79,7 +79,7 @@ template struct TSDRegistrySharedT { } void enable() { - for (s32 I = NumberOfTSDs - 1; I >= 0; I--) + for (s32 I = static_cast(NumberOfTSDs - 1); I >= 0; I--) TSDs[I].unlock(); Mutex.unlock(); } -- GitLab From 5a8819b216e322c4a1e9cdc47094d1b773309b9d Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 3 Feb 2020 21:17:36 +0100 Subject: [PATCH 024/142] [InstCombine] Use replaceOperand() in more places This is a followup to D73803, which uses the replaceOperand() helper in more places. This should be NFC apart from changes to worklist order. Differential Revision: https://reviews.llvm.org/D73919 --- .../InstCombine/InstCombineAddSub.cpp | 5 ++- .../InstCombine/InstCombineAtomicRMW.cpp | 6 +-- .../InstCombine/InstCombineCompares.cpp | 19 +++----- .../InstCombine/InstCombineSelect.cpp | 44 +++++++++---------- .../InstCombine/InstCombineShifts.cpp | 3 +- .../InstCombine/InstCombineVectorOps.cpp | 17 +++---- 6 files changed, 40 insertions(+), 54 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index 574662800941..d1b820f93660 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1380,8 +1380,9 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) { // (add (and A, B) (or A, B)) --> (add A, B) if (match(&I, m_c_BinOp(m_Or(m_Value(A), m_Value(B)), m_c_And(m_Deferred(A), m_Deferred(B))))) { - I.setOperand(0, A); - I.setOperand(1, B); + // Replacing operands in-place to preserve nuw/nsw flags. + replaceOperand(I, 0, A); + replaceOperand(I, 1, B); return &I; } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp index 825f4b468b0a..9d3ecba559c3 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp @@ -138,13 +138,11 @@ Instruction *InstCombiner::visitAtomicRMWInst(AtomicRMWInst &RMWI) { if (RMWI.getType()->isIntegerTy() && RMWI.getOperation() != AtomicRMWInst::Or) { RMWI.setOperation(AtomicRMWInst::Or); - RMWI.setOperand(1, ConstantInt::get(RMWI.getType(), 0)); - return &RMWI; + return replaceOperand(RMWI, 1, ConstantInt::get(RMWI.getType(), 0)); } else if (RMWI.getType()->isFloatingPointTy() && RMWI.getOperation() != AtomicRMWInst::FAdd) { RMWI.setOperation(AtomicRMWInst::FAdd); - RMWI.setOperand(1, ConstantFP::getNegativeZero(RMWI.getType())); - return &RMWI; + return replaceOperand(RMWI, 1, ConstantFP::getNegativeZero(RMWI.getType())); } // Check if the required ordering is compatible with an atomic load. diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 0f8767873cf1..37e04e68ec5f 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -6030,14 +6030,11 @@ Instruction *InstCombiner::visitFCmpInst(FCmpInst &I) { // If we're just checking for a NaN (ORD/UNO) and have a non-NaN operand, // then canonicalize the operand to 0.0. if (Pred == CmpInst::FCMP_ORD || Pred == CmpInst::FCMP_UNO) { - if (!match(Op0, m_PosZeroFP()) && isKnownNeverNaN(Op0, &TLI)) { - I.setOperand(0, ConstantFP::getNullValue(OpType)); - return &I; - } - if (!match(Op1, m_PosZeroFP()) && isKnownNeverNaN(Op1, &TLI)) { - I.setOperand(1, ConstantFP::getNullValue(OpType)); - return &I; - } + if (!match(Op0, m_PosZeroFP()) && isKnownNeverNaN(Op0, &TLI)) + return replaceOperand(I, 0, ConstantFP::getNullValue(OpType)); + + if (!match(Op1, m_PosZeroFP()) && isKnownNeverNaN(Op1, &TLI)) + return replaceOperand(I, 1, ConstantFP::getNullValue(OpType)); } // fcmp pred (fneg X), (fneg Y) -> fcmp swap(pred) X, Y @@ -6062,10 +6059,8 @@ Instruction *InstCombiner::visitFCmpInst(FCmpInst &I) { // The sign of 0.0 is ignored by fcmp, so canonicalize to +0.0: // fcmp Pred X, -0.0 --> fcmp Pred X, 0.0 - if (match(Op1, m_AnyZeroFP()) && !match(Op1, m_PosZeroFP())) { - I.setOperand(1, ConstantFP::getNullValue(OpType)); - return &I; - } + if (match(Op1, m_AnyZeroFP()) && !match(Op1, m_PosZeroFP())) + return replaceOperand(I, 1, ConstantFP::getNullValue(OpType)); // Handle fcmp with instruction LHS and constant RHS. Instruction *LHSI; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index c086b152c09b..c9baa8b87faf 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -56,7 +56,8 @@ static Value *createMinMax(InstCombiner::BuilderTy &Builder, /// Replace a select operand based on an equality comparison with the identity /// constant of a binop. static Instruction *foldSelectBinOpIdentity(SelectInst &Sel, - const TargetLibraryInfo &TLI) { + const TargetLibraryInfo &TLI, + InstCombiner &IC) { // The select condition must be an equality compare with a constant operand. Value *X; Constant *C; @@ -107,8 +108,7 @@ static Instruction *foldSelectBinOpIdentity(SelectInst &Sel, // S = { select (cmp eq X, C), BO, ? } or { select (cmp ne X, C), ?, BO } // => // S = { select (cmp eq X, C), Y, ? } or { select (cmp ne X, C), ?, Y } - Sel.setOperand(IsEq ? 1 : 2, Y); - return &Sel; + return IC.replaceOperand(Sel, IsEq ? 1 : 2, Y); } /// This folds: @@ -997,7 +997,7 @@ static bool adjustMinMax(SelectInst &Sel, ICmpInst &Cmp) { /// constant operand of the select. static Instruction * canonicalizeMinMaxWithConstant(SelectInst &Sel, ICmpInst &Cmp, - InstCombiner::BuilderTy &Builder) { + InstCombiner &IC) { if (!Cmp.hasOneUse() || !isa(Cmp.getOperand(1))) return nullptr; @@ -1020,7 +1020,7 @@ canonicalizeMinMaxWithConstant(SelectInst &Sel, ICmpInst &Cmp, return nullptr; // Create the canonical compare and plug it into the select. - Sel.setCondition(Builder.CreateICmp(CanonicalPred, LHS, RHS)); + IC.replaceOperand(Sel, 0, IC.Builder.CreateICmp(CanonicalPred, LHS, RHS)); // If the select operands did not change, we're done. if (Sel.getTrueValue() == LHS && Sel.getFalseValue() == RHS) @@ -1329,7 +1329,7 @@ static Instruction *canonicalizeClampLike(SelectInst &Sel0, ICmpInst &Cmp0, // and swap the hands of select. static Instruction * tryToReuseConstantFromSelectInComparison(SelectInst &Sel, ICmpInst &Cmp, - InstCombiner::BuilderTy &Builder) { + InstCombiner &IC) { ICmpInst::Predicate Pred; Value *X; Constant *C0; @@ -1381,13 +1381,13 @@ tryToReuseConstantFromSelectInComparison(SelectInst &Sel, ICmpInst &Cmp, return nullptr; // It matched! Lets insert the new comparison just before select. - InstCombiner::BuilderTy::InsertPointGuard Guard(Builder); - Builder.SetInsertPoint(&Sel); + InstCombiner::BuilderTy::InsertPointGuard Guard(IC.Builder); + IC.Builder.SetInsertPoint(&Sel); Pred = ICmpInst::getSwappedPredicate(Pred); // Yes, swapped. - Value *NewCmp = Builder.CreateICmp(Pred, X, FlippedStrictness->second, - Cmp.getName() + ".inv"); - Sel.setCondition(NewCmp); + Value *NewCmp = IC.Builder.CreateICmp(Pred, X, FlippedStrictness->second, + Cmp.getName() + ".inv"); + IC.replaceOperand(Sel, 0, NewCmp); Sel.swapValues(); Sel.swapProfMetadata(); @@ -1400,7 +1400,7 @@ Instruction *InstCombiner::foldSelectInstWithICmp(SelectInst &SI, if (Value *V = foldSelectValueEquivalence(SI, *ICI, SQ)) return replaceInstUsesWith(SI, V); - if (Instruction *NewSel = canonicalizeMinMaxWithConstant(SI, *ICI, Builder)) + if (Instruction *NewSel = canonicalizeMinMaxWithConstant(SI, *ICI, *this)) return NewSel; if (Instruction *NewAbs = canonicalizeAbsNabs(SI, *ICI, Builder)) @@ -1410,7 +1410,7 @@ Instruction *InstCombiner::foldSelectInstWithICmp(SelectInst &SI, return NewAbs; if (Instruction *NewSel = - tryToReuseConstantFromSelectInComparison(SI, *ICI, Builder)) + tryToReuseConstantFromSelectInComparison(SI, *ICI, *this)) return NewSel; bool Changed = adjustMinMax(SI, *ICI); @@ -1973,7 +1973,7 @@ static Instruction *canonicalizeSelectToShuffle(SelectInst &SI) { /// other operations in IR and having all operands of a select be vector types /// is likely better for vector codegen. static Instruction *canonicalizeScalarSelectOfVecs( - SelectInst &Sel, InstCombiner::BuilderTy &Builder) { + SelectInst &Sel, InstCombiner &IC) { Type *Ty = Sel.getType(); if (!Ty->isVectorTy()) return nullptr; @@ -1987,9 +1987,7 @@ static Instruction *canonicalizeScalarSelectOfVecs( // Splatting the extracted condition reduces code (we could directly create a // splat shuffle of the source vector to eliminate the intermediate step). unsigned NumElts = Ty->getVectorNumElements(); - Value *SplatCond = Builder.CreateVectorSplat(NumElts, Cond); - Sel.setCondition(SplatCond); - return &Sel; + return IC.replaceOperand(Sel, 0, IC.Builder.CreateVectorSplat(NumElts, Cond)); } /// Reuse bitcasted operands between a compare and select: @@ -2395,7 +2393,7 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) { if (Instruction *I = canonicalizeSelectToShuffle(SI)) return I; - if (Instruction *I = canonicalizeScalarSelectOfVecs(SI, Builder)) + if (Instruction *I = canonicalizeScalarSelectOfVecs(SI, *this)) return I; // Canonicalize a one-use integer compare with a non-canonical predicate by @@ -2698,8 +2696,7 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) { if (TrueSI->getCondition() == CondVal) { if (SI.getTrueValue() == TrueSI->getTrueValue()) return nullptr; - SI.setOperand(1, TrueSI->getTrueValue()); - return &SI; + return replaceOperand(SI, 1, TrueSI->getTrueValue()); } // select(C0, select(C1, a, b), b) -> select(C0&C1, a, b) // We choose this as normal form to enable folding on the And and shortening @@ -2718,8 +2715,7 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) { if (FalseSI->getCondition() == CondVal) { if (SI.getFalseValue() == FalseSI->getFalseValue()) return nullptr; - SI.setOperand(2, FalseSI->getFalseValue()); - return &SI; + return replaceOperand(SI, 2, FalseSI->getFalseValue()); } // select(C0, a, select(C1, a, b)) -> select(C0|C1, a, b) if (FalseSI->getTrueValue() == TrueVal && FalseSI->hasOneUse()) { @@ -2788,7 +2784,7 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) { Value *NotCond; if (match(CondVal, m_Not(m_Value(NotCond)))) { - SI.setOperand(0, NotCond); + replaceOperand(SI, 0, NotCond); SI.swapValues(); SI.swapProfMetadata(); return &SI; @@ -2826,7 +2822,7 @@ Instruction *InstCombiner::visitSelectInst(SelectInst &SI) { if (Instruction *Select = foldSelectCmpXchg(SI)) return Select; - if (Instruction *Select = foldSelectBinOpIdentity(SI, TLI)) + if (Instruction *Select = foldSelectBinOpIdentity(SI, TLI, *this)) return Select; if (Instruction *Rot = foldSelectRotate(SI)) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp index 43be42a40969..49d6443d2277 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp @@ -388,8 +388,7 @@ Instruction *InstCombiner::commonShiftTransforms(BinaryOperator &I) { // demand the sign bit (and many others) here?? Value *Rem = Builder.CreateAnd(A, ConstantInt::get(I.getType(), *B - 1), Op1->getName()); - I.setOperand(1, Rem); - return &I; + return replaceOperand(I, 1, Rem); } if (Instruction *Logic = foldShiftOfShiftedLogic(I, Builder)) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp index 4277774cff23..a5f41e43f9eb 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -1739,7 +1739,8 @@ static Instruction *foldIdentityExtractShuffle(ShuffleVectorInst &Shuf) { /// Try to replace a shuffle with an insertelement or try to replace a shuffle /// operand with the operand of an insertelement. -static Instruction *foldShuffleWithInsert(ShuffleVectorInst &Shuf) { +static Instruction *foldShuffleWithInsert(ShuffleVectorInst &Shuf, + InstCombiner &IC) { Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); SmallVector Mask = Shuf.getShuffleMask(); @@ -1759,20 +1760,16 @@ static Instruction *foldShuffleWithInsert(ShuffleVectorInst &Shuf) { uint64_t IdxC; if (match(V0, m_InsertElement(m_Value(X), m_Value(), m_ConstantInt(IdxC)))) { // shuf (inselt X, ?, IdxC), ?, Mask --> shuf X, ?, Mask - if (none_of(Mask, [IdxC](int MaskElt) { return MaskElt == (int)IdxC; })) { - Shuf.setOperand(0, X); - return &Shuf; - } + if (none_of(Mask, [IdxC](int MaskElt) { return MaskElt == (int)IdxC; })) + return IC.replaceOperand(Shuf, 0, X); } if (match(V1, m_InsertElement(m_Value(X), m_Value(), m_ConstantInt(IdxC)))) { // Offset the index constant by the vector width because we are checking for // accesses to the 2nd vector input of the shuffle. IdxC += NumElts; // shuf ?, (inselt X, ?, IdxC), Mask --> shuf ?, X, Mask - if (none_of(Mask, [IdxC](int MaskElt) { return MaskElt == (int)IdxC; })) { - Shuf.setOperand(1, X); - return &Shuf; - } + if (none_of(Mask, [IdxC](int MaskElt) { return MaskElt == (int)IdxC; })) + return IC.replaceOperand(Shuf, 1, X); } // shuffle (insert ?, Scalar, IndexC), V1, Mask --> insert V1, Scalar, IndexC' @@ -1949,7 +1946,7 @@ Instruction *InstCombiner::visitShuffleVectorInst(ShuffleVectorInst &SVI) { // These transforms have the potential to lose undef knowledge, so they are // intentionally placed after SimplifyDemandedVectorElts(). - if (Instruction *I = foldShuffleWithInsert(SVI)) + if (Instruction *I = foldShuffleWithInsert(SVI, *this)) return I; if (Instruction *I = foldIdentityPaddedShuffles(SVI)) return I; -- GitLab From 571b54cc38d997ea00a5d6f8e9514c64be257c49 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Tue, 11 Feb 2020 17:41:32 +0100 Subject: [PATCH 025/142] [IRBuilder] Remove more unnecessary NoFolder methods Split out from D73835. I removed some of these before, but missed these ones. They are not part of the ConstantFolder interface and are not going to be used by the IRBuilder. --- llvm/include/llvm/IR/NoFolder.h | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/llvm/include/llvm/IR/NoFolder.h b/llvm/include/llvm/IR/NoFolder.h index 9073878476b6..c03cdee1eb83 100644 --- a/llvm/include/llvm/IR/NoFolder.h +++ b/llvm/include/llvm/IR/NoFolder.h @@ -81,10 +81,6 @@ public: return BinaryOperator::CreateExactUDiv(LHS, RHS); } - Instruction *CreateExactUDiv(Constant *LHS, Constant *RHS) const { - return BinaryOperator::CreateExactUDiv(LHS, RHS); - } - Instruction *CreateSDiv(Constant *LHS, Constant *RHS, bool isExact = false) const { if (!isExact) @@ -92,10 +88,6 @@ public: return BinaryOperator::CreateExactSDiv(LHS, RHS); } - Instruction *CreateExactSDiv(Constant *LHS, Constant *RHS) const { - return BinaryOperator::CreateExactSDiv(LHS, RHS); - } - Instruction *CreateFDiv(Constant *LHS, Constant *RHS) const { return BinaryOperator::CreateFDiv(LHS, RHS); } @@ -163,14 +155,6 @@ public: return BO; } - Instruction *CreateNSWNeg(Constant *C) const { - return BinaryOperator::CreateNSWNeg(C); - } - - Instruction *CreateNUWNeg(Constant *C) const { - return BinaryOperator::CreateNUWNeg(C); - } - Instruction *CreateFNeg(Constant *C) const { return UnaryOperator::CreateFNeg(C); } -- GitLab From 9a8defcc34853e2cdc7d97f12df98c95930556ad Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 11 Feb 2020 11:10:43 -0500 Subject: [PATCH 026/142] [OPENMP50]Add support for relaxed clause in atomic directive. Added full support for relaxed clause. --- clang/include/clang/AST/OpenMPClause.h | 40 ++++++++++ clang/include/clang/AST/RecursiveASTVisitor.h | 5 ++ .../clang/Basic/DiagnosticSemaKinds.td | 2 +- clang/include/clang/Basic/OpenMPKinds.def | 2 + clang/include/clang/Sema/Sema.h | 3 + clang/lib/AST/OpenMPClause.cpp | 6 ++ clang/lib/AST/StmtProfile.cpp | 2 + clang/lib/Basic/OpenMPKinds.cpp | 4 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 10 ++- clang/lib/Parse/ParseOpenMP.cpp | 3 +- clang/lib/Sema/SemaOpenMP.cpp | 17 ++++- clang/lib/Sema/TreeTransform.h | 7 ++ clang/lib/Serialization/ASTReader.cpp | 5 ++ clang/lib/Serialization/ASTWriter.cpp | 2 + clang/test/OpenMP/atomic_ast_print.cpp | 75 +++++++++++++++++++ clang/test/OpenMP/atomic_capture_codegen.cpp | 4 +- clang/test/OpenMP/atomic_messages.cpp | 54 +++++++++++-- clang/test/OpenMP/atomic_read_codegen.c | 4 +- clang/test/OpenMP/atomic_update_codegen.cpp | 6 +- clang/test/OpenMP/atomic_write_codegen.c | 4 +- clang/test/OpenMP/flush_messages.cpp | 2 + clang/tools/libclang/CIndex.cpp | 2 + 22 files changed, 237 insertions(+), 22 deletions(-) diff --git a/clang/include/clang/AST/OpenMPClause.h b/clang/include/clang/AST/OpenMPClause.h index 19a84bd00a36..1e6c5f928eb9 100644 --- a/clang/include/clang/AST/OpenMPClause.h +++ b/clang/include/clang/AST/OpenMPClause.h @@ -1995,6 +1995,46 @@ public: } }; +/// This represents 'relaxed' clause in the '#pragma omp atomic' +/// directives. +/// +/// \code +/// #pragma omp atomic relaxed +/// \endcode +/// In this example directive '#pragma omp atomic' has 'relaxed' clause. +class OMPRelaxedClause final : public OMPClause { +public: + /// Build 'relaxed' clause. + /// + /// \param StartLoc Starting location of the clause. + /// \param EndLoc Ending location of the clause. + OMPRelaxedClause(SourceLocation StartLoc, SourceLocation EndLoc) + : OMPClause(OMPC_relaxed, StartLoc, EndLoc) {} + + /// Build an empty clause. + OMPRelaxedClause() + : OMPClause(OMPC_relaxed, SourceLocation(), SourceLocation()) {} + + child_range children() { + return child_range(child_iterator(), child_iterator()); + } + + const_child_range children() const { + return const_child_range(const_child_iterator(), const_child_iterator()); + } + + child_range used_children() { + return child_range(child_iterator(), child_iterator()); + } + const_child_range used_children() const { + return const_child_range(const_child_iterator(), const_child_iterator()); + } + + static bool classof(const OMPClause *T) { + return T->getClauseKind() == OMPC_relaxed; + } +}; + /// This represents clause 'private' in the '#pragma omp ...' directives. /// /// \code diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h index 4ef9528dcf5b..bcbac210c00f 100644 --- a/clang/include/clang/AST/RecursiveASTVisitor.h +++ b/clang/include/clang/AST/RecursiveASTVisitor.h @@ -3136,6 +3136,11 @@ bool RecursiveASTVisitor::VisitOMPReleaseClause(OMPReleaseClause *) { return true; } +template +bool RecursiveASTVisitor::VisitOMPRelaxedClause(OMPRelaxedClause *) { + return true; +} + template bool RecursiveASTVisitor::VisitOMPThreadsClause(OMPThreadsClause *) { return true; diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 9e4e89e61031..e5714a744692 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -9696,7 +9696,7 @@ def note_omp_atomic_capture: Note< def err_omp_atomic_several_clauses : Error< "directive '#pragma omp atomic' cannot contain more than one 'read', 'write', 'update' or 'capture' clause">; def err_omp_several_mem_order_clauses : Error< - "directive '#pragma omp %0' cannot contain more than one %select{'seq_cst', |}1'acq_rel', 'acquire' or 'release' clause">; + "directive '#pragma omp %0' cannot contain more than one %select{'seq_cst', 'relaxed', |}1'acq_rel', 'acquire' or 'release' clause">; def err_omp_atomic_incompatible_mem_order_clause : Error< "directive '#pragma omp atomic%select{ %0|}1' cannot be used with '%2' clause">; def note_omp_previous_mem_order_clause : Note< diff --git a/clang/include/clang/Basic/OpenMPKinds.def b/clang/include/clang/Basic/OpenMPKinds.def index 19fcf7cfac58..13b3438fec2c 100644 --- a/clang/include/clang/Basic/OpenMPKinds.def +++ b/clang/include/clang/Basic/OpenMPKinds.def @@ -260,6 +260,7 @@ OPENMP_CLAUSE(seq_cst, OMPSeqCstClause) OPENMP_CLAUSE(acq_rel, OMPAcqRelClause) OPENMP_CLAUSE(acquire, OMPAcquireClause) OPENMP_CLAUSE(release, OMPReleaseClause) +OPENMP_CLAUSE(relaxed, OMPRelaxedClause) OPENMP_CLAUSE(depend, OMPDependClause) OPENMP_CLAUSE(device, OMPDeviceClause) OPENMP_CLAUSE(threads, OMPThreadsClause) @@ -495,6 +496,7 @@ OPENMP_ATOMIC_CLAUSE(seq_cst) OPENMP_ATOMIC_CLAUSE(acq_rel) OPENMP_ATOMIC_CLAUSE(acquire) OPENMP_ATOMIC_CLAUSE(release) +OPENMP_ATOMIC_CLAUSE(relaxed) // Clauses allowed for OpenMP directive 'target'. OPENMP_TARGET_CLAUSE(if) diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 24cfceda45dc..a93addc5bee9 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -10337,6 +10337,9 @@ public: /// Called on well-formed 'release' clause. OMPClause *ActOnOpenMPReleaseClause(SourceLocation StartLoc, SourceLocation EndLoc); + /// Called on well-formed 'relaxed' clause. + OMPClause *ActOnOpenMPRelaxedClause(SourceLocation StartLoc, + SourceLocation EndLoc); /// Called on well-formed 'threads' clause. OMPClause *ActOnOpenMPThreadsClause(SourceLocation StartLoc, SourceLocation EndLoc); diff --git a/clang/lib/AST/OpenMPClause.cpp b/clang/lib/AST/OpenMPClause.cpp index 2947665981af..6eac98250c8f 100644 --- a/clang/lib/AST/OpenMPClause.cpp +++ b/clang/lib/AST/OpenMPClause.cpp @@ -119,6 +119,7 @@ const OMPClauseWithPreInit *OMPClauseWithPreInit::get(const OMPClause *C) { case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_depend: case OMPC_threads: case OMPC_simd: @@ -196,6 +197,7 @@ const OMPClauseWithPostUpdate *OMPClauseWithPostUpdate::get(const OMPClause *C) case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_depend: case OMPC_device: case OMPC_threads: @@ -1352,6 +1354,10 @@ void OMPClausePrinter::VisitOMPReleaseClause(OMPReleaseClause *) { OS << "release"; } +void OMPClausePrinter::VisitOMPRelaxedClause(OMPRelaxedClause *) { + OS << "relaxed"; +} + void OMPClausePrinter::VisitOMPThreadsClause(OMPThreadsClause *) { OS << "threads"; } diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp index b303851a75c6..14ddc13ce561 100644 --- a/clang/lib/AST/StmtProfile.cpp +++ b/clang/lib/AST/StmtProfile.cpp @@ -524,6 +524,8 @@ void OMPClauseProfiler::VisitOMPAcquireClause(const OMPAcquireClause *) {} void OMPClauseProfiler::VisitOMPReleaseClause(const OMPReleaseClause *) {} +void OMPClauseProfiler::VisitOMPRelaxedClause(const OMPRelaxedClause *) {} + void OMPClauseProfiler::VisitOMPThreadsClause(const OMPThreadsClause *) {} void OMPClauseProfiler::VisitOMPSIMDClause(const OMPSIMDClause *) {} diff --git a/clang/lib/Basic/OpenMPKinds.cpp b/clang/lib/Basic/OpenMPKinds.cpp index 124723552af4..f13364e5378b 100644 --- a/clang/lib/Basic/OpenMPKinds.cpp +++ b/clang/lib/Basic/OpenMPKinds.cpp @@ -217,6 +217,7 @@ unsigned clang::getOpenMPSimpleClauseType(OpenMPClauseKind Kind, case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_device: case OMPC_threads: case OMPC_simd: @@ -432,6 +433,7 @@ const char *clang::getOpenMPSimpleClauseTypeName(OpenMPClauseKind Kind, case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_device: case OMPC_threads: case OMPC_simd: @@ -598,7 +600,7 @@ bool clang::isAllowedClauseForDirective(OpenMPDirectiveKind DKind, break; case OMPD_atomic: if (OpenMPVersion < 50 && (CKind == OMPC_acq_rel || CKind == OMPC_acquire || - CKind == OMPC_release)) + CKind == OMPC_release || CKind == OMPC_relaxed)) return false; switch (CKind) { #define OPENMP_ATOMIC_CLAUSE(Name) \ diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index bc71c27fd95f..16914648a34d 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -4494,6 +4494,7 @@ static void emitOMPAtomicExpr(CodeGenFunction &CGF, OpenMPClauseKind Kind, case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_shared: case OMPC_linear: case OMPC_aligned: @@ -4549,14 +4550,17 @@ void CodeGenFunction::EmitOMPAtomicDirective(const OMPAtomicDirective &S) { AO = llvm::AtomicOrdering::Acquire; else if (S.getSingleClause()) AO = llvm::AtomicOrdering::Release; + else if (S.getSingleClause()) + AO = llvm::AtomicOrdering::Monotonic; OpenMPClauseKind Kind = OMPC_unknown; for (const OMPClause *C : S.clauses()) { - // Find first clause (skip seq_cst|acq_rel|aqcuire|release clause, if it is - // first). + // Find first clause (skip seq_cst|acq_rel|aqcuire|release|relaxed clause, + // if it is first). if (C->getClauseKind() != OMPC_seq_cst && C->getClauseKind() != OMPC_acq_rel && C->getClauseKind() != OMPC_acquire && - C->getClauseKind() != OMPC_release) { + C->getClauseKind() != OMPC_release && + C->getClauseKind() != OMPC_relaxed) { Kind = C->getClauseKind(); break; } diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp index 1a7916e5adb8..c893ffc13f51 100644 --- a/clang/lib/Parse/ParseOpenMP.cpp +++ b/clang/lib/Parse/ParseOpenMP.cpp @@ -2090,7 +2090,7 @@ bool Parser::ParseOpenMPSimpleVarList( /// nogroup-clause | num_tasks-clause | hint-clause | to-clause | /// from-clause | is_device_ptr-clause | task_reduction-clause | /// in_reduction-clause | allocator-clause | allocate-clause | -/// acq_rel-clause | acquire-clause | release-clause +/// acq_rel-clause | acquire-clause | release-clause | relaxed-clause /// OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind, OpenMPClauseKind CKind, bool FirstClause) { @@ -2202,6 +2202,7 @@ OMPClause *Parser::ParseOpenMPClause(OpenMPDirectiveKind DKind, case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_threads: case OMPC_simd: case OMPC_nogroup: diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 313c9791bf87..2a13f72f6936 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -4990,6 +4990,7 @@ StmtResult Sema::ActOnOpenMPExecutableDirective( case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_depend: case OMPC_threads: case OMPC_simd: @@ -8955,7 +8956,8 @@ StmtResult Sema::ActOnOpenMPAtomicDirective(ArrayRef Clauses, if (C->getClauseKind() == OMPC_seq_cst || C->getClauseKind() == OMPC_acq_rel || C->getClauseKind() == OMPC_acquire || - C->getClauseKind() == OMPC_release) { + C->getClauseKind() == OMPC_release || + C->getClauseKind() == OMPC_relaxed) { if (MemOrderKind != OMPC_unknown) { Diag(C->getBeginLoc(), diag::err_omp_several_mem_order_clauses) << getOpenMPDirectiveName(OMPD_atomic) << 0 @@ -10918,6 +10920,7 @@ OMPClause *Sema::ActOnOpenMPSingleExprClause(OpenMPClauseKind Kind, Expr *Expr, case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_depend: case OMPC_threads: case OMPC_simd: @@ -11633,6 +11636,7 @@ static OpenMPDirectiveKind getOpenMPCaptureRegionForClause( case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_depend: case OMPC_threads: case OMPC_simd: @@ -12058,6 +12062,7 @@ OMPClause *Sema::ActOnOpenMPSimpleClause( case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_depend: case OMPC_device: case OMPC_threads: @@ -12261,6 +12266,7 @@ OMPClause *Sema::ActOnOpenMPSingleExprWithArgClause( case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_depend: case OMPC_device: case OMPC_threads: @@ -12443,6 +12449,9 @@ OMPClause *Sema::ActOnOpenMPClause(OpenMPClauseKind Kind, case OMPC_release: Res = ActOnOpenMPReleaseClause(StartLoc, EndLoc); break; + case OMPC_relaxed: + Res = ActOnOpenMPRelaxedClause(StartLoc, EndLoc); + break; case OMPC_threads: Res = ActOnOpenMPThreadsClause(StartLoc, EndLoc); break; @@ -12571,6 +12580,11 @@ OMPClause *Sema::ActOnOpenMPReleaseClause(SourceLocation StartLoc, return new (Context) OMPReleaseClause(StartLoc, EndLoc); } +OMPClause *Sema::ActOnOpenMPRelaxedClause(SourceLocation StartLoc, + SourceLocation EndLoc) { + return new (Context) OMPRelaxedClause(StartLoc, EndLoc); +} + OMPClause *Sema::ActOnOpenMPThreadsClause(SourceLocation StartLoc, SourceLocation EndLoc) { return new (Context) OMPThreadsClause(StartLoc, EndLoc); @@ -12730,6 +12744,7 @@ OMPClause *Sema::ActOnOpenMPVarListClause( case OMPC_acq_rel: case OMPC_acquire: case OMPC_release: + case OMPC_relaxed: case OMPC_device: case OMPC_threads: case OMPC_simd: diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index dffaf8938627..3f3915b8c44b 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -8825,6 +8825,13 @@ TreeTransform::TransformOMPReleaseClause(OMPReleaseClause *C) { return C; } +template +OMPClause * +TreeTransform::TransformOMPRelaxedClause(OMPRelaxedClause *C) { + // No need to rebuild this clause, no template-dependent parameters. + return C; +} + template OMPClause * TreeTransform::TransformOMPThreadsClause(OMPThreadsClause *C) { diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index c9553de8143e..a1161d264838 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -11675,6 +11675,9 @@ OMPClause *OMPClauseReader::readClause() { case OMPC_release: C = new (Context) OMPReleaseClause(); break; + case OMPC_relaxed: + C = new (Context) OMPRelaxedClause(); + break; case OMPC_threads: C = new (Context) OMPThreadsClause(); break; @@ -11943,6 +11946,8 @@ void OMPClauseReader::VisitOMPAcquireClause(OMPAcquireClause *) {} void OMPClauseReader::VisitOMPReleaseClause(OMPReleaseClause *) {} +void OMPClauseReader::VisitOMPRelaxedClause(OMPRelaxedClause *) {} + void OMPClauseReader::VisitOMPThreadsClause(OMPThreadsClause *) {} void OMPClauseReader::VisitOMPSIMDClause(OMPSIMDClause *) {} diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index eb79ba20ddf7..f935a69769bf 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -6153,6 +6153,8 @@ void OMPClauseWriter::VisitOMPAcquireClause(OMPAcquireClause *) {} void OMPClauseWriter::VisitOMPReleaseClause(OMPReleaseClause *) {} +void OMPClauseWriter::VisitOMPRelaxedClause(OMPRelaxedClause *) {} + void OMPClauseWriter::VisitOMPThreadsClause(OMPThreadsClause *) {} void OMPClauseWriter::VisitOMPSIMDClause(OMPSIMDClause *) {} diff --git a/clang/test/OpenMP/atomic_ast_print.cpp b/clang/test/OpenMP/atomic_ast_print.cpp index f3f2883d2368..5d8e92c14765 100644 --- a/clang/test/OpenMP/atomic_ast_print.cpp +++ b/clang/test/OpenMP/atomic_ast_print.cpp @@ -89,6 +89,21 @@ T foo(T argc) { a = b; b++; } +#pragma omp atomic relaxed + a++; +#pragma omp atomic read + a = argc; +#pragma omp atomic relaxed write + a = argc + argc; +#pragma omp atomic update relaxed + a = a + argc; +#pragma omp atomic relaxed capture + a = b++; +#pragma omp atomic capture relaxed + { + a = b; + b++; + } return T(); } @@ -168,6 +183,21 @@ T foo(T argc) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } +// CHECK-NEXT: #pragma omp atomic relaxed +// CHECK-NEXT: a++; +// CHECK-NEXT: #pragma omp atomic read +// CHECK-NEXT: a = argc; +// CHECK-NEXT: #pragma omp atomic relaxed write +// CHECK-NEXT: a = argc + argc; +// CHECK-NEXT: #pragma omp atomic update relaxed +// CHECK-NEXT: a = a + argc; +// CHECK-NEXT: #pragma omp atomic relaxed capture +// CHECK-NEXT: a = b++; +// CHECK-NEXT: #pragma omp atomic capture relaxed +// CHECK-NEXT: { +// CHECK-NEXT: a = b; +// CHECK-NEXT: b++; +// CHECK-NEXT: } // CHECK: int a = int(); // CHECK-NEXT: #pragma omp atomic // CHECK-NEXT: a++; @@ -244,6 +274,21 @@ T foo(T argc) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } +// CHECK-NEXT: #pragma omp atomic relaxed +// CHECK-NEXT: a++; +// CHECK-NEXT: #pragma omp atomic read +// CHECK-NEXT: a = argc; +// CHECK-NEXT: #pragma omp atomic relaxed write +// CHECK-NEXT: a = argc + argc; +// CHECK-NEXT: #pragma omp atomic update relaxed +// CHECK-NEXT: a = a + argc; +// CHECK-NEXT: #pragma omp atomic relaxed capture +// CHECK-NEXT: a = b++; +// CHECK-NEXT: #pragma omp atomic capture relaxed +// CHECK-NEXT: { +// CHECK-NEXT: a = b; +// CHECK-NEXT: b++; +// CHECK-NEXT: } int main(int argc, char **argv) { int b = 0; @@ -324,6 +369,21 @@ int main(int argc, char **argv) { a = b; b++; } +#pragma omp atomic relaxed + a++; +#pragma omp atomic read + a = argc; +#pragma omp atomic relaxed write + a = argc + argc; +#pragma omp atomic update relaxed + a = a + argc; +#pragma omp atomic relaxed capture + a = b++; +#pragma omp atomic capture relaxed + { + a = b; + b++; + } // CHECK-NEXT: #pragma omp atomic // CHECK-NEXT: a++; // CHECK-NEXT: #pragma omp atomic read @@ -399,6 +459,21 @@ int main(int argc, char **argv) { // CHECK-NEXT: a = b; // CHECK-NEXT: b++; // CHECK-NEXT: } + // CHECK-NEXT: #pragma omp atomic relaxed + // CHECK-NEXT: a++; + // CHECK-NEXT: #pragma omp atomic read + // CHECK-NEXT: a = argc; + // CHECK-NEXT: #pragma omp atomic relaxed write + // CHECK-NEXT: a = argc + argc; + // CHECK-NEXT: #pragma omp atomic update relaxed + // CHECK-NEXT: a = a + argc; + // CHECK-NEXT: #pragma omp atomic relaxed capture + // CHECK-NEXT: a = b++; + // CHECK-NEXT: #pragma omp atomic capture relaxed + // CHECK-NEXT: { + // CHECK-NEXT: a = b; + // CHECK-NEXT: b++; + // CHECK-NEXT: } return foo(a); } diff --git a/clang/test/OpenMP/atomic_capture_codegen.cpp b/clang/test/OpenMP/atomic_capture_codegen.cpp index 3164c4f419f5..d7b8748bbc24 100644 --- a/clang/test/OpenMP/atomic_capture_codegen.cpp +++ b/clang/test/OpenMP/atomic_capture_codegen.cpp @@ -843,7 +843,7 @@ int main() { // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: store i32 [[NEW_VAL]], i32* @{{.+}}, -#pragma omp atomic capture +#pragma omp atomic relaxed capture iv = bfx4.a = bfx4.a * ldv; // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[PREV_VALUE:%.+]] = load atomic i8, i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @{{.+}}, i32 0, i32 0, i64 2) monotonic @@ -874,7 +874,7 @@ int main() { // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] // CHECK: store i32 [[CAST]], i32* @{{.+}}, -#pragma omp atomic capture +#pragma omp atomic capture relaxed {iv = bfx4_packed.a; bfx4_packed.a -= ldv;} // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[PREV_VALUE:%.+]] = load atomic i64, i64* bitcast (%struct.BitFields4* @{{.+}} to i64*) monotonic diff --git a/clang/test/OpenMP/atomic_messages.cpp b/clang/test/OpenMP/atomic_messages.cpp index af5fc90b35a3..c44405178c84 100644 --- a/clang/test/OpenMP/atomic_messages.cpp +++ b/clang/test/OpenMP/atomic_messages.cpp @@ -733,7 +733,7 @@ T acq_rel() { // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; -// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'acq_rel' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} omp50-error@+1 2 {{directive '#pragma omp atomic read' cannot be used with 'acq_rel' clause}} omp50-note@+1 2 {{'acq_rel' clause used here}} +// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'relaxed', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'acq_rel' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} omp50-error@+1 2 {{directive '#pragma omp atomic read' cannot be used with 'acq_rel' clause}} omp50-note@+1 2 {{'acq_rel' clause used here}} #pragma omp atomic read acq_rel seq_cst a = b; @@ -754,7 +754,7 @@ int acq_rel() { // expected-error@+2 {{the statement for 'atomic write' must be an expression statement of form 'x = expr;', where x is a lvalue expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; -// omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} +// omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'relaxed', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp atomic'}} #pragma omp atomic seq_cst acq_rel a += b; @@ -775,7 +775,7 @@ T acquire() { // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; -// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'acquire' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} omp50-error@+1 2 {{directive '#pragma omp atomic' cannot be used with 'acquire' clause}} omp50-note@+1 2 {{'acquire' clause used here}} +// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'relaxed', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'acquire' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} omp50-error@+1 2 {{directive '#pragma omp atomic' cannot be used with 'acquire' clause}} omp50-note@+1 2 {{'acquire' clause used here}} #pragma omp atomic acquire seq_cst a += b; @@ -796,7 +796,7 @@ int acquire() { // expected-error@+2 {{the statement for 'atomic write' must be an expression statement of form 'x = expr;', where x is a lvalue expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; -// omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} +// omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'relaxed', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'acquire' in directive '#pragma omp atomic'}} #pragma omp atomic seq_cst acquire a += b; @@ -817,7 +817,7 @@ T release() { // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} // expected-note@+1 {{expected an expression statement}} ; -// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'release' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'release' in directive '#pragma omp atomic'}} +// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'relaxed', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'release' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'release' in directive '#pragma omp atomic'}} #pragma omp atomic release seq_cst a += b; @@ -838,7 +838,7 @@ int release() { // expected-error@+2 {{the statement for 'atomic read' must be an expression statement of form 'v = x;', where v and x are both lvalue expressions with scalar type}} // expected-note@+1 {{expected an expression statement}} ; -// omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'release' in directive '#pragma omp atomic'}} +// omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'relaxed', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'release' in directive '#pragma omp atomic'}} #pragma omp atomic seq_cst release a += b; @@ -851,6 +851,48 @@ int release() { return release(); // omp50-note {{in instantiation of function template specialization 'release' requested here}} } +template +T relaxed() { + T a = 0, b = 0; +// omp45-error@+1 {{unexpected OpenMP clause 'relaxed' in directive '#pragma omp atomic'}} +#pragma omp atomic relaxed + // expected-error@+2 {{the statement for 'atomic' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} + // expected-note@+1 {{expected an expression statement}} + ; +// omp50-error@+1 2 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'relaxed', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 2 {{'relaxed' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'relaxed' in directive '#pragma omp atomic'}} +#pragma omp atomic relaxed seq_cst + a += b; + +// omp45-error@+1 {{unexpected OpenMP clause 'relaxed' in directive '#pragma omp atomic'}} +#pragma omp atomic update relaxed + // expected-error@+2 {{the statement for 'atomic update' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} + // expected-note@+1 {{expected an expression statement}} + ; + + return T(); +} + +int relaxed() { + int a = 0, b = 0; +// Test for atomic relaxed +// omp45-error@+1 {{unexpected OpenMP clause 'relaxed' in directive '#pragma omp atomic'}} +#pragma omp atomic read relaxed + // expected-error@+2 {{the statement for 'atomic read' must be an expression statement of form 'v = x;', where v and x are both lvalue expressions with scalar type}} + // expected-note@+1 {{expected an expression statement}} + ; +// omp50-error@+1 {{directive '#pragma omp atomic' cannot contain more than one 'seq_cst', 'relaxed', 'acq_rel', 'acquire' or 'release' clause}} omp50-note@+1 {{'seq_cst' clause used here}} omp45-error@+1 {{unexpected OpenMP clause 'relaxed' in directive '#pragma omp atomic'}} +#pragma omp atomic seq_cst relaxed + a += b; + +// omp45-error@+1 {{unexpected OpenMP clause 'relaxed' in directive '#pragma omp atomic'}} +#pragma omp atomic update relaxed + // expected-error@+2 {{the statement for 'atomic update' must be an expression statement of form '++x;', '--x;', 'x++;', 'x--;', 'x binop= expr;', 'x = x binop expr' or 'x = expr binop x', where x is an l-value expression with scalar type}} + // expected-note@+1 {{expected an expression statement}} + ; + + return relaxed(); // omp50-note {{in instantiation of function template specialization 'relaxed' requested here}} +} + template T mixed() { T a, b = T(); diff --git a/clang/test/OpenMP/atomic_read_codegen.c b/clang/test/OpenMP/atomic_read_codegen.c index 8d49115bc603..94e212f72447 100644 --- a/clang/test/OpenMP/atomic_read_codegen.c +++ b/clang/test/OpenMP/atomic_read_codegen.c @@ -304,7 +304,7 @@ int main() { // CHECK: [[ASHR:%.+]] = ashr i8 [[SHL]], 7 // CHECK: sext i8 [[ASHR]] to i32 // CHECK: store x86_fp80 -#pragma omp atomic read +#pragma omp atomic relaxed read ldv = bfx4_packed.a; // CHECK: [[LD:%.+]] = load atomic i64, i64* bitcast (%struct.BitFields4* @bfx4 to i64*) monotonic // CHECK: store i64 [[LD]], i64* [[LDTEMP:%.+]] @@ -312,7 +312,7 @@ int main() { // CHECK: [[SHL:%.+]] = shl i64 [[LD]], 40 // CHECK: [[ASHR:%.+]] = ashr i64 [[SHL]], 57 // CHECK: store x86_fp80 -#pragma omp atomic read +#pragma omp atomic read relaxed ldv = bfx4.b; // CHECK: [[LD:%.+]] = load atomic i8, i8* getelementptr inbounds (%struct.BitFields4_packed, %struct.BitFields4_packed* @bfx4_packed, i32 0, i32 0, i64 2) acquire // CHECK: store i8 [[LD]], i8* [[LDTEMP:%.+]] diff --git a/clang/test/OpenMP/atomic_update_codegen.cpp b/clang/test/OpenMP/atomic_update_codegen.cpp index 7913dc1ce69f..a2b6f70540aa 100644 --- a/clang/test/OpenMP/atomic_update_codegen.cpp +++ b/clang/test/OpenMP/atomic_update_codegen.cpp @@ -809,7 +809,7 @@ int main() { // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -#pragma omp atomic update +#pragma omp atomic relaxed update bfx4_packed.a -= ldv; // CHECK: [[EXPR:%.+]] = load x86_fp80, x86_fp80* @{{.+}} // CHECK: [[PREV_VALUE:%.+]] = load atomic i64, i64* bitcast (%struct.BitFields4* @{{.+}} to i64*) monotonic @@ -866,7 +866,7 @@ int main() { // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -#pragma omp atomic update +#pragma omp atomic update relaxed bfx4_packed.b += ldv; // CHECK: load i64, i64* // CHECK: [[EXPR:%.+]] = uitofp i64 %{{.+}} to float @@ -890,7 +890,7 @@ int main() { // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -#pragma omp atomic +#pragma omp atomic relaxed float2x.x = ulv - float2x.x; // CHECK: [[EXPR:%.+]] = load double, double* @{{.+}}, // CHECK: [[OLD_VAL:%.+]] = call i32 @llvm.read_register.i32([[REG:metadata ![0-9]+]]) diff --git a/clang/test/OpenMP/atomic_write_codegen.c b/clang/test/OpenMP/atomic_write_codegen.c index 053f46d55246..3cbaf2752448 100644 --- a/clang/test/OpenMP/atomic_write_codegen.c +++ b/clang/test/OpenMP/atomic_write_codegen.c @@ -486,7 +486,7 @@ int main() { // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i8, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -#pragma omp atomic write +#pragma omp atomic relaxed write bfx4_packed.b = ldv; // CHECK: load i64, i64* // CHECK: [[VEC_ITEM_VAL:%.+]] = uitofp i64 %{{.+}} to float @@ -505,7 +505,7 @@ int main() { // CHECK: [[FAIL_SUCCESS:%.+]] = extractvalue { i64, i1 } [[RES]], 1 // CHECK: br i1 [[FAIL_SUCCESS]], label %[[EXIT:.+]], label %[[CONT]] // CHECK: [[EXIT]] -#pragma omp atomic write +#pragma omp atomic write relaxed float2x.x = ulv; // CHECK: call i32 @llvm.read_register.i32( // CHECK: sitofp i32 %{{.+}} to double diff --git a/clang/test/OpenMP/flush_messages.cpp b/clang/test/OpenMP/flush_messages.cpp index 48a70f3f8dcb..51497249a8f3 100644 --- a/clang/test/OpenMP/flush_messages.cpp +++ b/clang/test/OpenMP/flush_messages.cpp @@ -138,6 +138,8 @@ label1 : { #pragma omp flush acq_rel // omp45-error {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp flush'}} #pragma omp flush acquire // omp45-error {{unexpected OpenMP clause 'acquire' in directive '#pragma omp flush'}} #pragma omp flush release // omp45-error {{unexpected OpenMP clause 'release' in directive '#pragma omp flush'}} +#pragma omp flush relaxed // expected-error {{unexpected OpenMP clause 'relaxed' in directive '#pragma omp flush'}} +#pragma omp flush seq_cst // expected-error {{unexpected OpenMP clause 'seq_cst' in directive '#pragma omp flush'}} #pragma omp flush acq_rel acquire // omp45-error {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp flush'}} omp45-error {{unexpected OpenMP clause 'acquire' in directive '#pragma omp flush'}} omp50-error {{directive '#pragma omp flush' cannot contain more than one 'acq_rel', 'acquire' or 'release' clause}} omp50-note {{'acq_rel' clause used here}} #pragma omp flush release acquire // omp45-error {{unexpected OpenMP clause 'release' in directive '#pragma omp flush'}} omp45-error {{unexpected OpenMP clause 'acquire' in directive '#pragma omp flush'}} omp50-error {{directive '#pragma omp flush' cannot contain more than one 'acq_rel', 'acquire' or 'release' clause}} omp50-note {{'release' clause used here}} #pragma omp flush acq_rel (argc) // omp45-error {{unexpected OpenMP clause 'acq_rel' in directive '#pragma omp flush'}} omp50-error {{'flush' directive with memory order clause 'acq_rel' cannot have the list}} omp50-note {{memory order clause 'acq_rel' is specified here}} diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp index 12479c7abb84..6f32240fe6e4 100644 --- a/clang/tools/libclang/CIndex.cpp +++ b/clang/tools/libclang/CIndex.cpp @@ -2241,6 +2241,8 @@ void OMPClauseEnqueue::VisitOMPAcquireClause(const OMPAcquireClause *) {} void OMPClauseEnqueue::VisitOMPReleaseClause(const OMPReleaseClause *) {} +void OMPClauseEnqueue::VisitOMPRelaxedClause(const OMPRelaxedClause *) {} + void OMPClauseEnqueue::VisitOMPThreadsClause(const OMPThreadsClause *) {} void OMPClauseEnqueue::VisitOMPSIMDClause(const OMPSIMDClause *) {} -- GitLab From 77a9e61c9ac89e93809789f904085dbf365829c4 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Sat, 11 Jan 2020 23:36:17 -0600 Subject: [PATCH 027/142] [Attributor][NFC] Improve debug message --- llvm/lib/Transforms/IPO/Attributor.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index 31a7e93b239a..a7b51b314d85 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -7705,10 +7705,12 @@ static bool runAttributorOnFunctions(InformationCache &InfoCache, A.identifyDefaultAbstractAttributes(*F); } - bool Changed = A.run() == ChangeStatus::CHANGED; + ChangeStatus Changed = A.run(); assert(!verifyModule(*Functions.front()->getParent(), &errs()) && "Module verification failed!"); - return Changed; + LLVM_DEBUG(dbgs() << "[Attributor] Done with " << Functions.size() + << " functions, result: " << Changed << ".\n"); + return Changed == ChangeStatus::CHANGED; } PreservedAnalyses AttributorPass::run(Module &M, ModuleAnalysisManager &AM) { -- GitLab From 4c62a358602e88abc275009bd4170b891eb07870 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Sun, 12 Jan 2020 00:17:08 -0600 Subject: [PATCH 028/142] [Attributor][FIX] Remove duplicate, half-broken functionality The changeXXXAfterManifest functions are better suited to deal with changes so we should prefer them. These functions also recursively delete dead instructions which is why we see test changes. --- llvm/include/llvm/Transforms/IPO/Attributor.h | 11 ---- llvm/lib/Transforms/IPO/Attributor.cpp | 11 ++-- .../live_called_from_dead.ll | 43 +++++++++++---- .../Attributor/ArgumentPromotion/musttail.ll | 52 ++++++++++++++++--- .../Attributor/IPConstantProp/comdat-ipo.ll | 1 - .../IPConstantProp/remove-call-inst.ll | 13 ----- .../IPConstantProp/return-constant.ll | 1 - ...fter-each-resolving-undefs-for-function.ll | 24 --------- llvm/test/Transforms/Attributor/liveness.ll | 31 +++++++++-- llvm/test/Transforms/Attributor/nonnull.ll | 6 ++- llvm/test/Transforms/Attributor/range.ll | 47 +++-------------- .../Attributor/undefined_behavior.ll | 2 - 12 files changed, 122 insertions(+), 120 deletions(-) diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h index 2228b62c0ca6..8437ed260f6c 100644 --- a/llvm/include/llvm/Transforms/IPO/Attributor.h +++ b/llvm/include/llvm/Transforms/IPO/Attributor.h @@ -1023,17 +1023,6 @@ struct Attributor { /// Return the data layout associated with the anchor scope. const DataLayout &getDataLayout() const { return InfoCache.DL; } - /// Replace all uses of \p Old with \p New and, for calls (and invokes), - /// update the call graph. - void replaceAllUsesWith(Value &Old, Value &New) { - if (CallBase *OldCB = dyn_cast(&Old)) { - // We do not modify the call graph here but simply reanalyze the old - // function. This should be revisited once the old PM is gone. - CGModifiedFunctions.insert(OldCB->getFunction()); - } - Old.replaceAllUsesWith(&New); - } - private: /// Check \p Pred on all call sites of \p Fn. /// diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index a7b51b314d85..52eafe5b8a4e 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -1192,8 +1192,9 @@ ChangeStatus AAReturnedValuesImpl::manifest(Attributor &A) { auto ReplaceCallSiteUsersWith = [&A](CallBase &CB, Constant &C) { if (CB.getNumUses() == 0 || CB.isMustTailCall()) return ChangeStatus::UNCHANGED; - A.replaceAllUsesWith(CB, C); - return ChangeStatus::CHANGED; + if (A.changeValueAfterManifest(CB, C)) + return ChangeStatus::CHANGED; + return ChangeStatus::UNCHANGED; }; // If the assumed unique return value is an argument, annotate it. @@ -4443,8 +4444,8 @@ struct AAValueSimplifyImpl : AAValueSimplify { if (!V.user_empty() && &V != C && V.getType() == C->getType()) { LLVM_DEBUG(dbgs() << "[ValueSimplify] " << V << " -> " << *C << " :: " << *this << "\n"); - A.changeValueAfterManifest(V, *C); - Changed = ChangeStatus::CHANGED; + if (A.changeValueAfterManifest(V, *C)) + Changed = ChangeStatus::CHANGED; } } @@ -4696,7 +4697,7 @@ struct AAHeapToStackImpl : public AAHeapToStack { AI = new BitCastInst(AI, MallocCall->getType(), "malloc_bc", AI->getNextNode()); - A.replaceAllUsesWith(*MallocCall, *AI); + A.changeValueAfterManifest(*MallocCall, *AI); if (auto *II = dyn_cast(MallocCall)) { auto *NBB = II->getNormalDest(); diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll index 6677cb546725..3396cf3b4ac7 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes -; RUN: opt -S -basicaa -attributor -attributor-disable=false -attributor-max-iterations-verify -attributor-max-iterations=3 < %s | FileCheck %s --check-prefixes=CHECK,OLDPM_MODULE -; RUN: opt -S -basicaa -attributor-cgscc -attributor-disable=false < %s | FileCheck %s --check-prefixes=CHECK,OLDPM_CGSCC -; RUN: opt -S -passes='attributor' -aa-pipeline='basic-aa' -attributor-disable=false -attributor-max-iterations-verify -attributor-max-iterations=3 < %s | FileCheck %s --check-prefixes=CHECK,NEWPM_MODULE -; RUN: opt -S -passes='attributor-cgscc' -aa-pipeline='basic-aa' -attributor-disable=false < %s | FileCheck %s --check-prefixes=CHECK,NEWPM_CGSCC +; RUN: opt -S -basicaa -attributor -attributor-disable=false -attributor-max-iterations-verify -attributor-max-iterations=3 < %s | FileCheck %s --check-prefixes=CHECK,OLDPM,OLDPM_MODULE +; RUN: opt -S -basicaa -attributor-cgscc -attributor-disable=false < %s | FileCheck %s --check-prefixes=CHECK,OLDPM,OLDPM_CGSCC +; RUN: opt -S -passes='attributor' -aa-pipeline='basic-aa' -attributor-disable=false -attributor-max-iterations-verify -attributor-max-iterations=3 < %s | FileCheck %s --check-prefixes=CHECK,NEWPM,NEWPM_MODULE +; RUN: opt -S -passes='attributor-cgscc' -aa-pipeline='basic-aa' -attributor-disable=false < %s | FileCheck %s --check-prefixes=CHECK,NEWPM,NEWPM_CGSCC ; OLDPM_MODULE-NOT: @dead ; NEWPM_MODULE-NOT: @dead @@ -15,15 +15,36 @@ define internal void @dead() { } define internal i32 @test(i32* %X, i32* %Y) { -; CHECK-LABEL: define {{[^@]+}}@test() -; CHECK-NEXT: br i1 true, label [[LIVE:%.*]], label [[DEAD:%.*]] -; CHECK: live: -; CHECK-NEXT: ret i32 0 -; CHECK: dead: -; CHECK-NEXT: unreachable +; OLDPM-LABEL: define {{[^@]+}}@test +; OLDPM-SAME: (i32* noalias nocapture nofree writeonly align 4 [[X:%.*]]) +; OLDPM-NEXT: br i1 true, label [[LIVE:%.*]], label [[DEAD:%.*]] +; OLDPM: live: +; OLDPM-NEXT: store i32 0, i32* [[X]], align 4 +; OLDPM-NEXT: ret i32 0 +; OLDPM: dead: +; OLDPM-NEXT: unreachable +; +; NEWPM_MODULE-LABEL: define {{[^@]+}}@test +; NEWPM_MODULE-SAME: (i32* noalias nocapture nofree writeonly align 4 [[X:%.*]]) +; NEWPM_MODULE-NEXT: br i1 true, label [[LIVE:%.*]], label [[DEAD:%.*]] +; NEWPM_MODULE: live: +; NEWPM_MODULE-NEXT: store i32 0, i32* [[X]], align 4 +; NEWPM_MODULE-NEXT: ret i32 0 +; NEWPM_MODULE: dead: +; NEWPM_MODULE-NEXT: unreachable +; +; NEWPM_CGSCC-LABEL: define {{[^@]+}}@test +; NEWPM_CGSCC-SAME: (i32* noalias nocapture nofree nonnull writeonly align 4 dereferenceable(4) [[X:%.*]]) +; NEWPM_CGSCC-NEXT: br i1 true, label [[LIVE:%.*]], label [[DEAD:%.*]] +; NEWPM_CGSCC: live: +; NEWPM_CGSCC-NEXT: store i32 0, i32* [[X]], align 4 +; NEWPM_CGSCC-NEXT: ret i32 0 +; NEWPM_CGSCC: dead: +; NEWPM_CGSCC-NEXT: unreachable ; br i1 true, label %live, label %dead live: + store i32 0, i32* %X ret i32 0 dead: call i32 @caller(i32* null) @@ -35,7 +56,7 @@ define internal i32 @caller(i32* %B) { ; CHECK-LABEL: define {{[^@]+}}@caller() ; CHECK-NEXT: [[A:%.*]] = alloca i32 ; CHECK-NEXT: store i32 1, i32* [[A]], align 4 -; CHECK-NEXT: [[C:%.*]] = call i32 @test() +; CHECK-NEXT: [[C:%.*]] = call i32 @test(i32* noalias nocapture nofree nonnull writeonly align 4 dereferenceable(4) [[A]]) ; CHECK-NEXT: ret i32 0 ; %A = alloca i32 diff --git a/llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll b/llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll index 2c83cbb4aff4..ac0fc2b9951c 100644 --- a/llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll +++ b/llvm/test/Transforms/Attributor/ArgumentPromotion/musttail.ll @@ -45,11 +45,6 @@ define i32 @foo(%T* %p, i32 %v) { } define internal i32 @test2(%T* %p, i32 %p2) { -; CHECK-LABEL: define {{[^@]+}}@test2 -; CHECK-SAME: (%T* nocapture nofree readonly [[P:%.*]], i32 [[P2:%.*]]) -; CHECK-NEXT: [[CA:%.*]] = musttail call i32 @foo(%T* undef, i32 undef) -; CHECK-NEXT: ret i32 [[CA]] -; %a.gep = getelementptr %T, %T* %p, i64 0, i32 3 %b.gep = getelementptr %T, %T* %p, i64 0, i32 2 %a = load i32, i32* %a.gep @@ -62,9 +57,54 @@ define internal i32 @test2(%T* %p, i32 %p2) { define i32 @caller2(%T* %g) { ; CHECK-LABEL: define {{[^@]+}}@caller2 ; CHECK-SAME: (%T* nocapture nofree readonly [[G:%.*]]) -; CHECK-NEXT: [[V:%.*]] = call i32 @test2(%T* nocapture nofree readonly undef, i32 undef) ; CHECK-NEXT: ret i32 0 ; %v = call i32 @test2(%T* %g, i32 0) ret i32 %v } + +; In the version above we can remove the call to foo completely. +; In the version below we keep the call and verify the return value +; is kept as well. + +define i32 @bar(%T* %p, i32 %v) { +; CHECK-LABEL: define {{[^@]+}}@bar +; CHECK-SAME: (%T* nocapture nofree nonnull writeonly dereferenceable(4) [[P:%.*]], i32 [[V:%.*]]) +; CHECK-NEXT: [[I32PTR:%.*]] = getelementptr [[T:%.*]], %T* [[P]], i64 0, i32 0 +; CHECK-NEXT: store i32 [[V]], i32* [[I32PTR]] +; CHECK-NEXT: ret i32 0 +; + %i32ptr = getelementptr %T, %T* %p, i64 0, i32 0 + store i32 %v, i32* %i32ptr + ret i32 0 +} + +define internal i32 @test2b(%T* %p, i32 %p2) { +; CHECK-LABEL: define {{[^@]+}}@test2b +; CHECK-SAME: (%T* nocapture nofree readonly [[P:%.*]], i32 [[P2:%.*]]) +; CHECK-NEXT: [[A_GEP:%.*]] = getelementptr [[T:%.*]], %T* [[P]], i64 0, i32 3 +; CHECK-NEXT: [[B_GEP:%.*]] = getelementptr [[T]], %T* [[P]], i64 0, i32 2 +; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[A_GEP]] +; CHECK-NEXT: [[B:%.*]] = load i32, i32* [[B_GEP]] +; CHECK-NEXT: [[V:%.*]] = add i32 [[A]], [[B]] +; CHECK-NEXT: [[CA:%.*]] = musttail call i32 @bar(%T* undef, i32 [[V]]) +; CHECK-NEXT: ret i32 [[CA]] +; + %a.gep = getelementptr %T, %T* %p, i64 0, i32 3 + %b.gep = getelementptr %T, %T* %p, i64 0, i32 2 + %a = load i32, i32* %a.gep + %b = load i32, i32* %b.gep + %v = add i32 %a, %b + %ca = musttail call i32 @bar(%T* undef, i32 %v) + ret i32 %ca +} + +define i32 @caller2b(%T* %g) { +; CHECK-LABEL: define {{[^@]+}}@caller2b +; CHECK-SAME: (%T* nocapture nofree readonly [[G:%.*]]) +; CHECK-NEXT: [[V:%.*]] = call i32 @test2b(%T* nocapture nofree readonly [[G]], i32 undef) +; CHECK-NEXT: ret i32 0 +; + %v = call i32 @test2b(%T* %g, i32 0) + ret i32 %v +} diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/comdat-ipo.ll b/llvm/test/Transforms/Attributor/IPConstantProp/comdat-ipo.ll index 2f50a9c3d203..2fcde7a92288 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/comdat-ipo.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/comdat-ipo.ll @@ -15,7 +15,6 @@ define i32 @baz() { define linkonce_odr i32 @foo() { ; CHECK-LABEL: define {{[^@]+}}@foo() -; CHECK-NEXT: [[VAL:%.*]] = call i32 @baz() ; CHECK-NEXT: ret i32 10 ; diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/remove-call-inst.ll b/llvm/test/Transforms/Attributor/IPConstantProp/remove-call-inst.ll index 3e0b575f94f5..339a9fc4b767 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/remove-call-inst.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/remove-call-inst.ll @@ -10,7 +10,6 @@ define i32 @main() noreturn nounwind { ; CHECK-LABEL: define {{[^@]+}}@main() ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 @wwrite(i64 0) ; CHECK-NEXT: ret i32 123 ; entry: @@ -19,18 +18,6 @@ entry: } define internal i32 @wwrite(i64 %i) nounwind readnone { -; CHECK-LABEL: define {{[^@]+}}@wwrite -; CHECK-SAME: (i64 [[I:%.*]]) -; CHECK-NEXT: entry: -; CHECK-NEXT: switch i64 0, label [[SW_DEFAULT:%.*]] [ -; CHECK-NEXT: i64 3, label [[RETURN:%.*]] -; CHECK-NEXT: i64 10, label [[RETURN]] -; CHECK-NEXT: ] -; CHECK: sw.default: -; CHECK-NEXT: ret i32 123 -; CHECK: return: -; CHECK-NEXT: unreachable -; entry: switch i64 %i, label %sw.default [ i64 3, label %return diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll b/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll index 4bc1b25572d4..cfbef759d41c 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/return-constant.ll @@ -44,7 +44,6 @@ F: ; preds = %0 define i1 @caller(i1 %C) { ; CHECK-LABEL: define {{[^@]+}}@caller ; CHECK-SAME: (i1 [[C:%.*]]) -; CHECK-NEXT: [[X:%.*]] = call i32 @foo(i1 [[C]]) ; CHECK-NEXT: ret i1 true ; %X = call i32 @foo( i1 %C ) ; [#uses=1] diff --git a/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll b/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll index ff33eccb2255..ba3f9f929cd5 100644 --- a/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll +++ b/llvm/test/Transforms/Attributor/IPConstantProp/solve-after-each-resolving-undefs-for-function.ll @@ -2,17 +2,6 @@ ; RUN: opt -S -passes=attributor -aa-pipeline='basic-aa' -attributor-disable=false -attributor-max-iterations-verify -attributor-max-iterations=2 < %s | FileCheck %s define internal i32 @testf(i1 %c) { -; CHECK-LABEL: define {{[^@]+}}@testf -; CHECK-SAME: (i1 [[C:%.*]]) -; CHECK-NEXT: entry: -; CHECK-NEXT: br i1 [[C]], label [[IF_COND:%.*]], label [[IF_END:%.*]] -; CHECK: if.cond: -; CHECK-NEXT: unreachable -; CHECK: if.then: -; CHECK-NEXT: unreachable -; CHECK: if.end: -; CHECK-NEXT: ret i32 10 -; entry: br i1 %c, label %if.cond, label %if.end @@ -27,18 +16,6 @@ if.end: ; preds = %if.then1, %entry } define internal i32 @test1(i1 %c) { -; CHECK-LABEL: define {{[^@]+}}@test1 -; CHECK-SAME: (i1 [[C:%.*]]) -; CHECK-NEXT: entry: -; CHECK-NEXT: br label [[IF_THEN:%.*]] -; CHECK: if.then: -; CHECK-NEXT: [[CALL:%.*]] = call i32 @testf(i1 [[C]]) -; CHECK-NEXT: br label [[RET1:%.*]] -; CHECK: ret1: -; CHECK-NEXT: ret i32 99 -; CHECK: ret2: -; CHECK-NEXT: unreachable -; entry: br label %if.then @@ -57,7 +34,6 @@ ret2: ; preds = %if.then, %entry define i32 @main(i1 %c) { ; CHECK-LABEL: define {{[^@]+}}@main ; CHECK-SAME: (i1 [[C:%.*]]) -; CHECK-NEXT: [[RES:%.*]] = call i32 @test1(i1 [[C]]) ; CHECK-NEXT: ret i32 99 ; %res = call i32 @test1(i1 %c) diff --git a/llvm/test/Transforms/Attributor/liveness.ll b/llvm/test/Transforms/Attributor/liveness.ll index d8e879e02279..4f1cc36f14ce 100644 --- a/llvm/test/Transforms/Attributor/liveness.ll +++ b/llvm/test/Transforms/Attributor/liveness.ll @@ -544,6 +544,7 @@ define internal i8* @f3(i8* readnone %0) local_unnamed_addr #0 { ret i8* %6 } +declare void @sink() nofree nosync nounwind willreturn define void @test_unreachable() { ; CHECK: define void @test_unreachable() ; CHECK-NEXT: call void @test_unreachable() @@ -906,6 +907,7 @@ define internal i32 @switch_default(i64 %i) nounwind { ; CHECK-NEXT: i64 10, label [[RETURN]] ; CHECK-NEXT: ] ; CHECK: sw.default: +; CHECK-NEXT: call void @sink() ; CHECK-NEXT: ret i32 123 ; CHECK: return: ; CHECK-NEXT: unreachable @@ -917,6 +919,7 @@ entry: ] sw.default: + call void @sink() ret i32 123 return: @@ -924,13 +927,35 @@ return: } define i32 @switch_default_caller() { -; CHECK-LABEL: define {{[^@]+}}@switch_default_caller() -; CHECK-NEXT: [[CALL2:%.*]] = tail call i32 @switch_default(i64 0) -; CHECK-NEXT: ret i32 123 +; CGSCC-LABEL: define {{[^@]+}}@switch_default_caller() +; CGSCC-NEXT: [[CALL2:%.*]] = tail call i32 @switch_default(i64 0) +; CGSCC-NEXT: ret i32 123 ; %call2 = tail call i32 @switch_default(i64 0) ret i32 %call2 } + +define internal i32 @switch_default_dead(i64 %i) nounwind { +entry: + switch i64 %i, label %sw.default [ + i64 3, label %return + i64 10, label %return + ] + +sw.default: + ret i32 123 + +return: + ret i32 0 +} + +define i32 @switch_default_dead_caller() { +; CHECK-LABEL: define {{[^@]+}}@switch_default_dead_caller() +; CHECK-NEXT: ret i32 123 +; + %call2 = tail call i32 @switch_default_dead(i64 0) + ret i32 %call2 +} ; UTC_ARGS: --turn off ; Allow blockaddress users diff --git a/llvm/test/Transforms/Attributor/nonnull.ll b/llvm/test/Transforms/Attributor/nonnull.ll index 7420a39b8907..f11f3941aaa8 100644 --- a/llvm/test/Transforms/Attributor/nonnull.ll +++ b/llvm/test/Transforms/Attributor/nonnull.ll @@ -525,12 +525,14 @@ define i32 addrspace(3)* @as(i32 addrspace(3)* dereferenceable(4) %p) { ret i32 addrspace(3)* %p } -; ATTRIBUTOR: define internal nonnull align 4 i32* @g2() +; ATTRIBUTOR-NOT: @g2() define internal i32* @g2() { ret i32* inttoptr (i64 4 to i32*) } -define i32* @g1() { +; ATTRIBUTOR: define nonnull align 4 i32* @g1() +; ATTRIBUTOR: ret i32* inttoptr (i64 4 to i32*) +define i32* @g1() { %c = call i32* @g2() ret i32* %c } diff --git a/llvm/test/Transforms/Attributor/range.ll b/llvm/test/Transforms/Attributor/range.ll index 5712c947ccf9..efdb8a5c0019 100644 --- a/llvm/test/Transforms/Attributor/range.ll +++ b/llvm/test/Transforms/Attributor/range.ll @@ -705,22 +705,6 @@ define internal i32 @r1(i32) local_unnamed_addr { ; OLD_PM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 100 ; OLD_PM-NEXT: br i1 [[TMP9]], label [[TMP1:%.*]], label [[TMP4]] ; -; NEW_PM-LABEL: define {{[^@]+}}@r1() local_unnamed_addr -; NEW_PM-NEXT: br label [[TMP3:%.*]] -; NEW_PM: 1: -; NEW_PM-NEXT: br label [[F:%.*]] -; NEW_PM: 2: -; NEW_PM-NEXT: unreachable -; NEW_PM: f: -; NEW_PM-NEXT: ret i32 10 -; NEW_PM: 3: -; NEW_PM-NEXT: [[TMP4:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[TMP3]] ] -; NEW_PM-NEXT: [[TMP5:%.*]] = phi i32 [ 0, [[TMP0]] ], [ [[TMP6:%.*]], [[TMP3]] ] -; NEW_PM-NEXT: [[TMP6]] = add nuw nsw i32 [[TMP4]], [[TMP5]] -; NEW_PM-NEXT: [[TMP7]] = add nuw nsw i32 [[TMP4]], 1 -; NEW_PM-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 100 -; NEW_PM-NEXT: br i1 [[TMP8]], label [[TMP1:%.*]], label [[TMP3]] -; ; CGSCC_OLD_PM-LABEL: define {{[^@]+}}@r1 ; CGSCC_OLD_PM-SAME: (i32 [[TMP0:%.*]]) local_unnamed_addr ; CGSCC_OLD_PM-NEXT: br label [[TMP5:%.*]] @@ -738,23 +722,6 @@ define internal i32 @r1(i32) local_unnamed_addr { ; CGSCC_OLD_PM-NEXT: [[TMP9]] = add nuw nsw i32 [[TMP6]], 1 ; CGSCC_OLD_PM-NEXT: [[TMP10:%.*]] = icmp eq i32 [[TMP9]], 100 ; CGSCC_OLD_PM-NEXT: br i1 [[TMP10]], label [[TMP2:%.*]], label [[TMP5]] -; -; CGSCC_NEW_PM-LABEL: define {{[^@]+}}@r1 -; CGSCC_NEW_PM-SAME: (i32 [[TMP0:%.*]]) local_unnamed_addr -; CGSCC_NEW_PM-NEXT: br label [[TMP4:%.*]] -; CGSCC_NEW_PM: 2: -; CGSCC_NEW_PM-NEXT: br label [[F:%.*]] -; CGSCC_NEW_PM: 3: -; CGSCC_NEW_PM-NEXT: unreachable -; CGSCC_NEW_PM: f: -; CGSCC_NEW_PM-NEXT: ret i32 10 -; CGSCC_NEW_PM: 4: -; CGSCC_NEW_PM-NEXT: [[TMP5:%.*]] = phi i32 [ 0, [[TMP1:%.*]] ], [ [[TMP8:%.*]], [[TMP4]] ] -; CGSCC_NEW_PM-NEXT: [[TMP6:%.*]] = phi i32 [ 0, [[TMP1]] ], [ [[TMP7:%.*]], [[TMP4]] ] -; CGSCC_NEW_PM-NEXT: [[TMP7]] = add nuw nsw i32 [[TMP5]], [[TMP6]] -; CGSCC_NEW_PM-NEXT: [[TMP8]] = add nuw nsw i32 [[TMP5]], 1 -; CGSCC_NEW_PM-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP8]], 100 -; CGSCC_NEW_PM-NEXT: br i1 [[TMP9]], label [[TMP2:%.*]], label [[TMP4]] ; br label %5 @@ -788,11 +755,10 @@ define void @f1(i32){ ; ; NEW_PM-LABEL: define {{[^@]+}}@f1 ; NEW_PM-SAME: (i32 [[TMP0:%.*]]) -; NEW_PM-NEXT: [[TMP2:%.*]] = tail call i32 @r1() -; NEW_PM-NEXT: br label [[TMP4:%.*]] -; NEW_PM: 3: +; NEW_PM-NEXT: br label [[TMP3:%.*]] +; NEW_PM: 2: ; NEW_PM-NEXT: unreachable -; NEW_PM: 4: +; NEW_PM: 3: ; NEW_PM-NEXT: ret void ; ; CGSCC_OLD_PM-LABEL: define {{[^@]+}}@f1 @@ -808,11 +774,10 @@ define void @f1(i32){ ; ; CGSCC_NEW_PM-LABEL: define {{[^@]+}}@f1 ; CGSCC_NEW_PM-SAME: (i32 [[TMP0:%.*]]) -; CGSCC_NEW_PM-NEXT: [[TMP2:%.*]] = tail call i32 @r1(i32 [[TMP0]]) -; CGSCC_NEW_PM-NEXT: br label [[TMP4:%.*]] -; CGSCC_NEW_PM: 3: +; CGSCC_NEW_PM-NEXT: br label [[TMP3:%.*]] +; CGSCC_NEW_PM: 2: ; CGSCC_NEW_PM-NEXT: unreachable -; CGSCC_NEW_PM: 4: +; CGSCC_NEW_PM: 3: ; CGSCC_NEW_PM-NEXT: ret void ; %2 = tail call i32 @r1(i32 %0) diff --git a/llvm/test/Transforms/Attributor/undefined_behavior.ll b/llvm/test/Transforms/Attributor/undefined_behavior.ll index 8e16a919f483..1d2f6fb430db 100644 --- a/llvm/test/Transforms/Attributor/undefined_behavior.ll +++ b/llvm/test/Transforms/Attributor/undefined_behavior.ll @@ -223,7 +223,6 @@ define i1 @ret_undef() { define void @cond_br_on_undef_interproc() { ; ATTRIBUTOR-LABEL: @cond_br_on_undef_interproc( -; ATTRIBUTOR-NEXT: %cond = call i1 @ret_undef() ; ATTRIBUTOR-NEXT: unreachable ; ATTRIBUTOR: t: ; ATTRIBUTOR-NEXT: unreachable @@ -249,7 +248,6 @@ e: ; More complicated interproc deduction of undef define void @cond_br_on_undef_interproc2() { ; ATTRIBUTOR-LABEL: @cond_br_on_undef_interproc2( -; ATTRIBUTOR-NEXT: %cond = call i1 @ret_undef2() ; ATTRIBUTOR-NEXT: unreachable ; ATTRIBUTOR: t: ; ATTRIBUTOR-NEXT: unreachable -- GitLab From f95553923f95f0c87b7ebbe5f8e41d313292dfda Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Fri, 10 Jan 2020 14:49:45 -0600 Subject: [PATCH 029/142] [Attributor] Return uses do not free pointers If a pointer is returned that does not mean it is freed in the current (function) scope. We can ignore such uses in AANoFree. --- llvm/lib/Transforms/IPO/Attributor.cpp | 2 ++ llvm/test/Transforms/Attributor/returned.ll | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index 52eafe5b8a4e..3aebc97a8635 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -1772,6 +1772,8 @@ struct AANoFreeFloating : AANoFreeImpl { Follow = true; return true; } + if (isa(UserI)) + return true; // Unknown user. return false; diff --git a/llvm/test/Transforms/Attributor/returned.ll b/llvm/test/Transforms/Attributor/returned.ll index 85ab69a0d99a..3efa581c9b77 100644 --- a/llvm/test/Transforms/Attributor/returned.ll +++ b/llvm/test/Transforms/Attributor/returned.ll @@ -334,8 +334,8 @@ if.end: ; BOTH: declare void @unknown_fn(i32* (i32*)*) ; ; BOTH: Function Attrs: noinline nounwind uwtable -; BOTH-NEXT: define i32* @calls_unknown_fn(i32* readnone returned "no-capture-maybe-returned" %r) -; ATTRIBUTOR: define i32* @calls_unknown_fn(i32* readnone returned "no-capture-maybe-returned" %r) +; BOTH-NEXT: define i32* @calls_unknown_fn(i32* nofree readnone returned "no-capture-maybe-returned" %r) +; ATTRIBUTOR: define i32* @calls_unknown_fn(i32* nofree readnone returned "no-capture-maybe-returned" %r) declare void @unknown_fn(i32* (i32*)*) #0 define i32* @calls_unknown_fn(i32* %r) #0 { -- GitLab From b0279d62ac68837bc58393a81518a2c5b4ca6163 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 11 Feb 2020 11:06:04 -0600 Subject: [PATCH 030/142] [CodingStandards] Add link to "Picking the Right Data Structure" See https://reviews.llvm.org/D74340 --- llvm/docs/CodingStandards.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/llvm/docs/CodingStandards.rst b/llvm/docs/CodingStandards.rst index 4cf6c726c535..2ade20b01c1d 100644 --- a/llvm/docs/CodingStandards.rst +++ b/llvm/docs/CodingStandards.rst @@ -92,6 +92,10 @@ We explicitly avoid some standard facilities, like the I/O streams, and instead use LLVM's streams library (raw_ostream_). More detailed information on these subjects is available in the :doc:`ProgrammersManual`. +For more information about LLVM's data structures and the tradeoffs they make, +please consult [that section of the programmer's +manual](https://llvm.org/docs/ProgrammersManual.html#picking-the-right-data-structure-for-a-task). + Guidelines for Go code ---------------------- -- GitLab From 185e9b083eba20e612642a5a81816d492bb9dfba Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 11 Feb 2020 11:19:34 -0600 Subject: [PATCH 031/142] [Attributor][NFC] Improve documentation --- llvm/lib/Transforms/IPO/Attributor.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index 3aebc97a8635..4c0185de3f04 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -374,7 +374,8 @@ static Value *constructPointer(Type *ResTy, Value *Ptr, int64_t Offset, /// will be done by looking through cast instructions, selects, phis, and calls /// with the "returned" attribute. Once we cannot look through the value any /// further, the callback \p VisitValueCB is invoked and passed the current -/// value, the \p State, and a flag to indicate if we stripped anything. To +/// value, the \p State, and a flag to indicate if we stripped anything (=the +/// value used for the callback is not the value associated with \p IRP). To /// limit how much effort is invested, we will never visit more values than /// specified by \p MaxValues. template -- GitLab From 2ac0c4b46ee2a3c22b85b4483f2fd4d0fb916720 Mon Sep 17 00:00:00 2001 From: Ben Langmuir Date: Mon, 10 Feb 2020 17:22:52 -0800 Subject: [PATCH 032/142] [DirectoryWatcher] Fix misuse of FSEvents API and data race I observed two bugs in the DirectoryWatcher on macOS 1. We were calling FSEventStreamStop and FSEventStreamInvalidate before we called FSEventStreamStart and FSEventStreamSetDispatchQueue, if the DirectoryWatcher was destroyed before the initial async work was done. This violates the requirements of the FSEvents API. 2. Calls to Receiver could race between the initial work and the invalidation during destruction. The second issue is easier to see when using TSan. Differential Revision: https://reviews.llvm.org/D74371 rdar://59215667 --- .../mac/DirectoryWatcher-mac.cpp | 32 ++++++++------- .../DirectoryWatcher/DirectoryWatcherTest.cpp | 39 +++++++++++++++++++ 2 files changed, 57 insertions(+), 14 deletions(-) diff --git a/clang/lib/DirectoryWatcher/mac/DirectoryWatcher-mac.cpp b/clang/lib/DirectoryWatcher/mac/DirectoryWatcher-mac.cpp index 2cae847e7657..7864fb76d160 100644 --- a/clang/lib/DirectoryWatcher/mac/DirectoryWatcher-mac.cpp +++ b/clang/lib/DirectoryWatcher/mac/DirectoryWatcher-mac.cpp @@ -43,24 +43,32 @@ namespace { class DirectoryWatcherMac : public clang::DirectoryWatcher { public: DirectoryWatcherMac( - FSEventStreamRef EventStream, + dispatch_queue_t Queue, FSEventStreamRef EventStream, std::function, bool)> Receiver, llvm::StringRef WatchedDirPath) - : EventStream(EventStream), Receiver(Receiver), + : Queue(Queue), EventStream(EventStream), Receiver(Receiver), WatchedDirPath(WatchedDirPath) {} ~DirectoryWatcherMac() override { - stopFSEventStream(EventStream); - EventStream = nullptr; - // Now it's safe to use Receiver as the only other concurrent use would have - // been in EventStream processing. - Receiver(DirectoryWatcher::Event( - DirectoryWatcher::Event::EventKind::WatcherGotInvalidated, ""), - false); + // FSEventStreamStop and Invalidate must be called after Start and + // SetDispatchQueue to follow FSEvents API contract. The call to Receiver + // also uses Queue to not race with the initial scan. + dispatch_sync(Queue, ^{ + stopFSEventStream(EventStream); + EventStream = nullptr; + Receiver( + DirectoryWatcher::Event( + DirectoryWatcher::Event::EventKind::WatcherGotInvalidated, ""), + false); + }); + + // Balance initial creation. + dispatch_release(Queue); } private: + dispatch_queue_t Queue; FSEventStreamRef EventStream; std::function, bool)> Receiver; const std::string WatchedDirPath; @@ -217,7 +225,7 @@ llvm::Expected> clang::DirectoryWatcher::creat assert(EventStream && "EventStream expected to be non-null"); std::unique_ptr Result = - std::make_unique(EventStream, Receiver, Path); + std::make_unique(Queue, EventStream, Receiver, Path); // We need to copy the data so the lifetime is ok after a const copy is made // for the block. @@ -230,10 +238,6 @@ llvm::Expected> clang::DirectoryWatcher::creat // inital scan and handling events ONLY AFTER the scan finishes. FSEventStreamSetDispatchQueue(EventStream, Queue); FSEventStreamStart(EventStream); - // We need to decrement the ref count for Queue as initialize() will return - // and FSEvents has incremented it. Since we have to wait for FSEvents to - // take ownership it's the easiest to do it here rather than main thread. - dispatch_release(Queue); Receiver(getAsFileEvents(scanDirectory(CopiedPath)), /*IsInitial=*/true); }; diff --git a/clang/unittests/DirectoryWatcher/DirectoryWatcherTest.cpp b/clang/unittests/DirectoryWatcher/DirectoryWatcherTest.cpp index 510ade453b0a..650c0fc49764 100644 --- a/clang/unittests/DirectoryWatcher/DirectoryWatcherTest.cpp +++ b/clang/unittests/DirectoryWatcher/DirectoryWatcherTest.cpp @@ -449,3 +449,42 @@ TEST(DirectoryWatcherTest, InvalidatedWatcher) { checkEventualResultWithTimeout(TestConsumer); } + +TEST(DirectoryWatcherTest, InvalidatedWatcherAsync) { + DirectoryWatcherTestFixture fixture; + fixture.addFile("a"); + + // This test is checking that we get the initial notification for 'a' before + // the final 'invalidated'. Strictly speaking, we do not care whether 'a' is + // processed or not, only that it is neither racing with, nor after + // 'invalidated'. In practice, it is always processed in our implementations. + VerifyingConsumer TestConsumer{ + {{EventKind::Modified, "a"}}, + {{EventKind::WatcherGotInvalidated, ""}}, + // We have to ignore these as it's a race between the test process + // which is scanning the directory and kernel which is sending + // notification. + {{EventKind::Modified, "a"}}, + }; + + // A counter that can help detect data races on the event receiver, + // particularly if used with TSan. Expected count will be 2 or 3 depending on + // whether we get the kernel event or not (see comment above). + unsigned Count = 0; + { + llvm::Expected> DW = + DirectoryWatcher::create( + fixture.TestWatchedDir, + [&TestConsumer, + &Count](llvm::ArrayRef Events, + bool IsInitial) { + Count += 1; + TestConsumer.consume(Events, IsInitial); + }, + /*waitForInitialSync=*/false); + ASSERT_THAT_ERROR(DW.takeError(), Succeeded()); + } // DW is destructed here. + + checkEventualResultWithTimeout(TestConsumer); + ASSERT_TRUE(Count == 2u || Count == 3u); +} -- GitLab From 62174682a039efce2ce7606d5416d2450ff42dab Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Tue, 11 Feb 2020 18:44:02 +0100 Subject: [PATCH 033/142] [lldb][NFC] Remove support file searching from SourceFileCompleter This code seems wrong as the directory variable actually contains the file name. It's also unreachable code as m_include_support_files is hardcoded to false which is the condition for the surrounding 'if statement'. Let's just remove all of this. --- .../lldb/Interpreter/CommandCompletions.h | 3 +- lldb/source/Commands/CommandCompletions.cpp | 62 ++++++------------- 2 files changed, 20 insertions(+), 45 deletions(-) diff --git a/lldb/include/lldb/Interpreter/CommandCompletions.h b/lldb/include/lldb/Interpreter/CommandCompletions.h index 275cc7e7c145..39061d9db8bc 100644 --- a/lldb/include/lldb/Interpreter/CommandCompletions.h +++ b/lldb/include/lldb/Interpreter/CommandCompletions.h @@ -121,7 +121,7 @@ public: class SourceFileCompleter : public Completer { public: SourceFileCompleter(CommandInterpreter &interpreter, - bool include_support_files, CompletionRequest &request); + CompletionRequest &request); lldb::SearchDepth GetDepth() override; @@ -132,7 +132,6 @@ public: void DoCompletion(SearchFilter *filter) override; private: - bool m_include_support_files; FileSpecList m_matching_files; const char *m_file_name; const char *m_dir_name; diff --git a/lldb/source/Commands/CommandCompletions.cpp b/lldb/source/Commands/CommandCompletions.cpp index e5f29115a8a7..2ced56f90178 100644 --- a/lldb/source/Commands/CommandCompletions.cpp +++ b/lldb/source/Commands/CommandCompletions.cpp @@ -66,8 +66,7 @@ bool CommandCompletions::InvokeCommonCompletionCallbacks( void CommandCompletions::SourceFiles(CommandInterpreter &interpreter, CompletionRequest &request, SearchFilter *searcher) { - // Find some way to switch "include support files..." - SourceFileCompleter completer(interpreter, false, request); + SourceFileCompleter completer(interpreter, request); if (searcher == nullptr) { lldb::TargetSP target_sp = interpreter.GetDebugger().GetSelectedTarget(); @@ -332,10 +331,8 @@ CommandCompletions::Completer::~Completer() = default; // SourceFileCompleter CommandCompletions::SourceFileCompleter::SourceFileCompleter( - CommandInterpreter &interpreter, bool include_support_files, - CompletionRequest &request) - : CommandCompletions::Completer(interpreter, request), - m_include_support_files(include_support_files), m_matching_files() { + CommandInterpreter &interpreter, CompletionRequest &request) + : CommandCompletions::Completer(interpreter, request), m_matching_files() { FileSpec partial_spec(m_request.GetCursorArgumentPrefix()); m_file_name = partial_spec.GetFilename().GetCString(); m_dir_name = partial_spec.GetDirectory().GetCString(); @@ -350,43 +347,22 @@ CommandCompletions::SourceFileCompleter::SearchCallback(SearchFilter &filter, SymbolContext &context, Address *addr) { if (context.comp_unit != nullptr) { - if (m_include_support_files) { - FileSpecList supporting_files = context.comp_unit->GetSupportFiles(); - for (size_t sfiles = 0; sfiles < supporting_files.GetSize(); sfiles++) { - const FileSpec &sfile_spec = - supporting_files.GetFileSpecAtIndex(sfiles); - const char *sfile_file_name = sfile_spec.GetFilename().GetCString(); - const char *sfile_dir_name = sfile_spec.GetFilename().GetCString(); - bool match = false; - if (m_file_name && sfile_file_name && - strstr(sfile_file_name, m_file_name) == sfile_file_name) - match = true; - if (match && m_dir_name && sfile_dir_name && - strstr(sfile_dir_name, m_dir_name) != sfile_dir_name) - match = false; - - if (match) { - m_matching_files.AppendIfUnique(sfile_spec); - } - } - } else { - const char *cur_file_name = - context.comp_unit->GetPrimaryFile().GetFilename().GetCString(); - const char *cur_dir_name = - context.comp_unit->GetPrimaryFile().GetDirectory().GetCString(); - - bool match = false; - if (m_file_name && cur_file_name && - strstr(cur_file_name, m_file_name) == cur_file_name) - match = true; - - if (match && m_dir_name && cur_dir_name && - strstr(cur_dir_name, m_dir_name) != cur_dir_name) - match = false; - - if (match) { - m_matching_files.AppendIfUnique(context.comp_unit->GetPrimaryFile()); - } + const char *cur_file_name = + context.comp_unit->GetPrimaryFile().GetFilename().GetCString(); + const char *cur_dir_name = + context.comp_unit->GetPrimaryFile().GetDirectory().GetCString(); + + bool match = false; + if (m_file_name && cur_file_name && + strstr(cur_file_name, m_file_name) == cur_file_name) + match = true; + + if (match && m_dir_name && cur_dir_name && + strstr(cur_dir_name, m_dir_name) != cur_dir_name) + match = false; + + if (match) { + m_matching_files.AppendIfUnique(context.comp_unit->GetPrimaryFile()); } } return Searcher::eCallbackReturnContinue; -- GitLab From 29bc5dd19407c4d7cad1c059dea26ee216ddc7ca Mon Sep 17 00:00:00 2001 From: Yonghong Song Date: Wed, 5 Feb 2020 10:27:43 -0800 Subject: [PATCH 034/142] [BPF] implement isTruncateFree and isZExtFree in BPFTargetLowering Currently, isTruncateFree() and isZExtFree() callbacks return false as they are not implemented in BPF backend. This may cause suboptimal code generation. For example, if the load in the context of zero extension has more than one use, the pattern zextload{i8,i16,i32} will not be generated. Rather, the load will be matched first and then the result is zero extended. For example, in the test together with this commit, we have I1: %0 = load i32, i32* %data_end1, align 4, !tbaa !2 I2: %conv = zext i32 %0 to i64 ... I3: %2 = load i32, i32* %data, align 4, !tbaa !7 I4: %conv2 = zext i32 %2 to i64 ... I5: %4 = trunc i64 %sub.ptr.lhs.cast to i32 I6: %conv13 = sub i32 %4, %2 ... The I1 and I2 will match to one zextloadi32 DAG node, where SUBREG_TO_REG is used to convert a 32bit register to 64bit one. During code generation, SUBREG_TO_REG is a noop. The %2 in I3 is used in both I4 and I6. If isTruncateFree() is false, the current implementation will generate a SLL_ri and SRL_ri for the zext part during lowering. This patch implement isTruncateFree() in the BPF backend, so for the above example, I3 and I4 will generate a zextloadi32 DAG node with SUBREG_TO_REG is generated during lowering to Machine IR. isZExtFree() is also implemented as it should help code gen as well. This patch also enables the change in https://reviews.llvm.org/D73985 since it won't kick in generates MOV_32_64 machine instruction. Differential Revision: https://reviews.llvm.org/D74101 --- llvm/lib/Target/BPF/BPFISelLowering.cpp | 32 ++++++++ llvm/lib/Target/BPF/BPFISelLowering.h | 10 +++ .../BPF/CORE/offset-reloc-fieldinfo-1.ll | 10 ++- .../BPF/CORE/offset-reloc-fieldinfo-2.ll | 23 +++--- llvm/test/CodeGen/BPF/is_trunc_free.ll | 80 +++++++++++++++++++ llvm/test/CodeGen/BPF/is_zext_free.ll | 26 ++++++ 6 files changed, 168 insertions(+), 13 deletions(-) create mode 100644 llvm/test/CodeGen/BPF/is_trunc_free.ll create mode 100644 llvm/test/CodeGen/BPF/is_zext_free.ll diff --git a/llvm/lib/Target/BPF/BPFISelLowering.cpp b/llvm/lib/Target/BPF/BPFISelLowering.cpp index 56e0288f26c9..799a60c6cc92 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.cpp +++ b/llvm/lib/Target/BPF/BPFISelLowering.cpp @@ -171,6 +171,38 @@ bool BPFTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) cons return false; } +bool BPFTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { + if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) + return false; + unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); + unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); + return NumBits1 > NumBits2; +} + +bool BPFTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { + if (!VT1.isInteger() || !VT2.isInteger()) + return false; + unsigned NumBits1 = VT1.getSizeInBits(); + unsigned NumBits2 = VT2.getSizeInBits(); + return NumBits1 > NumBits2; +} + +bool BPFTargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { + if (!getHasAlu32() || !Ty1->isIntegerTy() || !Ty2->isIntegerTy()) + return false; + unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); + unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); + return NumBits1 == 32 && NumBits2 == 64; +} + +bool BPFTargetLowering::isZExtFree(EVT VT1, EVT VT2) const { + if (!getHasAlu32() || !VT1.isInteger() || !VT2.isInteger()) + return false; + unsigned NumBits1 = VT1.getSizeInBits(); + unsigned NumBits2 = VT2.getSizeInBits(); + return NumBits1 == 32 && NumBits2 == 64; +} + std::pair BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, diff --git a/llvm/lib/Target/BPF/BPFISelLowering.h b/llvm/lib/Target/BPF/BPFISelLowering.h index 0e9ec1398aeb..cc752dda87b0 100644 --- a/llvm/lib/Target/BPF/BPFISelLowering.h +++ b/llvm/lib/Target/BPF/BPFISelLowering.h @@ -122,6 +122,16 @@ private: return false; } + // isTruncateFree - Return true if it's free to truncate a value of + // type Ty1 to type Ty2. e.g. On BPF at alu32 mode, it's free to truncate + // a i64 value in register R1 to i32 by referencing its sub-register W1. + bool isTruncateFree(Type *Ty1, Type *Ty2) const override; + bool isTruncateFree(EVT VT1, EVT VT2) const override; + + // For 32bit ALU result zext to 64bit is free. + bool isZExtFree(Type *Ty1, Type *Ty2) const override; + bool isZExtFree(EVT VT1, EVT VT2) const override; + unsigned EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, unsigned Reg, bool isSigned) const; diff --git a/llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll b/llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll index d7e48d390416..d871cb35311b 100644 --- a/llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll +++ b/llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-1.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s -; RUN: llc -march=bpfel -mattr=+alu32 -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK %s +; RUN: llc -march=bpfel -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK64 %s +; RUN: llc -march=bpfel -mattr=+alu32 -filetype=asm -o - %s | FileCheck -check-prefixes=CHECK,CHECK32 %s ; Source code: ; struct s { ; int a; @@ -74,8 +74,10 @@ entry: ; CHECK: r{{[0-9]+}} = 4 ; CHECK: r{{[0-9]+}} = 4 ; CHECK: r{{[0-9]+}} <<= 51 -; CHECK: r{{[0-9]+}} s>>= 60 -; CHECK: r{{[0-9]+}} >>= 60 +; CHECK64: r{{[0-9]+}} s>>= 60 +; CHECK64: r{{[0-9]+}} >>= 60 +; CHECK32: r{{[0-9]+}} >>= 60 +; CHECK32: r{{[0-9]+}} s>>= 60 ; CHECK: r{{[0-9]+}} = 1 ; CHECK: .byte 115 # string offset=1 diff --git a/llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll b/llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll index 01af9d8a697b..45d5ae1e1f30 100644 --- a/llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll +++ b/llvm/test/CodeGen/BPF/CORE/offset-reloc-fieldinfo-2.ll @@ -116,8 +116,10 @@ sw.epilog: ; preds = %entry, %sw.bb9, %sw ; CHECK: r{{[0-9]+}} = 4 ; CHECK-EL: r{{[0-9]+}} <<= 51 ; CHECK-EB: r{{[0-9]+}} <<= 41 -; CHECK: r{{[0-9]+}} s>>= 60 -; CHECK: r{{[0-9]+}} >>= 60 +; CHECK64: r{{[0-9]+}} s>>= 60 +; CHECK64: r{{[0-9]+}} >>= 60 +; CHECK32: r{{[0-9]+}} >>= 60 +; CHECK32: r{{[0-9]+}} s>>= 60 ; CHECK: r{{[0-9]+}} = 1 ; CHECK: .long 1 # BTF_KIND_STRUCT(id = 2) @@ -127,8 +129,11 @@ sw.epilog: ; preds = %entry, %sw.bb9, %sw ; CHECK: .long 16 # FieldReloc ; CHECK-NEXT: .long 30 # Field reloc section string offset=30 -; CHECK32: .long 6 -; CHECK64: .long 7 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .long .Ltmp{{[0-9]+}} +; CHECK-NEXT: .long 2 +; CHECK-NEXT: .long 36 +; CHECK-NEXT: .long 1 ; CHECK-NEXT: .long .Ltmp{{[0-9]+}} ; CHECK-NEXT: .long 2 ; CHECK-NEXT: .long 36 @@ -136,11 +141,11 @@ sw.epilog: ; preds = %entry, %sw.bb9, %sw ; CHECK-NEXT: .long .Ltmp{{[0-9]+}} ; CHECK-NEXT: .long 2 ; CHECK-NEXT: .long 36 -; CHECK-NEXT: .long 1 -; CHECK64: .long .Ltmp{{[0-9]+}} -; CHECK64: .long 2 -; CHECK64: .long 36 -; CHECK64: .long 0 +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .long .Ltmp{{[0-9]+}} +; CHECK-NEXT: .long 2 +; CHECK-NEXT: .long 36 +; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long .Ltmp{{[0-9]+}} ; CHECK-NEXT: .long 2 ; CHECK-NEXT: .long 36 diff --git a/llvm/test/CodeGen/BPF/is_trunc_free.ll b/llvm/test/CodeGen/BPF/is_trunc_free.ll new file mode 100644 index 000000000000..cc6bef1a92a9 --- /dev/null +++ b/llvm/test/CodeGen/BPF/is_trunc_free.ll @@ -0,0 +1,80 @@ +; RUN: llc -march=bpfel -mattr=+alu32 < %s | FileCheck %s +; Source: +; struct env_t { +; unsigned data; +; unsigned data_end; +; }; +; extern int work(struct env_t *skb, unsigned offset); +; int test(struct env_t *skb) +; { +; void *cursor, *data_end; +; struct env_t *srh, *ip; +; +; data_end = (void *)(long)skb->data_end; +; cursor = (void *)(long)skb->data; +; +; ip = cursor; cursor += sizeof(*ip); +; if ((void *)ip + sizeof(*ip) > data_end) +; return 0; +; +; srh = cursor; cursor += sizeof(*srh); +; if ((void *)srh + sizeof(*srh) > data_end) +; return 0; +; +; return work(skb, (char *)srh - (char *)(long)skb->data); +; } +; Compilation flag: +; clang -target bpf -O2 -emit-llvm -S test.c + +%struct.env_t = type { i32, i32 } + +; Function Attrs: nounwind +define dso_local i32 @test(%struct.env_t* %skb) local_unnamed_addr #0 { +entry: + %data_end1 = getelementptr inbounds %struct.env_t, %struct.env_t* %skb, i64 0, i32 1 + %0 = load i32, i32* %data_end1, align 4, !tbaa !2 + %conv = zext i32 %0 to i64 + %1 = inttoptr i64 %conv to i8* + %data = getelementptr inbounds %struct.env_t, %struct.env_t* %skb, i64 0, i32 0 + %2 = load i32, i32* %data, align 4, !tbaa !7 + %conv2 = zext i32 %2 to i64 + %3 = inttoptr i64 %conv2 to i8* + %add.ptr = getelementptr i8, i8* %3, i64 8 + %cmp = icmp ugt i8* %add.ptr, %1 + %add.ptr6 = getelementptr i8, i8* %3, i64 16 + %cmp7 = icmp ugt i8* %add.ptr6, %1 + %or.cond = or i1 %cmp, %cmp7 + br i1 %or.cond, label %cleanup, label %if.end10 + +if.end10: ; preds = %entry + %sub.ptr.lhs.cast = ptrtoint i8* %add.ptr to i64 + %4 = trunc i64 %sub.ptr.lhs.cast to i32 + %conv13 = sub i32 %4, %2 + %call = tail call i32 @work(%struct.env_t* nonnull %skb, i32 %conv13) #2 + br label %cleanup + +cleanup: ; preds = %entry, %if.end10 + %retval.0 = phi i32 [ %call, %if.end10 ], [ 0, %entry ] + ret i32 %retval.0 +} + +; CHECK: w{{[0-9]+}} = *(u32 *)(r{{[0-9]+}} + 0) +; CHECK-NOT: w{{[0-9]+}} = w{{[0-9]+}} + +declare dso_local i32 @work(%struct.env_t*, i32) local_unnamed_addr #1 + +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang version 11.0.0 (https://github.com/llvm/llvm-project.git 016d3ce1f4b07ee3056f7c10fedb24c441c4870f)"} +!2 = !{!3, !4, i64 4} +!3 = !{!"env_t", !4, i64 0, !4, i64 4} +!4 = !{!"int", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!3, !4, i64 0} diff --git a/llvm/test/CodeGen/BPF/is_zext_free.ll b/llvm/test/CodeGen/BPF/is_zext_free.ll new file mode 100644 index 000000000000..2a62dbefd62d --- /dev/null +++ b/llvm/test/CodeGen/BPF/is_zext_free.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=bpfel -mattr=+alu32 < %s | FileCheck %s +; Source: +; unsigned test(unsigned long x, unsigned long y) { +; return x & y; +; } +; Compilation flag: +; clang -target bpf -O2 -emit-llvm -S test.c + +; Function Attrs: norecurse nounwind readnone +define dso_local i32 @test(i64 %x, i64 %y) local_unnamed_addr #0 { +entry: + %and = and i64 %y, %x + %conv = trunc i64 %and to i32 + ret i32 %conv +} + +; CHECK: r[[REG1:[0-9]+]] = r{{[0-9]+}} +; CHECK: w[[REG1]] &= w{{[0-9]+}} + +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang version 11.0.0 (https://github.com/llvm/llvm-project.git b3ab5b2e7ffe9964ddf75a92fd7a444fe5aaa426)"} -- GitLab From 99451b4453688a94c6014cac233d371ab4cc342d Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Tue, 11 Feb 2020 10:01:16 -0800 Subject: [PATCH 035/142] [lldb][test] Remove symlink for API tests. Summary: Moves lldbsuite tests to lldb/test/API. This is a largely mechanical change, moved with the following steps: ``` rm lldb/test/API/testcases mkdir -p lldb/test/API/{test_runner/test,tools/lldb-{server,vscode}} mv lldb/packages/Python/lldbsuite/test/test_runner/test lldb/test/API/test_runner for d in $(find lldb/packages/Python/lldbsuite/test/* -maxdepth 0 -type d | egrep -v "make|plugins|test_runner|tools"); do mv $d lldb/test/API; done for d in $(find lldb/packages/Python/lldbsuite/test/tools/lldb-vscode -maxdepth 1 -mindepth 1 | grep -v ".py"); do mv $d lldb/test/API/tools/lldb-vscode; done for d in $(find lldb/packages/Python/lldbsuite/test/tools/lldb-server -maxdepth 1 -mindepth 1 | egrep -v "gdbremote_testcase.py|lldbgdbserverutils.py|socket_packet_pump.py"); do mv $d lldb/test/API/tools/lldb-server; done ``` lldb/packages/Python/lldbsuite/__init__.py and lldb/test/API/lit.cfg.py were also updated with the new directory structure. Reviewers: labath, JDevlieghere Tags: #lldb Differential Revision: https://reviews.llvm.org/D71151 --- lldb/packages/Python/lldbsuite/__init__.py | 9 +-------- .../test => test/API}/android/platform/Makefile | 0 .../android/platform/TestDefaultCacheLineSize.py | 0 .../test => test/API}/android/platform/main.cpp | 0 .../API}/api/check_public_api_headers/Makefile | 0 .../TestPublicAPIHeaders.py | 0 .../api/check_public_api_headers/main.cpp.template | 0 .../API}/api/command-return-object/Makefile | 0 .../TestSBCommandReturnObject.py | 0 .../API}/api/command-return-object/main.cpp | 0 .../test => test/API}/api/listeners/Makefile | 0 .../test => test/API}/api/listeners/TestListener.py | 0 .../test => test/API}/api/listeners/main.c | 0 .../test => test/API}/api/log/TestAPILog.py | 0 .../API}/api/multiple-debuggers/.categories | 0 .../API}/api/multiple-debuggers/Makefile | 0 .../api/multiple-debuggers/TestMultipleDebuggers.py | 0 .../api/multiple-debuggers/multi-process-driver.cpp | 0 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test/API}/types/TestLongTypes.py | 0 .../test => test/API}/types/TestLongTypesExpr.py | 0 .../test => test/API}/types/TestRecursiveTypes.py | 0 .../test => test/API}/types/TestShortType.py | 0 .../test => test/API}/types/TestShortTypeExpr.py | 0 .../test => test/API}/types/basic_type.cpp | 0 .../lldbsuite/test => test/API}/types/char.cpp | 0 .../lldbsuite/test => test/API}/types/double.cpp | 0 .../lldbsuite/test => test/API}/types/float.cpp | 0 .../lldbsuite/test => test/API}/types/int.cpp | 0 .../lldbsuite/test => test/API}/types/long.cpp | 0 .../lldbsuite/test => test/API}/types/long_long.cpp | 0 .../test => test/API}/types/recursive_type_1.cpp | 0 .../test => test/API}/types/recursive_type_2.cpp | 0 .../test => test/API}/types/recursive_type_main.cpp | 0 .../lldbsuite/test => test/API}/types/short.cpp | 0 .../test => test/API}/types/unsigned_char.cpp | 0 .../test => test/API}/types/unsigned_int.cpp | 0 .../test => test/API}/types/unsigned_long.cpp | 0 .../test => test/API}/types/unsigned_long_long.cpp | 0 .../test => test/API}/types/unsigned_short.cpp | 0 2609 files changed, 2 insertions(+), 11 deletions(-) rename lldb/{packages/Python/lldbsuite/test => test/API}/android/platform/Makefile (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/android/platform/TestDefaultCacheLineSize.py (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/android/platform/main.cpp (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/api/check_public_api_headers/Makefile (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/api/check_public_api_headers/TestPublicAPIHeaders.py (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/api/check_public_api_headers/main.cpp.template (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/api/command-return-object/Makefile (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/api/command-return-object/TestSBCommandReturnObject.py (100%) rename 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(100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/types/unsigned_long.cpp (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/types/unsigned_long_long.cpp (100%) rename lldb/{packages/Python/lldbsuite/test => test/API}/types/unsigned_short.cpp (100%) diff --git a/lldb/packages/Python/lldbsuite/__init__.py b/lldb/packages/Python/lldbsuite/__init__.py index 9efa05c7f454..195b2683f7b4 100644 --- a/lldb/packages/Python/lldbsuite/__init__.py +++ b/lldb/packages/Python/lldbsuite/__init__.py @@ -22,11 +22,4 @@ lldb_root = find_lldb_root() # lldbsuite.lldb_test_src_root refers to the root of the python test case tree # (i.e. the actual unit tests). -lldb_test_root = os.path.join( - lldb_root, - "packages", - "Python", - "lldbsuite", - "test") -# TODO(rupprecht): update the above definition after moving test cases: -# lldb_test_root = os.path.join(lldb_root, "test", "API") +lldb_test_root = os.path.join(lldb_root, "test", "API") diff --git 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a/lldb/packages/Python/lldbsuite/test/api/multiple-debuggers/multi-process-driver.cpp b/lldb/test/API/api/multiple-debuggers/multi-process-driver.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/api/multiple-debuggers/multi-process-driver.cpp rename to lldb/test/API/api/multiple-debuggers/multi-process-driver.cpp diff --git a/lldb/packages/Python/lldbsuite/test/api/multiple-debuggers/testprog.cpp b/lldb/test/API/api/multiple-debuggers/testprog.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/api/multiple-debuggers/testprog.cpp rename to lldb/test/API/api/multiple-debuggers/testprog.cpp diff --git a/lldb/packages/Python/lldbsuite/test/api/multiple-targets/Makefile b/lldb/test/API/api/multiple-targets/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/api/multiple-targets/Makefile rename to lldb/test/API/api/multiple-targets/Makefile diff --git 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a/lldb/packages/Python/lldbsuite/test/commands/expression/context-object-objc/Makefile b/lldb/test/API/commands/expression/context-object-objc/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/expression/context-object-objc/Makefile rename to lldb/test/API/commands/expression/context-object-objc/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/expression/context-object-objc/TestContextObjectObjc.py b/lldb/test/API/commands/expression/context-object-objc/TestContextObjectObjc.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/expression/context-object-objc/TestContextObjectObjc.py rename to lldb/test/API/commands/expression/context-object-objc/TestContextObjectObjc.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/expression/context-object-objc/main.m b/lldb/test/API/commands/expression/context-object-objc/main.m similarity index 100% rename from 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b/lldb/test/API/commands/expression/context-object/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/expression/context-object/main.cpp rename to lldb/test/API/commands/expression/context-object/main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/commands/expression/deleting-implicit-copy-constructor/TestDeletingImplicitCopyConstructor.py b/lldb/test/API/commands/expression/deleting-implicit-copy-constructor/TestDeletingImplicitCopyConstructor.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/expression/deleting-implicit-copy-constructor/TestDeletingImplicitCopyConstructor.py rename to lldb/test/API/commands/expression/deleting-implicit-copy-constructor/TestDeletingImplicitCopyConstructor.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/expression/deleting-implicit-copy-constructor/main.cpp b/lldb/test/API/commands/expression/deleting-implicit-copy-constructor/main.cpp similarity index 100% rename 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a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/bad-reference/Makefile b/lldb/test/API/commands/frame/diagnose/bad-reference/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/bad-reference/Makefile rename to lldb/test/API/commands/frame/diagnose/bad-reference/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/bad-reference/TestBadReference.py b/lldb/test/API/commands/frame/diagnose/bad-reference/TestBadReference.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/bad-reference/TestBadReference.py rename to lldb/test/API/commands/frame/diagnose/bad-reference/TestBadReference.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/bad-reference/main.cpp b/lldb/test/API/commands/frame/diagnose/bad-reference/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/bad-reference/main.cpp rename to lldb/test/API/commands/frame/diagnose/bad-reference/main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/complicated-expression/Makefile b/lldb/test/API/commands/frame/diagnose/complicated-expression/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/complicated-expression/Makefile rename to lldb/test/API/commands/frame/diagnose/complicated-expression/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/complicated-expression/TestComplicatedExpression.py b/lldb/test/API/commands/frame/diagnose/complicated-expression/TestComplicatedExpression.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/complicated-expression/TestComplicatedExpression.py rename to lldb/test/API/commands/frame/diagnose/complicated-expression/TestComplicatedExpression.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/complicated-expression/main.c b/lldb/test/API/commands/frame/diagnose/complicated-expression/main.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/complicated-expression/main.c rename to lldb/test/API/commands/frame/diagnose/complicated-expression/main.c diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-argument/Makefile b/lldb/test/API/commands/frame/diagnose/dereference-argument/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-argument/Makefile rename to lldb/test/API/commands/frame/diagnose/dereference-argument/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-argument/TestDiagnoseDereferenceArgument.py b/lldb/test/API/commands/frame/diagnose/dereference-argument/TestDiagnoseDereferenceArgument.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-argument/TestDiagnoseDereferenceArgument.py rename to lldb/test/API/commands/frame/diagnose/dereference-argument/TestDiagnoseDereferenceArgument.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-argument/main.c b/lldb/test/API/commands/frame/diagnose/dereference-argument/main.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-argument/main.c rename to lldb/test/API/commands/frame/diagnose/dereference-argument/main.c diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-function-return/Makefile b/lldb/test/API/commands/frame/diagnose/dereference-function-return/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-function-return/Makefile rename to lldb/test/API/commands/frame/diagnose/dereference-function-return/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-function-return/TestDiagnoseDereferenceFunctionReturn.py b/lldb/test/API/commands/frame/diagnose/dereference-function-return/TestDiagnoseDereferenceFunctionReturn.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-function-return/TestDiagnoseDereferenceFunctionReturn.py rename to lldb/test/API/commands/frame/diagnose/dereference-function-return/TestDiagnoseDereferenceFunctionReturn.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-function-return/main.c b/lldb/test/API/commands/frame/diagnose/dereference-function-return/main.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-function-return/main.c rename to lldb/test/API/commands/frame/diagnose/dereference-function-return/main.c diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-this/Makefile b/lldb/test/API/commands/frame/diagnose/dereference-this/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-this/Makefile rename to lldb/test/API/commands/frame/diagnose/dereference-this/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-this/TestDiagnoseDereferenceThis.py b/lldb/test/API/commands/frame/diagnose/dereference-this/TestDiagnoseDereferenceThis.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-this/TestDiagnoseDereferenceThis.py rename to lldb/test/API/commands/frame/diagnose/dereference-this/TestDiagnoseDereferenceThis.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-this/main.cpp b/lldb/test/API/commands/frame/diagnose/dereference-this/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/dereference-this/main.cpp rename to lldb/test/API/commands/frame/diagnose/dereference-this/main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/inheritance/Makefile b/lldb/test/API/commands/frame/diagnose/inheritance/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/inheritance/Makefile rename to lldb/test/API/commands/frame/diagnose/inheritance/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/inheritance/TestDiagnoseInheritance.py b/lldb/test/API/commands/frame/diagnose/inheritance/TestDiagnoseInheritance.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/inheritance/TestDiagnoseInheritance.py rename to lldb/test/API/commands/frame/diagnose/inheritance/TestDiagnoseInheritance.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/inheritance/main.cpp b/lldb/test/API/commands/frame/diagnose/inheritance/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/inheritance/main.cpp rename to lldb/test/API/commands/frame/diagnose/inheritance/main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/local-variable/Makefile b/lldb/test/API/commands/frame/diagnose/local-variable/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/local-variable/Makefile rename to lldb/test/API/commands/frame/diagnose/local-variable/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/local-variable/TestLocalVariable.py b/lldb/test/API/commands/frame/diagnose/local-variable/TestLocalVariable.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/local-variable/TestLocalVariable.py rename to lldb/test/API/commands/frame/diagnose/local-variable/TestLocalVariable.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/local-variable/main.c b/lldb/test/API/commands/frame/diagnose/local-variable/main.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/local-variable/main.c rename to lldb/test/API/commands/frame/diagnose/local-variable/main.c diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/virtual-method-call/Makefile b/lldb/test/API/commands/frame/diagnose/virtual-method-call/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/virtual-method-call/Makefile rename to lldb/test/API/commands/frame/diagnose/virtual-method-call/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/virtual-method-call/TestDiagnoseDereferenceVirtualMethodCall.py b/lldb/test/API/commands/frame/diagnose/virtual-method-call/TestDiagnoseDereferenceVirtualMethodCall.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/virtual-method-call/TestDiagnoseDereferenceVirtualMethodCall.py rename to lldb/test/API/commands/frame/diagnose/virtual-method-call/TestDiagnoseDereferenceVirtualMethodCall.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/virtual-method-call/main.cpp b/lldb/test/API/commands/frame/diagnose/virtual-method-call/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/diagnose/virtual-method-call/main.cpp rename to lldb/test/API/commands/frame/diagnose/virtual-method-call/main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/language/Makefile b/lldb/test/API/commands/frame/language/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/language/Makefile rename to lldb/test/API/commands/frame/language/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/language/TestGuessLanguage.py b/lldb/test/API/commands/frame/language/TestGuessLanguage.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/language/TestGuessLanguage.py rename to lldb/test/API/commands/frame/language/TestGuessLanguage.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/language/main.cpp b/lldb/test/API/commands/frame/language/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/language/main.cpp rename to lldb/test/API/commands/frame/language/main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/commands/frame/language/other-2.cpp b/lldb/test/API/commands/frame/language/other-2.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/frame/language/other-2.cpp rename to lldb/test/API/commands/frame/language/other-2.cpp diff --git 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lldb/test/API/commands/platform/basic/TestPlatformPython.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/platform/process/Makefile b/lldb/test/API/commands/platform/process/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/platform/process/Makefile rename to lldb/test/API/commands/platform/process/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/platform/process/TestProcessList.py b/lldb/test/API/commands/platform/process/TestProcessList.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/platform/process/TestProcessList.py rename to lldb/test/API/commands/platform/process/TestProcessList.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/platform/process/main.cpp b/lldb/test/API/commands/platform/process/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/platform/process/main.cpp rename to lldb/test/API/commands/platform/process/main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/commands/process/attach-resume/Makefile b/lldb/test/API/commands/process/attach-resume/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/process/attach-resume/Makefile rename to lldb/test/API/commands/process/attach-resume/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/commands/process/attach-resume/TestAttachResume.py b/lldb/test/API/commands/process/attach-resume/TestAttachResume.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/process/attach-resume/TestAttachResume.py rename to lldb/test/API/commands/process/attach-resume/TestAttachResume.py diff --git a/lldb/packages/Python/lldbsuite/test/commands/process/attach-resume/main.cpp b/lldb/test/API/commands/process/attach-resume/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/commands/process/attach-resume/main.cpp rename to lldb/test/API/commands/process/attach-resume/main.cpp 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a/lldb/packages/Python/lldbsuite/test/lang/objcxx/hide-runtime-values/Makefile b/lldb/test/API/lang/objcxx/hide-runtime-values/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/lang/objcxx/hide-runtime-values/Makefile rename to lldb/test/API/lang/objcxx/hide-runtime-values/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/lang/objcxx/hide-runtime-values/TestObjCXXHideRuntimeValues.py b/lldb/test/API/lang/objcxx/hide-runtime-values/TestObjCXXHideRuntimeValues.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/lang/objcxx/hide-runtime-values/TestObjCXXHideRuntimeValues.py rename to lldb/test/API/lang/objcxx/hide-runtime-values/TestObjCXXHideRuntimeValues.py diff --git a/lldb/packages/Python/lldbsuite/test/lang/objcxx/hide-runtime-values/main.mm b/lldb/test/API/lang/objcxx/hide-runtime-values/main.mm similarity index 100% rename from lldb/packages/Python/lldbsuite/test/lang/objcxx/hide-runtime-values/main.mm rename to lldb/test/API/lang/objcxx/hide-runtime-values/main.mm diff --git a/lldb/packages/Python/lldbsuite/test/lang/objcxx/objcxx-ivar-vector/TestIvarVector.py b/lldb/test/API/lang/objcxx/objcxx-ivar-vector/TestIvarVector.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/lang/objcxx/objcxx-ivar-vector/TestIvarVector.py rename to lldb/test/API/lang/objcxx/objcxx-ivar-vector/TestIvarVector.py diff --git a/lldb/packages/Python/lldbsuite/test/lang/objcxx/objcxx-ivar-vector/main.mm b/lldb/test/API/lang/objcxx/objcxx-ivar-vector/main.mm similarity index 100% rename from lldb/packages/Python/lldbsuite/test/lang/objcxx/objcxx-ivar-vector/main.mm rename to lldb/test/API/lang/objcxx/objcxx-ivar-vector/main.mm diff --git a/lldb/packages/Python/lldbsuite/test/lang/objcxx/sample/Makefile b/lldb/test/API/lang/objcxx/sample/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/lang/objcxx/sample/Makefile rename to lldb/test/API/lang/objcxx/sample/Makefile diff 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similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/add-symbols/main.c rename to lldb/test/API/linux/add-symbols/main.c diff --git a/lldb/packages/Python/lldbsuite/test/linux/builtin_trap/Makefile b/lldb/test/API/linux/builtin_trap/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/builtin_trap/Makefile rename to lldb/test/API/linux/builtin_trap/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/linux/builtin_trap/TestBuiltinTrap.py b/lldb/test/API/linux/builtin_trap/TestBuiltinTrap.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/builtin_trap/TestBuiltinTrap.py rename to lldb/test/API/linux/builtin_trap/TestBuiltinTrap.py diff --git a/lldb/packages/Python/lldbsuite/test/linux/builtin_trap/main.cpp b/lldb/test/API/linux/builtin_trap/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/builtin_trap/main.cpp rename to lldb/test/API/linux/builtin_trap/main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/linux/mix-dwo-and-regular-objects/Makefile b/lldb/test/API/linux/mix-dwo-and-regular-objects/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/mix-dwo-and-regular-objects/Makefile rename to lldb/test/API/linux/mix-dwo-and-regular-objects/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/linux/mix-dwo-and-regular-objects/TestMixedDwarfBinary.py b/lldb/test/API/linux/mix-dwo-and-regular-objects/TestMixedDwarfBinary.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/mix-dwo-and-regular-objects/TestMixedDwarfBinary.py rename to lldb/test/API/linux/mix-dwo-and-regular-objects/TestMixedDwarfBinary.py diff --git a/lldb/packages/Python/lldbsuite/test/linux/mix-dwo-and-regular-objects/a.c b/lldb/test/API/linux/mix-dwo-and-regular-objects/a.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/mix-dwo-and-regular-objects/a.c rename to lldb/test/API/linux/mix-dwo-and-regular-objects/a.c diff --git a/lldb/packages/Python/lldbsuite/test/linux/mix-dwo-and-regular-objects/b.c b/lldb/test/API/linux/mix-dwo-and-regular-objects/b.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/mix-dwo-and-regular-objects/b.c rename to lldb/test/API/linux/mix-dwo-and-regular-objects/b.c diff --git a/lldb/packages/Python/lldbsuite/test/linux/sepdebugsymlink/Makefile b/lldb/test/API/linux/sepdebugsymlink/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/sepdebugsymlink/Makefile rename to lldb/test/API/linux/sepdebugsymlink/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/linux/sepdebugsymlink/TestTargetSymbolsSepDebugSymlink.py b/lldb/test/API/linux/sepdebugsymlink/TestTargetSymbolsSepDebugSymlink.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/sepdebugsymlink/TestTargetSymbolsSepDebugSymlink.py rename to lldb/test/API/linux/sepdebugsymlink/TestTargetSymbolsSepDebugSymlink.py diff --git a/lldb/packages/Python/lldbsuite/test/linux/sepdebugsymlink/main.c b/lldb/test/API/linux/sepdebugsymlink/main.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/sepdebugsymlink/main.c rename to lldb/test/API/linux/sepdebugsymlink/main.c diff --git a/lldb/packages/Python/lldbsuite/test/linux/thread/create_during_instruction_step/Makefile b/lldb/test/API/linux/thread/create_during_instruction_step/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/thread/create_during_instruction_step/Makefile rename to lldb/test/API/linux/thread/create_during_instruction_step/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/linux/thread/create_during_instruction_step/TestCreateDuringInstructionStep.py b/lldb/test/API/linux/thread/create_during_instruction_step/TestCreateDuringInstructionStep.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/thread/create_during_instruction_step/TestCreateDuringInstructionStep.py rename to lldb/test/API/linux/thread/create_during_instruction_step/TestCreateDuringInstructionStep.py diff --git a/lldb/packages/Python/lldbsuite/test/linux/thread/create_during_instruction_step/main.cpp b/lldb/test/API/linux/thread/create_during_instruction_step/main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/linux/thread/create_during_instruction_step/main.cpp rename to lldb/test/API/linux/thread/create_during_instruction_step/main.cpp diff --git a/lldb/test/API/lit.cfg.py b/lldb/test/API/lit.cfg.py index 79401ae47d13..10df5600db4c 100644 --- a/lldb/test/API/lit.cfg.py +++ b/lldb/test/API/lit.cfg.py @@ -17,8 +17,7 @@ config.suffixes = ['.py'] # test_source_root: The root path where tests are located. # test_exec_root: The root path where tests should be run. -config.test_source_root = os.path.join(config.lldb_src_root, 'packages', - 'Python', 'lldbsuite', 'test') +config.test_source_root = os.path.dirname(__file__) config.test_exec_root = config.test_source_root if 'Address' in config.llvm_use_sanitizer: diff --git a/lldb/packages/Python/lldbsuite/test/macosx/DBGSourcePathRemapping/Inputs/main.c b/lldb/test/API/macosx/DBGSourcePathRemapping/Inputs/main.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/macosx/DBGSourcePathRemapping/Inputs/main.c rename to lldb/test/API/macosx/DBGSourcePathRemapping/Inputs/main.c diff --git a/lldb/packages/Python/lldbsuite/test/macosx/DBGSourcePathRemapping/Inputs/relative.c b/lldb/test/API/macosx/DBGSourcePathRemapping/Inputs/relative.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/macosx/DBGSourcePathRemapping/Inputs/relative.c rename to lldb/test/API/macosx/DBGSourcePathRemapping/Inputs/relative.c diff --git a/lldb/packages/Python/lldbsuite/test/macosx/DBGSourcePathRemapping/Makefile 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lldb/packages/Python/lldbsuite/test/macosx/find-app-in-bundle/TestFindAppInBundle.py rename to lldb/test/API/macosx/find-app-in-bundle/TestFindAppInBundle.py diff --git a/lldb/packages/Python/lldbsuite/test/macosx/find-app-in-bundle/main.c b/lldb/test/API/macosx/find-app-in-bundle/main.c similarity index 100% rename from lldb/packages/Python/lldbsuite/test/macosx/find-app-in-bundle/main.c rename to lldb/test/API/macosx/find-app-in-bundle/main.c diff --git a/lldb/packages/Python/lldbsuite/test/macosx/find-dsym/bundle-with-dot-in-filename/Makefile b/lldb/test/API/macosx/find-dsym/bundle-with-dot-in-filename/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/macosx/find-dsym/bundle-with-dot-in-filename/Makefile rename to lldb/test/API/macosx/find-dsym/bundle-with-dot-in-filename/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/macosx/find-dsym/bundle-with-dot-in-filename/TestBundleWithDotInFilename.py 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lldb/packages/Python/lldbsuite/test/macosx/find-dsym/bundle-with-dot-in-filename/main.c rename to lldb/test/API/macosx/find-dsym/bundle-with-dot-in-filename/main.c diff --git a/lldb/packages/Python/lldbsuite/test/macosx/find-dsym/deep-bundle/Info.plist b/lldb/test/API/macosx/find-dsym/deep-bundle/Info.plist similarity index 100% rename from lldb/packages/Python/lldbsuite/test/macosx/find-dsym/deep-bundle/Info.plist rename to lldb/test/API/macosx/find-dsym/deep-bundle/Info.plist diff --git a/lldb/packages/Python/lldbsuite/test/macosx/find-dsym/deep-bundle/Makefile b/lldb/test/API/macosx/find-dsym/deep-bundle/Makefile similarity index 100% rename from lldb/packages/Python/lldbsuite/test/macosx/find-dsym/deep-bundle/Makefile rename to lldb/test/API/macosx/find-dsym/deep-bundle/Makefile diff --git a/lldb/packages/Python/lldbsuite/test/macosx/find-dsym/deep-bundle/MyFramework.h b/lldb/test/API/macosx/find-dsym/deep-bundle/MyFramework.h similarity index 100% rename from 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a/lldb/packages/Python/lldbsuite/test/types/TestFloatTypesExpr.py b/lldb/test/API/types/TestFloatTypesExpr.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/TestFloatTypesExpr.py rename to lldb/test/API/types/TestFloatTypesExpr.py diff --git a/lldb/packages/Python/lldbsuite/test/types/TestIntegerType.py b/lldb/test/API/types/TestIntegerType.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/TestIntegerType.py rename to lldb/test/API/types/TestIntegerType.py diff --git a/lldb/packages/Python/lldbsuite/test/types/TestIntegerTypeExpr.py b/lldb/test/API/types/TestIntegerTypeExpr.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/TestIntegerTypeExpr.py rename to lldb/test/API/types/TestIntegerTypeExpr.py diff --git a/lldb/packages/Python/lldbsuite/test/types/TestLongTypes.py b/lldb/test/API/types/TestLongTypes.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/TestLongTypes.py rename to lldb/test/API/types/TestLongTypes.py diff --git a/lldb/packages/Python/lldbsuite/test/types/TestLongTypesExpr.py b/lldb/test/API/types/TestLongTypesExpr.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/TestLongTypesExpr.py rename to lldb/test/API/types/TestLongTypesExpr.py diff --git a/lldb/packages/Python/lldbsuite/test/types/TestRecursiveTypes.py b/lldb/test/API/types/TestRecursiveTypes.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/TestRecursiveTypes.py rename to lldb/test/API/types/TestRecursiveTypes.py diff --git a/lldb/packages/Python/lldbsuite/test/types/TestShortType.py b/lldb/test/API/types/TestShortType.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/TestShortType.py rename to lldb/test/API/types/TestShortType.py diff --git a/lldb/packages/Python/lldbsuite/test/types/TestShortTypeExpr.py b/lldb/test/API/types/TestShortTypeExpr.py similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/TestShortTypeExpr.py rename to lldb/test/API/types/TestShortTypeExpr.py diff --git a/lldb/packages/Python/lldbsuite/test/types/basic_type.cpp b/lldb/test/API/types/basic_type.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/basic_type.cpp rename to lldb/test/API/types/basic_type.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/char.cpp b/lldb/test/API/types/char.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/char.cpp rename to lldb/test/API/types/char.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/double.cpp b/lldb/test/API/types/double.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/double.cpp rename to lldb/test/API/types/double.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/float.cpp b/lldb/test/API/types/float.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/float.cpp rename to lldb/test/API/types/float.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/int.cpp b/lldb/test/API/types/int.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/int.cpp rename to lldb/test/API/types/int.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/long.cpp b/lldb/test/API/types/long.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/long.cpp rename to lldb/test/API/types/long.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/long_long.cpp b/lldb/test/API/types/long_long.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/long_long.cpp rename to lldb/test/API/types/long_long.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/recursive_type_1.cpp b/lldb/test/API/types/recursive_type_1.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/recursive_type_1.cpp rename to lldb/test/API/types/recursive_type_1.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/recursive_type_2.cpp b/lldb/test/API/types/recursive_type_2.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/recursive_type_2.cpp rename to lldb/test/API/types/recursive_type_2.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/recursive_type_main.cpp b/lldb/test/API/types/recursive_type_main.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/recursive_type_main.cpp rename to lldb/test/API/types/recursive_type_main.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/short.cpp b/lldb/test/API/types/short.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/short.cpp rename to lldb/test/API/types/short.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/unsigned_char.cpp b/lldb/test/API/types/unsigned_char.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/unsigned_char.cpp rename to lldb/test/API/types/unsigned_char.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/unsigned_int.cpp b/lldb/test/API/types/unsigned_int.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/unsigned_int.cpp rename to lldb/test/API/types/unsigned_int.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/unsigned_long.cpp b/lldb/test/API/types/unsigned_long.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/unsigned_long.cpp rename to lldb/test/API/types/unsigned_long.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/unsigned_long_long.cpp b/lldb/test/API/types/unsigned_long_long.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/unsigned_long_long.cpp rename to lldb/test/API/types/unsigned_long_long.cpp diff --git a/lldb/packages/Python/lldbsuite/test/types/unsigned_short.cpp b/lldb/test/API/types/unsigned_short.cpp similarity index 100% rename from lldb/packages/Python/lldbsuite/test/types/unsigned_short.cpp rename to lldb/test/API/types/unsigned_short.cpp -- GitLab From 76d6bce629458a37470cef304df3bc35f042eace Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Tue, 11 Feb 2020 10:03:35 -0800 Subject: [PATCH 036/142] gn build: Make scudo cflags more consistent with the cmake build. --- .../compiler-rt/lib/scudo/standalone/BUILD.gn | 12 ++++++++++-- .../compiler-rt/lib/scudo/standalone/tests/BUILD.gn | 11 +++++++++-- 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/BUILD.gn b/llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/BUILD.gn index 14bff487fff5..bcf28662f751 100644 --- a/llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/BUILD.gn +++ b/llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/BUILD.gn @@ -1,8 +1,14 @@ import("//compiler-rt/target.gni") +scudo_cflags = [ + "-Werror=conversion", + "-nostdinc++", +] + source_set("sources") { configs -= [ "//llvm/utils/gn/build:llvm_code" ] configs += [ "//llvm/utils/gn/build:crt_code" ] + cflags = scudo_cflags sources = [ "allocator_config.h", "atomic_helpers.h", @@ -47,10 +53,10 @@ source_set("sources") { ] if (current_cpu == "arm" || current_cpu == "arm64") { - cflags = [ "-mcrc" ] + cflags += [ "-mcrc" ] } if (current_cpu == "x64") { - cflags = [ "-msse4.2" ] + cflags += [ "-msse4.2" ] } public_configs = [ ":scudo_config" ] @@ -59,6 +65,7 @@ source_set("sources") { source_set("c_wrapper_sources") { configs -= [ "//llvm/utils/gn/build:llvm_code" ] configs += [ "//llvm/utils/gn/build:crt_code" ] + cflags = scudo_cflags sources = [ # Make `gn format` not collapse this, for sync_source_lists_from_cmake.py. "wrappers_c.cpp", @@ -70,6 +77,7 @@ source_set("c_wrapper_sources") { source_set("cxx_wrapper_sources") { configs -= [ "//llvm/utils/gn/build:llvm_code" ] configs += [ "//llvm/utils/gn/build:crt_code" ] + cflags = scudo_cflags sources = [ # Make `gn format` not collapse this, for sync_source_lists_from_cmake.py. "wrappers_cpp.cpp", diff --git a/llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/tests/BUILD.gn b/llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/tests/BUILD.gn index 3c8ed7353e1a..4574278677aa 100644 --- a/llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/tests/BUILD.gn +++ b/llvm/utils/gn/secondary/compiler-rt/lib/scudo/standalone/tests/BUILD.gn @@ -1,9 +1,14 @@ import("//llvm/utils/gn/build/toolchain/compiler.gni") import("//llvm/utils/unittest/unittest.gni") +test_cflags = [ "-DSCUDO_DEBUG=1" ] + unittest("ScudoUnitTest") { configs += [ "//llvm/utils/gn/build:crt_code" ] - deps = [ "//compiler-rt/lib/scudo/standalone:sources" ] + cflags = test_cflags + deps = [ + "//compiler-rt/lib/scudo/standalone:sources", + ] sources = [ "atomic_test.cpp", "bytemap_test.cpp", @@ -31,6 +36,7 @@ unittest("ScudoUnitTest") { unittest("ScudoCUnitTest") { configs += [ "//llvm/utils/gn/build:crt_code" ] + cflags = test_cflags deps = [ "//compiler-rt/lib/scudo/standalone:c_wrapper_sources", "//compiler-rt/lib/scudo/standalone:sources", @@ -44,6 +50,7 @@ unittest("ScudoCUnitTest") { unittest("ScudoCxxUnitTest") { configs += [ "//llvm/utils/gn/build:crt_code" ] + cflags = test_cflags deps = [ "//compiler-rt/lib/scudo/standalone:c_wrapper_sources", "//compiler-rt/lib/scudo/standalone:cxx_wrapper_sources", @@ -54,7 +61,7 @@ unittest("ScudoCxxUnitTest") { "wrappers_cpp_test.cpp", ] if (is_clang) { - cflags = [ "-Wno-mismatched-new-delete" ] + cflags += [ "-Wno-mismatched-new-delete" ] } has_custom_main = true } -- GitLab From 734f086b42c7e2d7aaee41cc4babad7ef8dcdb9c Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Tue, 11 Feb 2020 10:10:52 -0800 Subject: [PATCH 037/142] [NFC] Fix unused var in release builds --- llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index a0b68ed936e5..3ddba25fcef6 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -860,6 +860,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { const SDValue &Constant = Node->getOperand(3); assert(Chain.getValueType() == MVT::Other); + (void)Intrinsic; assert(Intrinsic.getOpcode() == ISD::TargetConstant && Constant.getOpcode() == ISD::Constant && "Invalid instruction operand."); @@ -931,6 +932,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { const SDValue &Constant = Node->getOperand(4); assert(Chain.getValueType() == MVT::Other); + (void)Intrinsic; assert(Intrinsic.getOpcode() == ISD::TargetConstant && Constant.getOpcode() == ISD::Constant && "Invalid instruction operand."); -- GitLab From 696f80736b861dfab5a7330dd009fd1d53b60356 Mon Sep 17 00:00:00 2001 From: Diego Caballero Date: Tue, 11 Feb 2020 09:38:34 -0800 Subject: [PATCH 038/142] [mlir] Turn flags in ConvertStandardToLLVM into pass flags Follow-up on D72802. Turn -convert-std-to-llvm-use-alloca and -convert-std-to-llvm-bare-ptr-memref-call-conv into pass flags of LLVMLoweringPass. Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D73912 --- .../ConvertStandardToLLVMPass.h | 3 +- .../StandardToLLVM/ConvertStandardToLLVM.cpp | 64 ++++++++----------- .../StandardToLLVM/calling-convention.mlir | 2 +- .../convert-static-memref-ops.mlir | 4 +- .../mlir-cpu-runner/bare_ptr_call_conv.mlir | 2 +- 5 files changed, 33 insertions(+), 42 deletions(-) diff --git a/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h b/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h index 8f319029f7b5..7d2a076aeb25 100644 --- a/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h +++ b/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h @@ -58,7 +58,8 @@ void populateStdToLLVMBarePtrConversionPatterns( /// Specifying `useAlloca-true` emits stack allocations instead. In the future /// this may become an enum when we have concrete uses for other options. std::unique_ptr> -createLowerToLLVMPass(bool useAlloca = false, bool emitCWrappers = false); +createLowerToLLVMPass(bool useAlloca = false, bool useBarePtrCallConv = false, + bool emitCWrappers = false); namespace LLVM { /// Make argument-taking successors of each block distinct. PHI nodes in LLVM diff --git a/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp b/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp index 36c98d0e85b1..17209c72e054 100644 --- a/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp +++ b/mlir/lib/Conversion/StandardToLLVM/ConvertStandardToLLVM.cpp @@ -36,25 +36,6 @@ using namespace mlir; #define PASS_NAME "convert-std-to-llvm" -static llvm::cl::OptionCategory - clOptionsCategory("Standard to LLVM lowering options"); - -static llvm::cl::opt - clUseAlloca(PASS_NAME "-use-alloca", - llvm::cl::desc("Replace emission of malloc/free by alloca"), - llvm::cl::init(false)); - -static llvm::cl::opt - clEmitCWrappers(PASS_NAME "-emit-c-wrappers", - llvm::cl::desc("Emit C-compatible wrapper functions"), - llvm::cl::init(false)); - -static llvm::cl::opt clUseBarePtrCallConv( - PASS_NAME "-use-bare-ptr-memref-call-conv", - llvm::cl::desc("Replace FuncOp's MemRef arguments with " - "bare pointers to the MemRef element types"), - llvm::cl::init(false)); - // Extract an LLVM IR type from the LLVM IR dialect type. static LLVM::LLVMType unwrap(Type type) { if (!type) @@ -2730,11 +2711,14 @@ namespace { /// A pass converting MLIR operations into the LLVM IR dialect. struct LLVMLoweringPass : public ModulePass { /// Creates an LLVM lowering pass. - explicit LLVMLoweringPass(bool useAlloca = false, - bool useBarePtrCallConv = false, - bool emitCWrappers = false) - : useAlloca(useAlloca), useBarePtrCallConv(useBarePtrCallConv), - emitCWrappers(emitCWrappers) {} + explicit LLVMLoweringPass(bool useAlloca, bool useBarePtrCallConv, + bool emitCWrappers) { + this->useAlloca = useAlloca; + this->useBarePtrCallConv = useBarePtrCallConv; + this->emitCWrappers = emitCWrappers; + } + explicit LLVMLoweringPass() {} + LLVMLoweringPass(const LLVMLoweringPass &pass) {} /// Run the dialect converter on the module. void runOnModule() override { @@ -2769,27 +2753,33 @@ struct LLVMLoweringPass : public ModulePass { } /// Use `alloca` instead of `call @malloc` for converting std.alloc. - bool useAlloca; + Option useAlloca{ + *this, "use-alloca", + llvm::cl::desc("Replace emission of malloc/free by alloca"), + llvm::cl::init(false)}; /// Convert memrefs to bare pointers in function signatures. - bool useBarePtrCallConv; + Option useBarePtrCallConv{ + *this, "use-bare-ptr-memref-call-conv", + llvm::cl::desc("Replace FuncOp's MemRef arguments with " + "bare pointers to the MemRef element types"), + llvm::cl::init(false)}; /// Emit wrappers for C-compatible pointer-to-struct memref descriptors. - bool emitCWrappers; + Option emitCWrappers{ + *this, "emit-c-wrappers", + llvm::cl::desc("Emit C-compatible wrapper functions"), + llvm::cl::init(false)}; }; } // end namespace std::unique_ptr> -mlir::createLowerToLLVMPass(bool useAlloca, bool emitCWrappers) { - return std::make_unique(useAlloca, emitCWrappers); +mlir::createLowerToLLVMPass(bool useAlloca, bool useBarePtrCallConv, + bool emitCWrappers) { + return std::make_unique(useAlloca, useBarePtrCallConv, + emitCWrappers); } static PassRegistration - pass(PASS_NAME, - "Convert scalar and vector operations from the " - "Standard to the LLVM dialect", - [] { - return std::make_unique( - clUseAlloca.getValue(), clUseBarePtrCallConv.getValue(), - clEmitCWrappers.getValue()); - }); + pass(PASS_NAME, "Convert scalar and vector operations from the " + "Standard to the LLVM dialect"); diff --git a/mlir/test/Conversion/StandardToLLVM/calling-convention.mlir b/mlir/test/Conversion/StandardToLLVM/calling-convention.mlir index d9b5b9474d48..348afff33967 100644 --- a/mlir/test/Conversion/StandardToLLVM/calling-convention.mlir +++ b/mlir/test/Conversion/StandardToLLVM/calling-convention.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt -convert-std-to-llvm -convert-std-to-llvm-emit-c-wrappers %s | FileCheck %s +// RUN: mlir-opt -convert-std-to-llvm='emit-c-wrappers=1' %s | FileCheck %s // This tests the default memref calling convention and the emission of C // wrappers. We don't need to separate runs because the wrapper-emission diff --git a/mlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir b/mlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir index c25d8a235701..cc8cfc3b6917 100644 --- a/mlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir +++ b/mlir/test/Conversion/StandardToLLVM/convert-static-memref-ops.mlir @@ -1,6 +1,6 @@ // RUN: mlir-opt -convert-std-to-llvm %s | FileCheck %s -// RUN: mlir-opt -convert-std-to-llvm -convert-std-to-llvm-use-alloca=1 %s | FileCheck %s --check-prefix=ALLOCA -// RUN: mlir-opt -convert-std-to-llvm -split-input-file -convert-std-to-llvm-use-bare-ptr-memref-call-conv=1 %s | FileCheck %s --check-prefix=BAREPTR +// RUN: mlir-opt -convert-std-to-llvm='use-alloca=1' %s | FileCheck %s --check-prefix=ALLOCA +// RUN: mlir-opt -convert-std-to-llvm='use-bare-ptr-memref-call-conv=1' -split-input-file %s | FileCheck %s --check-prefix=BAREPTR // BAREPTR-LABEL: func @check_noalias // BAREPTR-SAME: %{{.*}}: !llvm<"float*"> {llvm.noalias = true} diff --git a/mlir/test/mlir-cpu-runner/bare_ptr_call_conv.mlir b/mlir/test/mlir-cpu-runner/bare_ptr_call_conv.mlir index 59fd969661e3..a0022afac7e7 100644 --- a/mlir/test/mlir-cpu-runner/bare_ptr_call_conv.mlir +++ b/mlir/test/mlir-cpu-runner/bare_ptr_call_conv.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt %s -convert-loop-to-std -convert-std-to-llvm -convert-std-to-llvm-use-bare-ptr-memref-call-conv | mlir-cpu-runner -shared-libs=%linalg_test_lib_dir/libmlir_runner_utils%shlibext -entry-point-result=void | FileCheck %s +// RUN: mlir-opt %s -convert-loop-to-std -convert-std-to-llvm='use-bare-ptr-memref-call-conv=1' | mlir-cpu-runner -shared-libs=%linalg_test_lib_dir/libmlir_runner_utils%shlibext -entry-point-result=void | FileCheck %s // Verify bare pointer memref calling convention. `simple_add1_add2_test` // gets two 2xf32 memrefs, adds 1.0f to the first one and 2.0f to the second -- GitLab From f0fd852fcd054297f2b07e2ca87551de9b2a39c0 Mon Sep 17 00:00:00 2001 From: Justin Lebar Date: Mon, 10 Feb 2020 22:52:00 -0800 Subject: [PATCH 039/142] Fix SFINAE in CFG.cpp. Summary: Used std::enable_if without ::type. Reviewers: bkramer, MaskRay Subscribers: martong, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D74412 --- clang/lib/Analysis/CFG.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/clang/lib/Analysis/CFG.cpp b/clang/lib/Analysis/CFG.cpp index 4c1ea8995f9f..8091625703bc 100644 --- a/clang/lib/Analysis/CFG.cpp +++ b/clang/lib/Analysis/CFG.cpp @@ -720,10 +720,10 @@ private: // These sorts of call expressions don't have a common superclass, // hence strict duck-typing. template ::value || - std::is_same::value || - std::is_same::value>> + typename = std::enable_if_t< + std::is_base_of::value || + std::is_base_of::value || + std::is_base_of::value>> void findConstructionContextsForArguments(CallLikeExpr *E) { for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) { Expr *Arg = E->getArg(i); -- GitLab From 027eb71696f6ce4fdeb63f68c8c6b66e147ad407 Mon Sep 17 00:00:00 2001 From: Justin Lebar Date: Mon, 10 Feb 2020 23:23:44 -0800 Subject: [PATCH 040/142] Use std::foo_t rather than std::foo in clang. Summary: No functional change. Reviewers: bkramer, MaskRay, martong, shafik Subscribers: martong, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D74414 --- clang/include/clang/AST/ASTTypeTraits.h | 8 ++--- clang/include/clang/AST/CanonicalType.h | 2 +- clang/include/clang/AST/DataCollection.h | 7 ++-- clang/include/clang/AST/Expr.h | 14 ++++---- clang/include/clang/AST/OpenMPClause.h | 11 +++---- clang/include/clang/AST/RecursiveASTVisitor.h | 4 +-- .../clang/ASTMatchers/ASTMatchersInternal.h | 9 +++-- clang/include/clang/Analysis/CFG.h | 19 +++++------ clang/include/clang/Basic/Diagnostic.h | 10 +++--- clang/include/clang/Basic/PartialDiagnostic.h | 7 ++-- .../Tooling/Refactoring/RefactoringOptions.h | 8 ++--- clang/lib/AST/ASTImporter.cpp | 2 +- clang/lib/AST/Interp/Boolean.h | 7 ++-- clang/lib/AST/Interp/Integral.h | 33 +++++++++---------- clang/lib/AST/Interp/Source.h | 4 +-- clang/lib/Analysis/ThreadSafety.cpp | 6 ++-- clang/lib/CodeGen/CGOpenMPRuntime.h | 7 ++-- clang/lib/Sema/SemaDeclAttr.cpp | 3 +- clang/lib/Sema/SemaTemplateDeduction.cpp | 4 +-- .../Frontend/CheckerRegistry.cpp | 9 +++-- clang/lib/Tooling/ASTDiff/ASTDiff.cpp | 4 +-- clang/unittests/Tooling/ASTSelectionTest.cpp | 20 +++++------ 22 files changed, 91 insertions(+), 107 deletions(-) diff --git a/clang/include/clang/AST/ASTTypeTraits.h b/clang/include/clang/AST/ASTTypeTraits.h index 1a12281d039d..777ad2fec349 100644 --- a/clang/include/clang/AST/ASTTypeTraits.h +++ b/clang/include/clang/AST/ASTTypeTraits.h @@ -465,22 +465,22 @@ private: template struct DynTypedNode::BaseConverter< - T, typename std::enable_if::value>::type> + T, std::enable_if_t::value>> : public DynCastPtrConverter {}; template struct DynTypedNode::BaseConverter< - T, typename std::enable_if::value>::type> + T, std::enable_if_t::value>> : public DynCastPtrConverter {}; template struct DynTypedNode::BaseConverter< - T, typename std::enable_if::value>::type> + T, std::enable_if_t::value>> : public DynCastPtrConverter {}; template struct DynTypedNode::BaseConverter< - T, typename std::enable_if::value>::type> + T, std::enable_if_t::value>> : public DynCastPtrConverter {}; template <> diff --git a/clang/include/clang/AST/CanonicalType.h b/clang/include/clang/AST/CanonicalType.h index 64ec1c0ce471..31b14c0d39c3 100644 --- a/clang/include/clang/AST/CanonicalType.h +++ b/clang/include/clang/AST/CanonicalType.h @@ -74,7 +74,7 @@ public: /// canonical type pointers. template CanQual(const CanQual &Other, - typename std::enable_if::value, int>::type = 0); + std::enable_if_t::value, int> = 0); /// Retrieve the underlying type pointer, which refers to a /// canonical type. diff --git a/clang/include/clang/AST/DataCollection.h b/clang/include/clang/AST/DataCollection.h index 37f101793ecc..14d1bc188623 100644 --- a/clang/include/clang/AST/DataCollection.h +++ b/clang/include/clang/AST/DataCollection.h @@ -50,10 +50,9 @@ template void addDataToConsumer(T &DataConsumer, const QualType &QT) { } template -typename std::enable_if< - std::is_integral::value || std::is_enum::value || - std::is_convertible::value // for llvm::hash_code - >::type +std::enable_if_t::value || std::is_enum::value || + std::is_convertible::value // for llvm::hash_code + > addDataToConsumer(T &DataConsumer, Type Data) { DataConsumer.update(StringRef(reinterpret_cast(&Data), sizeof(Data))); } diff --git a/clang/include/clang/AST/Expr.h b/clang/include/clang/AST/Expr.h index 5d9174f6e627..fcdb0b992134 100644 --- a/clang/include/clang/AST/Expr.h +++ b/clang/include/clang/AST/Expr.h @@ -5282,10 +5282,9 @@ class GenericSelectionExpr final template class AssociationTy { friend class GenericSelectionExpr; template friend class AssociationIteratorTy; - using ExprPtrTy = - typename std::conditional::type; - using TSIPtrTy = typename std::conditional::type; + using ExprPtrTy = std::conditional_t; + using TSIPtrTy = + std::conditional_t; ExprPtrTy E; TSIPtrTy TSI; bool Selected; @@ -5327,10 +5326,9 @@ class GenericSelectionExpr final // const Association &Assoc = *It++; // Oops, Assoc is dangling. using BaseTy = typename AssociationIteratorTy::iterator_facade_base; using StmtPtrPtrTy = - typename std::conditional::type; - using TSIPtrPtrTy = - typename std::conditional::type; + std::conditional_t; + using TSIPtrPtrTy = std::conditional_t; StmtPtrPtrTy E; // = nullptr; FIXME: Once support for gcc 4.8 is dropped. TSIPtrPtrTy TSI; // Kept in sync with E. unsigned Offset = 0, SelectedOffset = 0; diff --git a/clang/include/clang/AST/OpenMPClause.h b/clang/include/clang/AST/OpenMPClause.h index 1e6c5f928eb9..f103530457ee 100644 --- a/clang/include/clang/AST/OpenMPClause.h +++ b/clang/include/clang/AST/OpenMPClause.h @@ -6611,7 +6611,7 @@ public: template class Ptr, typename RetTy> class OMPClauseVisitorBase { public: -#define PTR(CLASS) typename Ptr::type +#define PTR(CLASS) Ptr #define DISPATCH(CLASS) \ return static_cast(this)->Visit##CLASS(static_cast(S)) @@ -6634,12 +6634,11 @@ public: #undef DISPATCH }; -template -using const_ptr = typename std::add_pointer::type>; +template using const_ptr = std::add_pointer_t>; -template -class OMPClauseVisitor : - public OMPClauseVisitorBase {}; +template +class OMPClauseVisitor + : public OMPClauseVisitorBase {}; template class ConstOMPClauseVisitor : public OMPClauseVisitorBase {}; diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h index bcbac210c00f..29b2c3541002 100644 --- a/clang/include/clang/AST/RecursiveASTVisitor.h +++ b/clang/include/clang/AST/RecursiveASTVisitor.h @@ -340,11 +340,11 @@ private: (has_same_member_pointer_type::value \ - ? static_cast::value, \ - Derived &, RecursiveASTVisitor &>::type>(*this) \ + Derived &, RecursiveASTVisitor &>>(*this) \ .Traverse##NAME(static_cast(VAR), QUEUE) \ : getDerived().Traverse##NAME(static_cast(VAR))) diff --git a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h index 696eca1aa643..ff6aad056fcc 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchersInternal.h +++ b/clang/include/clang/ASTMatchers/ASTMatchersInternal.h @@ -516,8 +516,8 @@ public: /// Requires \c T to be derived from \c From. template Matcher(const Matcher &Other, - typename std::enable_if::value && - !std::is_same::value>::type * = nullptr) + std::enable_if_t::value && + !std::is_same::value> * = nullptr) : Implementation(restrictMatcher(Other.Implementation)) { assert(Implementation.getSupportedKind().isSame( ast_type_traits::ASTNodeKind::getFromNodeKind())); @@ -528,9 +528,8 @@ public: /// The resulting matcher is not strict, i.e. ignores qualifiers. template Matcher(const Matcher &Other, - typename std::enable_if< - std::is_same::value && - std::is_same::value>::type* = nullptr) + std::enable_if_t::value && + std::is_same::value> * = nullptr) : Implementation(new TypeToQualType(Other)) {} /// Convert \c this into a \c Matcher by applying dyn_cast<> to the diff --git a/clang/include/clang/Analysis/CFG.h b/clang/include/clang/Analysis/CFG.h index 93de3178e661..43fb523c863a 100644 --- a/clang/include/clang/Analysis/CFG.h +++ b/clang/include/clang/Analysis/CFG.h @@ -624,10 +624,10 @@ class CFGBlock { template friend class ElementRefImpl; using CFGBlockPtr = - typename std::conditional::type; + std::conditional_t; - using CFGElementPtr = typename std::conditional::type; + using CFGElementPtr = + std::conditional_t; protected: CFGBlockPtr Parent; @@ -675,15 +675,14 @@ class CFGBlock { friend class ElementRefIterator; using CFGBlockRef = - typename std::conditional::type; + std::conditional_t; - using UnderlayingIteratorTy = typename std::conditional< + using UnderlayingIteratorTy = std::conditional_t< IsConst, - typename std::conditional::type, - typename std::conditional::type>::type; + std::conditional_t, + std::conditional_t>; using IteratorTraits = typename std::iterator_traits; using ElementRef = typename CFGBlock::ElementRefImpl; diff --git a/clang/include/clang/Basic/Diagnostic.h b/clang/include/clang/Basic/Diagnostic.h index 377c3d56eafe..6bc8a143a26d 100644 --- a/clang/include/clang/Basic/Diagnostic.h +++ b/clang/include/clang/Basic/Diagnostic.h @@ -1217,9 +1217,7 @@ inline const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, int I) { // We use enable_if here to prevent that this overload is selected for // pointers or other arguments that are implicitly convertible to bool. template -inline -typename std::enable_if::value, - const DiagnosticBuilder &>::type +inline std::enable_if_t::value, const DiagnosticBuilder &> operator<<(const DiagnosticBuilder &DB, T I) { DB.AddTaggedVal(I, DiagnosticsEngine::ak_sint); return DB; @@ -1249,9 +1247,9 @@ inline const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB, // other arguments that derive from DeclContext (e.g., RecordDecls) will not // match. template -inline typename std::enable_if< - std::is_same::type, DeclContext>::value, - const DiagnosticBuilder &>::type +inline std::enable_if_t< + std::is_same, DeclContext>::value, + const DiagnosticBuilder &> operator<<(const DiagnosticBuilder &DB, T *DC) { DB.AddTaggedVal(reinterpret_cast(DC), DiagnosticsEngine::ak_declcontext); diff --git a/clang/include/clang/Basic/PartialDiagnostic.h b/clang/include/clang/Basic/PartialDiagnostic.h index c413cc2ffdf8..107d621f0dec 100644 --- a/clang/include/clang/Basic/PartialDiagnostic.h +++ b/clang/include/clang/Basic/PartialDiagnostic.h @@ -378,10 +378,9 @@ public: // so that we only match those arguments that are (statically) DeclContexts; // other arguments that derive from DeclContext (e.g., RecordDecls) will not // match. - template - friend inline - typename std::enable_if::value, - const PartialDiagnostic &>::type + template + friend inline std::enable_if_t::value, + const PartialDiagnostic &> operator<<(const PartialDiagnostic &PD, T *DC) { PD.AddTaggedVal(reinterpret_cast(DC), DiagnosticsEngine::ak_declcontext); diff --git a/clang/include/clang/Tooling/Refactoring/RefactoringOptions.h b/clang/include/clang/Tooling/Refactoring/RefactoringOptions.h index f25f526e146c..84122b111ee1 100644 --- a/clang/include/clang/Tooling/Refactoring/RefactoringOptions.h +++ b/clang/include/clang/Tooling/Refactoring/RefactoringOptions.h @@ -20,8 +20,8 @@ namespace clang { namespace tooling { /// A refactoring option that stores a value of type \c T. -template ::value>::type> +template ::value>> class OptionalRefactoringOption : public RefactoringOption { public: void passToVisitor(RefactoringOptionVisitor &Visitor) final override { @@ -39,8 +39,8 @@ protected: }; /// A required refactoring option that stores a value of type \c T. -template ::value>::type> +template ::value>> class RequiredRefactoringOption : public OptionalRefactoringOption { public: using ValueType = T; diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 6aad4543b41c..3361c7886c2d 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -650,7 +650,7 @@ namespace clang { template Error ImportArrayChecked(IIter Ibegin, IIter Iend, OIter Obegin) { - using ItemT = typename std::remove_reference::type; + using ItemT = std::remove_reference_t; for (; Ibegin != Iend; ++Ibegin, ++Obegin) { Expected ToOrErr = import(*Ibegin); if (!ToOrErr) diff --git a/clang/lib/AST/Interp/Boolean.h b/clang/lib/AST/Interp/Boolean.h index 3e6c8b5da9f0..2baa717311bc 100644 --- a/clang/lib/AST/Interp/Boolean.h +++ b/clang/lib/AST/Interp/Boolean.h @@ -85,14 +85,13 @@ class Boolean { static Boolean max(unsigned NumBits) { return Boolean(true); } template - static typename std::enable_if::value, Boolean>::type - from(T Value) { + static std::enable_if_t::value, Boolean> from(T Value) { return Boolean(Value != 0); } template - static typename std::enable_if::type from( - Integral Value) { + static std::enable_if_t + from(Integral Value) { return Boolean(!Value.isZero()); } diff --git a/clang/lib/AST/Interp/Integral.h b/clang/lib/AST/Interp/Integral.h index 7cc788070de8..46cd611ee389 100644 --- a/clang/lib/AST/Interp/Integral.h +++ b/clang/lib/AST/Interp/Integral.h @@ -156,13 +156,12 @@ public: } template - static typename std::enable_if::value, Integral>::type - from(T Value) { + static std::enable_if_t::value, Integral> from(T Value) { return Integral(Value); } template - static typename std::enable_if::type + static std::enable_if_t from(Integral Value) { return Integral(Value.V); } @@ -206,52 +205,52 @@ public: private: template - static typename std::enable_if::value, bool>::type - CheckAddUB(T A, T B, T &R) { + static std::enable_if_t::value, bool> CheckAddUB(T A, T B, + T &R) { return llvm::AddOverflow(A, B, R); } template - static typename std::enable_if::value, bool>::type - CheckAddUB(T A, T B, T &R) { + static std::enable_if_t::value, bool> CheckAddUB(T A, T B, + T &R) { R = A + B; return false; } template - static typename std::enable_if::value, bool>::type - CheckSubUB(T A, T B, T &R) { + static std::enable_if_t::value, bool> CheckSubUB(T A, T B, + T &R) { return llvm::SubOverflow(A, B, R); } template - static typename std::enable_if::value, bool>::type - CheckSubUB(T A, T B, T &R) { + static std::enable_if_t::value, bool> CheckSubUB(T A, T B, + T &R) { R = A - B; return false; } template - static typename std::enable_if::value, bool>::type - CheckMulUB(T A, T B, T &R) { + static std::enable_if_t::value, bool> CheckMulUB(T A, T B, + T &R) { return llvm::MulOverflow(A, B, R); } template - static typename std::enable_if::value, bool>::type - CheckMulUB(T A, T B, T &R) { + static std::enable_if_t::value, bool> CheckMulUB(T A, T B, + T &R) { R = A * B; return false; } template - static typename std::enable_if::value, bool>::type + static std::enable_if_t::value, bool> CheckRange(int64_t V) { return Min <= V && V <= Max; } template - static typename std::enable_if::value, bool>::type + static std::enable_if_t::value, bool> CheckRange(int64_t V) { return V >= 0 && static_cast(V) <= Max; } diff --git a/clang/lib/AST/Interp/Source.h b/clang/lib/AST/Interp/Source.h index e591c3399d7c..19c652b7331a 100644 --- a/clang/lib/AST/Interp/Source.h +++ b/clang/lib/AST/Interp/Source.h @@ -56,14 +56,14 @@ private: /// Helper to decode a value or a pointer. template - static typename std::enable_if::value, T>::type + static std::enable_if_t::value, T> ReadHelper(const char *Ptr) { using namespace llvm::support; return endian::read(Ptr); } template - static typename std::enable_if::value, T>::type + static std::enable_if_t::value, T> ReadHelper(const char *Ptr) { using namespace llvm::support; auto Punned = endian::read(Ptr); diff --git a/clang/lib/Analysis/ThreadSafety.cpp b/clang/lib/Analysis/ThreadSafety.cpp index 48f4106b6bae..252083f377d9 100644 --- a/clang/lib/Analysis/ThreadSafety.cpp +++ b/clang/lib/Analysis/ThreadSafety.cpp @@ -1249,8 +1249,7 @@ static StringRef ClassifyDiagnostic(const ValueDecl *VD) { } template -static typename std::enable_if::value, - StringRef>::type +static std::enable_if_t::value, StringRef> ClassifyDiagnostic(const AttrTy *A) { if (const ValueDecl *VD = getValueDecl(A->getArg())) return ClassifyDiagnostic(VD); @@ -1258,8 +1257,7 @@ ClassifyDiagnostic(const AttrTy *A) { } template -static typename std::enable_if::value, - StringRef>::type +static std::enable_if_t::value, StringRef> ClassifyDiagnostic(const AttrTy *A) { for (const auto *Arg : A->args()) { if (const ValueDecl *VD = getValueDecl(Arg)) diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h index b1a59b49fe4a..a4fe15eee26a 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.h +++ b/clang/lib/CodeGen/CGOpenMPRuntime.h @@ -80,11 +80,10 @@ public: template RegionCodeGenTy( Callable &&CodeGen, - typename std::enable_if< - !std::is_same::type, - RegionCodeGenTy>::value>::type * = nullptr) + std::enable_if_t, + RegionCodeGenTy>::value> * = nullptr) : CodeGen(reinterpret_cast(&CodeGen)), - Callback(CallbackFn::type>), + Callback(CallbackFn>), PrePostAction(nullptr) {} void setAction(PrePostActionTy &Action) const { PrePostAction = &Action; } void operator()(CodeGenFunction &CGF) const; diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 273b4e3c6f09..cf3fa3855cc8 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -225,8 +225,7 @@ static bool checkAttributeAtMostNumArgs(Sema &S, const ParsedAttr &AL, /// A helper function to provide Attribute Location for the Attr types /// AND the ParsedAttr. template -static typename std::enable_if::value, - SourceLocation>::type +static std::enable_if_t::value, SourceLocation> getAttrLoc(const AttrInfo &AL) { return AL.getLocation(); } diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp index 7451bf62cafe..24019bf7975b 100644 --- a/clang/lib/Sema/SemaTemplateDeduction.cpp +++ b/clang/lib/Sema/SemaTemplateDeduction.cpp @@ -2747,8 +2747,8 @@ CheckDeducedArgumentConstraints(Sema& S, TemplateDeclT *Template, /// Complete template argument deduction for a partial specialization. template -static typename std::enable_if::value, - Sema::TemplateDeductionResult>::type +static std::enable_if_t::value, + Sema::TemplateDeductionResult> FinishTemplateArgumentDeduction( Sema &S, T *Partial, bool IsPartialOrdering, const TemplateArgumentList &TemplateArgs, diff --git a/clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp b/clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp index 2f713a12eee0..4af204474494 100644 --- a/clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp +++ b/clang/lib/StaticAnalyzer/Frontend/CheckerRegistry.cpp @@ -51,11 +51,10 @@ using CheckerNameLT = FullNameLT; } // end of anonymous namespace template -static - typename std::conditional::value, - typename CheckerOrPackageInfoList::const_iterator, - typename CheckerOrPackageInfoList::iterator>::type - binaryFind(CheckerOrPackageInfoList &Collection, StringRef FullName) { +static std::conditional_t::value, + typename CheckerOrPackageInfoList::const_iterator, + typename CheckerOrPackageInfoList::iterator> +binaryFind(CheckerOrPackageInfoList &Collection, StringRef FullName) { using CheckerOrPackage = typename CheckerOrPackageInfoList::value_type; using CheckerOrPackageFullNameLT = FullNameLT; diff --git a/clang/lib/Tooling/ASTDiff/ASTDiff.cpp b/clang/lib/Tooling/ASTDiff/ASTDiff.cpp index df00183d417b..ec44ff18a2ce 100644 --- a/clang/lib/Tooling/ASTDiff/ASTDiff.cpp +++ b/clang/lib/Tooling/ASTDiff/ASTDiff.cpp @@ -117,12 +117,12 @@ public: Impl(SyntaxTree *Parent, Stmt *N, ASTContext &AST); template Impl(SyntaxTree *Parent, - typename std::enable_if::value, T>::type *Node, + std::enable_if_t::value, T> *Node, ASTContext &AST) : Impl(Parent, dyn_cast(Node), AST) {} template Impl(SyntaxTree *Parent, - typename std::enable_if::value, T>::type *Node, + std::enable_if_t::value, T> *Node, ASTContext &AST) : Impl(Parent, dyn_cast(Node), AST) {} diff --git a/clang/unittests/Tooling/ASTSelectionTest.cpp b/clang/unittests/Tooling/ASTSelectionTest.cpp index 7ad5148213ce..88988ef44787 100644 --- a/clang/unittests/Tooling/ASTSelectionTest.cpp +++ b/clang/unittests/Tooling/ASTSelectionTest.cpp @@ -101,22 +101,22 @@ void checkDeclName(const SelectedASTNode &Node, StringRef Name) { } template -const SelectedASTNode & -checkNode(const SelectedASTNode &StmtNode, SourceSelectionKind SelectionKind, - unsigned NumChildren = 0, - typename std::enable_if::value, T>::type - *StmtOverloadChecker = nullptr) { +const SelectedASTNode &checkNode( + const SelectedASTNode &StmtNode, SourceSelectionKind SelectionKind, + unsigned NumChildren = 0, + std::enable_if_t::value, T> *StmtOverloadChecker = + nullptr) { checkNodeImpl(isa(StmtNode.Node.get()), StmtNode, SelectionKind, NumChildren); return StmtNode; } template -const SelectedASTNode & -checkNode(const SelectedASTNode &DeclNode, SourceSelectionKind SelectionKind, - unsigned NumChildren = 0, StringRef Name = "", - typename std::enable_if::value, T>::type - *DeclOverloadChecker = nullptr) { +const SelectedASTNode &checkNode( + const SelectedASTNode &DeclNode, SourceSelectionKind SelectionKind, + unsigned NumChildren = 0, StringRef Name = "", + std::enable_if_t::value, T> *DeclOverloadChecker = + nullptr) { checkNodeImpl(isa(DeclNode.Node.get()), DeclNode, SelectionKind, NumChildren); if (!Name.empty()) -- GitLab From 8c3d0d6a5f5a2a521c4cbae7acbad82a49e2a92f Mon Sep 17 00:00:00 2001 From: Cyndy Ishida Date: Tue, 11 Feb 2020 10:31:54 -0800 Subject: [PATCH 041/142] [llvm][TextAPI] add simulators to output Summary: * for <= tbd_v3, simulator platforms appear the same as the real platform and we distinct the difference from the architecture. fixes: rdar://problem/59161559 Reviewers: ributzka, steven_wu Reviewed By: ributzka Subscribers: hiraditya, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74416 --- llvm/lib/TextAPI/MachO/TextStubCommon.cpp | 6 ++ llvm/unittests/TextAPI/TextStubV3Tests.cpp | 72 ++++++++++++++++++++++ 2 files changed, 78 insertions(+) diff --git a/llvm/lib/TextAPI/MachO/TextStubCommon.cpp b/llvm/lib/TextAPI/MachO/TextStubCommon.cpp index e4e58cd66f3f..21be654e130c 100644 --- a/llvm/lib/TextAPI/MachO/TextStubCommon.cpp +++ b/llvm/lib/TextAPI/MachO/TextStubCommon.cpp @@ -62,12 +62,18 @@ void ScalarTraits::output(const PlatformSet &Values, void *IO, case PlatformKind::macOS: OS << "macosx"; break; + case PlatformKind::iOSSimulator: + LLVM_FALLTHROUGH; case PlatformKind::iOS: OS << "ios"; break; + case PlatformKind::watchOSSimulator: + LLVM_FALLTHROUGH; case PlatformKind::watchOS: OS << "watchos"; break; + case PlatformKind::tvOSSimulator: + LLVM_FALLTHROUGH; case PlatformKind::tvOS: OS << "tvos"; break; diff --git a/llvm/unittests/TextAPI/TextStubV3Tests.cpp b/llvm/unittests/TextAPI/TextStubV3Tests.cpp index 0180989ff331..a9e54807cc85 100644 --- a/llvm/unittests/TextAPI/TextStubV3Tests.cpp +++ b/llvm/unittests/TextAPI/TextStubV3Tests.cpp @@ -364,6 +364,78 @@ TEST(TBDv3, Platform_zippered) { stripWhitespace(Buffer.c_str())); } +TEST(TBDv3, Platform_iOSSim) { + static const char tbd_v3_platform_iossim[] = "--- !tapi-tbd-v3\n" + "archs: [ x86_64 ]\n" + "platform: ios\n" + "install-name: Test.dylib\n" + "...\n"; + + auto Result = + TextAPIReader::get(MemoryBufferRef(tbd_v3_platform_iossim, "Test.tbd")); + EXPECT_TRUE(!!Result); + auto Platform = PlatformKind::iOSSimulator; + auto File = std::move(Result.get()); + EXPECT_EQ(FileType::TBD_V3, File->getFileType()); + EXPECT_EQ(File->getPlatforms().size(), 1U); + EXPECT_EQ(Platform, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_v3_platform_iossim), + stripWhitespace(Buffer.c_str())); +} + +TEST(TBDv3, Platform_watchOSSim) { + static const char tbd_v3_platform_watchossim[] = "--- !tapi-tbd-v3\n" + "archs: [ x86_64 ]\n" + "platform: watchos\n" + "install-name: Test.dylib\n" + "...\n"; + + auto Result = TextAPIReader::get( + MemoryBufferRef(tbd_v3_platform_watchossim, "Test.tbd")); + EXPECT_TRUE(!!Result); + auto Platform = PlatformKind::watchOSSimulator; + auto File = std::move(Result.get()); + EXPECT_EQ(FileType::TBD_V3, File->getFileType()); + EXPECT_EQ(File->getPlatforms().size(), 1U); + EXPECT_EQ(Platform, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_v3_platform_watchossim), + stripWhitespace(Buffer.c_str())); +} + +TEST(TBDv3, Platform_tvOSSim) { + static const char tbd_v3_platform_tvossim[] = "--- !tapi-tbd-v3\n" + "archs: [ x86_64 ]\n" + "platform: tvos\n" + "install-name: Test.dylib\n" + "...\n"; + + auto Result = + TextAPIReader::get(MemoryBufferRef(tbd_v3_platform_tvossim, "Test.tbd")); + EXPECT_TRUE(!!Result); + auto File = std::move(Result.get()); + auto Platform = PlatformKind::tvOSSimulator; + EXPECT_EQ(FileType::TBD_V3, File->getFileType()); + EXPECT_EQ(File->getPlatforms().size(), 1U); + EXPECT_EQ(Platform, *File->getPlatforms().begin()); + + SmallString<4096> Buffer; + raw_svector_ostream OS(Buffer); + auto WriteResult = TextAPIWriter::writeToStream(OS, *File); + EXPECT_TRUE(!WriteResult); + EXPECT_EQ(stripWhitespace(tbd_v3_platform_tvossim), + stripWhitespace(Buffer.c_str())); +} + TEST(TBDv3, Swift_1_0) { static const char tbd_v3_swift_1_0[] = "--- !tapi-tbd-v3\n" "archs: [ arm64 ]\n" -- GitLab From 57148e0379d30ecabd2a338c5bb9abbb3a0e314f Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 11 Feb 2020 11:06:21 -0600 Subject: [PATCH 042/142] [Hexagon] Fix ABI info for returning HVX vectors --- clang/lib/CodeGen/TargetInfo.cpp | 64 ++++++++++++++-------------- clang/test/CodeGen/hexagon-hvx-abi.c | 20 +++++++++ 2 files changed, 52 insertions(+), 32 deletions(-) create mode 100644 clang/test/CodeGen/hexagon-hvx-abi.c diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index a3e3a38a1033..29998f361926 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -7486,13 +7486,10 @@ void TCETargetCodeGenInfo::setTargetAttributes( namespace { class HexagonABIInfo : public ABIInfo { - - public: HexagonABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {} private: - ABIArgInfo classifyReturnType(QualType RetTy) const; ABIArgInfo classifyArgumentType(QualType RetTy) const; @@ -7505,14 +7502,14 @@ private: class HexagonTargetCodeGenInfo : public TargetCodeGenInfo { public: HexagonTargetCodeGenInfo(CodeGenTypes &CGT) - :TargetCodeGenInfo(new HexagonABIInfo(CGT)) {} + : TargetCodeGenInfo(new HexagonABIInfo(CGT)) {} int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override { return 29; } }; -} +} // namespace void HexagonABIInfo::computeInfo(CGFunctionInfo &FI) const { if (!getCXXABI().classifyReturnType(FI)) @@ -7527,8 +7524,8 @@ ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const { if (const EnumType *EnumTy = Ty->getAs()) Ty = EnumTy->getDecl()->getIntegerType(); - return (Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) - : ABIArgInfo::getDirect()); + return Ty->isPromotableIntegerType() ? ABIArgInfo::getExtend(Ty) + : ABIArgInfo::getDirect(); } if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) @@ -7539,53 +7536,56 @@ ABIArgInfo HexagonABIInfo::classifyArgumentType(QualType Ty) const { return ABIArgInfo::getIgnore(); uint64_t Size = getContext().getTypeSize(Ty); - if (Size > 64) - return getNaturalAlignIndirect(Ty, /*ByVal=*/true); + if (Size <= 64) { // Pass in the smallest viable integer type. - else if (Size > 32) - return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); - else if (Size > 16) - return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); - else if (Size > 8) - return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); - else - return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); + if (!llvm::isPowerOf2_64(Size)) + Size = llvm::NextPowerOf2(Size); + return ABIArgInfo::getDirect(llvm::Type::getIntNTy(getVMContext(), Size)); + } + return getNaturalAlignIndirect(Ty, /*ByVal=*/true); } ABIArgInfo HexagonABIInfo::classifyReturnType(QualType RetTy) const { if (RetTy->isVoidType()) return ABIArgInfo::getIgnore(); - // Large vector types should be returned via memory. - if (RetTy->isVectorType() && getContext().getTypeSize(RetTy) > 64) - return getNaturalAlignIndirect(RetTy); + const TargetInfo &T = CGT.getTarget(); + uint64_t Size = getContext().getTypeSize(RetTy); + + if (const auto *VecTy = RetTy->getAs()) { + // HVX vectors are returned in vector registers or register pairs. + if (T.hasFeature("hvx")) { + assert(T.hasFeature("hvx-length64b") || T.hasFeature("hvx-length128b")); + uint64_t VecSize = T.hasFeature("hvx-length64b") ? 64*8 : 128*8; + if (Size == VecSize || Size == 2*VecSize) + return ABIArgInfo::getDirectInReg(); + } + + // Large vector types should be returned via memory. + if (Size > 64) + return getNaturalAlignIndirect(RetTy); + } if (!isAggregateTypeForABI(RetTy)) { // Treat an enum type as its underlying type. if (const EnumType *EnumTy = RetTy->getAs()) RetTy = EnumTy->getDecl()->getIntegerType(); - return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy) - : ABIArgInfo::getDirect()); + return RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy) + : ABIArgInfo::getDirect(); } if (isEmptyRecord(getContext(), RetTy, true)) return ABIArgInfo::getIgnore(); - // Aggregates <= 8 bytes are returned in r0; other aggregates + // Aggregates <= 8 bytes are returned in registers, other aggregates // are returned indirectly. - uint64_t Size = getContext().getTypeSize(RetTy); if (Size <= 64) { // Return in the smallest viable integer type. - if (Size <= 8) - return ABIArgInfo::getDirect(llvm::Type::getInt8Ty(getVMContext())); - if (Size <= 16) - return ABIArgInfo::getDirect(llvm::Type::getInt16Ty(getVMContext())); - if (Size <= 32) - return ABIArgInfo::getDirect(llvm::Type::getInt32Ty(getVMContext())); - return ABIArgInfo::getDirect(llvm::Type::getInt64Ty(getVMContext())); + if (!llvm::isPowerOf2_64(Size)) + Size = llvm::NextPowerOf2(Size); + return ABIArgInfo::getDirect(llvm::Type::getIntNTy(getVMContext(), Size)); } - return getNaturalAlignIndirect(RetTy, /*ByVal=*/true); } diff --git a/clang/test/CodeGen/hexagon-hvx-abi.c b/clang/test/CodeGen/hexagon-hvx-abi.c new file mode 100644 index 000000000000..cd70f57e4ffc --- /dev/null +++ b/clang/test/CodeGen/hexagon-hvx-abi.c @@ -0,0 +1,20 @@ +// RUN: %clang_cc1 -triple hexagon -emit-llvm -target-cpu hexagonv66 -target-feature +hvxv66 -target-feature +hvx-length64b -o - %s | FileCheck %s --check-prefix CHECK-HVX64 +// RUN: %clang_cc1 -triple hexagon -emit-llvm -target-cpu hexagonv66 -target-feature +hvxv66 -target-feature +hvx-length128b -o - %s | FileCheck %s --check-prefix CHECK-HVX128 + +typedef long HVX_Vector __attribute__((__vector_size__(__HVX_LENGTH__))) + __attribute__((aligned(__HVX_LENGTH__))); +typedef long HVX_VectorPair __attribute__((__vector_size__(2*__HVX_LENGTH__))) + __attribute__((aligned(__HVX_LENGTH__))); + +// CHECK-HVX64: define {{.*}} <16 x i32> @foo(<16 x i32> %a, <32 x i32> %b) +// CHECK-HVX128: define {{.*}} <32 x i32> @foo(<32 x i32> %a, <64 x i32> %b) +HVX_Vector foo(HVX_Vector a, HVX_VectorPair b) { + return a; +} + +// CHECK-HVX64: define {{.*}} <32 x i32> @bar(<16 x i32> %a, <32 x i32> %b) +// CHECK-HVX128: define {{.*}} <64 x i32> @bar(<32 x i32> %a, <64 x i32> %b) +HVX_VectorPair bar(HVX_Vector a, HVX_VectorPair b) { + return b; +} + -- GitLab From 80d0a137a5aba6998fadb764f1e11cb901aae233 Mon Sep 17 00:00:00 2001 From: Teresa Johnson Date: Thu, 6 Feb 2020 10:54:15 -0800 Subject: [PATCH 043/142] Restore "[WPD/LowerTypeTests] Delay lowering/removal of type tests until after ICP" This restores commit 748bb5a0f1964d20dfb3891b0948ab6c66236c70, along with a fix for a Chromium test suite build issue (and a new test for that case). Differential Revision: https://reviews.llvm.org/D73242 --- llvm/include/llvm/IR/ModuleSummaryIndex.h | 5 +- llvm/include/llvm/IR/ModuleSummaryIndexYAML.h | 1 + llvm/lib/AsmParser/LLParser.cpp | 3 + llvm/lib/IR/AsmWriter.cpp | 2 + llvm/lib/Passes/PassBuilder.cpp | 16 ++++ llvm/lib/Transforms/IPO/LowerTypeTests.cpp | 15 +++- .../lib/Transforms/IPO/PassManagerBuilder.cpp | 12 ++- .../lib/Transforms/IPO/WholeProgramDevirt.cpp | 55 +++++++++----- llvm/test/Bitcode/summary_version.ll | 2 +- llvm/test/Other/new-pm-lto-defaults.ll | 1 + llvm/test/Other/new-pm-thinlto-defaults.ll | 1 + .../new-pm-thinlto-postlink-pgo-defaults.ll | 1 + ...-pm-thinlto-postlink-samplepgo-defaults.ll | 1 + llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll | 50 +++++++++++++ llvm/test/ThinLTO/X86/cfi-unsat.ll | 74 +++++++++++++++++++ .../WholeProgramDevirt/branch-funnel.ll | 6 +- .../WholeProgramDevirt/devirt-single-impl2.ll | 2 +- .../WholeProgramDevirt/export-single-impl.ll | 8 +- .../export-uniform-ret-val.ll | 2 +- .../export-unique-ret-val.ll | 4 +- .../WholeProgramDevirt/export-vcp.ll | 4 +- .../WholeProgramDevirt/import-indir.ll | 2 +- .../WholeProgramDevirt/uniform-retval.ll | 2 +- 23 files changed, 226 insertions(+), 43 deletions(-) create mode 100644 llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll create mode 100644 llvm/test/ThinLTO/X86/cfi-unsat.ll diff --git a/llvm/include/llvm/IR/ModuleSummaryIndex.h b/llvm/include/llvm/IR/ModuleSummaryIndex.h index dab0ad9fe055..69f4bd6313d4 100644 --- a/llvm/include/llvm/IR/ModuleSummaryIndex.h +++ b/llvm/include/llvm/IR/ModuleSummaryIndex.h @@ -833,7 +833,8 @@ struct TypeTestResolution { Single, ///< Single element (last example in "Short Inline Bit Vectors") AllOnes, ///< All-ones bit vector ("Eliminating Bit Vector Checks for /// All-Ones Bit Vectors") - } TheKind = Unsat; + Unknown, ///< Unknown (analysis not performed, don't lower) + } TheKind = Unknown; /// Range of size-1 expressed as a bit width. For example, if the size is in /// range [1,256], this number will be 8. This helps generate the most compact @@ -1027,7 +1028,7 @@ public: // in the way some record are interpreted, like flags for instance. // Note that incrementing this may require changes in both BitcodeReader.cpp // and BitcodeWriter.cpp. - static constexpr uint64_t BitcodeSummaryVersion = 8; + static constexpr uint64_t BitcodeSummaryVersion = 9; // Regular LTO module name for ASM writer static constexpr const char *getRegularLTOModuleName() { diff --git a/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h b/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h index 7dcb455274f8..e51ec67b4c91 100644 --- a/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h +++ b/llvm/include/llvm/IR/ModuleSummaryIndexYAML.h @@ -17,6 +17,7 @@ namespace yaml { template <> struct ScalarEnumerationTraits { static void enumeration(IO &io, TypeTestResolution::Kind &value) { + io.enumCase(value, "Unknown", TypeTestResolution::Unknown); io.enumCase(value, "Unsat", TypeTestResolution::Unsat); io.enumCase(value, "ByteArray", TypeTestResolution::ByteArray); io.enumCase(value, "Inline", TypeTestResolution::Inline); diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index 453c5cdd5410..b22e7cb4f581 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -7660,6 +7660,9 @@ bool LLParser::ParseTypeTestResolution(TypeTestResolution &TTRes) { return true; switch (Lex.getKind()) { + case lltok::kw_unknown: + TTRes.TheKind = TypeTestResolution::Unknown; + break; case lltok::kw_unsat: TTRes.TheKind = TypeTestResolution::Unsat; break; diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 953d7ae49ffc..1a3043b9da08 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -2772,6 +2772,8 @@ static const char *getWholeProgDevirtResByArgKindName( static const char *getTTResKindName(TypeTestResolution::Kind K) { switch (K) { + case TypeTestResolution::Unknown: + return "unknown"; case TypeTestResolution::Unsat: return "unsat"; case TypeTestResolution::ByteArray: diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index d47b56f628d9..72719c77af70 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -751,6 +751,12 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, } MPM.addPass(AttributorPass()); + // Lower type metadata and the type.test intrinsic in the ThinLTO + // post link pipeline after ICP. This is to enable usage of the type + // tests in ICP sequences. + if (Phase == ThinLTOPhase::PostLink) + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); + // Interprocedural constant propagation now that basic cleanup has occurred // and prior to optimizing globals. // FIXME: This position in the pipeline hasn't been carefully considered in @@ -1183,6 +1189,9 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, bool DebugLogging, // metadata and intrinsics. MPM.addPass(WholeProgramDevirtPass(ExportSummary, nullptr)); MPM.addPass(LowerTypeTestsPass(ExportSummary, nullptr)); + // Run a second time to clean up any type tests left behind by WPD for use + // in ICP. + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); return MPM; } @@ -1249,6 +1258,10 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, bool DebugLogging, // The LowerTypeTestsPass needs to run to lower type metadata and the // type.test intrinsics. The pass does nothing if CFI is disabled. MPM.addPass(LowerTypeTestsPass(ExportSummary, nullptr)); + // Run a second time to clean up any type tests left behind by WPD for use + // in ICP (which is performed earlier than this in the regular LTO + // pipeline). + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); return MPM; } @@ -1376,6 +1389,9 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, bool DebugLogging, // to be run at link time if CFI is enabled. This pass does nothing if // CFI is disabled. MPM.addPass(LowerTypeTestsPass(ExportSummary, nullptr)); + // Run a second time to clean up any type tests left behind by WPD for use + // in ICP (which is performed earlier than this in the regular LTO pipeline). + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); // Enable splitting late in the FullLTO post-link pipeline. This is done in // the same stage in the old pass manager (\ref addLateLTOOptimizationPasses). diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp index 6f38a3123932..7c26f156d4c9 100644 --- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp +++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp @@ -735,6 +735,9 @@ static bool isKnownTypeIdMember(Metadata *TypeId, const DataLayout &DL, /// replace the call with. Value *LowerTypeTestsModule::lowerTypeTestCall(Metadata *TypeId, CallInst *CI, const TypeIdLowering &TIL) { + // Delay lowering if the resolution is currently unknown. + if (TIL.TheKind == TypeTestResolution::Unknown) + return nullptr; if (TIL.TheKind == TypeTestResolution::Unsat) return ConstantInt::getFalse(M.getContext()); @@ -1043,8 +1046,10 @@ void LowerTypeTestsModule::importTypeTest(CallInst *CI) { TypeIdLowering TIL = importTypeId(TypeIdStr->getString()); Value *Lowered = lowerTypeTestCall(TypeIdStr, CI, TIL); - CI->replaceAllUsesWith(Lowered); - CI->eraseFromParent(); + if (Lowered) { + CI->replaceAllUsesWith(Lowered); + CI->eraseFromParent(); + } } // ThinLTO backend: the function F has a jump table entry; update this module @@ -1167,8 +1172,10 @@ void LowerTypeTestsModule::lowerTypeTestCalls( for (CallInst *CI : TIUI.CallSites) { ++NumTypeTestCallsLowered; Value *Lowered = lowerTypeTestCall(TypeId, CI, TIL); - CI->replaceAllUsesWith(Lowered); - CI->eraseFromParent(); + if (Lowered) { + CI->replaceAllUsesWith(Lowered); + CI->eraseFromParent(); + } } } } diff --git a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp index 61ec141835c9..6f155dfebb56 100644 --- a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp +++ b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp @@ -504,6 +504,7 @@ void PassManagerBuilder::populateModulePassManager( MPM.add(createBarrierNoopPass()); if (PerformThinLTO) { + MPM.add(createLowerTypeTestsPass(nullptr, nullptr, true)); // Drop available_externally and unreferenced globals. This is necessary // with ThinLTO in order to avoid leaving undefined references to dead // globals in the object file. @@ -537,9 +538,11 @@ void PassManagerBuilder::populateModulePassManager( // inter-module indirect calls. For that we perform indirect call promotion // earlier in the pass pipeline, here before globalopt. Otherwise imported // available_externally functions look unreferenced and are removed. - if (PerformThinLTO) + if (PerformThinLTO) { MPM.add(createPGOIndirectCallPromotionLegacyPass(/*InLTO = */ true, !PGOSampleUse.empty())); + MPM.add(createLowerTypeTestsPass(nullptr, nullptr, true)); + } // For SamplePGO in ThinLTO compile phase, we do not want to unroll loops // as it will change the CFG too much to make the 2nd profile annotation @@ -1060,8 +1063,8 @@ void PassManagerBuilder::populateThinLTOPassManager( PM.add(createVerifierPass()); if (ImportSummary) { - // These passes import type identifier resolutions for whole-program - // devirtualization and CFI. They must run early because other passes may + // This pass imports type identifier resolutions for whole-program + // devirtualization and CFI. It must run early because other passes may // disturb the specific instruction patterns that these passes look for, // creating dependencies on resolutions that may not appear in the summary. // @@ -1109,6 +1112,9 @@ void PassManagerBuilder::populateLTOPassManager(legacy::PassManagerBase &PM) { // control flow integrity mechanisms (-fsanitize=cfi*) and needs to run at // link time if CFI is enabled. The pass does nothing if CFI is disabled. PM.add(createLowerTypeTestsPass(ExportSummary, nullptr)); + // Run a second time to clean up any type tests left behind by WPD for use + // in ICP (which is performed earlier than this in the regular LTO pipeline). + PM.add(createLowerTypeTestsPass(nullptr, nullptr, true)); if (OptLevel != 0) addLateLTOOptimizationPasses(PM); diff --git a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp index bbc1433a22e8..26beb54c205c 100644 --- a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp +++ b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp @@ -510,7 +510,9 @@ struct DevirtModule { bool areRemarksEnabled(); - void scanTypeTestUsers(Function *TypeTestFunc); + void + scanTypeTestUsers(Function *TypeTestFunc, + DenseMap> &TypeIdMap); void scanTypeCheckedLoadUsers(Function *TypeCheckedLoadFunc); void buildTypeIdentifierMap( @@ -1666,7 +1668,9 @@ bool DevirtModule::areRemarksEnabled() { return false; } -void DevirtModule::scanTypeTestUsers(Function *TypeTestFunc) { +void DevirtModule::scanTypeTestUsers( + Function *TypeTestFunc, + DenseMap> &TypeIdMap) { // Find all virtual calls via a virtual table pointer %p under an assumption // of the form llvm.assume(llvm.type.test(%p, %md)). This indicates that %p // points to a member of the type identifier %md. Group calls by (type ID, @@ -1686,10 +1690,10 @@ void DevirtModule::scanTypeTestUsers(Function *TypeTestFunc) { auto &DT = LookupDomTree(*CI->getFunction()); findDevirtualizableCallsForTypeTest(DevirtCalls, Assumes, CI, DT); + Metadata *TypeId = + cast(CI->getArgOperand(1))->getMetadata(); // If we found any, add them to CallSlots. if (!Assumes.empty()) { - Metadata *TypeId = - cast(CI->getArgOperand(1))->getMetadata(); Value *Ptr = CI->getArgOperand(0)->stripPointerCasts(); for (DevirtCallSite Call : DevirtCalls) { // Only add this CallSite if we haven't seen it before. The vtable @@ -1702,6 +1706,13 @@ void DevirtModule::scanTypeTestUsers(Function *TypeTestFunc) { } } + // If we have any uses on type metadata, keep the type test assumes for + // later analysis. Otherwise remove as they aren't useful, and + // LowerTypeTests will think they are Unsat and lower to False, which + // breaks any uses on assumes. + if (TypeIdMap.count(TypeId)) + continue; + // We no longer need the assumes or the type test. for (auto Assume : Assumes) Assume->eraseFromParent(); @@ -1900,8 +1911,13 @@ bool DevirtModule::run() { (!TypeCheckedLoadFunc || TypeCheckedLoadFunc->use_empty())) return false; + // Rebuild type metadata into a map for easy lookup. + std::vector Bits; + DenseMap> TypeIdMap; + buildTypeIdentifierMap(Bits, TypeIdMap); + if (TypeTestFunc && AssumeFunc) - scanTypeTestUsers(TypeTestFunc); + scanTypeTestUsers(TypeTestFunc, TypeIdMap); if (TypeCheckedLoadFunc) scanTypeCheckedLoadUsers(TypeCheckedLoadFunc); @@ -1923,10 +1939,6 @@ bool DevirtModule::run() { return true; } - // Rebuild type metadata into a map for easy lookup. - std::vector Bits; - DenseMap> TypeIdMap; - buildTypeIdentifierMap(Bits, TypeIdMap); if (TypeIdMap.empty()) return true; @@ -1983,14 +1995,18 @@ bool DevirtModule::run() { // function implementation at offset S.first.ByteOffset, and add to // TargetsForSlot. std::vector TargetsForSlot; + WholeProgramDevirtResolution *Res = nullptr; + if (ExportSummary && isa(S.first.TypeID) && + TypeIdMap.count(S.first.TypeID)) + // For any type id used on a global's type metadata, create the type id + // summary resolution regardless of whether we can devirtualize, so that + // lower type tests knows the type id is not Unsat. + Res = &ExportSummary + ->getOrInsertTypeIdSummary( + cast(S.first.TypeID)->getString()) + .WPDRes[S.first.ByteOffset]; if (tryFindVirtualCallTargets(TargetsForSlot, TypeIdMap[S.first.TypeID], S.first.ByteOffset)) { - WholeProgramDevirtResolution *Res = nullptr; - if (ExportSummary && isa(S.first.TypeID)) - Res = &ExportSummary - ->getOrInsertTypeIdSummary( - cast(S.first.TypeID)->getString()) - .WPDRes[S.first.ByteOffset]; if (!trySingleImplDevirt(ExportSummary, TargetsForSlot, S.second, Res)) { DidVirtualConstProp |= @@ -2104,11 +2120,14 @@ void DevirtIndex::run() { std::vector TargetsForSlot; auto TidSummary = ExportSummary.getTypeIdCompatibleVtableSummary(S.first.TypeID); assert(TidSummary); + // Create the type id summary resolution regardlness of whether we can + // devirtualize, so that lower type tests knows the type id is used on + // a global and not Unsat. + WholeProgramDevirtResolution *Res = + &ExportSummary.getOrInsertTypeIdSummary(S.first.TypeID) + .WPDRes[S.first.ByteOffset]; if (tryFindVirtualCallTargets(TargetsForSlot, *TidSummary, S.first.ByteOffset)) { - WholeProgramDevirtResolution *Res = - &ExportSummary.getOrInsertTypeIdSummary(S.first.TypeID) - .WPDRes[S.first.ByteOffset]; if (!trySingleImplDevirt(TargetsForSlot, S.first, S.second, Res, DevirtTargets)) diff --git a/llvm/test/Bitcode/summary_version.ll b/llvm/test/Bitcode/summary_version.ll index 2a67073713c0..98feab6fe2f9 100644 --- a/llvm/test/Bitcode/summary_version.ll +++ b/llvm/test/Bitcode/summary_version.ll @@ -2,7 +2,7 @@ ; RUN: opt -module-summary %s -o - | llvm-bcanalyzer -dump | FileCheck %s ; CHECK: +; CHECK: diff --git a/llvm/test/Other/new-pm-lto-defaults.ll b/llvm/test/Other/new-pm-lto-defaults.ll index 4bfee73720f7..bab23c924d64 100644 --- a/llvm/test/Other/new-pm-lto-defaults.ll +++ b/llvm/test/Other/new-pm-lto-defaults.ll @@ -92,6 +92,7 @@ ; CHECK-O2-NEXT: Running analysis: DemandedBitsAnalysis ; CHECK-O2-NEXT: Running pass: CrossDSOCFIPass ; CHECK-O2-NEXT: Running pass: LowerTypeTestsPass +; CHECK-O-NEXT: Running pass: LowerTypeTestsPass ; CHECK-O2-NEXT: Running pass: ModuleToFunctionPassAdaptor<{{.*}}SimplifyCFGPass> ; CHECK-O2-NEXT: Running pass: EliminateAvailableExternallyPass ; CHECK-O2-NEXT: Running pass: GlobalDCEPass diff --git a/llvm/test/Other/new-pm-thinlto-defaults.ll b/llvm/test/Other/new-pm-thinlto-defaults.ll index 74daa0505b8c..cc2dff646faf 100644 --- a/llvm/test/Other/new-pm-thinlto-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-defaults.ll @@ -80,6 +80,7 @@ ; CHECK-O3-NEXT: Running pass: CallSiteSplittingPass ; CHECK-O-NEXT: Finished llvm::Function pass manager run. ; CHECK-O-NEXT: Running pass: AttributorPass +; CHECK-POSTLINK-O-NEXT: Running pass: LowerTypeTestsPass ; CHECK-O-NEXT: Running pass: IPSCCPPass ; CHECK-O-NEXT: Running pass: CalledValuePropagationPass ; CHECK-O-NEXT: Running pass: GlobalOptPass diff --git a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll index d31767d8fe79..eb6caff8c9fa 100644 --- a/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll @@ -49,6 +49,7 @@ ; CHECK-O3-NEXT: Running pass: CallSiteSplittingPass ; CHECK-O-NEXT: Finished {{.*}}Function pass manager run. ; CHECK-O-NEXT: Running pass: AttributorPass +; CHECK-O-NEXT: Running pass: LowerTypeTestsPass ; CHECK-O-NEXT: Running pass: IPSCCPPass ; CHECK-O-NEXT: Running pass: CalledValuePropagationPass ; CHECK-O-NEXT: Running pass: GlobalOptPass diff --git a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll index d9a2d4b41291..435e29fdff0e 100644 --- a/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll +++ b/llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll @@ -60,6 +60,7 @@ ; CHECK-O-NEXT: Running pass: RequireAnalysisPass<{{.*}}ProfileSummaryAnalysis ; CHECK-O-NEXT: Running pass: PGOIndirectCallPromotion ; CHECK-O-NEXT: Running pass: AttributorPass +; CHECK-O-NEXT: Running pass: LowerTypeTestsPass ; CHECK-O-NEXT: Running pass: IPSCCPPass ; CHECK-O-NEXT: Running pass: CalledValuePropagationPass ; CHECK-O-NEXT: Running pass: GlobalOptPass diff --git a/llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll b/llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll new file mode 100644 index 000000000000..bc7a0e36dfa3 --- /dev/null +++ b/llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll @@ -0,0 +1,50 @@ +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-grtev4-linux-gnu" + +%struct.A = type { i32 (...)** } +%struct.B = type { i32 (...)** } + +@_ZTV1B = linkonce_odr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1nEi to i8*)] }, !type !0 + +$test = comdat any + +; CHECK-IR-LABEL: define i32 @test +define linkonce_odr i32 @test(%struct.A* %obj, i32 %a) comdat { +entry: + %0 = bitcast %struct.A* %obj to i8** + %vtable5 = load i8*, i8** %0 + + %1 = tail call { i8*, i1 } @llvm.type.checked.load(i8* %vtable5, i32 8, metadata !"_ZTS1A") + %2 = extractvalue { i8*, i1 } %1, 1 + br i1 %2, label %cont, label %trap + +trap: + tail call void @llvm.trap() + unreachable + +cont: + %3 = extractvalue { i8*, i1 } %1, 0 + %4 = bitcast i8* %3 to i32 (%struct.A*, i32)* + + ; Check that the call was devirtualized. + ; CHECK-IR: %call = tail call i32 @_ZN1A1nEi + %call = tail call i32 %4(%struct.A* nonnull %obj, i32 %a) + + ret i32 %call +} +; CHECK-IR-LABEL: ret i32 +; CHECK-IR-LABEL: } + +declare { i8*, i1 } @llvm.type.checked.load(i8*, i32, metadata) +declare void @llvm.trap() + +define internal i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) { +entry: + ret i32 0 +} +define internal i32 @_ZN1B1nEi(%struct.B* %this, i32 %a) { +entry: + ret i32 0 +} + +!0 = !{i64 16, !"_ZTS1B"} diff --git a/llvm/test/ThinLTO/X86/cfi-unsat.ll b/llvm/test/ThinLTO/X86/cfi-unsat.ll new file mode 100644 index 000000000000..24e837303c2a --- /dev/null +++ b/llvm/test/ThinLTO/X86/cfi-unsat.ll @@ -0,0 +1,74 @@ +; REQUIRES: x86-registered-target + +; Test CFI devirtualization through the thin link and backend when +; a type id is Unsat (not used on any global's type metadata). +; +; In this test case, the first module is split and will import a resolution +; for its type test. The resolution would be exported by the second +; module, which is set up so that it does not get split (treated as regular +; LTO because it does not have any external globals from which to create +; a unique module ID). We should not actually get any resolution for the +; type id in this case, since no globals include it in their type metadata, +; so the resolution is Unsat and the type.checked.load instructions are +; converted to type tests that evaluate to false. + +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t.o %s +; RUN: opt -thinlto-bc -thinlto-split-lto-unit -o %t1.o %p/Inputs/cfi-unsat.ll + +; RUN: llvm-lto2 run %t.o %t1.o -save-temps -use-new-pm -pass-remarks=. \ +; RUN: -whole-program-visibility \ +; RUN: -o %t3 \ +; RUN: -r=%t.o,test2,px \ +; RUN: -r=%t1.o,_ZTV1B,px \ +; RUN: -r=%t1.o,test,px +; RUN: llvm-dis %t3.index.bc -o - | FileCheck %s --check-prefix=INDEX +; RUN: llvm-dis %t3.0.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-IR0 +; RUN: llvm-dis %t3.1.4.opt.bc -o - | FileCheck %s --check-prefix=CHECK-IR1 + +; INDEX-NOT: "typeid:" + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-grtev4-linux-gnu" + +%struct.A = type { i32 (...)** } + +$test2 = comdat any + +; CHECK-IR0: define weak_odr i32 @test +define linkonce_odr i32 @test2(%struct.A* %obj, i32 %a) comdat { +; CHECK-IR0-NEXT: entry: +entry: +; CHECK-IR0-NEXT: %0 = bitcast + %0 = bitcast %struct.A* %obj to i8** +; CHECK-IR0-NEXT: %vtable5 = + %vtable5 = load i8*, i8** %0 + +; CHECK-IR0-NEXT: tail call void @llvm.trap() +; CHECK-IR0-NEXT: unreachable + + %1 = tail call { i8*, i1 } @llvm.type.checked.load(i8* %vtable5, i32 8, metadata !"_ZTS1A") + %2 = extractvalue { i8*, i1 } %1, 1 + br i1 %2, label %cont, label %trap + +trap: + tail call void @llvm.trap() + unreachable + +cont: + %3 = extractvalue { i8*, i1 } %1, 0 + %4 = bitcast i8* %3 to i32 (%struct.A*, i32)* + + %call = tail call i32 %4(%struct.A* nonnull %obj, i32 %a) + + ret i32 %call +; CHECK-IR0-NEXT: } +} + +; CHECK-IR1: define weak_odr i32 @test2 +; CHECK-IR1-NEXT: entry: +; CHECK-IR1-NEXT: tail call void @llvm.trap() +; CHECK-IR1-NEXT: unreachable +; CHECK-IR1-NEXT: } + +declare { i8*, i1 } @llvm.type.checked.load(i8*, i32, metadata) +declare void @llvm.trap() diff --git a/llvm/test/Transforms/WholeProgramDevirt/branch-funnel.ll b/llvm/test/Transforms/WholeProgramDevirt/branch-funnel.ll index 32d964819fee..bf7c8547f271 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/branch-funnel.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/branch-funnel.ll @@ -10,7 +10,7 @@ ; SUMMARY: TypeIdMap: ; SUMMARY-NEXT: typeid3: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 @@ -23,7 +23,7 @@ ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: typeid1: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 @@ -36,7 +36,7 @@ ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: typeid2: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 diff --git a/llvm/test/Transforms/WholeProgramDevirt/devirt-single-impl2.ll b/llvm/test/Transforms/WholeProgramDevirt/devirt-single-impl2.ll index 63ccfb833d45..7c85114239cf 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/devirt-single-impl2.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/devirt-single-impl2.ll @@ -14,7 +14,7 @@ ; RUN: -wholeprogramdevirt-summary-action=export -o /dev/null 2>&1 | FileCheck %s --check-prefix=MISSING-MODULE ; Check single impl devirtulation in summary -; CHECK: typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: unsat, sizeM1BitWidth: 0), wpdResolutions: ((offset: 0, wpdRes: (kind: singleImpl, singleImplName: "_ZNK1A1fEv"))))) ; guid +; CHECK: typeid: (name: "_ZTS1A", summary: (typeTestRes: (kind: unknown, sizeM1BitWidth: 0), wpdResolutions: ((offset: 0, wpdRes: (kind: singleImpl, singleImplName: "_ZNK1A1fEv"))))) ; guid ; MISSING-MODULE: combined summary should contain Regular LTO module diff --git a/llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll b/llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll index 33ff9e1afe50..861f5f658489 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll @@ -4,7 +4,7 @@ ; SUMMARY: TypeIdMap: ; SUMMARY-NEXT: typeid3: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 @@ -17,7 +17,7 @@ ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: typeid1: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 @@ -30,7 +30,7 @@ ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: typeid2: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 @@ -43,7 +43,7 @@ ; SUMMARY-NEXT: ResByArg: ; SUMMARY-NEXT: typeid4: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 diff --git a/llvm/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll b/llvm/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll index cb2fddd75d1d..634eaa12196e 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll @@ -6,7 +6,7 @@ ; SUMMARY: TypeIdMap: ; SUMMARY-NEXT: typeid4: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 diff --git a/llvm/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll b/llvm/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll index 0f780a387368..7b646341ece2 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll @@ -6,7 +6,7 @@ ; SUMMARY: TypeIdMap: ; SUMMARY-NEXT: typeid3: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 @@ -24,7 +24,7 @@ ; SUMMARY-NEXT: Bit: 0 ; SUMMARY-NEXT: typeid4: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 diff --git a/llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll b/llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll index eb7b36e87dd6..e33abd259625 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll @@ -9,7 +9,7 @@ target datalayout = "e-p:64:64" ; SUMMARY: TypeIdMap: ; SUMMARY-NEXT: typeid3: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 @@ -29,7 +29,7 @@ target datalayout = "e-p:64:64" ; SUMMARY-ARM-NEXT: Bit: 1 ; SUMMARY-NEXT: typeid4: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 diff --git a/llvm/test/Transforms/WholeProgramDevirt/import-indir.ll b/llvm/test/Transforms/WholeProgramDevirt/import-indir.ll index 5c2be7d86296..19ee68be955a 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/import-indir.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/import-indir.ll @@ -32,7 +32,7 @@ ; SUMMARY-NEXT: TypeIdMap: ; SUMMARY-NEXT: typeid1: ; SUMMARY-NEXT: TTRes: -; SUMMARY-NEXT: Kind: Unsat +; SUMMARY-NEXT: Kind: Unknown ; SUMMARY-NEXT: SizeM1BitWidth: 0 ; SUMMARY-NEXT: AlignLog2: 0 ; SUMMARY-NEXT: SizeM1: 0 diff --git a/llvm/test/Transforms/WholeProgramDevirt/uniform-retval.ll b/llvm/test/Transforms/WholeProgramDevirt/uniform-retval.ll index 7626aba24c1a..16f9ef822d6f 100644 --- a/llvm/test/Transforms/WholeProgramDevirt/uniform-retval.ll +++ b/llvm/test/Transforms/WholeProgramDevirt/uniform-retval.ll @@ -25,7 +25,7 @@ define i32 @call(i8* %obj) { %fptr = load i8*, i8** %fptrptr %fptr_casted = bitcast i8* %fptr to i32 (i8*)* %result = call i32 %fptr_casted(i8* %obj) - ; CHECK-NOT: call + ; CHECK-NOT: call i32 % ; CHECK: ret i32 123 ret i32 %result } -- GitLab From 1e0be76e9832e3e02262921abac492e9a52382eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Halkenh=C3=A4user?= Date: Tue, 11 Feb 2020 12:46:31 -0600 Subject: [PATCH 044/142] [Polly] LLVM OpenMP Backend -- Fix "static chunked" scheduling. Static chunked OpenMP scheduling has not been treated correctly. This patch fixes the problem that threads would not process their (work-)chunks as intended. Differential Revision: https://reviews.llvm.org/D61081 --- polly/lib/CodeGen/LoopGeneratorsKMP.cpp | 91 +++++++--- polly/test/Isl/CodeGen/OpenMP/single_loop.ll | 168 ++++++++++++------- 2 files changed, 171 insertions(+), 88 deletions(-) diff --git a/polly/lib/CodeGen/LoopGeneratorsKMP.cpp b/polly/lib/CodeGen/LoopGeneratorsKMP.cpp index e57205107f9a..db753b1f4606 100644 --- a/polly/lib/CodeGen/LoopGeneratorsKMP.cpp +++ b/polly/lib/CodeGen/LoopGeneratorsKMP.cpp @@ -103,28 +103,31 @@ Function *ParallelLoopGeneratorKMP::prepareSubFnDefinition(Function *F) const { // Create a subfunction of the following (preliminary) structure: // -// PrevBB -// | -// v -// HeaderBB -// | _____ -// v v | -// CheckNextBB PreHeaderBB -// |\ | -// | \______/ -// | -// v -// ExitBB +// PrevBB +// | +// v +// HeaderBB +// / | _____ +// / v v | +// / PreHeaderBB | +// | | | +// | v | +// | CheckNextBB | +// \ | \_____/ +// \ | +// v v +// ExitBB // // HeaderBB will hold allocations, loading of variables and kmp-init calls. -// CheckNextBB will check for more work (dynamic) or will be "empty" (static). +// CheckNextBB will check for more work (dynamic / static chunked) or will be +// empty (static non chunked). // If there is more work to do: go to PreHeaderBB, otherwise go to ExitBB. // PreHeaderBB loads the new boundaries (& will lead to the loop body later on). -// Just like CheckNextBB: PreHeaderBB is empty in the static scheduling case. -// ExitBB marks the end of the parallel execution. +// Just like CheckNextBB: PreHeaderBB is (preliminary) empty in the static non +// chunked scheduling case. ExitBB marks the end of the parallel execution. // The possibly empty BasicBlocks will automatically be removed. std::tuple -ParallelLoopGeneratorKMP::createSubFn(Value *StrideNotUsed, +ParallelLoopGeneratorKMP::createSubFn(Value *SequentialLoopStride, AllocaInst *StructData, SetVector Data, ValueMapT &Map) { Function *SubFn = createSubFnDefinition(); @@ -193,7 +196,10 @@ ParallelLoopGeneratorKMP::createSubFn(Value *StrideNotUsed, Value *ChunkSize = ConstantInt::get(LongType, std::max(PollyChunkSize, 1)); - switch (PollyScheduling) { + OMPGeneralSchedulingType Scheduling = + getSchedType(PollyChunkSize, PollyScheduling); + + switch (Scheduling) { case OMPGeneralSchedulingType::Dynamic: case OMPGeneralSchedulingType::Guided: case OMPGeneralSchedulingType::Runtime: @@ -224,24 +230,56 @@ ParallelLoopGeneratorKMP::createSubFn(Value *StrideNotUsed, case OMPGeneralSchedulingType::StaticNonChunked: // "STATIC" scheduling types are handled below { + Builder.CreateAlignedStore(AdjustedUB, UBPtr, Alignment); createCallStaticInit(ID, IsLastPtr, LBPtr, UBPtr, StridePtr, ChunkSize); - LB = Builder.CreateAlignedLoad(LBPtr, Alignment, "polly.indvar.LB"); - UB = Builder.CreateAlignedLoad(UBPtr, Alignment, "polly.indvar.UB"); + Value *ChunkedStride = + Builder.CreateAlignedLoad(StridePtr, Alignment, "polly.kmpc.stride"); - Value *AdjUBOutOfBounds = - Builder.CreateICmp(llvm::CmpInst::Predicate::ICMP_SLT, UB, AdjustedUB, - "polly.adjustedUBOutOfBounds"); + LB = Builder.CreateAlignedLoad(LBPtr, Alignment, "polly.indvar.LB"); + UB = Builder.CreateAlignedLoad(UBPtr, Alignment, "polly.indvar.UB.temp"); - UB = Builder.CreateSelect(AdjUBOutOfBounds, UB, AdjustedUB); + Value *UBInRange = + Builder.CreateICmp(llvm::CmpInst::Predicate::ICMP_SLE, UB, AdjustedUB, + "polly.indvar.UB.inRange"); + UB = Builder.CreateSelect(UBInRange, UB, AdjustedUB, "polly.indvar.UB"); Builder.CreateAlignedStore(UB, UBPtr, Alignment); Value *HasIteration = Builder.CreateICmp( llvm::CmpInst::Predicate::ICMP_SLE, LB, UB, "polly.hasIteration"); Builder.CreateCondBr(HasIteration, PreHeaderBB, ExitBB); + if (Scheduling == OMPGeneralSchedulingType::StaticChunked) { + Builder.SetInsertPoint(PreHeaderBB); + LB = Builder.CreateAlignedLoad(LBPtr, Alignment, + "polly.indvar.LB.entry"); + UB = Builder.CreateAlignedLoad(UBPtr, Alignment, + "polly.indvar.UB.entry"); + } + Builder.SetInsertPoint(CheckNextBB); - Builder.CreateBr(ExitBB); + + if (Scheduling == OMPGeneralSchedulingType::StaticChunked) { + Value *NextLB = + Builder.CreateAdd(LB, ChunkedStride, "polly.indvar.nextLB"); + Value *NextUB = Builder.CreateAdd(UB, ChunkedStride); + + Value *NextUBOutOfBounds = + Builder.CreateICmp(llvm::CmpInst::Predicate::ICMP_SGT, NextUB, + AdjustedUB, "polly.indvar.nextUB.outOfBounds"); + NextUB = Builder.CreateSelect(NextUBOutOfBounds, AdjustedUB, NextUB, + "polly.indvar.nextUB"); + + Builder.CreateAlignedStore(NextLB, LBPtr, Alignment); + Builder.CreateAlignedStore(NextUB, UBPtr, Alignment); + + Value *HasWork = + Builder.CreateICmp(llvm::CmpInst::Predicate::ICMP_SLE, NextLB, + AdjustedUB, "polly.hasWork"); + Builder.CreateCondBr(HasWork, PreHeaderBB, ExitBB); + } else { + Builder.CreateBr(ExitBB); + } Builder.SetInsertPoint(PreHeaderBB); } @@ -251,7 +289,7 @@ ParallelLoopGeneratorKMP::createSubFn(Value *StrideNotUsed, Builder.CreateBr(CheckNextBB); Builder.SetInsertPoint(&*--Builder.GetInsertPoint()); BasicBlock *AfterBB; - Value *IV = createLoop(LB, UB, Stride, Builder, LI, DT, AfterBB, + Value *IV = createLoop(LB, UB, SequentialLoopStride, Builder, LI, DT, AfterBB, ICmpInst::ICMP_SLE, nullptr, true, /* UseGuard */ false); @@ -260,7 +298,8 @@ ParallelLoopGeneratorKMP::createSubFn(Value *StrideNotUsed, // Add code to terminate this subfunction. Builder.SetInsertPoint(ExitBB); // Static (i.e. non-dynamic) scheduling types, are terminated with a fini-call - if (PollyScheduling == OMPGeneralSchedulingType::StaticChunked) { + if (Scheduling == OMPGeneralSchedulingType::StaticChunked || + Scheduling == OMPGeneralSchedulingType::StaticNonChunked) { createCallStaticFini(ID); } Builder.CreateRetVoid(); diff --git a/polly/test/Isl/CodeGen/OpenMP/single_loop.ll b/polly/test/Isl/CodeGen/OpenMP/single_loop.ll index 6de65bd8ad98..38e336a564d2 100644 --- a/polly/test/Isl/CodeGen/OpenMP/single_loop.ll +++ b/polly/test/Isl/CodeGen/OpenMP/single_loop.ll @@ -4,7 +4,8 @@ ; RUN: opt %loadPolly -polly-parallel -polly-parallel-force -polly-import-jscop -polly-ast -analyze < %s | FileCheck %s -check-prefix=AST-STRIDE4 ; RUN: opt %loadPolly -polly-parallel -polly-parallel-force -polly-import-jscop -polly-codegen -S < %s | FileCheck %s -check-prefix=IR-STRIDE4 -; RUN: opt %loadPolly -polly-parallel -polly-parallel-force -polly-codegen -polly-omp-backend=LLVM -polly-scheduling=static -polly-scheduling-chunksize=43 -S -verify-dom-info < %s | FileCheck %s -check-prefix=LIBOMP-IR +; RUN: opt %loadPolly -polly-parallel -polly-parallel-force -polly-codegen -polly-omp-backend=LLVM -polly-scheduling=static -polly-scheduling-chunksize=43 -S -verify-dom-info < %s | FileCheck %s -check-prefix=LIBOMP-IR-STATIC-CHUNKED +; RUN: opt %loadPolly -polly-parallel -polly-parallel-force -polly-codegen -polly-omp-backend=LLVM -polly-scheduling=static -S -verify-dom-info < %s | FileCheck %s -check-prefix=LIBOMP-IR-STATIC ; RUN: opt %loadPolly -polly-parallel -polly-parallel-force -polly-codegen -polly-omp-backend=LLVM -polly-scheduling=dynamic -S -verify-dom-info < %s | FileCheck %s -check-prefix=LIBOMP-IR-DYNAMIC ; RUN: opt %loadPolly -polly-parallel -polly-parallel-force -polly-codegen -polly-omp-backend=LLVM -polly-scheduling=dynamic -polly-scheduling-chunksize=4 -S -verify-dom-info < %s | FileCheck %s -check-prefix=LIBOMP-IR-DYNAMIC-FOUR ; RUN: opt %loadPolly -polly-parallel -polly-parallel-force -polly-import-jscop -polly-codegen -polly-omp-backend=LLVM -S < %s | FileCheck %s -check-prefix=LIBOMP-IR-STRIDE4 @@ -88,67 +89,110 @@ ; IR-STRIDE4: %polly.indvar_next = add nsw i64 %polly.indvar, 4 ; IR-STRIDE4 %polly.adjust_ub = sub i64 %polly.par.UBAdjusted, 4 -; LIBOMP-IR: %struct.ident_t = type { i32, i32, i32, i32, i8* } - -; LIBOMP-IR-LABEL: single_parallel_loop() -; LIBOMP-IR-NEXT: entry -; LIBOMP-IR-NEXT: %polly.par.userContext = alloca - -; LIBOMP-IR-LABEL: polly.parallel.for: -; LIBOMP-IR-NEXT: %polly.par.userContext1 = bitcast {}* %polly.par.userContext to i8* -; LIBOMP-IR-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @.loc.dummy, i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i8*)* @single_parallel_loop_polly_subfn to void (i32*, i32*, ...)*), i64 0, i64 1024, i64 1, i8* %polly.par.userContext1) -; LIBOMP-IR-NEXT: br label %polly.exiting - -; LIBOMP-IR: define internal void @single_parallel_loop_polly_subfn(i32* %polly.kmpc.global_tid, i32* %polly.kmpc.bound_tid, i64 %polly.kmpc.lb, i64 %polly.kmpc.ub, i64 %polly.kmpc.inc, i8* %polly.kmpc.shared) -; LIBOMP-IR-LABEL: polly.par.setup: -; LIBOMP-IR-NEXT: %polly.par.LBPtr = alloca i64 -; LIBOMP-IR-NEXT: %polly.par.UBPtr = alloca i64 -; LIBOMP-IR-NEXT: %polly.par.lastIterPtr = alloca i32 -; LIBOMP-IR-NEXT: %polly.par.StridePtr = alloca i64 -; LIBOMP-IR-NEXT: %polly.par.userContext = bitcast i8* %polly.kmpc.shared -; LIBOMP-IR-NEXT: %polly.par.global_tid = load i32, i32* %polly.kmpc.global_tid -; LIBOMP-IR-NEXT: store i64 %polly.kmpc.lb, i64* %polly.par.LBPtr -; LIBOMP-IR-NEXT: store i64 %polly.kmpc.ub, i64* %polly.par.UBPtr -; LIBOMP-IR-NEXT: store i32 0, i32* %polly.par.lastIterPtr -; LIBOMP-IR-NEXT: store i64 %polly.kmpc.inc, i64* %polly.par.StridePtr -; LIBOMP-IR-NEXT: %polly.indvar.UBAdjusted = add i64 %polly.kmpc.ub, -1 -; LIBOMP-IR-NEXT: call void @__kmpc_for_static_init_{{[4|8]}}(%struct.ident_t* @.loc.dummy{{[.0-9]*}}, i32 %polly.par.global_tid, i32 33, i32* %polly.par.lastIterPtr, i64* %polly.par.LBPtr, i64* %polly.par.UBPtr, i64* %polly.par.StridePtr, i64 1, i64 43) -; LIBOMP-IR-NEXT: %polly.indvar.LB = load i64, i64* %polly.par.LBPtr -; LIBOMP-IR-NEXT: %polly.indvar.UB = load i64, i64* %polly.par.UBPtr -; LIBOMP-IR-NEXT: %polly.adjustedUBOutOfBounds = icmp slt i64 %polly.indvar.UB, %polly.indvar.UBAdjusted -; LIBOMP-IR-NEXT: %{{[0-9]+}} = select i1 %polly.adjustedUBOutOfBounds, i64 %polly.indvar.UB, i64 %polly.indvar.UBAdjusted -; LIBOMP-IR-NEXT: store i64 %{{[0-9]+}}, i64* %polly.par.UBPtr -; LIBOMP-IR-NEXT: %polly.hasIteration = icmp sle i64 %polly.indvar.LB, %{{[0-9]+}} -; LIBOMP-IR: br i1 %polly.hasIteration, label %polly.par.loadIVBounds, label %polly.par.exit - -; LIBOMP-IR-LABEL: polly.par.exit: -; LIBOMP-IR-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @.loc.dummy, i32 %polly.par.global_tid) -; LIBOMP-IR-NEXT: ret void - -; LIBOMP-IR-LABEL: polly.par.checkNext: -; LIBOMP-IR-NEXT: br label %polly.par.exit - -; LIBOMP-IR-LABEL: polly.par.loadIVBounds: -; LIBOMP-IR-NEXT: br label %polly.loop_preheader - -; LIBOMP-IR-LABEL: polly.loop_exit: -; LIBOMP-IR-NEXT: br label %polly.par.checkNext - -; LIBOMP-IR-LABEL: polly.loop_header: -; LIBOMP-IR-NEXT: %polly.indvar = phi i64 [ %polly.indvar.LB, %polly.loop_preheader ], [ %polly.indvar_next, %polly.stmt.S ] -; LIBOMP-IR-NEXT: br label %polly.stmt.S - -; LIBOMP-IR-LABEL: polly.stmt.S: -; LIBOMP-IR-NEXT: %[[gep:[._a-zA-Z0-9]*]] = getelementptr [1024 x float], [1024 x float]* {{.*}}, i64 0, i64 %polly.indvar -; LIBOMP-IR-NEXT: store float 1.000000e+00, float* %[[gep]] -; LIBOMP-IR-NEXT: %polly.indvar_next = add nsw i64 %polly.indvar, %polly.kmpc.inc -; LIBOMP-IR-NEXT: %polly.loop_cond = icmp sle i64 %polly.indvar_next, %{{[0-9]+}} -; LIBOMP-IR-NEXT: br i1 %polly.loop_cond, label %polly.loop_header, label %polly.loop_exit - -; LIBOMP-IR-LABEL: polly.loop_preheader: -; LIBOMP-IR-NEXT: br label %polly.loop_header - -; LIBOMP-IR: attributes #1 = { "polly.skip.fn" } +; LIBOMP-IR-STATIC-CHUNKED: %struct.ident_t = type { i32, i32, i32, i32, i8* } + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: single_parallel_loop() +; LIBOMP-IR-STATIC-CHUNKED-NEXT: entry +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.par.userContext = alloca + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.parallel.for: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.par.userContext1 = bitcast {}* %polly.par.userContext to i8* +; LIBOMP-IR-STATIC-CHUNKED-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @.loc.dummy, i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, i8*)* @single_parallel_loop_polly_subfn to void (i32*, i32*, ...)*), i64 0, i64 1024, i64 1, i8* %polly.par.userContext1) +; LIBOMP-IR-STATIC-CHUNKED-NEXT: br label %polly.exiting + +; LIBOMP-IR-STATIC-CHUNKED: define internal void @single_parallel_loop_polly_subfn(i32* %polly.kmpc.global_tid, i32* %polly.kmpc.bound_tid, i64 %polly.kmpc.lb, i64 %polly.kmpc.ub, i64 %polly.kmpc.inc, i8* %polly.kmpc.shared) +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.par.setup: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.par.LBPtr = alloca i64 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.par.UBPtr = alloca i64 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.par.lastIterPtr = alloca i32 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.par.StridePtr = alloca i64 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.par.userContext = bitcast i8* %polly.kmpc.shared +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.par.global_tid = load i32, i32* %polly.kmpc.global_tid +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store i64 %polly.kmpc.lb, i64* %polly.par.LBPtr +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store i64 %polly.kmpc.ub, i64* %polly.par.UBPtr +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store i32 0, i32* %polly.par.lastIterPtr +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store i64 %polly.kmpc.inc, i64* %polly.par.StridePtr +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.UBAdjusted = add i64 %polly.kmpc.ub, -1 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store i64 %polly.indvar.UBAdjusted, i64* %polly.par.UBPtr, align 8 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: call void @__kmpc_for_static_init_{{[4|8]}}(%struct.ident_t* @.loc.dummy{{[.0-9]*}}, i32 %polly.par.global_tid, i32 33, i32* %polly.par.lastIterPtr, i64* %polly.par.LBPtr, i64* %polly.par.UBPtr, i64* %polly.par.StridePtr, i64 1, i64 43) +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.kmpc.stride = load i64, i64* %polly.par.StridePtr, align 8 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.LB = load i64, i64* %polly.par.LBPtr +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.UB.temp = load i64, i64* %polly.par.UBPtr +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.UB.inRange = icmp sle i64 %polly.indvar.UB.temp, %polly.indvar.UBAdjusted +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.UB = select i1 %polly.indvar.UB.inRange, i64 %polly.indvar.UB.temp, i64 %polly.indvar.UBAdjusted +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store i64 %polly.indvar.UB, i64* %polly.par.UBPtr, align 8 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.hasIteration = icmp sle i64 %polly.indvar.LB, %polly.indvar.UB +; LIBOMP-IR-STATIC-CHUNKED: br i1 %polly.hasIteration, label %polly.par.loadIVBounds, label %polly.par.exit + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.par.exit: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @.loc.dummy, i32 %polly.par.global_tid) +; LIBOMP-IR-STATIC-CHUNKED-NEXT: ret void + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.par.checkNext: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.nextLB = add i64 %polly.indvar.LB.entry, %polly.kmpc.stride +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %{{[0-9]+}} = add i64 %polly.indvar.UB.entry, %polly.kmpc.stride +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.nextUB.outOfBounds = icmp sgt i64 %{{[0-9]+}}, %polly.indvar.UBAdjusted +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.nextUB = select i1 %polly.indvar.nextUB.outOfBounds, i64 %polly.indvar.UBAdjusted, i64 %{{[0-9]+}} +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store i64 %polly.indvar.nextLB, i64* %polly.par.LBPtr, align 8 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store i64 %polly.indvar.nextUB, i64* %polly.par.UBPtr, align 8 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.hasWork = icmp sle i64 %polly.indvar.nextLB, %polly.indvar.UBAdjusted +; LIBOMP-IR-STATIC-CHUNKED-NEXT: br i1 %polly.hasWork, label %polly.par.loadIVBounds, label %polly.par.exit + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.par.loadIVBounds: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.LB.entry = load i64, i64* %polly.par.LBPtr, align 8 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar.UB.entry = load i64, i64* %polly.par.UBPtr, align 8 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: br label %polly.loop_preheader + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.loop_exit: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: br label %polly.par.checkNext + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.loop_header: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar = phi i64 [ %polly.indvar.LB.entry, %polly.loop_preheader ], [ %polly.indvar_next, %polly.stmt.S ] +; LIBOMP-IR-STATIC-CHUNKED-NEXT: br label %polly.stmt.S + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.stmt.S: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %[[gep:[._a-zA-Z0-9]*]] = getelementptr [1024 x float], [1024 x float]* {{.*}}, i64 0, i64 %polly.indvar +; LIBOMP-IR-STATIC-CHUNKED-NEXT: store float 1.000000e+00, float* %[[gep]] +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.indvar_next = add nsw i64 %polly.indvar, 1 +; LIBOMP-IR-STATIC-CHUNKED-NEXT: %polly.loop_cond = icmp sle i64 %polly.indvar_next, %polly.indvar.UB.entry +; LIBOMP-IR-STATIC-CHUNKED-NEXT: br i1 %polly.loop_cond, label %polly.loop_header, label %polly.loop_exit + +; LIBOMP-IR-STATIC-CHUNKED-LABEL: polly.loop_preheader: +; LIBOMP-IR-STATIC-CHUNKED-NEXT: br label %polly.loop_header + +; LIBOMP-IR-STATIC-CHUNKED: attributes #1 = { "polly.skip.fn" } + +; LIBOMP-IR-STATIC: define internal void @single_parallel_loop_polly_subfn(i32* %polly.kmpc.global_tid, i32* %polly.kmpc.bound_tid, i64 %polly.kmpc.lb, i64 %polly.kmpc.ub, i64 %polly.kmpc.inc, i8* %polly.kmpc.shared) +; LIBOMP-IR-STATIC-LABEL: polly.par.setup: +; LIBOMP-IR-STATIC: call void @__kmpc_for_static_init_{{[4|8]}}(%struct.ident_t* @.loc.dummy{{[.0-9]*}}, i32 %polly.par.global_tid, i32 34, i32* %polly.par.lastIterPtr, i64* %polly.par.LBPtr, i64* %polly.par.UBPtr, i64* %polly.par.StridePtr, i64 1, i64 1) +; LIBOMP-IR-STATIC: br i1 %polly.hasIteration, label %polly.par.loadIVBounds, label %polly.par.exit + +; LIBOMP-IR-STATIC-LABEL: polly.par.exit: +; LIBOMP-IR-STATIC-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @.loc.dummy, i32 %polly.par.global_tid) +; LIBOMP-IR-STATIC-NEXT: ret void + +; LIBOMP-IR-STATIC-LABEL: polly.par.checkNext: +; LIBOMP-IR-STATIC-NEXT: br label %polly.par.exit + +; LIBOMP-IR-STATIC-LABEL: polly.par.loadIVBounds: +; LIBOMP-IR-STATIC-NEXT: br label %polly.loop_preheader + +; LIBOMP-IR-STATIC-LABEL: polly.loop_exit: +; LIBOMP-IR-STATIC-NEXT: br label %polly.par.checkNext + +; LIBOMP-IR-STATIC-LABEL: polly.loop_header: +; LIBOMP-IR-STATIC-NEXT: %polly.indvar = phi i64 [ %polly.indvar.LB, %polly.loop_preheader ], [ %polly.indvar_next, %polly.stmt.S ] +; LIBOMP-IR-STATIC-NEXT: br label %polly.stmt.S + +; LIBOMP-IR-STATIC-LABEL: polly.stmt.S: +; LIBOMP-IR-STATIC-NEXT: %[[gep:[._a-zA-Z0-9]*]] = getelementptr [1024 x float], [1024 x float]* {{.*}}, i64 0, i64 %polly.indvar +; LIBOMP-IR-STATIC-NEXT: store float 1.000000e+00, float* %[[gep]] +; LIBOMP-IR-STATIC-NEXT: %polly.indvar_next = add nsw i64 %polly.indvar, 1 +; LIBOMP-IR-STATIC-NEXT: %polly.loop_cond = icmp sle i64 %polly.indvar_next, %polly.indvar.UB +; LIBOMP-IR-STATIC-NEXT: br i1 %polly.loop_cond, label %polly.loop_header, label %polly.loop_exit + +; LIBOMP-IR-STATIC-LABEL: polly.loop_preheader: +; LIBOMP-IR-STATIC-NEXT: br label %polly.loop_header ; LIBOMP-IR-DYNAMIC: call void @__kmpc_dispatch_init_{{[4|8]}}(%struct.ident_t* @.loc.dummy, i32 %polly.par.global_tid, i32 35, i64 %polly.kmpc.lb, i64 %polly.indvar.UBAdjusted, i64 %polly.kmpc.inc, i64 1) ; LIBOMP-IR-DYNAMIC-NEXT: %{{[0-9]+}} = call i32 @__kmpc_dispatch_next_{{[4|8]}}(%struct.ident_t* @.loc.dummy, i32 %polly.par.global_tid, i32* %polly.par.lastIterPtr, i64* %polly.par.LBPtr, i64* %polly.par.UBPtr, i64* %polly.par.StridePtr) -- GitLab From 8888992dee3706d3e84d3533d506c7e971a66382 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Tue, 11 Feb 2020 19:59:21 +0100 Subject: [PATCH 045/142] [lldb][NFC] Test SourceFileCompletion by completing the target line-table argument --- .../test/API/functionalities/completion/TestCompletion.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lldb/test/API/functionalities/completion/TestCompletion.py b/lldb/test/API/functionalities/completion/TestCompletion.py index 26c70c1e7fc9..83c72b34d75f 100644 --- a/lldb/test/API/functionalities/completion/TestCompletion.py +++ b/lldb/test/API/functionalities/completion/TestCompletion.py @@ -348,6 +348,14 @@ class CommandLineCompletionTestCase(TestBase): 'stop-hook', 'variable']) + @skipIfFreeBSD # timing out on the FreeBSD buildbot + def test_target_modules_dump_line_table(self): + """Tests source file completion by completing the line-table argument.""" + self.build() + self.dbg.CreateTarget(self.getBuildArtifact("a.out")) + self.complete_from_to('target modules dump line-table main.cp', + ['main.cpp']) + @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_target_create_dash_co(self): """Test that 'target create --co' completes to 'target variable --core '.""" -- GitLab From 453a8f3af7813121bd3024d83ca75fe3f0f3848b Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Tue, 11 Feb 2020 10:55:14 -0800 Subject: [PATCH 046/142] [AMDGPU] Remove AMDGPURegisterInfo R600 and GCN do not have anything in common in terms of register file organization anymore. Differential Revision: https://reviews.llvm.org/D74426 --- llvm/lib/Target/AMDGPU/AMDGPU.td | 2 +- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp | 1 - .../AMDGPU/AMDGPUInstructionSelector.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp | 82 -------------- llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h | 34 ------ llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td | 21 ---- llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 - .../Disassembler/AMDGPUDisassembler.cpp | 1 - .../AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp | 1 - llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 107 ++++++++++++++---- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 8 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 10 ++ 14 files changed, 101 insertions(+), 170 deletions(-) delete mode 100644 llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp delete mode 100644 llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h delete mode 100644 llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 106480311b5d..9623e1d0f165 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -1175,7 +1175,7 @@ def EnableLateCFGStructurize : Predicate< include "SISchedule.td" include "GCNProcessors.td" include "AMDGPUInstrInfo.td" -include "AMDGPURegisterInfo.td" +include "SIRegisterInfo.td" include "AMDGPURegisterBanks.td" include "AMDGPUInstructions.td" include "SIInstrInfo.td" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index 2abba0cfb727..16a41be23eed 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -16,7 +16,6 @@ #include "AMDGPUISelLowering.h" // For AMDGPUISD #include "AMDGPUInstrInfo.h" #include "AMDGPUPerfHintAnalysis.h" -#include "AMDGPURegisterInfo.h" #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index e0cd2c6b29c6..bf21dedef6dd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -16,7 +16,6 @@ #include "AMDGPU.h" #include "AMDGPUCallLowering.h" #include "AMDGPUFrameLowering.h" -#include "AMDGPURegisterInfo.h" #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" #include "Utils/AMDGPUBaseInfo.h" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp index 9951cbf2326e..6c13bc8599db 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp @@ -13,7 +13,6 @@ //===----------------------------------------------------------------------===// #include "AMDGPUInstrInfo.h" -#include "AMDGPURegisterInfo.h" #include "AMDGPUTargetMachine.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/MachineFrameInfo.h" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index ff7cb9dc2c1a..600988a8080f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -15,7 +15,6 @@ #include "AMDGPUInstrInfo.h" #include "AMDGPUGlobalISelUtils.h" #include "AMDGPURegisterBankInfo.h" -#include "AMDGPURegisterInfo.h" #include "AMDGPUSubtarget.h" #include "AMDGPUTargetMachine.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp deleted file mode 100644 index 148e761125a3..000000000000 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp +++ /dev/null @@ -1,82 +0,0 @@ -//===-- AMDGPURegisterInfo.cpp - AMDGPU Register Information -------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -/// \file -/// Parent TargetRegisterInfo class common to all hw codegen targets. -// -//===----------------------------------------------------------------------===// - -#include "AMDGPURegisterInfo.h" -#include "AMDGPUTargetMachine.h" -#include "SIMachineFunctionInfo.h" -#include "SIRegisterInfo.h" -#include "MCTargetDesc/AMDGPUMCTargetDesc.h" - -using namespace llvm; - -AMDGPURegisterInfo::AMDGPURegisterInfo() : AMDGPUGenRegisterInfo(0) {} - -void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const { - MCRegAliasIterator R(Reg, this, true); - - for (; R.isValid(); ++R) - Reserved.set(*R); -} - -#define GET_REGINFO_TARGET_DESC -#include "AMDGPUGenRegisterInfo.inc" - -// Forced to be here by one .inc -const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs( - const MachineFunction *MF) const { - CallingConv::ID CC = MF->getFunction().getCallingConv(); - switch (CC) { - case CallingConv::C: - case CallingConv::Fast: - case CallingConv::Cold: - return CSR_AMDGPU_HighRegs_SaveList; - default: { - // Dummy to not crash RegisterClassInfo. - static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; - return &NoCalleeSavedReg; - } - } -} - -const MCPhysReg * -SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const { - return nullptr; -} - -const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF, - CallingConv::ID CC) const { - switch (CC) { - case CallingConv::C: - case CallingConv::Fast: - case CallingConv::Cold: - return CSR_AMDGPU_HighRegs_RegMask; - default: - return nullptr; - } -} - -Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const SIFrameLowering *TFI = - MF.getSubtarget().getFrameLowering(); - const SIMachineFunctionInfo *FuncInfo = MF.getInfo(); - return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg() - : FuncInfo->getStackPtrOffsetReg(); -} - -const uint32_t *SIRegisterInfo::getAllVGPRRegMask() const { - return CSR_AMDGPU_AllVGPRs_RegMask; -} - -const uint32_t *SIRegisterInfo::getAllAllocatableSRegMask() const { - return CSR_AMDGPU_AllAllocatableSRegs_RegMask; -} diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h deleted file mode 100644 index e8dc8ba66e1d..000000000000 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h +++ /dev/null @@ -1,34 +0,0 @@ -//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -/// \file -/// TargetRegisterInfo interface that is implemented by all hw codegen -/// targets. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H -#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H - -#define GET_REGINFO_HEADER -#include "AMDGPUGenRegisterInfo.inc" - -namespace llvm { - -class GCNSubtarget; -class TargetInstrInfo; - -struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { - AMDGPURegisterInfo(); - - void reserveRegisterTuples(BitVector &, unsigned Reg) const; -}; - -} // End namespace llvm - -#endif diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td b/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td deleted file mode 100644 index ab71b7aa8a57..000000000000 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.td +++ /dev/null @@ -1,21 +0,0 @@ -//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Tablegen register definitions common to all hw codegen targets. -// -//===----------------------------------------------------------------------===// - -let Namespace = "AMDGPU" in { - -foreach Index = 0-31 in { - def sub#Index : SubRegIndex<32, !shl(Index, 5)>; -} - -} - -include "SIRegisterInfo.td" diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt index b52fcdc53638..bce539dfb6bc 100644 --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -64,7 +64,6 @@ add_llvm_target(AMDGPUCodeGen AMDGPUPromoteAlloca.cpp AMDGPUPropagateAttributes.cpp AMDGPURegisterBankInfo.cpp - AMDGPURegisterInfo.cpp AMDGPURewriteOutArguments.cpp AMDGPUSubtarget.cpp AMDGPUTargetMachine.cpp diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index 8945b576ae78..f563e169ace8 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -18,7 +18,6 @@ #include "Disassembler/AMDGPUDisassembler.h" #include "AMDGPU.h" -#include "AMDGPURegisterInfo.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "SIDefines.h" #include "TargetInfo/AMDGPUTargetInfo.h" diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp index f8ec3c36f019..05c8ff53dd3e 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -13,7 +13,6 @@ //===----------------------------------------------------------------------===// #include "AMDGPU.h" -#include "AMDGPURegisterInfo.h" #include "MCTargetDesc/AMDGPUFixupKinds.h" #include "MCTargetDesc/AMDGPUMCCodeEmitter.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 685fccbaad6b..3b07fc1346e2 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -29,24 +29,8 @@ using namespace llvm; -static bool hasPressureSet(const int *PSets, unsigned PSetID) { - for (unsigned i = 0; PSets[i] != -1; ++i) { - if (PSets[i] == (int)PSetID) - return true; - } - return false; -} - -void SIRegisterInfo::classifyPressureSet(unsigned PSetID, unsigned Reg, - BitVector &PressureSets) const { - for (MCRegUnitIterator U(Reg, this); U.isValid(); ++U) { - const int *PSets = getRegUnitPressureSets(*U); - if (hasPressureSet(PSets, PSetID)) { - PressureSets.set(PSetID); - break; - } - } -} +#define GET_REGINFO_TARGET_DESC +#include "AMDGPUGenRegisterInfo.inc" static cl::opt EnableSpillSGPRToVGPR( "amdgpu-spill-sgpr-to-vgpr", @@ -55,7 +39,7 @@ static cl::opt EnableSpillSGPRToVGPR( cl::init(true)); SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST) : - AMDGPURegisterInfo(), + AMDGPUGenRegisterInfo(0), ST(ST), SGPRPressureSets(getNumRegPressureSets()), VGPRPressureSets(getNumRegPressureSets()), @@ -106,6 +90,83 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST) : AGPRSetID < NumRegPressureSets); } +void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, + unsigned Reg) const { + MCRegAliasIterator R(Reg, this, true); + + for (; R.isValid(); ++R) + Reserved.set(*R); +} + +// Forced to be here by one .inc +const MCPhysReg *SIRegisterInfo::getCalleeSavedRegs( + const MachineFunction *MF) const { + CallingConv::ID CC = MF->getFunction().getCallingConv(); + switch (CC) { + case CallingConv::C: + case CallingConv::Fast: + case CallingConv::Cold: + return CSR_AMDGPU_HighRegs_SaveList; + default: { + // Dummy to not crash RegisterClassInfo. + static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; + return &NoCalleeSavedReg; + } + } +} + +const MCPhysReg * +SIRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const { + return nullptr; +} + +const uint32_t *SIRegisterInfo::getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID CC) const { + switch (CC) { + case CallingConv::C: + case CallingConv::Fast: + case CallingConv::Cold: + return CSR_AMDGPU_HighRegs_RegMask; + default: + return nullptr; + } +} + +Register SIRegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const SIFrameLowering *TFI = + MF.getSubtarget().getFrameLowering(); + const SIMachineFunctionInfo *FuncInfo = MF.getInfo(); + return TFI->hasFP(MF) ? FuncInfo->getFrameOffsetReg() + : FuncInfo->getStackPtrOffsetReg(); +} + +const uint32_t *SIRegisterInfo::getAllVGPRRegMask() const { + return CSR_AMDGPU_AllVGPRs_RegMask; +} + +const uint32_t *SIRegisterInfo::getAllAllocatableSRegMask() const { + return CSR_AMDGPU_AllAllocatableSRegs_RegMask; +} + +static bool hasPressureSet(const int *PSets, unsigned PSetID) { + for (unsigned i = 0; PSets[i] != -1; ++i) { + if (PSets[i] == (int)PSetID) + return true; + } + return false; +} + +void SIRegisterInfo::classifyPressureSet(unsigned PSetID, unsigned Reg, + BitVector &PressureSets) const { + for (MCRegUnitIterator U(Reg, this); U.isValid(); ++U) { + const int *PSets = getRegUnitPressureSets(*U); + if (hasPressureSet(PSets, PSetID)) { + PressureSets.set(PSetID); + break; + } + } +} + // FIXME: TableGen should generate something to make this manageable for all // register classes. At a minimum we could use the opposite of // composeSubRegIndices and go up from the base 32-bit subreg. @@ -1789,7 +1850,7 @@ unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, MF.getFunction()); switch (RC->getID()) { default: - return AMDGPURegisterInfo::getRegPressureLimit(RC, MF); + return AMDGPUGenRegisterInfo::getRegPressureLimit(RC, MF); case AMDGPU::VGPR_32RegClassID: return std::min(ST.getMaxNumVGPRs(Occupancy), ST.getMaxNumVGPRs(MF)); case AMDGPU::SGPR_32RegClassID: @@ -1807,7 +1868,7 @@ unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF, return getRegPressureLimit(&AMDGPU::SGPR_32RegClass, const_cast(MF)); - return AMDGPURegisterInfo::getRegPressureSetLimit(MF, Idx); + return AMDGPUGenRegisterInfo::getRegPressureSetLimit(MF, Idx); } const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { @@ -1815,7 +1876,7 @@ const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { if (hasRegUnit(AMDGPU::M0, RegUnit)) return Empty; - return AMDGPURegisterInfo::getRegUnitPressureSets(RegUnit); + return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit); } unsigned SIRegisterInfo::getReturnAddressReg(const MachineFunction &MF) const { @@ -1899,7 +1960,7 @@ SIRegisterInfo::getRegClass(unsigned RCID) const { case -1: return nullptr; default: - return AMDGPURegisterInfo::getRegClass(RCID); + return AMDGPUGenRegisterInfo::getRegClass(RCID); } } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index ac6d936154d0..cf4cf47bf0fd 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -14,7 +14,9 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H -#include "AMDGPURegisterInfo.h" +#define GET_REGINFO_HEADER +#include "AMDGPUGenRegisterInfo.inc" + #include "SIDefines.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -25,7 +27,7 @@ class LiveIntervals; class MachineRegisterInfo; class SIMachineFunctionInfo; -class SIRegisterInfo final : public AMDGPURegisterInfo { +class SIRegisterInfo final : public AMDGPUGenRegisterInfo { private: const GCNSubtarget &ST; unsigned SGPRSetID; @@ -37,6 +39,8 @@ private: bool SpillSGPRToVGPR; bool isWave32; + void reserveRegisterTuples(BitVector &, unsigned Reg) const; + void classifyPressureSet(unsigned PSetID, unsigned Reg, BitVector &PressureSets) const; public: diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 558e964ec3f0..927cf6eafb52 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -6,6 +6,16 @@ // //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// Subregister declarations +//===----------------------------------------------------------------------===// + +let Namespace = "AMDGPU" in { +foreach Index = 0-31 in { + def sub#Index : SubRegIndex<32, !shl(Index, 5)>; +} +} + //===----------------------------------------------------------------------===// // Helpers //===----------------------------------------------------------------------===// -- GitLab From 9220bbc9091d5804a8321618cf73903c0ec9493f Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Tue, 11 Feb 2020 19:14:15 +0000 Subject: [PATCH 047/142] [gn build] Port 453a8f3af78 --- llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn index 37d08f813a25..d33e4e1e4aee 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn @@ -130,7 +130,6 @@ static_library("LLVMAMDGPUCodeGen") { "AMDGPUPromoteAlloca.cpp", "AMDGPUPropagateAttributes.cpp", "AMDGPURegisterBankInfo.cpp", - "AMDGPURegisterInfo.cpp", "AMDGPURewriteOutArguments.cpp", "AMDGPUSubtarget.cpp", "AMDGPUTargetMachine.cpp", -- GitLab From d7de7ac370181ec0acb42fa2e4085c870868c4e0 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 11 Feb 2020 11:04:47 -0800 Subject: [PATCH 048/142] [X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models Based on uops.info these should have 5 cycle latency as they did on Haswell/Broadwell. I have no additional internal information from Intel. This was also shown as a discrepancy in the spreadsheet that was sent with an early llvm-dev post about llvm-exegesis. It also matches Agner Fog. Differential Revision: https://reviews.llvm.org/D74357 --- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 6 ++-- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 8 ++--- .../X86/SkylakeClient/resources-avx1.s | 32 +++++++++---------- .../X86/SkylakeClient/resources-avx2.s | 32 +++++++++---------- .../X86/SkylakeClient/resources-mmx.s | 12 +++---- .../X86/SkylakeClient/resources-sse1.s | 4 +-- .../X86/SkylakeClient/resources-sse2.s | 24 +++++++------- .../X86/SkylakeClient/resources-sse41.s | 4 +-- .../X86/SkylakeClient/resources-ssse3.s | 16 +++++----- .../X86/SkylakeServer/resources-avx1.s | 32 +++++++++---------- .../X86/SkylakeServer/resources-avx2.s | 32 +++++++++---------- .../X86/SkylakeServer/resources-mmx.s | 12 +++---- .../X86/SkylakeServer/resources-sse1.s | 4 +-- .../X86/SkylakeServer/resources-sse2.s | 24 +++++++------- .../X86/SkylakeServer/resources-sse41.s | 4 +-- .../X86/SkylakeServer/resources-ssse3.s | 16 +++++----- 16 files changed, 131 insertions(+), 131 deletions(-) diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 0950203801af..febef9cc32b9 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -362,9 +362,9 @@ defm : X86WriteResPairUnsupported; defm : SKLWriteResPair; // Vector integer TEST instructions. defm : SKLWriteResPair; defm : X86WriteResPairUnsupported; -defm : SKLWriteResPair; // Vector integer multiply. -defm : SKLWriteResPair; -defm : SKLWriteResPair; +defm : SKLWriteResPair; // Vector integer multiply. +defm : SKLWriteResPair; +defm : SKLWriteResPair; defm : X86WriteResPairUnsupported; defm : SKLWriteResPair; // Vector PMULLD. defm : SKLWriteResPair; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 2556f06c64c3..55893945638e 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -362,10 +362,10 @@ defm : SKXWriteResPair; defm : SKXWriteResPair; // Vector integer TEST instructions. defm : SKXWriteResPair; defm : SKXWriteResPair; -defm : SKXWriteResPair; // Vector integer multiply. -defm : SKXWriteResPair; -defm : SKXWriteResPair; -defm : SKXWriteResPair; +defm : SKXWriteResPair; // Vector integer multiply. +defm : SKXWriteResPair; +defm : SKXWriteResPair; +defm : SKXWriteResPair; defm : SKXWriteResPair; // Vector PMULLD. defm : SKXWriteResPair; defm : SKXWriteResPair; diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s index 62816f790cc2..210f18c13232 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx1.s @@ -1477,10 +1477,10 @@ vzeroupper # CHECK-NEXT: 2 6 1.00 * vpinsrq $1, (%rax), %xmm1, %xmm2 # CHECK-NEXT: 2 2 2.00 vpinsrw $1, %eax, %xmm1, %xmm2 # CHECK-NEXT: 2 6 1.00 * vpinsrw $1, (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmaddubsw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmaddwd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmaddwd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmaddubsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmaddwd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmaddwd (%rax), %xmm1, %xmm2 # CHECK-NEXT: 1 1 0.50 vpmaxsb %xmm0, %xmm1, %xmm2 # CHECK-NEXT: 2 7 0.50 * vpmaxsb (%rax), %xmm1, %xmm2 # CHECK-NEXT: 1 1 0.50 vpmaxsd %xmm0, %xmm1, %xmm2 @@ -1530,20 +1530,20 @@ vzeroupper # CHECK-NEXT: 2 6 1.00 * vpmovzxwd (%rax), %xmm2 # CHECK-NEXT: 1 1 1.00 vpmovzxwq %xmm0, %xmm2 # CHECK-NEXT: 2 6 1.00 * vpmovzxwq (%rax), %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmuldq %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmuldq (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmulhrsw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmulhuw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmulhuw (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmulhw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmulhw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmuldq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmuldq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmulhrsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmulhuw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmulhuw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmulhw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmulhw (%rax), %xmm1, %xmm2 # CHECK-NEXT: 2 10 1.00 vpmulld %xmm0, %xmm1, %xmm2 # CHECK-NEXT: 3 16 1.00 * vpmulld (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmullw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmullw (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmuludq %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmuludq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmullw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmullw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmuludq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmuludq (%rax), %xmm1, %xmm2 # CHECK-NEXT: 1 1 0.33 vpor %xmm0, %xmm1, %xmm2 # CHECK-NEXT: 2 7 0.50 * vpor (%rax), %xmm1, %xmm2 # CHECK-NEXT: 1 3 1.00 vpsadbw %xmm0, %xmm1, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx2.s index 9f6b518da9d8..8072a0611355 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx2.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-avx2.s @@ -588,10 +588,10 @@ vpxor (%rax), %ymm1, %ymm2 # CHECK-NEXT: 4 10 2.00 * vphsubsw (%rax), %ymm1, %ymm2 # CHECK-NEXT: 3 3 2.00 vphsubw %ymm0, %ymm1, %ymm2 # CHECK-NEXT: 4 10 2.00 * vphsubw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmaddubsw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmaddwd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmaddwd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmaddubsw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmaddwd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmaddwd (%rax), %ymm1, %ymm2 # CHECK-NEXT: 2 7 0.50 * vpmaskmovd (%rax), %xmm0, %xmm2 # CHECK-NEXT: 2 8 0.50 * vpmaskmovd (%rax), %ymm0, %ymm2 # CHECK-NEXT: 2 2 1.00 * * vpmaskmovd %xmm0, %xmm1, (%rax) @@ -649,20 +649,20 @@ vpxor (%rax), %ymm1, %ymm2 # CHECK-NEXT: 2 9 1.00 * vpmovzxwd (%rax), %ymm2 # CHECK-NEXT: 1 3 1.00 vpmovzxwq %xmm0, %ymm2 # CHECK-NEXT: 2 10 1.00 * vpmovzxwq (%rax), %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmuldq %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmuldq (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmulhrsw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmulhuw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmulhuw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmulhw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmulhw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmuldq %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmuldq (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmulhrsw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmulhuw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmulhuw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmulhw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmulhw (%rax), %ymm1, %ymm2 # CHECK-NEXT: 2 10 1.00 vpmulld %ymm0, %ymm1, %ymm2 # CHECK-NEXT: 3 17 1.00 * vpmulld (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmullw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmullw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmuludq %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmuludq (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmullw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmullw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmuludq %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmuludq (%rax), %ymm1, %ymm2 # CHECK-NEXT: 1 1 0.33 vpor %ymm0, %ymm1, %ymm2 # CHECK-NEXT: 2 8 0.50 * vpor (%rax), %ymm1, %ymm2 # CHECK-NEXT: 1 3 1.00 vpsadbw %ymm0, %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-mmx.s index 8da7071f0b78..75c49be784eb 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-mmx.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-mmx.s @@ -209,12 +209,12 @@ pxor (%rax), %mm2 # CHECK-NEXT: 2 6 1.00 * pcmpgtd (%rax), %mm2 # CHECK-NEXT: 1 1 1.00 pcmpgtw %mm0, %mm2 # CHECK-NEXT: 2 6 1.00 * pcmpgtw (%rax), %mm2 -# CHECK-NEXT: 1 4 1.00 pmaddwd %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmaddwd (%rax), %mm2 -# CHECK-NEXT: 1 4 1.00 pmulhw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmulhw (%rax), %mm2 -# CHECK-NEXT: 1 4 1.00 pmullw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmullw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmaddwd %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmaddwd (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmullw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmullw (%rax), %mm2 # CHECK-NEXT: 1 1 0.50 por %mm0, %mm2 # CHECK-NEXT: 2 6 0.50 * por (%rax), %mm2 # CHECK-NEXT: 1 1 1.00 pslld $1, %mm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s index 8a2fb55ab734..11557412ea51 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse1.s @@ -280,8 +280,8 @@ xorps (%rax), %xmm2 # CHECK-NEXT: 1 1 1.00 pminub %mm0, %mm2 # CHECK-NEXT: 2 6 1.00 * pminub (%rax), %mm2 # CHECK-NEXT: 1 2 1.00 pmovmskb %mm0, %ecx -# CHECK-NEXT: 1 4 1.00 pmulhuw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmulhuw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhuw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhuw (%rax), %mm2 # CHECK-NEXT: 1 5 0.50 * * prefetcht0 (%rax) # CHECK-NEXT: 1 5 0.50 * * prefetcht1 (%rax) # CHECK-NEXT: 1 5 0.50 * * prefetcht2 (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s index 869a2a4a1c78..7b31b045bc10 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse2.s @@ -563,8 +563,8 @@ xorpd (%rax), %xmm2 # CHECK-NEXT: 2 3 1.00 pextrw $1, %xmm0, %ecx # CHECK-NEXT: 2 2 2.00 pinsrw $1, %eax, %xmm0 # CHECK-NEXT: 2 6 1.00 * pinsrw $1, (%rax), %xmm0 -# CHECK-NEXT: 1 4 0.50 pmaddwd %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmaddwd (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmaddwd %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmaddwd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxsw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxsw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxub %xmm0, %xmm2 @@ -574,16 +574,16 @@ xorpd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminub %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminub (%rax), %xmm2 # CHECK-NEXT: 1 2 1.00 pmovmskb %xmm0, %ecx -# CHECK-NEXT: 1 4 0.50 pmulhuw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmulhuw (%rax), %xmm2 -# CHECK-NEXT: 1 4 0.50 pmulhw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmulhw (%rax), %xmm2 -# CHECK-NEXT: 1 4 0.50 pmullw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmullw (%rax), %xmm2 -# CHECK-NEXT: 1 4 1.00 pmuludq %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmuludq (%rax), %mm2 -# CHECK-NEXT: 1 4 0.50 pmuludq %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmuludq (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmulhuw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmulhuw (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmulhw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmulhw (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmullw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmullw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmuludq %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmuludq (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 pmuludq %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmuludq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.33 por %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * por (%rax), %xmm2 # CHECK-NEXT: 1 3 1.00 psadbw %xmm0, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse41.s index 5789de04c3d9..6e11bb6df8e2 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse41.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-sse41.s @@ -237,8 +237,8 @@ roundss $1, (%rax), %xmm2 # CHECK-NEXT: 2 6 1.00 * pmovzxwd (%rax), %xmm2 # CHECK-NEXT: 1 1 1.00 pmovzxwq %xmm0, %xmm2 # CHECK-NEXT: 2 6 1.00 * pmovzxwq (%rax), %xmm2 -# CHECK-NEXT: 1 4 0.50 pmuldq %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmuldq (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmuldq %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmuldq (%rax), %xmm2 # CHECK-NEXT: 2 10 1.00 pmulld %xmm0, %xmm2 # CHECK-NEXT: 3 16 1.00 * pmulld (%rax), %xmm2 # CHECK-NEXT: 2 3 1.00 ptest %xmm0, %xmm1 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-ssse3.s index a0e2de6e923a..047974f8a6c7 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-ssse3.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-ssse3.s @@ -146,14 +146,14 @@ psignw (%rax), %xmm2 # CHECK-NEXT: 4 8 2.00 * phsubw (%rax), %mm2 # CHECK-NEXT: 3 3 2.00 phsubw %xmm0, %xmm2 # CHECK-NEXT: 4 9 2.00 * phsubw (%rax), %xmm2 -# CHECK-NEXT: 1 4 1.00 pmaddubsw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmaddubsw (%rax), %mm2 -# CHECK-NEXT: 1 4 0.50 pmaddubsw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmaddubsw (%rax), %xmm2 -# CHECK-NEXT: 1 4 1.00 pmulhrsw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmulhrsw (%rax), %mm2 -# CHECK-NEXT: 1 4 0.50 pmulhrsw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmulhrsw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmaddubsw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmaddubsw (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 pmaddubsw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmaddubsw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmulhrsw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhrsw (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 pmulhrsw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmulhrsw (%rax), %xmm2 # CHECK-NEXT: 1 1 1.00 pshufb %mm0, %mm2 # CHECK-NEXT: 2 6 1.00 * pshufb (%rax), %mm2 # CHECK-NEXT: 1 1 1.00 pshufb %xmm0, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s index 97eb3ae44eab..5a8671922f6c 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx1.s @@ -1477,10 +1477,10 @@ vzeroupper # CHECK-NEXT: 2 6 1.00 * vpinsrq $1, (%rax), %xmm1, %xmm2 # CHECK-NEXT: 2 2 2.00 vpinsrw $1, %eax, %xmm1, %xmm2 # CHECK-NEXT: 2 6 1.00 * vpinsrw $1, (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmaddubsw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmaddwd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmaddwd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmaddubsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmaddubsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmaddwd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmaddwd (%rax), %xmm1, %xmm2 # CHECK-NEXT: 1 1 0.50 vpmaxsb %xmm0, %xmm1, %xmm2 # CHECK-NEXT: 2 7 0.50 * vpmaxsb (%rax), %xmm1, %xmm2 # CHECK-NEXT: 1 1 0.50 vpmaxsd %xmm0, %xmm1, %xmm2 @@ -1530,20 +1530,20 @@ vzeroupper # CHECK-NEXT: 2 6 1.00 * vpmovzxwd (%rax), %xmm2 # CHECK-NEXT: 1 1 1.00 vpmovzxwq %xmm0, %xmm2 # CHECK-NEXT: 2 6 1.00 * vpmovzxwq (%rax), %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmuldq %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmuldq (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmulhrsw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmulhuw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmulhuw (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmulhw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmulhw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmuldq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmuldq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmulhrsw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmulhrsw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmulhuw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmulhuw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmulhw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmulhw (%rax), %xmm1, %xmm2 # CHECK-NEXT: 2 10 1.00 vpmulld %xmm0, %xmm1, %xmm2 # CHECK-NEXT: 3 16 1.00 * vpmulld (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmullw %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmullw (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 0.50 vpmuludq %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 10 0.50 * vpmuludq (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmullw %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmullw (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 vpmuludq %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 0.50 * vpmuludq (%rax), %xmm1, %xmm2 # CHECK-NEXT: 1 1 0.33 vpor %xmm0, %xmm1, %xmm2 # CHECK-NEXT: 2 7 0.50 * vpor (%rax), %xmm1, %xmm2 # CHECK-NEXT: 1 3 1.00 vpsadbw %xmm0, %xmm1, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx2.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx2.s index f9c51a18ff7d..546ff0c9dc67 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx2.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-avx2.s @@ -588,10 +588,10 @@ vpxor (%rax), %ymm1, %ymm2 # CHECK-NEXT: 4 10 2.00 * vphsubsw (%rax), %ymm1, %ymm2 # CHECK-NEXT: 3 3 2.00 vphsubw %ymm0, %ymm1, %ymm2 # CHECK-NEXT: 4 10 2.00 * vphsubw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmaddubsw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmaddwd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmaddwd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmaddubsw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmaddubsw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmaddwd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmaddwd (%rax), %ymm1, %ymm2 # CHECK-NEXT: 2 7 0.50 * vpmaskmovd (%rax), %xmm0, %xmm2 # CHECK-NEXT: 2 8 0.50 * vpmaskmovd (%rax), %ymm0, %ymm2 # CHECK-NEXT: 2 2 1.00 * * vpmaskmovd %xmm0, %xmm1, (%rax) @@ -649,20 +649,20 @@ vpxor (%rax), %ymm1, %ymm2 # CHECK-NEXT: 2 9 1.00 * vpmovzxwd (%rax), %ymm2 # CHECK-NEXT: 1 3 1.00 vpmovzxwq %xmm0, %ymm2 # CHECK-NEXT: 2 10 1.00 * vpmovzxwq (%rax), %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmuldq %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmuldq (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmulhrsw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmulhuw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmulhuw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmulhw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmulhw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmuldq %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmuldq (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmulhrsw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmulhrsw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmulhuw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmulhuw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmulhw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmulhw (%rax), %ymm1, %ymm2 # CHECK-NEXT: 2 10 1.00 vpmulld %ymm0, %ymm1, %ymm2 # CHECK-NEXT: 3 17 1.00 * vpmulld (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmullw %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmullw (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 0.50 vpmuludq %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 11 0.50 * vpmuludq (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmullw %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmullw (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 vpmuludq %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 0.50 * vpmuludq (%rax), %ymm1, %ymm2 # CHECK-NEXT: 1 1 0.33 vpor %ymm0, %ymm1, %ymm2 # CHECK-NEXT: 2 8 0.50 * vpor (%rax), %ymm1, %ymm2 # CHECK-NEXT: 1 3 1.00 vpsadbw %ymm0, %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-mmx.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-mmx.s index 91c550c00bf4..befbe68689ff 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-mmx.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-mmx.s @@ -209,12 +209,12 @@ pxor (%rax), %mm2 # CHECK-NEXT: 2 6 1.00 * pcmpgtd (%rax), %mm2 # CHECK-NEXT: 1 1 1.00 pcmpgtw %mm0, %mm2 # CHECK-NEXT: 2 6 1.00 * pcmpgtw (%rax), %mm2 -# CHECK-NEXT: 1 4 1.00 pmaddwd %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmaddwd (%rax), %mm2 -# CHECK-NEXT: 1 4 1.00 pmulhw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmulhw (%rax), %mm2 -# CHECK-NEXT: 1 4 1.00 pmullw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmullw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmaddwd %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmaddwd (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmullw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmullw (%rax), %mm2 # CHECK-NEXT: 1 1 0.50 por %mm0, %mm2 # CHECK-NEXT: 2 6 0.50 * por (%rax), %mm2 # CHECK-NEXT: 1 1 1.00 pslld $1, %mm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s index 7ce873567f51..9754746949ef 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse1.s @@ -280,8 +280,8 @@ xorps (%rax), %xmm2 # CHECK-NEXT: 1 1 1.00 pminub %mm0, %mm2 # CHECK-NEXT: 2 6 1.00 * pminub (%rax), %mm2 # CHECK-NEXT: 1 2 1.00 pmovmskb %mm0, %ecx -# CHECK-NEXT: 1 4 1.00 pmulhuw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmulhuw (%rax), %mm2 +# CHECK-NEXT: 1 5 1.00 pmulhuw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhuw (%rax), %mm2 # CHECK-NEXT: 1 5 0.50 * * prefetcht0 (%rax) # CHECK-NEXT: 1 5 0.50 * * prefetcht1 (%rax) # CHECK-NEXT: 1 5 0.50 * * prefetcht2 (%rax) diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s index 27ecebd9589a..6a09e157a2ff 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse2.s @@ -563,8 +563,8 @@ xorpd (%rax), %xmm2 # CHECK-NEXT: 2 3 1.00 pextrw $1, %xmm0, %ecx # CHECK-NEXT: 2 2 2.00 pinsrw $1, %eax, %xmm0 # CHECK-NEXT: 2 6 1.00 * pinsrw $1, (%rax), %xmm0 -# CHECK-NEXT: 1 4 0.50 pmaddwd %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmaddwd (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmaddwd %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmaddwd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxsw %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pmaxsw (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pmaxub %xmm0, %xmm2 @@ -574,16 +574,16 @@ xorpd (%rax), %xmm2 # CHECK-NEXT: 1 1 0.50 pminub %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * pminub (%rax), %xmm2 # CHECK-NEXT: 1 2 1.00 pmovmskb %xmm0, %ecx -# CHECK-NEXT: 1 4 0.50 pmulhuw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmulhuw (%rax), %xmm2 -# CHECK-NEXT: 1 4 0.50 pmulhw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmulhw (%rax), %xmm2 -# CHECK-NEXT: 1 4 0.50 pmullw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmullw (%rax), %xmm2 -# CHECK-NEXT: 1 4 1.00 pmuludq %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmuludq (%rax), %mm2 -# CHECK-NEXT: 1 4 0.50 pmuludq %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmuludq (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmulhuw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmulhuw (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmulhw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmulhw (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmullw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmullw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmuludq %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmuludq (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 pmuludq %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmuludq (%rax), %xmm2 # CHECK-NEXT: 1 1 0.33 por %xmm0, %xmm2 # CHECK-NEXT: 2 7 0.50 * por (%rax), %xmm2 # CHECK-NEXT: 1 3 1.00 psadbw %xmm0, %xmm2 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse41.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse41.s index 9c4ccd4987a0..15cd09bf7e97 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse41.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-sse41.s @@ -237,8 +237,8 @@ roundss $1, (%rax), %xmm2 # CHECK-NEXT: 2 6 1.00 * pmovzxwd (%rax), %xmm2 # CHECK-NEXT: 1 1 1.00 pmovzxwq %xmm0, %xmm2 # CHECK-NEXT: 2 6 1.00 * pmovzxwq (%rax), %xmm2 -# CHECK-NEXT: 1 4 0.50 pmuldq %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmuldq (%rax), %xmm2 +# CHECK-NEXT: 1 5 0.50 pmuldq %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmuldq (%rax), %xmm2 # CHECK-NEXT: 2 10 1.00 pmulld %xmm0, %xmm2 # CHECK-NEXT: 3 16 1.00 * pmulld (%rax), %xmm2 # CHECK-NEXT: 2 3 1.00 ptest %xmm0, %xmm1 diff --git a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-ssse3.s b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-ssse3.s index bc28ab550b09..c8b5cbb95245 100644 --- a/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-ssse3.s +++ b/llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-ssse3.s @@ -146,14 +146,14 @@ psignw (%rax), %xmm2 # CHECK-NEXT: 4 8 2.00 * phsubw (%rax), %mm2 # CHECK-NEXT: 3 3 2.00 phsubw %xmm0, %xmm2 # CHECK-NEXT: 4 9 2.00 * phsubw (%rax), %xmm2 -# CHECK-NEXT: 1 4 1.00 pmaddubsw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmaddubsw (%rax), %mm2 -# CHECK-NEXT: 1 4 0.50 pmaddubsw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmaddubsw (%rax), %xmm2 -# CHECK-NEXT: 1 4 1.00 pmulhrsw %mm0, %mm2 -# CHECK-NEXT: 2 9 1.00 * pmulhrsw (%rax), %mm2 -# CHECK-NEXT: 1 4 0.50 pmulhrsw %xmm0, %xmm2 -# CHECK-NEXT: 2 10 0.50 * pmulhrsw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmaddubsw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmaddubsw (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 pmaddubsw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmaddubsw (%rax), %xmm2 +# CHECK-NEXT: 1 5 1.00 pmulhrsw %mm0, %mm2 +# CHECK-NEXT: 2 10 1.00 * pmulhrsw (%rax), %mm2 +# CHECK-NEXT: 1 5 0.50 pmulhrsw %xmm0, %xmm2 +# CHECK-NEXT: 2 11 0.50 * pmulhrsw (%rax), %xmm2 # CHECK-NEXT: 1 1 1.00 pshufb %mm0, %mm2 # CHECK-NEXT: 2 6 1.00 * pshufb (%rax), %mm2 # CHECK-NEXT: 1 1 1.00 pshufb %xmm0, %xmm2 -- GitLab From 0cecafd647ccd9d0acc5968d4d6e80c1cbdee275 Mon Sep 17 00:00:00 2001 From: Alina Sbirlea Date: Fri, 7 Feb 2020 10:15:59 -0800 Subject: [PATCH 049/142] [BasicAA] Make BasicAA a cfg pass. Summary: Part of the changes in D44564 made BasicAA not CFG only due to it using PhiAnalysisValues which may have values invalidated. Subsequent patches (rL340613) appear to have addressed this limitation. BasicAA should not be invalidated by non-CFG-altering passes. A concrete example is MemCpyOpt which preserves CFG, but we are testing it invalidates BasicAA. llvm-dev RFC: https://groups.google.com/forum/#!topic/llvm-dev/eSPXuWnNfzM Reviewers: john.brawn, sebpop, hfinkel, brzycki Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74353 --- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 5 +++-- llvm/test/Analysis/BasicAA/phi-values-usage.ll | 6 +++--- llvm/test/Other/opt-O2-pipeline.ll | 6 ------ llvm/test/Other/opt-O3-pipeline.ll | 6 ------ llvm/test/Other/opt-Os-pipeline.ll | 6 ------ 5 files changed, 6 insertions(+), 23 deletions(-) diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp index 894afc643ca0..0cc28efd4489 100644 --- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp +++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp @@ -2059,12 +2059,13 @@ char BasicAAWrapperPass::ID = 0; void BasicAAWrapperPass::anchor() {} INITIALIZE_PASS_BEGIN(BasicAAWrapperPass, "basicaa", - "Basic Alias Analysis (stateless AA impl)", false, true) + "Basic Alias Analysis (stateless AA impl)", true, true) INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker) INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(PhiValuesWrapperPass) INITIALIZE_PASS_END(BasicAAWrapperPass, "basicaa", - "Basic Alias Analysis (stateless AA impl)", false, true) + "Basic Alias Analysis (stateless AA impl)", true, true) FunctionPass *llvm::createBasicAAWrapperPass() { return new BasicAAWrapperPass(); diff --git a/llvm/test/Analysis/BasicAA/phi-values-usage.ll b/llvm/test/Analysis/BasicAA/phi-values-usage.ll index 22743881e939..2ed5ea54283b 100644 --- a/llvm/test/Analysis/BasicAA/phi-values-usage.ll +++ b/llvm/test/Analysis/BasicAA/phi-values-usage.ll @@ -2,7 +2,7 @@ ; RUN: opt -debug-pass=Executions -memdep -instcombine -disable-output < %s 2>&1 | FileCheck %s -check-prefix=CHECK ; Check that phi values is not run when it's not already available, and that -; basicaa is freed after a pass that preserves CFG. +; basicaa is not freed after a pass that preserves CFG, as it preserves CFG. ; CHECK: Executing Pass 'Phi Values Analysis' ; CHECK: Executing Pass 'Basic Alias Analysis (stateless AA impl)' @@ -11,9 +11,9 @@ ; CHECK-MEMCPY-DAG: Freeing Pass 'MemCpy Optimization' ; CHECK-DAG: Freeing Pass 'Phi Values Analysis' ; CHECK-DAG: Freeing Pass 'Memory Dependence Analysis' -; CHECK-DAG: Freeing Pass 'Basic Alias Analysis (stateless AA impl)' +; CHECK-MEMCPY-NOT: Freeing Pass 'Basic Alias Analysis (stateless AA impl)' ; CHECK-NOT: Executing Pass 'Phi Values Analysis' -; CHECK-MEMCPY: Executing Pass 'Basic Alias Analysis (stateless AA impl)' +; CHECK-NOT: Executing Pass 'Basic Alias Analysis (stateless AA impl)' ; CHECK: Executing Pass 'Combine redundant instructions' target datalayout = "p:8:8-n8" diff --git a/llvm/test/Other/opt-O2-pipeline.ll b/llvm/test/Other/opt-O2-pipeline.ll index 4a4cdbb52b99..49144beec3af 100644 --- a/llvm/test/Other/opt-O2-pipeline.ll +++ b/llvm/test/Other/opt-O2-pipeline.ll @@ -70,7 +70,6 @@ ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Early CSE w/ MemorySSA ; CHECK-NEXT: Speculatively execute instructions if target has divergent branches -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Value Information Analysis ; CHECK-NEXT: Jump Threading @@ -134,7 +133,6 @@ ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: MergedLoadStoreMotion ; CHECK-NEXT: Phi Values Analysis -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -149,7 +147,6 @@ ; CHECK-NEXT: Sparse Conditional Constant Propagation ; CHECK-NEXT: Demanded bits analysis ; CHECK-NEXT: Bit-Tracking Dead Code Elimination -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Branch Probability Analysis ; CHECK-NEXT: Lazy Block Frequency Analysis @@ -163,7 +160,6 @@ ; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Dead Store Elimination -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Natural Loop Information @@ -231,7 +227,6 @@ ; CHECK-NEXT: Loop Vectorization ; CHECK-NEXT: Canonicalize natural loops ; CHECK-NEXT: Scalar Evolution Analysis -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Loop Access Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -256,7 +251,6 @@ ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: SLP Vectorizer ; CHECK-NEXT: Optimize scalar/vector ops -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: Combine redundant instructions diff --git a/llvm/test/Other/opt-O3-pipeline.ll b/llvm/test/Other/opt-O3-pipeline.ll index 5a9e85efaa81..cbb90eef5ef7 100644 --- a/llvm/test/Other/opt-O3-pipeline.ll +++ b/llvm/test/Other/opt-O3-pipeline.ll @@ -74,7 +74,6 @@ ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Early CSE w/ MemorySSA ; CHECK-NEXT: Speculatively execute instructions if target has divergent branches -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Value Information Analysis ; CHECK-NEXT: Jump Threading @@ -139,7 +138,6 @@ ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: MergedLoadStoreMotion ; CHECK-NEXT: Phi Values Analysis -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -154,7 +152,6 @@ ; CHECK-NEXT: Sparse Conditional Constant Propagation ; CHECK-NEXT: Demanded bits analysis ; CHECK-NEXT: Bit-Tracking Dead Code Elimination -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Branch Probability Analysis ; CHECK-NEXT: Lazy Block Frequency Analysis @@ -168,7 +165,6 @@ ; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Dead Store Elimination -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Natural Loop Information @@ -236,7 +232,6 @@ ; CHECK-NEXT: Loop Vectorization ; CHECK-NEXT: Canonicalize natural loops ; CHECK-NEXT: Scalar Evolution Analysis -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Loop Access Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -261,7 +256,6 @@ ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: SLP Vectorizer ; CHECK-NEXT: Optimize scalar/vector ops -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: Combine redundant instructions diff --git a/llvm/test/Other/opt-Os-pipeline.ll b/llvm/test/Other/opt-Os-pipeline.ll index 3e25010b6eec..ce3801388b1e 100644 --- a/llvm/test/Other/opt-Os-pipeline.ll +++ b/llvm/test/Other/opt-Os-pipeline.ll @@ -70,7 +70,6 @@ ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Early CSE w/ MemorySSA ; CHECK-NEXT: Speculatively execute instructions if target has divergent branches -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Value Information Analysis ; CHECK-NEXT: Jump Threading @@ -121,7 +120,6 @@ ; CHECK-NEXT: Unroll loops ; CHECK-NEXT: MergedLoadStoreMotion ; CHECK-NEXT: Phi Values Analysis -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -136,7 +134,6 @@ ; CHECK-NEXT: Sparse Conditional Constant Propagation ; CHECK-NEXT: Demanded bits analysis ; CHECK-NEXT: Bit-Tracking Dead Code Elimination -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Lazy Branch Probability Analysis ; CHECK-NEXT: Lazy Block Frequency Analysis @@ -150,7 +147,6 @@ ; CHECK-NEXT: Phi Values Analysis ; CHECK-NEXT: Memory Dependence Analysis ; CHECK-NEXT: Dead Store Elimination -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Memory SSA ; CHECK-NEXT: Natural Loop Information @@ -218,7 +214,6 @@ ; CHECK-NEXT: Loop Vectorization ; CHECK-NEXT: Canonicalize natural loops ; CHECK-NEXT: Scalar Evolution Analysis -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Loop Access Analysis ; CHECK-NEXT: Lazy Branch Probability Analysis @@ -243,7 +238,6 @@ ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: SLP Vectorizer ; CHECK-NEXT: Optimize scalar/vector ops -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: Combine redundant instructions -- GitLab From e83b7b99da2e0385c567cd3883cad66fb5ce271c Mon Sep 17 00:00:00 2001 From: aartbik Date: Tue, 11 Feb 2020 11:09:14 -0800 Subject: [PATCH 050/142] [mlir] [VectorOps] Implement vector.reduce operation Summary: This new operation operates on 1-D vectors and forms the bridge between vector.contract and llvm intrinsics for vector reductions. Reviewers: nicolasvasilache, andydavis1, ftynse Reviewed By: nicolasvasilache Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74370 --- .../mlir/Dialect/VectorOps/VectorOps.td | 33 ++++++++ .../VectorToLLVM/ConvertVectorToLLVM.cpp | 80 +++++++++++++++++-- mlir/lib/Dialect/VectorOps/VectorOps.cpp | 27 +++++++ .../VectorToLLVM/vector-to-llvm.mlir | 44 +++++++++- mlir/test/Dialect/VectorOps/invalid.mlir | 28 +++++++ mlir/test/Dialect/VectorOps/ops.mlir | 34 ++++++++ 6 files changed, 237 insertions(+), 9 deletions(-) diff --git a/mlir/include/mlir/Dialect/VectorOps/VectorOps.td b/mlir/include/mlir/Dialect/VectorOps/VectorOps.td index de7007e3b509..074a6d005376 100644 --- a/mlir/include/mlir/Dialect/VectorOps/VectorOps.td +++ b/mlir/include/mlir/Dialect/VectorOps/VectorOps.td @@ -183,6 +183,39 @@ def Vector_ContractionOp : }]; } +def Vector_ReductionOp : + Vector_Op<"reduction", [NoSideEffect, + PredOpTrait<"source operand and result have same element type", + TCresVTEtIsSameAsOpBase<0, 0>>]>, + Arguments<(ins StrAttr:$kind, AnyVector:$vector)>, + Results<(outs AnyType:$dest)> { + let summary = "reduction operation"; + let description = [{ + Reduces an 1-D vector "horizontally" into a scalar using the given + operation (add/mul/min/max for int/fp and and/or/xor for int only). + Note that these operations are restricted to 1-D vectors to remain + close to the corresponding LLVM intrinsics: + + http://llvm.org/docs/LangRef.html#experimental-vector-reduction-intrinsics + + Examples: + ``` + %1 = vector.reduction "add", %0 : vector<16xf32> into f32 + + %3 = vector.reduction "xor", %2 : vector<4xi32> into i32 + ``` + }]; + let verifier = [{ return ::verify(*this); }]; + let assemblyFormat = [{ + $kind `,` $vector attr-dict `:` type($vector) `into` type($dest) + }]; + let extraClassDeclaration = [{ + VectorType getVectorType() { + return vector().getType().cast(); + } + }]; +} + def Vector_BroadcastOp : Vector_Op<"broadcast", [NoSideEffect, PredOpTrait<"source operand and result have same element type", diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp index a3d724bea834..9fcad2f5063a 100644 --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -124,6 +124,7 @@ static SmallVector getI64SubArray(ArrayAttr arrayAttr, } namespace { + class VectorBroadcastOpConversion : public LLVMOpLowering { public: explicit VectorBroadcastOpConversion(MLIRContext *context, @@ -272,6 +273,73 @@ private: } }; +class VectorReductionOpConversion : public LLVMOpLowering { +public: + explicit VectorReductionOpConversion(MLIRContext *context, + LLVMTypeConverter &typeConverter) + : LLVMOpLowering(vector::ReductionOp::getOperationName(), context, + typeConverter) {} + + PatternMatchResult + matchAndRewrite(Operation *op, ArrayRef operands, + ConversionPatternRewriter &rewriter) const override { + auto reductionOp = cast(op); + auto kind = reductionOp.kind(); + Type eltType = reductionOp.dest().getType(); + Type llvmType = lowering.convertType(eltType); + if (eltType.isInteger(32) || eltType.isInteger(64)) { + // Integer reductions: add/mul/min/max/and/or/xor. + if (kind == "add") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else if (kind == "mul") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else if (kind == "min") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else if (kind == "max") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else if (kind == "and") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else if (kind == "or") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else if (kind == "xor") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else + return matchFailure(); + return matchSuccess(); + + } else if (eltType.isF32() || eltType.isF64()) { + // Floating-point reductions: add/mul/min/max + if (kind == "add") { + Value zero = rewriter.create( + op->getLoc(), llvmType, rewriter.getZeroAttr(eltType)); + rewriter.replaceOpWithNewOp( + op, llvmType, zero, operands[0]); + } else if (kind == "mul") { + Value one = rewriter.create( + op->getLoc(), llvmType, rewriter.getFloatAttr(eltType, 1.0)); + rewriter.replaceOpWithNewOp( + op, llvmType, one, operands[0]); + } else if (kind == "min") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else if (kind == "max") + rewriter.replaceOpWithNewOp( + op, llvmType, operands[0]); + else + return matchFailure(); + return matchSuccess(); + } + return matchFailure(); + } +}; + class VectorShuffleOpConversion : public LLVMOpLowering { public: explicit VectorShuffleOpConversion(MLIRContext *context, @@ -1056,12 +1124,12 @@ void mlir::populateVectorToLLVMConversionPatterns( VectorInsertStridedSliceOpDifferentRankRewritePattern, VectorInsertStridedSliceOpSameRankRewritePattern, VectorStridedSliceOpConversion>(ctx); - patterns.insert( - ctx, converter); + patterns.insert(ctx, converter); } namespace { diff --git a/mlir/lib/Dialect/VectorOps/VectorOps.cpp b/mlir/lib/Dialect/VectorOps/VectorOps.cpp index a987a54f5ea1..b4d7aee70b17 100644 --- a/mlir/lib/Dialect/VectorOps/VectorOps.cpp +++ b/mlir/lib/Dialect/VectorOps/VectorOps.cpp @@ -60,6 +60,33 @@ ArrayAttr vector::getVectorSubscriptAttr(Builder &builder, return builder.getI64ArrayAttr(values); } +//===----------------------------------------------------------------------===// +// ReductionOp +//===----------------------------------------------------------------------===// + +static LogicalResult verify(ReductionOp op) { + // Verify for 1-D vector. + int64_t rank = op.getVectorType().getRank(); + if (rank != 1) + return op.emitOpError("unsupported reduction rank: ") << rank; + + // Verify supported reduction kind. + auto kind = op.kind(); + Type eltType = op.dest().getType(); + if (kind == "add" || kind == "mul" || kind == "min" || kind == "max") { + if (eltType.isF32() || eltType.isF64() || eltType.isInteger(32) || + eltType.isInteger(64)) + return success(); + return op.emitOpError("unsupported reduction type"); + } + if (kind == "and" || kind == "or" || kind == "xor") { + if (eltType.isInteger(32) || eltType.isInteger(64)) + return success(); + return op.emitOpError("unsupported reduction type"); + } + return op.emitOpError("unknown reduction kind: ") << kind; +} + //===----------------------------------------------------------------------===// // ContractionOp //===----------------------------------------------------------------------===// diff --git a/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir b/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir index d1535d59593c..5159031339aa 100644 --- a/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir +++ b/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir @@ -645,7 +645,7 @@ func @vector_fma(%a: vector<8xf32>, %b: vector<2x4xf32>) -> (vector<8xf32>, vect // CHECK: "llvm.intr.fma"(%[[A]], %[[A]], %[[A]]) : // CHECK-SAME: (!llvm<"<8 x float>">, !llvm<"<8 x float>">, !llvm<"<8 x float>">) -> !llvm<"<8 x float>"> %0 = vector.fma %a, %a, %a : vector<8xf32> - + // CHECK: %[[b00:.*]] = llvm.extractvalue %[[B]][0] : !llvm<"[2 x <4 x float>]"> // CHECK: %[[b01:.*]] = llvm.extractvalue %[[B]][0] : !llvm<"[2 x <4 x float>]"> // CHECK: %[[b02:.*]] = llvm.extractvalue %[[B]][0] : !llvm<"[2 x <4 x float>]"> @@ -659,7 +659,45 @@ func @vector_fma(%a: vector<8xf32>, %b: vector<2x4xf32>) -> (vector<8xf32>, vect // CHECK-SAME: (!llvm<"<4 x float>">, !llvm<"<4 x float>">, !llvm<"<4 x float>">) -> !llvm<"<4 x float>"> // CHECK: llvm.insertvalue %[[B1]], {{.*}}[1] : !llvm<"[2 x <4 x float>]"> %1 = vector.fma %b, %b, %b : vector<2x4xf32> - + return %0, %1: vector<8xf32>, vector<2x4xf32> } - + +func @reduce_f32(%arg0: vector<16xf32>) -> f32 { + %0 = vector.reduction "add", %arg0 : vector<16xf32> into f32 + return %0 : f32 +} +// CHECK-LABEL: llvm.func @reduce_f32 +// CHECK-SAME: %[[A:.*]]: !llvm<"<16 x float>"> +// CHECK: %[[C:.*]] = llvm.mlir.constant(0.000000e+00 : f32) : !llvm.float +// CHECK: %[[V:.*]] = "llvm.intr.experimental.vector.reduce.v2.fadd"(%[[C]], %[[A]]) +// CHECK: llvm.return %[[V]] : !llvm.float + +func @reduce_f64(%arg0: vector<16xf64>) -> f64 { + %0 = vector.reduction "add", %arg0 : vector<16xf64> into f64 + return %0 : f64 +} +// CHECK-LABEL: llvm.func @reduce_f64 +// CHECK-SAME: %[[A:.*]]: !llvm<"<16 x double>"> +// CHECK: %[[C:.*]] = llvm.mlir.constant(0.000000e+00 : f64) : !llvm.double +// CHECK: %[[V:.*]] = "llvm.intr.experimental.vector.reduce.v2.fadd"(%[[C]], %[[A]]) +// CHECK: llvm.return %[[V]] : !llvm.double + +func @reduce_i32(%arg0: vector<16xi32>) -> i32 { + %0 = vector.reduction "add", %arg0 : vector<16xi32> into i32 + return %0 : i32 +} +// CHECK-LABEL: llvm.func @reduce_i32 +// CHECK-SAME: %[[A:.*]]: !llvm<"<16 x i32>"> +// CHECK: %[[V:.*]] = "llvm.intr.experimental.vector.reduce.add"(%[[A]]) +// CHECK: llvm.return %[[V]] : !llvm.i32 + +func @reduce_i64(%arg0: vector<16xi64>) -> i64 { + %0 = vector.reduction "add", %arg0 : vector<16xi64> into i64 + return %0 : i64 +} +// CHECK-LABEL: llvm.func @reduce_i64 +// CHECK-SAME: %[[A:.*]]: !llvm<"<16 x i64>"> +// CHECK: %[[V:.*]] = "llvm.intr.experimental.vector.reduce.add"(%[[A]]) +// CHECK: llvm.return %[[V]] : !llvm.i64 + diff --git a/mlir/test/Dialect/VectorOps/invalid.mlir b/mlir/test/Dialect/VectorOps/invalid.mlir index a1fee2cf9a62..2a45820be7b0 100644 --- a/mlir/test/Dialect/VectorOps/invalid.mlir +++ b/mlir/test/Dialect/VectorOps/invalid.mlir @@ -990,3 +990,31 @@ func @shape_cast_different_tuple_sizes( %1 = vector.shape_cast %arg1 : tuple, vector<3x4x2xf32>> to tuple> } + +// ----- + +func @reduce_unknown_kind(%arg0: vector<16xf32>) -> f32 { + // expected-error@+1 {{'vector.reduction' op unknown reduction kind: joho}} + %0 = vector.reduction "joho", %arg0 : vector<16xf32> into f32 +} + +// ----- + +func @reduce_elt_type_mismatch(%arg0: vector<16xf32>) -> i32 { + // expected-error@+1 {{'vector.reduction' op failed to verify that source operand and result have same element type}} + %0 = vector.reduction "add", %arg0 : vector<16xf32> into i32 +} + +// ----- + +func @reduce_unsupported_type(%arg0: vector<16xf32>) -> f32 { + // expected-error@+1 {{'vector.reduction' op unsupported reduction type}} + %0 = vector.reduction "xor", %arg0 : vector<16xf32> into f32 +} + +// ----- + +func @reduce_unsupported_rank(%arg0: vector<4x16xf32>) -> f32 { + // expected-error@+1 {{'vector.reduction' op unsupported reduction rank: 2}} + %0 = vector.reduction "add", %arg0 : vector<4x16xf32> into f32 +} diff --git a/mlir/test/Dialect/VectorOps/ops.mlir b/mlir/test/Dialect/VectorOps/ops.mlir index ff0078310af2..bb5ca6eb8538 100644 --- a/mlir/test/Dialect/VectorOps/ops.mlir +++ b/mlir/test/Dialect/VectorOps/ops.mlir @@ -277,3 +277,37 @@ func @vector_fma(%a: vector<8xf32>, %b: vector<8x4xf32>) { vector.fma %b, %b, %b : vector<8x4xf32> return } + +// CHECK-LABEL: reduce_fp +func @reduce_fp(%arg0: vector<16xf32>) -> f32 { + // CHECK: vector.reduction "add", %{{.*}} : vector<16xf32> into f32 + vector.reduction "add", %arg0 : vector<16xf32> into f32 + // CHECK: vector.reduction "mul", %{{.*}} : vector<16xf32> into f32 + vector.reduction "mul", %arg0 : vector<16xf32> into f32 + // CHECK: vector.reduction "min", %{{.*}} : vector<16xf32> into f32 + vector.reduction "min", %arg0 : vector<16xf32> into f32 + // CHECK: %[[X:.*]] = vector.reduction "max", %{{.*}} : vector<16xf32> into f32 + %0 = vector.reduction "max", %arg0 : vector<16xf32> into f32 + // CHECK: return %[[X]] : f32 + return %0 : f32 +} + +// CHECK-LABEL: reduce_int +func @reduce_int(%arg0: vector<16xi32>) -> i32 { + // CHECK: vector.reduction "add", %{{.*}} : vector<16xi32> into i32 + vector.reduction "add", %arg0 : vector<16xi32> into i32 + // CHECK: vector.reduction "mul", %{{.*}} : vector<16xi32> into i32 + vector.reduction "mul", %arg0 : vector<16xi32> into i32 + // CHECK: vector.reduction "min", %{{.*}} : vector<16xi32> into i32 + vector.reduction "min", %arg0 : vector<16xi32> into i32 + // CHECK: vector.reduction "max", %{{.*}} : vector<16xi32> into i32 + vector.reduction "max", %arg0 : vector<16xi32> into i32 + // CHECK: vector.reduction "and", %{{.*}} : vector<16xi32> into i32 + vector.reduction "and", %arg0 : vector<16xi32> into i32 + // CHECK: vector.reduction "or", %{{.*}} : vector<16xi32> into i32 + vector.reduction "or", %arg0 : vector<16xi32> into i32 + // CHECK: %[[X:.*]] = vector.reduction "xor", %{{.*}} : vector<16xi32> into i32 + %0 = vector.reduction "xor", %arg0 : vector<16xi32> into i32 + // CHECK: return %[[X]] : i32 + return %0 : i32 +} -- GitLab From c69ec6476806147e46bf09b693acb24177982dc2 Mon Sep 17 00:00:00 2001 From: Nathan James Date: Tue, 11 Feb 2020 19:35:41 +0000 Subject: [PATCH 051/142] [clang-tidy] Added check to disable bugprone-infinite-loop on known false condition Summary: Addresses [[ https://bugs.llvm.org/show_bug.cgi?id=44816 | bugprone-infinite-loop false positive with CATCH2 ]] by disabling the check on loops where the condition is known to always eval as false, in other words not a loop. Reviewers: aaron.ballman, alexfh, hokein, gribozavr2, JonasToth Reviewed By: gribozavr2 Subscribers: xazax.hun, cfe-commits Tags: #clang, #clang-tools-extra Differential Revision: https://reviews.llvm.org/D74374 --- .../clang-tidy/bugprone/InfiniteLoopCheck.cpp | 10 ++++++++++ .../clang-tidy/checkers/bugprone-infinite-loop.cpp | 9 +++++++++ 2 files changed, 19 insertions(+) diff --git a/clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp index 5a705376cd4b..00793009ed39 100644 --- a/clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/InfiniteLoopCheck.cpp @@ -152,6 +152,13 @@ static std::string getCondVarNames(const Stmt *Cond) { return Result; } +static bool isKnownFalse(const Expr &Cond, const ASTContext &Ctx) { + bool Result = false; + if (Cond.EvaluateAsBooleanCondition(Result, Ctx)) + return !Result; + return false; +} + void InfiniteLoopCheck::registerMatchers(MatchFinder *Finder) { const auto LoopCondition = allOf( hasCondition( @@ -170,6 +177,9 @@ void InfiniteLoopCheck::check(const MatchFinder::MatchResult &Result) { const auto *LoopStmt = Result.Nodes.getNodeAs("loop-stmt"); const auto *Func = Result.Nodes.getNodeAs("func"); + if (isKnownFalse(*Cond, *Result.Context)) + return; + bool ShouldHaveConditionVariables = true; if (const auto *While = dyn_cast(LoopStmt)) { if (const VarDecl *LoopVarDecl = While->getConditionVariable()) { diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.cpp index d89bdadf0212..427b5f0272b9 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone-infinite-loop.cpp @@ -354,3 +354,12 @@ void lambda_capture() { (*p)++; } while (i < Limit); } + +void evaluatable(bool CondVar) { + for (; false && CondVar;) { + } + while (false && CondVar) { + } + do { + } while (false && CondVar); +} -- GitLab From f65f9d3bc5ab9444a9fcde17bca490bfc1f425b7 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Tue, 11 Feb 2020 20:37:26 +0100 Subject: [PATCH 052/142] [lldb][NFC] Test ModuleCompletion mode by completing the target modules load argument --- .../test/API/functionalities/completion/TestCompletion.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lldb/test/API/functionalities/completion/TestCompletion.py b/lldb/test/API/functionalities/completion/TestCompletion.py index 83c72b34d75f..538c626d60fd 100644 --- a/lldb/test/API/functionalities/completion/TestCompletion.py +++ b/lldb/test/API/functionalities/completion/TestCompletion.py @@ -356,6 +356,14 @@ class CommandLineCompletionTestCase(TestBase): self.complete_from_to('target modules dump line-table main.cp', ['main.cpp']) + @skipIfFreeBSD # timing out on the FreeBSD buildbot + def test_target_modules_load_aout(self): + """Tests modules completion by completing the target modules load argument.""" + self.build() + self.dbg.CreateTarget(self.getBuildArtifact("a.out")) + self.complete_from_to('target modules load a.ou', + ['a.out']) + @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_target_create_dash_co(self): """Test that 'target create --co' completes to 'target variable --core '.""" -- GitLab From 2040831d0566221aa01640123451b7839fc45920 Mon Sep 17 00:00:00 2001 From: Reid Kleckner Date: Wed, 22 Jan 2020 14:31:12 -0800 Subject: [PATCH 053/142] [gn] Paper over Py3 urllib2 incompatibility in gn/get.py Tested with both Python 2.7 and Python 3.7. Reviewed By: thakis Differential Revision: https://reviews.llvm.org/D73234 --- llvm/utils/gn/get.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/llvm/utils/gn/get.py b/llvm/utils/gn/get.py index c39649df78a4..adb8eb7d5715 100755 --- a/llvm/utils/gn/get.py +++ b/llvm/utils/gn/get.py @@ -5,7 +5,12 @@ from __future__ import print_function import io import os -import urllib2 +try: + # In Python 3, we need the module urllib.reqest. In Python 2, this + # functionality was in the urllib2 module. + from urllib import request as urllib_request +except ImportError: + import urllib2 as urllib_request import sys import zipfile @@ -14,7 +19,7 @@ def download_and_unpack(url, output_dir, gn): """Download an archive from url and extract gn from it into output_dir.""" print('downloading %s ...' % url, end='') sys.stdout.flush() - data = urllib2.urlopen(url).read() + data = urllib_request.urlopen(url).read() print(' done') zipfile.ZipFile(io.BytesIO(data)).extract(gn, path=output_dir) -- GitLab From 9c1a88c96457ffde71f13c74fd4d52a77d86cc9f Mon Sep 17 00:00:00 2001 From: diggerlin Date: Tue, 11 Feb 2020 14:41:24 -0500 Subject: [PATCH 054/142] [NFC] Refactor the tuple of symbol information with structure for llvm-objdump SUMMARY: address the comment of https://reviews.llvm.org/D74240#inline-676127 https://reviews.llvm.org/D74240#inline-675875 Reviewers: daltenty, jason liu, xiangling liao Subscribers: wuzish, nemanjai, hiraditya Differential Revision: https://reviews.llvm.org/D74240 --- llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h | 10 +++++++--- llvm/tools/llvm-objdump/llvm-objdump.cpp | 10 ---------- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h b/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h index 05e47deadfc6..737edb3ae21a 100644 --- a/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h +++ b/llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h @@ -22,15 +22,19 @@ struct SymbolInfoTy { StringRef Name; uint8_t Type; - SymbolInfoTy(uint64_t Addr, StringRef Name, uint8_t Type): - Addr(Addr),Name(Name),Type(Type) {}; + SymbolInfoTy(uint64_t Addr, StringRef Name, uint8_t Type) + : Addr(Addr), Name(Name), Type(Type){}; + + friend bool operator<(const SymbolInfoTy &P1, const SymbolInfoTy &P2) { + return std::tie(P1.Addr, P1.Name, P1.Type) < + std::tie(P2.Addr, P2.Name, P2.Type); + } }; using SectionSymbolsTy = std::vector; template class ArrayRef; -class StringRef; class MCContext; class MCInst; class MCSubtargetInfo; diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp index 6719aed44912..a1c37bc8bff4 100644 --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -341,16 +341,6 @@ static StringSet<> DisasmFuncsSet; StringSet<> FoundSectionSet; static StringRef ToolName; -static bool operator<(const SymbolInfoTy& P1 ,const SymbolInfoTy& P2) { - if (P1.Addr < P2.Addr) - return true; - - if (P1.Addr == P2.Addr) - return P1.Name < P2.Name; - - return false; -} - namespace { struct FilterResult { // True if the section should not be skipped. -- GitLab From 417375d785b865b21ca4dc6cb6d70f833fb196cc Mon Sep 17 00:00:00 2001 From: Sterling Augustine Date: Fri, 24 Jan 2020 14:36:22 -0800 Subject: [PATCH 055/142] Allow retrieving source files relative to the compilation directory. Summary: Dwarf stores source-file names the three parts: Prior to this change, the code only allowed retrieving either all three as the absolute path, or just the filename. But many compile-command lines--especially those in hermetic build systems don't specify an absolute path, nor just the filename, but rather the path relative to the compilation directory. This features allows retrieving them in that style. Add tests for path printing styles. Modify createBasicPrologue to handle include directories. Subscribers: aprantl, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73383 --- llvm/include/llvm/DebugInfo/DIContext.h | 7 ++- llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp | 15 ++++-- .../DebugInfo/DWARF/DWARFDebugLineTest.cpp | 47 +++++++++++++++++++ 3 files changed, 63 insertions(+), 6 deletions(-) diff --git a/llvm/include/llvm/DebugInfo/DIContext.h b/llvm/include/llvm/DebugInfo/DIContext.h index fbebfe634b63..b32bb17a1610 100644 --- a/llvm/include/llvm/DebugInfo/DIContext.h +++ b/llvm/include/llvm/DebugInfo/DIContext.h @@ -133,7 +133,12 @@ enum class DINameKind { None, ShortName, LinkageName }; /// Controls which fields of DILineInfo container should be filled /// with data. struct DILineInfoSpecifier { - enum class FileLineInfoKind { None, Default, AbsoluteFilePath }; + enum class FileLineInfoKind { + None, + Default, + RelativeFilePath, + AbsoluteFilePath + }; using FunctionNameKind = DINameKind; FileLineInfoKind FLIKind; diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp index 4ede9ffc2cfa..d3d2c58d3395 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugLine.cpp @@ -1082,7 +1082,7 @@ bool DWARFDebugLine::Prologue::getFileNameByIndex( if (!Name) return false; StringRef FileName = *Name; - if (Kind != FileLineInfoKind::AbsoluteFilePath || + if (Kind == FileLineInfoKind::Default || isPathAbsoluteOnWindowsOrPosix(FileName)) { Result = std::string(FileName); return true; @@ -1099,12 +1099,17 @@ bool DWARFDebugLine::Prologue::getFileNameByIndex( IncludeDir = IncludeDirectories[Entry.DirIdx - 1].getAsCString().getValue(); } - // We may still need to append compilation directory of compile unit. - // We know that FileName is not absolute, the only way to have an - // absolute path at this point would be if IncludeDir is absolute. - if (!CompDir.empty() && !isPathAbsoluteOnWindowsOrPosix(IncludeDir)) + // For absolute paths only, include the compilation directory of compile unit. + // We know that FileName is not absolute, the only way to have an absolute + // path at this point would be if IncludeDir is absolute. + if (Kind == FileLineInfoKind::AbsoluteFilePath && !CompDir.empty() && + !isPathAbsoluteOnWindowsOrPosix(IncludeDir)) sys::path::append(FilePath, Style, CompDir); + assert((Kind == FileLineInfoKind::AbsoluteFilePath || + Kind == FileLineInfoKind::RelativeFilePath) && + "invalid FileLineInfo Kind"); + // sys::path::append skips empty strings. sys::path::append(FilePath, Style, IncludeDir, FileName); Result = std::string(FilePath.str()); diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp b/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp index 5d037463b636..10a9f95a0c69 100644 --- a/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp @@ -917,4 +917,51 @@ TEST_F(DebugLineBasicFixture, ParserPrintsStandardOpcodesWhenRequested) { EXPECT_TRUE(InOutput("0x0000003f: 0c DW_LNS_set_isa (66)\n")) << Output; } +TEST_F(DebugLineBasicFixture, PrintPathsProperly) { + if (!setupGenerator(5)) + return; + + LineTable < = Gen->addLineTable(); + DWARFDebugLine::Prologue P = LT.createBasicPrologue(); + P.IncludeDirectories.push_back( + DWARFFormValue::createFromPValue(DW_FORM_string, "b dir")); + P.FileNames.push_back(DWARFDebugLine::FileNameEntry()); + P.FileNames.back().Name = + DWARFFormValue::createFromPValue(DW_FORM_string, "b file"); + P.FileNames.back().DirIdx = 1; + P.PrologueLength += 14; + LT.setPrologue(P); + generate(); + + auto ExpectedLineTable = Line.getOrParseLineTable(LineData, 0, *Context, + nullptr, RecordRecoverable); + EXPECT_THAT_EXPECTED(ExpectedLineTable, Succeeded()); + std::string Result; + // DWARF 5 stores the compilation directory in two places: the Compilation + // Unit and the directory table entry 0, and implementations are free to use + // one or the other. This copy serves as the one stored in the CU. + StringRef CompDir = "a dir"; + EXPECT_FALSE( + (*ExpectedLineTable) + ->Prologue.getFileNameByIndex( + 1, CompDir, DILineInfoSpecifier::FileLineInfoKind::None, Result)); + EXPECT_TRUE((*ExpectedLineTable) + ->Prologue.getFileNameByIndex( + 1, CompDir, + DILineInfoSpecifier::FileLineInfoKind::Default, Result)); + EXPECT_STREQ(Result.c_str(), "b file"); + EXPECT_TRUE((*ExpectedLineTable) + ->Prologue.getFileNameByIndex( + 1, CompDir, + DILineInfoSpecifier::FileLineInfoKind::RelativeFilePath, + Result)); + EXPECT_STREQ(Result.c_str(), "b dir/b file"); + EXPECT_TRUE((*ExpectedLineTable) + ->Prologue.getFileNameByIndex( + 1, CompDir, + DILineInfoSpecifier::FileLineInfoKind::AbsoluteFilePath, + Result)); + EXPECT_STREQ(Result.c_str(), "a dir/b dir/b file"); +} + } // end anonymous namespace -- GitLab From 11fb68abab9594fd9e9b07a5facf5f5dbf4a4050 Mon Sep 17 00:00:00 2001 From: David Zarzycki Date: Tue, 11 Feb 2020 14:58:05 -0500 Subject: [PATCH 056/142] [libc++] Unbreak test suite (CWG1423) clang 9ce6dc9872be4081fb98f6161c28581e1cbbe7dc drops support for implicit conversion of nullptr_t to bool. From that commit: The C++ rules briefly allowed this, but the rule changed nearly 10 years ago and we never updated our implementation to match. However, we've warned on this by default for a long time, and no other compiler accepts (even as an extension). --- .../std/language.support/support.types/nullptr_t.pass.cpp | 8 -------- 1 file changed, 8 deletions(-) diff --git a/libcxx/test/std/language.support/support.types/nullptr_t.pass.cpp b/libcxx/test/std/language.support/support.types/nullptr_t.pass.cpp index 14ab3c65d024..b12e5c00638b 100644 --- a/libcxx/test/std/language.support/support.types/nullptr_t.pass.cpp +++ b/libcxx/test/std/language.support/support.types/nullptr_t.pass.cpp @@ -56,14 +56,6 @@ void test_comparisons() #pragma clang diagnostic ignored "-Wnull-conversion" #endif void test_nullptr_conversions() { -// GCC does not accept this due to CWG Defect #1423 -// http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#1423 -#if defined(__clang__) - { - bool b = nullptr; - assert(!b); - } -#endif { bool b(nullptr); assert(!b); -- GitLab From 9df0c264d4e34e895208a270045b0e9ed22b658f Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 11 Feb 2020 19:12:48 +0000 Subject: [PATCH 057/142] [AMDGPU] Fix implicit operands for ENTER_WWM pseudo Summary: SIInstrInfo::expandPostRAPseudo converts ENTER_WWM in-place into an S_OR_SAVEEXEC instruction that needs certain implicit operands. Without this patch I get errors like this that make it harder to use -stop-after to bisect the pass pipeline: $ llc -march=amdgcn test/CodeGen/AMDGPU/wqm.ll -stop-after=postrapseudos -o - | sed -E 's/ (from|into) custom "TargetCustom[0-9]+"//' | llc -march=amdgcn -x=mir error: :1295:70: missing implicit register operand 'implicit-def $scc' renamable $sgpr2_sgpr3 = S_OR_SAVEEXEC_B64 -1, implicit-def $exec ^ Note that this error is currently only generated by MIParser but it comes with a FIXME comment: // FIXME: Move the implicit operand verification to the machine verifier. Reviewers: critson, arsenm, rampitec, nhaehnle Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74428 --- llvm/lib/Target/AMDGPU/SIInstructions.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index bb685568f14c..2bb4d5979780 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -169,7 +169,8 @@ def WWM : PseudoInstSI <(outs unknown:$vdst), (ins unknown:$src0)>; } // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] def ENTER_WWM : SPseudoInstSI <(outs SReg_1:$sdst), (ins i64imm:$src0)> { - let Defs = [EXEC]; + let Uses = [EXEC]; + let Defs = [EXEC, SCC]; let hasSideEffects = 0; let mayLoad = 0; let mayStore = 0; -- GitLab From 87303fd9171199ac3082e17d4a91304bf82baeea Mon Sep 17 00:00:00 2001 From: Peter Collingbourne Date: Tue, 11 Feb 2020 11:28:16 -0800 Subject: [PATCH 058/142] scudo: Fix various test failures, mostly on 32-bit. Differential Revision: https://reviews.llvm.org/D74429 --- .../lib/scudo/standalone/size_class_map.h | 14 +++++++-- .../standalone/tests/wrappers_c_test.cpp | 30 +++++++++++++++---- 2 files changed, 36 insertions(+), 8 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/size_class_map.h b/compiler-rt/lib/scudo/standalone/size_class_map.h index 151f4f95f541..3bbd165289e6 100644 --- a/compiler-rt/lib/scudo/standalone/size_class_map.h +++ b/compiler-rt/lib/scudo/standalone/size_class_map.h @@ -24,7 +24,6 @@ inline uptr scaledLog2(uptr Size, uptr ZeroLog, uptr LogBits) { template struct SizeClassMapBase { static u32 getMaxCachedHint(uptr Size) { - DCHECK_LE(Size, (1UL << Config::MaxSizeLog) + Chunk::getHeaderSize()); DCHECK_NE(Size, 0); u32 N; // Force a 32-bit division if the template parameters allow for it. @@ -95,10 +94,17 @@ public: return (Size + MinSize - 1) >> Config::MinSizeLog; return MidClass + 1 + scaledLog2(Size - 1, Config::MidSizeLog, S); } + + static u32 getMaxCachedHint(uptr Size) { + DCHECK_LE(Size, MaxSize); + return Base::getMaxCachedHint(Size); + } }; template class TableSizeClassMap : public SizeClassMapBase { + typedef SizeClassMapBase Base; + static const u8 S = Config::NumBits - 1; static const uptr M = (1UL << S) - 1; static const uptr ClassesSize = @@ -156,8 +162,10 @@ public: return Table.Tab[scaledLog2(Size - 1, Config::MidSizeLog, S)]; } - static void print() {} - static void validate() {} + static u32 getMaxCachedHint(uptr Size) { + DCHECK_LE(Size, MaxSize); + return Base::getMaxCachedHint(Size); + } }; struct AndroidSizeClassConfig { diff --git a/compiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cpp b/compiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cpp index d4ba7d7138ab..8b2bc6ecbd5b 100644 --- a/compiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/wrappers_c_test.cpp @@ -268,10 +268,26 @@ TEST(ScudoWrappersCTest, MallocIterateBoundary) { const size_t BlockDelta = FIRST_32_SECOND_64(8U, 16U); const size_t SpecialSize = PageSize - BlockDelta; - void *P = malloc(SpecialSize); - EXPECT_NE(P, nullptr); - BoundaryP = reinterpret_cast(P); - const uintptr_t Block = BoundaryP - BlockDelta; + // We aren't guaranteed that any size class is exactly a page wide. So we need + // to keep making allocations until we succeed. + // + // With a 16-byte block alignment and 4096-byte page size, each allocation has + // a probability of (1 - (16/4096)) of failing to meet the alignment + // requirements, and the probability of failing 65536 times is + // (1 - (16/4096))^65536 < 10^-112. So if we still haven't succeeded after + // 65536 tries, give up. + uintptr_t Block; + void *P = nullptr; + for (unsigned I = 0; I != 65536; ++I) { + void *PrevP = P; + P = malloc(SpecialSize); + EXPECT_NE(P, nullptr); + *reinterpret_cast(P) = PrevP; + BoundaryP = reinterpret_cast(P); + Block = BoundaryP - BlockDelta; + if ((Block & (PageSize - 1)) == 0U) + break; + } EXPECT_EQ((Block & (PageSize - 1)), 0U); Count = 0U; @@ -281,7 +297,11 @@ TEST(ScudoWrappersCTest, MallocIterateBoundary) { malloc_enable(); EXPECT_EQ(Count, 1U); - free(P); + while (P) { + void *NextP = *reinterpret_cast(P); + free(P); + P = NextP; + } } // We expect heap operations within a disable/enable scope to deadlock. -- GitLab From 257e412762e36de278ffe1488ba3c6f609111632 Mon Sep 17 00:00:00 2001 From: Sterling Augustine Date: Tue, 11 Feb 2020 12:35:10 -0800 Subject: [PATCH 059/142] Update test for windows. --- llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp b/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp index 10a9f95a0c69..b0fdabb433f0 100644 --- a/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp +++ b/llvm/unittests/DebugInfo/DWARF/DWARFDebugLineTest.cpp @@ -955,13 +955,13 @@ TEST_F(DebugLineBasicFixture, PrintPathsProperly) { 1, CompDir, DILineInfoSpecifier::FileLineInfoKind::RelativeFilePath, Result)); - EXPECT_STREQ(Result.c_str(), "b dir/b file"); + EXPECT_THAT(Result.c_str(), MatchesRegex("b dir.b file")); EXPECT_TRUE((*ExpectedLineTable) ->Prologue.getFileNameByIndex( 1, CompDir, DILineInfoSpecifier::FileLineInfoKind::AbsoluteFilePath, Result)); - EXPECT_STREQ(Result.c_str(), "a dir/b dir/b file"); + EXPECT_THAT(Result.c_str(), MatchesRegex("a dir.b dir.b file")); } } // end anonymous namespace -- GitLab From 2d4f80f78aa5c25f19c396bf85d022d009706936 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 11 Feb 2020 15:15:21 -0500 Subject: [PATCH 060/142] [OPENMP50]Full handling of atomic_default_mem_order in requires directive. According to OpenMP 5.0, The atomic_default_mem_order clause specifies the default memory ordering behavior for atomic constructs that must be provided by an implementation. If the default memory ordering is specified as seq_cst, all atomic constructs on which memory-order-clause is not specified behave as if the seq_cst clause appears. If the default memory ordering is specified as relaxed, all atomic constructs on which memory-order-clause is not specified behave as if the relaxed clause appears. If the default memory ordering is specified as acq_rel, atomic constructs on which memory-order-clause is not specified behave as if the release clause appears if the atomic write or atomic update operation is specified, as if the acquire clause appears if the atomic read operation is specified, and as if the acq_rel clause appears if the atomic captured update operation is specified. --- .../clang/Basic/DiagnosticSemaKinds.td | 8 ++-- clang/lib/AST/ASTContext.cpp | 2 + clang/lib/CodeGen/CGDecl.cpp | 2 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 25 ++++++++++-- clang/lib/CodeGen/CGOpenMPRuntime.h | 9 ++++- clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp | 4 +- clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.h | 2 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 35 ++++++++++++++--- clang/lib/Parse/ParseOpenMP.cpp | 2 +- clang/lib/Sema/SemaOpenMP.cpp | 33 +++++++++++++--- clang/lib/Serialization/ASTReaderDecl.cpp | 3 +- .../test/OpenMP/requires_acq_rel_codegen.cpp | 39 +++++++++++++++++++ ...ires_default_atomic_mem_order_messages.cpp | 12 ++++++ .../test/OpenMP/requires_relaxed_codegen.cpp | 39 +++++++++++++++++++ .../test/OpenMP/requires_seq_cst_codegen.cpp | 39 +++++++++++++++++++ .../test/OpenMP/requires_target_messages.cpp | 10 ++--- 16 files changed, 235 insertions(+), 29 deletions(-) create mode 100644 clang/test/OpenMP/requires_acq_rel_codegen.cpp create mode 100644 clang/test/OpenMP/requires_default_atomic_mem_order_messages.cpp create mode 100644 clang/test/OpenMP/requires_relaxed_codegen.cpp create mode 100644 clang/test/OpenMP/requires_seq_cst_codegen.cpp diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index e5714a744692..37f0acf010d6 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -9852,10 +9852,10 @@ def err_omp_requires_clause_redeclaration : Error < "Only one %0 clause can appear on a requires directive in a single translation unit">; def note_omp_requires_previous_clause : Note < "%0 clause previously used here">; -def err_omp_target_before_requires : Error < - "target region encountered before requires directive with '%0' clause">; -def note_omp_requires_encountered_target : Note < - "target previously encountered here">; +def err_omp_directive_before_requires : Error < + "'%0' region encountered before requires directive with '%1' clause">; +def note_omp_requires_encountered_directive : Note < + "'%0' previously encountered here">; def err_omp_invalid_scope : Error < "'#pragma omp %0' directive must appear only in file scope">; def note_omp_invalid_length_on_this_ptr_mapping : Note < diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index c80d3948d003..50a0c3d76da2 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -10041,6 +10041,8 @@ bool ASTContext::DeclMustBeEmitted(const Decl *D) { return true; else if (isa(D)) return true; + else if (isa(D)) + return true; else if (isa(D)) return !D->getDeclContext()->isDependentContext(); else if (isa(D)) diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index 29462592887a..1767e744bac7 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -2537,5 +2537,5 @@ void CodeGenModule::EmitOMPDeclareMapper(const OMPDeclareMapperDecl *D, } void CodeGenModule::EmitOMPRequiresDecl(const OMPRequiresDecl *D) { - getOpenMPRuntime().checkArchForUnifiedAddressing(D); + getOpenMPRuntime().processRequiresDirective(D); } diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 23d49b23a3b4..c3e2e1e0a5d9 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -21,6 +21,7 @@ #include "clang/AST/StmtOpenMP.h" #include "clang/AST/StmtVisitor.h" #include "clang/Basic/BitmaskEnum.h" +#include "clang/Basic/OpenMPKinds.h" #include "clang/CodeGen/ConstantInitBuilder.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SetOperations.h" @@ -30,6 +31,7 @@ #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/GlobalValue.h" #include "llvm/IR/Value.h" +#include "llvm/Support/AtomicOrdering.h" #include "llvm/Support/Format.h" #include "llvm/Support/raw_ostream.h" #include @@ -9784,16 +9786,33 @@ void CGOpenMPRuntime::adjustTargetSpecificDataForLambdas( " Expected target-based directive."); } -void CGOpenMPRuntime::checkArchForUnifiedAddressing( - const OMPRequiresDecl *D) { +void CGOpenMPRuntime::processRequiresDirective(const OMPRequiresDecl *D) { for (const OMPClause *Clause : D->clauselists()) { if (Clause->getClauseKind() == OMPC_unified_shared_memory) { HasRequiresUnifiedSharedMemory = true; - break; + } else if (const auto *AC = + dyn_cast(Clause)) { + switch (AC->getAtomicDefaultMemOrderKind()) { + case OMPC_ATOMIC_DEFAULT_MEM_ORDER_acq_rel: + RequiresAtomicOrdering = llvm::AtomicOrdering::AcquireRelease; + break; + case OMPC_ATOMIC_DEFAULT_MEM_ORDER_seq_cst: + RequiresAtomicOrdering = llvm::AtomicOrdering::SequentiallyConsistent; + break; + case OMPC_ATOMIC_DEFAULT_MEM_ORDER_relaxed: + RequiresAtomicOrdering = llvm::AtomicOrdering::Monotonic; + break; + case OMPC_ATOMIC_DEFAULT_MEM_ORDER_unknown: + break; + } } } } +llvm::AtomicOrdering CGOpenMPRuntime::getDefaultMemoryOrdering() const { + return RequiresAtomicOrdering; +} + bool CGOpenMPRuntime::hasAllocateAttributeForGlobalVar(const VarDecl *VD, LangAS &AS) { if (!VD || !VD->hasAttr()) diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h index a4fe15eee26a..f559e0d22574 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.h +++ b/clang/lib/CodeGen/CGOpenMPRuntime.h @@ -26,6 +26,7 @@ #include "llvm/Frontend/OpenMP/OMPConstants.h" #include "llvm/IR/Function.h" #include "llvm/IR/ValueHandle.h" +#include "llvm/Support/AtomicOrdering.h" namespace llvm { class ArrayType; @@ -704,6 +705,9 @@ private: /// directive is present. bool HasRequiresUnifiedSharedMemory = false; + /// Atomic ordering from the omp requires directive. + llvm::AtomicOrdering RequiresAtomicOrdering = llvm::AtomicOrdering::Monotonic; + /// Flag for keeping track of weather a target region has been emitted. bool HasEmittedTargetRegion = false; @@ -1700,7 +1704,10 @@ public: /// Perform check on requires decl to ensure that target architecture /// supports unified addressing - virtual void checkArchForUnifiedAddressing(const OMPRequiresDecl *D); + virtual void processRequiresDirective(const OMPRequiresDecl *D); + + /// Gets default memory ordering as specified in requires directive. + llvm::AtomicOrdering getDefaultMemoryOrdering() const; /// Checks if the variable has associated OMPAllocateDeclAttr attribute with /// the predefined allocator and translates it into the corresponding address diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp index d00d84b79cfe..867bfb072736 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp @@ -4962,7 +4962,7 @@ static CudaArch getCudaArch(CodeGenModule &CGM) { /// Check to see if target architecture supports unified addressing which is /// a restriction for OpenMP requires clause "unified_shared_memory". -void CGOpenMPRuntimeNVPTX::checkArchForUnifiedAddressing( +void CGOpenMPRuntimeNVPTX::processRequiresDirective( const OMPRequiresDecl *D) { for (const OMPClause *Clause : D->clauselists()) { if (Clause->getClauseKind() == OMPC_unified_shared_memory) { @@ -5017,7 +5017,7 @@ void CGOpenMPRuntimeNVPTX::checkArchForUnifiedAddressing( } } } - CGOpenMPRuntime::checkArchForUnifiedAddressing(D); + CGOpenMPRuntime::processRequiresDirective(D); } /// Get number of SMs and number of blocks per SM. diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.h b/clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.h index 4159af0a622f..834adb3782a0 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.h +++ b/clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.h @@ -395,7 +395,7 @@ public: /// Perform check on requires decl to ensure that target architecture /// supports unified addressing - void checkArchForUnifiedAddressing(const OMPRequiresDecl *D) override; + void processRequiresDirective(const OMPRequiresDecl *D) override; /// Returns default address space for the constant firstprivates, __constant__ /// address space by default. diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp index 16914648a34d..7181374a73fc 100644 --- a/clang/lib/CodeGen/CGStmtOpenMP.cpp +++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp @@ -25,6 +25,7 @@ #include "clang/Basic/PrettyStackTrace.h" #include "llvm/Frontend/OpenMP/OMPIRBuilder.h" #include "llvm/IR/Instructions.h" +#include "llvm/Support/AtomicOrdering.h" using namespace clang; using namespace CodeGen; using namespace llvm::omp; @@ -4542,16 +4543,23 @@ static void emitOMPAtomicExpr(CodeGenFunction &CGF, OpenMPClauseKind Kind, void CodeGenFunction::EmitOMPAtomicDirective(const OMPAtomicDirective &S) { llvm::AtomicOrdering AO = llvm::AtomicOrdering::Monotonic; - if (S.getSingleClause()) + bool MemOrderingSpecified = false; + if (S.getSingleClause()) { AO = llvm::AtomicOrdering::SequentiallyConsistent; - else if (S.getSingleClause()) + MemOrderingSpecified = true; + } else if (S.getSingleClause()) { AO = llvm::AtomicOrdering::AcquireRelease; - else if (S.getSingleClause()) + MemOrderingSpecified = true; + } else if (S.getSingleClause()) { AO = llvm::AtomicOrdering::Acquire; - else if (S.getSingleClause()) + MemOrderingSpecified = true; + } else if (S.getSingleClause()) { AO = llvm::AtomicOrdering::Release; - else if (S.getSingleClause()) + MemOrderingSpecified = true; + } else if (S.getSingleClause()) { AO = llvm::AtomicOrdering::Monotonic; + MemOrderingSpecified = true; + } OpenMPClauseKind Kind = OMPC_unknown; for (const OMPClause *C : S.clauses()) { // Find first clause (skip seq_cst|acq_rel|aqcuire|release|relaxed clause, @@ -4565,6 +4573,23 @@ void CodeGenFunction::EmitOMPAtomicDirective(const OMPAtomicDirective &S) { break; } } + if (!MemOrderingSpecified) { + llvm::AtomicOrdering DefaultOrder = + CGM.getOpenMPRuntime().getDefaultMemoryOrdering(); + if (DefaultOrder == llvm::AtomicOrdering::Monotonic || + DefaultOrder == llvm::AtomicOrdering::SequentiallyConsistent || + (DefaultOrder == llvm::AtomicOrdering::AcquireRelease && + Kind == OMPC_capture)) { + AO = DefaultOrder; + } else if (DefaultOrder == llvm::AtomicOrdering::AcquireRelease) { + if (Kind == OMPC_unknown || Kind == OMPC_update || Kind == OMPC_write) { + AO = llvm::AtomicOrdering::Release; + } else if (Kind == OMPC_read) { + assert(Kind == OMPC_read && "Unexpected atomic kind."); + AO = llvm::AtomicOrdering::Acquire; + } + } + } const Stmt *CS = S.getInnermostCapturedStmt()->IgnoreContainers(); if (const auto *FE = dyn_cast(CS)) diff --git a/clang/lib/Parse/ParseOpenMP.cpp b/clang/lib/Parse/ParseOpenMP.cpp index c893ffc13f51..fbabe92977c9 100644 --- a/clang/lib/Parse/ParseOpenMP.cpp +++ b/clang/lib/Parse/ParseOpenMP.cpp @@ -1473,7 +1473,7 @@ Parser::DeclGroupPtrTy Parser::ParseOpenMPDeclarativeDirectiveWithExtDecl( Actions.EndOpenMPClause(); } // Consume final annot_pragma_openmp_end - if (Clauses.size() == 0) { + if (Clauses.empty()) { Diag(Tok, diag::err_omp_expected_clause) << getOpenMPDirectiveName(OMPD_requires); ConsumeAnnotationToken(); diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 2a13f72f6936..bd1c4777bc0d 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -271,6 +271,7 @@ private: nullptr}; /// Vector of previously encountered target directives SmallVector TargetLocations; + SourceLocation AtomicLocation; public: explicit DSAStackTy(Sema &S) : SemaRef(S) {} @@ -555,7 +556,7 @@ public: /// Checks if the defined 'requires' directive has specified type of clause. template - bool hasRequiresDeclWithClause() { + bool hasRequiresDeclWithClause() const { return llvm::any_of(RequiresDecls, [](const OMPRequiresDecl *D) { return llvm::any_of(D->clauselists(), [](const OMPClause *C) { return isa(C); @@ -590,6 +591,18 @@ public: TargetLocations.push_back(LocStart); } + /// Add location for the first encountered atomicc directive. + void addAtomicDirectiveLoc(SourceLocation Loc) { + if (AtomicLocation.isInvalid()) + AtomicLocation = Loc; + } + + /// Returns the location of the first encountered atomic directive in the + /// module. + SourceLocation getAtomicDirectiveLoc() const { + return AtomicLocation; + } + // Return previously encountered target region locations. ArrayRef getEncounteredTargetLocs() const { return TargetLocations; @@ -2830,18 +2843,26 @@ OMPRequiresDecl *Sema::CheckOMPRequiresDecl(SourceLocation Loc, /// current compilation unit. ArrayRef TargetLocations = DSAStack->getEncounteredTargetLocs(); - if (!TargetLocations.empty()) { + SourceLocation AtomicLoc = DSAStack->getAtomicDirectiveLoc(); + if (!TargetLocations.empty() || !AtomicLoc.isInvalid()) { for (const OMPClause *CNew : ClauseList) { // Check if any of the requires clauses affect target regions. if (isa(CNew) || isa(CNew) || isa(CNew) || isa(CNew)) { - Diag(Loc, diag::err_omp_target_before_requires) - << getOpenMPClauseName(CNew->getClauseKind()); + Diag(Loc, diag::err_omp_directive_before_requires) + << "target" << getOpenMPClauseName(CNew->getClauseKind()); for (SourceLocation TargetLoc : TargetLocations) { - Diag(TargetLoc, diag::note_omp_requires_encountered_target); + Diag(TargetLoc, diag::note_omp_requires_encountered_directive) + << "target"; } + } else if (!AtomicLoc.isInvalid() && + isa(CNew)) { + Diag(Loc, diag::err_omp_directive_before_requires) + << "atomic" << getOpenMPClauseName(CNew->getClauseKind()); + Diag(AtomicLoc, diag::note_omp_requires_encountered_directive) + << "atomic"; } } } @@ -8926,6 +8947,8 @@ StmtResult Sema::ActOnOpenMPAtomicDirective(ArrayRef Clauses, Stmt *AStmt, SourceLocation StartLoc, SourceLocation EndLoc) { + // Register location of the first atomic directive. + DSAStack->addAtomicDirectiveLoc(StartLoc); if (!AStmt) return StmtError(); diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp index 093b69ab19d0..3d47274079fa 100644 --- a/clang/lib/Serialization/ASTReaderDecl.cpp +++ b/clang/lib/Serialization/ASTReaderDecl.cpp @@ -2840,7 +2840,8 @@ static bool isConsumerInterestedIn(ASTContext &Ctx, Decl *D, bool HasBody) { isa(D)) return true; if (isa(D) || isa(D) || - isa(D) || isa(D)) + isa(D) || isa(D) || + isa(D)) return !D->getDeclContext()->isFunctionOrMethod(); if (const auto *Var = dyn_cast(D)) return Var->isFileVarDecl() && diff --git a/clang/test/OpenMP/requires_acq_rel_codegen.cpp b/clang/test/OpenMP/requires_acq_rel_codegen.cpp new file mode 100644 index 000000000000..b8ba01b0cafe --- /dev/null +++ b/clang/test/OpenMP/requires_acq_rel_codegen.cpp @@ -0,0 +1,39 @@ +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 %s -triple x86_64-apple-darwin10 -x c++ -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -triple x86_64-apple-darwin10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -std=c++11 -include-pch %t -verify %s -triple x86_64-apple-darwin10 -x c++ -emit-llvm -o -| FileCheck %s + +// RUN: %clang_cc1 -verify -fopenmp-simd %s -fopenmp-version=50 -x c++ -emit-llvm -triple x86_64-apple-darwin10 -o -| FileCheck %s --check-prefix SIMD-ONLY0 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -triple x86_64-apple-darwin10 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -std=c++11 -include-pch %t -verify %s -emit-llvm -x c++ -emit-llvm -triple x86_64-apple-darwin10 -o -| FileCheck %s --check-prefix SIMD-ONLY0 +// SIMD-ONLY0-NOT: {{__kmpc|__tgt}} +// expected-no-diagnostics + +#ifndef HEADER +#define HEADER + +#pragma omp requires atomic_default_mem_order(acq_rel) + +// CHECK-LABEL: foo +void foo() { + int a = 0, b = 0; +// CHECK: load atomic i32,{{.*}}acquire +#pragma omp atomic read + a = b; +// CHECK: store atomic i32{{.*}}release +#pragma omp atomic write + a = b; +// CHECK: atomicrmw add i32{{.*}}release +#pragma omp atomic + a += 1; +// CHECK: atomicrmw add i32{{.*}}release +#pragma omp atomic update + a += 1; +// CHECK: atomicrmw add i32{{.*}}acq_rel +#pragma omp atomic capture + { + b = a; + a += 1; + } +} + +#endif diff --git a/clang/test/OpenMP/requires_default_atomic_mem_order_messages.cpp b/clang/test/OpenMP/requires_default_atomic_mem_order_messages.cpp new file mode 100644 index 000000000000..19f6ede043d8 --- /dev/null +++ b/clang/test/OpenMP/requires_default_atomic_mem_order_messages.cpp @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -verify -fopenmp -ferror-limit 100 %s + +void foo2() { + int a; + #pragma omp atomic update // expected-note 3 {{'atomic' previously encountered here}} + a = a + 1; +} + +#pragma omp requires atomic_default_mem_order(seq_cst) // expected-error {{'atomic' region encountered before requires directive with 'atomic_default_mem_order' clause}} expected-note 2 {{atomic_default_mem_order clause previously used here}} +#pragma omp requires atomic_default_mem_order(acq_rel) // expected-error {{'atomic' region encountered before requires directive with 'atomic_default_mem_order' clause}} expected-error {{Only one atomic_default_mem_order clause can appear on a requires directive in a single translation unit}} +#pragma omp requires atomic_default_mem_order(relaxed) // expected-error {{'atomic' region encountered before requires directive with 'atomic_default_mem_order' clause}} expected-error {{Only one atomic_default_mem_order clause can appear on a requires directive in a single translation unit}} +#pragma omp requires atomic_default_mem_order(release) // expected-error {{expected 'seq_cst', 'acq_rel' or 'relaxed' in OpenMP clause 'atomic_default_mem_order'}} expected-error {{expected at least one clause on '#pragma omp requires' directive}} diff --git a/clang/test/OpenMP/requires_relaxed_codegen.cpp b/clang/test/OpenMP/requires_relaxed_codegen.cpp new file mode 100644 index 000000000000..e92b55e8f137 --- /dev/null +++ b/clang/test/OpenMP/requires_relaxed_codegen.cpp @@ -0,0 +1,39 @@ +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 %s -triple x86_64-apple-darwin10 -x c++ -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -triple x86_64-apple-darwin10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -std=c++11 -include-pch %t -verify %s -triple x86_64-apple-darwin10 -x c++ -emit-llvm -o -| FileCheck %s + +// RUN: %clang_cc1 -verify -fopenmp-simd %s -fopenmp-version=50 -x c++ -emit-llvm -triple x86_64-apple-darwin10 -o -| FileCheck %s --check-prefix SIMD-ONLY0 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -triple x86_64-apple-darwin10 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -std=c++11 -include-pch %t -verify %s -emit-llvm -x c++ -emit-llvm -triple x86_64-apple-darwin10 -o -| FileCheck %s --check-prefix SIMD-ONLY0 +// SIMD-ONLY0-NOT: {{__kmpc|__tgt}} +// expected-no-diagnostics + +#ifndef HEADER +#define HEADER + +#pragma omp requires atomic_default_mem_order(relaxed) + +// CHECK-LABEL: foo +void foo() { + int a = 0, b = 0; +// CHECK: load atomic i32,{{.*}}monotonic +#pragma omp atomic read + a = b; +// CHECK: store atomic i32{{.*}}monotonic +#pragma omp atomic write + a = b; +// CHECK: atomicrmw add i32{{.*}}monotonic +#pragma omp atomic + a += 1; +// CHECK: atomicrmw add i32{{.*}}monotonic +#pragma omp atomic update + a += 1; +// CHECK: atomicrmw add i32{{.*}}monotonic +#pragma omp atomic capture + { + b = a; + a += 1; + } +} + +#endif diff --git a/clang/test/OpenMP/requires_seq_cst_codegen.cpp b/clang/test/OpenMP/requires_seq_cst_codegen.cpp new file mode 100644 index 000000000000..c2f02665d153 --- /dev/null +++ b/clang/test/OpenMP/requires_seq_cst_codegen.cpp @@ -0,0 +1,39 @@ +// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=50 %s -triple x86_64-apple-darwin10 -x c++ -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -triple x86_64-apple-darwin10 +// RUN: %clang_cc1 -fopenmp -fopenmp-version=50 -std=c++11 -include-pch %t -verify %s -triple x86_64-apple-darwin10 -x c++ -emit-llvm -o -| FileCheck %s + +// RUN: %clang_cc1 -verify -fopenmp-simd %s -fopenmp-version=50 -x c++ -emit-llvm -triple x86_64-apple-darwin10 -o -| FileCheck %s --check-prefix SIMD-ONLY0 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -x c++ -std=c++11 -emit-pch -o %t %s -triple x86_64-apple-darwin10 +// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=50 -std=c++11 -include-pch %t -verify %s -emit-llvm -x c++ -emit-llvm -triple x86_64-apple-darwin10 -o -| FileCheck %s --check-prefix SIMD-ONLY0 +// SIMD-ONLY0-NOT: {{__kmpc|__tgt}} +// expected-no-diagnostics + +#ifndef HEADER +#define HEADER + +#pragma omp requires atomic_default_mem_order(seq_cst) + +// CHECK-LABEL: foo +void foo() { + int a = 0, b = 0; +// CHECK: load atomic i32,{{.*}}seq_cst +#pragma omp atomic read + a = b; +// CHECK: store atomic i32{{.*}}seq_cst +#pragma omp atomic write + a = b; +// CHECK: atomicrmw add i32{{.*}}seq_cst +#pragma omp atomic + a += 1; +// CHECK: atomicrmw add i32{{.*}}seq_cst +#pragma omp atomic update + a += 1; +// CHECK: atomicrmw add i32{{.*}}seq_cst +#pragma omp atomic capture + { + b = a; + a += 1; + } +} + +#endif diff --git a/clang/test/OpenMP/requires_target_messages.cpp b/clang/test/OpenMP/requires_target_messages.cpp index ef65d98fed9c..93f318ea1bb7 100644 --- a/clang/test/OpenMP/requires_target_messages.cpp +++ b/clang/test/OpenMP/requires_target_messages.cpp @@ -2,14 +2,14 @@ void foo2() { int a; - #pragma omp target // expected-note 4 {{target previously encountered here}} + #pragma omp target // expected-note 4 {{'target' previously encountered here}} { a = a + 1; } } #pragma omp requires atomic_default_mem_order(seq_cst) -#pragma omp requires unified_address //expected-error {{target region encountered before requires directive with 'unified_address' clause}} -#pragma omp requires unified_shared_memory //expected-error {{target region encountered before requires directive with 'unified_shared_memory' clause}} -#pragma omp requires reverse_offload //expected-error {{target region encountered before requires directive with 'reverse_offload' clause}} -#pragma omp requires dynamic_allocators //expected-error {{target region encountered before requires directive with 'dynamic_allocators' clause}} +#pragma omp requires unified_address //expected-error {{'target' region encountered before requires directive with 'unified_address' clause}} +#pragma omp requires unified_shared_memory //expected-error {{'target' region encountered before requires directive with 'unified_shared_memory' clause}} +#pragma omp requires reverse_offload //expected-error {{'target' region encountered before requires directive with 'reverse_offload' clause}} +#pragma omp requires dynamic_allocators //expected-error {{'target' region encountered before requires directive with 'dynamic_allocators' clause}} -- GitLab From 86787f159a0737662a8a3086a9b03223ff839dd2 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Tue, 11 Feb 2020 09:14:44 -0800 Subject: [PATCH 061/142] [ORC] Add debug logging to JITDylib::addDependencies. --- llvm/lib/ExecutionEngine/Orc/Core.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/llvm/lib/ExecutionEngine/Orc/Core.cpp b/llvm/lib/ExecutionEngine/Orc/Core.cpp index f2b161cc9fc1..a7af34a21926 100644 --- a/llvm/lib/ExecutionEngine/Orc/Core.cpp +++ b/llvm/lib/ExecutionEngine/Orc/Core.cpp @@ -205,7 +205,7 @@ raw_ostream &operator<<(raw_ostream &OS, const SymbolMap &Symbols) { raw_ostream &operator<<(raw_ostream &OS, const SymbolDependenceMap::value_type &KV) { - return OS << "(" << KV.first << ", " << KV.second << ")"; + return OS << "(" << KV.first->getName() << ", " << KV.second << ")"; } raw_ostream &operator<<(raw_ostream &OS, const SymbolDependenceMap &Deps) { @@ -941,6 +941,11 @@ void JITDylib::addDependencies(const SymbolStringPtr &Name, assert(Symbols[Name].isInMaterializationPhase() && "Can not add dependencies for a symbol that is not materializing"); + LLVM_DEBUG({ + dbgs() << "In " << getName() << " adding dependencies for " + << *Name << ": " << Dependencies << "\n"; + }); + // If Name is already in an error state then just bail out. if (Symbols[Name].getFlags().hasError()) return; -- GitLab From 7a6ae494c522e91f56c91a27045ebfdcbd7327fc Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Tue, 11 Feb 2020 08:51:45 -0800 Subject: [PATCH 062/142] [JITLink] Add an assertion that block removal leaves no dangling symbols. --- llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h b/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h index fa04653fa7bd..1a8f5cacbcd4 100644 --- a/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h +++ b/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h @@ -17,6 +17,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/Optional.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/Triple.h" #include "llvm/ExecutionEngine/JITSymbol.h" #include "llvm/Support/Allocator.h" @@ -990,6 +991,11 @@ public: /// Remove a block. void removeBlock(Block &B) { + assert(llvm::none_of(B.getSection().symbols(), + [&](const Symbol *Sym) { + return &Sym->getBlock() == &B; + }) && + "Block still has symbols attached"); B.getSection().removeBlock(B); destroyBlock(B); } -- GitLab From ca6f58486ffda249a4330f5a9e20266ea8a40806 Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Tue, 11 Feb 2020 09:02:22 -0800 Subject: [PATCH 063/142] [ORC] Fix symbol dependence propagation algorithm in ObjectLinkingLayer. ObjectLinkingLayer was not correctly propagating dependencies through local symbols within an object. This could cause symbol lookup to return before a searched-for symbol is ready if the following conditions are met: (1) The definition of the symbol being searched for transitively depends on a local symbol within the same object, and that local symbol in turn transitively depends on an external symbol provided by some other module in the JIT. (2) Concurrent compilation is enabled. (3) Thread scheduling causes the lookup of the searched-for symbol to return before all transitive dependencies of the looked-up symbol are emitted. This bug was found by inspection and has not been observed in practice. A jitlink test case has been added to verify that symbol dependencies are correctly propagated through local symbol definitions. --- .../Orc/ObjectLinkingLayer.cpp | 108 +++++++++++------- .../JITLink/X86/LocalDependencyPropagation.s | 31 +++++ 2 files changed, 98 insertions(+), 41 deletions(-) create mode 100644 llvm/test/ExecutionEngine/JITLink/X86/LocalDependencyPropagation.s diff --git a/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp b/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp index 2572b7f4878d..6575b0a6ccb2 100644 --- a/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp @@ -84,6 +84,12 @@ public: } }; + for (auto &KV : InternalNamedSymbolDeps) { + SymbolDependenceMap InternalDeps; + InternalDeps[&MR.getTargetJITDylib()] = std::move(KV.second); + MR.addDependencies(KV.first, InternalDeps); + } + ES.lookup(LookupKind::Static, SearchOrder, std::move(LookupSet), SymbolState::Resolved, std::move(OnResolve), [this](const SymbolDependenceMap &Deps) { @@ -168,16 +174,18 @@ public: // link graph to build the symbol dependence graph. Config.PrePrunePasses.push_back( [this](LinkGraph &G) { return externalizeWeakAndCommonSymbols(G); }); - Config.PostPrunePasses.push_back( - [this](LinkGraph &G) { return computeNamedSymbolDependencies(G); }); Layer.modifyPassConfig(MR, TT, Config); + Config.PostPrunePasses.push_back( + [this](LinkGraph &G) { return computeNamedSymbolDependencies(G); }); + return Error::success(); } private: - using AnonToNamedDependenciesMap = DenseMap; + using JITLinkSymbolSet = DenseSet; + using LocalToNamedDependenciesMap = DenseMap; Error externalizeWeakAndCommonSymbols(LinkGraph &G) { auto &ES = Layer.getExecutionSession(); @@ -206,90 +214,107 @@ private: Error computeNamedSymbolDependencies(LinkGraph &G) { auto &ES = MR.getTargetJITDylib().getExecutionSession(); - auto AnonDeps = computeAnonDeps(G); + auto LocalDeps = computeLocalDeps(G); for (auto *Sym : G.defined_symbols()) { - // Skip anonymous and non-global atoms: we do not need dependencies for - // these. + // Skip local symbols: we do not track dependencies for these. if (Sym->getScope() == Scope::Local) continue; + assert(Sym->hasName() && + "Defined non-local jitlink::Symbol should have a name"); - auto SymName = ES.intern(Sym->getName()); - SymbolNameSet &SymDeps = NamedSymbolDeps[SymName]; + SymbolNameSet ExternalSymDeps, InternalSymDeps; + // Find internal and external named symbol dependencies. for (auto &E : Sym->getBlock().edges()) { auto &TargetSym = E.getTarget(); - if (TargetSym.getScope() != Scope::Local) - SymDeps.insert(ES.intern(TargetSym.getName())); - else { + if (TargetSym.getScope() != Scope::Local) { + if (TargetSym.isExternal()) + ExternalSymDeps.insert(ES.intern(TargetSym.getName())); + else if (&TargetSym != Sym) + InternalSymDeps.insert(ES.intern(TargetSym.getName())); + } else { assert(TargetSym.isDefined() && - "Anonymous/local symbols must be defined"); - auto I = AnonDeps.find(&TargetSym); - if (I != AnonDeps.end()) - for (auto &S : I->second) - SymDeps.insert(S); + "local symbols must be defined"); + auto I = LocalDeps.find(&TargetSym); + if (I != LocalDeps.end()) + for (auto &S : I->second) { + assert(S->hasName() && + "LocalDeps should only contain named values"); + if (S->isExternal()) + ExternalSymDeps.insert(ES.intern(S->getName())); + else if (S != Sym) + InternalSymDeps.insert(ES.intern(S->getName())); + } } } + + if (ExternalSymDeps.empty() && InternalSymDeps.empty()) + continue; + + auto SymName = ES.intern(Sym->getName()); + if (!ExternalSymDeps.empty()) + ExternalNamedSymbolDeps[SymName] = std::move(ExternalSymDeps); + if (!InternalSymDeps.empty()) + InternalNamedSymbolDeps[SymName] = std::move(InternalSymDeps); } return Error::success(); } - AnonToNamedDependenciesMap computeAnonDeps(LinkGraph &G) { + LocalToNamedDependenciesMap computeLocalDeps(LinkGraph &G) { + LocalToNamedDependenciesMap DepMap; - auto &ES = MR.getTargetJITDylib().getExecutionSession(); - AnonToNamedDependenciesMap DepMap; - - // For all anonymous symbols: + // For all local symbols: // (1) Add their named dependencies. // (2) Add them to the worklist for further iteration if they have any - // depend on any other anonymous symbols. + // depend on any other local symbols. struct WorklistEntry { - WorklistEntry(Symbol *Sym, DenseSet SymAnonDeps) - : Sym(Sym), SymAnonDeps(std::move(SymAnonDeps)) {} + WorklistEntry(Symbol *Sym, DenseSet LocalDeps) + : Sym(Sym), LocalDeps(std::move(LocalDeps)) {} Symbol *Sym = nullptr; - DenseSet SymAnonDeps; + DenseSet LocalDeps; }; std::vector Worklist; for (auto *Sym : G.defined_symbols()) - if (!Sym->hasName()) { + if (Sym->getScope() == Scope::Local) { auto &SymNamedDeps = DepMap[Sym]; - DenseSet SymAnonDeps; + DenseSet LocalDeps; for (auto &E : Sym->getBlock().edges()) { auto &TargetSym = E.getTarget(); - if (TargetSym.hasName()) - SymNamedDeps.insert(ES.intern(TargetSym.getName())); + if (TargetSym.getScope() != Scope::Local) + SymNamedDeps.insert(&TargetSym); else { assert(TargetSym.isDefined() && - "Anonymous symbols must be defined"); - SymAnonDeps.insert(&TargetSym); + "local symbols must be defined"); + LocalDeps.insert(&TargetSym); } } - if (!SymAnonDeps.empty()) - Worklist.push_back(WorklistEntry(Sym, std::move(SymAnonDeps))); + if (!LocalDeps.empty()) + Worklist.push_back(WorklistEntry(Sym, std::move(LocalDeps))); } - // Loop over all anonymous symbols with anonymous dependencies, propagating - // their respective *named* dependencies. Iterate until we hit a stable + // Loop over all local symbols with local dependencies, propagating + // their respective non-local dependencies. Iterate until we hit a stable // state. bool Changed; do { Changed = false; for (auto &WLEntry : Worklist) { auto *Sym = WLEntry.Sym; - auto &SymNamedDeps = DepMap[Sym]; - auto &SymAnonDeps = WLEntry.SymAnonDeps; + auto &NamedDeps = DepMap[Sym]; + auto &LocalDeps = WLEntry.LocalDeps; - for (auto *TargetSym : SymAnonDeps) { + for (auto *TargetSym : LocalDeps) { auto I = DepMap.find(TargetSym); if (I != DepMap.end()) for (const auto &S : I->second) - Changed |= SymNamedDeps.insert(S).second; + Changed |= NamedDeps.insert(S).second; } } } while (Changed); @@ -298,7 +323,7 @@ private: } void registerDependencies(const SymbolDependenceMap &QueryDeps) { - for (auto &NamedDepsEntry : NamedSymbolDeps) { + for (auto &NamedDepsEntry : ExternalNamedSymbolDeps) { auto &Name = NamedDepsEntry.first; auto &NameDeps = NamedDepsEntry.second; SymbolDependenceMap SymbolDeps; @@ -323,7 +348,8 @@ private: ObjectLinkingLayer &Layer; MaterializationResponsibility MR; std::unique_ptr ObjBuffer; - DenseMap NamedSymbolDeps; + DenseMap ExternalNamedSymbolDeps; + DenseMap InternalNamedSymbolDeps; }; ObjectLinkingLayer::Plugin::~Plugin() {} diff --git a/llvm/test/ExecutionEngine/JITLink/X86/LocalDependencyPropagation.s b/llvm/test/ExecutionEngine/JITLink/X86/LocalDependencyPropagation.s new file mode 100644 index 000000000000..e44e39f67fae --- /dev/null +++ b/llvm/test/ExecutionEngine/JITLink/X86/LocalDependencyPropagation.s @@ -0,0 +1,31 @@ +# REQUIRES: asserts +# RUN: llvm-mc -triple=x86_64-apple-macosx10.9 -filetype=obj -o %t %s +# RUN: llvm-jitlink -debug-only=orc -noexec -define-abs _external_func=0x1 \ +# RUN: -entry=_foo %t 2>&1 | FileCheck %s +# +# Verify that symbol dependencies are correctly propagated through local +# symbols: _baz depends on _foo indirectly via the local symbol _bar. We expect +# _baz to depend on _foo, and _foo on _external_func. + +# CHECK-DAG: In
adding dependencies for _foo: { (
, { _external_func }) } +# CHECK-DAG: In
adding dependencies for _baz: { (
, { _foo }) } + + .section __TEXT,__text,regular,pure_instructions + + .globl _foo + .p2align 4, 0x90 +_foo: + jmp _external_func + + .p2align 4, 0x90 +_bar: + + jmp _foo + + .globl _baz + .p2align 4, 0x90 +_baz: + + jmp _bar + +.subsections_via_symbols -- GitLab From 5e37fb1776de2698c10db697e3c479d0e94234e0 Mon Sep 17 00:00:00 2001 From: Steven Wan Date: Tue, 11 Feb 2020 15:58:32 -0500 Subject: [PATCH 064/142] [NFC] Delete extra white space in a test case. Remove an extra empty line in one of the AIX driver test cases. --- clang/test/Driver/aix-as.c | 1 - 1 file changed, 1 deletion(-) diff --git a/clang/test/Driver/aix-as.c b/clang/test/Driver/aix-as.c index 4f67d1ba90b7..cb3053f5acd3 100644 --- a/clang/test/Driver/aix-as.c +++ b/clang/test/Driver/aix-as.c @@ -23,7 +23,6 @@ // CHECK-AS64: "-u" // CHECK-AS64: "-many" - // Check powerpc-ibm-aix7.1.0.0, 32-bit. -Xassembler option. // RUN: %clang -no-canonical-prefixes %s -### -c -o %t.o 2>&1 \ // RUN: -Xassembler -w \ -- GitLab From 813bfffec34b87d32c9c834718f660afb5275bc8 Mon Sep 17 00:00:00 2001 From: Andy Davis Date: Tue, 11 Feb 2020 12:57:57 -0800 Subject: [PATCH 065/142] [mlir][VectorOps] Adds canonicalization rewrite patterns for vector ShapeCastOp. Summary: Adds two rewrite patterns for the vector ShapeCastOp. *) ShapeCastOp decomposer: decomposes ShapeCastOp on tuple-of-vectors to multiple ShapeCastOps each on vector types. *) ShapeCastOp folder: folds canceling shape cast ops (e.g. shape_cast A -> B followed by shape_cast B -> A) away. Reviewers: nicolasvasilache, aartbik Reviewed By: nicolasvasilache Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74327 --- .../Dialect/VectorOps/VectorTransforms.cpp | 88 ++++++++++++++++++- .../Dialect/VectorOps/vector-transforms.mlir | 59 +++++++++++++ 2 files changed, 145 insertions(+), 2 deletions(-) diff --git a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp b/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp index 440c7707ce75..8bdeb92afe5e 100644 --- a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp +++ b/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp @@ -646,6 +646,90 @@ struct SplitTransferWriteOp : public OpRewritePattern { } }; +/// Decomposes ShapeCastOp on tuple-of-vectors to multiple ShapeCastOps, each +/// on vector types. +struct ShapeCastOpDecomposer : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + PatternMatchResult matchAndRewrite(vector::ShapeCastOp shapeCastOp, + PatternRewriter &rewriter) const override { + // Check if 'shapeCastOp' has tuple source/result type. + auto sourceTupleType = + shapeCastOp.source().getType().dyn_cast_or_null(); + auto resultTupleType = + shapeCastOp.result().getType().dyn_cast_or_null(); + if (!sourceTupleType || !resultTupleType) + return matchFailure(); + assert(sourceTupleType.size() == resultTupleType.size()); + + // Create single-vector ShapeCastOp for each source tuple element. + Location loc = shapeCastOp.getLoc(); + SmallVector resultElements; + resultElements.reserve(resultTupleType.size()); + for (unsigned i = 0, e = sourceTupleType.size(); i < e; ++i) { + auto sourceElement = rewriter.create( + loc, sourceTupleType.getType(i), shapeCastOp.source(), + rewriter.getI64IntegerAttr(i)); + resultElements.push_back(rewriter.create( + loc, resultTupleType.getType(i), sourceElement)); + } + + // Replace 'shapeCastOp' with tuple of 'resultElements'. + rewriter.replaceOpWithNewOp(shapeCastOp, resultTupleType, + resultElements); + return matchSuccess(); + } +}; + +/// ShapeCastOpFolder folds cancelling ShapeCastOps away. +// +// Example: +// +// The following MLIR with cancelling ShapeCastOps: +// +// %0 = source : vector<5x4x2xf32> +// %1 = shape_cast %0 : vector<5x4x2xf32> to vector<20x2xf32> +// %2 = shape_cast %1 : vector<20x2xf32> to vector<5x4x2xf32> +// %3 = user %2 : vector<5x4x2xf32> +// +// Should canonicalize to the following: +// +// %0 = source : vector<5x4x2xf32> +// %1 = user %0 : vector<5x4x2xf32> +// +struct ShapeCastOpFolder : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + PatternMatchResult matchAndRewrite(vector::ShapeCastOp shapeCastOp, + PatternRewriter &rewriter) const override { + // Check if 'shapeCastOp' has vector source/result type. + auto sourceVectorType = + shapeCastOp.source().getType().dyn_cast_or_null(); + auto resultVectorType = + shapeCastOp.result().getType().dyn_cast_or_null(); + if (!sourceVectorType || !resultVectorType) + return matchFailure(); + + // Check if shape cast op source operand is also a shape cast op. + auto sourceShapeCastOp = dyn_cast_or_null( + shapeCastOp.source().getDefiningOp()); + if (!sourceShapeCastOp) + return matchFailure(); + auto operandSourceVectorType = + sourceShapeCastOp.source().getType().cast(); + auto operandResultVectorType = + sourceShapeCastOp.result().getType().cast(); + + // Check if shape cast operations invert each other. + if (operandSourceVectorType != resultVectorType || + operandResultVectorType != sourceVectorType) + return matchFailure(); + + rewriter.replaceOp(shapeCastOp, sourceShapeCastOp.source()); + return matchSuccess(); + } +}; + // Patter rewrite which forward tuple elements to their users. // User(TupleGetOp(ExtractSlicesOp(InsertSlicesOp(TupleOp(Producer))))) // -> User(Producer) @@ -784,8 +868,8 @@ public: // TODO(andydavis) Add this as DRR pattern. void mlir::vector::populateVectorToVectorTransformationPatterns( OwningRewritePatternList &patterns, MLIRContext *context) { - patterns.insert( - context); + patterns.insert(context); } void mlir::vector::populateVectorSlicesLoweringPatterns( diff --git a/mlir/test/Dialect/VectorOps/vector-transforms.mlir b/mlir/test/Dialect/VectorOps/vector-transforms.mlir index 1153ffb2999f..7582758384ce 100644 --- a/mlir/test/Dialect/VectorOps/vector-transforms.mlir +++ b/mlir/test/Dialect/VectorOps/vector-transforms.mlir @@ -346,3 +346,62 @@ func @vector_transfers_vector_element_type() { return } + +// Test that ShapeCastOp on tuple of vectors, decomposes to multiple +// ShapeCastOps on vectors. +// CHECK-LABEL: func @shape_cast_decomposition +// CHECK: %[[V0:.*]] = vector.shape_cast %{{.*}} : vector<5x4x2xf32> to vector<20x2xf32> +// CHECK-NEXT: %[[V1:.*]] = vector.shape_cast %{{.*}} : vector<3x4x2xf32> to vector<12x2xf32> +// CHECK-NEXT: return %[[V0]], %[[V1]] : vector<20x2xf32>, vector<12x2xf32> + +func @shape_cast_decomposition(%arg0 : vector<5x4x2xf32>, + %arg1 : vector<3x4x2xf32>) + -> (vector<20x2xf32>, vector<12x2xf32>) { + %0 = vector.tuple %arg0, %arg1 : vector<5x4x2xf32>, vector<3x4x2xf32> + %1 = vector.shape_cast %0 : tuple, vector<3x4x2xf32>> to + tuple, vector<12x2xf32>> + %2 = vector.tuple_get %1, 0 : tuple, vector<12x2xf32>> + %3 = vector.tuple_get %1, 1 : tuple, vector<12x2xf32>> + return %2, %3 : vector<20x2xf32>, vector<12x2xf32> +} + +// Test that cancelling ShapeCastOps are canonicalized away. +// EX: +// +// The following MLIR with cancelling ShapeCastOps: +// +// %0 = source : vector<5x4x2xf32> +// %1 = shape_cast %0 : vector<5x4x2xf32> to vector<20x2xf32> +// %2 = shape_cast %1 : vector<20x2xf32> to vector<5x4x2xf32> +// %3 = user %2 : vector<5x4x2xf32> +// +// Should canonicalize to the following: +// +// +// %0 = source : vector<5x4x2xf32> +// %1 = user %0 : vector<5x4x2xf32> +// + +// ShapeCastOps on vectors. +// CHECK-LABEL: func @shape_cast_fold +// CHECK: return %{{.*}}, %{{.*}} : vector<5x4x2xf32>, vector<3x4x2xf32> + +func @shape_cast_fold(%arg0 : vector<5x4x2xf32>, %arg1 : vector<3x4x2xf32>) + -> (vector<5x4x2xf32>, vector<3x4x2xf32>) { + %0 = vector.tuple %arg0, %arg1 : vector<5x4x2xf32>, vector<3x4x2xf32> + + %1 = vector.shape_cast %0 : tuple, vector<3x4x2xf32>> to + tuple, vector<12x2xf32>> + + %2 = vector.tuple_get %1, 0 : tuple, vector<12x2xf32>> + %3 = vector.tuple_get %1, 1 : tuple, vector<12x2xf32>> + + %4 = vector.tuple %2, %3 : vector<20x2xf32>, vector<12x2xf32> + %5 = vector.shape_cast %4 : tuple, vector<12x2xf32>> to + tuple, vector<3x4x2xf32>> + + %6 = vector.tuple_get %5, 0 : tuple, vector<3x4x2xf32>> + %7 = vector.tuple_get %5, 1 : tuple, vector<3x4x2xf32>> + + return %6, %7 : vector<5x4x2xf32>, vector<3x4x2xf32> +} -- GitLab From 8e62968d45429815411ca9bb358a913dde7b1152 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 11 Feb 2020 00:10:35 -0600 Subject: [PATCH 066/142] [Attributor] Identify dead uses in PHIs (almost) based on dead edges As an approximation to a dead edge we can check if the terminator is dead. If so, the corresponding operand use in a PHI node is dead even if the PHI node itself is not. --- llvm/lib/Transforms/IPO/Attributor.cpp | 27 +++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index 4c0185de3f04..877557a92fb5 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -6489,14 +6489,27 @@ bool Attributor::checkForAllUses( const Use *U = Worklist.pop_back_val(); if (!Visited.insert(U).second) continue; - LLVM_DEBUG(dbgs() << "[Attributor] Check use: " << **U << "\n"); - if (Instruction *UserI = dyn_cast(U->getUser())) - if (LivenessAA && LivenessAA->isAssumedDead(UserI)) { - LLVM_DEBUG(dbgs() << "[Attributor] Dead user: " << *UserI << ": " - << *LivenessAA << "\n"); - AnyDead = true; - continue; + LLVM_DEBUG(dbgs() << "[Attributor] Check use: " << **U << " [" << LivenessAA + << "]\n"); + if (LivenessAA) { + if (Instruction *UserI = dyn_cast(U->getUser())) { + if (LivenessAA->isAssumedDead(UserI)) { + LLVM_DEBUG(dbgs() << "[Attributor] Dead user: " << *UserI << ": " + << *LivenessAA << "\n"); + AnyDead = true; + continue; + } + if (PHINode *PHI = dyn_cast(UserI)) { + BasicBlock *IncomingBB = PHI->getIncomingBlock(*U); + if (LivenessAA->isAssumedDead(IncomingBB->getTerminator())) { + LLVM_DEBUG(dbgs() << "[Attributor] Dead user: " << *UserI << ": " + << *LivenessAA << "\n"); + AnyDead = true; + continue; + } + } } + } bool Follow = false; if (!Pred(*U, Follow)) -- GitLab From 52aec3221fa5766c669cfd16e6ba0cf0737d1fff Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 11 Feb 2020 15:11:32 -0600 Subject: [PATCH 067/142] [Attributor][NFC] Clarify the documentation a bit more --- llvm/lib/Transforms/IPO/Attributor.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp index 877557a92fb5..86968d1f7761 100644 --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -374,10 +374,11 @@ static Value *constructPointer(Type *ResTy, Value *Ptr, int64_t Offset, /// will be done by looking through cast instructions, selects, phis, and calls /// with the "returned" attribute. Once we cannot look through the value any /// further, the callback \p VisitValueCB is invoked and passed the current -/// value, the \p State, and a flag to indicate if we stripped anything (=the -/// value used for the callback is not the value associated with \p IRP). To -/// limit how much effort is invested, we will never visit more values than -/// specified by \p MaxValues. +/// value, the \p State, and a flag to indicate if we stripped anything. +/// Stripped means that we unpacked the value associated with \p IRP at least +/// once. Note that the value used for the callback may still be the value +/// associated with \p IRP (due to PHIs). To limit how much effort is invested, +/// we will never visit more values than specified by \p MaxValues. template static bool genericValueTraversal( Attributor &A, IRPosition IRP, const AAType &QueryingAA, StateTy &State, -- GitLab From 07f7c00208b393296f8f27d6cd3cec2b11d86fd8 Mon Sep 17 00:00:00 2001 From: lewis-revill Date: Tue, 11 Feb 2020 21:23:03 +0000 Subject: [PATCH 068/142] [RISCV] Add support for save/restore of callee-saved registers via libcalls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds the support required for using the __riscv_save and __riscv_restore libcalls to implement a size-optimization for prologue and epilogue code, whereby the spill and restore code of callee-saved registers is implemented by common functions to reduce code duplication. Logic is also included to ensure that if both this optimization and shrink wrapping are enabled then the prologue and epilogue code can be safely inserted into the basic blocks chosen by shrink wrapping. Differential Revision: https://reviews.llvm.org/D62686 --- clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 11 +- clang/test/Driver/riscv-features.c | 7 +- llvm/lib/Target/RISCV/RISCV.td | 3 + llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 331 ++++++++++++++++-- llvm/lib/Target/RISCV/RISCVFrameLowering.h | 12 + .../Target/RISCV/RISCVMachineFunctionInfo.h | 13 + llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 34 ++ llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 3 + llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 + llvm/test/CodeGen/RISCV/saverestore.ll | 299 ++++++++++++++++ llvm/test/CodeGen/RISCV/shrinkwrap.ll | 29 ++ 11 files changed, 714 insertions(+), 30 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/saverestore.ll diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index 5f69fddb5e03..f5764ca5dc06 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -433,12 +433,11 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple, Features.push_back("-relax"); // GCC Compatibility: -mno-save-restore is default, unless -msave-restore is - // specified... - if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore, false)) { - // ... but we don't support -msave-restore, so issue a warning. - D.Diag(diag::warn_drv_clang_unsupported) - << Args.getLastArg(options::OPT_msave_restore)->getAsString(Args); - } + // specified. + if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore, false)) + Features.push_back("+save-restore"); + else + Features.push_back("-save-restore"); // Now add any that the user explicitly requested on the command line, // which may override the defaults. diff --git a/clang/test/Driver/riscv-features.c b/clang/test/Driver/riscv-features.c index 2f2ae51e4716..8d76e681289b 100644 --- a/clang/test/Driver/riscv-features.c +++ b/clang/test/Driver/riscv-features.c @@ -16,9 +16,10 @@ // RUN: %clang -target riscv32-unknown-elf -### %s -msave-restore 2>&1 | FileCheck %s -check-prefix=SAVE-RESTORE // RUN: %clang -target riscv32-unknown-elf -### %s -mno-save-restore 2>&1 | FileCheck %s -check-prefix=NO-SAVE-RESTORE -// SAVE-RESTORE: warning: the clang compiler does not support '-msave-restore' -// NO-SAVE-RESTORE-NOT: warning: the clang compiler does not support -// DEFAULT-NOT: warning: the clang compiler does not support +// SAVE-RESTORE: "-target-feature" "+save-restore" +// NO-SAVE-RESTORE: "-target-feature" "-save-restore" +// DEFAULT: "-target-feature" "-save-restore" +// DEFAULT-NOT: "-target-feature" "+save-restore" // RUN: %clang -target riscv32-linux -### %s -fsyntax-only 2>&1 \ // RUN: | FileCheck %s -check-prefix=DEFAULT-LINUX diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 770e883221d1..5f887fdf79ef 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -82,6 +82,9 @@ foreach i = {1-31} in SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]", "true", "Reserve X"#i>; +def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", + "true", "Enable save/restore.">; + //===----------------------------------------------------------------------===// // Named operands for CSR instructions. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index f7cd19cbb8e7..de6e8bf090d4 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -23,6 +23,100 @@ using namespace llvm; +// Get the ID of the libcall used for spilling and restoring callee saved +// registers. The ID is representative of the number of registers saved or +// restored by the libcall, except it is zero-indexed - ID 0 corresponds to a +// single register. +static int getLibCallID(const MachineFunction &MF, + const std::vector &CSI) { + const auto *RVFI = MF.getInfo(); + + if (CSI.empty() || !RVFI->useSaveRestoreLibCalls()) + return -1; + + Register MaxReg = RISCV::NoRegister; + for (auto &CS : CSI) + // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indexes to + // registers which can be saved by libcall. + if (CS.getFrameIdx() < 0) + MaxReg = std::max(MaxReg.id(), CS.getReg()); + + if (MaxReg == RISCV::NoRegister) + return -1; + + switch (MaxReg) { + default: + llvm_unreachable("Something has gone wrong!"); + case /*s11*/ RISCV::X27: return 12; + case /*s10*/ RISCV::X26: return 11; + case /*s9*/ RISCV::X25: return 10; + case /*s8*/ RISCV::X24: return 9; + case /*s7*/ RISCV::X23: return 8; + case /*s6*/ RISCV::X22: return 7; + case /*s5*/ RISCV::X21: return 6; + case /*s4*/ RISCV::X20: return 5; + case /*s3*/ RISCV::X19: return 4; + case /*s2*/ RISCV::X18: return 3; + case /*s1*/ RISCV::X9: return 2; + case /*s0*/ RISCV::X8: return 1; + case /*ra*/ RISCV::X1: return 0; + } +} + +// Get the name of the libcall used for spilling callee saved registers. +// If this function will not use save/restore libcalls, then return a nullptr. +static const char * +getSpillLibCallName(const MachineFunction &MF, + const std::vector &CSI) { + static const char *const SpillLibCalls[] = { + "__riscv_save_0", + "__riscv_save_1", + "__riscv_save_2", + "__riscv_save_3", + "__riscv_save_4", + "__riscv_save_5", + "__riscv_save_6", + "__riscv_save_7", + "__riscv_save_8", + "__riscv_save_9", + "__riscv_save_10", + "__riscv_save_11", + "__riscv_save_12" + }; + + int LibCallID = getLibCallID(MF, CSI); + if (LibCallID == -1) + return nullptr; + return SpillLibCalls[LibCallID]; +} + +// Get the name of the libcall used for restoring callee saved registers. +// If this function will not use save/restore libcalls, then return a nullptr. +static const char * +getRestoreLibCallName(const MachineFunction &MF, + const std::vector &CSI) { + static const char *const RestoreLibCalls[] = { + "__riscv_restore_0", + "__riscv_restore_1", + "__riscv_restore_2", + "__riscv_restore_3", + "__riscv_restore_4", + "__riscv_restore_5", + "__riscv_restore_6", + "__riscv_restore_7", + "__riscv_restore_8", + "__riscv_restore_9", + "__riscv_restore_10", + "__riscv_restore_11", + "__riscv_restore_12" + }; + + int LibCallID = getLibCallID(MF, CSI); + if (LibCallID == -1) + return nullptr; + return RestoreLibCalls[LibCallID]; +} + bool RISCVFrameLowering::hasFP(const MachineFunction &MF) const { const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); @@ -105,6 +199,17 @@ static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; } // Returns the register used to hold the stack pointer. static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; } +static SmallVector +getNonLibcallCSI(const std::vector &CSI) { + SmallVector NonLibcallCSI; + + for (auto &CS : CSI) + if (CS.getFrameIdx() >= 0) + NonLibcallCSI.push_back(CS); + + return NonLibcallCSI; +} + void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineFrameInfo &MFI = MF.getFrameInfo(); @@ -117,6 +222,11 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, Register SPReg = getSPReg(STI); Register BPReg = RISCVABI::getBPReg(); + // Since spillCalleeSavedRegisters may have inserted a libcall, skip past + // any instructions marked as FrameSetup + while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) + ++MBBI; + // Debug location must be unknown since the first debug location is used // to determine the end of the prologue. DebugLoc DL; @@ -124,12 +234,38 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // Determine the correct frame layout determineFrameLayout(MF); + // If libcalls are used to spill and restore callee-saved registers, the frame + // has two sections; the opaque section managed by the libcalls, and the + // section managed by MachineFrameInfo which can also hold callee saved + // registers in fixed stack slots, both of which have negative frame indices. + // This gets even more complicated when incoming arguments are passed via the + // stack, as these too have negative frame indices. An example is detailed + // below: + // + // | incoming arg | <- FI[-3] + // | libcallspill | + // | calleespill | <- FI[-2] + // | calleespill | <- FI[-1] + // | this_frame | <- FI[0] + // + // For negative frame indices, the offset from the frame pointer will differ + // depending on which of these groups the frame index applies to. + // The following calculates the correct offset knowing the number of callee + // saved registers spilt by the two methods. + if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) { + // Calculate the size of the frame managed by the libcall. The libcalls are + // implemented such that the stack will always be 16 byte aligned. + unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16); + RVFI->setLibCallStackSize(LibCallFrameSize); + } + // FIXME (note copied from Lanai): This appears to be overallocating. Needs // investigation. Get the number of bytes to allocate from the FrameInfo. uint64_t StackSize = MFI.getStackSize(); + uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize(); // Early exit if there is no need to allocate on the stack - if (StackSize == 0 && !MFI.adjustsStack()) + if (RealStackSize == 0 && !MFI.adjustsStack()) return; // If the stack pointer has been marked as reserved, then produce an error if @@ -140,31 +276,42 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF); // Split the SP adjustment to reduce the offsets of callee saved spill. - if (FirstSPAdjustAmount) + if (FirstSPAdjustAmount) { StackSize = FirstSPAdjustAmount; + RealStackSize = FirstSPAdjustAmount; + } // Allocate space on the stack if necessary. adjustReg(MBB, MBBI, DL, SPReg, SPReg, -StackSize, MachineInstr::FrameSetup); - // Emit ".cfi_def_cfa_offset StackSize" + // Emit ".cfi_def_cfa_offset RealStackSize" unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize)); + MCCFIInstruction::createDefCfaOffset(nullptr, -RealStackSize)); BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); + const auto &CSI = MFI.getCalleeSavedInfo(); + // The frame pointer is callee-saved, and code has been generated for us to // save it to the stack. We need to skip over the storing of callee-saved // registers as the frame pointer must be modified after it has been saved // to the stack, not before. // FIXME: assumes exactly one instruction is used to save each callee-saved // register. - const std::vector &CSI = MFI.getCalleeSavedInfo(); - std::advance(MBBI, CSI.size()); + std::advance(MBBI, getNonLibcallCSI(CSI).size()); // Iterate over list of callee-saved registers and emit .cfi_offset // directives. for (const auto &Entry : CSI) { - int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx()); + int FrameIdx = Entry.getFrameIdx(); + int64_t Offset; + // Offsets for objects with fixed locations (IE: those saved by libcall) are + // simply calculated from the frame index. + if (FrameIdx < 0) + Offset = FrameIdx * (int64_t) STI.getXLen() / 8; + else + Offset = MFI.getObjectOffset(Entry.getFrameIdx()) - + RVFI->getLibCallStackSize(); Register Reg = Entry.getReg(); unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( nullptr, RI->getDwarfRegNum(Reg, true), Offset)); @@ -179,7 +326,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, MF.getFunction(), "Frame pointer required, but has been reserved."}); adjustReg(MBB, MBBI, DL, FPReg, SPReg, - StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup); + RealStackSize - RVFI->getVarArgsSaveSize(), + MachineInstr::FrameSetup); // Emit ".cfi_def_cfa $fp, -RVFI->getVarArgsSaveSize()" unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa( @@ -264,15 +412,26 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, // last instruction. if (!MBBI->isTerminator()) MBBI = std::next(MBBI); + + // If callee-saved registers are saved via libcall, place stack adjustment + // before this call. + while (MBBI != MBB.begin() && + std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy)) + --MBBI; } + const auto &CSI = getNonLibcallCSI(MFI.getCalleeSavedInfo()); + // Skip to before the restores of callee-saved registers // FIXME: assumes exactly one instruction is used to restore each // callee-saved register. - auto LastFrameDestroy = std::prev(MBBI, MFI.getCalleeSavedInfo().size()); + auto LastFrameDestroy = MBBI; + if (!CSI.empty()) + LastFrameDestroy = std::prev(MBBI, CSI.size()); uint64_t StackSize = MFI.getStackSize(); - uint64_t FPOffset = StackSize - RVFI->getVarArgsSaveSize(); + uint64_t RealStackSize = StackSize + RVFI->getLibCallStackSize(); + uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize(); // Restore the stack pointer using the value of the frame pointer. Only // necessary if the stack pointer was modified, meaning the stack size is @@ -310,7 +469,7 @@ int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, // Callee-saved registers should be referenced relative to the stack // pointer (positive offset), otherwise use the frame pointer (negative // offset). - const std::vector &CSI = MFI.getCalleeSavedInfo(); + const auto &CSI = getNonLibcallCSI(MFI.getCalleeSavedInfo()); int MinCSFI = 0; int MaxCSFI = -1; @@ -330,7 +489,7 @@ int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, if (FirstSPAdjustAmount) Offset += FirstSPAdjustAmount; else - Offset += MF.getFrameInfo().getStackSize(); + Offset += MFI.getStackSize(); } else if (RI->needsStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) { // If the stack was realigned, the frame pointer is set in order to allow // SP to be restored, so we need another base register to record the stack @@ -339,13 +498,20 @@ int RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, FrameReg = RISCVABI::getBPReg(); else FrameReg = RISCV::X2; - Offset += MF.getFrameInfo().getStackSize(); + Offset += MFI.getStackSize(); + if (FI < 0) + Offset += RVFI->getLibCallStackSize(); } else { FrameReg = RI->getFrameRegister(MF); - if (hasFP(MF)) + if (hasFP(MF)) { Offset += RVFI->getVarArgsSaveSize(); - else - Offset += MF.getFrameInfo().getStackSize(); + if (FI >= 0) + Offset -= RVFI->getLibCallStackSize(); + } else { + Offset += MFI.getStackSize(); + if (FI < 0) + Offset += RVFI->getLibCallStackSize(); + } } return Offset; } @@ -461,16 +627,18 @@ MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr( // add sp,sp,-64 uint64_t RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const { + const auto *RVFI = MF.getInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo(); const std::vector &CSI = MFI.getCalleeSavedInfo(); uint64_t StackSize = MFI.getStackSize(); uint64_t StackAlign = getStackAlignment(); - // FIXME: Disable SplitSPAdjust if save-restore libcall enabled when the patch - // landing. The callee saved registers will be pushed by the - // save-restore libcalls, so we don't have to split the SP adjustment - // in this case. - // + // Disable SplitSPAdjust if save-restore libcall used. The callee saved + // registers will be pushed by the save-restore libcalls, so we don't have to + // split the SP adjustment in this case. + if (RVFI->getLibCallStackSize()) + return 0; + // Return the FirstSPAdjustAmount if the StackSize can not fit in signed // 12-bit and there exists a callee saved register need to be pushed. if (!isInt<12>(StackSize) && (CSI.size() > 0)) { @@ -484,3 +652,124 @@ RISCVFrameLowering::getFirstSPAdjustAmount(const MachineFunction &MF) const { } return 0; } + +bool RISCVFrameLowering::spillCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + ArrayRef CSI, const TargetRegisterInfo *TRI) const { + if (CSI.empty()) + return true; + + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + DebugLoc DL; + if (MI != MBB.end() && !MI->isDebugInstr()) + DL = MI->getDebugLoc(); + + const char *SpillLibCall = getSpillLibCallName(*MF, CSI); + if (SpillLibCall) { + // Add spill libcall via non-callee-saved register t0. + BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5) + .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL) + .setMIFlag(MachineInstr::FrameSetup); + + // Add registers spilled in libcall as liveins. + for (auto &CS : CSI) + MBB.addLiveIn(CS.getReg()); + } + + // Manually spill values not spilled by libcall. + const auto &NonLibcallCSI = getNonLibcallCSI(CSI); + for (auto &CS : NonLibcallCSI) { + // Insert the spill to the stack frame. + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI); + } + + return true; +} + +bool RISCVFrameLowering::restoreCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + std::vector &CSI, const TargetRegisterInfo *TRI) const { + if (CSI.empty()) + return true; + + MachineFunction *MF = MBB.getParent(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + DebugLoc DL; + if (MI != MBB.end() && !MI->isDebugInstr()) + DL = MI->getDebugLoc(); + + // Manually restore values not restored by libcall. Insert in reverse order. + // loadRegFromStackSlot can insert multiple instructions. + const auto &NonLibcallCSI = getNonLibcallCSI(CSI); + for (auto &CS : reverse(NonLibcallCSI)) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI); + assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); + } + + const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI); + if (RestoreLibCall) { + // Add restore libcall via tail call. + MachineBasicBlock::iterator NewMI = + BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL)) + .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL) + .setMIFlag(MachineInstr::FrameDestroy); + + // Remove trailing returns, since the terminator is now a tail call to the + // restore function. + if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) { + NewMI->copyImplicitOps(*MF, *MI); + MI->eraseFromParent(); + } + } + + return true; +} + +bool RISCVFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { + MachineBasicBlock *TmpMBB = const_cast(&MBB); + const auto *RVFI = MBB.getParent()->getInfo(); + + if (!RVFI->useSaveRestoreLibCalls()) + return true; + + // Inserting a call to a __riscv_save libcall requires the use of the register + // t0 (X5) to hold the return address. Therefore if this register is already + // used we can't insert the call. + + RegScavenger RS; + RS.enterBasicBlock(*TmpMBB); + return !RS.isRegUsed(RISCV::X5); +} + +bool RISCVFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { + MachineBasicBlock *TmpMBB = const_cast(&MBB); + const auto *RVFI = MBB.getParent()->getInfo(); + + if (!RVFI->useSaveRestoreLibCalls()) + return true; + + // Using the __riscv_restore libcalls to restore CSRs requires a tail call. + // This means if we still need to continue executing code within this function + // the restore cannot take place in this basic block. + + if (MBB.succ_size() > 1) + return false; + + MachineBasicBlock *SuccMBB = + MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin(); + + // Doing a tail call should be safe if there are no successors, because either + // we have a returning block or the end of the block is unreachable, so the + // restore will be eliminated regardless. + if (!SuccMBB) + return true; + + // The successor can only contain a return, since we would effectively be + // replacing the successor with our own tail return at the end of our block. + return SuccMBB->isReturnBlock() && SuccMBB->size() == 1; +} diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h index 3a16cf93cf10..a032c1c0d6e1 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -46,12 +46,24 @@ public: MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override; + bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + ArrayRef CSI, + const TargetRegisterInfo *TRI) const override; + bool + restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + std::vector &CSI, + const TargetRegisterInfo *TRI) const override; // Get the first stack adjustment amount for SplitSPAdjust. // Return 0 if we don't want to to split the SP adjustment in prologue and // epilogue. uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const; + bool canUseAsPrologue(const MachineBasicBlock &MBB) const override; + bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override; + protected: const RISCVSubtarget &STI; diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h index 585bff2bc20a..593dabc95890 100644 --- a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h +++ b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h @@ -13,6 +13,7 @@ #ifndef LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H #define LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H +#include "RISCVSubtarget.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -30,6 +31,8 @@ private: /// FrameIndex used for transferring values between 64-bit FPRs and a pair /// of 32-bit GPRs via the stack. int MoveF64FrameIndex = -1; + /// Size of any opaque stack adjustment due to save/restore libcalls. + unsigned LibCallStackSize = 0; public: RISCVMachineFunctionInfo(MachineFunction &MF) : MF(MF) {} @@ -45,6 +48,16 @@ public: MoveF64FrameIndex = MF.getFrameInfo().CreateStackObject(8, 8, false); return MoveF64FrameIndex; } + + unsigned getLibCallStackSize() const { return LibCallStackSize; } + void setLibCallStackSize(unsigned Size) { LibCallStackSize = Size; } + + bool useSaveRestoreLibCalls() const { + // We cannot use fixed locations for the callee saved spill slots if the + // function uses a varargs save area. + return MF.getSubtarget().enableSaveRestore() && + VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall(); + } }; } // end namespace llvm diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 1d41994ef1e3..01116419d055 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -12,6 +12,7 @@ #include "RISCVRegisterInfo.h" #include "RISCV.h" +#include "RISCVMachineFunctionInfo.h" #include "RISCVSubtarget.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -103,6 +104,39 @@ const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { return CSR_NoRegs_RegMask; } +// Frame indexes representing locations of CSRs which are given a fixed location +// by save/restore libcalls. +static const std::map FixedCSRFIMap = { + {/*ra*/ RISCV::X1, -1}, + {/*s0*/ RISCV::X8, -2}, + {/*s1*/ RISCV::X9, -3}, + {/*s2*/ RISCV::X18, -4}, + {/*s3*/ RISCV::X19, -5}, + {/*s4*/ RISCV::X20, -6}, + {/*s5*/ RISCV::X21, -7}, + {/*s6*/ RISCV::X22, -8}, + {/*s7*/ RISCV::X23, -9}, + {/*s8*/ RISCV::X24, -10}, + {/*s9*/ RISCV::X25, -11}, + {/*s10*/ RISCV::X26, -12}, + {/*s11*/ RISCV::X27, -13} +}; + +bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, + unsigned Reg, + int &FrameIdx) const { + const auto *RVFI = MF.getInfo(); + if (!RVFI->useSaveRestoreLibCalls()) + return false; + + auto FII = FixedCSRFIMap.find(Reg); + if (FII == FixedCSRFIMap.end()) + return false; + + FrameIdx = FII->second; + return true; +} + void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h index ee5b3b767d4a..023a4ee2f1e8 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h @@ -37,6 +37,9 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo { const uint32_t *getNoPreservedMask() const override; + bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, + int &FrameIdx) const override; + void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS = nullptr) const override; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 605d4abcc9ae..5f8619e65333 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -43,6 +43,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool IsRV32E = false; bool EnableLinkerRelax = false; bool EnableRVCHintInstrs = false; + bool EnableSaveRestore = false; unsigned XLen = 32; MVT XLenVT = MVT::i32; RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; @@ -91,6 +92,7 @@ public: bool isRV32E() const { return IsRV32E; } bool enableLinkerRelax() const { return EnableLinkerRelax; } bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; } + bool enableSaveRestore() const { return EnableSaveRestore; } MVT getXLenVT() const { return XLenVT; } unsigned getXLen() const { return XLen; } RISCVABI::ABI getTargetABI() const { return TargetABI; } diff --git a/llvm/test/CodeGen/RISCV/saverestore.ll b/llvm/test/CodeGen/RISCV/saverestore.ll new file mode 100644 index 000000000000..ef1b2a52afa9 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/saverestore.ll @@ -0,0 +1,299 @@ +; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I +; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I +; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR +; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR +; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR +; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR + +; Check that the correct save/restore libcalls are generated. + +@var0 = global [18 x i32] zeroinitializer +@var1 = global [24 x i32] zeroinitializer +@var2 = global [30 x i32] zeroinitializer + +define void @callee_saved0() nounwind { +; RV32I-LABEL: callee_saved0: +; RV32I-NOT: call t0, __riscv_save +; RV32I-NOT: tail __riscv_restore +; +; RV64I-LABEL: callee_saved0: +; RV64I-NOT: call t0, __riscv_save +; RV64I-NOT: tail __riscv_restore +; +; RV32I-SR-LABEL: callee_saved0: +; RV32I-SR: call t0, __riscv_save_5 +; RV32I-SR: tail __riscv_restore_5 +; +; RV64I-SR-LABEL: callee_saved0: +; RV64I-SR: call t0, __riscv_save_5 +; RV64I-SR: tail __riscv_restore_5 +; +; RV32I-FP-SR-LABEL: callee_saved0: +; RV32I-FP-SR: call t0, __riscv_save_5 +; RV32I-FP-SR: tail __riscv_restore_5 +; +; RV64I-FP-SR-LABEL: callee_saved0: +; RV64I-FP-SR: call t0, __riscv_save_5 +; RV64I-FP-SR: tail __riscv_restore_5 + %val = load [18 x i32], [18 x i32]* @var0 + store volatile [18 x i32] %val, [18 x i32]* @var0 + ret void +} + +define void @callee_saved1() nounwind { +; RV32I-LABEL: callee_saved1: +; RV32I-NOT: call t0, __riscv_save +; RV32I-NOT: tail __riscv_restore +; +; RV64I-LABEL: callee_saved1: +; RV64I-NOT: call t0, __riscv_save +; RV64I-NOT: tail __riscv_restore +; +; RV32I-SR-LABEL: callee_saved1: +; RV32I-SR: call t0, __riscv_save_11 +; RV32I-SR: tail __riscv_restore_11 +; +; RV64I-SR-LABEL: callee_saved1: +; RV64I-SR: call t0, __riscv_save_11 +; RV64I-SR: tail __riscv_restore_11 +; +; RV32I-FP-SR-LABEL: callee_saved1: +; RV32I-FP-SR: call t0, __riscv_save_11 +; RV32I-FP-SR: tail __riscv_restore_11 +; +; RV64I-FP-SR-LABEL: callee_saved1: +; RV64I-FP-SR: call t0, __riscv_save_11 +; RV64I-FP-SR: tail __riscv_restore_11 + %val = load [24 x i32], [24 x i32]* @var1 + store volatile [24 x i32] %val, [24 x i32]* @var1 + ret void +} + +define void @callee_saved2() nounwind { +; RV32I-LABEL: callee_saved2: +; RV32I-NOT: call t0, __riscv_save +; RV32I-NOT: tail __riscv_restore +; +; RV64I-LABEL: callee_saved2: +; RV64I-NOT: call t0, __riscv_save +; RV64I-NOT: tail __riscv_restore +; +; RV32I-SR-LABEL: callee_saved2: +; RV32I-SR: call t0, __riscv_save_12 +; RV32I-SR: tail __riscv_restore_12 +; +; RV64I-SR-LABEL: callee_saved2: +; RV64I-SR: call t0, __riscv_save_12 +; RV64I-SR: tail __riscv_restore_12 +; +; RV32I-FP-SR-LABEL: callee_saved2: +; RV32I-FP-SR: call t0, __riscv_save_12 +; RV32I-FP-SR: tail __riscv_restore_12 +; +; RV64I-FP-SR-LABEL: callee_saved2: +; RV64I-FP-SR: call t0, __riscv_save_12 +; RV64I-FP-SR: tail __riscv_restore_12 + %val = load [30 x i32], [30 x i32]* @var2 + store volatile [30 x i32] %val, [30 x i32]* @var2 + ret void +} + +; Check that floating point callee saved registers are still manually saved and +; restored. + +define void @callee_saved_fp() nounwind { +; RV32I-LABEL: callee_saved_fp: +; RV32I-NOT: call t0, __riscv_save +; RV32I-NOT: tail __riscv_restore +; +; RV64I-LABEL: callee_saved_fp: +; RV64I-NOT: call t0, __riscv_save +; RV64I-NOT: tail __riscv_restore +; +; RV32I-SR-LABEL: callee_saved_fp: +; RV32I-SR: call t0, __riscv_save_7 +; RV32I-SR: tail __riscv_restore_7 +; +; RV64I-SR-LABEL: callee_saved_fp: +; RV64I-SR: call t0, __riscv_save_7 +; RV64I-SR: tail __riscv_restore_7 +; +; RV32I-FP-SR-LABEL: callee_saved_fp: +; RV32I-FP-SR: call t0, __riscv_save_7 +; RV32I-FP-SR-NEXT: addi sp, sp, -16 +; RV32I-FP-SR-NEXT: fsw fs0, 12(sp) +; RV32I-FP-SR: flw fs0, 12(sp) +; RV32I-FP-SR-NEXT: addi sp, sp, 16 +; RV32I-FP-SR-NEXT: tail __riscv_restore_7 +; +; RV64I-FP-SR-LABEL: callee_saved_fp: +; RV64I-FP-SR: call t0, __riscv_save_7 +; RV64I-FP-SR-NEXT: addi sp, sp, -16 +; RV64I-FP-SR-NEXT: fsd fs0, 8(sp) +; RV64I-FP-SR: fld fs0, 8(sp) +; RV64I-FP-SR-NEXT: addi sp, sp, 16 +; RV64I-FP-SR-NEXT: tail __riscv_restore_7 + call void asm sideeffect "", "~{f8},~{x9},~{x18},~{x19},~{x20},~{x21},~{x22}"() + ret void +} + +; Check that preserving tail calls is preferred over save/restore + +declare i32 @tail_callee(i32 %i) + +define i32 @tail_call(i32 %i) nounwind { +; RV32I-LABEL: tail_call: +; RV32I-NOT: call t0, __riscv_save +; RV32I: tail tail_callee +; RV32I-NOT: tail __riscv_restore +; +; RV64I-LABEL: tail_call: +; RV64I-NOT: call t0, __riscv_save +; RV64I: tail tail_callee +; RV64I-NOT: tail __riscv_restore +; +; RV32I-SR-LABEL: tail_call: +; RV32I-SR-NOT: call t0, __riscv_save +; RV32I-SR: tail tail_callee +; RV32I-SR-NOT: tail __riscv_restore +; +; RV64I-SR-LABEL: tail_call: +; RV64I-SR-NOT: call t0, __riscv_save +; RV64I-SR: tail tail_callee +; RV64I-SR-NOT: tail __riscv_restore +; +; RV32I-FP-SR-LABEL: tail_call: +; RV32I-FP-SR-NOT: call t0, __riscv_save +; RV32I-FP-SR: tail tail_callee +; RV32I-FP-SR-NOT: tail __riscv_restore +; +; RV64I-FP-SR-LABEL: tail_call: +; RV64I-FP-SR-NOT: call t0, __riscv_save +; RV64I-FP-SR: tail tail_callee +; RV64I-FP-SR-NOT: tail __riscv_restore +entry: + %val = load [18 x i32], [18 x i32]* @var0 + store volatile [18 x i32] %val, [18 x i32]* @var0 + %r = tail call i32 @tail_callee(i32 %i) + ret i32 %r +} + +; Check that functions with varargs do not use save/restore code + +declare void @llvm.va_start(i8*) +declare void @llvm.va_end(i8*) + +define i32 @varargs(i8* %fmt, ...) nounwind { +; RV32I-LABEL: varargs: +; RV32I-NOT: call t0, __riscv_save +; RV32I-NOT: tail __riscv_restore +; +; RV64I-LABEL: varargs: +; RV64I-NOT: call t0, __riscv_save +; RV64I-NOT: tail __riscv_restore +; +; RV32I-SR-LABEL: varargs: +; RV32I-SR-NOT: call t0, __riscv_save +; RV32I-SR-NOT: tail __riscv_restore +; +; RV64I-SR-LABEL: varargs: +; RV64I-SR-NOT: call t0, __riscv_save +; RV64I-SR-NOT: tail __riscv_restore +; +; RV32I-FP-SR-LABEL: varargs: +; RV32I-FP-SR-NOT: call t0, __riscv_save +; RV32I-FP-SR-NOT: tail __riscv_restore +; +; RV64I-FP-SR-LABEL: varargs: +; RV64I-FP-SR-NOT: call t0, __riscv_save +; RV64I-FP-SR-NOT: tail __riscv_restore + %va = alloca i8*, align 4 + %1 = bitcast i8** %va to i8* + call void @llvm.va_start(i8* %1) + %argp.cur = load i8*, i8** %va, align 4 + %argp.next = getelementptr inbounds i8, i8* %argp.cur, i32 4 + store i8* %argp.next, i8** %va, align 4 + %2 = bitcast i8* %argp.cur to i32* + %3 = load i32, i32* %2, align 4 + call void @llvm.va_end(i8* %1) + ret i32 %3 +} + +define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind { +; RV32I-LABEL: many_args: +; RV32I-NOT: call t0, __riscv_save +; RV32I-NOT: tail __riscv_restore +; +; RV64I-LABEL: many_args: +; RV64I-NOT: call t0, __riscv_save +; RV64I-NOT: tail __riscv_restore +; +; RV32I-SR-LABEL: many_args: +; RV32I-SR: call t0, __riscv_save_5 +; RV32I-SR: tail __riscv_restore_5 +; +; RV64I-SR-LABEL: many_args: +; RV64I-SR: call t0, __riscv_save_5 +; RV64I-SR: tail __riscv_restore_5 +; +; RV32I-FP-SR-LABEL: many_args: +; RV32I-FP-SR: call t0, __riscv_save_5 +; RV32I-FP-SR: tail __riscv_restore_5 +; +; RV64I-FP-SR-LABEL: many_args: +; RV64I-FP-SR: call t0, __riscv_save_5 +; RV64I-FP-SR: tail __riscv_restore_5 +entry: + %val = load [18 x i32], [18 x i32]* @var0 + store volatile [18 x i32] %val, [18 x i32]* @var0 + ret void +} + +; Check that dynamic allocation calculations remain correct + +declare i8* @llvm.stacksave() +declare void @llvm.stackrestore(i8*) +declare void @notdead(i8*) + +define void @alloca(i32 %n) nounwind { +; RV32I-LABEL: alloca: +; RV32I-NOT: call t0, __riscv_save +; RV32I: addi s0, sp, 16 +; RV32I: addi sp, s0, -16 +; RV32I-NOT: tail __riscv_restore +; +; RV64I-LABEL: alloca: +; RV64I-NOT: call t0, __riscv_save +; RV64I: addi s0, sp, 32 +; RV64I: addi sp, s0, -32 +; RV64I-NOT: tail __riscv_restore +; +; RV32I-SR-LABEL: alloca: +; RV32I-SR: call t0, __riscv_save_2 +; RV32I-SR: addi s0, sp, 16 +; RV32I-SR: addi sp, s0, -16 +; RV32I-SR: tail __riscv_restore_2 +; +; RV64I-SR-LABEL: alloca: +; RV64I-SR: call t0, __riscv_save_2 +; RV64I-SR: addi s0, sp, 32 +; RV64I-SR: addi sp, s0, -32 +; RV64I-SR: tail __riscv_restore_2 +; +; RV32I-FP-SR-LABEL: alloca: +; RV32I-FP-SR: call t0, __riscv_save_2 +; RV32I-FP-SR: addi s0, sp, 16 +; RV32I-FP-SR: addi sp, s0, -16 +; RV32I-FP-SR: tail __riscv_restore_2 +; +; RV64I-FP-SR-LABEL: alloca: +; RV64I-FP-SR: call t0, __riscv_save_2 +; RV64I-FP-SR: addi s0, sp, 32 +; RV64I-FP-SR: addi sp, s0, -32 +; RV64I-FP-SR: tail __riscv_restore_2 + %sp = call i8* @llvm.stacksave() + %addr = alloca i8, i32 %n + call void @notdead(i8* %addr) + call void @llvm.stackrestore(i8* %sp) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap.ll b/llvm/test/CodeGen/RISCV/shrinkwrap.ll index 88ff585a7a20..d8e9fdf0b7d0 100644 --- a/llvm/test/CodeGen/RISCV/shrinkwrap.ll +++ b/llvm/test/CodeGen/RISCV/shrinkwrap.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW +; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \ +; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR declare void @abort() @@ -29,6 +31,16 @@ define void @eliminate_restore(i32 %n) nounwind { ; RV32I-SW-NEXT: addi sp, sp, -16 ; RV32I-SW-NEXT: sw ra, 12(sp) ; RV32I-SW-NEXT: call abort +; +; RV32I-SW-SR-LABEL: eliminate_restore: +; RV32I-SW-SR: # %bb.0: +; RV32I-SW-SR-NEXT: addi a1, zero, 32 +; RV32I-SW-SR-NEXT: bgeu a1, a0, .LBB0_2 +; RV32I-SW-SR-NEXT: # %bb.1: # %if.end +; RV32I-SW-SR-NEXT: ret +; RV32I-SW-SR-NEXT: .LBB0_2: # %if.then +; RV32I-SW-SR-NEXT: call t0, __riscv_save_0 +; RV32I-SW-SR-NEXT: call abort %cmp = icmp ule i32 %n, 32 br i1 %cmp, label %if.then, label %if.end @@ -84,6 +96,23 @@ define void @conditional_alloca(i32 %n) nounwind { ; RV32I-SW-NEXT: addi sp, sp, 16 ; RV32I-SW-NEXT: .LBB1_2: # %if.end ; RV32I-SW-NEXT: ret +; +; RV32I-SW-SR-LABEL: conditional_alloca: +; RV32I-SW-SR: # %bb.0: +; RV32I-SW-SR-NEXT: addi a1, zero, 32 +; RV32I-SW-SR-NEXT: bltu a1, a0, .LBB1_2 +; RV32I-SW-SR-NEXT: # %bb.1: # %if.then +; RV32I-SW-SR-NEXT: call t0, __riscv_save_1 +; RV32I-SW-SR-NEXT: addi s0, sp, 16 +; RV32I-SW-SR-NEXT: addi a0, a0, 15 +; RV32I-SW-SR-NEXT: andi a0, a0, -16 +; RV32I-SW-SR-NEXT: sub a0, sp, a0 +; RV32I-SW-SR-NEXT: mv sp, a0 +; RV32I-SW-SR-NEXT: call notdead +; RV32I-SW-SR-NEXT: addi sp, s0, -16 +; RV32I-SW-SR-NEXT: tail __riscv_restore_1 +; RV32I-SW-SR-NEXT: .LBB1_2: # %if.end +; RV32I-SW-SR-NEXT: ret %cmp = icmp ule i32 %n, 32 br i1 %cmp, label %if.then, label %if.end -- GitLab From a6bd1256ce8ae5d5faf66a2ed198e0bc8674ee97 Mon Sep 17 00:00:00 2001 From: lewis-revill Date: Tue, 11 Feb 2020 21:23:18 +0000 Subject: [PATCH 069/142] [DebugInfo] Call site entries cannot be generated for FrameSetup calls Instructions marked as FrameSetup do not cause requestLabelAfterInsn to be called and so no such label is generated. Call instructions which require call site entries to be generated require this label to be present in order to calculate the return PC offset/address, but the check for whether the call instruction is marked as FrameSetup was not present. Therefore in the case where a call instruction is marked as FrameSetup, an assertion failure occurs if a call site entry is to be generated. This is the case with RISC-V's implementation of save/restore via library calls. Differential Revision: https://reviews.llvm.org/D71593 --- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 5 ++++ llvm/test/DebugInfo/RISCV/saverestore.ll | 28 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) create mode 100644 llvm/test/DebugInfo/RISCV/saverestore.ll diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index fd27f241d808..c1e7d9fe0211 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -767,6 +767,11 @@ void DwarfDebug::constructCallSiteEntryDIEs(const DISubprogram &SP, if (!MI.isCandidateForCallSiteEntry()) continue; + // Skip instructions marked as frame setup, as they are not interesting to + // the user. + if (MI.getFlag(MachineInstr::FrameSetup)) + continue; + // TODO: Add support for targets with delay slots (see: beginInstruction). if (MI.hasDelaySlot()) return; diff --git a/llvm/test/DebugInfo/RISCV/saverestore.ll b/llvm/test/DebugInfo/RISCV/saverestore.ll new file mode 100644 index 000000000000..77ece5e55ac5 --- /dev/null +++ b/llvm/test/DebugInfo/RISCV/saverestore.ll @@ -0,0 +1,28 @@ +; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s + +; Ensure that the addition of framesetup instructions which call save/restore +; libcalls do not cause a crash when DIFlagAllCallsDescribed is set. + +define i32 @main() noreturn nounwind !dbg !7 { +entry: + tail call void @exit(i32 0) + unreachable +} + +declare void @exit(i32) noreturn + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, nameTableKind: None) +!1 = !DIFile(filename: "saverestore.c", directory: ".") +!2 = !{} +!3 = !{i32 7, !"Dwarf Version", i32 5} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{!"clang"} +!7 = distinct !DISubprogram(name: "main", scope: !1, file: !1, line: 1, type: !8, scopeLine: 1, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2) +!8 = !DISubroutineType(types: !9) +!9 = !{!10} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) -- GitLab From 61ca996e79bbde58623320ea1f35423ef8a0aa64 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 11 Feb 2020 15:17:22 -0600 Subject: [PATCH 070/142] [Hexagon] Don't generate short vectors in ISD::SELECT in preprocessing Selection DAG preprocessing runs long after legalization, so make sure that the types can be handled by the selection code. --- .../Target/Hexagon/HexagonISelDAGToDAG.cpp | 13 +++++-- llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll | 35 +++++++++++++++++++ 2 files changed, 45 insertions(+), 3 deletions(-) create mode 100644 llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 481869cb8f2c..8632250fa7f5 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1187,7 +1187,7 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector &&Nodes) { Ops[i] = U->getOperand(i); EVT BVT = Ops[I1N].getValueType(); - SDLoc dl(U); + const SDLoc &dl(U); SDValue C0 = DAG.getConstant(0, dl, BVT); SDValue C1 = DAG.getConstant(1, dl, BVT); SDValue If0, If1; @@ -1205,8 +1205,15 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector &&Nodes) { Ops[I1N] = C1; If1 = DAG.getNode(UseOpc, dl, UVT, Ops); } - SDValue Sel = DAG.getNode(ISD::SELECT, dl, UVT, OpI1, If1, If0); - DAG.ReplaceAllUsesWith(U, Sel.getNode()); + // We're generating a SELECT way after legalization, so keep the types + // simple. + unsigned UW = UVT.getSizeInBits(); + EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(UW) : UVT; + SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1, + DAG.getBitcast(SVT, If1), + DAG.getBitcast(SVT, If0)); + SDValue Ret = DAG.getBitcast(UVT, Sel); + DAG.ReplaceAllUsesWith(U, Ret.getNode()); } } } diff --git a/llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll b/llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll new file mode 100644 index 000000000000..58f72a15497a --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/isel-select-v4i8.ll @@ -0,0 +1,35 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; This used to fail: +; LLVM ERROR: Cannot select: t54: v4i8 = select t50, t53, t52 + +; CHECK: jumpr r31 + +target triple = "hexagon" + +@g0 = external dso_local unnamed_addr constant [41 x i8], align 1 +define dso_local void @f0() local_unnamed_addr #0 { +b0: + %v0 = load <16 x i32>, <16 x i32>* undef, align 16 + %v1 = icmp eq <16 x i32> %v0, zeroinitializer + %v2 = or <16 x i1> %v1, zeroinitializer + %v3 = or <16 x i1> %v2, zeroinitializer + %v4 = or <16 x i1> %v3, zeroinitializer + %v5 = shufflevector <16 x i1> %v4, <16 x i1> undef, <16 x i32> + %v6 = or <16 x i1> %v4, %v5 + %v7 = extractelement <16 x i1> %v6, i32 0 + %v8 = or i1 %v7, undef + %v9 = or i1 %v8, undef + br i1 %v9, label %b2, label %b1 + +b1: ; preds = %b0 + call void (i8*, ...) @f1(i8* getelementptr inbounds ([41 x i8], [41 x i8]* @g0, i32 0, i32 0)) + unreachable + +b2: ; preds = %b0 + ret void +} +declare dso_local void @f1(i8*, ...) local_unnamed_addr #1 + +attributes #0 = { "target-cpu"="hexagonv66" "target-features"="+hvx-length64b,+hvxv66,+v66,-long-calls" } +attributes #1 = { "use-soft-float"="false" } -- GitLab From 20a604d3f5bc8cdba161e7e12f12f3f5260aad57 Mon Sep 17 00:00:00 2001 From: Max Moroz Date: Mon, 10 Feb 2020 14:25:00 -0800 Subject: [PATCH 071/142] [compiler-rt] FuzzedDataProvider: add ConsumeData and method. Reviewers: metzman Subscribers: dberris, #sanitizers, llvm-commits Tags: #sanitizers, #llvm Differential Revision: https://reviews.llvm.org/D74359 --- .../include/fuzzer/FuzzedDataProvider.h | 24 +++++++++++++++---- .../tests/FuzzedDataProviderUnittest.cpp | 19 +++++++++++++++ 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/compiler-rt/include/fuzzer/FuzzedDataProvider.h b/compiler-rt/include/fuzzer/FuzzedDataProvider.h index 3e069eba69b4..b0a37737af75 100644 --- a/compiler-rt/include/fuzzer/FuzzedDataProvider.h +++ b/compiler-rt/include/fuzzer/FuzzedDataProvider.h @@ -237,6 +237,18 @@ class FuzzedDataProvider { return result + range * ConsumeProbability(); } + // Writes |num_bytes| of input data to the given destination pointer. If there + // is not enough data left, writes all remaining bytes. Return value is the + // number of bytes written. + // In general, it's better to avoid using this function, but it may be useful + // in cases when it's necessary to fill a certain buffer or object with + // fuzzing data. + size_t ConsumeData(void *destination, size_t num_bytes) { + num_bytes = std::min(num_bytes, remaining_bytes_); + CopyAndAdvance(destination, num_bytes); + return num_bytes; + } + // Reports the remaining bytes available for fuzzed input. size_t remaining_bytes() { return remaining_bytes_; } @@ -244,6 +256,11 @@ class FuzzedDataProvider { FuzzedDataProvider(const FuzzedDataProvider &) = delete; FuzzedDataProvider &operator=(const FuzzedDataProvider &) = delete; + void CopyAndAdvance(void *destination, size_t num_bytes) { + std::memcpy(destination, data_ptr_, num_bytes); + Advance(num_bytes); + } + void Advance(size_t num_bytes) { if (num_bytes > remaining_bytes_) abort(); @@ -253,7 +270,7 @@ class FuzzedDataProvider { } template - std::vector ConsumeBytes(size_t size, size_t num_bytes_to_consume) { + std::vector ConsumeBytes(size_t size, size_t num_bytes) { static_assert(sizeof(T) == sizeof(uint8_t), "Incompatible data type."); // The point of using the size-based constructor below is to increase the @@ -264,13 +281,12 @@ class FuzzedDataProvider { // To increase the odds even more, we also call |shrink_to_fit| below. std::vector result(size); if (size == 0) { - if (num_bytes_to_consume != 0) + if (num_bytes != 0) abort(); return result; } - std::memcpy(result.data(), data_ptr_, num_bytes_to_consume); - Advance(num_bytes_to_consume); + CopyAndAdvance(result.data(), num_bytes); // Even though |shrink_to_fit| is also implementation specific, we expect it // to provide an additional assurance in case vector's constructor allocated diff --git a/compiler-rt/lib/fuzzer/tests/FuzzedDataProviderUnittest.cpp b/compiler-rt/lib/fuzzer/tests/FuzzedDataProviderUnittest.cpp index 222283434eb8..5eb46533d98a 100644 --- a/compiler-rt/lib/fuzzer/tests/FuzzedDataProviderUnittest.cpp +++ b/compiler-rt/lib/fuzzer/tests/FuzzedDataProviderUnittest.cpp @@ -399,6 +399,25 @@ TEST(FuzzedDataProvider, ConsumeFloatingPoint) { -13.37, 31.337)); } +TEST(FuzzedDataProvider, ConsumeData) { + FuzzedDataProvider DataProv(Data, sizeof(Data)); + uint8_t Buffer[10] = {}; + EXPECT_EQ(sizeof(Buffer), DataProv.ConsumeData(Buffer, sizeof(Buffer))); + std::vector Expected(Data, Data + sizeof(Buffer)); + EXPECT_EQ(Expected, std::vector(Buffer, Buffer + sizeof(Buffer))); + + EXPECT_EQ(size_t(2), DataProv.ConsumeData(Buffer, 2)); + Expected[0] = Data[sizeof(Buffer)]; + Expected[1] = Data[sizeof(Buffer) + 1]; + EXPECT_EQ(Expected, std::vector(Buffer, Buffer + sizeof(Buffer))); + + // Exhaust the buffer. + EXPECT_EQ(std::vector(Data + 12, Data + sizeof(Data)), + DataProv.ConsumeRemainingBytes()); + EXPECT_EQ(size_t(0), DataProv.ConsumeData(Buffer, sizeof(Buffer))); + EXPECT_EQ(Expected, std::vector(Buffer, Buffer + sizeof(Buffer))); +} + int main(int argc, char **argv) { testing::InitGoogleTest(&argc, argv); return RUN_ALL_TESTS(); -- GitLab From 40b2eb353043f4e526575a61b0a90fe06e938db1 Mon Sep 17 00:00:00 2001 From: Andy Davis Date: Tue, 11 Feb 2020 13:30:49 -0800 Subject: [PATCH 072/142] [mlir][AffineOps] Adds affine loop fusion transformation function to LoopFusionUtils. Summary: Adds affine loop fusion transformation function to LoopFusionUtils. Updates TestLoopFusion utility to run loop fusion transformation until a fixed point is reached. Adds unit tests to test the transformation. Includes ASAN bug fix for D73190. Reviewers: bondhugula, dcaballe Reviewed By: bondhugula, dcaballe Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, Joonsoo, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74330 --- .../include/mlir/Transforms/LoopFusionUtils.h | 5 + mlir/lib/Transforms/Utils/LoopFusionUtils.cpp | 29 +++++ .../loop-fusion-transformation.mlir | 105 ++++++++++++++++++ mlir/test/lib/Transforms/TestLoopFusion.cpp | 96 ++++++++++++---- 4 files changed, 215 insertions(+), 20 deletions(-) create mode 100644 mlir/test/Transforms/loop-fusion-transformation.mlir diff --git a/mlir/include/mlir/Transforms/LoopFusionUtils.h b/mlir/include/mlir/Transforms/LoopFusionUtils.h index f79571f523f8..2832f050fc55 100644 --- a/mlir/include/mlir/Transforms/LoopFusionUtils.h +++ b/mlir/include/mlir/Transforms/LoopFusionUtils.h @@ -51,6 +51,11 @@ FusionResult canFuseLoops(AffineForOp srcForOp, AffineForOp dstForOp, unsigned dstLoopDepth, ComputationSliceState *srcSlice); +/// Fuses 'srcForOp' into 'dstForOp' with destination loop block insertion point +/// and source slice loop bounds specified in 'srcSlice'. +void fuseLoops(AffineForOp srcForOp, AffineForOp dstForOp, + ComputationSliceState *srcSlice); + /// LoopNestStats aggregates various per-loop statistics (eg. loop trip count /// and operation count) for a loop nest up until (and including) the innermost /// loop body. diff --git a/mlir/lib/Transforms/Utils/LoopFusionUtils.cpp b/mlir/lib/Transforms/Utils/LoopFusionUtils.cpp index c5011a79c74d..2860a61f18d9 100644 --- a/mlir/lib/Transforms/Utils/LoopFusionUtils.cpp +++ b/mlir/lib/Transforms/Utils/LoopFusionUtils.cpp @@ -24,6 +24,7 @@ #include "mlir/IR/Builders.h" #include "mlir/IR/Function.h" #include "mlir/IR/Operation.h" +#include "mlir/Transforms/LoopUtils.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Debug.h" @@ -246,6 +247,34 @@ FusionResult mlir::canFuseLoops(AffineForOp srcForOp, AffineForOp dstForOp, return FusionResult::Success; } +/// Fuses 'srcForOp' into 'dstForOp' with destination loop block insertion point +/// and source slice loop bounds specified in 'srcSlice'. +void mlir::fuseLoops(AffineForOp srcForOp, AffineForOp dstForOp, + ComputationSliceState *srcSlice) { + // Clone 'srcForOp' into 'dstForOp' at 'srcSlice->insertPoint'. + OpBuilder b(srcSlice->insertPoint->getBlock(), srcSlice->insertPoint); + BlockAndValueMapping mapper; + b.clone(*srcForOp, mapper); + + // Update 'sliceLoopNest' upper and lower bounds from computed 'srcSlice'. + SmallVector sliceLoops; + for (unsigned i = 0, e = srcSlice->ivs.size(); i < e; ++i) { + auto loopIV = mapper.lookupOrNull(srcSlice->ivs[i]); + if (!loopIV) + continue; + auto forOp = getForInductionVarOwner(loopIV); + sliceLoops.push_back(forOp); + if (AffineMap lbMap = srcSlice->lbs[i]) + forOp.setLowerBound(srcSlice->lbOperands[i], lbMap); + if (AffineMap ubMap = srcSlice->ubs[i]) + forOp.setUpperBound(srcSlice->ubOperands[i], ubMap); + } + + // Promote any single iteration slice loops. + for (AffineForOp forOp : sliceLoops) + promoteIfSingleIteration(forOp); +} + /// Collect loop nest statistics (eg. loop trip count and operation count) /// in 'stats' for loop nest rooted at 'forOp'. Returns true on success, /// returns false otherwise. diff --git a/mlir/test/Transforms/loop-fusion-transformation.mlir b/mlir/test/Transforms/loop-fusion-transformation.mlir new file mode 100644 index 000000000000..1a0106301627 --- /dev/null +++ b/mlir/test/Transforms/loop-fusion-transformation.mlir @@ -0,0 +1,105 @@ +// RUN: mlir-opt %s -test-loop-fusion -test-loop-fusion-transformation -split-input-file -canonicalize | FileCheck %s + +// CHECK-LABEL: func @slice_depth1_loop_nest() { +func @slice_depth1_loop_nest() { + %0 = alloc() : memref<100xf32> + %cst = constant 7.000000e+00 : f32 + affine.for %i0 = 0 to 16 { + affine.store %cst, %0[%i0] : memref<100xf32> + } + affine.for %i1 = 0 to 5 { + %1 = affine.load %0[%i1] : memref<100xf32> + } + // CHECK: affine.for %[[IV0:.*]] = 0 to 5 { + // CHECK-NEXT: affine.store %{{.*}}, %{{.*}}[%[[IV0]]] : memref<100xf32> + // CHECK-NEXT: affine.load %{{.*}}[%[[IV0]]] : memref<100xf32> + // CHECK-NEXT: } + // CHECK-NEXT: return + return +} + +// ----- + +// CHECK-LABEL: func @should_fuse_reduction_to_pointwise() { +func @should_fuse_reduction_to_pointwise() { + %a = alloc() : memref<10x10xf32> + %b = alloc() : memref<10xf32> + %c = alloc() : memref<10xf32> + + %cf7 = constant 7.0 : f32 + + affine.for %i0 = 0 to 10 { + affine.for %i1 = 0 to 10 { + %v0 = affine.load %b[%i0] : memref<10xf32> + %v1 = affine.load %a[%i0, %i1] : memref<10x10xf32> + %v3 = addf %v0, %v1 : f32 + affine.store %v3, %b[%i0] : memref<10xf32> + } + } + affine.for %i2 = 0 to 10 { + %v4 = affine.load %b[%i2] : memref<10xf32> + affine.store %v4, %c[%i2] : memref<10xf32> + } + + // Match on the fused loop nest. + // Should fuse in entire inner loop on %i1 from source loop nest, as %i1 + // is not used in the access function of the store/load on %b. + // CHECK: affine.for %{{.*}} = 0 to 10 { + // CHECK-NEXT: affine.for %{{.*}} = 0 to 10 { + // CHECK-NEXT: affine.load %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: affine.load %{{.*}}[%{{.*}}, %{{.*}}] : memref<10x10xf32> + // CHECK-NEXT: addf %{{.*}}, %{{.*}} : f32 + // CHECK-NEXT: affine.store %{{.*}}, %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: } + // CHECK-NEXT: affine.load %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: affine.store %{{.*}}, %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: } + // CHECK-NEXT: return + return +} + +// ----- + +// CHECK-LABEL: func @should_fuse_avoiding_dependence_cycle() { +func @should_fuse_avoiding_dependence_cycle() { + %a = alloc() : memref<10xf32> + %b = alloc() : memref<10xf32> + %c = alloc() : memref<10xf32> + + %cf7 = constant 7.0 : f32 + + // Set up the following dependences: + // 1) loop0 -> loop1 on memref '%{{.*}}' + // 2) loop0 -> loop2 on memref '%{{.*}}' + // 3) loop1 -> loop2 on memref '%{{.*}}' + affine.for %i0 = 0 to 10 { + %v0 = affine.load %a[%i0] : memref<10xf32> + affine.store %cf7, %b[%i0] : memref<10xf32> + } + affine.for %i1 = 0 to 10 { + affine.store %cf7, %a[%i1] : memref<10xf32> + %v1 = affine.load %c[%i1] : memref<10xf32> + } + affine.for %i2 = 0 to 10 { + %v2 = affine.load %b[%i2] : memref<10xf32> + affine.store %cf7, %c[%i2] : memref<10xf32> + } + // Fusing loop first loop into last would create a cycle: + // {1} <--> {0, 2} + // However, we can avoid the dependence cycle if we first fuse loop0 into + // loop1: + // {0, 1) --> {2} + // Then fuse this loop nest with loop2: + // {0, 1, 2} + // + // CHECK: affine.for %{{.*}} = 0 to 10 { + // CHECK-NEXT: affine.load %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: affine.store %{{.*}}, %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: affine.store %{{.*}}, %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: affine.load %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: affine.load %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: affine.store %{{.*}}, %{{.*}}[%{{.*}}] : memref<10xf32> + // CHECK-NEXT: } + // CHECK-NEXT: return + return +} diff --git a/mlir/test/lib/Transforms/TestLoopFusion.cpp b/mlir/test/lib/Transforms/TestLoopFusion.cpp index 4a4e5f9c05f6..93e6fd450160 100644 --- a/mlir/test/lib/Transforms/TestLoopFusion.cpp +++ b/mlir/test/lib/Transforms/TestLoopFusion.cpp @@ -41,6 +41,11 @@ static llvm::cl::opt clTestSliceComputation( llvm::cl::desc("Enable testing of loop fusion slice computation"), llvm::cl::cat(clOptionsCategory)); +static llvm::cl::opt clTestLoopFusionTransformation( + "test-loop-fusion-transformation", + llvm::cl::desc("Enable testing of loop fusion transformation"), + llvm::cl::cat(clOptionsCategory)); + namespace { struct TestLoopFusion : public FunctionPass { @@ -69,11 +74,10 @@ gatherLoops(Block *block, unsigned currLoopDepth, // Run fusion dependence check on 'loops[i]' and 'loops[j]' at loop depths // in range ['loopDepth' + 1, 'maxLoopDepth']. // Emits a remark on 'loops[i]' if a fusion-preventing dependence exists. -static void testDependenceCheck(SmallVector &loops, unsigned i, - unsigned j, unsigned loopDepth, +// Returns false as IR is not transformed. +static bool testDependenceCheck(AffineForOp srcForOp, AffineForOp dstForOp, + unsigned i, unsigned j, unsigned loopDepth, unsigned maxLoopDepth) { - AffineForOp srcForOp = loops[i]; - AffineForOp dstForOp = loops[j]; mlir::ComputationSliceState sliceUnion; for (unsigned d = loopDepth + 1; d <= maxLoopDepth; ++d) { FusionResult result = @@ -84,6 +88,7 @@ static void testDependenceCheck(SmallVector &loops, unsigned i, << i << " into loop nest " << j << " at depth " << loopDepth; } } + return false; } // Returns the index of 'op' in its block. @@ -121,11 +126,10 @@ static std::string getSliceStr(const mlir::ComputationSliceState &sliceUnion) { // Computes fusion slice union on 'loops[i]' and 'loops[j]' at loop depths // in range ['loopDepth' + 1, 'maxLoopDepth']. // Emits a string representation of the slice union as a remark on 'loops[j]'. -static void testSliceComputation(SmallVector &loops, unsigned i, - unsigned j, unsigned loopDepth, +// Returns false as IR is not transformed. +static bool testSliceComputation(AffineForOp forOpA, AffineForOp forOpB, + unsigned i, unsigned j, unsigned loopDepth, unsigned maxLoopDepth) { - AffineForOp forOpA = loops[i]; - AffineForOp forOpB = loops[j]; for (unsigned d = loopDepth + 1; d <= maxLoopDepth; ++d) { mlir::ComputationSliceState sliceUnion; FusionResult result = mlir::canFuseLoops(forOpA, forOpB, d, &sliceUnion); @@ -135,31 +139,83 @@ static void testSliceComputation(SmallVector &loops, unsigned i, << " : " << getSliceStr(sliceUnion) << ")"; } } + return false; } -void TestLoopFusion::runOnFunction() { - // Gather all AffineForOps by loop depth. - DenseMap> depthToLoops; - for (auto &block : getFunction()) { - gatherLoops(&block, /*currLoopDepth=*/0, depthToLoops); +// Attempts to fuse 'forOpA' into 'forOpB' at loop depths in range +// ['loopDepth' + 1, 'maxLoopDepth']. +// Returns true if loops were successfully fused, false otherwise. +static bool testLoopFusionTransformation(AffineForOp forOpA, AffineForOp forOpB, + unsigned i, unsigned j, + unsigned loopDepth, + unsigned maxLoopDepth) { + for (unsigned d = loopDepth + 1; d <= maxLoopDepth; ++d) { + mlir::ComputationSliceState sliceUnion; + FusionResult result = mlir::canFuseLoops(forOpA, forOpB, d, &sliceUnion); + if (result.value == FusionResult::Success) { + mlir::fuseLoops(forOpA, forOpB, &sliceUnion); + // Note: 'forOpA' is removed to simplify test output. A proper loop + // fusion pass should check the data dependence graph and run memref + // region analysis to ensure removing 'forOpA' is safe. + forOpA.erase(); + return true; + } } + return false; +} - // Run tests on all combinations of src/dst loop nests in 'depthToLoops'. +using LoopFunc = function_ref; + +// Run tests on all combinations of src/dst loop nests in 'depthToLoops'. +// If 'return_on_change' is true, returns on first invocation of 'fn' which +// returns true. +static bool +iterateLoops(DenseMap> &depthToLoops, + LoopFunc fn, bool return_on_change = false) { + bool changed = false; for (auto &depthAndLoops : depthToLoops) { unsigned loopDepth = depthAndLoops.first; auto &loops = depthAndLoops.second; unsigned numLoops = loops.size(); for (unsigned j = 0; j < numLoops; ++j) { for (unsigned k = 0; k < numLoops; ++k) { - if (j == k) - continue; - if (clTestDependenceCheck) - testDependenceCheck(loops, j, k, loopDepth, depthToLoops.size()); - if (clTestSliceComputation) - testSliceComputation(loops, j, k, loopDepth, depthToLoops.size()); + if (j != k) + changed |= + fn(loops[j], loops[k], j, k, loopDepth, depthToLoops.size()); + if (changed && return_on_change) + return true; } } } + return changed; +} + +void TestLoopFusion::runOnFunction() { + DenseMap> depthToLoops; + if (clTestLoopFusionTransformation) { + // Run loop fusion until a fixed point is reached. + do { + depthToLoops.clear(); + // Gather all AffineForOps by loop depth. + for (auto &block : getFunction()) + gatherLoops(&block, /*currLoopDepth=*/0, depthToLoops); + + // Try to fuse all combinations of src/dst loop nests in 'depthToLoops'. + } while (iterateLoops(depthToLoops, testLoopFusionTransformation, + /*return_on_change=*/true)); + return; + } + + // Gather all AffineForOps by loop depth. + for (Block &block : getFunction()) + gatherLoops(&block, /*currLoopDepth=*/0, depthToLoops); + + // Run tests on all combinations of src/dst loop nests in 'depthToLoops'. + if (clTestDependenceCheck) + iterateLoops(depthToLoops, testDependenceCheck); + if (clTestSliceComputation) + iterateLoops(depthToLoops, testSliceComputation); } static PassRegistration -- GitLab From 14f870366a93ba0c6311883d900e24339681ba76 Mon Sep 17 00:00:00 2001 From: Ian Levesque Date: Tue, 11 Feb 2020 13:52:45 -0800 Subject: [PATCH 073/142] [xray][clang] Always add xray-skip-entry/exit and xray-ignore-loops attrs The function attributes xray-skip-entry, xray-skip-exit, and xray-ignore-loops were only being applied if a function had an xray-instrument attribute, but they should apply if xray is enabled globally too. Differential Revision: https://reviews.llvm.org/D73842 --- clang/include/clang/Driver/XRayArgs.h | 1 + clang/lib/CodeGen/CodeGenFunction.cpp | 22 ++++++++++--------- clang/lib/Driver/XRayArgs.cpp | 7 ++++++ clang/lib/Frontend/CompilerInvocation.cpp | 3 +-- .../xray-attributes-skip-entry-exit.cpp | 22 +++++++++++++++++++ clang/test/CodeGen/xray-ignore-loops.cpp | 2 +- .../Driver/XRay/xray-ignore-loops-flags.cpp | 10 +++++++++ 7 files changed, 54 insertions(+), 13 deletions(-) create mode 100644 clang/test/CodeGen/xray-attributes-skip-entry-exit.cpp create mode 100644 clang/test/Driver/XRay/xray-ignore-loops-flags.cpp diff --git a/clang/include/clang/Driver/XRayArgs.h b/clang/include/clang/Driver/XRayArgs.h index fa2583f4b966..96098bf629cd 100644 --- a/clang/include/clang/Driver/XRayArgs.h +++ b/clang/include/clang/Driver/XRayArgs.h @@ -30,6 +30,7 @@ class XRayArgs { bool XRayAlwaysEmitCustomEvents = false; bool XRayAlwaysEmitTypedEvents = false; bool XRayRT = true; + bool XRayIgnoreLoops = false; public: /// Parses the XRay arguments from an argument list. diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index af0adc213580..b7506b53030d 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -814,23 +814,25 @@ void CodeGenFunction::StartFunction(GlobalDecl GD, QualType RetTy, if (ShouldXRayInstrumentFunction()) Fn->addFnAttr("xray-log-args", llvm::utostr(LogArgs->getArgumentCount())); - if (!CGM.getCodeGenOpts().XRayInstrumentationBundle.has( - XRayInstrKind::FunctionExit)) { - Fn->addFnAttr("xray-skip-exit"); - } - if (!CGM.getCodeGenOpts().XRayInstrumentationBundle.has( - XRayInstrKind::FunctionEntry)) { - Fn->addFnAttr("xray-skip-entry"); - } } } else { if (ShouldXRayInstrumentFunction() && !CGM.imbueXRayAttrs(Fn, Loc)) Fn->addFnAttr( "xray-instruction-threshold", llvm::itostr(CGM.getCodeGenOpts().XRayInstructionThreshold)); - if (CGM.getCodeGenOpts().XRayIgnoreLoops) { + } + + if (ShouldXRayInstrumentFunction()) { + if (CGM.getCodeGenOpts().XRayIgnoreLoops) Fn->addFnAttr("xray-ignore-loops"); - } + + if (!CGM.getCodeGenOpts().XRayInstrumentationBundle.has( + XRayInstrKind::FunctionExit)) + Fn->addFnAttr("xray-skip-exit"); + + if (!CGM.getCodeGenOpts().XRayInstrumentationBundle.has( + XRayInstrKind::FunctionEntry)) + Fn->addFnAttr("xray-skip-entry"); } unsigned Count, Offset; diff --git a/clang/lib/Driver/XRayArgs.cpp b/clang/lib/Driver/XRayArgs.cpp index 66c3959648ac..54c15685d389 100644 --- a/clang/lib/Driver/XRayArgs.cpp +++ b/clang/lib/Driver/XRayArgs.cpp @@ -101,6 +101,10 @@ XRayArgs::XRayArgs(const ToolChain &TC, const ArgList &Args) { options::OPT_fnoxray_link_deps, true)) XRayRT = false; + if (Args.hasFlag(options::OPT_fxray_ignore_loops, + options::OPT_fno_xray_ignore_loops, false)) + XRayIgnoreLoops = true; + auto Bundles = Args.getAllArgValues(options::OPT_fxray_instrumentation_bundle); if (Bundles.empty()) @@ -197,6 +201,9 @@ void XRayArgs::addArgs(const ToolChain &TC, const ArgList &Args, if (XRayAlwaysEmitTypedEvents) CmdArgs.push_back("-fxray-always-emit-typedevents"); + if (XRayIgnoreLoops) + CmdArgs.push_back("-fxray-ignore-loops"); + CmdArgs.push_back(Args.MakeArgString(Twine(XRayInstructionThresholdOption) + Twine(InstructionThreshold))); diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index e57c7ef55bb5..ae39066edd4c 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1099,8 +1099,7 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK, Args.hasArg(OPT_fxray_always_emit_typedevents); Opts.XRayInstructionThreshold = getLastArgIntValue(Args, OPT_fxray_instruction_threshold_EQ, 200, Diags); - Opts.XRayIgnoreLoops = - Args.hasArg(OPT_fxray_ignore_loops, OPT_fno_xray_ignore_loops, false); + Opts.XRayIgnoreLoops = Args.hasArg(OPT_fxray_ignore_loops); auto XRayInstrBundles = Args.getAllArgValues(OPT_fxray_instrumentation_bundle); diff --git a/clang/test/CodeGen/xray-attributes-skip-entry-exit.cpp b/clang/test/CodeGen/xray-attributes-skip-entry-exit.cpp new file mode 100644 index 000000000000..e23262fd5dbc --- /dev/null +++ b/clang/test/CodeGen/xray-attributes-skip-entry-exit.cpp @@ -0,0 +1,22 @@ +// RUN: %clang_cc1 -fxray-instrument \ +// RUN: -fxray-instrumentation-bundle=function-entry -x c++ \ +// RUN: -std=c++11 -triple x86_64-unknown-unknown -emit-llvm -o - %s \ +// RUN: | FileCheck --check-prefixes CHECK,SKIPEXIT %s +// RUN: %clang_cc1 -fxray-instrument \ +// RUN: -fxray-instrumentation-bundle=function-exit -x c++ \ +// RUN: -std=c++11 -triple x86_64-unknown-unknown -emit-llvm -o - %s \ +// RUN: | FileCheck --check-prefixes CHECK,SKIPENTRY %s +// RUN: %clang_cc1 -fxray-instrument \ +// RUN: -fxray-instrumentation-bundle=function-entry,function-exit -x c++ \ +// RUN: -std=c++11 -triple x86_64-unknown-unknown -emit-llvm -o - %s \ +// RUN: | FileCheck --check-prefixes CHECK,NOSKIPENTRY,NOSKIPEXIT %s + +// CHECK: define void @_Z13justAFunctionv() #[[ATTR:[0-9]+]] { +void justAFunction() { +} + +// SKIPENTRY: attributes #[[ATTR]] = {{.*}} "xray-skip-entry" {{.*}} +// SKIPEXIT: attributes #[[ATTR]] = {{.*}} "xray-skip-exit" {{.*}} + +// NOSKIPENTRY-NOT: attributes #[[ATTR]] = {{.*}} "xray-skip-entry" {{.*}} +// NOSKIPEXIT-NOT: attributes #[[ATTR]] = {{.*}} "xray-skip-exit" {{.*}} diff --git a/clang/test/CodeGen/xray-ignore-loops.cpp b/clang/test/CodeGen/xray-ignore-loops.cpp index 17ea2afbeece..ed918b8f9b31 100644 --- a/clang/test/CodeGen/xray-ignore-loops.cpp +++ b/clang/test/CodeGen/xray-ignore-loops.cpp @@ -4,5 +4,5 @@ int foo() { return 1; } -// CHECK: define i32 @_Z3foov() #[[ATTRS:[0-9]+]] { +// CHECK: define{{.*}} i32 @_Z3foov() #[[ATTRS:[0-9]+]] { // CHECK-DAG: attributes #[[ATTRS]] = {{.*}} "xray-ignore-loops" {{.*}} diff --git a/clang/test/Driver/XRay/xray-ignore-loops-flags.cpp b/clang/test/Driver/XRay/xray-ignore-loops-flags.cpp new file mode 100644 index 000000000000..476786fc639a --- /dev/null +++ b/clang/test/Driver/XRay/xray-ignore-loops-flags.cpp @@ -0,0 +1,10 @@ +// This test ensures that when we invoke the clang compiler, that the -cc1 +// options include the -fxray-ignore-loops flag we provide in the +// invocation. +// +// RUN: %clang -fxray-instrument -fxray-ignore-loops -target x86_64-linux- -### \ +// RUN: -x c++ -std=c++11 -emit-llvm -c -o - %s 2>&1 \ +// RUN: | FileCheck %s +// CHECK: -fxray-ignore-loops +// +// REQUIRES: x86_64 || x86_64h -- GitLab From 88de9338f26c3c75001c17a5c4b71736e18fa0b6 Mon Sep 17 00:00:00 2001 From: Huihui Zhang Date: Tue, 11 Feb 2020 14:04:45 -0800 Subject: [PATCH 074/142] [ConstantFold][SVE] Fix constand fold for vector call. Summary: Do not iterate on scalable vectors. Reviewers: sdesmalen, efriedma, apazos, huntergr, willlovett Reviewed By: sdesmalen Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74419 --- llvm/lib/Analysis/ConstantFolding.cpp | 5 +++++ llvm/test/Analysis/ConstantFolding/vscale.ll | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp index 280a13ff1153..0ebc6a5919e8 100644 --- a/llvm/lib/Analysis/ConstantFolding.cpp +++ b/llvm/lib/Analysis/ConstantFolding.cpp @@ -2400,6 +2400,11 @@ static Constant *ConstantFoldVectorCall(StringRef Name, SmallVector Lane(Operands.size()); Type *Ty = VTy->getElementType(); + // Do not iterate on scalable vector. The number of elements is unknown at + // compile-time. + if (VTy->getVectorIsScalable()) + return nullptr; + if (IntrinsicID == Intrinsic::masked_load) { auto *SrcPtr = Operands[0]; auto *Mask = Operands[2]; diff --git a/llvm/test/Analysis/ConstantFolding/vscale.ll b/llvm/test/Analysis/ConstantFolding/vscale.ll index 2491308910df..3a3d6a16c7d6 100644 --- a/llvm/test/Analysis/ConstantFolding/vscale.ll +++ b/llvm/test/Analysis/ConstantFolding/vscale.ll @@ -210,3 +210,14 @@ define @select() { %r = select undef, zeroinitializer, undef ret %r } + +declare @llvm.sadd.sat.nxv16i8(, ) + +define @call() { +; CHECK-LABEL: @call( +; CHECK-NEXT: [[R:%.*]] = call @llvm.sadd.sat.nxv16i8( undef, undef) +; CHECK-NEXT: ret [[R]] +; + %r = call @llvm.sadd.sat.nxv16i8( undef, undef) + ret %r +} -- GitLab From 3fcdf2fa945aca5849c5587c55de4186c7d81b8a Mon Sep 17 00:00:00 2001 From: Melanie Blower Date: Tue, 11 Feb 2020 12:39:53 -0800 Subject: [PATCH 075/142] Change clang option -ffp-model=precise to select ffp-contract=on Reviewers: rjmccall Differential Revision: https://reviews.llvm.org/D74436 --- clang/docs/UsersManual.rst | 48 +++++++++++++++++++++++++-- clang/lib/Driver/ToolChains/Clang.cpp | 16 ++++----- clang/test/CodeGen/ppc-emmintrin.c | 4 +-- clang/test/CodeGen/ppc-xmmintrin.c | 4 +-- clang/test/Driver/fp-model.c | 7 ++-- 5 files changed, 60 insertions(+), 19 deletions(-) diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 856d5e34bbcc..6c8c9f802082 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -1190,8 +1190,50 @@ installed. Controlling Floating Point Behavior ----------------------------------- -Clang provides a number of ways to control floating point behavior. The options -are listed below. +Clang provides a number of ways to control floating point behavior, including +with command line options and source pragmas. This section +describes the various floating point semantic modes and the corresponding options. + +.. csv-table:: Floating Point Semantic Modes + :header: "Mode", "Values" + :widths: 15, 30, 30 + + "except_behavior", "{ignore, strict, may_trap}", "ffp-exception-behavior" + "fenv_access", "{off, on}", "(none)" + "rounding_mode", "{dynamic, tonearest, downward, upward, towardzero}", "frounding-math" + "contract", "{on, off, fast}", "ffp-contract" + "denormal_fp_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math" + "denormal_fp32_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math-fp32" + "support_math_errno", "{on, off}", "fmath-errno" + "no_honor_nans", "{on, off}", "fhonor-nans" + "no_honor_infinities", "{on, off}", "fhonor-infinities" + "no_signed_zeros", "{on, off}", "fsigned-zeros" + "allow_reciprocal", "{on, off}", "freciprocal-math" + "allow_approximate_fns", "{on, off}", "(none)" + "allow_reassociation", "{on, off}", "fassociative-math" + + +This table describes the option settings that correspond to the three +floating point semantic models: precise (the default), strict, and fast. + + +.. csv-table:: Floating Point Models + :header: "Mode", "Precise", "Strict", "Fast" + :widths: 25, 15, 15, 15 + + "except_behavior", "ignore", "strict", "ignore" + "fenv_access", "off", "on", "off" + "rounding_mode", "tonearest", "dynamic", "tonearest" + "contract", "on", "off", "fast" + "denormal_fp_math", "IEEE", "IEEE", "PreserveSign" + "denormal_fp32_math", "IEEE","IEEE", "PreserveSign" + "support_math_errno", "on", "on", "off" + "no_honor_nans", "off", "off", "on" + "no_honor_infinities", "off", "off", "on" + "no_signed_zeros", "off", "off", "on" + "allow_reciprocal", "off", "off", "on" + "allow_approximate_fns", "off", "off", "on" + "allow_reassociation", "off", "off", "on" .. option:: -ffast-math @@ -1385,7 +1427,7 @@ Note that floating-point operations performed as part of constant initialization and ``fast``. Details: - * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=fast``). This is the default behavior. + * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=on``). This is the default behavior. * ``strict`` Enables ``-frounding-math`` and ``-ffp-exception-behavior=strict``, and disables contractions (FMA). All of the ``-ffast-math`` enablements are disabled. * ``fast`` Behaves identically to specifying both ``-ffast-math`` and ``ffp-contract=fast`` diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 7901f8a48f5f..c70659bf1485 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2520,10 +2520,9 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, llvm::DenormalMode DenormalFPMath = DefaultDenormalFPMath; llvm::DenormalMode DenormalFP32Math = DefaultDenormalFP32Math; - StringRef FPContract = ""; + StringRef FPContract = "on"; bool StrictFPModel = false; - if (const Arg *A = Args.getLastArg(options::OPT_flimited_precision_EQ)) { CmdArgs.push_back("-mlimit-float-precision"); CmdArgs.push_back(A->getValue()); @@ -2560,12 +2559,10 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // ffp-model= is a Driver option, it is entirely rewritten into more // granular options before being passed into cc1. // Use the gcc option in the switch below. - if (!FPModel.empty() && !FPModel.equals(Val)) { + if (!FPModel.empty() && !FPModel.equals(Val)) D.Diag(clang::diag::warn_drv_overriding_flag_option) << Args.MakeArgString("-ffp-model=" + FPModel) << Args.MakeArgString("-ffp-model=" + Val); - FPContract = ""; - } if (Val.equals("fast")) { optID = options::OPT_ffast_math; FPModel = Val; @@ -2573,13 +2570,14 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, } else if (Val.equals("precise")) { optID = options::OPT_ffp_contract; FPModel = Val; - FPContract = "fast"; + FPContract = "on"; PreciseFPModel = true; } else if (Val.equals("strict")) { StrictFPModel = true; optID = options::OPT_frounding_math; FPExceptionBehavior = "strict"; FPModel = Val; + FPContract = "off"; TrappingMath = true; } else D.Diag(diag::err_drv_unsupported_option_argument) @@ -2658,7 +2656,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_ffp_contract: { StringRef Val = A->getValue(); if (PreciseFPModel) { - // -ffp-model=precise enables ffp-contract=fast as a side effect + // -ffp-model=precise enables ffp-contract=on as a side effect // the FPContract value has already been set to a string literal // and the Val string isn't a pertinent value. ; @@ -2757,7 +2755,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // -fno_fast_math restores default denormal and fpcontract handling DenormalFPMath = DefaultDenormalFPMath; DenormalFP32Math = DefaultDenormalFP32Math; - FPContract = ""; + FPContract = "on"; break; } if (StrictFPModel) { @@ -2768,7 +2766,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, !AssociativeMath && !ReciprocalMath && SignedZeros && TrappingMath && RoundingFPMath && DenormalFPMath != llvm::DenormalMode::getIEEE() && - FPContract.empty()) + (FPContract.equals("off") || FPContract.empty())) // OK: Current Arg doesn't conflict with -ffp-model=strict ; else { diff --git a/clang/test/CodeGen/ppc-emmintrin.c b/clang/test/CodeGen/ppc-emmintrin.c index 631b6c9d2614..c14b2dd210f8 100644 --- a/clang/test/CodeGen/ppc-emmintrin.c +++ b/clang/test/CodeGen/ppc-emmintrin.c @@ -2,9 +2,9 @@ // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE // CHECK-BE-DAG: @_mm_movemask_pd.perm_mask = internal constant <4 x i32> , align 16 // CHECK-BE-DAG: @_mm_shuffle_epi32.permute_selectors = internal constant [4 x i32] [i32 66051, i32 67438087, i32 134810123, i32 202182159], align 4 diff --git a/clang/test/CodeGen/ppc-xmmintrin.c b/clang/test/CodeGen/ppc-xmmintrin.c index e9466b32257f..d7499cbedc48 100644 --- a/clang/test/CodeGen/ppc-xmmintrin.c +++ b/clang/test/CodeGen/ppc-xmmintrin.c @@ -2,9 +2,9 @@ // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE #include diff --git a/clang/test/Driver/fp-model.c b/clang/test/Driver/fp-model.c index a3984acef62b..8ebbc1803c65 100644 --- a/clang/test/Driver/fp-model.c +++ b/clang/test/Driver/fp-model.c @@ -27,9 +27,9 @@ // RUN: | FileCheck --check-prefix=WARN5 %s // WARN5: warning: overriding '-ffp-model=strict' option with '-ffp-contract=fast' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -ffp-contract=off -c %s 2>&1 \ +// RUN: %clang -### -ffp-model=strict -ffp-contract=fast -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN6 %s -// WARN6: warning: overriding '-ffp-model=strict' option with '-ffp-contract=off' [-Woverriding-t-option] +// WARN6: warning: overriding '-ffp-model=strict' option with '-ffp-contract=fast' [-Woverriding-t-option] // RUN: %clang -### -ffp-model=strict -ffp-contract=on -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN7 %s @@ -100,13 +100,14 @@ // RUN: %clang -### -nostdinc -ffp-model=precise -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-PRECISE %s // CHECK-FPM-PRECISE: "-cc1" -// CHECK-FPM-PRECISE: "-ffp-contract=fast" +// CHECK-FPM-PRECISE: "-ffp-contract=on" // CHECK-FPM-PRECISE: "-fno-rounding-math" // RUN: %clang -### -nostdinc -ffp-model=strict -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-STRICT %s // CHECK-FPM-STRICT: "-cc1" // CHECK-FPM-STRICT: "-ftrapping-math" +// CHECK-FPM-STRICT: "-ffp-contract=off" // CHECK-FPM-STRICT: "-frounding-math" // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict" -- GitLab From 99c5bcbce89f07e68ccd89891a0300346705d013 Mon Sep 17 00:00:00 2001 From: Melanie Blower Date: Tue, 11 Feb 2020 14:20:00 -0800 Subject: [PATCH 076/142] Revert "Change clang option -ffp-model=precise to select ffp-contract=on" This reverts commit 3fcdf2fa945aca5849c5587c55de4186c7d81b8a. Sorry I was too hasty with my commit, I will review Andy's comments and resubmit. --- clang/docs/UsersManual.rst | 48 ++------------------------- clang/lib/Driver/ToolChains/Clang.cpp | 16 +++++---- clang/test/CodeGen/ppc-emmintrin.c | 4 +-- clang/test/CodeGen/ppc-xmmintrin.c | 4 +-- clang/test/Driver/fp-model.c | 7 ++-- 5 files changed, 19 insertions(+), 60 deletions(-) diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 6c8c9f802082..856d5e34bbcc 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -1190,50 +1190,8 @@ installed. Controlling Floating Point Behavior ----------------------------------- -Clang provides a number of ways to control floating point behavior, including -with command line options and source pragmas. This section -describes the various floating point semantic modes and the corresponding options. - -.. csv-table:: Floating Point Semantic Modes - :header: "Mode", "Values" - :widths: 15, 30, 30 - - "except_behavior", "{ignore, strict, may_trap}", "ffp-exception-behavior" - "fenv_access", "{off, on}", "(none)" - "rounding_mode", "{dynamic, tonearest, downward, upward, towardzero}", "frounding-math" - "contract", "{on, off, fast}", "ffp-contract" - "denormal_fp_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math" - "denormal_fp32_math", "{IEEE, PreserveSign, PositiveZero}", "fdenormal-fp-math-fp32" - "support_math_errno", "{on, off}", "fmath-errno" - "no_honor_nans", "{on, off}", "fhonor-nans" - "no_honor_infinities", "{on, off}", "fhonor-infinities" - "no_signed_zeros", "{on, off}", "fsigned-zeros" - "allow_reciprocal", "{on, off}", "freciprocal-math" - "allow_approximate_fns", "{on, off}", "(none)" - "allow_reassociation", "{on, off}", "fassociative-math" - - -This table describes the option settings that correspond to the three -floating point semantic models: precise (the default), strict, and fast. - - -.. csv-table:: Floating Point Models - :header: "Mode", "Precise", "Strict", "Fast" - :widths: 25, 15, 15, 15 - - "except_behavior", "ignore", "strict", "ignore" - "fenv_access", "off", "on", "off" - "rounding_mode", "tonearest", "dynamic", "tonearest" - "contract", "on", "off", "fast" - "denormal_fp_math", "IEEE", "IEEE", "PreserveSign" - "denormal_fp32_math", "IEEE","IEEE", "PreserveSign" - "support_math_errno", "on", "on", "off" - "no_honor_nans", "off", "off", "on" - "no_honor_infinities", "off", "off", "on" - "no_signed_zeros", "off", "off", "on" - "allow_reciprocal", "off", "off", "on" - "allow_approximate_fns", "off", "off", "on" - "allow_reassociation", "off", "off", "on" +Clang provides a number of ways to control floating point behavior. The options +are listed below. .. option:: -ffast-math @@ -1427,7 +1385,7 @@ Note that floating-point operations performed as part of constant initialization and ``fast``. Details: - * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=on``). This is the default behavior. + * ``precise`` Disables optimizations that are not value-safe on floating-point data, although FP contraction (FMA) is enabled (``-ffp-contract=fast``). This is the default behavior. * ``strict`` Enables ``-frounding-math`` and ``-ffp-exception-behavior=strict``, and disables contractions (FMA). All of the ``-ffast-math`` enablements are disabled. * ``fast`` Behaves identically to specifying both ``-ffast-math`` and ``ffp-contract=fast`` diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index c70659bf1485..7901f8a48f5f 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2520,9 +2520,10 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, llvm::DenormalMode DenormalFPMath = DefaultDenormalFPMath; llvm::DenormalMode DenormalFP32Math = DefaultDenormalFP32Math; - StringRef FPContract = "on"; + StringRef FPContract = ""; bool StrictFPModel = false; + if (const Arg *A = Args.getLastArg(options::OPT_flimited_precision_EQ)) { CmdArgs.push_back("-mlimit-float-precision"); CmdArgs.push_back(A->getValue()); @@ -2559,10 +2560,12 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // ffp-model= is a Driver option, it is entirely rewritten into more // granular options before being passed into cc1. // Use the gcc option in the switch below. - if (!FPModel.empty() && !FPModel.equals(Val)) + if (!FPModel.empty() && !FPModel.equals(Val)) { D.Diag(clang::diag::warn_drv_overriding_flag_option) << Args.MakeArgString("-ffp-model=" + FPModel) << Args.MakeArgString("-ffp-model=" + Val); + FPContract = ""; + } if (Val.equals("fast")) { optID = options::OPT_ffast_math; FPModel = Val; @@ -2570,14 +2573,13 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, } else if (Val.equals("precise")) { optID = options::OPT_ffp_contract; FPModel = Val; - FPContract = "on"; + FPContract = "fast"; PreciseFPModel = true; } else if (Val.equals("strict")) { StrictFPModel = true; optID = options::OPT_frounding_math; FPExceptionBehavior = "strict"; FPModel = Val; - FPContract = "off"; TrappingMath = true; } else D.Diag(diag::err_drv_unsupported_option_argument) @@ -2656,7 +2658,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_ffp_contract: { StringRef Val = A->getValue(); if (PreciseFPModel) { - // -ffp-model=precise enables ffp-contract=on as a side effect + // -ffp-model=precise enables ffp-contract=fast as a side effect // the FPContract value has already been set to a string literal // and the Val string isn't a pertinent value. ; @@ -2755,7 +2757,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // -fno_fast_math restores default denormal and fpcontract handling DenormalFPMath = DefaultDenormalFPMath; DenormalFP32Math = DefaultDenormalFP32Math; - FPContract = "on"; + FPContract = ""; break; } if (StrictFPModel) { @@ -2766,7 +2768,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, !AssociativeMath && !ReciprocalMath && SignedZeros && TrappingMath && RoundingFPMath && DenormalFPMath != llvm::DenormalMode::getIEEE() && - (FPContract.equals("off") || FPContract.empty())) + FPContract.empty()) // OK: Current Arg doesn't conflict with -ffp-model=strict ; else { diff --git a/clang/test/CodeGen/ppc-emmintrin.c b/clang/test/CodeGen/ppc-emmintrin.c index c14b2dd210f8..631b6c9d2614 100644 --- a/clang/test/CodeGen/ppc-emmintrin.c +++ b/clang/test/CodeGen/ppc-emmintrin.c @@ -2,9 +2,9 @@ // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE // CHECK-BE-DAG: @_mm_movemask_pd.perm_mask = internal constant <4 x i32> , align 16 // CHECK-BE-DAG: @_mm_shuffle_epi32.permute_selectors = internal constant [4 x i32] [i32 66051, i32 67438087, i32 134810123, i32 202182159], align 4 diff --git a/clang/test/CodeGen/ppc-xmmintrin.c b/clang/test/CodeGen/ppc-xmmintrin.c index d7499cbedc48..e9466b32257f 100644 --- a/clang/test/CodeGen/ppc-xmmintrin.c +++ b/clang/test/CodeGen/ppc-xmmintrin.c @@ -2,9 +2,9 @@ // REQUIRES: powerpc-registered-target // RUN: %clang -S -emit-llvm -target powerpc64-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-BE // RUN: %clang -S -emit-llvm -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ffreestanding -DNO_WARN_X86_INTRINSICS %s \ -// RUN: -ffp-contract=off -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: -fno-discard-value-names -mllvm -disable-llvm-optzns -o - | llvm-cxxfilt -n | FileCheck %s --check-prefixes=CHECK,CHECK-LE #include diff --git a/clang/test/Driver/fp-model.c b/clang/test/Driver/fp-model.c index 8ebbc1803c65..a3984acef62b 100644 --- a/clang/test/Driver/fp-model.c +++ b/clang/test/Driver/fp-model.c @@ -27,9 +27,9 @@ // RUN: | FileCheck --check-prefix=WARN5 %s // WARN5: warning: overriding '-ffp-model=strict' option with '-ffp-contract=fast' [-Woverriding-t-option] -// RUN: %clang -### -ffp-model=strict -ffp-contract=fast -c %s 2>&1 \ +// RUN: %clang -### -ffp-model=strict -ffp-contract=off -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN6 %s -// WARN6: warning: overriding '-ffp-model=strict' option with '-ffp-contract=fast' [-Woverriding-t-option] +// WARN6: warning: overriding '-ffp-model=strict' option with '-ffp-contract=off' [-Woverriding-t-option] // RUN: %clang -### -ffp-model=strict -ffp-contract=on -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN7 %s @@ -100,14 +100,13 @@ // RUN: %clang -### -nostdinc -ffp-model=precise -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-PRECISE %s // CHECK-FPM-PRECISE: "-cc1" -// CHECK-FPM-PRECISE: "-ffp-contract=on" +// CHECK-FPM-PRECISE: "-ffp-contract=fast" // CHECK-FPM-PRECISE: "-fno-rounding-math" // RUN: %clang -### -nostdinc -ffp-model=strict -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-FPM-STRICT %s // CHECK-FPM-STRICT: "-cc1" // CHECK-FPM-STRICT: "-ftrapping-math" -// CHECK-FPM-STRICT: "-ffp-contract=off" // CHECK-FPM-STRICT: "-frounding-math" // CHECK-FPM-STRICT: "-ffp-exception-behavior=strict" -- GitLab From d538dc05f3b50653b97c13b446121ac16c364a14 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Tue, 11 Feb 2020 14:04:51 -0800 Subject: [PATCH 077/142] [AMDGPU] Fixed subreg use in sdwa-scalar-ops.mir. NFC --- llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir b/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir index 2e96d2129ec5..ed12cdd9d25b 100644 --- a/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir +++ b/llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir @@ -219,7 +219,7 @@ body: | %13 = COPY %7.sub1 %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc - %16 = REG_SEQUENCE %14, 1, %15, 2 + %16 = REG_SEQUENCE %14, %subreg.sub0, %15, %subreg.sub1 %18 = COPY %16 %17 = FLAT_LOAD_DWORD %18, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.uglygep45) %60 = V_BFE_U32 %17, 8, 8, implicit $exec @@ -227,23 +227,23 @@ body: | %70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec %66 = COPY %13 %65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec - %67 = REG_SEQUENCE %70, 1, killed %65, 2 + %67 = REG_SEQUENCE %70, %subreg.sub0, killed %65, %subreg.sub1 FLAT_STORE_DWORD %67, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp9) %37 = S_ADD_U32 %14, 4, implicit-def $scc %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc %71 = COPY killed %37 %72 = COPY killed %38 - %41 = REG_SEQUENCE killed %71, 1, killed %72, 2 + %41 = REG_SEQUENCE killed %71, %subreg.sub0, killed %72, %subreg.sub1 %40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.scevgep) %73 = V_BFE_U32 %40, 8, 8, implicit $exec %74 = V_LSHLREV_B32_e32 2, killed %73, implicit $exec %83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec %78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec - %80 = REG_SEQUENCE %83, 1, killed %78, 2 + %80 = REG_SEQUENCE %83, %subreg.sub0, killed %78, %subreg.sub1 FLAT_STORE_DWORD %80, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp17) %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc - %57 = REG_SEQUENCE %55, 1, killed %56, 2 + %57 = REG_SEQUENCE %55, %subreg.sub0, killed %56, %subreg.sub1 %1 = COPY %57 S_CMPK_EQ_I32 %55, 4096, implicit-def $scc S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc @@ -382,7 +382,7 @@ body: | %13 = COPY %7.sub1 %14 = S_ADD_U32 %7.sub0, %0.sub0, implicit-def $scc %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead $scc, implicit $scc - %16 = REG_SEQUENCE %14, 1, %15, 2 + %16 = REG_SEQUENCE %14, %subreg.sub0, %15, %subreg.sub1 %18 = COPY %16 %17 = FLAT_LOAD_DWORD %18, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.uglygep45) %60 = V_BFE_U32 %17, 8, 8, implicit $exec @@ -390,23 +390,23 @@ body: | %70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def $vcc, implicit $exec %66 = COPY %13 %65 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec - %67 = REG_SEQUENCE %70, 1, killed %65, 2 + %67 = REG_SEQUENCE %70, %subreg.sub0, killed %65, %subreg.sub1 FLAT_STORE_DWORD %67, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp9) %37 = S_ADD_U32 %14, 4, implicit-def $scc %38 = S_ADDC_U32 %15, 0, implicit-def dead $scc, implicit $scc %71 = COPY killed %37 %72 = COPY killed %38 - %41 = REG_SEQUENCE killed %71, 1, killed %72, 2 + %41 = REG_SEQUENCE killed %71, %subreg.sub0, killed %72, %subreg.sub1 %40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %ir.scevgep) %73 = V_BFE_U32 %40, 8, 8, implicit $exec %74 = V_LSHLREV_B32_e32 %84, killed %73, implicit $exec %83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def $vcc, implicit $exec %78 = V_ADDC_U32_e32 0, %66, implicit-def $vcc, implicit $vcc, implicit $exec - %80 = REG_SEQUENCE %83, 1, killed %78, 2 + %80 = REG_SEQUENCE %83, %subreg.sub0, killed %78, %subreg.sub1 FLAT_STORE_DWORD %80, %30, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %ir.tmp17) %55 = S_ADD_U32 %0.sub0, 8, implicit-def $scc %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead $scc, implicit $scc - %57 = REG_SEQUENCE %55, 1, killed %56, 2 + %57 = REG_SEQUENCE %55, %subreg.sub0, killed %56, %subreg.sub1 %1 = COPY %57 S_CMPK_EQ_I32 %55, 4096, implicit-def $scc S_CBRANCH_SCC1 %bb.1.bb1, implicit $scc -- GitLab From 1698cc7ebabe47be6cf225960e55ddb8a884d118 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Thu, 31 Oct 2019 22:45:17 -0500 Subject: [PATCH 078/142] [Utils] Allow "on-the-fly" argument changes for update_test_check scripts Update test scripts were limited because they performed a single action on the entire file and if that action was controlled by arguments, like the one introduced in D68819, there was no record of it. This patch introduces the capability of changing the arguments passed to the script "on-the-fly" while processing a test file. In addition, an "on/off" switch was added so that processing can be disabled for parts of the file where the content is simply copied. The last extension is a record of the invocation arguments in the auto generated NOTE. These arguments are also picked up in a subsequent invocation, allowing updates with special options enabled without user interaction. To change the arguments the string `UTC_ARGS:` has to be present in a line, followed by "additional command line arguments". That is everything that follows `UTC_ARGS:` will be added to a growing list of "command line arguments" which is reparsed after every update. Reviewed By: arichardson Differential Revision: https://reviews.llvm.org/D69701 --- llvm/test/Transforms/Attributor/align.ll | 4 +- llvm/test/Transforms/Attributor/liveness.ll | 11 ++--- .../Inputs/argument_name_reuse.ll.expected | 2 +- .../Inputs/basic.ll.funcsig.expected | 2 +- .../Inputs/on_the_fly_arg_change.ll | 30 +++++++++++++ .../Inputs/on_the_fly_arg_change.ll.expected | 45 +++++++++++++++++++ .../Inputs/scrub_attrs.ll.scrub.expected | 2 +- .../update_test_checks/basic.test | 7 ++- .../on_the_fly_arg_change.test | 6 +++ .../update_test_checks/scrub_attrs.test | 6 +-- llvm/utils/UpdateTestChecks/common.py | 26 +++++++++++ llvm/utils/update_test_checks.py | 23 +++++++--- 12 files changed, 144 insertions(+), 20 deletions(-) create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/on_the_fly_arg_change.ll create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/on_the_fly_arg_change.ll.expected create mode 100644 llvm/test/tools/UpdateTestChecks/update_test_checks/on_the_fly_arg_change.test diff --git a/llvm/test/Transforms/Attributor/align.ll b/llvm/test/Transforms/Attributor/align.ll index 13f524d9b059..3d4a761d0812 100644 --- a/llvm/test/Transforms/Attributor/align.ll +++ b/llvm/test/Transforms/Attributor/align.ll @@ -133,7 +133,7 @@ define internal i8* @f3(i8* readnone %0) local_unnamed_addr #0 { ret i8* %6 } -; UTC_ARGS: --turn=on +; UTC_ARGS: --enable ; TEST 7 ; Better than IR information @@ -264,7 +264,7 @@ define align 4 i32* @test7b(i32* align 32 %p) #0 { ret i32* %p } -; UTC_ARGS: --turn=off +; UTC_ARGS: --disable ; TEST 8 define void @test8_helper() { diff --git a/llvm/test/Transforms/Attributor/liveness.ll b/llvm/test/Transforms/Attributor/liveness.ll index 4f1cc36f14ce..92142f06d4ee 100644 --- a/llvm/test/Transforms/Attributor/liveness.ll +++ b/llvm/test/Transforms/Attributor/liveness.ll @@ -3,7 +3,7 @@ ; RUN: opt -attributor-cgscc --attributor-disable=false -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,CGSCC ; RUN: opt -passes=attributor --attributor-disable=false -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,MODULE,ALL_BUT_OLD_CGSCCC ; RUN: opt -passes='attributor-cgscc' --attributor-disable=false -attributor-annotate-decl-cs -attributor-max-iterations=6 -S < %s | FileCheck %s --check-prefixes=CHECK,CGSCC,ALL_BUT_OLD_CGSCCC -; UTC_ARGS: --turn off +; UTC_ARGS: --disable ; ALL_BUT_OLD_CGSCCC: @dead_with_blockaddress_users.l = constant [2 x i8*] [i8* inttoptr (i32 1 to i8*), i8* inttoptr (i32 1 to i8*)] @dead_with_blockaddress_users.l = constant [2 x i8*] [i8* blockaddress(@dead_with_blockaddress_users, %lab0), i8* blockaddress(@dead_with_blockaddress_users, %end)] @@ -280,7 +280,7 @@ cleanup: ret i32 0 } -; UTC_ARGS: --turn on +; UTC_ARGS: --enable ; TEST 5.4 unounwind invoke instruction replaced by a call and a branch instruction put after it. define i32 @invoke_nounwind_phi(i32 %a) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { @@ -370,7 +370,7 @@ cleanup: ret i32 0 } -; UTC_ARGS: --turn off +; UTC_ARGS: --disable ; TEST 6: Undefined behvior, taken from LangRef. ; FIXME: Should be able to detect undefined behavior. @@ -894,7 +894,7 @@ define void @useless_arg_ext_int_ext(i32* %a) { ret void } -; UTC_ARGS: --turn on +; UTC_ARGS: --enable ; FIXME: We should fold terminators. @@ -956,7 +956,8 @@ define i32 @switch_default_dead_caller() { %call2 = tail call i32 @switch_default_dead(i64 0) ret i32 %call2 } -; UTC_ARGS: --turn off + +; UTC_ARGS: --disable ; Allow blockaddress users ; ALL_BUT_OLD_CGSCCC-NOT @dead_with_blockaddress_users diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/argument_name_reuse.ll.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/argument_name_reuse.ll.expected index ee9582663e2a..461a8b6a5bf6 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/argument_name_reuse.ll.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/argument_name_reuse.ll.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature ; RUN: opt < %s -S | FileCheck %s define i32 @reuse_arg_names(i32 %X, i32 %Y) { diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/basic.ll.funcsig.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/basic.ll.funcsig.expected index 103b58115c19..d97d1b8f77bc 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/basic.ll.funcsig.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/basic.ll.funcsig.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature ; Example input for update_llc_test_checks (taken from test/Transforms/InstSimplify/add.ll) ; RUN: opt < %s -instsimplify -S | FileCheck %s diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/on_the_fly_arg_change.ll b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/on_the_fly_arg_change.ll new file mode 100644 index 000000000000..7c54acae5cc7 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/on_the_fly_arg_change.ll @@ -0,0 +1,30 @@ +; RUN: opt -S < %s | FileCheck %s + +declare void @foo() + +define void @check_lines_1() { + ret void +} + +; UTC_ARGS: --disable + +; A check line that would not be auto generated. +; CHECK: define void @no_check_lines() { +define void @no_check_lines() { + ret void +} + +; UTC_ARGS: --enable + +define void @check_lines_2() { + ret void +} + +define void @scrub() { + call void @foo() readnone + ret void +} + +define i32 @signature(i32 %arg) { + ret i32 %arg +} diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/on_the_fly_arg_change.ll.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/on_the_fly_arg_change.ll.expected new file mode 100644 index 000000000000..b76f62c9cb13 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/on_the_fly_arg_change.ll.expected @@ -0,0 +1,45 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes +; RUN: opt -S < %s | FileCheck %s + +declare void @foo() + +define void @check_lines_1() { +; CHECK-LABEL: define {{[^@]+}}@check_lines_1() +; CHECK-NEXT: ret void +; + ret void +} + +; UTC_ARGS: --disable + +; A check line that would not be auto generated. +; CHECK: define void @no_check_lines() { +define void @no_check_lines() { + ret void +} + +; UTC_ARGS: --enable + +define void @check_lines_2() { +; CHECK-LABEL: define {{[^@]+}}@check_lines_2() +; CHECK-NEXT: ret void +; + ret void +} + +define void @scrub() { +; CHECK-LABEL: define {{[^@]+}}@scrub() +; CHECK-NEXT: call void @foo() +; CHECK-NEXT: ret void +; + call void @foo() readnone + ret void +} + +define i32 @signature(i32 %arg) { +; CHECK-LABEL: define {{[^@]+}}@signature +; CHECK-SAME: (i32 [[ARG:%.*]]) +; CHECK-NEXT: ret i32 [[ARG]] +; + ret i32 %arg +} diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scrub_attrs.ll.scrub.expected b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scrub_attrs.ll.scrub.expected index cbea04a09719..0674a8938e1f 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scrub_attrs.ll.scrub.expected +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/scrub_attrs.ll.scrub.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --scrub-attributes ; RUN: opt -S < %s | FileCheck %s declare void @foo() diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/basic.test b/llvm/test/tools/UpdateTestChecks/update_test_checks/basic.test index 023cccc481ee..2227ead65470 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/basic.test +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/basic.test @@ -8,6 +8,9 @@ ## Also try the --function-signature flag # RUN: %update_test_checks %t.ll --function-signature # RUN: diff -u %t.ll %S/Inputs/basic.ll.funcsig.expected -## Verify that running without the --function-signature flag removes the -SAME: lines: +## Verify that running without the --function-signature flag does not removes +## the -SAME: lines since the generated file will have --function-signature in +## an UTC_ARGS: comment in the first line (from the invocation above) which is +## added to the update invocation below. # RUN: %update_test_checks %t.ll -# RUN: diff -u %t.ll %S/Inputs/basic.ll.expected +# RUN: diff -u %t.ll %S/Inputs/basic.ll.funcsig.expected diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/on_the_fly_arg_change.test b/llvm/test/tools/UpdateTestChecks/update_test_checks/on_the_fly_arg_change.test new file mode 100644 index 000000000000..bb5f6367cd05 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/on_the_fly_arg_change.test @@ -0,0 +1,6 @@ +# RUN: cp -f %S/Inputs/on_the_fly_arg_change.ll %t.ll +# RUN: %update_test_checks %t.ll --function-signature --scrub-attributes +# RUN: diff -u %t.ll %S/Inputs/on_the_fly_arg_change.ll.expected +## Check that running the script again does not change the result: +# RUN: %update_test_checks %t.ll +# RUN: diff -u %t.ll %S/Inputs/on_the_fly_arg_change.ll.expected diff --git a/llvm/test/tools/UpdateTestChecks/update_test_checks/scrub_attrs.test b/llvm/test/tools/UpdateTestChecks/update_test_checks/scrub_attrs.test index 0adfb8440b36..63a5c9c9aa87 100644 --- a/llvm/test/tools/UpdateTestChecks/update_test_checks/scrub_attrs.test +++ b/llvm/test/tools/UpdateTestChecks/update_test_checks/scrub_attrs.test @@ -1,9 +1,9 @@ ## scrub_attrs test checking that update_test_checks.py works correctly # RUN: cp -f %S/Inputs/scrub_attrs.ll %t.ll && %update_test_checks %t.ll # RUN: diff -u %t.ll %S/Inputs/scrub_attrs.ll.plain.expected -## Check that running the script again does not change the result: -# RUN: %update_test_checks %t.ll -# RUN: diff -u %t.ll %S/Inputs/scrub_attrs.ll.plain.expected ## Also try the --scrub-attributes flag # RUN: %update_test_checks %t.ll --scrub-attributes # RUN: diff -u %t.ll %S/Inputs/scrub_attrs.ll.scrub.expected +## Check that running the script again does not change the result: +# RUN: %update_test_checks %t.ll +# RUN: diff -u %t.ll %S/Inputs/scrub_attrs.ll.scrub.expected diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py index ae4621c76978..f3a87a07037c 100644 --- a/llvm/utils/UpdateTestChecks/common.py +++ b/llvm/utils/UpdateTestChecks/common.py @@ -63,6 +63,9 @@ CHECK_PREFIX_RE = re.compile(r'--?check-prefix(?:es)?[= ](\S+)') PREFIX_RE = re.compile('^[a-zA-Z0-9_-]+$') CHECK_RE = re.compile(r'^\s*(?://|[;#])\s*([^:]+?)(?:-NEXT|-NOT|-DAG|-LABEL|-SAME|-EMPTY)?:') +UTC_ARGS_KEY = 'UTC_ARGS:' +UTC_ARGS_CMD = re.compile(r'.*' + UTC_ARGS_KEY + '\s*(?P.*)\s*$') + OPT_FUNCTION_RE = re.compile( r'^\s*define\s+(?:internal\s+)?[^@]*@(?P[\w-]+?)\s*' r'(?P\((\)|(.*?[\w\.\-]+?)\))[^{]*)\{\n(?P.*?)^\}$', @@ -396,3 +399,26 @@ def verify_filecheck_prefixes(fc_cmd): check_prefix(prefix) if prefixes.count(prefix) > 1: warn("Supplied prefix '%s' is not unique in the prefix list." % (prefix,)) + +def get_autogennote_suffix(parser, args): + autogenerated_note_args = '' + for k, v in args._get_kwargs(): + if parser.get_default(k) == v or k == 'tests' or k == 'update_only' or k == 'opt_binary': + continue + k = k.replace('_', '-') + if type(v) is bool: + autogenerated_note_args += '--%s ' % (k) + else: + autogenerated_note_args += '--%s %s ' % (k, v) + if autogenerated_note_args: + autogenerated_note_args = ' %s %s' % (UTC_ARGS_KEY, autogenerated_note_args[:-1]) + return autogenerated_note_args + + +def check_for_command(line, parser, args, argv): + cmd_m = UTC_ARGS_CMD.match(line) + if cmd_m: + cmd = cmd_m.group('cmd').strip().split(' ') + argv = argv + cmd + args = parser.parse_args(filter(lambda arg: arg not in args.tests, argv)) + return args, argv diff --git a/llvm/utils/update_test_checks.py b/llvm/utils/update_test_checks.py index 94e3fef1fcad..a54cbbb40ba8 100755 --- a/llvm/utils/update_test_checks.py +++ b/llvm/utils/update_test_checks.py @@ -66,6 +66,10 @@ def main(): help='Keep function signature information around for the check line') parser.add_argument('--scrub-attributes', action='store_true', help='Remove attribute annotations (#0) from the end of check line') + parser.add_argument('--enable', action='store_true', dest='enabled', default=True, + help='Activate CHECK line generation from this point forward') + parser.add_argument('--disable', action='store_false', dest='enabled', + help='Deativate CHECK line generation from this point forward') parser.add_argument('tests', nargs='+') args = common.parse_commandline_args(parser) @@ -86,6 +90,8 @@ def main(): # On Windows we must expand the patterns ourselves. test_paths = [test for pattern in args.tests for test in glob.glob(pattern)] for test in test_paths: + argv = sys.argv[:] + args = parser.parse_args() with open(test) as f: input_lines = [l.rstrip() for l in f] @@ -93,6 +99,9 @@ def main(): if 'autogenerated' in first_line and script_name not in first_line: common.warn("Skipping test which wasn't autogenerated by " + script_name, test) continue + if first_line and 'autogenerated' in first_line: + args, argv = common.check_for_command(first_line, parser, args, argv) + test_autogenerated_note = autogenerated_note + common.get_autogennote_suffix(parser, args) if args.update_only: if not first_line or 'autogenerated' not in first_line: @@ -154,9 +163,17 @@ def main(): prefix_set = set([prefix for prefixes, _ in prefix_list for prefix in prefixes]) common.debug('Rewriting FileCheck prefixes:', str(prefix_set)) output_lines = [] - output_lines.append(autogenerated_note) + output_lines.append(test_autogenerated_note) for input_line in input_lines: + # Discard any previous script advertising. + if input_line.startswith(ADVERT): + continue + + args, argv = common.check_for_command(input_line, parser, args, argv) + if not args.enabled: + output_lines.append(input_line) + continue if is_in_function_start: if input_line == '': continue @@ -183,10 +200,6 @@ def main(): is_in_function = False continue - # Discard any previous script advertising. - if input_line.startswith(ADVERT): - continue - # If it's outside a function, it just gets copied to the output. output_lines.append(input_line) -- GitLab From 846d0ac43eb95c7f2f7e98b076b42c8c3208f506 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 11 Feb 2020 13:14:03 -0800 Subject: [PATCH 079/142] [X86] Don't disable code in combineHorizontalPredicateResult just because we have avx512 We aren't doing a good job of optimizing AVX512 outside of this code. So remove the bail out for AVX512 and replace with a FIXME. This at least gets us the AVX2 codegen. Differential Revision: https://reviews.llvm.org/D74431 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 5 +- .../test/CodeGen/X86/vector-compare-all_of.ll | 197 ++++++++---------- .../test/CodeGen/X86/vector-compare-any_of.ll | 165 +++++---------- 3 files changed, 134 insertions(+), 233 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f5a101196d09..4321bb79d857 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -37359,10 +37359,7 @@ static SDValue combineHorizontalPredicateResult(SDNode *Extract, return SDValue(); Movmsk = DAG.getZExtOrTrunc(Movmsk, DL, NumElts > 32 ? MVT::i64 : MVT::i32); } else { - // Bail with AVX512VL (which uses predicate registers). - if (Subtarget.hasVLX()) - return SDValue(); - + // FIXME: Better handling of k-registers or 512-bit vectors? unsigned MatchSizeInBits = Match.getValueSizeInBits(); if (!(MatchSizeInBits == 128 || (MatchSizeInBits == 256 && Subtarget.hasAVX()))) diff --git a/llvm/test/CodeGen/X86/vector-compare-all_of.ll b/llvm/test/CodeGen/X86/vector-compare-all_of.ll index 02c9f4f17fd4..4348edf5b7c2 100644 --- a/llvm/test/CodeGen/X86/vector-compare-all_of.ll +++ b/llvm/test/CodeGen/X86/vector-compare-all_of.ll @@ -28,9 +28,11 @@ define i64 @test_v2f64_sext(<2 x double> %a0, <2 x double> %a1) { ; AVX512-LABEL: test_v2f64_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vandpd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovq %xmm0, %rax +; AVX512-NEXT: vmovmskpd %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $3, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negq %rax ; AVX512-NEXT: retq %c = fcmp ogt <2 x double> %a0, %a1 %s = sext <2 x i1> %c to <2 x i64> @@ -67,11 +69,11 @@ define i64 @test_v4f64_sext(<4 x double> %a0, <4 x double> %a1) { ; AVX512-LABEL: test_v4f64_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 -; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vandpd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vandpd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovq %xmm0, %rax +; AVX512-NEXT: vmovmskpd %ymm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $15, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negq %rax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = fcmp ogt <4 x double> %a0, %a1 @@ -115,12 +117,11 @@ define i64 @test_v4f64_legal_sext(<4 x double> %a0, <4 x double> %a1) { ; AVX512-NEXT: vcmpltpd %ymm0, %ymm1, %k1 ; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: cltq +; AVX512-NEXT: vmovmskps %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $15, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negq %rax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = fcmp ogt <4 x double> %a0, %a1 @@ -158,11 +159,11 @@ define i32 @test_v4f32_sext(<4 x float> %a0, <4 x float> %a1) { ; AVX512-LABEL: test_v4f32_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltps %xmm0, %xmm1, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovmskps %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $15, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negl %eax ; AVX512-NEXT: retq %c = fcmp ogt <4 x float> %a0, %a1 %s = sext <4 x i1> %c to <4 x i32> @@ -201,13 +202,11 @@ define i32 @test_v8f32_sext(<8 x float> %a0, <8 x float> %a1) { ; AVX512-LABEL: test_v8f32_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltps %ymm0, %ymm1, %ymm0 -; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovmskps %ymm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $255, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negl %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = fcmp ogt <8 x float> %a0, %a1 @@ -252,14 +251,11 @@ define i32 @test_v8f32_legal_sext(<8 x float> %a0, <8 x float> %a1) { ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltps %ymm0, %ymm1, %k0 ; AVX512-NEXT: vpmovm2w %k0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: cwtl +; AVX512-NEXT: vpmovmskb %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $65535, %ecx # imm = 0xFFFF +; AVX512-NEXT: sete %al +; AVX512-NEXT: negl %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = fcmp ogt <8 x float> %a0, %a1 @@ -299,9 +295,11 @@ define i64 @test_v2i64_sext(<2 x i64> %a0, <2 x i64> %a1) { ; AVX512-LABEL: test_v2i64_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovq %xmm0, %rax +; AVX512-NEXT: vmovmskpd %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $3, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negq %rax ; AVX512-NEXT: retq %c = icmp sgt <2 x i64> %a0, %a1 %s = sext <2 x i1> %c to <2 x i64> @@ -353,11 +351,11 @@ define i64 @test_v4i64_sext(<4 x i64> %a0, <4 x i64> %a1) { ; AVX512-LABEL: test_v4i64_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovq %xmm0, %rax +; AVX512-NEXT: vmovmskpd %ymm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $15, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negq %rax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <4 x i64> %a0, %a1 @@ -416,12 +414,11 @@ define i64 @test_v4i64_legal_sext(<4 x i64> %a0, <4 x i64> %a1) { ; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %k1 ; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: cltq +; AVX512-NEXT: vmovmskps %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $15, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negq %rax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <4 x i64> %a0, %a1 @@ -459,11 +456,11 @@ define i32 @test_v4i32_sext(<4 x i32> %a0, <4 x i32> %a1) { ; AVX512-LABEL: test_v4i32_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovmskps %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $15, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negl %eax ; AVX512-NEXT: retq %c = icmp sgt <4 x i32> %a0, %a1 %s = sext <4 x i1> %c to <4 x i32> @@ -517,13 +514,11 @@ define i32 @test_v8i32_sext(<8 x i32> %a0, <8 x i32> %a1) { ; AVX512-LABEL: test_v8i32_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovmskps %ymm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $255, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negl %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <8 x i32> %a0, %a1 @@ -583,14 +578,11 @@ define i32 @test_v8i32_legal_sext(<8 x i32> %a0, <8 x i32> %a1) { ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; AVX512-NEXT: vpmovm2w %k0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: cwtl +; AVX512-NEXT: vpmovmskb %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $65535, %ecx # imm = 0xFFFF +; AVX512-NEXT: sete %al +; AVX512-NEXT: negl %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <8 x i32> %a0, %a1 @@ -632,13 +624,11 @@ define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) { ; AVX512-LABEL: test_v8i16_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vpmovmskb %xmm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $65535, %ecx # imm = 0xFFFF +; AVX512-NEXT: sete %al +; AVX512-NEXT: negl %eax ; AVX512-NEXT: # kill: def $ax killed $ax killed $eax ; AVX512-NEXT: retq %c = icmp sgt <8 x i16> %a0, %a1 @@ -698,15 +688,11 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX512-LABEL: test_v16i16_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vpmovmskb %ymm0, %ecx +; AVX512-NEXT: xorl %eax, %eax +; AVX512-NEXT: cmpl $-1, %ecx +; AVX512-NEXT: sete %al +; AVX512-NEXT: negl %eax ; AVX512-NEXT: # kill: def $ax killed $ax killed $eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq @@ -772,15 +758,10 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 ; AVX512-NEXT: vpmovm2b %k0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpextrb $0, %xmm0, %eax +; AVX512-NEXT: vpmovmskb %xmm0, %eax +; AVX512-NEXT: cmpl $65535, %eax # imm = 0xFFFF +; AVX512-NEXT: sete %al +; AVX512-NEXT: negb %al ; AVX512-NEXT: movsbl %al, %eax ; AVX512-NEXT: # kill: def $ax killed $ax killed $eax ; AVX512-NEXT: vzeroupper @@ -822,16 +803,10 @@ define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) { ; AVX512-LABEL: test_v16i8_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpextrb $0, %xmm0, %eax -; AVX512-NEXT: # kill: def $al killed $al killed $eax +; AVX512-NEXT: vpmovmskb %xmm0, %eax +; AVX512-NEXT: cmpl $65535, %eax # imm = 0xFFFF +; AVX512-NEXT: sete %al +; AVX512-NEXT: negb %al ; AVX512-NEXT: retq %c = icmp sgt <16 x i8> %a0, %a1 %s = sext <16 x i1> %c to <16 x i8> @@ -886,18 +861,10 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; AVX512-LABEL: test_v32i8_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpextrb $0, %xmm0, %eax -; AVX512-NEXT: # kill: def $al killed $al killed $eax +; AVX512-NEXT: vpmovmskb %ymm0, %eax +; AVX512-NEXT: cmpl $-1, %eax +; AVX512-NEXT: sete %al +; AVX512-NEXT: negb %al ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <32 x i8> %a0, %a1 diff --git a/llvm/test/CodeGen/X86/vector-compare-any_of.ll b/llvm/test/CodeGen/X86/vector-compare-any_of.ll index 084de61dd086..b3443b9707b7 100644 --- a/llvm/test/CodeGen/X86/vector-compare-any_of.ll +++ b/llvm/test/CodeGen/X86/vector-compare-any_of.ll @@ -24,9 +24,9 @@ define i64 @test_v2f64_sext(<2 x double> %a0, <2 x double> %a1) { ; AVX512-LABEL: test_v2f64_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vorpd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovq %xmm0, %rax +; AVX512-NEXT: vmovmskpd %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbq %rax, %rax ; AVX512-NEXT: retq %c = fcmp ogt <2 x double> %a0, %a1 %s = sext <2 x i1> %c to <2 x i64> @@ -59,11 +59,9 @@ define i64 @test_v4f64_sext(<4 x double> %a0, <4 x double> %a1) { ; AVX512-LABEL: test_v4f64_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltpd %ymm0, %ymm1, %ymm0 -; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vorpd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vorpd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovq %xmm0, %rax +; AVX512-NEXT: vmovmskpd %ymm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbq %rax, %rax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = fcmp ogt <4 x double> %a0, %a1 @@ -103,12 +101,9 @@ define i64 @test_v4f64_legal_sext(<4 x double> %a0, <4 x double> %a1) { ; AVX512-NEXT: vcmpltpd %ymm0, %ymm1, %k1 ; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: cltq +; AVX512-NEXT: vmovmskps %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbq %rax, %rax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = fcmp ogt <4 x double> %a0, %a1 @@ -142,11 +137,9 @@ define i32 @test_v4f32_sext(<4 x float> %a0, <4 x float> %a1) { ; AVX512-LABEL: test_v4f32_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltps %xmm0, %xmm1, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vorps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vorps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovmskps %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: retq %c = fcmp ogt <4 x float> %a0, %a1 %s = sext <4 x i1> %c to <4 x i32> @@ -181,13 +174,9 @@ define i32 @test_v8f32_sext(<8 x float> %a0, <8 x float> %a1) { ; AVX512-LABEL: test_v8f32_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltps %ymm0, %ymm1, %ymm0 -; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vorps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vorps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vorps %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovmskps %ymm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = fcmp ogt <8 x float> %a0, %a1 @@ -228,14 +217,9 @@ define i32 @test_v8f32_legal_sext(<8 x float> %a0, <8 x float> %a1) { ; AVX512: # %bb.0: ; AVX512-NEXT: vcmpltps %ymm0, %ymm1, %k0 ; AVX512-NEXT: vpmovm2w %k0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: cwtl +; AVX512-NEXT: vpmovmskb %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = fcmp ogt <8 x float> %a0, %a1 @@ -271,9 +255,9 @@ define i64 @test_v2i64_sext(<2 x i64> %a0, <2 x i64> %a1) { ; AVX512-LABEL: test_v2i64_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovq %xmm0, %rax +; AVX512-NEXT: vmovmskpd %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbq %rax, %rax ; AVX512-NEXT: retq %c = icmp sgt <2 x i64> %a0, %a1 %s = sext <2 x i1> %c to <2 x i64> @@ -319,11 +303,9 @@ define i64 @test_v4i64_sext(<4 x i64> %a0, <4 x i64> %a1) { ; AVX512-LABEL: test_v4i64_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovq %xmm0, %rax +; AVX512-NEXT: vmovmskpd %ymm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbq %rax, %rax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <4 x i64> %a0, %a1 @@ -376,12 +358,9 @@ define i64 @test_v4i64_legal_sext(<4 x i64> %a0, <4 x i64> %a1) { ; AVX512-NEXT: vpcmpgtq %ymm1, %ymm0, %k1 ; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: cltq +; AVX512-NEXT: vmovmskps %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbq %rax, %rax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <4 x i64> %a0, %a1 @@ -415,11 +394,9 @@ define i32 @test_v4i32_sext(<4 x i32> %a0, <4 x i32> %a1) { ; AVX512-LABEL: test_v4i32_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtd %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovmskps %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: retq %c = icmp sgt <4 x i32> %a0, %a1 %s = sext <4 x i1> %c to <4 x i32> @@ -467,13 +444,9 @@ define i32 @test_v8i32_sext(<8 x i32> %a0, <8 x i32> %a1) { ; AVX512-LABEL: test_v8i32_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vmovmskps %ymm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <8 x i32> %a0, %a1 @@ -527,14 +500,9 @@ define i32 @test_v8i32_legal_sext(<8 x i32> %a0, <8 x i32> %a1) { ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtd %ymm1, %ymm0, %k0 ; AVX512-NEXT: vpmovm2w %k0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax -; AVX512-NEXT: cwtl +; AVX512-NEXT: vpmovmskb %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq %c = icmp sgt <8 x i32> %a0, %a1 @@ -572,13 +540,9 @@ define i16 @test_v8i16_sext(<8 x i16> %a0, <8 x i16> %a1) { ; AVX512-LABEL: test_v8i16_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vpmovmskb %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: # kill: def $ax killed $ax killed $eax ; AVX512-NEXT: retq %c = icmp sgt <8 x i16> %a0, %a1 @@ -632,15 +596,9 @@ define i16 @test_v16i16_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX512-LABEL: test_v16i16_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtw %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vmovd %xmm0, %eax +; AVX512-NEXT: vpmovmskb %ymm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: # kill: def $ax killed $ax killed $eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq @@ -700,16 +658,9 @@ define i16 @test_v16i16_legal_sext(<16 x i16> %a0, <16 x i16> %a1) { ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtw %ymm1, %ymm0, %k0 ; AVX512-NEXT: vpmovm2b %k0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpextrb $0, %xmm0, %eax -; AVX512-NEXT: movsbl %al, %eax +; AVX512-NEXT: vpmovmskb %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: # kill: def $ax killed $ax killed $eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq @@ -750,15 +701,9 @@ define i8 @test_v16i8_sext(<16 x i8> %a0, <16 x i8> %a1) { ; AVX512-LABEL: test_v16i8_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtb %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpextrb $0, %xmm0, %eax +; AVX512-NEXT: vpmovmskb %xmm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: # kill: def $al killed $al killed $eax ; AVX512-NEXT: retq %c = icmp sgt <16 x i8> %a0, %a1 @@ -814,17 +759,9 @@ define i8 @test_v32i8_sext(<32 x i8> %a0, <32 x i8> %a1) { ; AVX512-LABEL: test_v32i8_sext: ; AVX512: # %bb.0: ; AVX512-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm0 -; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrld $16, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpsrlw $8, %xmm0, %xmm1 -; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX512-NEXT: vpextrb $0, %xmm0, %eax +; AVX512-NEXT: vpmovmskb %ymm0, %eax +; AVX512-NEXT: negl %eax +; AVX512-NEXT: sbbl %eax, %eax ; AVX512-NEXT: # kill: def $al killed $al killed $eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq -- GitLab From ac66c61bf9463bf419102ad8b6565dcbc495b0ab Mon Sep 17 00:00:00 2001 From: Justin Lebar Date: Tue, 11 Feb 2020 10:34:01 -0800 Subject: [PATCH 080/142] Use C++14-style return type deduction in clang. Summary: Simplifies the C++11-style "-> decltype(...)" return-type deduction. Note that you have to be careful about whether the function return type is `auto` or `decltype(auto)`. The difference is that bare `auto` strips const and reference, just like lambda return type deduction. In some cases that's what we want (or more likely, we know that the return type is a value type), but whenever we're wrapping a templated function which might return a reference, we need to be sure that the return type is decltype(auto). No functional change. Reviewers: bkramer, MaskRay, martong, shafik Subscribers: martong, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D74423 --- clang/lib/AST/ASTImporter.cpp | 4 +--- .../lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp | 8 +++----- clang/lib/StaticAnalyzer/Checkers/OSObjectCStyleCast.cpp | 3 +-- .../Checkers/ObjCAutoreleaseWriteChecker.cpp | 3 +-- .../lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp | 2 +- 5 files changed, 7 insertions(+), 13 deletions(-) diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 3361c7886c2d..49058ceaab25 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -204,9 +204,7 @@ namespace clang { // Wrapper for an overload set. template struct CallOverloadedCreateFun { - template - auto operator()(Args &&... args) - -> decltype(ToDeclT::Create(std::forward(args)...)) { + template decltype(auto) operator()(Args &&... args) { return ToDeclT::Create(std::forward(args)...); } }; diff --git a/clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp index d471c23b83bf..76fa56406443 100644 --- a/clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/GCDAntipatternChecker.cpp @@ -52,18 +52,16 @@ public: BugReporter &BR) const; }; -auto callsName(const char *FunctionName) - -> decltype(callee(functionDecl())) { +decltype(auto) callsName(const char *FunctionName) { return callee(functionDecl(hasName(FunctionName))); } -auto equalsBoundArgDecl(int ArgIdx, const char *DeclName) - -> decltype(hasArgument(0, expr())) { +decltype(auto) equalsBoundArgDecl(int ArgIdx, const char *DeclName) { return hasArgument(ArgIdx, ignoringParenCasts(declRefExpr( to(varDecl(equalsBoundNode(DeclName)))))); } -auto bindAssignmentToDecl(const char *DeclName) -> decltype(hasLHS(expr())) { +decltype(auto) bindAssignmentToDecl(const char *DeclName) { return hasLHS(ignoringParenImpCasts( declRefExpr(to(varDecl().bind(DeclName))))); } diff --git a/clang/lib/StaticAnalyzer/Checkers/OSObjectCStyleCast.cpp b/clang/lib/StaticAnalyzer/Checkers/OSObjectCStyleCast.cpp index 5b9895c338d8..90d69b81305c 100644 --- a/clang/lib/StaticAnalyzer/Checkers/OSObjectCStyleCast.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/OSObjectCStyleCast.cpp @@ -55,8 +55,7 @@ static void emitDiagnostics(const BoundNodes &Nodes, CE->getSourceRange()); } -static auto hasTypePointingTo(DeclarationMatcher DeclM) - -> decltype(hasType(pointerType())) { +static decltype(auto) hasTypePointingTo(DeclarationMatcher DeclM) { return hasType(pointerType(pointee(hasDeclaration(DeclM)))); } diff --git a/clang/lib/StaticAnalyzer/Checkers/ObjCAutoreleaseWriteChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/ObjCAutoreleaseWriteChecker.cpp index d2371fe60d21..9d587c585650 100644 --- a/clang/lib/StaticAnalyzer/Checkers/ObjCAutoreleaseWriteChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/ObjCAutoreleaseWriteChecker.cpp @@ -100,8 +100,7 @@ static inline std::vector toRefs(std::vector V) { return std::vector(V.begin(), V.end()); } -static auto callsNames(std::vector FunctionNames) - -> decltype(callee(functionDecl())) { +static decltype(auto) callsNames(std::vector FunctionNames) { return callee(functionDecl(hasAnyName(toRefs(FunctionNames)))); } diff --git a/clang/lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp index 586d9d3af2a6..a3bfac97e40a 100644 --- a/clang/lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/PointerSortingChecker.cpp @@ -54,7 +54,7 @@ static void emitDiagnostics(const BoundNodes &Match, const Decl *D, OS.str(), Location, Range); } -auto callsName(const char *FunctionName) -> decltype(callee(functionDecl())) { +decltype(auto) callsName(const char *FunctionName) { return callee(functionDecl(hasName(FunctionName))); } -- GitLab From 7baf2a434c8675752efeb185984ca01dbc03f7a4 Mon Sep 17 00:00:00 2001 From: Jacques Pienaar Date: Tue, 11 Feb 2020 14:38:18 -0800 Subject: [PATCH 081/142] [mlir] Start Shape dialect * Add basic skeleton for Shape dialect; * Add description of types and ops to be used; Differential Revision: https://reviews.llvm.org/D73944 --- mlir/include/mlir/Dialect/CMakeLists.txt | 1 + .../include/mlir/Dialect/Shape/CMakeLists.txt | 1 + .../mlir/Dialect/Shape/IR/CMakeLists.txt | 1 + mlir/include/mlir/Dialect/Shape/IR/Shape.h | 117 ++++++++ .../include/mlir/Dialect/Shape/IR/ShapeOps.td | 284 ++++++++++++++++++ .../include/mlir/IR/DialectSymbolRegistry.def | 3 +- mlir/lib/Dialect/CMakeLists.txt | 1 + mlir/lib/Dialect/Shape/CMakeLists.txt | 9 + .../lib/Dialect/Shape/DialectRegistration.cpp | 13 + 9 files changed, 429 insertions(+), 1 deletion(-) create mode 100644 mlir/include/mlir/Dialect/Shape/CMakeLists.txt create mode 100644 mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt create mode 100644 mlir/include/mlir/Dialect/Shape/IR/Shape.h create mode 100644 mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td create mode 100644 mlir/lib/Dialect/Shape/CMakeLists.txt create mode 100644 mlir/lib/Dialect/Shape/DialectRegistration.cpp diff --git a/mlir/include/mlir/Dialect/CMakeLists.txt b/mlir/include/mlir/Dialect/CMakeLists.txt index 8b7eaeef3974..db9de7b7ea3a 100644 --- a/mlir/include/mlir/Dialect/CMakeLists.txt +++ b/mlir/include/mlir/Dialect/CMakeLists.txt @@ -6,6 +6,7 @@ add_subdirectory(LLVMIR) add_subdirectory(LoopOps) add_subdirectory(OpenMP) add_subdirectory(QuantOps) +add_subdirectory(Shape) add_subdirectory(SPIRV) add_subdirectory(StandardOps) add_subdirectory(VectorOps) diff --git a/mlir/include/mlir/Dialect/Shape/CMakeLists.txt b/mlir/include/mlir/Dialect/Shape/CMakeLists.txt new file mode 100644 index 000000000000..f33061b2d87c --- /dev/null +++ b/mlir/include/mlir/Dialect/Shape/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory(IR) diff --git a/mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt b/mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt new file mode 100644 index 000000000000..3d1adca9c2be --- /dev/null +++ b/mlir/include/mlir/Dialect/Shape/IR/CMakeLists.txt @@ -0,0 +1 @@ +add_mlir_dialect(ShapeOps ShapeOps) diff --git a/mlir/include/mlir/Dialect/Shape/IR/Shape.h b/mlir/include/mlir/Dialect/Shape/IR/Shape.h new file mode 100644 index 000000000000..f2cb12d99f90 --- /dev/null +++ b/mlir/include/mlir/Dialect/Shape/IR/Shape.h @@ -0,0 +1,117 @@ +//===- Shape.h - MLIR Shape dialect -----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the shape dialect that is used to describe and solve shape +// relations of MLIR operations using ShapedType. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_SHAPE_IR_SHAPE_H +#define MLIR_SHAPE_IR_SHAPE_H + +#include "mlir/IR/Dialect.h" +#include "mlir/IR/OpDefinition.h" + +namespace mlir { +namespace shape { + +/// This dialect contains shape inference related operations and facilities. +class ShapeDialect : public Dialect { +public: + /// Create the dialect in the given `context`. + explicit ShapeDialect(MLIRContext *context); +}; + +namespace ShapeTypes { +enum Kind { + Component = Type::FIRST_SHAPE_TYPE, + Element, + Shape, + Size, + ValueShape +}; +} // namespace ShapeTypes + +/// The component type corresponding to shape, element type and attribute. +class ComponentType : public Type::TypeBase { +public: + using Base::Base; + + static ComponentType get(MLIRContext *context) { + return Base::get(context, ShapeTypes::Kind::Component); + } + + /// Support method to enable LLVM-style type casting. + static bool kindof(unsigned kind) { + return kind == ShapeTypes::Kind::Component; + } +}; + +/// The element type of the shaped type. +class ElementType : public Type::TypeBase { +public: + using Base::Base; + + static ElementType get(MLIRContext *context) { + return Base::get(context, ShapeTypes::Kind::Element); + } + + /// Support method to enable LLVM-style type casting. + static bool kindof(unsigned kind) { + return kind == ShapeTypes::Kind::Element; + } +}; + +/// The shape descriptor type represents rank and dimension sizes. +class ShapeType : public Type::TypeBase { +public: + using Base::Base; + + static ShapeType get(MLIRContext *context) { + return Base::get(context, ShapeTypes::Kind::Shape); + } + + /// Support method to enable LLVM-style type casting. + static bool kindof(unsigned kind) { return kind == ShapeTypes::Kind::Shape; } +}; + +/// The type of a single dimension. +class SizeType : public Type::TypeBase { +public: + using Base::Base; + + static SizeType get(MLIRContext *context) { + return Base::get(context, ShapeTypes::Kind::Size); + } + + /// Support method to enable LLVM-style type casting. + static bool kindof(unsigned kind) { return kind == ShapeTypes::Kind::Size; } +}; + +/// The ValueShape represents a (potentially unknown) runtime value and shape. +class ValueShapeType : public Type::TypeBase { +public: + using Base::Base; + + static ValueShapeType get(MLIRContext *context) { + return Base::get(context, ShapeTypes::Kind::ValueShape); + } + + /// Support method to enable LLVM-style type casting. + static bool kindof(unsigned kind) { + return kind == ShapeTypes::Kind::ValueShape; + } +}; + +#define GET_OP_CLASSES +#include "mlir/Dialect/Shape/IR/ShapeOps.h.inc" + +} // namespace shape +} // namespace mlir + +#endif // MLIR_SHAPE_IR_SHAPE_H diff --git a/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td b/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td new file mode 100644 index 000000000000..105677fd08e1 --- /dev/null +++ b/mlir/include/mlir/Dialect/Shape/IR/ShapeOps.td @@ -0,0 +1,284 @@ +//===- Shape.td - Shape operations definition --------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This is the operation definition file for Shape dialect operations. +// +//===----------------------------------------------------------------------===// + +#ifndef SHAPE_OPS +#define SHAPE_OPS + +include "mlir/IR/OpBase.td" + +// TODO(jpienaar): Move to base. +def AnyShaped: ShapedContainerType<[AnyType], IsShapedTypePred, "shaped">; + +//===----------------------------------------------------------------------===// +// Shape Inference dialect definitions +//===----------------------------------------------------------------------===// + +def ShapeDialect : Dialect { + let name = "shape"; + + let summary = "Types and operations for shape dialect"; + let description = [{ + This dialect contains operations for shape inference. + + Note: Unless explicitly stated, all functions that return a shape and take + shapes as input, return the invalid shape if one of its operands is an + invalid shape. This avoids flagging multiple errors for one verification + failure. The dialect itself does not specify how errors should be combined + (there are multiple different options, from always chosing first operand, + concatting etc. on how to combine them). + }]; + + let cppNamespace = "shape"; +} + +def Shape_SizeType : DialectType()">, "dim"> { + let typeDescription = [{ + `shape.size` represents a non-negative integer with support for being + unknown and invalid. + + Operations on `shape.size` types are specialized to handle unknown/dynamic + value. So, for example, ` + x == ` for all non-error `x : + !shape.size` (e.g., an unknown value does not become known due to addition). + }]; +} + +def Shape_ShapeType : DialectType()">, "shape"> { + let typeDescription = [{ + `shape.type` represents either an unranked shape, a ranked shape with + possibly unknown dimensions or an invalid shape. The rank is of type + `shape.size` and, if rank is known, the extent is a 1D tensor of type + `shape.size`. + + Shape is printed: + * `[*]` if it is an unranked shape + * `[?, 2]` if a rank 2 tensor with one unknown dimension + * `[3, 4]` is a rank 2 static tensor + * `[]` is a scalar + * `[1]` is a rank 1 tensor with 1 element + * `[invalid]` for an invalid shape + }]; +} + +def Shape_ElementType : DialectType()">, "element type"> { + let typeDescription = [{ + `shape.element_type` represents the element type of the ShapedType. It may + be unknown, error or regular element type supported by ShapedType. + }]; +} + +def Shape_ComponentType : DialectType()">, "component type"> { + let typeDescription = [{ + `shape.element_type` represents the element type of the ShapedType. It may + be unknown, error or regular element type supported by ShapedType. + }]; +} + +def Shape_ValueShapeType : DialectType()">, "value shape"> { + let typeDescription = [{ + `shape.value_shape` represents the value produced by an operation (this + corresponds to `Value` in the compiler) and a shape. Conceptually this is a + tuple of a value (potentially unknown) and `shape.type`. The value and shape + can either or both be unknown. If both the `value` and `shape` are known, + then the shape of `value` is conformant with `shape`. + }]; +} + +def Shape_ShapeOrSizeType: AnyTypeOf<[Shape_SizeType, Shape_ShapeType], + "shape or size">; + +//===----------------------------------------------------------------------===// +// Shape op definitions +//===----------------------------------------------------------------------===// + +// Base class for the operation in this dialect +class Shape_Op traits = []> : + Op; + +def Shape_AddOp : Shape_Op<"add", [SameOperandsAndResultType]> { + let summary = "Addition of sizes"; + let description = [{ + Adds two valid sizes as follows: + * lhs + rhs = unknown if either lhs or rhs unknown; + * lhs + rhs = (int)lhs + (int)rhs if known; + }]; + + let arguments = (ins Shape_ShapeType:$lhs, Shape_ShapeType:$rhs); + let results = (outs Shape_ShapeType:$result); +} + +def Shape_BroadcastOp : Shape_Op<"broadcast", []> { + let summary = "Returns the broadcasted output shape of two inputs"; + let description = [{ + Computes the broadcasted output shape following: + 1. If any inputs are unranked, output is unranked; + 2. Else the input array with number of dimensions smaller than the max + input dimension, has 1’s prepended to its shapes and the output shape is + calculated as follows: + + output[i] = lhs[i] if lhs[i] == rhs[i] or rhs[i] is unknown/undefined + = rhs[i] if lhs[i] is unknown/undefined + = lhs[i] if rhs[i] == 1 + = rhs[i] if lhs[i] == 1 + = error if lhs[i] != rhs[i] + + Op has an optional string attribute for the error case where there is no + broadcastable output shape possible for the given inputs. + }]; + + let arguments = (ins Shape_ShapeType:$lhs, Shape_ShapeType:$rhs, + OptionalAttr:$error); + let results = (outs Shape_ShapeType:$result); +} + +def Shape_ConstantOp : Shape_Op<"constant", []> { + let summary = "Creates a shape constant"; + let description = [{ + An operation that builds a size or shape from integer or array attribute. + It allows for creating dynamically valued shapes by using `?` for unknown + values. A constant shape specified with `*` will return an unranked shape. + + ```mlir + %x = shape.constant 10 : !shape.size + ``` + }]; + + // TODO(jpienaar): Change to a more specialized attribute that would + // encapsulate the unknown parsing while using denser packing. + let arguments = (ins ArrayAttr:$value); + let results = (outs Shape_ShapeOrSizeType:$result); +} + +def Shape_CreateShapeOp : Shape_Op<"create_shape", []> { + let summary = "Creates a shape descriptor from a tensor"; + let description = [{ + Creates a shape from a 1D integral tensor. The rank equals the number of + elements in the tensor, and extent matches the values of the elements. + }]; + + let arguments = (ins I32Tensor:$input); + let results = (outs Shape_ShapeType:$result); +} + +def Shape_JoinOp : Shape_Op<"join", []> { + let summary = "Returns the least general shape.size of its operands"; + let description = [{ + An operation that computes the least general shape of input operands. This + effectively asserts that corresponding static dimensions are equal. The + behavior is to match each element of the `shape.type` and propagate the most + restrictive information, returning an invalid shape if there are + contradictory requirements. E.g., using pseudo code + + ``` + shape.join([*], [*]) -> [*] + shape.join([*], [1, ?]) -> [1, ?] + shape.join([1, 2], [1, ?]) -> [1, 2] + shape.join([*], [1, 2]) -> [1, 2] + shape.join([], []) -> [] + shape.join([], [*]) -> [] + shape.join([], [?, ?]) -> [invalid] + shape.join([1, ?], [2, ?, ?]) -> [invalid] + ``` + + `shape.join` also allows specifying an optional error string, that may be + used to return an error to the user upon mismatch of dimensions. + + ```mlir + %c = shape.join %a, %b, error="" : !shape.type + ``` + }]; + + let arguments = (ins Shape_ShapeOrSizeType:$arg0, Shape_ShapeOrSizeType:$arg1, + OptionalAttr:$error); + let results = (outs Shape_ShapeOrSizeType:$result); +} + +def Shape_MulOp : Shape_Op<"mul", [SameOperandsAndResultType]> { + let summary = "Multiplication of sizes"; + let description = [{ + Multiplies two valid sizes as follows: + - lhs * rhs = unknown if either lhs or rhs unknown; + - lhs * rhs = (int)lhs * (int)rhs if both known; + }]; + + let arguments = (ins Shape_ShapeType:$lhs, Shape_ShapeType:$rhs); + let results = (outs Shape_ShapeType:$result); +} + +def Shape_ReduceOp : Shape_Op<"reduce", []> { + let summary = "Returns an expression reduced over a shape"; + let description = [{ + An operation that takes as input a shape, number of initial values and has a + region/function that is applied repeatedly for every dimension of the shape. + + Conceptually this op performs the following reduction: + + ``` + res[] = init; + for (int i = 0, e = shape.rank(); i != e; ++i) { + res = fn(i, shape[i], res[0], ..., res[n]); + } + ``` + + Where fn is provided by the user and the result of the reduce op is the + last computed output of the reduce function. As an example, computing the + number of elements + + ```mlir + func @shape_num_elements(%shape : !shape.type) -> !shape.size { + %0 = "shape.constant_dim"() {value = 1 : i32} : () -> !shape.size + %1 = "shape.reduce"(%shape, %0) ( { + ^bb0(%index: i32, %dim: !shape.size, %lci: !shape.size): + %acc = "shape.mul"(%lci, %dim) : + (!shape.size, !shape.size) -> !shape.size + "shape.return"(%acc) : (!shape.size) -> () + }) : (!shape.type, !shape.size) -> (!shape.size) + return %1 : !shape.size + } + ``` + + If the shape is unranked, then the results of the op is also unranked. + }]; + + let arguments = (ins Shape_ShapeType:$shape, Variadic:$args); + let results = (outs Variadic:$result); + + let regions = (region SizedRegion<1>:$body); +} + +def Shape_ShapeOfOp : Shape_Op<"shape_of", []> { + let summary = "Returns shape of a value or shaped type operand"; + + let arguments = (ins AnyTypeOf<[AnyShaped, Shape_ValueShapeType]>:$arg); + let results = (outs Shape_ShapeType:$result); +} + +// TODO: Add Ops: if_static, if_ranked + +// For testing usage. +def Shape_DebugPrintOp : Shape_Op<"debug_print", []> { + let summary = "Prints the input shape or size"; + let description = [{ + Prints the input dim or shape and passes through input. + + Note: This is intended for testing and debugging only. + }]; + + let arguments = (ins Shape_ShapeOrSizeType:$input); + let results = (outs Shape_ShapeOrSizeType:$output); +} + +#endif // SHAPE_OPS diff --git a/mlir/include/mlir/IR/DialectSymbolRegistry.def b/mlir/include/mlir/IR/DialectSymbolRegistry.def index 361ff89e86bb..d082e16026b1 100644 --- a/mlir/include/mlir/IR/DialectSymbolRegistry.def +++ b/mlir/include/mlir/IR/DialectSymbolRegistry.def @@ -1,6 +1,6 @@ //===- DialectSymbolRegistry.def - MLIR Dialect Symbol Registry -*- C++ -*-===// // -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // @@ -24,6 +24,7 @@ DEFINE_SYM_KIND_RANGE(OPENMP) // OpenMP IR Dialect DEFINE_SYM_KIND_RANGE(TOY) // Toy language (tutorial) Dialect DEFINE_SYM_KIND_RANGE(SPIRV) // SPIR-V dialect DEFINE_SYM_KIND_RANGE(XLA_HLO) // XLA HLO dialect +DEFINE_SYM_KIND_RANGE(SHAPE) // Shape dialect // The following ranges are reserved for experimenting with MLIR dialects in a // private context without having to register them here. diff --git a/mlir/lib/Dialect/CMakeLists.txt b/mlir/lib/Dialect/CMakeLists.txt index 77f529633658..f1d30d86d321 100644 --- a/mlir/lib/Dialect/CMakeLists.txt +++ b/mlir/lib/Dialect/CMakeLists.txt @@ -7,6 +7,7 @@ add_subdirectory(LoopOps) add_subdirectory(OpenMP) add_subdirectory(QuantOps) add_subdirectory(SDBM) +add_subdirectory(Shape) add_subdirectory(SPIRV) add_subdirectory(StandardOps) add_subdirectory(VectorOps) diff --git a/mlir/lib/Dialect/Shape/CMakeLists.txt b/mlir/lib/Dialect/Shape/CMakeLists.txt new file mode 100644 index 000000000000..219a78b563df --- /dev/null +++ b/mlir/lib/Dialect/Shape/CMakeLists.txt @@ -0,0 +1,9 @@ +file(GLOB globbed *.c *.cpp) +add_llvm_library(MLIRShape + ${globbed} + + ADDITIONAL_HEADER_DIRS + ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/Shape + ) +add_dependencies(MLIRShape MLIRShapeOpsIncGen LLVMSupport) +target_link_libraries(MLIRShape LLVMSupport) diff --git a/mlir/lib/Dialect/Shape/DialectRegistration.cpp b/mlir/lib/Dialect/Shape/DialectRegistration.cpp new file mode 100644 index 000000000000..818ac149453c --- /dev/null +++ b/mlir/lib/Dialect/Shape/DialectRegistration.cpp @@ -0,0 +1,13 @@ +//===- DialectRegistration.cpp - Register shape dialect -------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/Shape/IR/Shape.h" +using namespace mlir; + +// Static initialization for shape dialect registration. +static DialectRegistration ShapeOps; -- GitLab From 1217ea502edb4884c2438692bfcad1dde6e14bf9 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 11 Feb 2020 16:43:52 -0600 Subject: [PATCH 082/142] [NFC] Fix spelling --- llvm/utils/update_test_checks.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/utils/update_test_checks.py b/llvm/utils/update_test_checks.py index a54cbbb40ba8..f6fee1437f5d 100755 --- a/llvm/utils/update_test_checks.py +++ b/llvm/utils/update_test_checks.py @@ -69,7 +69,7 @@ def main(): parser.add_argument('--enable', action='store_true', dest='enabled', default=True, help='Activate CHECK line generation from this point forward') parser.add_argument('--disable', action='store_false', dest='enabled', - help='Deativate CHECK line generation from this point forward') + help='Deactivate CHECK line generation from this point forward') parser.add_argument('tests', nargs='+') args = common.parse_commandline_args(parser) -- GitLab From aedda89f656b286cff44756a4dcb50117051ebe9 Mon Sep 17 00:00:00 2001 From: Huihui Zhang Date: Tue, 11 Feb 2020 14:42:41 -0800 Subject: [PATCH 083/142] [NFC] Fix warning: comparison of integers of different signs. ../polly/lib/Transform/ScheduleOptimizer.cpp:812:54: warning: comparison of integers of different signs: 'isl_size' (aka 'int') and 'const unsigned int' [-Wsign-compare] isl_schedule_node_band_n_member(Node.get()) > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ --- polly/lib/Transform/ScheduleOptimizer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/polly/lib/Transform/ScheduleOptimizer.cpp b/polly/lib/Transform/ScheduleOptimizer.cpp index c54bc08445b7..d9dffb8f1f11 100644 --- a/polly/lib/Transform/ScheduleOptimizer.cpp +++ b/polly/lib/Transform/ScheduleOptimizer.cpp @@ -809,7 +809,7 @@ static isl::schedule_node permuteBandNodeDimensions(isl::schedule_node Node, unsigned FirstDim, unsigned SecondDim) { assert(isl_schedule_node_get_type(Node.get()) == isl_schedule_node_band && - isl_schedule_node_band_n_member(Node.get()) > + (unsigned)isl_schedule_node_band_n_member(Node.get()) > std::max(FirstDim, SecondDim)); auto PartialSchedule = isl::manage(isl_schedule_node_band_get_partial_schedule(Node.get())); -- GitLab From bdc3c73454aa04eda74dff2e5061482e13ed4ee7 Mon Sep 17 00:00:00 2001 From: Aditya Nandakumar Date: Tue, 11 Feb 2020 14:51:49 -0800 Subject: [PATCH 084/142] [MachO] Pad section data to pointer size bytes https://reviews.llvm.org/D74273 Pad macho section data to pointer size bytes, so that relocation table and symbol table following section data will be pointer size aligned. Patch by pguo. --- llvm/lib/MC/MachObjectWriter.cpp | 4 ++-- llvm/test/MC/MachO/darwin-x86_64-diff-relocs.s | 4 ++-- llvm/test/MC/MachO/variable-exprs.s | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/lib/MC/MachObjectWriter.cpp b/llvm/lib/MC/MachObjectWriter.cpp index 9f6af981aca1..65a282002ccf 100644 --- a/llvm/lib/MC/MachObjectWriter.cpp +++ b/llvm/lib/MC/MachObjectWriter.cpp @@ -831,11 +831,11 @@ uint64_t MachObjectWriter::writeObject(MCAssembler &Asm, SectionDataFileSize = std::max(SectionDataFileSize, Address + FileSize); } - // The section data is padded to 4 bytes. + // The section data is padded to pointer size bytes. // // FIXME: Is this machine dependent? unsigned SectionDataPadding = - offsetToAlignment(SectionDataFileSize, Align(4)); + offsetToAlignment(SectionDataFileSize, is64Bit() ? Align(8) : Align(4)); SectionDataFileSize += SectionDataPadding; // Write the prolog, starting with the header and load command... diff --git a/llvm/test/MC/MachO/darwin-x86_64-diff-relocs.s b/llvm/test/MC/MachO/darwin-x86_64-diff-relocs.s index 3a25999c2b8c..c5e022671dce 100644 --- a/llvm/test/MC/MachO/darwin-x86_64-diff-relocs.s +++ b/llvm/test/MC/MachO/darwin-x86_64-diff-relocs.s @@ -147,7 +147,7 @@ L3: // CHECK: Size: 0x5E // CHECK: Offset: 384 // CHECK: Alignment: 0 -// CHECK: RelocationOffset: 0x26C +// CHECK: RelocationOffset: 0x270 // CHECK: RelocationCount: 12 // CHECK: Type: Regular (0x0) // CHECK: Attributes [ (0x800004) @@ -174,7 +174,7 @@ L3: // CHECK: Size: 0x8E // CHECK: Offset: 478 // CHECK: Alignment: 0 -// CHECK: RelocationOffset: 0x2CC +// CHECK: RelocationOffset: 0x2D0 // CHECK: RelocationCount: 16 // CHECK: Type: Regular (0x0) // CHECK: Attributes [ (0x4) diff --git a/llvm/test/MC/MachO/variable-exprs.s b/llvm/test/MC/MachO/variable-exprs.s index c2eb05dceaee..b4b57811529d 100644 --- a/llvm/test/MC/MachO/variable-exprs.s +++ b/llvm/test/MC/MachO/variable-exprs.s @@ -298,7 +298,7 @@ Lt0_x = Lt0_a - Lt0_b // CHECK-X86_64: Size: 0x38 // CHECK-X86_64: Offset: 385 // CHECK-X86_64: Alignment: 0 -// CHECK-X86_64: RelocationOffset: 0x1BC +// CHECK-X86_64: RelocationOffset: 0x1C0 // CHECK-X86_64: RelocationCount: 9 // CHECK-X86_64: Type: Regular (0x0) // CHECK-X86_64: Attributes [ (0x0) -- GitLab From b87e3e2d0db8b0eb7a8f26525dad74cc7014b85f Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Feb 2020 10:16:16 -0500 Subject: [PATCH 085/142] AMDGPU: Don't create potentially dead rcp declarations This will introduce unused declarations if this doesn't reach any of the paths that will really use it. --- llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index e3cc2a4abdee..e6499afcd7a3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -620,10 +620,12 @@ static Value *optimizeWithRcp(Value *Num, Value *Den, bool AllowInaccurateRcp, return nullptr; Type *Ty = Den->getType(); - Function *Decl = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, Ty); if (const ConstantFP *CLHS = dyn_cast(Num)) { if (AllowInaccurateRcp || RcpIsAccurate) { if (CLHS->isExactlyValue(1.0)) { + Function *Decl = Intrinsic::getDeclaration( + Mod, Intrinsic::amdgcn_rcp, Ty); + // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to // the CI documentation has a worst case error of 1 ulp. // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to @@ -636,10 +638,13 @@ static Value *optimizeWithRcp(Value *Num, Value *Den, bool AllowInaccurateRcp, // 1.0 / x -> rcp(x) return Builder.CreateCall(Decl, { Den }); - } + } // Same as for 1.0, but expand the sign out of the constant. - if (CLHS->isExactlyValue(-1.0)) { + if (CLHS->isExactlyValue(-1.0)) { + Function *Decl = Intrinsic::getDeclaration( + Mod, Intrinsic::amdgcn_rcp, Ty); + // -1.0 / x -> rcp (fneg x) Value *FNeg = Builder.CreateFNeg(Den); return Builder.CreateCall(Decl, { FNeg }); @@ -648,6 +653,9 @@ static Value *optimizeWithRcp(Value *Num, Value *Den, bool AllowInaccurateRcp, } if (AllowInaccurateRcp) { + Function *Decl = Intrinsic::getDeclaration( + Mod, Intrinsic::amdgcn_rcp, Ty); + // Turn into multiply by the reciprocal. // x / y -> x * (1.0 / y) Value *Recip = Builder.CreateCall(Decl, { Den }); -- GitLab From 92c62582fc546c56b73f78402291337a24acf54e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Feb 2020 09:58:53 -0500 Subject: [PATCH 086/142] AMDGPU: Directly use rcp intrinsic in idiv expansions Since natural fdiv lowering is now more conservative even with denormals disabled, we get a slower expansion from just a plain 1.0/fdiv. Directly emit the rcp intrinsic when using it to implement integer division to avoid a pointlessly complex sequence. --- .../Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 9 +- ...amdgpu-codegenprepare-fold-binop-select.ll | 4 +- .../AMDGPU/amdgpu-codegenprepare-idiv.ll | 144 +++++++++--------- llvm/test/CodeGen/AMDGPU/divrem24-assume.ll | 2 +- 4 files changed, 82 insertions(+), 77 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index e6499afcd7a3..225cf48d61f8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -855,7 +855,9 @@ Value* AMDGPUCodeGenPrepare::expandDivRem24(IRBuilder<> &Builder, Value *FB = IsSigned ? Builder.CreateSIToFP(IB,F32Ty) : Builder.CreateUIToFP(IB,F32Ty); - Value *RCP = Builder.CreateFDiv(ConstantFP::get(F32Ty, 1.0), FB); + Function *RcpDecl = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, + Builder.getFloatTy()); + Value *RCP = Builder.CreateCall(RcpDecl, { FB }); Value *FQM = Builder.CreateFMul(FA, RCP); // fq = trunc(fqm); @@ -965,7 +967,10 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder, // RCP = URECIP(Den) = 2^32 / Den + e // e is rounding error. Value *DEN_F32 = Builder.CreateUIToFP(Den, F32Ty); - Value *RCP_F32 = Builder.CreateFDiv(ConstantFP::get(F32Ty, 1.0), DEN_F32); + + Function *RcpDecl = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, + Builder.getFloatTy()); + Value *RCP_F32 = Builder.CreateCall(RcpDecl, { DEN_F32 }); Constant *UINT_MAX_PLUS_1 = ConstantFP::get(F32Ty, BitsToFloat(0x4f800000)); Value *RCP_SCALE = Builder.CreateFMul(RCP_F32, UINT_MAX_PLUS_1); Value *RCP = Builder.CreateFPToUI(RCP_SCALE, I32Ty); diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll index 11bb1c27b1d5..fbe9f525300e 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll @@ -92,7 +92,7 @@ define i32 @select_sdiv_lhs_opaque_const0_i32(i1 %cond) { ; IR-NEXT: [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]] ; IR-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]] ; IR-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float -; IR-NEXT: [[TMP6:%.*]] = fdiv fast float 1.000000e+00, [[TMP5]] +; IR-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]]) ; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41F0000000000000 ; IR-NEXT: [[TMP8:%.*]] = fptoui float [[TMP7]] to i32 ; IR-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 @@ -190,7 +190,7 @@ define i32 @select_sdiv_lhs_opaque_const1_i32(i1 %cond) { ; IR-NEXT: [[TMP3:%.*]] = add i32 [[SELECT]], [[TMP1]] ; IR-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], [[TMP1]] ; IR-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP4]] to float -; IR-NEXT: [[TMP6:%.*]] = fdiv fast float 1.000000e+00, [[TMP5]] +; IR-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP5]]) ; IR-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP6]], 0x41F0000000000000 ; IR-NEXT: [[TMP8:%.*]] = fptoui float [[TMP7]] to i32 ; IR-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index 9faaa1001ab3..f1a5722467b1 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -4,7 +4,7 @@ define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-LABEL: @udiv_i32( ; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float -; CHECK-NEXT: [[TMP2:%.*]] = fdiv fast float 1.000000e+00, [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 @@ -54,7 +54,7 @@ define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { define amdgpu_kernel void @urem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-LABEL: @urem_i32( ; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[Y:%.*]] to float -; CHECK-NEXT: [[TMP2:%.*]] = fdiv fast float 1.000000e+00, [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 @@ -111,7 +111,7 @@ define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP1]] ; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]] ; CHECK-NEXT: [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float -; CHECK-NEXT: [[TMP9:%.*]] = fdiv fast float 1.000000e+00, [[TMP8]] +; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]]) ; CHECK-NEXT: [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP11:%.*]] = fptoui float [[TMP10]] to i32 ; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 @@ -169,7 +169,7 @@ define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP1]] ; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]] ; CHECK-NEXT: [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float -; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP9]] to i32 ; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 @@ -224,7 +224,7 @@ define amdgpu_kernel void @udiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32 ; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]]) ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] @@ -251,7 +251,7 @@ define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[Y:%.*]] to i32 ; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]]) ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] @@ -283,7 +283,7 @@ define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] @@ -314,7 +314,7 @@ define amdgpu_kernel void @srem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] @@ -344,7 +344,7 @@ define amdgpu_kernel void @udiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32 ; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]]) ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] @@ -371,7 +371,7 @@ define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[Y:%.*]] to i32 ; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]]) ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] @@ -403,7 +403,7 @@ define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] @@ -434,7 +434,7 @@ define amdgpu_kernel void @srem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] @@ -463,7 +463,7 @@ define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0 ; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP4:%.*]] = fdiv fast float 1.000000e+00, [[TMP3]] +; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]]) ; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32 ; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64 @@ -506,7 +506,7 @@ define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[X]], i64 1 ; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[Y]], i64 1 ; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP45]] to float -; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] +; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP47]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP49:%.*]] = fptoui float [[TMP48]] to i32 ; CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 @@ -549,7 +549,7 @@ define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[X]], i64 2 ; CHECK-NEXT: [[TMP88:%.*]] = extractelement <4 x i32> [[Y]], i64 2 ; CHECK-NEXT: [[TMP89:%.*]] = uitofp i32 [[TMP88]] to float -; CHECK-NEXT: [[TMP90:%.*]] = fdiv fast float 1.000000e+00, [[TMP89]] +; CHECK-NEXT: [[TMP90:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP89]]) ; CHECK-NEXT: [[TMP91:%.*]] = fmul fast float [[TMP90]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP92:%.*]] = fptoui float [[TMP91]] to i32 ; CHECK-NEXT: [[TMP93:%.*]] = zext i32 [[TMP92]] to i64 @@ -592,7 +592,7 @@ define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP130:%.*]] = extractelement <4 x i32> [[X]], i64 3 ; CHECK-NEXT: [[TMP131:%.*]] = extractelement <4 x i32> [[Y]], i64 3 ; CHECK-NEXT: [[TMP132:%.*]] = uitofp i32 [[TMP131]] to float -; CHECK-NEXT: [[TMP133:%.*]] = fdiv fast float 1.000000e+00, [[TMP132]] +; CHECK-NEXT: [[TMP133:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP132]]) ; CHECK-NEXT: [[TMP134:%.*]] = fmul fast float [[TMP133]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP135:%.*]] = fptoui float [[TMP134]] to i32 ; CHECK-NEXT: [[TMP136:%.*]] = zext i32 [[TMP135]] to i64 @@ -645,7 +645,7 @@ define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 0 ; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP4:%.*]] = fdiv fast float 1.000000e+00, [[TMP3]] +; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]]) ; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32 ; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64 @@ -688,7 +688,7 @@ define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[X]], i64 1 ; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[Y]], i64 1 ; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP45]] to float -; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] +; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP47]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP49:%.*]] = fptoui float [[TMP48]] to i32 ; CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 @@ -731,7 +731,7 @@ define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[X]], i64 2 ; CHECK-NEXT: [[TMP88:%.*]] = extractelement <4 x i32> [[Y]], i64 2 ; CHECK-NEXT: [[TMP89:%.*]] = uitofp i32 [[TMP88]] to float -; CHECK-NEXT: [[TMP90:%.*]] = fdiv fast float 1.000000e+00, [[TMP89]] +; CHECK-NEXT: [[TMP90:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP89]]) ; CHECK-NEXT: [[TMP91:%.*]] = fmul fast float [[TMP90]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP92:%.*]] = fptoui float [[TMP91]] to i32 ; CHECK-NEXT: [[TMP93:%.*]] = zext i32 [[TMP92]] to i64 @@ -774,7 +774,7 @@ define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP130:%.*]] = extractelement <4 x i32> [[X]], i64 3 ; CHECK-NEXT: [[TMP131:%.*]] = extractelement <4 x i32> [[Y]], i64 3 ; CHECK-NEXT: [[TMP132:%.*]] = uitofp i32 [[TMP131]] to float -; CHECK-NEXT: [[TMP133:%.*]] = fdiv fast float 1.000000e+00, [[TMP132]] +; CHECK-NEXT: [[TMP133:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP132]]) ; CHECK-NEXT: [[TMP134:%.*]] = fmul fast float [[TMP133]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP135:%.*]] = fptoui float [[TMP134]] to i32 ; CHECK-NEXT: [[TMP136:%.*]] = zext i32 [[TMP135]] to i64 @@ -834,7 +834,7 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]] ; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]] ; CHECK-NEXT: [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float -; CHECK-NEXT: [[TMP11:%.*]] = fdiv fast float 1.000000e+00, [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]]) ; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP13:%.*]] = fptoui float [[TMP12]] to i32 ; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 @@ -886,7 +886,7 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP60:%.*]] = xor i32 [[TMP58]], [[TMP55]] ; CHECK-NEXT: [[TMP61:%.*]] = xor i32 [[TMP59]], [[TMP56]] ; CHECK-NEXT: [[TMP62:%.*]] = uitofp i32 [[TMP61]] to float -; CHECK-NEXT: [[TMP63:%.*]] = fdiv fast float 1.000000e+00, [[TMP62]] +; CHECK-NEXT: [[TMP63:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP62]]) ; CHECK-NEXT: [[TMP64:%.*]] = fmul fast float [[TMP63]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP65:%.*]] = fptoui float [[TMP64]] to i32 ; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP65]] to i64 @@ -938,7 +938,7 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP112:%.*]] = xor i32 [[TMP110]], [[TMP107]] ; CHECK-NEXT: [[TMP113:%.*]] = xor i32 [[TMP111]], [[TMP108]] ; CHECK-NEXT: [[TMP114:%.*]] = uitofp i32 [[TMP113]] to float -; CHECK-NEXT: [[TMP115:%.*]] = fdiv fast float 1.000000e+00, [[TMP114]] +; CHECK-NEXT: [[TMP115:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP114]]) ; CHECK-NEXT: [[TMP116:%.*]] = fmul fast float [[TMP115]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP117:%.*]] = fptoui float [[TMP116]] to i32 ; CHECK-NEXT: [[TMP118:%.*]] = zext i32 [[TMP117]] to i64 @@ -990,7 +990,7 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP164:%.*]] = xor i32 [[TMP162]], [[TMP159]] ; CHECK-NEXT: [[TMP165:%.*]] = xor i32 [[TMP163]], [[TMP160]] ; CHECK-NEXT: [[TMP166:%.*]] = uitofp i32 [[TMP165]] to float -; CHECK-NEXT: [[TMP167:%.*]] = fdiv fast float 1.000000e+00, [[TMP166]] +; CHECK-NEXT: [[TMP167:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP166]]) ; CHECK-NEXT: [[TMP168:%.*]] = fmul fast float [[TMP167]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP169:%.*]] = fptoui float [[TMP168]] to i32 ; CHECK-NEXT: [[TMP170:%.*]] = zext i32 [[TMP169]] to i64 @@ -1051,7 +1051,7 @@ define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]] ; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]] ; CHECK-NEXT: [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float -; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP11]] to i32 ; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 @@ -1102,7 +1102,7 @@ define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP58:%.*]] = xor i32 [[TMP56]], [[TMP54]] ; CHECK-NEXT: [[TMP59:%.*]] = xor i32 [[TMP57]], [[TMP55]] ; CHECK-NEXT: [[TMP60:%.*]] = uitofp i32 [[TMP59]] to float -; CHECK-NEXT: [[TMP61:%.*]] = fdiv fast float 1.000000e+00, [[TMP60]] +; CHECK-NEXT: [[TMP61:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP60]]) ; CHECK-NEXT: [[TMP62:%.*]] = fmul fast float [[TMP61]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP63:%.*]] = fptoui float [[TMP62]] to i32 ; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[TMP63]] to i64 @@ -1153,7 +1153,7 @@ define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP109:%.*]] = xor i32 [[TMP107]], [[TMP105]] ; CHECK-NEXT: [[TMP110:%.*]] = xor i32 [[TMP108]], [[TMP106]] ; CHECK-NEXT: [[TMP111:%.*]] = uitofp i32 [[TMP110]] to float -; CHECK-NEXT: [[TMP112:%.*]] = fdiv fast float 1.000000e+00, [[TMP111]] +; CHECK-NEXT: [[TMP112:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP111]]) ; CHECK-NEXT: [[TMP113:%.*]] = fmul fast float [[TMP112]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP114:%.*]] = fptoui float [[TMP113]] to i32 ; CHECK-NEXT: [[TMP115:%.*]] = zext i32 [[TMP114]] to i64 @@ -1204,7 +1204,7 @@ define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP160:%.*]] = xor i32 [[TMP158]], [[TMP156]] ; CHECK-NEXT: [[TMP161:%.*]] = xor i32 [[TMP159]], [[TMP157]] ; CHECK-NEXT: [[TMP162:%.*]] = uitofp i32 [[TMP161]] to float -; CHECK-NEXT: [[TMP163:%.*]] = fdiv fast float 1.000000e+00, [[TMP162]] +; CHECK-NEXT: [[TMP163:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP162]]) ; CHECK-NEXT: [[TMP164:%.*]] = fmul fast float [[TMP163]], 0x41F0000000000000 ; CHECK-NEXT: [[TMP165:%.*]] = fptoui float [[TMP164]] to i32 ; CHECK-NEXT: [[TMP166:%.*]] = zext i32 [[TMP165]] to i64 @@ -1262,7 +1262,7 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP2]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) ; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] @@ -1282,7 +1282,7 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP24:%.*]] = zext i16 [[TMP22]] to i32 ; CHECK-NEXT: [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float ; CHECK-NEXT: [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float -; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] +; CHECK-NEXT: [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]]) ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) ; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] @@ -1302,7 +1302,7 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP44:%.*]] = zext i16 [[TMP42]] to i32 ; CHECK-NEXT: [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float ; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float -; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] +; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) ; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] @@ -1322,7 +1322,7 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP64:%.*]] = zext i16 [[TMP62]] to i32 ; CHECK-NEXT: [[TMP65:%.*]] = uitofp i32 [[TMP63]] to float ; CHECK-NEXT: [[TMP66:%.*]] = uitofp i32 [[TMP64]] to float -; CHECK-NEXT: [[TMP67:%.*]] = fdiv fast float 1.000000e+00, [[TMP66]] +; CHECK-NEXT: [[TMP67:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP66]]) ; CHECK-NEXT: [[TMP68:%.*]] = fmul fast float [[TMP65]], [[TMP67]] ; CHECK-NEXT: [[TMP69:%.*]] = call fast float @llvm.trunc.f32(float [[TMP68]]) ; CHECK-NEXT: [[TMP70:%.*]] = fneg fast float [[TMP69]] @@ -1352,7 +1352,7 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP2]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) ; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] @@ -1374,7 +1374,7 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP26:%.*]] = zext i16 [[TMP24]] to i32 ; CHECK-NEXT: [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float ; CHECK-NEXT: [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float -; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] +; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]]) ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) ; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] @@ -1396,7 +1396,7 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP48:%.*]] = zext i16 [[TMP46]] to i32 ; CHECK-NEXT: [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float ; CHECK-NEXT: [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float -; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] +; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]]) ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) ; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] @@ -1418,7 +1418,7 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP70:%.*]] = zext i16 [[TMP68]] to i32 ; CHECK-NEXT: [[TMP71:%.*]] = uitofp i32 [[TMP69]] to float ; CHECK-NEXT: [[TMP72:%.*]] = uitofp i32 [[TMP70]] to float -; CHECK-NEXT: [[TMP73:%.*]] = fdiv fast float 1.000000e+00, [[TMP72]] +; CHECK-NEXT: [[TMP73:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP72]]) ; CHECK-NEXT: [[TMP74:%.*]] = fmul fast float [[TMP71]], [[TMP73]] ; CHECK-NEXT: [[TMP75:%.*]] = call fast float @llvm.trunc.f32(float [[TMP74]]) ; CHECK-NEXT: [[TMP76:%.*]] = fneg fast float [[TMP75]] @@ -1453,7 +1453,7 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 1 ; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) ; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] @@ -1477,7 +1477,7 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP31:%.*]] = or i32 [[TMP30]], 1 ; CHECK-NEXT: [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float ; CHECK-NEXT: [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float -; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] +; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]]) ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) ; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] @@ -1501,7 +1501,7 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP55:%.*]] = or i32 [[TMP54]], 1 ; CHECK-NEXT: [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float ; CHECK-NEXT: [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float -; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] +; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]]) ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) ; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] @@ -1525,7 +1525,7 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP79:%.*]] = or i32 [[TMP78]], 1 ; CHECK-NEXT: [[TMP80:%.*]] = sitofp i32 [[TMP75]] to float ; CHECK-NEXT: [[TMP81:%.*]] = sitofp i32 [[TMP76]] to float -; CHECK-NEXT: [[TMP82:%.*]] = fdiv fast float 1.000000e+00, [[TMP81]] +; CHECK-NEXT: [[TMP82:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP81]]) ; CHECK-NEXT: [[TMP83:%.*]] = fmul fast float [[TMP80]], [[TMP82]] ; CHECK-NEXT: [[TMP84:%.*]] = call fast float @llvm.trunc.f32(float [[TMP83]]) ; CHECK-NEXT: [[TMP85:%.*]] = fneg fast float [[TMP84]] @@ -1559,7 +1559,7 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 1 ; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) ; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] @@ -1585,7 +1585,7 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP33:%.*]] = or i32 [[TMP32]], 1 ; CHECK-NEXT: [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float ; CHECK-NEXT: [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float -; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] +; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]]) ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) ; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] @@ -1611,7 +1611,7 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP59:%.*]] = or i32 [[TMP58]], 1 ; CHECK-NEXT: [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float ; CHECK-NEXT: [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float -; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] +; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]]) ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) ; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] @@ -1637,7 +1637,7 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: [[TMP85:%.*]] = or i32 [[TMP84]], 1 ; CHECK-NEXT: [[TMP86:%.*]] = sitofp i32 [[TMP81]] to float ; CHECK-NEXT: [[TMP87:%.*]] = sitofp i32 [[TMP82]] to float -; CHECK-NEXT: [[TMP88:%.*]] = fdiv fast float 1.000000e+00, [[TMP87]] +; CHECK-NEXT: [[TMP88:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP87]]) ; CHECK-NEXT: [[TMP89:%.*]] = fmul fast float [[TMP86]], [[TMP88]] ; CHECK-NEXT: [[TMP90:%.*]] = call fast float @llvm.trunc.f32(float [[TMP89]]) ; CHECK-NEXT: [[TMP91:%.*]] = fneg fast float [[TMP90]] @@ -1668,7 +1668,7 @@ define amdgpu_kernel void @udiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i32 ; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]]) ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] @@ -1695,7 +1695,7 @@ define amdgpu_kernel void @urem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: [[TMP2:%.*]] = zext i3 [[Y:%.*]] to i32 ; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP4:%.*]] = uitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP5:%.*]] = fdiv fast float 1.000000e+00, [[TMP4]] +; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP4]]) ; CHECK-NEXT: [[TMP6:%.*]] = fmul fast float [[TMP3]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.trunc.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fneg fast float [[TMP7]] @@ -1727,7 +1727,7 @@ define amdgpu_kernel void @sdiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] @@ -1758,7 +1758,7 @@ define amdgpu_kernel void @srem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = sitofp i32 [[TMP1]] to float ; CHECK-NEXT: [[TMP7:%.*]] = sitofp i32 [[TMP2]] to float -; CHECK-NEXT: [[TMP8:%.*]] = fdiv fast float 1.000000e+00, [[TMP7]] +; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) ; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.trunc.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fneg fast float [[TMP10]] @@ -1790,7 +1790,7 @@ define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP2]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) ; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] @@ -1810,7 +1810,7 @@ define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP24:%.*]] = zext i16 [[TMP22]] to i32 ; CHECK-NEXT: [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float ; CHECK-NEXT: [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float -; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] +; CHECK-NEXT: [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]]) ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) ; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] @@ -1830,7 +1830,7 @@ define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP44:%.*]] = zext i16 [[TMP42]] to i32 ; CHECK-NEXT: [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float ; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float -; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] +; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) ; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] @@ -1860,7 +1860,7 @@ define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP2]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) ; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] @@ -1882,7 +1882,7 @@ define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP26:%.*]] = zext i16 [[TMP24]] to i32 ; CHECK-NEXT: [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float ; CHECK-NEXT: [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float -; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] +; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]]) ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) ; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] @@ -1904,7 +1904,7 @@ define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP48:%.*]] = zext i16 [[TMP46]] to i32 ; CHECK-NEXT: [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float ; CHECK-NEXT: [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float -; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] +; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]]) ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) ; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] @@ -1939,7 +1939,7 @@ define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 1 ; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) ; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] @@ -1963,7 +1963,7 @@ define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP31:%.*]] = or i32 [[TMP30]], 1 ; CHECK-NEXT: [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float ; CHECK-NEXT: [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float -; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] +; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]]) ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) ; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] @@ -1987,7 +1987,7 @@ define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP55:%.*]] = or i32 [[TMP54]], 1 ; CHECK-NEXT: [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float ; CHECK-NEXT: [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float -; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] +; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]]) ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) ; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] @@ -2021,7 +2021,7 @@ define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 1 ; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) ; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] @@ -2047,7 +2047,7 @@ define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP33:%.*]] = or i32 [[TMP32]], 1 ; CHECK-NEXT: [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float ; CHECK-NEXT: [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float -; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] +; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]]) ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) ; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] @@ -2073,7 +2073,7 @@ define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: [[TMP59:%.*]] = or i32 [[TMP58]], 1 ; CHECK-NEXT: [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float ; CHECK-NEXT: [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float -; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] +; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]]) ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) ; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] @@ -2106,7 +2106,7 @@ define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP4:%.*]] = zext i15 [[TMP2]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) ; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] @@ -2126,7 +2126,7 @@ define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP24:%.*]] = zext i15 [[TMP22]] to i32 ; CHECK-NEXT: [[TMP25:%.*]] = uitofp i32 [[TMP23]] to float ; CHECK-NEXT: [[TMP26:%.*]] = uitofp i32 [[TMP24]] to float -; CHECK-NEXT: [[TMP27:%.*]] = fdiv fast float 1.000000e+00, [[TMP26]] +; CHECK-NEXT: [[TMP27:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP26]]) ; CHECK-NEXT: [[TMP28:%.*]] = fmul fast float [[TMP25]], [[TMP27]] ; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.trunc.f32(float [[TMP28]]) ; CHECK-NEXT: [[TMP30:%.*]] = fneg fast float [[TMP29]] @@ -2146,7 +2146,7 @@ define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP44:%.*]] = zext i15 [[TMP42]] to i32 ; CHECK-NEXT: [[TMP45:%.*]] = uitofp i32 [[TMP43]] to float ; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP44]] to float -; CHECK-NEXT: [[TMP47:%.*]] = fdiv fast float 1.000000e+00, [[TMP46]] +; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) ; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP45]], [[TMP47]] ; CHECK-NEXT: [[TMP49:%.*]] = call fast float @llvm.trunc.f32(float [[TMP48]]) ; CHECK-NEXT: [[TMP50:%.*]] = fneg fast float [[TMP49]] @@ -2176,7 +2176,7 @@ define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP4:%.*]] = zext i15 [[TMP2]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = uitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP6:%.*]] = uitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP7:%.*]] = fdiv fast float 1.000000e+00, [[TMP6]] +; CHECK-NEXT: [[TMP7:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP6]]) ; CHECK-NEXT: [[TMP8:%.*]] = fmul fast float [[TMP5]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP8]]) ; CHECK-NEXT: [[TMP10:%.*]] = fneg fast float [[TMP9]] @@ -2198,7 +2198,7 @@ define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP26:%.*]] = zext i15 [[TMP24]] to i32 ; CHECK-NEXT: [[TMP27:%.*]] = uitofp i32 [[TMP25]] to float ; CHECK-NEXT: [[TMP28:%.*]] = uitofp i32 [[TMP26]] to float -; CHECK-NEXT: [[TMP29:%.*]] = fdiv fast float 1.000000e+00, [[TMP28]] +; CHECK-NEXT: [[TMP29:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP28]]) ; CHECK-NEXT: [[TMP30:%.*]] = fmul fast float [[TMP27]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = call fast float @llvm.trunc.f32(float [[TMP30]]) ; CHECK-NEXT: [[TMP32:%.*]] = fneg fast float [[TMP31]] @@ -2220,7 +2220,7 @@ define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP48:%.*]] = zext i15 [[TMP46]] to i32 ; CHECK-NEXT: [[TMP49:%.*]] = uitofp i32 [[TMP47]] to float ; CHECK-NEXT: [[TMP50:%.*]] = uitofp i32 [[TMP48]] to float -; CHECK-NEXT: [[TMP51:%.*]] = fdiv fast float 1.000000e+00, [[TMP50]] +; CHECK-NEXT: [[TMP51:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP50]]) ; CHECK-NEXT: [[TMP52:%.*]] = fmul fast float [[TMP49]], [[TMP51]] ; CHECK-NEXT: [[TMP53:%.*]] = call fast float @llvm.trunc.f32(float [[TMP52]]) ; CHECK-NEXT: [[TMP54:%.*]] = fneg fast float [[TMP53]] @@ -2255,7 +2255,7 @@ define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 1 ; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) ; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] @@ -2279,7 +2279,7 @@ define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP31:%.*]] = or i32 [[TMP30]], 1 ; CHECK-NEXT: [[TMP32:%.*]] = sitofp i32 [[TMP27]] to float ; CHECK-NEXT: [[TMP33:%.*]] = sitofp i32 [[TMP28]] to float -; CHECK-NEXT: [[TMP34:%.*]] = fdiv fast float 1.000000e+00, [[TMP33]] +; CHECK-NEXT: [[TMP34:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP33]]) ; CHECK-NEXT: [[TMP35:%.*]] = fmul fast float [[TMP32]], [[TMP34]] ; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.trunc.f32(float [[TMP35]]) ; CHECK-NEXT: [[TMP37:%.*]] = fneg fast float [[TMP36]] @@ -2303,7 +2303,7 @@ define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP55:%.*]] = or i32 [[TMP54]], 1 ; CHECK-NEXT: [[TMP56:%.*]] = sitofp i32 [[TMP51]] to float ; CHECK-NEXT: [[TMP57:%.*]] = sitofp i32 [[TMP52]] to float -; CHECK-NEXT: [[TMP58:%.*]] = fdiv fast float 1.000000e+00, [[TMP57]] +; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]]) ; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP56]], [[TMP58]] ; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.trunc.f32(float [[TMP59]]) ; CHECK-NEXT: [[TMP61:%.*]] = fneg fast float [[TMP60]] @@ -2337,7 +2337,7 @@ define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], 1 ; CHECK-NEXT: [[TMP8:%.*]] = sitofp i32 [[TMP3]] to float ; CHECK-NEXT: [[TMP9:%.*]] = sitofp i32 [[TMP4]] to float -; CHECK-NEXT: [[TMP10:%.*]] = fdiv fast float 1.000000e+00, [[TMP9]] +; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]]) ; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP8]], [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]]) ; CHECK-NEXT: [[TMP13:%.*]] = fneg fast float [[TMP12]] @@ -2363,7 +2363,7 @@ define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP33:%.*]] = or i32 [[TMP32]], 1 ; CHECK-NEXT: [[TMP34:%.*]] = sitofp i32 [[TMP29]] to float ; CHECK-NEXT: [[TMP35:%.*]] = sitofp i32 [[TMP30]] to float -; CHECK-NEXT: [[TMP36:%.*]] = fdiv fast float 1.000000e+00, [[TMP35]] +; CHECK-NEXT: [[TMP36:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP35]]) ; CHECK-NEXT: [[TMP37:%.*]] = fmul fast float [[TMP34]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = call fast float @llvm.trunc.f32(float [[TMP37]]) ; CHECK-NEXT: [[TMP39:%.*]] = fneg fast float [[TMP38]] @@ -2389,7 +2389,7 @@ define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: [[TMP59:%.*]] = or i32 [[TMP58]], 1 ; CHECK-NEXT: [[TMP60:%.*]] = sitofp i32 [[TMP55]] to float ; CHECK-NEXT: [[TMP61:%.*]] = sitofp i32 [[TMP56]] to float -; CHECK-NEXT: [[TMP62:%.*]] = fdiv fast float 1.000000e+00, [[TMP61]] +; CHECK-NEXT: [[TMP62:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP61]]) ; CHECK-NEXT: [[TMP63:%.*]] = fmul fast float [[TMP60]], [[TMP62]] ; CHECK-NEXT: [[TMP64:%.*]] = call fast float @llvm.trunc.f32(float [[TMP63]]) ; CHECK-NEXT: [[TMP65:%.*]] = fneg fast float [[TMP64]] diff --git a/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll b/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll index e32c93bdf407..81bccd608c64 100644 --- a/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll +++ b/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll @@ -9,7 +9,7 @@ define amdgpu_kernel void @divrem24_assume(i32 addrspace(1)* %arg, i32 %arg1) { ; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]]) ; CHECK-NEXT: [[TMP0:%.*]] = uitofp i32 [[TMP]] to float ; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[ARG1]] to float -; CHECK-NEXT: [[TMP2:%.*]] = fdiv fast float 1.000000e+00, [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.trunc.f32(float [[TMP3]]) ; CHECK-NEXT: [[TMP5:%.*]] = fneg fast float [[TMP4]] -- GitLab From f734ce0488d45c8073892abb6805c9fd9d99fd46 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Feb 2020 14:33:50 -0500 Subject: [PATCH 087/142] AMDGPU: Fix crash on v3i15 kernel arguments This was split into 3 i15 arguments. The i15 piece needs to be rounded to a simple MVT for the memory type. --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 2 ++ .../AMDGPU/kernel-argument-dag-lowering.ll | 22 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index bf21dedef6dd..24e0b9a6d02e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -1019,6 +1019,8 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute( assert(MemVT.getVectorNumElements() == 3 || MemVT.getVectorNumElements() == 5); MemVT = MemVT.getPow2VectorType(State.getContext()); + } else if (!MemVT.isSimple() && !MemVT.isVector()) { + MemVT = MemVT.getRoundIntegerType(State.getContext()); } unsigned PartOffset = 0; diff --git a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll index 6691696924b4..8a33e92557cb 100644 --- a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll +++ b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll @@ -130,3 +130,25 @@ define amdgpu_kernel void @array_3xi16(i8 %arg0, [3 x i16] %arg1) { store volatile [3 x i16] %arg1, [3 x i16] addrspace(1)* undef ret void } + +; GCN-LABEL: {{^}}v2i15_arg: +; GCN: s_load_dword [[DWORD:s[0-9]+]] +; GCN-DAG: s_bfe_u32 [[BFE:s[0-9]+]], [[DWORD]], 0x100010{{$}} +; GCN-DAG: s_and_b32 [[AND:s[0-9]+]], [[DWORD]], 0x7fff{{$}} +define amdgpu_kernel void @v2i15_arg(<2 x i15> addrspace(1)* nocapture %out, <2 x i15> %in) { +entry: + store <2 x i15> %in, <2 x i15> addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}v3i15_arg: +; GCN: s_load_dword [[DWORD:s[0-9]+]] +; GCN: s_lshl_b64 +; GCN: s_and_b32 +; GCN: s_and_b32 +; GCN: s_or_b32 +define amdgpu_kernel void @v3i15_arg(<3 x i15> addrspace(1)* nocapture %out, <3 x i15> %in) { +entry: + store <3 x i15> %in, <3 x i15> addrspace(1)* %out, align 4 + ret void +} -- GitLab From d3a96fc082bef6a15f1ce8aed1849ff4122636dc Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Feb 2020 13:54:17 -0500 Subject: [PATCH 088/142] AMDGPU: Add baseline tests for CGP div expansion These cases are harmed by expanding division early in the IR, before DAGCombiner. --- .../AMDGPU/amdgpu-codegenprepare-idiv.ll | 5211 ++++++++++++++++- 1 file changed, 5210 insertions(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index f1a5722467b1..6ed9d23f64be 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -1,5 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -amdgpu-codegenprepare %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-LABEL: @udiv_i32( @@ -46,6 +48,38 @@ define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: store i32 [[TMP40]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: udiv_i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s8, v1 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, s8, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 +; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = udiv i32 %x, %y store i32 %r, i32 addrspace(1)* %out ret void @@ -96,6 +130,38 @@ define amdgpu_kernel void @urem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: store i32 [[TMP40]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: urem_i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s9 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v0 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s8, v0 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, s9, v1 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s9, v1 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[2:3] +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = urem i32 %x, %y store i32 %r, i32 addrspace(1)* %out ret void @@ -155,6 +221,47 @@ define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: store i32 [[TMP49]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: sdiv_i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s8, s3, 31 +; GCN-NEXT: s_add_i32 s3, s3, s8 +; GCN-NEXT: s_xor_b32 s9, s3, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_xor_b32 s3, s3, s8 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s2 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s2, v1 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, s2, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 +; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GCN-NEXT: v_xor_b32_e32 v0, s3, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = sdiv i32 %x, %y store i32 %r, i32 addrspace(1)* %out ret void @@ -213,6 +320,47 @@ define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: store i32 [[TMP48]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: srem_i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s5, 31 +; GCN-NEXT: s_add_i32 s3, s5, s2 +; GCN-NEXT: s_xor_b32 s10, s3, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10 +; GCN-NEXT: s_ashr_i32 s8, s4, 31 +; GCN-NEXT: s_add_i32 s4, s4, s8 +; GCN-NEXT: s_xor_b32 s9, s4, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s10 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s10 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s9 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s10 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s9, v0 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v0 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, s10, v1 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s10, v1 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[2:3] +; GCN-NEXT: v_xor_b32_e32 v0, s8, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = srem i32 %x, %y store i32 %r, i32 addrspace(1)* %out ret void @@ -240,6 +388,26 @@ define amdgpu_kernel void @udiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: store i16 [[TMP17]], i16 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: udiv_i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s2, s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s3, s2, 16 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s3 +; GCN-NEXT: s_and_b32 s2, s2, 0xffff +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm %r = udiv i16 %x, %y store i16 %r, i16 addrspace(1)* %out ret void @@ -269,6 +437,28 @@ define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: store i16 [[TMP19]], i16 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: urem_i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s4, s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s2, s4, 16 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_and_b32 s3, s4, 0xffff +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm %r = urem i16 %x, %y store i16 %r, i16 addrspace(1)* %out ret void @@ -300,6 +490,31 @@ define amdgpu_kernel void @sdiv_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: store i16 [[TMP21]], i16 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: sdiv_i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s1, s0, 16 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1 +; GCN-NEXT: s_sext_i32_i16 s0, s0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = sdiv i16 %x, %y store i16 %r, i16 addrspace(1)* %out ret void @@ -333,6 +548,33 @@ define amdgpu_kernel void @srem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) { ; CHECK-NEXT: store i16 [[TMP23]], i16 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: srem_i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s4, s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s4, 16 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2 +; GCN-NEXT: s_sext_i32_i16 s3, s4 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3 +; GCN-NEXT: s_xor_b32 s3, s3, s2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s3, s3, 30 +; GCN-NEXT: s_or_b32 s3, s3, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm %r = srem i16 %x, %y store i16 %r, i16 addrspace(1)* %out ret void @@ -360,6 +602,24 @@ define amdgpu_kernel void @udiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: store i8 [[TMP17]], i8 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: udiv_i8: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 +; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s0 +; GCN-NEXT: v_mul_f32_e32 v1, v2, v1 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = udiv i8 %x, %y store i8 %r, i8 addrspace(1)* %out ret void @@ -389,6 +649,27 @@ define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: store i8 [[TMP19]], i8 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: urem_i8: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s4, s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_ubyte1_e32 v0, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 +; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s4 +; GCN-NEXT: s_lshr_b32 s2, s4, 8 +; GCN-NEXT: v_mul_f32_e32 v1, v2, v1 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-NEXT: buffer_store_byte v0, off, s[0:3], 0 +; GCN-NEXT: s_endpgm %r = urem i8 %x, %y store i8 %r, i8 addrspace(1)* %out ret void @@ -420,6 +701,31 @@ define amdgpu_kernel void @sdiv_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: store i8 [[TMP21]], i8 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: sdiv_i8: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_bfe_i32 s1, s0, 0x80008 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1 +; GCN-NEXT: s_sext_i32_i8 s0, s0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = sdiv i8 %x, %y store i8 %r, i8 addrspace(1)* %out ret void @@ -453,6 +759,34 @@ define amdgpu_kernel void @srem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) { ; CHECK-NEXT: store i8 [[TMP23]], i8 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: srem_i8: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_bfe_i32 s1, s0, 0x80008 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1 +; GCN-NEXT: s_sext_i32_i8 s3, s0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3 +; GCN-NEXT: s_xor_b32 s1, s3, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s1 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: s_lshr_b32 s2, s0, 8 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = srem i8 %x, %y store i8 %r, i8 addrspace(1)* %out ret void @@ -635,6 +969,108 @@ define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: store <4 x i32> [[TMP172]], <4 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: udiv_v4i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s6, 0x4f800000 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 +; GCN-NEXT: v_cvt_f32_u32_e32 v7, s15 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v0, s6, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v1, s6, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s12 +; GCN-NEXT: v_mul_lo_u32 v3, v0, s12 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s13 +; GCN-NEXT: v_mul_lo_u32 v5, v1, s13 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v6, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v0 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v2, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v6, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v3, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v1 +; GCN-NEXT: v_mul_lo_u32 v3, v0, s12 +; GCN-NEXT: v_add_i32_e32 v4, vcc, -1, v0 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, s8, v3 +; GCN-NEXT: v_cmp_le_u32_e64 s[4:5], s12, v5 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s14 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, s9 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s8, v3 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v0 +; GCN-NEXT: s_and_b64 vcc, s[4:5], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; GCN-NEXT: v_mul_f32_e32 v2, s6, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_mul_lo_u32 v3, v1, s13 +; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v6, v2, s14 +; GCN-NEXT: v_mul_lo_u32 v5, v2, s14 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s9, v3 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v3 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v3, v3, v2 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, -1, v1 +; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v1 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v3, v2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v7 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v2, v2, s10 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_mul_f32_e32 v3, s6, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v2, s14 +; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v7, v3, s15 +; GCN-NEXT: v_mul_lo_u32 v6, v3, s15 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s10, v5 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v4 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v7 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v6 +; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v4, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v4, v4, v3 +; GCN-NEXT: v_add_i32_e32 v6, vcc, -1, v2 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v4, v3 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v3, v3, s11 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s10, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v2 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_mul_lo_u32 v5, v3, s15 +; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[2:3] +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v5 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v4 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s11, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, -1, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v3 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[2:3] +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 +; GCN-NEXT: s_endpgm %r = udiv <4 x i32> %x, %y store <4 x i32> %r, <4 x i32> addrspace(1)* %out ret void @@ -817,6 +1253,108 @@ define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: store <4 x i32> [[TMP172]], <4 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: urem_v4i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s6, 0x4f800000 +; GCN-NEXT: s_load_dwordx2 s[16:17], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s19, 0xf000 +; GCN-NEXT: s_mov_b32 s18, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 +; GCN-NEXT: v_cvt_f32_u32_e32 v7, s15 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v0, s6, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v1, s6, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_lo_u32 v2, v0, s12 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s12 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v2 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v0 +; GCN-NEXT: v_mul_lo_u32 v3, v1, s13 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v2, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0 +; GCN-NEXT: v_mul_hi_u32 v2, v1, s13 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v1 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s12 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s14 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], s8, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v1, s13 +; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v3 +; GCN-NEXT: v_mul_f32_e32 v2, s6, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_add_i32_e32 v4, vcc, s12, v3 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v3 +; GCN-NEXT: s_and_b64 vcc, s[2:3], s[4:5] +; GCN-NEXT: v_mul_lo_u32 v5, v2, s14 +; GCN-NEXT: v_mul_hi_u32 v6, v2, s14 +; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[4:5] +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s9, v1 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v1 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, 0, v5 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6 +; GCN-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v2 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, s13, v3 +; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s13, v3 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v1, v2 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v1, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v1, v1, s10 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v7 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v1, s14 +; GCN-NEXT: v_mul_f32_e32 v1, s6, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v3, s[2:3] +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v5 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v3 +; GCN-NEXT: v_mul_lo_u32 v4, v2, s15 +; GCN-NEXT: v_mul_hi_u32 v6, v2, s15 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v4 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v6 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v4, v4, v2 +; GCN-NEXT: v_add_i32_e32 v6, vcc, s14, v3 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v4, v2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v7, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v2, v2, s11 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s10, v5 +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s14, v3 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_mul_lo_u32 v5, v2, s15 +; GCN-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[2:3] +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s11, v5 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s11, v5 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, s15, v3 +; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s15, v3 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[2:3] +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 +; GCN-NEXT: s_endpgm %r = urem <4 x i32> %x, %y store <4 x i32> %r, <4 x i32> addrspace(1)* %out ret void @@ -1035,6 +1573,144 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: store <4 x i32> [[TMP208]], <4 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: sdiv_v4i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx8 s[12:19], s[0:1], 0xd +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s16, 31 +; GCN-NEXT: s_add_i32 s3, s16, s2 +; GCN-NEXT: s_xor_b32 s5, s3, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5 +; GCN-NEXT: s_mov_b32 s16, 0x4f800000 +; GCN-NEXT: s_ashr_i32 s6, s17, 31 +; GCN-NEXT: s_add_i32 s0, s17, s6 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_xor_b32 s17, s0, s6 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s17 +; GCN-NEXT: s_ashr_i32 s3, s12, 31 +; GCN-NEXT: v_mul_f32_e32 v0, s16, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: s_add_i32 s4, s12, s3 +; GCN-NEXT: s_xor_b32 s4, s4, s3 +; GCN-NEXT: s_xor_b32 s7, s3, s2 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s5 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s5 +; GCN-NEXT: s_ashr_i32 s12, s13, 31 +; GCN-NEXT: s_add_i32 s13, s13, s12 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v3 +; GCN-NEXT: s_xor_b32 s13, s13, s12 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s4 +; GCN-NEXT: v_mul_f32_e32 v1, s16, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_lo_u32 v2, v0, s5 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 +; GCN-NEXT: v_mul_hi_u32 v5, v1, s17 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v2 +; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s5, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s17 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s4, v2 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v4, v4, v1 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v4, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v4, v1 +; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: s_ashr_i32 s5, s18, 31 +; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1] +; GCN-NEXT: s_add_i32 s0, s18, s5 +; GCN-NEXT: s_xor_b32 s4, s12, s6 +; GCN-NEXT: s_xor_b32 s12, s0, s5 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, s12 +; GCN-NEXT: v_mul_hi_u32 v1, v1, s13 +; GCN-NEXT: v_xor_b32_e32 v0, s7, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v4 +; GCN-NEXT: v_mul_lo_u32 v2, v1, s17 +; GCN-NEXT: s_ashr_i32 s6, s19, 31 +; GCN-NEXT: v_mul_f32_e32 v4, s16, v4 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s13, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s17, v3 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s13, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v1 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v2, v4, s12 +; GCN-NEXT: v_mul_hi_u32 v3, v4, s12 +; GCN-NEXT: s_ashr_i32 s2, s14, 31 +; GCN-NEXT: s_add_i32 s3, s14, s2 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v2 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v4 +; GCN-NEXT: s_xor_b32 s3, s3, s2 +; GCN-NEXT: v_xor_b32_e32 v1, s4, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s4, v1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v2, v4 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: s_add_i32 s0, s19, s6 +; GCN-NEXT: s_xor_b32 s14, s0, s6 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, s14 +; GCN-NEXT: v_mul_hi_u32 v2, v2, s3 +; GCN-NEXT: s_xor_b32 s7, s2, s5 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v4 +; GCN-NEXT: v_mul_lo_u32 v3, v2, s12 +; GCN-NEXT: v_mul_f32_e32 v4, s16, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, s3, v3 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v5 +; GCN-NEXT: s_ashr_i32 s12, s15, 31 +; GCN-NEXT: v_mul_lo_u32 v6, v4, s14 +; GCN-NEXT: v_mul_hi_u32 v7, v4, s14 +; GCN-NEXT: s_add_i32 s13, s15, s12 +; GCN-NEXT: s_xor_b32 s13, s13, s12 +; GCN-NEXT: v_sub_i32_e32 v8, vcc, 0, v6 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v7 +; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v6, v6, v4 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s3, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, -1, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v2 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v6, v4 +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v4, v4, s13 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v3, v4, s14 +; GCN-NEXT: v_xor_b32_e32 v2, s7, v2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s7, v2 +; GCN-NEXT: s_xor_b32 s4, s12, s6 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, s13, v3 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v5 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s13, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, -1, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v4 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[2:3] +; GCN-NEXT: v_xor_b32_e32 v3, s4, v3 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 +; GCN-NEXT: s_endpgm %r = sdiv <4 x i32> %x, %y store <4 x i32> %r, <4 x i32> addrspace(1)* %out ret void @@ -1249,6 +1925,140 @@ define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: store <4 x i32> [[TMP204]], <4 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: srem_v4i32: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx8 s[12:19], s[0:1], 0xd +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s16, 31 +; GCN-NEXT: s_add_i32 s3, s16, s2 +; GCN-NEXT: s_xor_b32 s5, s3, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s5 +; GCN-NEXT: s_mov_b32 s16, 0x4f800000 +; GCN-NEXT: s_ashr_i32 s6, s12, 31 +; GCN-NEXT: s_ashr_i32 s2, s17, 31 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_add_i32 s0, s12, s6 +; GCN-NEXT: s_add_i32 s3, s17, s2 +; GCN-NEXT: s_xor_b32 s4, s0, s6 +; GCN-NEXT: v_mul_f32_e32 v0, s16, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: s_xor_b32 s17, s3, s2 +; GCN-NEXT: s_ashr_i32 s7, s13, 31 +; GCN-NEXT: s_add_i32 s12, s13, s7 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s5 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s5 +; GCN-NEXT: s_xor_b32 s12, s12, s7 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s17 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s4 +; GCN-NEXT: v_mul_f32_e32 v1, s16, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s5 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s17 +; GCN-NEXT: v_mul_hi_u32 v5, v1, s17 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s4, v0 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s4, v0 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s5, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, s5, v2 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s5, v2 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v4, v4, v1 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v4, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v4, v1 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: s_ashr_i32 s0, s18, 31 +; GCN-NEXT: s_add_i32 s1, s18, s0 +; GCN-NEXT: s_xor_b32 s13, s1, s0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s13 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v1, v1, s12 +; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[2:3] +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_xor_b32_e32 v0, s6, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v1, s17 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 +; GCN-NEXT: v_mul_f32_e32 v2, s16, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s12, v1 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s12, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s17, v3 +; GCN-NEXT: v_mul_lo_u32 v5, v2, s13 +; GCN-NEXT: v_mul_hi_u32 v6, v2, s13 +; GCN-NEXT: v_add_i32_e32 v4, vcc, s17, v3 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s17, v3 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v5 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v5, v5, v2 +; GCN-NEXT: s_ashr_i32 s6, s14, 31 +; GCN-NEXT: s_add_i32 s12, s14, s6 +; GCN-NEXT: s_xor_b32 s12, s12, s6 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v5, v2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: s_ashr_i32 s0, s19, 31 +; GCN-NEXT: s_add_i32 s1, s19, s0 +; GCN-NEXT: s_xor_b32 s14, s1, s0 +; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s14 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v2, v2, s12 +; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[2:3] +; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v3 +; GCN-NEXT: v_xor_b32_e32 v1, s7, v1 +; GCN-NEXT: v_mul_lo_u32 v2, v2, s13 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s7, v1 +; GCN-NEXT: v_mul_f32_e32 v3, s16, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: s_ashr_i32 s7, s15, 31 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s12, v2 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s12, v2 +; GCN-NEXT: v_mul_lo_u32 v6, v3, s14 +; GCN-NEXT: v_mul_hi_u32 v7, v3, s14 +; GCN-NEXT: s_add_i32 s12, s15, s7 +; GCN-NEXT: s_xor_b32 s12, s12, s7 +; GCN-NEXT: v_sub_i32_e32 v8, vcc, 0, v6 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v7 +; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v6, v6, v3 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, s13, v4 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s13, v4 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v6, v3 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v7, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v3, v3, s12 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v3, v3, s14 +; GCN-NEXT: v_xor_b32_e32 v2, s6, v2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s6, v2 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s12, v3 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s12, v3 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, s14, v4 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s14, v4 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[2:3] +; GCN-NEXT: v_xor_b32_e32 v3, s7, v3 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s7, v3 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 +; GCN-NEXT: s_endpgm %r = srem <4 x i32> %x, %y store <4 x i32> %r, <4 x i32> addrspace(1)* %out ret void @@ -1339,6 +2149,66 @@ define amdgpu_kernel void @udiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: store <4 x i16> [[TMP80]], <4 x i16> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: udiv_v4i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s8, 0xffff +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s9, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_lshr_b32 s9, s0, 16 +; GCN-NEXT: s_and_b32 s0, s0, s8 +; GCN-NEXT: s_lshr_b32 s2, s2, 16 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3 +; GCN-NEXT: s_and_b32 s2, s3, s8 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_mul_f32_e32 v1, v4, v5 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_mad_f32 v2, -v1, v3, v4 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, s2 +; GCN-NEXT: s_lshr_b32 s0, s1, 16 +; GCN-NEXT: s_and_b32 s1, s1, s8 +; GCN-NEXT: s_lshr_b32 s10, s3, 16 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s10 +; GCN-NEXT: v_cvt_f32_u32_e32 v5, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v1, vcc +; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_mul_f32_e32 v1, v5, v6 +; GCN-NEXT: v_cvt_f32_u32_e32 v6, s0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mad_f32 v5, -v1, v4, v5 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v4, v6, v7 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mad_f32 v4, -v4, v3, v6 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GCN-NEXT: v_and_b32_e32 v0, s8, v0 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_and_b32_e32 v1, s8, v1 +; GCN-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = udiv <4 x i16> %x, %y store <4 x i16> %r, <4 x i16> addrspace(1)* %out ret void @@ -1437,6 +2307,74 @@ define amdgpu_kernel void @urem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: store <4 x i16> [[TMP88]], <4 x i16> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: urem_v4i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s8, 0xffff +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s9, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_and_b32 s10, s0, s8 +; GCN-NEXT: s_lshr_b32 s11, s2, 16 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s10 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s11 +; GCN-NEXT: s_lshr_b32 s9, s0, 16 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, s9 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_mul_f32_e32 v1, v4, v5 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v3, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v3 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: s_and_b32 s2, s3, s8 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 +; GCN-NEXT: s_and_b32 s2, s1, s8 +; GCN-NEXT: v_mul_lo_u32 v1, v1, s11 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 +; GCN-NEXT: s_lshr_b32 s12, s3, 16 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, s9, v1 +; GCN-NEXT: s_lshr_b32 s10, s1, 16 +; GCN-NEXT: v_mul_f32_e32 v1, v3, v4 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, s12 +; GCN-NEXT: v_cvt_f32_u32_e32 v6, s10 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v4 +; GCN-NEXT: v_mad_f32 v3, -v1, v2, v3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v2, v6, v7 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mad_f32 v2, -v2, v4, v6 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v1, v1, s3 +; GCN-NEXT: v_mul_lo_u32 v2, v2, s12 +; GCN-NEXT: v_and_b32_e32 v0, s8, v0 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v1 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_and_b32_e32 v1, s8, v1 +; GCN-NEXT: v_or_b32_e32 v1, v1, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v5 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = urem <4 x i16> %x, %y store <4 x i16> %r, <4 x i16> addrspace(1)* %out ret void @@ -1543,6 +2481,86 @@ define amdgpu_kernel void @sdiv_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: store <4 x i16> [[TMP96]], <4 x i16> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: sdiv_v4i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sext_i32_i16 s8, s2 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 +; GCN-NEXT: s_sext_i32_i16 s9, s0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s9 +; GCN-NEXT: s_xor_b32 s8, s9, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s2, s2, 16 +; GCN-NEXT: s_ashr_i32 s8, s8, 30 +; GCN-NEXT: s_or_b32 s8, s8, 1 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s8 +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: s_ashr_i32 s0, s0, 16 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1 +; GCN-NEXT: s_xor_b32 s0, s0, s2 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mul_f32_e32 v3, v2, v3 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mad_f32 v2, -v3, v1, v2 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: s_sext_i32_i16 s0, s3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1| +; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; GCN-NEXT: s_sext_i32_i16 s2, s1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v1, v3 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 +; GCN-NEXT: s_xor_b32 s0, s2, s0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mul_f32_e32 v4, v1, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v1, -v4, v2, v1 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: s_ashr_i32 s0, s3, 16 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2| +; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc +; GCN-NEXT: s_ashr_i32 s1, s1, 16 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GCN-NEXT: v_cvt_f32_i32_e32 v4, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2 +; GCN-NEXT: s_xor_b32 s0, s1, s0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mul_f32_e32 v5, v4, v5 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_mad_f32 v4, -v5, v2, v4 +; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2| +; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: s_mov_b32 s0, 0xffff +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_and_b32_e32 v1, s0, v1 +; GCN-NEXT: v_or_b32_e32 v1, v1, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; GCN-NEXT: v_and_b32_e32 v0, s0, v0 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = sdiv <4 x i16> %x, %y store <4 x i16> %r, <4 x i16> addrspace(1)* %out ret void @@ -1657,6 +2675,94 @@ define amdgpu_kernel void @srem_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %x ; CHECK-NEXT: store <4 x i16> [[TMP104]], <4 x i16> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: srem_v4i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sext_i32_i16 s8, s2 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 +; GCN-NEXT: s_sext_i32_i16 s9, s0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s9 +; GCN-NEXT: s_xor_b32 s8, s9, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s8, s8, 30 +; GCN-NEXT: s_or_b32 s8, s8, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s8 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: s_ashr_i32 s2, s2, 16 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s2 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: s_ashr_i32 s0, s0, 16 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1 +; GCN-NEXT: s_xor_b32 s8, s0, s2 +; GCN-NEXT: s_ashr_i32 s8, s8, 30 +; GCN-NEXT: s_or_b32 s8, s8, 1 +; GCN-NEXT: v_mul_f32_e32 v3, v2, v3 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mad_f32 v2, -v3, v1, v2 +; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 +; GCN-NEXT: v_mov_b32_e32 v4, s8 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1| +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_mul_lo_u32 v1, v1, s2 +; GCN-NEXT: s_sext_i32_i16 s2, s3 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s0, v1 +; GCN-NEXT: s_sext_i32_i16 s0, s1 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 +; GCN-NEXT: s_xor_b32 s0, s0, s2 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mul_f32_e32 v4, v1, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v1, -v4, v2, v1 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: s_ashr_i32 s0, s3, 16 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2| +; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc +; GCN-NEXT: s_ashr_i32 s2, s1, 16 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GCN-NEXT: v_cvt_f32_i32_e32 v4, s2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2 +; GCN-NEXT: v_mul_lo_u32 v1, v1, s3 +; GCN-NEXT: s_xor_b32 s3, s2, s0 +; GCN-NEXT: s_ashr_i32 s3, s3, 30 +; GCN-NEXT: v_mul_f32_e32 v5, v4, v5 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_mad_f32 v4, -v5, v2, v4 +; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 +; GCN-NEXT: s_or_b32 s3, s3, 1 +; GCN-NEXT: v_mov_b32_e32 v6, s3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2| +; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v6, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v2, v2, s0 +; GCN-NEXT: s_mov_b32 s0, 0xffff +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v1 +; GCN-NEXT: v_and_b32_e32 v1, s0, v1 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s2, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GCN-NEXT: v_or_b32_e32 v1, v1, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; GCN-NEXT: v_and_b32_e32 v0, s0, v0 +; GCN-NEXT: v_or_b32_e32 v0, v0, v2 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = srem <4 x i16> %x, %y store <4 x i16> %r, <4 x i16> addrspace(1)* %out ret void @@ -1684,6 +2790,27 @@ define amdgpu_kernel void @udiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: store i3 [[TMP17]], i3 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: udiv_i3: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_bfe_u32 s1, s0, 0x30008 +; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 +; GCN-NEXT: s_and_b32 s0, s0, 7 +; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s0 +; GCN-NEXT: v_mul_f32_e32 v1, v2, v1 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_and_b32_e32 v0, 7, v0 +; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = udiv i3 %x, %y store i3 %r, i3 addrspace(1)* %out ret void @@ -1713,6 +2840,30 @@ define amdgpu_kernel void @urem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: store i3 [[TMP19]], i3 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: urem_i3: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_bfe_u32 s1, s0, 0x30008 +; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 +; GCN-NEXT: s_and_b32 s2, s0, 7 +; GCN-NEXT: v_cvt_f32_ubyte0_e32 v2, s2 +; GCN-NEXT: s_lshr_b32 s1, s0, 8 +; GCN-NEXT: v_mul_f32_e32 v1, v2, v1 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v0, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v0, v0, s1 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: v_and_b32_e32 v0, 7, v0 +; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = urem i3 %x, %y store i3 %r, i3 addrspace(1)* %out ret void @@ -1744,6 +2895,32 @@ define amdgpu_kernel void @sdiv_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: store i3 [[TMP21]], i3 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: sdiv_i3: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_bfe_i32 s1, s0, 0x30008 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1 +; GCN-NEXT: s_bfe_i32 s0, s0, 0x30000 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_and_b32_e32 v0, 7, v0 +; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = sdiv i3 %x, %y store i3 %r, i3 addrspace(1)* %out ret void @@ -1777,6 +2954,35 @@ define amdgpu_kernel void @srem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) { ; CHECK-NEXT: store i3 [[TMP23]], i3 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: srem_i3: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_bfe_i32 s1, s0, 0x30008 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s1 +; GCN-NEXT: s_bfe_i32 s3, s0, 0x30000 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3 +; GCN-NEXT: s_xor_b32 s1, s3, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s1 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: s_lshr_b32 s2, s0, 8 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: v_and_b32_e32 v0, 7, v0 +; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = srem i3 %x, %y store i3 %r, i3 addrspace(1)* %out ret void @@ -1847,6 +3053,54 @@ define amdgpu_kernel void @udiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: store <3 x i16> [[TMP60]], <3 x i16> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: udiv_v3i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s8, 0xffff +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s6, s0, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GCN-NEXT: s_and_b32 s6, s2, s8 +; GCN-NEXT: s_lshr_b32 s0, s0, 16 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s0 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s6 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_lshr_b32 s0, s2, 16 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_mul_f32_e32 v1, v4, v5 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: s_and_b32 s0, s1, s8 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_mad_f32 v2, -v1, v3, v4 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, s0 +; GCN-NEXT: s_and_b32 s0, s3, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v5, s0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v3 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_f32_e32 v2, v5, v6 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v2, -v2, v4, v5 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: v_and_b32_e32 v0, s8, v0 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc +; GCN-NEXT: v_or_b32_e32 v0, v0, v1 +; GCN-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = udiv <3 x i16> %x, %y store <3 x i16> %r, <3 x i16> addrspace(1)* %out ret void @@ -1923,6 +3177,64 @@ define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: store <3 x i16> [[TMP66]], <3 x i16> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: urem_v3i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s8, 0xffff +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v1, s2 +; GCN-NEXT: s_and_b32 s6, s0, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GCN-NEXT: s_and_b32 s6, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s6 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0 +; GCN-NEXT: v_alignbit_b32 v4, s1, v4, 16 +; GCN-NEXT: v_and_b32_e32 v5, s8, v4 +; GCN-NEXT: v_alignbit_b32 v1, s3, v1, 16 +; GCN-NEXT: v_mul_f32_e32 v3, v2, v3 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v6, v3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, v5 +; GCN-NEXT: v_and_b32_e32 v3, s8, v1 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: s_and_b32 s0, s1, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v3 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v6, s0 +; GCN-NEXT: s_and_b32 s0, s3, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v7, s0 +; GCN-NEXT: v_mul_f32_e32 v5, v3, v5 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v6 +; GCN-NEXT: v_mad_f32 v3, -v5, v2, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 +; GCN-NEXT: v_mul_f32_e32 v3, v7, v8 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v3 +; GCN-NEXT: v_mad_f32 v3, -v3, v6, v7 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v6 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v3, s1 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: v_and_b32_e32 v0, s8, v0 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s3, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v1 +; GCN-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = urem <3 x i16> %x, %y store <3 x i16> %r, <3 x i16> addrspace(1)* %out ret void @@ -2005,6 +3317,68 @@ define amdgpu_kernel void @sdiv_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: store <3 x i16> [[TMP72]], <3 x i16> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: sdiv_v3i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sext_i32_i16 s9, s2 +; GCN-NEXT: s_sext_i32_i16 s8, s0 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s9 +; GCN-NEXT: s_xor_b32 s8, s9, s8 +; GCN-NEXT: s_ashr_i32 s0, s0, 16 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_ashr_i32 s8, s8, 30 +; GCN-NEXT: s_or_b32 s8, s8, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s8 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s0 +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: s_ashr_i32 s2, s2, 16 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1 +; GCN-NEXT: s_xor_b32 s0, s2, s0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mul_f32_e32 v3, v2, v3 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mad_f32 v2, -v3, v1, v2 +; GCN-NEXT: v_mov_b32_e32 v4, s0 +; GCN-NEXT: s_sext_i32_i16 s0, s1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1| +; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0 +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc +; GCN-NEXT: s_sext_i32_i16 s1, s3 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 +; GCN-NEXT: s_xor_b32 s0, s1, s0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 +; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| +; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GCN-NEXT: v_or_b32_e32 v0, v0, v1 +; GCN-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = sdiv <3 x i16> %x, %y store <3 x i16> %r, <3 x i16> addrspace(1)* %out ret void @@ -2093,6 +3467,77 @@ define amdgpu_kernel void @srem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x ; CHECK-NEXT: store <3 x i16> [[TMP78]], <3 x i16> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: srem_v3i16: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sext_i32_i16 s8, s2 +; GCN-NEXT: s_sext_i32_i16 s6, s0 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s8 +; GCN-NEXT: s_xor_b32 s6, s8, s6 +; GCN-NEXT: s_ashr_i32 s6, s6, 30 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_or_b32 s6, s6, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: v_mov_b32_e32 v1, s2 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 16 +; GCN-NEXT: v_bfe_i32 v3, v2, 0, 16 +; GCN-NEXT: v_cvt_f32_i32_e32 v4, v3 +; GCN-NEXT: v_alignbit_b32 v1, s3, v1, 16 +; GCN-NEXT: v_bfe_i32 v5, v1, 0, 16 +; GCN-NEXT: v_cvt_f32_i32_e32 v6, v5 +; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v4 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: v_xor_b32_e32 v3, v5, v3 +; GCN-NEXT: s_sext_i32_i16 s0, s1 +; GCN-NEXT: v_mul_f32_e32 v5, v6, v7 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 +; GCN-NEXT: v_mad_f32 v6, -v5, v4, v6 +; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 +; GCN-NEXT: v_ashrrev_i32_e32 v3, 30, v3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v6|, |v4| +; GCN-NEXT: v_cvt_f32_i32_e32 v4, s0 +; GCN-NEXT: v_or_b32_e32 v3, 1, v3 +; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: s_sext_i32_i16 s2, s3 +; GCN-NEXT: v_mul_lo_u32 v2, v3, v2 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, s2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v4 +; GCN-NEXT: s_xor_b32 s0, s2, s0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mul_f32_e32 v5, v3, v5 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_mad_f32 v3, -v5, v4, v3 +; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4| +; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_mul_lo_u32 v3, v3, s1 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s3, v3 +; GCN-NEXT: v_or_b32_e32 v0, v0, v1 +; GCN-NEXT: buffer_store_short v2, off, s[4:7], 0 offset:4 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm %r = srem <3 x i16> %x, %y store <3 x i16> %r, <3 x i16> addrspace(1)* %out ret void @@ -2163,6 +3608,62 @@ define amdgpu_kernel void @udiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: store <3 x i15> [[TMP60]], <3 x i15> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: udiv_v3i15: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 30 +; GCN-NEXT: s_movk_i32 s3, 0x7fff +; GCN-NEXT: s_and_b32 s9, s0, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: s_and_b32 s8, s2, s3 +; GCN-NEXT: s_bfe_u32 s0, s0, 0xf000f +; GCN-NEXT: v_cvt_f32_u32_e32 v5, s0 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1 +; GCN-NEXT: s_bfe_u32 s2, s2, 0xf000f +; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 30 +; GCN-NEXT: v_cvt_f32_u32_e32 v6, s2 +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v5 +; GCN-NEXT: v_and_b32_e32 v2, s3, v2 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v3, -v4, v1, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1 +; GCN-NEXT: v_mul_f32_e32 v1, v6, v7 +; GCN-NEXT: v_and_b32_e32 v0, s3, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc +; GCN-NEXT: v_mad_f32 v4, -v1, v5, v6 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v5 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_f32_e32 v1, v0, v6 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v1 +; GCN-NEXT: v_mad_f32 v0, -v1, v2, v0 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2 +; GCN-NEXT: v_and_b32_e32 v2, s3, v3 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc +; GCN-NEXT: v_and_b32_e32 v3, s3, v4 +; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 30 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3 +; GCN-NEXT: v_or_b32_e32 v2, v2, v3 +; GCN-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-NEXT: v_and_b32_e32 v1, 0x1fff, v1 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 +; GCN-NEXT: s_endpgm %r = udiv <3 x i15> %x, %y store <3 x i15> %r, <3 x i15> addrspace(1)* %out ret void @@ -2239,6 +3740,70 @@ define amdgpu_kernel void @urem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: store <3 x i15> [[TMP66]], <3 x i15> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: urem_v3i15: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 30 +; GCN-NEXT: s_movk_i32 s3, 0x7fff +; GCN-NEXT: s_and_b32 s10, s0, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s10 +; GCN-NEXT: s_and_b32 s9, s2, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s9 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1 +; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 30 +; GCN-NEXT: s_bfe_u32 s1, s0, 0xf000f +; GCN-NEXT: v_cvt_f32_u32_e32 v5, s1 +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v3, -v4, v1, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1 +; GCN-NEXT: s_bfe_u32 s10, s2, 0xf000f +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s10 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v1, v1, s0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v5 +; GCN-NEXT: v_and_b32_e32 v2, s3, v2 +; GCN-NEXT: v_and_b32_e32 v0, s3, v0 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, s2, v1 +; GCN-NEXT: v_mul_f32_e32 v1, v3, v4 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v7, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mad_f32 v3, -v1, v5, v3 +; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v5 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_lshr_b32 s0, s0, 15 +; GCN-NEXT: v_mul_f32_e32 v3, v7, v8 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mad_f32 v3, -v3, v4, v7 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v1, v1, s0 +; GCN-NEXT: v_mul_lo_u32 v2, v3, v2 +; GCN-NEXT: s_lshr_b32 s8, s2, 15 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v1 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0 +; GCN-NEXT: v_and_b32_e32 v3, s3, v3 +; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 30 +; GCN-NEXT: v_and_b32_e32 v2, s3, v6 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3 +; GCN-NEXT: v_or_b32_e32 v2, v2, v3 +; GCN-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-NEXT: v_and_b32_e32 v1, 0x1fff, v1 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 +; GCN-NEXT: s_endpgm %r = urem <3 x i15> %x, %y store <3 x i15> %r, <3 x i15> addrspace(1)* %out ret void @@ -2321,6 +3886,76 @@ define amdgpu_kernel void @sdiv_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: store <3 x i15> [[TMP72]], <3 x i15> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: sdiv_v3i15: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 30 +; GCN-NEXT: s_bfe_i32 s3, s0, 0xf0000 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s3 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_alignbit_b32 v1, s1, v1, 30 +; GCN-NEXT: s_bfe_i32 s1, s2, 0xf0000 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 +; GCN-NEXT: s_xor_b32 s1, s1, s3 +; GCN-NEXT: s_bfe_i32 s0, s0, 0xf000f +; GCN-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| +; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, s0 +; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: v_mov_b32_e32 v5, s1 +; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc +; GCN-NEXT: s_bfe_i32 s1, s2, 0xf000f +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_cvt_f32_i32_e32 v4, s1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3 +; GCN-NEXT: s_xor_b32 s0, s1, s0 +; GCN-NEXT: v_bfe_i32 v1, v1, 0, 15 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: v_mul_f32_e32 v5, v4, v5 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_mad_f32 v4, -v5, v3, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v3| +; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 +; GCN-NEXT: v_cvt_f32_i32_e32 v4, v1 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc +; GCN-NEXT: v_bfe_i32 v0, v0, 0, 15 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_cvt_f32_i32_e32 v5, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v1 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-NEXT: v_mul_f32_e32 v1, v5, v6 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mad_f32 v5, -v1, v4, v5 +; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, |v4| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GCN-NEXT: s_movk_i32 s0, 0x7fff +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_and_b32_e32 v3, s0, v3 +; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 30 +; GCN-NEXT: v_and_b32_e32 v2, s0, v2 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3 +; GCN-NEXT: v_or_b32_e32 v2, v2, v3 +; GCN-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-NEXT: v_and_b32_e32 v1, 0x1fff, v1 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 +; GCN-NEXT: s_endpgm %r = sdiv <3 x i15> %x, %y store <3 x i15> %r, <3 x i15> addrspace(1)* %out ret void @@ -2409,7 +4044,3581 @@ define amdgpu_kernel void @srem_v3i15(<3 x i15> addrspace(1)* %out, <3 x i15> %x ; CHECK-NEXT: store <3 x i15> [[TMP78]], <3 x i15> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; +; GCN-LABEL: srem_v3i15: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 30 +; GCN-NEXT: s_movk_i32 s3, 0x7fff +; GCN-NEXT: s_and_b32 s11, s0, s3 +; GCN-NEXT: s_bfe_i32 s11, s11, 0xf0000 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s11 +; GCN-NEXT: s_and_b32 s9, s2, s3 +; GCN-NEXT: s_bfe_i32 s9, s9, 0xf0000 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 +; GCN-NEXT: s_xor_b32 s9, s9, s11 +; GCN-NEXT: s_ashr_i32 s9, s9, 30 +; GCN-NEXT: s_or_b32 s9, s9, 1 +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 +; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-NEXT: v_mov_b32_e32 v5, s9 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| +; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: s_bfe_u32 s12, s0, 0xf000f +; GCN-NEXT: v_alignbit_b32 v1, s1, v1, 30 +; GCN-NEXT: v_mul_lo_u32 v2, v2, s0 +; GCN-NEXT: s_lshr_b32 s1, s0, 15 +; GCN-NEXT: s_bfe_i32 s0, s12, 0xf0000 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, s0 +; GCN-NEXT: s_bfe_u32 s10, s2, 0xf000f +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s2, v2 +; GCN-NEXT: s_lshr_b32 s8, s2, 15 +; GCN-NEXT: s_bfe_i32 s2, s10, 0xf0000 +; GCN-NEXT: v_cvt_f32_i32_e32 v4, s2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3 +; GCN-NEXT: s_xor_b32 s0, s2, s0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mul_f32_e32 v5, v4, v5 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_mad_f32 v4, -v5, v3, v4 +; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 +; GCN-NEXT: v_and_b32_e32 v1, s3, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v3| +; GCN-NEXT: v_mov_b32_e32 v6, s0 +; GCN-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc +; GCN-NEXT: v_bfe_i32 v4, v1, 0, 15 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_cvt_f32_i32_e32 v5, v4 +; GCN-NEXT: v_and_b32_e32 v0, s3, v0 +; GCN-NEXT: v_bfe_i32 v6, v0, 0, 15 +; GCN-NEXT: v_cvt_f32_i32_e32 v7, v6 +; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v5 +; GCN-NEXT: v_xor_b32_e32 v4, v6, v4 +; GCN-NEXT: v_ashrrev_i32_e32 v4, 30, v4 +; GCN-NEXT: v_or_b32_e32 v4, 1, v4 +; GCN-NEXT: v_mul_f32_e32 v6, v7, v8 +; GCN-NEXT: v_trunc_f32_e32 v6, v6 +; GCN-NEXT: v_mad_f32 v7, -v6, v5, v7 +; GCN-NEXT: v_cvt_i32_f32_e32 v6, v6 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v7|, |v5| +; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v3, s1 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_mul_lo_u32 v1, v4, v1 +; GCN-NEXT: v_and_b32_e32 v2, s3, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v3 +; GCN-NEXT: v_and_b32_e32 v3, s3, v3 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 30 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3 +; GCN-NEXT: v_or_b32_e32 v2, v2, v3 +; GCN-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-NEXT: v_and_b32_e32 v1, 0x1fff, v1 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 +; GCN-NEXT: s_endpgm %r = srem <3 x i15> %x, %y store <3 x i15> %r, <3 x i15> addrspace(1)* %out ret void } + +define amdgpu_kernel void @udiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) { +; CHECK-LABEL: @udiv_i32_oddk_denom( +; CHECK-NEXT: [[R:%.*]] = udiv i32 [[X:%.*]], 1235195 +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_i32_oddk_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: v_mov_b32_e32 v0, 0xb2a50881 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_hi_u32 v0, s0, v0 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 20, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = udiv i32 %x, 1235195 + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) { +; CHECK-LABEL: @udiv_i32_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = udiv i32 [[X:%.*]], 4096 +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_i32_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s0, s0, 12 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = udiv i32 %x, 4096 + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) { +; CHECK-LABEL: @udiv_i32_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[SHL_Y]] to float +; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]]) +; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32 +; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[SHL_Y]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i32 +; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP7]], 32 +; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32 +; CHECK-NEXT: [[TMP11:%.*]] = sub i32 0, [[TMP8]] +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP10]], 0 +; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 [[TMP8]] +; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 +; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP4]] to i64 +; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32 +; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32 +; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32 +; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP4]], [[TMP19]] +; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[TMP4]], [[TMP19]] +; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP12]], i32 [[TMP20]], i32 [[TMP21]] +; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 +; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[X:%.*]] to i64 +; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]] +; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32 +; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 32 +; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32 +; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[SHL_Y]] +; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[X]], [[TMP29]] +; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[SHL_Y]] +; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP31]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[X]], [[TMP29]] +; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP32]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = icmp eq i32 [[TMP35]], 0 +; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP28]], 1 +; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP28]], 1 +; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP28]], i32 [[TMP37]] +; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP33]], i32 [[TMP39]], i32 [[TMP38]] +; CHECK-NEXT: store i32 [[TMP40]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_i32_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s9, 0x1000, s9 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s8, v1 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, s8, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 +; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl i32 4096, %y + %r = udiv i32 %x, %shl.y + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) { +; CHECK-LABEL: @udiv_v2i32_pow2k_denom( +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 4096 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[TMP4]], 4096 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_v2i32_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s0, s0, 12 +; GCN-NEXT: s_lshr_b32 s1, s1, 12 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = udiv <2 x i32> %x, + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) { +; CHECK-LABEL: @udiv_v2i32_mixed_pow2k_denom( +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 4096 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP5:%.*]] = udiv i32 [[TMP4]], 4095 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_v2i32_mixed_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb +; GCN-NEXT: v_mov_b32_e32 v0, 0x100101 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_hi_u32 v0, s1, v0 +; GCN-NEXT: s_lshr_b32 s0, s0, 12 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s1, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 11, v0 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = udiv <2 x i32> %x, + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) { +; CHECK-LABEL: @udiv_v2i32_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i32> , [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0 +; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float +; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32 +; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64 +; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]] +; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32 +; CHECK-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP9]], 32 +; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32 +; CHECK-NEXT: [[TMP13:%.*]] = sub i32 0, [[TMP10]] +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP12]], 0 +; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP13]], i32 [[TMP10]] +; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP6]] to i64 +; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]] +; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32 +; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32 +; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32 +; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP6]], [[TMP21]] +; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP6]], [[TMP21]] +; CHECK-NEXT: [[TMP24:%.*]] = select i1 [[TMP14]], i32 [[TMP22]], i32 [[TMP23]] +; CHECK-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 +; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[TMP27:%.*]] = mul i64 [[TMP25]], [[TMP26]] +; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32 +; CHECK-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP27]], 32 +; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i32 +; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[TMP2]] +; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP1]], [[TMP31]] +; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP2]] +; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP35:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] +; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP37:%.*]] = and i32 [[TMP34]], [[TMP36]] +; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i32 [[TMP37]], 0 +; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[TMP30]], 1 +; CHECK-NEXT: [[TMP40:%.*]] = sub i32 [[TMP30]], 1 +; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP38]], i32 [[TMP30]], i32 [[TMP39]] +; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], i32 [[TMP41]], i32 [[TMP40]] +; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x i32> undef, i32 [[TMP42]], i64 0 +; CHECK-NEXT: [[TMP44:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP45:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 +; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP45]] to float +; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) +; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP47]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP49:%.*]] = fptoui float [[TMP48]] to i32 +; CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 +; CHECK-NEXT: [[TMP51:%.*]] = zext i32 [[TMP45]] to i64 +; CHECK-NEXT: [[TMP52:%.*]] = mul i64 [[TMP50]], [[TMP51]] +; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32 +; CHECK-NEXT: [[TMP54:%.*]] = lshr i64 [[TMP52]], 32 +; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i32 +; CHECK-NEXT: [[TMP56:%.*]] = sub i32 0, [[TMP53]] +; CHECK-NEXT: [[TMP57:%.*]] = icmp eq i32 [[TMP55]], 0 +; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], i32 [[TMP56]], i32 [[TMP53]] +; CHECK-NEXT: [[TMP59:%.*]] = zext i32 [[TMP58]] to i64 +; CHECK-NEXT: [[TMP60:%.*]] = zext i32 [[TMP49]] to i64 +; CHECK-NEXT: [[TMP61:%.*]] = mul i64 [[TMP59]], [[TMP60]] +; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32 +; CHECK-NEXT: [[TMP63:%.*]] = lshr i64 [[TMP61]], 32 +; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[TMP63]] to i32 +; CHECK-NEXT: [[TMP65:%.*]] = add i32 [[TMP49]], [[TMP64]] +; CHECK-NEXT: [[TMP66:%.*]] = sub i32 [[TMP49]], [[TMP64]] +; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP57]], i32 [[TMP65]], i32 [[TMP66]] +; CHECK-NEXT: [[TMP68:%.*]] = zext i32 [[TMP67]] to i64 +; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP44]] to i64 +; CHECK-NEXT: [[TMP70:%.*]] = mul i64 [[TMP68]], [[TMP69]] +; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 +; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP70]], 32 +; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP72]] to i32 +; CHECK-NEXT: [[TMP74:%.*]] = mul i32 [[TMP73]], [[TMP45]] +; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP44]], [[TMP74]] +; CHECK-NEXT: [[TMP76:%.*]] = icmp uge i32 [[TMP75]], [[TMP45]] +; CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP78:%.*]] = icmp uge i32 [[TMP44]], [[TMP74]] +; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP78]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP80:%.*]] = and i32 [[TMP77]], [[TMP79]] +; CHECK-NEXT: [[TMP81:%.*]] = icmp eq i32 [[TMP80]], 0 +; CHECK-NEXT: [[TMP82:%.*]] = add i32 [[TMP73]], 1 +; CHECK-NEXT: [[TMP83:%.*]] = sub i32 [[TMP73]], 1 +; CHECK-NEXT: [[TMP84:%.*]] = select i1 [[TMP81]], i32 [[TMP73]], i32 [[TMP82]] +; CHECK-NEXT: [[TMP85:%.*]] = select i1 [[TMP78]], i32 [[TMP84]], i32 [[TMP83]] +; CHECK-NEXT: [[TMP86:%.*]] = insertelement <2 x i32> [[TMP43]], i32 [[TMP85]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP86]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_v2i32_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd +; GCN-NEXT: s_movk_i32 s4, 0x1000 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s2, s4, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_lshl_b32 s10, s4, s3 +; GCN-NEXT: s_mov_b32 s3, 0x4f800000 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s10 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v0, s3, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v1, s3, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_lo_u32 v2, v0, s2 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s2 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v2 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v0 +; GCN-NEXT: v_mul_lo_u32 v3, v1, s10 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v2, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0 +; GCN-NEXT: v_mul_hi_u32 v2, v1, s10 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v1 +; GCN-NEXT: v_mul_lo_u32 v5, v0, s2 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v2, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v5 +; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s2, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s10 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s8, v5 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s9, v4 +; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, -1, v1 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v1 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[2:3] +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl <2 x i32> , %y + %r = udiv <2 x i32> %x, %shl.y + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) { +; CHECK-LABEL: @urem_i32_oddk_denom( +; CHECK-NEXT: [[R:%.*]] = urem i32 [[X:%.*]], 1235195 +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_i32_oddk_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: v_mov_b32_e32 v0, 0xb2a50881 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_hi_u32 v0, s0, v0 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 1, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 20, v0 +; GCN-NEXT: v_mul_u32_u24_e32 v0, 0x12d8fb, v0 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = urem i32 %x, 1235195 + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) { +; CHECK-LABEL: @urem_i32_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = urem i32 [[X:%.*]], 4096 +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_i32_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s0, s0, 0xfff +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = urem i32 %x, 4096 + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) { +; CHECK-LABEL: @urem_i32_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[SHL_Y]] to float +; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]]) +; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32 +; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[SHL_Y]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i32 +; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP7]], 32 +; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32 +; CHECK-NEXT: [[TMP11:%.*]] = sub i32 0, [[TMP8]] +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP10]], 0 +; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 [[TMP8]] +; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 +; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP4]] to i64 +; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32 +; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32 +; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32 +; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP4]], [[TMP19]] +; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[TMP4]], [[TMP19]] +; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP12]], i32 [[TMP20]], i32 [[TMP21]] +; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 +; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[X:%.*]] to i64 +; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]] +; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32 +; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 32 +; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32 +; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[SHL_Y]] +; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[X]], [[TMP29]] +; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[SHL_Y]] +; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP31]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[X]], [[TMP29]] +; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP32]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = icmp eq i32 [[TMP35]], 0 +; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP30]], [[SHL_Y]] +; CHECK-NEXT: [[TMP38:%.*]] = add i32 [[TMP30]], [[SHL_Y]] +; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP30]], i32 [[TMP37]] +; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP33]], i32 [[TMP39]], i32 [[TMP38]] +; CHECK-NEXT: store i32 [[TMP40]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_i32_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s9, 0x1000, s9 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s9 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v0 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s8, v0 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, s9, v1 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s9, v1 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[2:3] +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl i32 4096, %y + %r = urem i32 %x, %shl.y + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) { +; CHECK-LABEL: @urem_v2i32_pow2k_denom( +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = urem i32 [[TMP1]], 4096 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP5:%.*]] = urem i32 [[TMP4]], 4096 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_v2i32_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb +; GCN-NEXT: s_movk_i32 s2, 0xfff +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s0, s0, s2 +; GCN-NEXT: s_and_b32 s1, s1, s2 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = urem <2 x i32> %x, + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) { +; CHECK-LABEL: @urem_v2i32_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i32> , [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0 +; CHECK-NEXT: [[TMP3:%.*]] = uitofp i32 [[TMP2]] to float +; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP6:%.*]] = fptoui float [[TMP5]] to i32 +; CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64 +; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[TMP7]], [[TMP8]] +; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32 +; CHECK-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP9]], 32 +; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i32 +; CHECK-NEXT: [[TMP13:%.*]] = sub i32 0, [[TMP10]] +; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP12]], 0 +; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP13]], i32 [[TMP10]] +; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64 +; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP6]] to i64 +; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], [[TMP17]] +; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32 +; CHECK-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32 +; CHECK-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32 +; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP6]], [[TMP21]] +; CHECK-NEXT: [[TMP23:%.*]] = sub i32 [[TMP6]], [[TMP21]] +; CHECK-NEXT: [[TMP24:%.*]] = select i1 [[TMP14]], i32 [[TMP22]], i32 [[TMP23]] +; CHECK-NEXT: [[TMP25:%.*]] = zext i32 [[TMP24]] to i64 +; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP1]] to i64 +; CHECK-NEXT: [[TMP27:%.*]] = mul i64 [[TMP25]], [[TMP26]] +; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32 +; CHECK-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP27]], 32 +; CHECK-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i32 +; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[TMP2]] +; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP1]], [[TMP31]] +; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP2]] +; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP35:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] +; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP37:%.*]] = and i32 [[TMP34]], [[TMP36]] +; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i32 [[TMP37]], 0 +; CHECK-NEXT: [[TMP39:%.*]] = sub i32 [[TMP32]], [[TMP2]] +; CHECK-NEXT: [[TMP40:%.*]] = add i32 [[TMP32]], [[TMP2]] +; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP38]], i32 [[TMP32]], i32 [[TMP39]] +; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], i32 [[TMP41]], i32 [[TMP40]] +; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x i32> undef, i32 [[TMP42]], i64 0 +; CHECK-NEXT: [[TMP44:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP45:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 +; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP45]] to float +; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) +; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP47]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP49:%.*]] = fptoui float [[TMP48]] to i32 +; CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 +; CHECK-NEXT: [[TMP51:%.*]] = zext i32 [[TMP45]] to i64 +; CHECK-NEXT: [[TMP52:%.*]] = mul i64 [[TMP50]], [[TMP51]] +; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32 +; CHECK-NEXT: [[TMP54:%.*]] = lshr i64 [[TMP52]], 32 +; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i32 +; CHECK-NEXT: [[TMP56:%.*]] = sub i32 0, [[TMP53]] +; CHECK-NEXT: [[TMP57:%.*]] = icmp eq i32 [[TMP55]], 0 +; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], i32 [[TMP56]], i32 [[TMP53]] +; CHECK-NEXT: [[TMP59:%.*]] = zext i32 [[TMP58]] to i64 +; CHECK-NEXT: [[TMP60:%.*]] = zext i32 [[TMP49]] to i64 +; CHECK-NEXT: [[TMP61:%.*]] = mul i64 [[TMP59]], [[TMP60]] +; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32 +; CHECK-NEXT: [[TMP63:%.*]] = lshr i64 [[TMP61]], 32 +; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[TMP63]] to i32 +; CHECK-NEXT: [[TMP65:%.*]] = add i32 [[TMP49]], [[TMP64]] +; CHECK-NEXT: [[TMP66:%.*]] = sub i32 [[TMP49]], [[TMP64]] +; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP57]], i32 [[TMP65]], i32 [[TMP66]] +; CHECK-NEXT: [[TMP68:%.*]] = zext i32 [[TMP67]] to i64 +; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP44]] to i64 +; CHECK-NEXT: [[TMP70:%.*]] = mul i64 [[TMP68]], [[TMP69]] +; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 +; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP70]], 32 +; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP72]] to i32 +; CHECK-NEXT: [[TMP74:%.*]] = mul i32 [[TMP73]], [[TMP45]] +; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP44]], [[TMP74]] +; CHECK-NEXT: [[TMP76:%.*]] = icmp uge i32 [[TMP75]], [[TMP45]] +; CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP78:%.*]] = icmp uge i32 [[TMP44]], [[TMP74]] +; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP78]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP80:%.*]] = and i32 [[TMP77]], [[TMP79]] +; CHECK-NEXT: [[TMP81:%.*]] = icmp eq i32 [[TMP80]], 0 +; CHECK-NEXT: [[TMP82:%.*]] = sub i32 [[TMP75]], [[TMP45]] +; CHECK-NEXT: [[TMP83:%.*]] = add i32 [[TMP75]], [[TMP45]] +; CHECK-NEXT: [[TMP84:%.*]] = select i1 [[TMP81]], i32 [[TMP75]], i32 [[TMP82]] +; CHECK-NEXT: [[TMP85:%.*]] = select i1 [[TMP78]], i32 [[TMP84]], i32 [[TMP83]] +; CHECK-NEXT: [[TMP86:%.*]] = insertelement <2 x i32> [[TMP43]], i32 [[TMP85]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP86]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_v2i32_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd +; GCN-NEXT: s_movk_i32 s4, 0x1000 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s10, s4, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10 +; GCN-NEXT: s_mov_b32 s2, 0x4f800000 +; GCN-NEXT: s_lshl_b32 s11, s4, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s11 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GCN-NEXT: v_mul_f32_e32 v0, s2, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v1, s2, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_lo_u32 v2, v0, s10 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s10 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v2 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v0 +; GCN-NEXT: v_mul_lo_u32 v3, v1, s11 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v2, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v2, v0 +; GCN-NEXT: v_mul_hi_u32 v2, v1, s11 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v2, v2, v1 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s10 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s8, v0 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s8, v0 +; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s10, v3 +; GCN-NEXT: v_mul_lo_u32 v1, v1, s11 +; GCN-NEXT: v_add_i32_e32 v4, vcc, s10, v3 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s10, v3 +; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s9, v1 +; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v0, s[0:1] +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, s11, v2 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s11, v2 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[2:3] +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl <2 x i32> , %y + %r = urem <2 x i32> %x, %shl.y + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) { +; CHECK-LABEL: @sdiv_i32_oddk_denom( +; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], 1235195 +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_i32_oddk_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: v_mov_b32_e32 v0, 0xd9528441 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_hi_i32 v0, s0, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 20, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = sdiv i32 %x, 1235195 + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) { +; CHECK-LABEL: @sdiv_i32_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], 4096 +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_i32_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: s_lshr_b32 s1, s1, 20 +; GCN-NEXT: s_add_i32 s0, s0, s1 +; GCN-NEXT: s_ashr_i32 s0, s0, 12 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = sdiv i32 %x, 4096 + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) { +; CHECK-LABEL: @sdiv_i32_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31 +; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[SHL_Y]], 31 +; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[X]], [[TMP1]] +; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[SHL_Y]], [[TMP2]] +; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP1]] +; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]] +; CHECK-NEXT: [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float +; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]]) +; CHECK-NEXT: [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP11:%.*]] = fptoui float [[TMP10]] to i32 +; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 +; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP7]] to i64 +; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP12]], [[TMP13]] +; CHECK-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32 +; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP14]], 32 +; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32 +; CHECK-NEXT: [[TMP18:%.*]] = sub i32 0, [[TMP15]] +; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[TMP17]], 0 +; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[TMP18]], i32 [[TMP15]] +; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 +; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP11]] to i64 +; CHECK-NEXT: [[TMP23:%.*]] = mul i64 [[TMP21]], [[TMP22]] +; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 +; CHECK-NEXT: [[TMP25:%.*]] = lshr i64 [[TMP23]], 32 +; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32 +; CHECK-NEXT: [[TMP27:%.*]] = add i32 [[TMP11]], [[TMP26]] +; CHECK-NEXT: [[TMP28:%.*]] = sub i32 [[TMP11]], [[TMP26]] +; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP19]], i32 [[TMP27]], i32 [[TMP28]] +; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64 +; CHECK-NEXT: [[TMP31:%.*]] = zext i32 [[TMP6]] to i64 +; CHECK-NEXT: [[TMP32:%.*]] = mul i64 [[TMP30]], [[TMP31]] +; CHECK-NEXT: [[TMP33:%.*]] = trunc i64 [[TMP32]] to i32 +; CHECK-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP32]], 32 +; CHECK-NEXT: [[TMP35:%.*]] = trunc i64 [[TMP34]] to i32 +; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[TMP35]], [[TMP7]] +; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP6]], [[TMP36]] +; CHECK-NEXT: [[TMP38:%.*]] = icmp uge i32 [[TMP37]], [[TMP7]] +; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP40:%.*]] = icmp uge i32 [[TMP6]], [[TMP36]] +; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP42:%.*]] = and i32 [[TMP39]], [[TMP41]] +; CHECK-NEXT: [[TMP43:%.*]] = icmp eq i32 [[TMP42]], 0 +; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP35]], 1 +; CHECK-NEXT: [[TMP45:%.*]] = sub i32 [[TMP35]], 1 +; CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP43]], i32 [[TMP35]], i32 [[TMP44]] +; CHECK-NEXT: [[TMP47:%.*]] = select i1 [[TMP40]], i32 [[TMP46]], i32 [[TMP45]] +; CHECK-NEXT: [[TMP48:%.*]] = xor i32 [[TMP47]], [[TMP3]] +; CHECK-NEXT: [[TMP49:%.*]] = sub i32 [[TMP48]], [[TMP3]] +; CHECK-NEXT: store i32 [[TMP49]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_i32_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s3, 0x1000, s3 +; GCN-NEXT: s_ashr_i32 s8, s3, 31 +; GCN-NEXT: s_add_i32 s3, s3, s8 +; GCN-NEXT: s_xor_b32 s9, s3, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_xor_b32 s3, s3, s8 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s9 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s2 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s2, v1 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, s2, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 +; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GCN-NEXT: v_xor_b32_e32 v0, s3, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl i32 4096, %y + %r = sdiv i32 %x, %shl.y + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) { +; CHECK-LABEL: @sdiv_v2i32_pow2k_denom( +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = sdiv i32 [[TMP1]], 4096 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP5:%.*]] = sdiv i32 [[TMP4]], 4096 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_v2i32_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s0, 31 +; GCN-NEXT: s_lshr_b32 s2, s2, 20 +; GCN-NEXT: s_ashr_i32 s3, s1, 31 +; GCN-NEXT: s_add_i32 s0, s0, s2 +; GCN-NEXT: s_lshr_b32 s2, s3, 20 +; GCN-NEXT: s_add_i32 s1, s1, s2 +; GCN-NEXT: s_ashr_i32 s0, s0, 12 +; GCN-NEXT: s_ashr_i32 s1, s1, 12 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = sdiv <2 x i32> %x, + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @ssdiv_v2i32_mixed_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) { +; CHECK-LABEL: @ssdiv_v2i32_mixed_pow2k_denom( +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = sdiv i32 [[TMP1]], 4096 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP5:%.*]] = sdiv i32 [[TMP4]], 4095 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: ssdiv_v2i32_mixed_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb +; GCN-NEXT: v_mov_b32_e32 v0, 0x80080081 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_hi_i32 v0, s1, v0 +; GCN-NEXT: s_ashr_i32 s2, s0, 31 +; GCN-NEXT: s_lshr_b32 s2, s2, 20 +; GCN-NEXT: s_add_i32 s0, s0, s2 +; GCN-NEXT: v_add_i32_e32 v0, vcc, s1, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 11, v0 +; GCN-NEXT: s_ashr_i32 s0, s0, 12 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v0 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = sdiv <2 x i32> %x, + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) { +; CHECK-LABEL: @sdiv_v2i32_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i32> , [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0 +; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP1]], 31 +; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP2]], 31 +; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP4]] +; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP1]], [[TMP3]] +; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP2]], [[TMP4]] +; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP3]] +; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP4]] +; CHECK-NEXT: [[TMP10:%.*]] = uitofp i32 [[TMP9]] to float +; CHECK-NEXT: [[TMP11:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP10]]) +; CHECK-NEXT: [[TMP12:%.*]] = fmul fast float [[TMP11]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP13:%.*]] = fptoui float [[TMP12]] to i32 +; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 +; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP9]] to i64 +; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]] +; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32 +; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32 +; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32 +; CHECK-NEXT: [[TMP20:%.*]] = sub i32 0, [[TMP17]] +; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[TMP19]], 0 +; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP21]], i32 [[TMP20]], i32 [[TMP17]] +; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 +; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[TMP13]] to i64 +; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]] +; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32 +; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 32 +; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32 +; CHECK-NEXT: [[TMP29:%.*]] = add i32 [[TMP13]], [[TMP28]] +; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[TMP13]], [[TMP28]] +; CHECK-NEXT: [[TMP31:%.*]] = select i1 [[TMP21]], i32 [[TMP29]], i32 [[TMP30]] +; CHECK-NEXT: [[TMP32:%.*]] = zext i32 [[TMP31]] to i64 +; CHECK-NEXT: [[TMP33:%.*]] = zext i32 [[TMP8]] to i64 +; CHECK-NEXT: [[TMP34:%.*]] = mul i64 [[TMP32]], [[TMP33]] +; CHECK-NEXT: [[TMP35:%.*]] = trunc i64 [[TMP34]] to i32 +; CHECK-NEXT: [[TMP36:%.*]] = lshr i64 [[TMP34]], 32 +; CHECK-NEXT: [[TMP37:%.*]] = trunc i64 [[TMP36]] to i32 +; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP9]] +; CHECK-NEXT: [[TMP39:%.*]] = sub i32 [[TMP8]], [[TMP38]] +; CHECK-NEXT: [[TMP40:%.*]] = icmp uge i32 [[TMP39]], [[TMP9]] +; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP42:%.*]] = icmp uge i32 [[TMP8]], [[TMP38]] +; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP44:%.*]] = and i32 [[TMP41]], [[TMP43]] +; CHECK-NEXT: [[TMP45:%.*]] = icmp eq i32 [[TMP44]], 0 +; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP37]], 1 +; CHECK-NEXT: [[TMP47:%.*]] = sub i32 [[TMP37]], 1 +; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP45]], i32 [[TMP37]], i32 [[TMP46]] +; CHECK-NEXT: [[TMP49:%.*]] = select i1 [[TMP42]], i32 [[TMP48]], i32 [[TMP47]] +; CHECK-NEXT: [[TMP50:%.*]] = xor i32 [[TMP49]], [[TMP5]] +; CHECK-NEXT: [[TMP51:%.*]] = sub i32 [[TMP50]], [[TMP5]] +; CHECK-NEXT: [[TMP52:%.*]] = insertelement <2 x i32> undef, i32 [[TMP51]], i64 0 +; CHECK-NEXT: [[TMP53:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP54:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 +; CHECK-NEXT: [[TMP55:%.*]] = ashr i32 [[TMP53]], 31 +; CHECK-NEXT: [[TMP56:%.*]] = ashr i32 [[TMP54]], 31 +; CHECK-NEXT: [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]] +; CHECK-NEXT: [[TMP58:%.*]] = add i32 [[TMP53]], [[TMP55]] +; CHECK-NEXT: [[TMP59:%.*]] = add i32 [[TMP54]], [[TMP56]] +; CHECK-NEXT: [[TMP60:%.*]] = xor i32 [[TMP58]], [[TMP55]] +; CHECK-NEXT: [[TMP61:%.*]] = xor i32 [[TMP59]], [[TMP56]] +; CHECK-NEXT: [[TMP62:%.*]] = uitofp i32 [[TMP61]] to float +; CHECK-NEXT: [[TMP63:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP62]]) +; CHECK-NEXT: [[TMP64:%.*]] = fmul fast float [[TMP63]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP65:%.*]] = fptoui float [[TMP64]] to i32 +; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP65]] to i64 +; CHECK-NEXT: [[TMP67:%.*]] = zext i32 [[TMP61]] to i64 +; CHECK-NEXT: [[TMP68:%.*]] = mul i64 [[TMP66]], [[TMP67]] +; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32 +; CHECK-NEXT: [[TMP70:%.*]] = lshr i64 [[TMP68]], 32 +; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 +; CHECK-NEXT: [[TMP72:%.*]] = sub i32 0, [[TMP69]] +; CHECK-NEXT: [[TMP73:%.*]] = icmp eq i32 [[TMP71]], 0 +; CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP73]], i32 [[TMP72]], i32 [[TMP69]] +; CHECK-NEXT: [[TMP75:%.*]] = zext i32 [[TMP74]] to i64 +; CHECK-NEXT: [[TMP76:%.*]] = zext i32 [[TMP65]] to i64 +; CHECK-NEXT: [[TMP77:%.*]] = mul i64 [[TMP75]], [[TMP76]] +; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32 +; CHECK-NEXT: [[TMP79:%.*]] = lshr i64 [[TMP77]], 32 +; CHECK-NEXT: [[TMP80:%.*]] = trunc i64 [[TMP79]] to i32 +; CHECK-NEXT: [[TMP81:%.*]] = add i32 [[TMP65]], [[TMP80]] +; CHECK-NEXT: [[TMP82:%.*]] = sub i32 [[TMP65]], [[TMP80]] +; CHECK-NEXT: [[TMP83:%.*]] = select i1 [[TMP73]], i32 [[TMP81]], i32 [[TMP82]] +; CHECK-NEXT: [[TMP84:%.*]] = zext i32 [[TMP83]] to i64 +; CHECK-NEXT: [[TMP85:%.*]] = zext i32 [[TMP60]] to i64 +; CHECK-NEXT: [[TMP86:%.*]] = mul i64 [[TMP84]], [[TMP85]] +; CHECK-NEXT: [[TMP87:%.*]] = trunc i64 [[TMP86]] to i32 +; CHECK-NEXT: [[TMP88:%.*]] = lshr i64 [[TMP86]], 32 +; CHECK-NEXT: [[TMP89:%.*]] = trunc i64 [[TMP88]] to i32 +; CHECK-NEXT: [[TMP90:%.*]] = mul i32 [[TMP89]], [[TMP61]] +; CHECK-NEXT: [[TMP91:%.*]] = sub i32 [[TMP60]], [[TMP90]] +; CHECK-NEXT: [[TMP92:%.*]] = icmp uge i32 [[TMP91]], [[TMP61]] +; CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP94:%.*]] = icmp uge i32 [[TMP60]], [[TMP90]] +; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP94]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP96:%.*]] = and i32 [[TMP93]], [[TMP95]] +; CHECK-NEXT: [[TMP97:%.*]] = icmp eq i32 [[TMP96]], 0 +; CHECK-NEXT: [[TMP98:%.*]] = add i32 [[TMP89]], 1 +; CHECK-NEXT: [[TMP99:%.*]] = sub i32 [[TMP89]], 1 +; CHECK-NEXT: [[TMP100:%.*]] = select i1 [[TMP97]], i32 [[TMP89]], i32 [[TMP98]] +; CHECK-NEXT: [[TMP101:%.*]] = select i1 [[TMP94]], i32 [[TMP100]], i32 [[TMP99]] +; CHECK-NEXT: [[TMP102:%.*]] = xor i32 [[TMP101]], [[TMP57]] +; CHECK-NEXT: [[TMP103:%.*]] = sub i32 [[TMP102]], [[TMP57]] +; CHECK-NEXT: [[TMP104:%.*]] = insertelement <2 x i32> [[TMP52]], i32 [[TMP103]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP104]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_v2i32_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd +; GCN-NEXT: s_movk_i32 s4, 0x1000 +; GCN-NEXT: s_mov_b32 s14, 0x4f800000 +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s2, s4, s2 +; GCN-NEXT: s_ashr_i32 s5, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s5 +; GCN-NEXT: s_xor_b32 s13, s2, s5 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s13 +; GCN-NEXT: s_ashr_i32 s2, s6, 31 +; GCN-NEXT: s_lshl_b32 s0, s4, s3 +; GCN-NEXT: s_add_i32 s1, s6, s2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_ashr_i32 s6, s0, 31 +; GCN-NEXT: s_add_i32 s4, s0, s6 +; GCN-NEXT: s_xor_b32 s3, s1, s2 +; GCN-NEXT: v_mul_f32_e32 v0, s14, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: s_xor_b32 s15, s4, s6 +; GCN-NEXT: s_xor_b32 s12, s2, s5 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s13 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s13 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s15 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v2 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s3 +; GCN-NEXT: v_mul_f32_e32 v1, s14, v1 +; GCN-NEXT: v_mul_lo_u32 v2, v0, s13 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s3, v2 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s15 +; GCN-NEXT: v_mul_hi_u32 v5, v1, s15 +; GCN-NEXT: s_ashr_i32 s13, s7, 31 +; GCN-NEXT: s_add_i32 s7, s7, s13 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v4, v4, v1 +; GCN-NEXT: s_xor_b32 s7, s7, s13 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s3, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v4, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v4, v1 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v1, v1, s7 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v2, v1, s15 +; GCN-NEXT: v_xor_b32_e32 v0, s12, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 +; GCN-NEXT: s_xor_b32 s4, s13, s6 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s7, v2 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v3 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s7, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v1 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[2:3] +; GCN-NEXT: v_xor_b32_e32 v1, s4, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s4, v1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl <2 x i32> , %y + %r = sdiv <2 x i32> %x, %shl.y + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) { +; CHECK-LABEL: @srem_i32_oddk_denom( +; CHECK-NEXT: [[R:%.*]] = srem i32 [[X:%.*]], 1235195 +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_i32_oddk_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: v_mov_b32_e32 v0, 0xd9528441 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_hi_i32 v0, s0, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 20, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mul_i32_i24_e32 v0, 0x12d8fb, v0 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = srem i32 %x, 1235195 + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) { +; CHECK-LABEL: @srem_i32_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = srem i32 [[X:%.*]], 4096 +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_i32_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s0, s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: s_lshr_b32 s1, s1, 20 +; GCN-NEXT: s_add_i32 s1, s0, s1 +; GCN-NEXT: s_and_b32 s1, s1, 0xfffff000 +; GCN-NEXT: s_sub_i32 s0, s0, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = srem i32 %x, 4096 + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) { +; CHECK-LABEL: @srem_i32_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31 +; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[SHL_Y]], 31 +; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[X]], [[TMP1]] +; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[SHL_Y]], [[TMP2]] +; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP1]] +; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]] +; CHECK-NEXT: [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float +; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) +; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP9]] to i32 +; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 +; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64 +; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP11]], [[TMP12]] +; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32 +; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 32 +; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32 +; CHECK-NEXT: [[TMP17:%.*]] = sub i32 0, [[TMP14]] +; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP16]], 0 +; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP17]], i32 [[TMP14]] +; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 +; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP10]] to i64 +; CHECK-NEXT: [[TMP22:%.*]] = mul i64 [[TMP20]], [[TMP21]] +; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32 +; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP22]], 32 +; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32 +; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP10]], [[TMP25]] +; CHECK-NEXT: [[TMP27:%.*]] = sub i32 [[TMP10]], [[TMP25]] +; CHECK-NEXT: [[TMP28:%.*]] = select i1 [[TMP18]], i32 [[TMP26]], i32 [[TMP27]] +; CHECK-NEXT: [[TMP29:%.*]] = zext i32 [[TMP28]] to i64 +; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP5]] to i64 +; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[TMP29]], [[TMP30]] +; CHECK-NEXT: [[TMP32:%.*]] = trunc i64 [[TMP31]] to i32 +; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP31]], 32 +; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[TMP33]] to i32 +; CHECK-NEXT: [[TMP35:%.*]] = mul i32 [[TMP34]], [[TMP6]] +; CHECK-NEXT: [[TMP36:%.*]] = sub i32 [[TMP5]], [[TMP35]] +; CHECK-NEXT: [[TMP37:%.*]] = icmp uge i32 [[TMP36]], [[TMP6]] +; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP39:%.*]] = icmp uge i32 [[TMP5]], [[TMP35]] +; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP39]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP41:%.*]] = and i32 [[TMP38]], [[TMP40]] +; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i32 [[TMP41]], 0 +; CHECK-NEXT: [[TMP43:%.*]] = sub i32 [[TMP36]], [[TMP6]] +; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP36]], [[TMP6]] +; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP42]], i32 [[TMP36]], i32 [[TMP43]] +; CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP39]], i32 [[TMP45]], i32 [[TMP44]] +; CHECK-NEXT: [[TMP47:%.*]] = xor i32 [[TMP46]], [[TMP1]] +; CHECK-NEXT: [[TMP48:%.*]] = sub i32 [[TMP47]], [[TMP1]] +; CHECK-NEXT: store i32 [[TMP48]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_i32_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s2, 0x1000, s5 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s10, s2, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10 +; GCN-NEXT: s_ashr_i32 s8, s4, 31 +; GCN-NEXT: s_add_i32 s4, s4, s8 +; GCN-NEXT: s_xor_b32 s9, s4, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s10 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s10 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s9 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s10 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s9, v0 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v0 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, s10, v1 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s10, v1 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[2:3] +; GCN-NEXT: v_xor_b32_e32 v0, s8, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl i32 4096, %y + %r = srem i32 %x, %shl.y + store i32 %r, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_v2i32_pow2k_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x) { +; CHECK-LABEL: @srem_v2i32_pow2k_denom( +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = srem i32 [[TMP1]], 4096 +; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i64 0 +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP5:%.*]] = srem i32 [[TMP4]], 4096 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP5]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP6]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_v2i32_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb +; GCN-NEXT: s_movk_i32 s2, 0xf000 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s3, s0, 31 +; GCN-NEXT: s_lshr_b32 s3, s3, 20 +; GCN-NEXT: s_add_i32 s3, s0, s3 +; GCN-NEXT: s_and_b32 s3, s3, s2 +; GCN-NEXT: s_sub_i32 s0, s0, s3 +; GCN-NEXT: s_ashr_i32 s3, s1, 31 +; GCN-NEXT: s_lshr_b32 s3, s3, 20 +; GCN-NEXT: s_add_i32 s3, s1, s3 +; GCN-NEXT: s_and_b32 s2, s3, s2 +; GCN-NEXT: s_sub_i32 s1, s1, s2 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = srem <2 x i32> %x, + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) { +; CHECK-LABEL: @srem_v2i32_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i32> , [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[X:%.*]], i64 0 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 0 +; CHECK-NEXT: [[TMP3:%.*]] = ashr i32 [[TMP1]], 31 +; CHECK-NEXT: [[TMP4:%.*]] = ashr i32 [[TMP2]], 31 +; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP1]], [[TMP3]] +; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP2]], [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP3]] +; CHECK-NEXT: [[TMP8:%.*]] = xor i32 [[TMP6]], [[TMP4]] +; CHECK-NEXT: [[TMP9:%.*]] = uitofp i32 [[TMP8]] to float +; CHECK-NEXT: [[TMP10:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP9]]) +; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP10]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP12:%.*]] = fptoui float [[TMP11]] to i32 +; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP12]] to i64 +; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP8]] to i64 +; CHECK-NEXT: [[TMP15:%.*]] = mul i64 [[TMP13]], [[TMP14]] +; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32 +; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP15]], 32 +; CHECK-NEXT: [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32 +; CHECK-NEXT: [[TMP19:%.*]] = sub i32 0, [[TMP16]] +; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i32 [[TMP18]], 0 +; CHECK-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP19]], i32 [[TMP16]] +; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64 +; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP12]] to i64 +; CHECK-NEXT: [[TMP24:%.*]] = mul i64 [[TMP22]], [[TMP23]] +; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32 +; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP24]], 32 +; CHECK-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP26]] to i32 +; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[TMP12]], [[TMP27]] +; CHECK-NEXT: [[TMP29:%.*]] = sub i32 [[TMP12]], [[TMP27]] +; CHECK-NEXT: [[TMP30:%.*]] = select i1 [[TMP20]], i32 [[TMP28]], i32 [[TMP29]] +; CHECK-NEXT: [[TMP31:%.*]] = zext i32 [[TMP30]] to i64 +; CHECK-NEXT: [[TMP32:%.*]] = zext i32 [[TMP7]] to i64 +; CHECK-NEXT: [[TMP33:%.*]] = mul i64 [[TMP31]], [[TMP32]] +; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[TMP33]] to i32 +; CHECK-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP33]], 32 +; CHECK-NEXT: [[TMP36:%.*]] = trunc i64 [[TMP35]] to i32 +; CHECK-NEXT: [[TMP37:%.*]] = mul i32 [[TMP36]], [[TMP8]] +; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP7]], [[TMP37]] +; CHECK-NEXT: [[TMP39:%.*]] = icmp uge i32 [[TMP38]], [[TMP8]] +; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP39]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP41:%.*]] = icmp uge i32 [[TMP7]], [[TMP37]] +; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP43:%.*]] = and i32 [[TMP40]], [[TMP42]] +; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], 0 +; CHECK-NEXT: [[TMP45:%.*]] = sub i32 [[TMP38]], [[TMP8]] +; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP38]], [[TMP8]] +; CHECK-NEXT: [[TMP47:%.*]] = select i1 [[TMP44]], i32 [[TMP38]], i32 [[TMP45]] +; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP41]], i32 [[TMP47]], i32 [[TMP46]] +; CHECK-NEXT: [[TMP49:%.*]] = xor i32 [[TMP48]], [[TMP3]] +; CHECK-NEXT: [[TMP50:%.*]] = sub i32 [[TMP49]], [[TMP3]] +; CHECK-NEXT: [[TMP51:%.*]] = insertelement <2 x i32> undef, i32 [[TMP50]], i64 0 +; CHECK-NEXT: [[TMP52:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP53:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 +; CHECK-NEXT: [[TMP54:%.*]] = ashr i32 [[TMP52]], 31 +; CHECK-NEXT: [[TMP55:%.*]] = ashr i32 [[TMP53]], 31 +; CHECK-NEXT: [[TMP56:%.*]] = add i32 [[TMP52]], [[TMP54]] +; CHECK-NEXT: [[TMP57:%.*]] = add i32 [[TMP53]], [[TMP55]] +; CHECK-NEXT: [[TMP58:%.*]] = xor i32 [[TMP56]], [[TMP54]] +; CHECK-NEXT: [[TMP59:%.*]] = xor i32 [[TMP57]], [[TMP55]] +; CHECK-NEXT: [[TMP60:%.*]] = uitofp i32 [[TMP59]] to float +; CHECK-NEXT: [[TMP61:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP60]]) +; CHECK-NEXT: [[TMP62:%.*]] = fmul fast float [[TMP61]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP63:%.*]] = fptoui float [[TMP62]] to i32 +; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[TMP63]] to i64 +; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP59]] to i64 +; CHECK-NEXT: [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]] +; CHECK-NEXT: [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32 +; CHECK-NEXT: [[TMP68:%.*]] = lshr i64 [[TMP66]], 32 +; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32 +; CHECK-NEXT: [[TMP70:%.*]] = sub i32 0, [[TMP67]] +; CHECK-NEXT: [[TMP71:%.*]] = icmp eq i32 [[TMP69]], 0 +; CHECK-NEXT: [[TMP72:%.*]] = select i1 [[TMP71]], i32 [[TMP70]], i32 [[TMP67]] +; CHECK-NEXT: [[TMP73:%.*]] = zext i32 [[TMP72]] to i64 +; CHECK-NEXT: [[TMP74:%.*]] = zext i32 [[TMP63]] to i64 +; CHECK-NEXT: [[TMP75:%.*]] = mul i64 [[TMP73]], [[TMP74]] +; CHECK-NEXT: [[TMP76:%.*]] = trunc i64 [[TMP75]] to i32 +; CHECK-NEXT: [[TMP77:%.*]] = lshr i64 [[TMP75]], 32 +; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32 +; CHECK-NEXT: [[TMP79:%.*]] = add i32 [[TMP63]], [[TMP78]] +; CHECK-NEXT: [[TMP80:%.*]] = sub i32 [[TMP63]], [[TMP78]] +; CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP71]], i32 [[TMP79]], i32 [[TMP80]] +; CHECK-NEXT: [[TMP82:%.*]] = zext i32 [[TMP81]] to i64 +; CHECK-NEXT: [[TMP83:%.*]] = zext i32 [[TMP58]] to i64 +; CHECK-NEXT: [[TMP84:%.*]] = mul i64 [[TMP82]], [[TMP83]] +; CHECK-NEXT: [[TMP85:%.*]] = trunc i64 [[TMP84]] to i32 +; CHECK-NEXT: [[TMP86:%.*]] = lshr i64 [[TMP84]], 32 +; CHECK-NEXT: [[TMP87:%.*]] = trunc i64 [[TMP86]] to i32 +; CHECK-NEXT: [[TMP88:%.*]] = mul i32 [[TMP87]], [[TMP59]] +; CHECK-NEXT: [[TMP89:%.*]] = sub i32 [[TMP58]], [[TMP88]] +; CHECK-NEXT: [[TMP90:%.*]] = icmp uge i32 [[TMP89]], [[TMP59]] +; CHECK-NEXT: [[TMP91:%.*]] = select i1 [[TMP90]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP92:%.*]] = icmp uge i32 [[TMP58]], [[TMP88]] +; CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i32 -1, i32 0 +; CHECK-NEXT: [[TMP94:%.*]] = and i32 [[TMP91]], [[TMP93]] +; CHECK-NEXT: [[TMP95:%.*]] = icmp eq i32 [[TMP94]], 0 +; CHECK-NEXT: [[TMP96:%.*]] = sub i32 [[TMP89]], [[TMP59]] +; CHECK-NEXT: [[TMP97:%.*]] = add i32 [[TMP89]], [[TMP59]] +; CHECK-NEXT: [[TMP98:%.*]] = select i1 [[TMP95]], i32 [[TMP89]], i32 [[TMP96]] +; CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP92]], i32 [[TMP98]], i32 [[TMP97]] +; CHECK-NEXT: [[TMP100:%.*]] = xor i32 [[TMP99]], [[TMP54]] +; CHECK-NEXT: [[TMP101:%.*]] = sub i32 [[TMP100]], [[TMP54]] +; CHECK-NEXT: [[TMP102:%.*]] = insertelement <2 x i32> [[TMP51]], i32 [[TMP101]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP102]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_v2i32_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd +; GCN-NEXT: s_movk_i32 s4, 0x1000 +; GCN-NEXT: s_mov_b32 s14, 0x4f800000 +; GCN-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0xb +; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b32 s2, s4, s2 +; GCN-NEXT: s_ashr_i32 s5, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s5 +; GCN-NEXT: s_xor_b32 s13, s2, s5 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s13 +; GCN-NEXT: s_lshl_b32 s2, s4, s3 +; GCN-NEXT: s_ashr_i32 s12, s6, 31 +; GCN-NEXT: s_add_i32 s3, s6, s12 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_ashr_i32 s4, s2, 31 +; GCN-NEXT: s_add_i32 s6, s2, s4 +; GCN-NEXT: s_xor_b32 s5, s3, s12 +; GCN-NEXT: v_mul_f32_e32 v0, s14, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: s_xor_b32 s15, s6, s4 +; GCN-NEXT: s_ashr_i32 s6, s7, 31 +; GCN-NEXT: s_add_i32 s7, s7, s6 +; GCN-NEXT: v_mul_lo_u32 v1, v0, s13 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s13 +; GCN-NEXT: s_xor_b32 s7, s7, s6 +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s15 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v1, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v2 +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v0, v0, s5 +; GCN-NEXT: v_mul_f32_e32 v1, s14, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s13 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s15 +; GCN-NEXT: v_mul_hi_u32 v5, v1, s15 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s5, v0 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s5, v0 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v4 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v6, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v4, v4, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, s13, v2 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s13, v2 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v4, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, v4, v1 +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v5, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v1, v1, s7 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v1, v1, s15 +; GCN-NEXT: v_xor_b32_e32 v0, s12, v0 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v1 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s7, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, s15, v2 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s15, v2 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[2:3] +; GCN-NEXT: v_xor_b32_e32 v1, s6, v1 +; GCN-NEXT: v_subrev_i32_e32 v1, vcc, s6, v1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl <2 x i32> , %y + %r = srem <2 x i32> %x, %shl.y + store <2 x i32> %r, <2 x i32> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { +; CHECK-LABEL: @udiv_i64_oddk_denom( +; CHECK-NEXT: [[R:%.*]] = udiv i64 [[X:%.*]], 1235195949943 +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_i64_oddk_denom: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, 0x4f176a73 +; GCN-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GCN-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_movk_i32 s2, 0xfee0 +; GCN-NEXT: s_mov_b32 s3, 0x68958c89 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: v_mul_lo_u32 v2, v0, s2 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s3 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s3 +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s8, s4 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, v0, s3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: s_mov_b32 s4, 0x976a7376 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v1, v3 +; GCN-NEXT: v_mul_hi_u32 v3, v1, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 +; GCN-NEXT: v_mul_hi_u32 v5, v0, s3 +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, v2, s3 +; GCN-NEXT: s_movk_i32 s2, 0x11f +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, s3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v2, v4 +; GCN-NEXT: s_mov_b32 s3, 0x976a7377 +; GCN-NEXT: s_mov_b32 s9, s5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s6, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 +; GCN-NEXT: v_mul_hi_u32 v4, s6, v1 +; GCN-NEXT: v_mul_hi_u32 v5, s7, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s7, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s7, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v0, s2 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s3 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s3 +; GCN-NEXT: v_mov_b32_e32 v5, s2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, v0, s3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s7, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s6, v3 +; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc +; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s3, v3 +; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: s_movk_i32 s3, 0x11e +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s3, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s4, v5 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] +; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 +; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v6, s7 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s3, v2 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s4, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s2, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 +; GCN-NEXT: s_endpgm + %r = udiv i64 %x, 1235195949943 + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { +; CHECK-LABEL: @udiv_i64_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = udiv i64 [[X:%.*]], 4096 +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_i64_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_lshr_b64 s[4:5], s[6:7], 12 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm + %r = udiv i64 %x, 4096 + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) { +; CHECK-LABEL: @udiv_i64_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = udiv i64 [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_i64_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s8, s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_add_i32 s8, s8, 12 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_lshr_b64 s[4:5], s[6:7], s8 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl i64 4096, %y + %r = udiv i64 %x, %shl.y + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) { +; CHECK-LABEL: @udiv_v2i64_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = udiv <2 x i64> [[X:%.*]], +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_v2i64_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 12 +; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 12 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = udiv <2 x i64> %x, + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) { +; CHECK-LABEL: @udiv_v2i64_mixed_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = udiv <2 x i64> [[X:%.*]], +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_v2i64_mixed_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_movk_i32 s4, 0xf001 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v2, 0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s4 +; GCN-NEXT: v_mul_lo_u32 v5, v1, s4 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s4 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v2, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_mul_hi_u32 v5, v0, s4 +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v1, v4, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v6, v3, s4 +; GCN-NEXT: v_mul_lo_u32 v8, v0, s4 +; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v8 +; GCN-NEXT: v_mul_hi_u32 v10, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v3, v5 +; GCN-NEXT: s_movk_i32 s0, 0xfff +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v3, v8 +; GCN-NEXT: v_mul_hi_u32 v8, v3, v8 +; GCN-NEXT: v_mul_lo_u32 v3, v3, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v11, v2, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v3, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v4, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v6, s11, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v1, s0 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s0 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s10, v4 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s0, v4 +; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc +; GCN-NEXT: s_movk_i32 s0, 0xffe +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 +; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0 +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v3, v1, v3, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v0, v1, s[0:1] +; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], 12 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = udiv <2 x i64> %x, + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { +; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> , [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = udiv <2 x i64> [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: udiv_v2i64_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_add_i32 s1, s2, 12 +; GCN-NEXT: s_add_i32 s0, s0, 12 +; GCN-NEXT: s_lshr_b64 s[2:3], s[10:11], s1 +; GCN-NEXT: s_lshr_b64 s[0:1], s[8:9], s0 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl <2 x i64> , %y + %r = udiv <2 x i64> %x, %shl.y + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { +; CHECK-LABEL: @urem_i64_oddk_denom( +; CHECK-NEXT: [[R:%.*]] = urem i64 [[X:%.*]], 1235195393993 +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_i64_oddk_denom: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, 0x4f1761f8 +; GCN-NEXT: v_mov_b32_e32 v1, 0x4f800000 +; GCN-NEXT: v_madmk_f32 v0, v1, 0x438f8000, v0 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_movk_i32 s2, 0xfee0 +; GCN-NEXT: s_mov_b32 s3, 0x689e0837 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: v_mul_lo_u32 v2, v0, s2 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s3 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s3 +; GCN-NEXT: s_mov_b32 s12, 0x9761f7c9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s8, s4 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, v0, s3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: s_movk_i32 s4, 0x11f +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v1, v3 +; GCN-NEXT: v_mul_hi_u32 v3, v1, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 +; GCN-NEXT: v_mul_hi_u32 v5, v0, s3 +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, v2, s3 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, s3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v2, v4 +; GCN-NEXT: s_mov_b32 s9, s5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s6, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 +; GCN-NEXT: v_mul_hi_u32 v4, s6, v1 +; GCN-NEXT: v_mul_hi_u32 v5, s7, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s7, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s7, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v0, s4 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s12 +; GCN-NEXT: v_mul_lo_u32 v1, v1, s12 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s12 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s7, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s4 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 +; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 +; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: s_movk_i32 s2, 0x11e +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s2, v2 +; GCN-NEXT: s_mov_b32 s3, 0x9761f7c8 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s3, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s4, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s12, v4 +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v3, s7 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s2, v1 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s3, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s4, v1 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 +; GCN-NEXT: s_endpgm + %r = urem i64 %x, 1235195393993 + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { +; CHECK-LABEL: @urem_i64_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = urem i64 [[X:%.*]], 4096 +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_i64_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_and_b32 s4, s6, 0xfff +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm + %r = urem i64 %x, 4096 + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) { +; CHECK-LABEL: @urem_i64_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = urem i64 [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_i64_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s8, s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_mov_b32 s5, 0 +; GCN-NEXT: s_movk_i32 s4, 0x1000 +; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], s8 +; GCN-NEXT: s_add_u32 s4, s4, -1 +; GCN-NEXT: s_addc_u32 s5, s5, -1 +; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5] +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl i64 4096, %y + %r = urem i64 %x, %shl.y + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) { +; CHECK-LABEL: @urem_v2i64_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = urem <2 x i64> [[X:%.*]], +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_v2i64_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd +; GCN-NEXT: s_movk_i32 s8, 0xfff +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s1, s2, s8 +; GCN-NEXT: s_and_b32 s0, s0, s8 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v2, s1 +; GCN-NEXT: v_mov_b32_e32 v3, v1 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = urem <2 x i64> %x, + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @urem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { +; CHECK-LABEL: @urem_v2i64_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> , [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = urem <2 x i64> [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: urem_v2i64_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 +; GCN-NEXT: s_mov_b32 s13, 0 +; GCN-NEXT: s_movk_i32 s12, 0x1000 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b64 s[0:1], s[12:13], s0 +; GCN-NEXT: s_lshl_b64 s[2:3], s[12:13], s2 +; GCN-NEXT: s_add_u32 s2, s2, -1 +; GCN-NEXT: s_addc_u32 s3, s3, -1 +; GCN-NEXT: s_and_b64 s[2:3], s[10:11], s[2:3] +; GCN-NEXT: s_add_u32 s0, s0, -1 +; GCN-NEXT: s_addc_u32 s1, s1, -1 +; GCN-NEXT: s_and_b64 s[0:1], s[8:9], s[0:1] +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl <2 x i64> , %y + %r = urem <2 x i64> %x, %shl.y + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { +; CHECK-LABEL: @sdiv_i64_oddk_denom( +; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], 1235195 +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_i64_oddk_denom: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s2, 0xffed2705 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v2, v1, s2 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc +; GCN-NEXT: s_mov_b32 s5, s9 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v4, v2, s2 +; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, s2 +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v8, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v10 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: s_ashr_i32 s2, s11, 31 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] +; GCN-NEXT: s_add_u32 s0, s10, s2 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: s_mov_b32 s3, s2 +; GCN-NEXT: s_addc_u32 s1, s11, s2 +; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v1 +; GCN-NEXT: v_mul_hi_u32 v5, s1, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s1, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s1, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s1, v0 +; GCN-NEXT: s_mov_b32 s3, 0x12d8fb +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v1, s3 +; GCN-NEXT: v_mul_hi_u32 v3, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s0, v4 +; GCN-NEXT: v_mov_b32_e32 v3, s1 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s3, v4 +; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc +; GCN-NEXT: s_mov_b32 s0, 0x12d8fa +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 +; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0 +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] +; GCN-NEXT: v_xor_b32_e32 v0, s2, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s2, v1 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = sdiv i64 %x, 1235195 + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { +; CHECK-LABEL: @sdiv_i64_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], 4096 +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_i64_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_ashr_i32 s4, s7, 31 +; GCN-NEXT: s_lshr_b32 s4, s4, 20 +; GCN-NEXT: s_add_u32 s4, s6, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_addc_u32 s5, s7, 0 +; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], 12 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm + %r = sdiv i64 %x, 4096 + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) { +; CHECK-LABEL: @sdiv_i64_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = sdiv i64 [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_i64_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s4, s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s3, 0 +; GCN-NEXT: s_movk_i32 s2, 0x1000 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 +; GCN-NEXT: s_ashr_i32 s12, s3, 31 +; GCN-NEXT: s_add_u32 s2, s2, s12 +; GCN-NEXT: s_mov_b32 s13, s12 +; GCN-NEXT: s_addc_u32 s3, s3, s12 +; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-NEXT: s_sub_u32 s4, 0, s2 +; GCN-NEXT: s_subb_u32 s5, 0, s3 +; GCN-NEXT: s_ashr_i32 s14, s11, 31 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s15, s14 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 +; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v7, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v5, s4, v2 +; GCN-NEXT: v_mul_hi_u32 v7, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s5, v0 +; GCN-NEXT: s_mov_b32 s5, s9 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v7, s4, v0 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v5 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, v5 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1] +; GCN-NEXT: s_add_u32 s0, s10, s14 +; GCN-NEXT: s_addc_u32 s1, s11, s14 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v7, s11, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 +; GCN-NEXT: v_mov_b32_e32 v5, s3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, s2, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 +; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc +; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 +; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] +; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 +; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v6, s11 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_xor_b32_e32 v0, s0, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s1, v1 +; GCN-NEXT: v_mov_b32_e32 v2, s1 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl i64 4096, %y + %r = sdiv i64 %x, %shl.y + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) { +; CHECK-LABEL: @sdiv_v2i64_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = sdiv <2 x i64> [[X:%.*]], +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_v2i64_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s8, s3, 31 +; GCN-NEXT: s_lshr_b32 s8, s8, 20 +; GCN-NEXT: s_add_u32 s2, s2, s8 +; GCN-NEXT: s_addc_u32 s3, s3, 0 +; GCN-NEXT: s_ashr_i32 s8, s1, 31 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 12 +; GCN-NEXT: s_lshr_b32 s8, s8, 20 +; GCN-NEXT: s_add_u32 s0, s0, s8 +; GCN-NEXT: s_addc_u32 s1, s1, 0 +; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = sdiv <2 x i64> %x, + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) { +; CHECK-LABEL: @ssdiv_v2i64_mixed_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = sdiv <2 x i64> [[X:%.*]], +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: ssdiv_v2i64_mixed_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_movk_i32 s6, 0xf001 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v5, 0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 +; GCN-NEXT: v_mul_lo_u32 v2, v1, s6 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s6 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v8, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v4, vcc +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v4, v2, s6 +; GCN-NEXT: v_mul_hi_u32 v6, s6, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v6, v0, s6 +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v7, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v5, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v6, v2 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[2:3] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s11, 31 +; GCN-NEXT: s_add_u32 s0, s10, s2 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: s_mov_b32 s3, s2 +; GCN-NEXT: s_addc_u32 s1, s11, s2 +; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v1 +; GCN-NEXT: v_mul_hi_u32 v6, s1, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s1, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s1, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s1, v0 +; GCN-NEXT: s_movk_i32 s3, 0xfff +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v1, s3 +; GCN-NEXT: v_mul_hi_u32 v3, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s0, v4 +; GCN-NEXT: v_mov_b32_e32 v3, s1 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, s3, v4 +; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc +; GCN-NEXT: s_movk_i32 s0, 0xffe +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 +; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0 +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v4 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc +; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: s_ashr_i32 s0, s9, 31 +; GCN-NEXT: s_lshr_b32 s0, s0, 20 +; GCN-NEXT: s_add_u32 s0, s8, s0 +; GCN-NEXT: s_addc_u32 s1, s9, 0 +; GCN-NEXT: v_xor_b32_e32 v0, s2, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s2, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0 +; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 12 +; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = sdiv <2 x i64> %x, + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { +; CHECK-LABEL: @sdiv_v2i64_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> , [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = sdiv <2 x i64> [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: sdiv_v2i64_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 +; GCN-NEXT: s_mov_b32 s3, 0 +; GCN-NEXT: s_movk_i32 s2, 0x1000 +; GCN-NEXT: s_mov_b32 s18, 0x4f800000 +; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b64 s[12:13], s[2:3], s4 +; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s6 +; GCN-NEXT: s_ashr_i32 s16, s3, 31 +; GCN-NEXT: s_add_u32 s2, s2, s16 +; GCN-NEXT: s_mov_b32 s17, s16 +; GCN-NEXT: s_addc_u32 s3, s3, s16 +; GCN-NEXT: s_xor_b64 s[14:15], s[2:3], s[16:17] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s14 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s15 +; GCN-NEXT: s_mov_b32 s20, 0x2f800000 +; GCN-NEXT: s_mov_b32 s21, 0xcf800000 +; GCN-NEXT: s_sub_u32 s6, 0, s14 +; GCN-NEXT: v_mac_f32_e32 v0, s18, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_subb_u32 s7, 0, s15 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-NEXT: v_mul_f32_e32 v0, s19, v0 +; GCN-NEXT: v_mul_f32_e32 v1, s20, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, s21, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 +; GCN-NEXT: v_mul_lo_u32 v2, s6, v1 +; GCN-NEXT: v_mul_lo_u32 v4, s7, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s6, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v3, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v7, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v1, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v1, v5 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v5, s6, v2 +; GCN-NEXT: v_mul_hi_u32 v7, s6, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s7, v0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v7, s6, v0 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v5 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, v5 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s2, s11, 31 +; GCN-NEXT: s_add_u32 s0, s10, s2 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: s_mov_b32 s3, s2 +; GCN-NEXT: s_addc_u32 s1, s11, s2 +; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[2:3] +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v7, s11, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[16:17] +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s14, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s14, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s15, v0 +; GCN-NEXT: v_mov_b32_e32 v7, s15 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, s14, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, s11, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 +; GCN-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v7, vcc +; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s14, v3 +; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s15, v5 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v7 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s15, v5 +; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v7, s[0:1] +; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v0 +; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: s_ashr_i32 s10, s13, 31 +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: s_add_u32 s12, s12, s10 +; GCN-NEXT: v_cndmask_b32_e64 v5, v10, v8, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v8, s11 +; GCN-NEXT: s_mov_b32 s11, s10 +; GCN-NEXT: s_addc_u32 s13, s13, s10 +; GCN-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11] +; GCN-NEXT: v_cvt_f32_u32_e32 v10, s12 +; GCN-NEXT: v_cvt_f32_u32_e32 v11, s13 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s15, v2 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s14, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s15, v2 +; GCN-NEXT: v_mac_f32_e32 v10, s18, v11 +; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc +; GCN-NEXT: v_rcp_f32_e32 v3, v10 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GCN-NEXT: s_sub_u32 s14, 0, s12 +; GCN-NEXT: v_mul_f32_e32 v3, s19, v3 +; GCN-NEXT: v_mul_f32_e32 v5, s20, v3 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_mac_f32_e32 v3, s21, v5 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_cndmask_b32_e64 v2, v9, v7, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_mul_hi_u32 v2, s14, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s14, v5 +; GCN-NEXT: s_subb_u32 s15, 0, s13 +; GCN-NEXT: v_mul_lo_u32 v8, s15, v3 +; GCN-NEXT: v_xor_b32_e32 v0, s2, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7 +; GCN-NEXT: v_mul_lo_u32 v7, s14, v3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v11, v5, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v5, v2 +; GCN-NEXT: v_xor_b32_e32 v1, s3, v1 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v5, v7 +; GCN-NEXT: v_mul_hi_u32 v7, v5, v7 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2 +; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v8, s14, v3 +; GCN-NEXT: v_mul_hi_u32 v9, s14, v2 +; GCN-NEXT: v_mul_lo_u32 v10, s15, v2 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_mul_lo_u32 v9, s14, v2 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_mul_lo_u32 v12, v2, v8 +; GCN-NEXT: v_mul_hi_u32 v14, v2, v8 +; GCN-NEXT: v_mul_hi_u32 v13, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v11, v3, v9 +; GCN-NEXT: v_mul_lo_u32 v9, v3, v9 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v8 +; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12 +; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v3, v8 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: s_ashr_i32 s14, s9, 31 +; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1] +; GCN-NEXT: s_add_u32 s0, s8, s14 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GCN-NEXT: s_mov_b32 s15, s14 +; GCN-NEXT: s_addc_u32 s1, s9, s14 +; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[14:15] +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 +; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 +; GCN-NEXT: v_mul_hi_u32 v9, s8, v3 +; GCN-NEXT: v_mul_hi_u32 v10, s9, v3 +; GCN-NEXT: v_mul_lo_u32 v3, s9, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v9, s9, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s9, v2 +; GCN-NEXT: v_mov_b32_e32 v8, s3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v6, s12, v4 +; GCN-NEXT: v_mul_hi_u32 v7, s12, v5 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s13, v5 +; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v8, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v7, v6 +; GCN-NEXT: v_mov_b32_e32 v7, s13 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s12, v5 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, s9, v0 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v1 +; GCN-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc +; GCN-NEXT: v_subrev_i32_e64 v7, s[0:1], s12, v1 +; GCN-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6 +; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] +; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v5 +; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: v_add_i32_e64 v9, s[0:1], 1, v5 +; GCN-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 +; GCN-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v8, s9 +; GCN-NEXT: v_subb_u32_e32 v0, vcc, v8, v0, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v0 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v1 +; GCN-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[10:11] +; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc +; GCN-NEXT: v_xor_b32_e32 v1, s0, v1 +; GCN-NEXT: v_xor_b32_e32 v4, s1, v0 +; GCN-NEXT: v_mov_b32_e32 v5, s1 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v1 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v5, vcc +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl <2 x i64> , %y + %r = sdiv <2 x i64> %x, %shl.y + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { +; CHECK-LABEL: @srem_i64_oddk_denom( +; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], 1235195 +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_i64_oddk_denom: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 +; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s2, 0xffed2705 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v2, v1, s2 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc +; GCN-NEXT: s_mov_b32 s5, s9 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v4, v2, s2 +; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, s2 +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v8, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v10 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: s_ashr_i32 s2, s11, 31 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] +; GCN-NEXT: s_add_u32 s0, s10, s2 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: s_mov_b32 s3, s2 +; GCN-NEXT: s_addc_u32 s1, s11, s2 +; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v1 +; GCN-NEXT: v_mul_hi_u32 v5, s1, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s1, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s1, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s1, v0 +; GCN-NEXT: s_mov_b32 s3, 0x12d8fb +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GCN-NEXT: v_mul_hi_u32 v2, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v1, v1, s3 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s3 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: v_mov_b32_e32 v2, s1 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s3, v0 +; GCN-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, s3, v2 +; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc +; GCN-NEXT: s_mov_b32 s0, 0x12d8fa +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, s0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v0 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1 +; GCN-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] +; GCN-NEXT: v_xor_b32_e32 v0, s2, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s2, v1 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = srem i64 %x, 1235195 + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) { +; CHECK-LABEL: @srem_i64_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], 4096 +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_i64_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_ashr_i32 s4, s7, 31 +; GCN-NEXT: s_lshr_b32 s4, s4, 20 +; GCN-NEXT: s_add_u32 s4, s6, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_addc_u32 s5, s7, 0 +; GCN-NEXT: s_and_b32 s4, s4, 0xfffff000 +; GCN-NEXT: s_sub_u32 s4, s6, s4 +; GCN-NEXT: s_subb_u32 s5, s7, s5 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_endpgm + %r = srem i64 %x, 4096 + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 %x, i64 %y) { +; CHECK-LABEL: @srem_i64_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl i64 4096, [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = srem i64 [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_i64_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s4, s[0:1], 0xd +; GCN-NEXT: s_mov_b32 s3, 0 +; GCN-NEXT: s_movk_i32 s2, 0x1000 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s4 +; GCN-NEXT: s_ashr_i32 s4, s3, 31 +; GCN-NEXT: s_add_u32 s2, s2, s4 +; GCN-NEXT: s_mov_b32 s5, s4 +; GCN-NEXT: s_addc_u32 s3, s3, s4 +; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[4:5] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 +; GCN-NEXT: s_sub_u32 s2, 0, s12 +; GCN-NEXT: s_subb_u32 s3, 0, s13 +; GCN-NEXT: s_ashr_i32 s14, s11, 31 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s15, s14 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_mov_b32 s5, s9 +; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 +; GCN-NEXT: v_mul_lo_u32 v5, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s2, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v7, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v5, s2, v2 +; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v5 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, v5 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[0:1] +; GCN-NEXT: s_add_u32 s0, s10, s14 +; GCN-NEXT: s_addc_u32 s1, s11, s14 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v7, s11, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s13 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0 +; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 +; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s12, v4 +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_xor_b32_e32 v0, s14, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s14, v1 +; GCN-NEXT: v_mov_b32_e32 v2, s14 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s14, v0 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl i64 4096, %y + %r = srem i64 %x, %shl.y + store i64 %r, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_v2i64_pow2k_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x) { +; CHECK-LABEL: @srem_v2i64_pow2k_denom( +; CHECK-NEXT: [[R:%.*]] = srem <2 x i64> [[X:%.*]], +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_v2i64_pow2k_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd +; GCN-NEXT: s_movk_i32 s8, 0xf000 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s9, s3, 31 +; GCN-NEXT: s_lshr_b32 s9, s9, 20 +; GCN-NEXT: s_add_u32 s9, s2, s9 +; GCN-NEXT: s_addc_u32 s10, s3, 0 +; GCN-NEXT: s_and_b32 s9, s9, s8 +; GCN-NEXT: s_sub_u32 s2, s2, s9 +; GCN-NEXT: s_subb_u32 s3, s3, s10 +; GCN-NEXT: s_ashr_i32 s9, s1, 31 +; GCN-NEXT: s_lshr_b32 s9, s9, 20 +; GCN-NEXT: s_add_u32 s9, s0, s9 +; GCN-NEXT: s_addc_u32 s10, s1, 0 +; GCN-NEXT: s_and_b32 s8, s9, s8 +; GCN-NEXT: s_sub_u32 s0, s0, s8 +; GCN-NEXT: s_subb_u32 s1, s1, s10 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %r = srem <2 x i64> %x, + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { +; CHECK-LABEL: @srem_v2i64_pow2_shl_denom( +; CHECK-NEXT: [[SHL_Y:%.*]] = shl <2 x i64> , [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = srem <2 x i64> [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store <2 x i64> [[R]], <2 x i64> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: ret void +; +; GCN-LABEL: srem_v2i64_pow2_shl_denom: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x11 +; GCN-NEXT: s_mov_b32 s3, 0 +; GCN-NEXT: s_movk_i32 s2, 0x1000 +; GCN-NEXT: s_mov_b32 s18, 0x4f800000 +; GCN-NEXT: s_mov_b32 s19, 0x5f7ffffc +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshl_b64 s[14:15], s[2:3], s4 +; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s6 +; GCN-NEXT: s_ashr_i32 s4, s3, 31 +; GCN-NEXT: s_add_u32 s2, s2, s4 +; GCN-NEXT: s_mov_b32 s5, s4 +; GCN-NEXT: s_addc_u32 s3, s3, s4 +; GCN-NEXT: s_xor_b64 s[16:17], s[2:3], s[4:5] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s16 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s17 +; GCN-NEXT: s_mov_b32 s20, 0x2f800000 +; GCN-NEXT: s_mov_b32 s21, 0xcf800000 +; GCN-NEXT: s_sub_u32 s6, 0, s16 +; GCN-NEXT: v_mac_f32_e32 v0, s18, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_subb_u32 s7, 0, s17 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-NEXT: v_mul_f32_e32 v0, s19, v0 +; GCN-NEXT: v_mul_f32_e32 v1, s20, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, s21, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_ashr_i32 s12, s11, 31 +; GCN-NEXT: s_add_u32 s0, s10, s12 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 +; GCN-NEXT: v_mul_lo_u32 v2, s6, v1 +; GCN-NEXT: v_mul_lo_u32 v4, s7, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s6, v0 +; GCN-NEXT: s_mov_b32 s13, s12 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v3, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v7, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v1, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v1, v5 +; GCN-NEXT: s_addc_u32 s1, s11, s12 +; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[12:13] +; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mov_b32_e32 v6, 0 +; GCN-NEXT: v_add_i32_e64 v0, s[2:3], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v5, s6, v2 +; GCN-NEXT: v_mul_hi_u32 v7, s6, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s7, v0 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v7, s6, v0 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v5 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, v5 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v5, s[2:3] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v7, s11, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v1, s16, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s16, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s17, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s16, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s17 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0 +; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc +; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v0 +; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s17, v2 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s16, v5 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s17, v2 +; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v8, s[0:1], s16, v5 +; GCN-NEXT: s_ashr_i32 s2, s15, 31 +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 +; GCN-NEXT: s_add_u32 s10, s14, s2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: s_mov_b32 s3, s2 +; GCN-NEXT: s_addc_u32 s11, s15, s2 +; GCN-NEXT: s_xor_b64 s[10:11], s[10:11], s[2:3] +; GCN-NEXT: v_cvt_f32_u32_e32 v7, s10 +; GCN-NEXT: v_cvt_f32_u32_e32 v9, s11 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s17, v1 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_mac_f32_e32 v7, s18, v9 +; GCN-NEXT: v_rcp_f32_e32 v7, v7 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s16, v0 +; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s17, v1 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, s19, v7 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v8, s[0:1] +; GCN-NEXT: v_mul_f32_e32 v5, s20, v3 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_mac_f32_e32 v3, s21, v5 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: s_sub_u32 s2, 0, s10 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_mul_hi_u32 v2, s2, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s2, v5 +; GCN-NEXT: s_subb_u32 s3, 0, s11 +; GCN-NEXT: v_mul_lo_u32 v8, s3, v3 +; GCN-NEXT: s_ashr_i32 s14, s9, 31 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7 +; GCN-NEXT: v_mul_lo_u32 v7, s2, v3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v8 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v11, v5, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v5, v2 +; GCN-NEXT: s_mov_b32 s15, s14 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v5, v7 +; GCN-NEXT: v_mul_hi_u32 v7, v5, v7 +; GCN-NEXT: v_xor_b32_e32 v0, s12, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s12, v1 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v11, v4, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v7, v2 +; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v3, v2 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v6, v8, vcc +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v5, v7, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v8, s2, v3 +; GCN-NEXT: v_mul_hi_u32 v9, s2, v2 +; GCN-NEXT: v_mul_lo_u32 v10, s3, v2 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_mul_lo_u32 v9, s2, v2 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_mul_lo_u32 v12, v2, v8 +; GCN-NEXT: v_mul_hi_u32 v14, v2, v8 +; GCN-NEXT: v_mul_hi_u32 v13, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v11, v3, v9 +; GCN-NEXT: v_mul_lo_u32 v9, v3, v9 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v8 +; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12 +; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v3, v8 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v4, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v9, v3 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v6, v8, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1] +; GCN-NEXT: s_add_u32 s0, s8, s14 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GCN-NEXT: s_addc_u32 s1, s9, s14 +; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[14:15] +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 +; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 +; GCN-NEXT: v_mul_hi_u32 v9, s8, v3 +; GCN-NEXT: v_mul_hi_u32 v10, s9, v3 +; GCN-NEXT: v_mul_lo_u32 v3, s9, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v9, s9, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s9, v2 +; GCN-NEXT: v_mov_b32_e32 v8, s12 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v7, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v4, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v2, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s10, v2 +; GCN-NEXT: v_mul_hi_u32 v6, s10, v5 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, s12, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s11, v5 +; GCN-NEXT: v_subb_u32_e32 v3, vcc, v1, v8, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v6, v4 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s10, v5 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s9, v0 +; GCN-NEXT: v_mov_b32_e32 v5, s11 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v1 +; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc +; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s10, v1 +; GCN-NEXT: v_subb_u32_e64 v5, s[2:3], v4, v5, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4 +; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v8, s[0:1], s10, v6 +; GCN-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v5, s9 +; GCN-NEXT: v_subb_u32_e32 v0, vcc, v5, v0, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s11, v0 +; GCN-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v8, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_xor_b32_e32 v1, s14, v1 +; GCN-NEXT: v_xor_b32_e32 v4, s14, v0 +; GCN-NEXT: v_mov_b32_e32 v5, s14 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s14, v1 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v5, vcc +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_endpgm + %shl.y = shl <2 x i64> , %y + %r = srem <2 x i64> %x, %shl.y + store <2 x i64> %r, <2 x i64> addrspace(1)* %out + ret void +} -- GitLab From 3ff4e2eee8c39fd4ae13b1df412f0af219fbf382 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 11 Feb 2020 17:08:48 -0600 Subject: [PATCH 089/142] [OpenMP] Switch default C++ standard to C++ 14 Reviewed By: JonChesterfield Differential Revision: https://reviews.llvm.org/D74258 --- openmp/CMakeLists.txt | 6 +++--- openmp/cmake/HandleOpenMPOptions.cmake | 6 +++--- openmp/cmake/config-ix.cmake | 4 ++-- .../cmake/Modules/LibomptargetNVPTXBitcodeLibrary.cmake | 2 +- openmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt | 2 +- openmp/runtime/test/lit.cfg | 2 +- openmp/tools/archer/tests/lit.cfg | 2 +- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/openmp/CMakeLists.txt b/openmp/CMakeLists.txt index 9825183a0dd7..7007611301f0 100644 --- a/openmp/CMakeLists.txt +++ b/openmp/CMakeLists.txt @@ -62,7 +62,7 @@ set(ENABLE_LIBOMPTARGET ON) # Currently libomptarget cannot be compiled on Windows or MacOS X. # Since the device plugins are only supported on Linux anyway, # there is no point in trying to compile libomptarget on other OSes. -if (APPLE OR WIN32 OR NOT OPENMP_HAVE_STD_CPP11_FLAG) +if (APPLE OR WIN32 OR NOT OPENMP_HAVE_STD_CPP14_FLAG) set(ENABLE_LIBOMPTARGET OFF) endif() @@ -72,8 +72,8 @@ if (OPENMP_ENABLE_LIBOMPTARGET) # Check that the library can actually be built. if (APPLE OR WIN32) message(FATAL_ERROR "libomptarget cannot be built on Windows and MacOS X!") - elseif (NOT OPENMP_HAVE_STD_CPP11_FLAG) - message(FATAL_ERROR "Host compiler must support C++11 to build libomptarget!") + elseif (NOT OPENMP_HAVE_STD_CPP14_FLAG) + message(FATAL_ERROR "Host compiler must support C++14 to build libomptarget!") endif() add_subdirectory(libomptarget) diff --git a/openmp/cmake/HandleOpenMPOptions.cmake b/openmp/cmake/HandleOpenMPOptions.cmake index eb7b286b3383..15382bcf12de 100644 --- a/openmp/cmake/HandleOpenMPOptions.cmake +++ b/openmp/cmake/HandleOpenMPOptions.cmake @@ -29,7 +29,7 @@ append_if(OPENMP_HAVE_WNO_EXTRA_FLAG "-Wno-extra" CMAKE_C_FLAGS CMAKE_CXX_FLAGS) append_if(OPENMP_HAVE_WNO_PEDANTIC_FLAG "-Wno-pedantic" CMAKE_C_FLAGS CMAKE_CXX_FLAGS) append_if(OPENMP_HAVE_WNO_MAYBE_UNINITIALIZED_FLAG "-Wno-maybe-uninitialized" CMAKE_C_FLAGS CMAKE_CXX_FLAGS) -append_if(OPENMP_HAVE_STD_GNUPP11_FLAG "-std=gnu++11" CMAKE_CXX_FLAGS) -if (NOT OPENMP_HAVE_STD_GNUPP11_FLAG) - append_if(OPENMP_HAVE_STD_CPP11_FLAG "-std=c++11" CMAKE_CXX_FLAGS) +append_if(OPENMP_HAVE_STD_GNUPP14_FLAG "-std=gnu++14" CMAKE_CXX_FLAGS) +if (NOT OPENMP_HAVE_STD_GNUPP14_FLAG) + append_if(OPENMP_HAVE_STD_CPP14_FLAG "-std=c++14" CMAKE_CXX_FLAGS) endif() diff --git a/openmp/cmake/config-ix.cmake b/openmp/cmake/config-ix.cmake index ebb2530ae541..d9ea3bbb0574 100644 --- a/openmp/cmake/config-ix.cmake +++ b/openmp/cmake/config-ix.cmake @@ -14,5 +14,5 @@ check_cxx_compiler_flag(-Wno-extra OPENMP_HAVE_WNO_EXTRA_FLAG) check_cxx_compiler_flag(-Wno-pedantic OPENMP_HAVE_WNO_PEDANTIC_FLAG) check_cxx_compiler_flag(-Wno-maybe-uninitialized OPENMP_HAVE_WNO_MAYBE_UNINITIALIZED_FLAG) -check_cxx_compiler_flag(-std=gnu++11 OPENMP_HAVE_STD_GNUPP11_FLAG) -check_cxx_compiler_flag(-std=c++11 OPENMP_HAVE_STD_CPP11_FLAG) +check_cxx_compiler_flag(-std=gnu++14 OPENMP_HAVE_STD_GNUPP14_FLAG) +check_cxx_compiler_flag(-std=c++14 OPENMP_HAVE_STD_CPP14_FLAG) diff --git a/openmp/libomptarget/cmake/Modules/LibomptargetNVPTXBitcodeLibrary.cmake b/openmp/libomptarget/cmake/Modules/LibomptargetNVPTXBitcodeLibrary.cmake index 538bf9277495..6ec0cc2b61bc 100644 --- a/openmp/libomptarget/cmake/Modules/LibomptargetNVPTXBitcodeLibrary.cmake +++ b/openmp/libomptarget/cmake/Modules/LibomptargetNVPTXBitcodeLibrary.cmake @@ -78,7 +78,7 @@ endfunction() # These flags are required to emit LLVM Bitcode. We check them together because # if any of them are not supported, there is no point in finding out which are. -set(compiler_flags_required -emit-llvm -O1 --cuda-device-only -std=c++11 --cuda-path=${CUDA_TOOLKIT_ROOT_DIR}) +set(compiler_flags_required -emit-llvm -O1 --cuda-device-only -std=c++14 --cuda-path=${CUDA_TOOLKIT_ROOT_DIR}) set(compiler_flags_required_src "extern \"C\" __device__ int thread() { return threadIdx.x; }") check_bitcode_compilation(LIBOMPTARGET_NVPTX_CUDA_COMPILER_SUPPORTS_FLAGS_REQUIRED "${compiler_flags_required_src}" ${compiler_flags_required}) diff --git a/openmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt b/openmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt index aac7ddc28adc..ec08bd912663 100644 --- a/openmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt +++ b/openmp/libomptarget/deviceRTLs/amdgcn/CMakeLists.txt @@ -98,7 +98,7 @@ endif() macro(add_cuda_bc_library) set(cu_cmd ${AOMP_BINDIR}/clang++ - -std=c++11 + -std=c++14 -fcuda-rdc -fvisibility=default --cuda-device-only diff --git a/openmp/runtime/test/lit.cfg b/openmp/runtime/test/lit.cfg index 22be385ab417..8ff668aaaa00 100644 --- a/openmp/runtime/test/lit.cfg +++ b/openmp/runtime/test/lit.cfg @@ -111,7 +111,7 @@ config.substitutions.append(("%libomp-compile-and-run", \ config.substitutions.append(("%libomp-cxx-compile-and-run", \ "%libomp-cxx-compile && %libomp-run")) config.substitutions.append(("%libomp-cxx-compile", \ - "%clangXX %openmp_flags %flags -std=c++11 %s -o %t" + libs)) + "%clangXX %openmp_flags %flags -std=c++14 %s -o %t" + libs)) config.substitutions.append(("%libomp-compile", \ "%clang %openmp_flags %flags %s -o %t" + libs)) config.substitutions.append(("%libomp-run", "%t")) diff --git a/openmp/tools/archer/tests/lit.cfg b/openmp/tools/archer/tests/lit.cfg index 3014c020bb99..7ec88d3ca4e4 100644 --- a/openmp/tools/archer/tests/lit.cfg +++ b/openmp/tools/archer/tests/lit.cfg @@ -97,7 +97,7 @@ config.substitutions.append(("%libarcher-compile-and-run", \ config.substitutions.append(("%libarcher-cxx-compile-and-run", \ "%libarcher-cxx-compile && %libarcher-run")) config.substitutions.append(("%libarcher-cxx-compile", \ - "%clang-archerXX %openmp_flags %archer_flags %flags -std=c++11 %s -o %t" + libs)) + "%clang-archerXX %openmp_flags %archer_flags %flags -std=c++14 %s -o %t" + libs)) config.substitutions.append(("%libarcher-compile", \ "%clang-archer %openmp_flags %archer_flags %flags %s -o %t" + libs)) config.substitutions.append(("%libarcher-run-race", "%suppression %deflake %t 2>&1 | tee %t.log")) -- GitLab From 1bd6123b781120c9190b9ba58b900cdcb718cdd1 Mon Sep 17 00:00:00 2001 From: Justin Lebar Date: Mon, 10 Feb 2020 20:33:08 -0800 Subject: [PATCH 090/142] Use std::foo_t rather than std::foo in LLVM. Summary: C++14 migration. No functional change. Reviewers: bkramer, JDevlieghere, lebedev.ri Subscribers: MatzeB, hiraditya, jkorous, dexonsmith, arphaman, kadircet, lebedev.ri, usaxena95, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74384 --- clang-tools-extra/clang-tidy/ClangTidyCheck.h | 6 +- clang-tools-extra/clangd/Shutdown.h | 2 +- llvm/include/llvm/ADT/APFloat.h | 4 +- llvm/include/llvm/ADT/AllocatorList.h | 4 +- llvm/include/llvm/ADT/Any.h | 63 +++++------ llvm/include/llvm/ADT/ArrayRef.h | 32 +++--- llvm/include/llvm/ADT/BitmaskEnum.h | 33 +++--- llvm/include/llvm/ADT/DenseMap.h | 2 +- llvm/include/llvm/ADT/Hashing.h | 12 +-- llvm/include/llvm/ADT/PriorityWorklist.h | 2 +- llvm/include/llvm/ADT/STLExtras.h | 45 ++++---- llvm/include/llvm/ADT/SmallVector.h | 20 ++-- llvm/include/llvm/ADT/StringRef.h | 11 +- llvm/include/llvm/ADT/TinyPtrVector.h | 8 +- llvm/include/llvm/ADT/ilist_iterator.h | 7 +- llvm/include/llvm/ADT/iterator.h | 20 ++-- llvm/include/llvm/Analysis/RegionInfo.h | 5 +- llvm/include/llvm/Analysis/RegionInfoImpl.h | 4 +- llvm/include/llvm/BinaryFormat/Dwarf.h | 3 +- llvm/include/llvm/CodeGen/LiveInterval.h | 11 +- .../llvm/CodeGen/MachineInstrBundleIterator.h | 4 +- .../DebugInfo/CodeView/CodeViewRecordIO.h | 2 +- llvm/include/llvm/ExecutionEngine/JITSymbol.h | 7 +- llvm/include/llvm/ExecutionEngine/Orc/Core.h | 8 +- .../include/llvm/ExecutionEngine/Orc/Legacy.h | 12 +-- .../Orc/OrcRemoteTargetRPCAPI.h | 3 +- .../Orc/OrcRemoteTargetServer.h | 2 +- .../Orc/RPC/RPCSerialization.h | 17 ++- .../llvm/ExecutionEngine/Orc/RPC/RPCUtils.h | 43 ++++---- .../ExecutionEngine/Orc/RPC/RawByteChannel.h | 32 +++--- llvm/include/llvm/FuzzMutate/Random.h | 6 +- llvm/include/llvm/IR/Constants.h | 3 +- llvm/include/llvm/IR/DerivedTypes.h | 8 +- llvm/include/llvm/IR/DiagnosticInfo.h | 35 +++--- llvm/include/llvm/IR/Metadata.h | 32 +++--- llvm/include/llvm/IR/ValueMap.h | 2 +- llvm/include/llvm/Object/ELFTypes.h | 8 +- llvm/include/llvm/Support/AllocatorBase.h | 3 +- .../include/llvm/Support/BinaryStreamReader.h | 2 +- .../include/llvm/Support/BinaryStreamWriter.h | 2 +- llvm/include/llvm/Support/Casting.h | 44 ++++---- llvm/include/llvm/Support/CheckedArithmetic.h | 18 ++-- llvm/include/llvm/Support/Chrono.h | 4 +- llvm/include/llvm/Support/CommandLine.h | 17 ++- llvm/include/llvm/Support/Endian.h | 2 +- llvm/include/llvm/Support/Error.h | 27 +++-- llvm/include/llvm/Support/ErrorOr.h | 46 ++++---- llvm/include/llvm/Support/FormatProviders.h | 14 +-- .../llvm/Support/FormatVariadicDetails.h | 34 +++--- llvm/include/llvm/Support/GenericDomTree.h | 2 +- .../GenericIteratedDominanceFrontier.h | 2 +- llvm/include/llvm/Support/JSON.h | 16 ++- .../llvm/Support/MSVCErrorWorkarounds.h | 9 +- llvm/include/llvm/Support/MathExtras.h | 31 +++--- llvm/include/llvm/Support/SwapByteOrder.h | 5 +- llvm/include/llvm/Support/TaskQueue.h | 6 +- llvm/include/llvm/Support/TrailingObjects.h | 8 +- llvm/include/llvm/Support/YAMLTraits.h | 102 ++++++++---------- llvm/include/llvm/Support/raw_ostream.h | 6 +- llvm/include/llvm/Support/type_traits.h | 13 ++- llvm/include/llvm/XRay/Graph.h | 24 ++--- llvm/lib/Demangle/ItaniumDemangle.cpp | 6 +- .../Support/ItaniumManglingCanonicalizer.cpp | 5 +- llvm/lib/Support/NativeFormatting.cpp | 2 +- .../AArch64/AsmParser/AArch64AsmParser.cpp | 14 ++- .../MCTargetDesc/AArch64AddressingModes.h | 7 +- .../MCTargetDesc/AArch64InstPrinter.cpp | 6 +- llvm/lib/XRay/FDRTraceWriter.cpp | 14 ++- llvm/tools/dsymutil/CFBundle.cpp | 5 +- llvm/tools/llvm-pdbutil/FormatUtil.h | 3 +- llvm/tools/llvm-xray/trie-node.h | 2 +- llvm/unittests/ADT/DenseSetTest.cpp | 2 +- llvm/unittests/IR/PatternMatch.cpp | 4 +- llvm/unittests/XRay/GraphTest.cpp | 2 +- .../benchmark/include/benchmark/benchmark.h | 3 +- llvm/utils/benchmark/src/sysinfo.cc | 5 +- .../googlemock/include/gmock/gmock-matchers.h | 20 ++-- 77 files changed, 483 insertions(+), 572 deletions(-) diff --git a/clang-tools-extra/clang-tidy/ClangTidyCheck.h b/clang-tools-extra/clang-tidy/ClangTidyCheck.h index 1ad881f673a9..440293f5beaa 100644 --- a/clang-tools-extra/clang-tidy/ClangTidyCheck.h +++ b/clang-tools-extra/clang-tidy/ClangTidyCheck.h @@ -133,8 +133,8 @@ public: /// ``CheckOptions``. If the corresponding key is not present, returns /// \p Default. template - typename std::enable_if::value, T>::type - get(StringRef LocalName, T Default) const { + std::enable_if_t::value, T> get(StringRef LocalName, + T Default) const { std::string Value = get(LocalName, ""); T Result = Default; if (!Value.empty()) @@ -150,7 +150,7 @@ public: /// present, falls back to get global option. If global option is not /// present either, returns Default. template - typename std::enable_if::value, T>::type + std::enable_if_t::value, T> getLocalOrGlobal(StringRef LocalName, T Default) const { std::string Value = getLocalOrGlobal(LocalName, ""); T Result = Default; diff --git a/clang-tools-extra/clangd/Shutdown.h b/clang-tools-extra/clangd/Shutdown.h index 3097f6a3e63c..94ada3171f31 100644 --- a/clang-tools-extra/clangd/Shutdown.h +++ b/clang-tools-extra/clangd/Shutdown.h @@ -66,7 +66,7 @@ bool shutdownRequested(); /// requested (which interrupts IO), we'll fail rather than retry. template ()())> Ret retryAfterSignalUnlessShutdown( - const typename std::enable_if::type &Fail, // Suppress deduction. + const std::enable_if_t &Fail, // Suppress deduction. const Fun &F) { Ret Res; do { diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h index ed25b2cd89f1..0b744267a9ad 100644 --- a/llvm/include/llvm/ADT/APFloat.h +++ b/llvm/include/llvm/ADT/APFloat.h @@ -853,8 +853,8 @@ public: APFloat(const fltSemantics &Semantics) : U(Semantics) {} APFloat(const fltSemantics &Semantics, StringRef S); APFloat(const fltSemantics &Semantics, integerPart I) : U(Semantics, I) {} - template ::value>::type> + template ::value>> APFloat(const fltSemantics &Semantics, T V) = delete; // TODO: Remove this constructor. This isn't faster than the first one. APFloat(const fltSemantics &Semantics, uninitializedTag) diff --git a/llvm/include/llvm/ADT/AllocatorList.h b/llvm/include/llvm/ADT/AllocatorList.h index 405a2e4264df..447d7a7538db 100644 --- a/llvm/include/llvm/ADT/AllocatorList.h +++ b/llvm/include/llvm/ADT/AllocatorList.h @@ -110,8 +110,8 @@ private: template IteratorImpl(const IteratorImpl &X, - typename std::enable_if::value>::type * = nullptr) + std::enable_if_t::value> * = nullptr) : base_type(X.wrapped()) {} ~IteratorImpl() = default; diff --git a/llvm/include/llvm/ADT/Any.h b/llvm/include/llvm/ADT/Any.h index 49657e02a991..9d819841e3fc 100644 --- a/llvm/include/llvm/ADT/Any.h +++ b/llvm/include/llvm/ADT/Any.h @@ -59,26 +59,26 @@ public: // When T is Any or T is not copy-constructible we need to explicitly disable // the forwarding constructor so that the copy constructor gets selected // instead. - template < - typename T, - typename std::enable_if< - llvm::conjunction< - llvm::negation::type, Any>>, - // We also disable this overload when an `Any` object can be - // converted to the parameter type because in that case, this - // constructor may combine with that conversion during overload - // resolution for determining copy constructibility, and then - // when we try to determine copy constructibility below we may - // infinitely recurse. This is being evaluated by the standards - // committee as a potential DR in `std::any` as well, but we're - // going ahead and adopting it to work-around usage of `Any` with - // types that need to be implicitly convertible from an `Any`. - llvm::negation::type>>, - std::is_copy_constructible::type>>::value, - int>::type = 0> + template , Any>>, + // We also disable this overload when an `Any` object can be + // converted to the parameter type because in that case, + // this constructor may combine with that conversion during + // overload resolution for determining copy + // constructibility, and then when we try to determine copy + // constructibility below we may infinitely recurse. This is + // being evaluated by the standards committee as a potential + // DR in `std::any` as well, but we're going ahead and + // adopting it to work-around usage of `Any` with types that + // need to be implicitly convertible from an `Any`. + llvm::negation>>, + std::is_copy_constructible>>::value, + int> = 0> Any(T &&Value) { - using U = typename std::decay::type; - Storage = std::make_unique>(std::forward(Value)); + Storage = + std::make_unique>>(std::forward(Value)); } Any(Any &&Other) : Storage(std::move(Other.Storage)) {} @@ -114,32 +114,27 @@ template const char Any::TypeId::Id = 0; template bool any_isa(const Any &Value) { if (!Value.Storage) return false; - using U = - typename std::remove_cv::type>::type; - return Value.Storage->id() == &Any::TypeId::Id; + return Value.Storage->id() == + &Any::TypeId>>::Id; } template T any_cast(const Any &Value) { - using U = - typename std::remove_cv::type>::type; - return static_cast(*any_cast(&Value)); + return static_cast( + *any_cast>>(&Value)); } template T any_cast(Any &Value) { - using U = - typename std::remove_cv::type>::type; - return static_cast(*any_cast(&Value)); + return static_cast( + *any_cast>>(&Value)); } template T any_cast(Any &&Value) { - using U = - typename std::remove_cv::type>::type; - return static_cast(std::move(*any_cast(&Value))); + return static_cast(std::move( + *any_cast>>(&Value))); } template const T *any_cast(const Any *Value) { - using U = - typename std::remove_cv::type>::type; + using U = std::remove_cv_t>; assert(Value && any_isa(*Value) && "Bad any cast!"); if (!Value || !any_isa(*Value)) return nullptr; @@ -147,7 +142,7 @@ template const T *any_cast(const Any *Value) { } template T *any_cast(Any *Value) { - using U = typename std::decay::type; + using U = std::decay_t; assert(Value && any_isa(*Value) && "Bad any cast!"); if (!Value || !any_isa(*Value)) return nullptr; diff --git a/llvm/include/llvm/ADT/ArrayRef.h b/llvm/include/llvm/ADT/ArrayRef.h index 898a7c707a8d..5cba73e67f04 100644 --- a/llvm/include/llvm/ADT/ArrayRef.h +++ b/llvm/include/llvm/ADT/ArrayRef.h @@ -114,30 +114,28 @@ namespace llvm { /// Construct an ArrayRef from ArrayRef. This uses SFINAE to /// ensure that only ArrayRefs of pointers can be converted. template - ArrayRef( - const ArrayRef &A, - typename std::enable_if< - std::is_convertible::value>::type * = nullptr) - : Data(A.data()), Length(A.size()) {} + ArrayRef(const ArrayRef &A, + std::enable_if_t::value> + * = nullptr) + : Data(A.data()), Length(A.size()) {} /// Construct an ArrayRef from a SmallVector. This is /// templated in order to avoid instantiating SmallVectorTemplateCommon /// whenever we copy-construct an ArrayRef. - template + template /*implicit*/ ArrayRef( - const SmallVectorTemplateCommon &Vec, - typename std::enable_if< - std::is_convertible::value>::type * = nullptr) - : Data(Vec.data()), Length(Vec.size()) { - } + const SmallVectorTemplateCommon &Vec, + std::enable_if_t::value> * = + nullptr) + : Data(Vec.data()), Length(Vec.size()) {} /// Construct an ArrayRef from std::vector. This uses SFINAE /// to ensure that only vectors of pointers can be converted. - template + template ArrayRef(const std::vector &Vec, - typename std::enable_if< - std::is_convertible::value>::type* = 0) - : Data(Vec.data()), Length(Vec.size()) {} + std::enable_if_t::value> + * = 0) + : Data(Vec.data()), Length(Vec.size()) {} /// @} /// @name Simple Operations @@ -256,7 +254,7 @@ namespace llvm { /// The declaration here is extra complicated so that "arrayRef = {}" /// continues to select the move assignment operator. template - typename std::enable_if::value, ArrayRef>::type & + std::enable_if_t::value, ArrayRef> & operator=(U &&Temporary) = delete; /// Disallow accidental assignment from a temporary. @@ -264,7 +262,7 @@ namespace llvm { /// The declaration here is extra complicated so that "arrayRef = {}" /// continues to select the move assignment operator. template - typename std::enable_if::value, ArrayRef>::type & + std::enable_if_t::value, ArrayRef> & operator=(std::initializer_list) = delete; /// @} diff --git a/llvm/include/llvm/ADT/BitmaskEnum.h b/llvm/include/llvm/ADT/BitmaskEnum.h index 1a18bc721b21..d5854d0de200 100644 --- a/llvm/include/llvm/ADT/BitmaskEnum.h +++ b/llvm/include/llvm/ADT/BitmaskEnum.h @@ -71,49 +71,45 @@ struct is_bitmask_enum : std::false_type {}; template struct is_bitmask_enum< - E, typename std::enable_if= - 0>::type> : std::true_type {}; + E, std::enable_if_t= 0>> + : std::true_type {}; namespace BitmaskEnumDetail { /// Get a bitmask with 1s in all places up to the high-order bit of E's largest /// value. -template typename std::underlying_type::type Mask() { +template std::underlying_type_t Mask() { // On overflow, NextPowerOf2 returns zero with the type uint64_t, so // subtracting 1 gives us the mask with all bits set, like we want. - return NextPowerOf2(static_cast::type>( + return NextPowerOf2(static_cast>( E::LLVM_BITMASK_LARGEST_ENUMERATOR)) - 1; } /// Check that Val is in range for E, and return Val cast to E's underlying /// type. -template typename std::underlying_type::type Underlying(E Val) { - auto U = static_cast::type>(Val); +template std::underlying_type_t Underlying(E Val) { + auto U = static_cast>(Val); assert(U >= 0 && "Negative enum values are not allowed."); assert(U <= Mask() && "Enum value too large (or largest val too small?)"); return U; } -template ::value>::type> +template ::value>> E operator~(E Val) { return static_cast(~Underlying(Val) & Mask()); } -template ::value>::type> +template ::value>> E operator|(E LHS, E RHS) { return static_cast(Underlying(LHS) | Underlying(RHS)); } -template ::value>::type> +template ::value>> E operator&(E LHS, E RHS) { return static_cast(Underlying(LHS) & Underlying(RHS)); } -template ::value>::type> +template ::value>> E operator^(E LHS, E RHS) { return static_cast(Underlying(LHS) ^ Underlying(RHS)); } @@ -121,22 +117,19 @@ E operator^(E LHS, E RHS) { // |=, &=, and ^= return a reference to LHS, to match the behavior of the // operators on builtin types. -template ::value>::type> +template ::value>> E &operator|=(E &LHS, E RHS) { LHS = LHS | RHS; return LHS; } -template ::value>::type> +template ::value>> E &operator&=(E &LHS, E RHS) { LHS = LHS & RHS; return LHS; } -template ::value>::type> +template ::value>> E &operator^=(E &LHS, E RHS) { LHS = LHS ^ RHS; return LHS; diff --git a/llvm/include/llvm/ADT/DenseMap.h b/llvm/include/llvm/ADT/DenseMap.h index 148d319c8603..b73afae4bce6 100644 --- a/llvm/include/llvm/ADT/DenseMap.h +++ b/llvm/include/llvm/ADT/DenseMap.h @@ -1194,7 +1194,7 @@ public: // for const iterator destinations so it doesn't end up as a user defined copy // constructor. template ::type> + typename = std::enable_if_t> DenseMapIterator( const DenseMapIterator &I) : DebugEpochBase::HandleBase(I), Ptr(I.Ptr), End(I.End) {} diff --git a/llvm/include/llvm/ADT/Hashing.h b/llvm/include/llvm/ADT/Hashing.h index adcc5cf54da9..dac0e0556ff3 100644 --- a/llvm/include/llvm/ADT/Hashing.h +++ b/llvm/include/llvm/ADT/Hashing.h @@ -101,8 +101,7 @@ public: /// differing argument types even if they would implicit promote to a common /// type without changing the value. template -typename std::enable_if::value, hash_code>::type -hash_value(T value); +std::enable_if_t::value, hash_code> hash_value(T value); /// Compute a hash_code for a pointer's address. /// @@ -360,7 +359,7 @@ template struct is_hashable_data > /// Helper to get the hashable data representation for a type. /// This variant is enabled when the type itself can be used. template -typename std::enable_if::value, T>::type +std::enable_if_t::value, T> get_hashable_data(const T &value) { return value; } @@ -368,7 +367,7 @@ get_hashable_data(const T &value) { /// This variant is enabled when we must first call hash_value and use the /// result as our data. template -typename std::enable_if::value, size_t>::type +std::enable_if_t::value, size_t> get_hashable_data(const T &value) { using ::llvm::hash_value; return hash_value(value); @@ -442,7 +441,7 @@ hash_code hash_combine_range_impl(InputIteratorT first, InputIteratorT last) { /// are stored in contiguous memory, this routine avoids copying each value /// and directly reads from the underlying memory. template -typename std::enable_if::value, hash_code>::type +std::enable_if_t::value, hash_code> hash_combine_range_impl(ValueT *first, ValueT *last) { const uint64_t seed = get_execution_seed(); const char *s_begin = reinterpret_cast(first); @@ -627,8 +626,7 @@ inline hash_code hash_integer_value(uint64_t value) { // Declared and documented above, but defined here so that any of the hashing // infrastructure is available. template -typename std::enable_if::value, hash_code>::type -hash_value(T value) { +std::enable_if_t::value, hash_code> hash_value(T value) { return ::llvm::hashing::detail::hash_integer_value( static_cast(value)); } diff --git a/llvm/include/llvm/ADT/PriorityWorklist.h b/llvm/include/llvm/ADT/PriorityWorklist.h index 96d22c87557e..01dd59a2e71a 100644 --- a/llvm/include/llvm/ADT/PriorityWorklist.h +++ b/llvm/include/llvm/ADT/PriorityWorklist.h @@ -110,7 +110,7 @@ public: /// Insert a sequence of new elements into the PriorityWorklist. template - typename std::enable_if::value>::type + std::enable_if_t::value> insert(SequenceT &&Input) { if (std::begin(Input) == std::end(Input)) // Nothing to do for an empty input sequence. diff --git a/llvm/include/llvm/ADT/STLExtras.h b/llvm/include/llvm/ADT/STLExtras.h index 172ef2bef2ae..8888e8d48978 100644 --- a/llvm/include/llvm/ADT/STLExtras.h +++ b/llvm/include/llvm/ADT/STLExtras.h @@ -115,9 +115,8 @@ public: template function_ref(Callable &&callable, - typename std::enable_if< - !std::is_same::type, - function_ref>::value>::type * = nullptr) + std::enable_if_t, + function_ref>::value> * = nullptr) : callback(callback_fn::type>), callable(reinterpret_cast(&callable)) {} @@ -254,9 +253,8 @@ struct has_rbegin : has_rbegin_impl::type> { // Returns an iterator_range over the given container which iterates in reverse. // Note that the container must have rbegin()/rend() methods for this to work. template -auto reverse( - ContainerTy &&C, - typename std::enable_if::value>::type * = nullptr) { +auto reverse(ContainerTy &&C, + std::enable_if_t::value> * = nullptr) { return make_range(C.rbegin(), C.rend()); } @@ -271,8 +269,7 @@ std::reverse_iterator make_reverse_iterator(IteratorTy It) { // bidirectional iterators for this to work. template auto reverse(ContainerTy &&C, - typename std::enable_if::value>::type * = - nullptr) { + std::enable_if_t::value> * = nullptr) { return make_range(llvm::make_reverse_iterator(std::end(C)), llvm::make_reverse_iterator(std::begin(C))); } @@ -1148,11 +1145,11 @@ void DeleteContainerSeconds(Container &C) { /// Get the size of a range. This is a wrapper function around std::distance /// which is only enabled when the operation is O(1). template -auto size(R &&Range, typename std::enable_if< - std::is_same::iterator_category, - std::random_access_iterator_tag>::value, - void>::type * = nullptr) { +auto size(R &&Range, + std::enable_if_t::iterator_category, + std::random_access_iterator_tag>::value, + void> * = nullptr) { return std::distance(Range.begin(), Range.end()); } @@ -1516,12 +1513,11 @@ decltype(auto) apply_tuple(F &&f, Tuple &&t) { template bool hasNItems( IterTy &&Begin, IterTy &&End, unsigned N, - typename std::enable_if< - !std::is_same< - typename std::iterator_traits::type>::iterator_category, - std::random_access_iterator_tag>::value, - void>::type * = nullptr) { + std::enable_if_t< + !std::is_same>::iterator_category, + std::random_access_iterator_tag>::value, + void> * = nullptr) { for (; N; --N, ++Begin) if (Begin == End) return false; // Too few. @@ -1533,12 +1529,11 @@ bool hasNItems( template bool hasNItemsOrMore( IterTy &&Begin, IterTy &&End, unsigned N, - typename std::enable_if< - !std::is_same< - typename std::iterator_traits::type>::iterator_category, - std::random_access_iterator_tag>::value, - void>::type * = nullptr) { + std::enable_if_t< + !std::is_same>::iterator_category, + std::random_access_iterator_tag>::value, + void> * = nullptr) { for (; N; --N, ++Begin) if (Begin == End) return false; // Too few. diff --git a/llvm/include/llvm/ADT/SmallVector.h b/llvm/include/llvm/ADT/SmallVector.h index 8c46aa906905..28b514d530dc 100644 --- a/llvm/include/llvm/ADT/SmallVector.h +++ b/llvm/include/llvm/ADT/SmallVector.h @@ -284,8 +284,8 @@ protected: template static void uninitialized_copy( T1 *I, T1 *E, T2 *Dest, - typename std::enable_if::type, - T2>::value>::type * = nullptr) { + std::enable_if_t::type, + T2>::value> * = nullptr) { // Use memcpy for PODs iterated by pointers (which includes SmallVector // iterators): std::uninitialized_copy optimizes to memmove, but we can // use memcpy here. Note that I and E are iterators and thus might be @@ -381,9 +381,9 @@ public: /// Add the specified range to the end of the SmallVector. template ::iterator_category, - std::input_iterator_tag>::value>::type> + std::input_iterator_tag>::value>> void append(in_iter in_start, in_iter in_end) { size_type NumInputs = std::distance(in_start, in_end); if (NumInputs > this->capacity() - this->size()) @@ -418,9 +418,9 @@ public: } template ::iterator_category, - std::input_iterator_tag>::value>::type> + std::input_iterator_tag>::value>> void assign(in_iter in_start, in_iter in_end) { clear(); append(in_start, in_end); @@ -575,9 +575,9 @@ public: } template ::iterator_category, - std::input_iterator_tag>::value>::type> + std::input_iterator_tag>::value>> iterator insert(iterator I, ItTy From, ItTy To) { // Convert iterator to elt# to avoid invalidating iterator when we reserve() size_t InsertElt = I - this->begin(); @@ -849,9 +849,9 @@ public: } template ::iterator_category, - std::input_iterator_tag>::value>::type> + std::input_iterator_tag>::value>> SmallVector(ItTy S, ItTy E) : SmallVectorImpl(N) { this->append(S, E); } diff --git a/llvm/include/llvm/ADT/StringRef.h b/llvm/include/llvm/ADT/StringRef.h index 0c36e33cca91..ad31517a1ea7 100644 --- a/llvm/include/llvm/ADT/StringRef.h +++ b/llvm/include/llvm/ADT/StringRef.h @@ -265,8 +265,7 @@ namespace llvm { /// The declaration here is extra complicated so that `stringRef = {}` /// and `stringRef = "abc"` continue to select the move assignment operator. template - typename std::enable_if::value, - StringRef>::type & + std::enable_if_t::value, StringRef> & operator=(T &&Str) = delete; /// @} @@ -508,7 +507,7 @@ namespace llvm { /// this returns true to signify the error. The string is considered /// erroneous if empty or if it overflows T. template - typename std::enable_if::is_signed, bool>::type + std::enable_if_t::is_signed, bool> getAsInteger(unsigned Radix, T &Result) const { long long LLVal; if (getAsSignedInteger(*this, Radix, LLVal) || @@ -519,7 +518,7 @@ namespace llvm { } template - typename std::enable_if::is_signed, bool>::type + std::enable_if_t::is_signed, bool> getAsInteger(unsigned Radix, T &Result) const { unsigned long long ULLVal; // The additional cast to unsigned long long is required to avoid the @@ -542,7 +541,7 @@ namespace llvm { /// The portion of the string representing the discovered numeric value /// is removed from the beginning of the string. template - typename std::enable_if::is_signed, bool>::type + std::enable_if_t::is_signed, bool> consumeInteger(unsigned Radix, T &Result) { long long LLVal; if (consumeSignedInteger(*this, Radix, LLVal) || @@ -553,7 +552,7 @@ namespace llvm { } template - typename std::enable_if::is_signed, bool>::type + std::enable_if_t::is_signed, bool> consumeInteger(unsigned Radix, T &Result) { unsigned long long ULLVal; if (consumeUnsignedInteger(*this, Radix, ULLVal) || diff --git a/llvm/include/llvm/ADT/TinyPtrVector.h b/llvm/include/llvm/ADT/TinyPtrVector.h index 6b76d35d4e92..ed20a762f307 100644 --- a/llvm/include/llvm/ADT/TinyPtrVector.h +++ b/llvm/include/llvm/ADT/TinyPtrVector.h @@ -152,10 +152,10 @@ public: } // Implicit conversion to ArrayRef if EltTy* implicitly converts to U*. - template, ArrayRef>::value, - bool>::type = false> + template < + typename U, + std::enable_if_t, ArrayRef>::value, + bool> = false> operator ArrayRef() const { return operator ArrayRef(); } diff --git a/llvm/include/llvm/ADT/ilist_iterator.h b/llvm/include/llvm/ADT/ilist_iterator.h index cbe5cefa96d1..be876347907b 100644 --- a/llvm/include/llvm/ADT/ilist_iterator.h +++ b/llvm/include/llvm/ADT/ilist_iterator.h @@ -88,15 +88,14 @@ public: // This is templated so that we can allow constructing a const iterator from // a nonconst iterator... template - ilist_iterator( - const ilist_iterator &RHS, - typename std::enable_if::type = nullptr) + ilist_iterator(const ilist_iterator &RHS, + std::enable_if_t = nullptr) : NodePtr(RHS.NodePtr) {} // This is templated so that we can allow assigning to a const iterator from // a nonconst iterator... template - typename std::enable_if::type + std::enable_if_t operator=(const ilist_iterator &RHS) { NodePtr = RHS.NodePtr; return *this; diff --git a/llvm/include/llvm/ADT/iterator.h b/llvm/include/llvm/ADT/iterator.h index 8fd5c11a2dcb..9a1f6e1511e7 100644 --- a/llvm/include/llvm/ADT/iterator.h +++ b/llvm/include/llvm/ADT/iterator.h @@ -194,14 +194,14 @@ template < typename T = typename std::iterator_traits::value_type, typename DifferenceTypeT = typename std::iterator_traits::difference_type, - typename PointerT = typename std::conditional< + typename PointerT = std::conditional_t< std::is_same::value_type>::value, - typename std::iterator_traits::pointer, T *>::type, - typename ReferenceT = typename std::conditional< + typename std::iterator_traits::pointer, T *>, + typename ReferenceT = std::conditional_t< std::is_same::value_type>::value, - typename std::iterator_traits::reference, T &>::type> + typename std::iterator_traits::reference, T &>> class iterator_adaptor_base : public iterator_facade_base { @@ -281,8 +281,8 @@ public: /// using iterator = pointee_iterator::iterator>; /// \endcode template ())>::type> + typename T = std::remove_reference_t())>> struct pointee_iterator : iterator_adaptor_base< pointee_iterator, WrappedIteratorT, @@ -334,9 +334,11 @@ make_pointer_range(RangeT &&Range) { } template ())>::type, - typename T2 = typename std::add_pointer::type> -using raw_pointer_iterator = pointer_iterator, T2>; + typename T1 = std::remove_reference_t())>, + typename T2 = std::add_pointer_t> +using raw_pointer_iterator = + pointer_iterator, T2>; // Wrapper iterator over iterator ItType, adding DataRef to the type of ItType, // to create NodeRef = std::pair. diff --git a/llvm/include/llvm/Analysis/RegionInfo.h b/llvm/include/llvm/Analysis/RegionInfo.h index 8bcc3e851200..b0336c559774 100644 --- a/llvm/include/llvm/Analysis/RegionInfo.h +++ b/llvm/include/llvm/Analysis/RegionInfo.h @@ -574,10 +574,9 @@ public: template class block_iterator_wrapper : public df_iterator< - typename std::conditional::type *> { + std::conditional_t *> { using super = - df_iterator< - typename std::conditional::type *>; + df_iterator *>; public: using Self = block_iterator_wrapper; diff --git a/llvm/include/llvm/Analysis/RegionInfoImpl.h b/llvm/include/llvm/Analysis/RegionInfoImpl.h index 539f15d13f2f..8d9ec646f519 100644 --- a/llvm/include/llvm/Analysis/RegionInfoImpl.h +++ b/llvm/include/llvm/Analysis/RegionInfoImpl.h @@ -724,7 +724,7 @@ void RegionInfoBase::findRegionsWithEntry(BlockT *entry, template void RegionInfoBase::scanForRegions(FuncT &F, BBtoBBMap *ShortCut) { - using FuncPtrT = typename std::add_pointer::type; + using FuncPtrT = std::add_pointer_t; BlockT *entry = GraphTraits::getEntryNode(&F); DomTreeNodeT *N = DT->getNode(entry); @@ -912,7 +912,7 @@ RegionInfoBase::getCommonRegion(SmallVectorImpl &BBs) const { template void RegionInfoBase::calculate(FuncT &F) { - using FuncPtrT = typename std::add_pointer::type; + using FuncPtrT = std::add_pointer_t; // ShortCut a function where for every BB the exit of the largest region // starting with BB is stored. These regions can be threated as single BBS. diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.h b/llvm/include/llvm/BinaryFormat/Dwarf.h index 6195079c7ff5..27747300f229 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.h +++ b/llvm/include/llvm/BinaryFormat/Dwarf.h @@ -672,8 +672,7 @@ template <> struct EnumTraits : public std::true_type { /// dumping functions above, these format unknown enumerator values as /// DW_TYPE_unknown_1234 (e.g. DW_TAG_unknown_ffff). template -struct format_provider< - Enum, typename std::enable_if::value>::type> { +struct format_provider::value>> { static void format(const Enum &E, raw_ostream &OS, StringRef Style) { StringRef Str = dwarf::EnumTraits::StringFn(E); if (Str.empty()) { diff --git a/llvm/include/llvm/CodeGen/LiveInterval.h b/llvm/include/llvm/CodeGen/LiveInterval.h index fe5adb59dac2..dfb104a7df7b 100644 --- a/llvm/include/llvm/CodeGen/LiveInterval.h +++ b/llvm/include/llvm/CodeGen/LiveInterval.h @@ -625,11 +625,12 @@ namespace llvm { // if the Seg is lower find first segment that is above Idx using binary // search if (Seg->end <= *Idx) { - Seg = std::upper_bound(++Seg, EndSeg, *Idx, - [=](typename std::remove_reference::type V, - const typename std::remove_reference::type &S) { - return V < S.end; - }); + Seg = std::upper_bound( + ++Seg, EndSeg, *Idx, + [=](std::remove_reference_t V, + const std::remove_reference_t &S) { + return V < S.end; + }); if (Seg == EndSeg) break; } diff --git a/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h b/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h index 0f59563e7e1b..250cb0d78a68 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h @@ -152,8 +152,8 @@ public: template MachineInstrBundleIterator( const MachineInstrBundleIterator &I, - typename std::enable_if::value, - void *>::type = nullptr) + std::enable_if_t::value, void *> = + nullptr) : MII(I.getInstrIterator()) {} MachineInstrBundleIterator() : MII(nullptr) {} diff --git a/llvm/include/llvm/DebugInfo/CodeView/CodeViewRecordIO.h b/llvm/include/llvm/DebugInfo/CodeView/CodeViewRecordIO.h index 60829a51dc25..c5caddab15bf 100644 --- a/llvm/include/llvm/DebugInfo/CodeView/CodeViewRecordIO.h +++ b/llvm/include/llvm/DebugInfo/CodeView/CodeViewRecordIO.h @@ -114,7 +114,7 @@ public: if (!isStreaming() && sizeof(Value) > maxFieldLength()) return make_error(cv_error_code::insufficient_buffer); - using U = typename std::underlying_type::type; + using U = std::underlying_type_t; U X; if (isWriting() || isStreaming()) diff --git a/llvm/include/llvm/ExecutionEngine/JITSymbol.h b/llvm/include/llvm/ExecutionEngine/JITSymbol.h index 7a2a6cfa5203..67e531afb9b9 100644 --- a/llvm/include/llvm/ExecutionEngine/JITSymbol.h +++ b/llvm/include/llvm/ExecutionEngine/JITSymbol.h @@ -58,10 +58,9 @@ template T jitTargetAddressToPointer(JITTargetAddress Addr) { /// Casts the given address to a callable function pointer. This operation /// will perform pointer signing for platforms that require it (e.g. arm64e). template T jitTargetAddressToFunction(JITTargetAddress Addr) { - static_assert( - std::is_pointer::value && - std::is_function::type>::value, - "T must be a function pointer type"); + static_assert(std::is_pointer::value && + std::is_function>::value, + "T must be a function pointer type"); return jitTargetAddressToPointer(Addr); } diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h index 9113ccf459b0..1a55801b9d87 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h @@ -202,10 +202,10 @@ public: /// If Body returns true then the element just passed in is removed from the /// set. If Body returns false then the element is retained. template - auto forEachWithRemoval(BodyFn &&Body) -> typename std::enable_if< + auto forEachWithRemoval(BodyFn &&Body) -> std::enable_if_t< std::is_same(), std::declval())), - bool>::value>::type { + bool>::value> { UnderlyingVector::size_type I = 0; while (I != Symbols.size()) { const auto &Name = Symbols[I].first; @@ -224,11 +224,11 @@ public: /// returns true then the element just passed in is removed from the set. If /// Body returns false then the element is retained. template - auto forEachWithRemoval(BodyFn &&Body) -> typename std::enable_if< + auto forEachWithRemoval(BodyFn &&Body) -> std::enable_if_t< std::is_same(), std::declval())), Expected>::value, - Error>::type { + Error> { UnderlyingVector::size_type I = 0; while (I != Symbols.size()) { const auto &Name = Symbols[I].first; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Legacy.h b/llvm/include/llvm/ExecutionEngine/Orc/Legacy.h index 148e260c9569..b20202a49ef6 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/Legacy.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/Legacy.h @@ -73,17 +73,13 @@ private: /// function objects. template std::unique_ptr::type>::type, - typename std::remove_cv< - typename std::remove_reference::type>::type>> + std::remove_cv_t>, + std::remove_cv_t>>> createSymbolResolver(GetResponsibilitySetFn &&GetResponsibilitySet, LookupFn &&Lookup) { using LambdaSymbolResolverImpl = LambdaSymbolResolver< - typename std::remove_cv< - typename std::remove_reference::type>::type, - typename std::remove_cv< - typename std::remove_reference::type>::type>; + std::remove_cv_t>, + std::remove_cv_t>>; return std::make_unique( std::forward(GetResponsibilitySet), std::forward(Lookup)); diff --git a/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetRPCAPI.h b/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetRPCAPI.h index 3ff5a5f6e90e..52a328165240 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetRPCAPI.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetRPCAPI.h @@ -108,8 +108,7 @@ public: template class SerializationTraits< ChannelT, remote::DirectBufferWriter, remote::DirectBufferWriter, - typename std::enable_if< - std::is_base_of::value>::type> { + std::enable_if_t::value>> { public: static Error serialize(ChannelT &C, const remote::DirectBufferWriter &DBW) { if (auto EC = serializeSeq(C, DBW.getDst())) diff --git a/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetServer.h b/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetServer.h index 4c8e2ea1a7be..ac1df847cf7e 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetServer.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetServer.h @@ -60,7 +60,7 @@ public: SymbolLookup(std::move(SymbolLookup)), EHFramesRegister(std::move(EHFramesRegister)), EHFramesDeregister(std::move(EHFramesDeregister)) { - using ThisT = typename std::remove_reference::type; + using ThisT = std::remove_reference_t; addHandler(*this, &ThisT::handleCallIntVoid); addHandler(*this, &ThisT::handleCallMain); addHandler(*this, &ThisT::handleCallVoidVoid); diff --git a/llvm/include/llvm/ExecutionEngine/Orc/RPC/RPCSerialization.h b/llvm/include/llvm/ExecutionEngine/Orc/RPC/RPCSerialization.h index 9c69a84f4c67..2f37ab40c7f8 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/RPC/RPCSerialization.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/RPC/RPCSerialization.h @@ -230,9 +230,9 @@ public: /// /// template /// class SerializationTraits::value -/// >::type> { +/// >> { /// public: /// static const char* getName() { ... }; /// } @@ -274,9 +274,8 @@ public: template static Error serialize(ChannelT &C, CArgT &&CArg) { - return SerializationTraits::type>:: - serialize(C, std::forward(CArg)); + return SerializationTraits>::serialize( + C, std::forward(CArg)); } template @@ -293,8 +292,8 @@ public: static Error serialize(ChannelT &C, CArgT &&CArg, CArgTs &&... CArgs) { if (auto Err = - SerializationTraits::type>:: - serialize(C, std::forward(CArg))) + SerializationTraits>::serialize( + C, std::forward(CArg))) return Err; if (auto Err = SequenceTraits::emitSeparator(C)) return Err; @@ -316,8 +315,8 @@ public: template Error serializeSeq(ChannelT &C, ArgTs &&... Args) { - return SequenceSerialization::type...>:: - serialize(C, std::forward(Args)...); + return SequenceSerialization...>::serialize( + C, std::forward(Args)...); } template diff --git a/llvm/include/llvm/ExecutionEngine/Orc/RPC/RPCUtils.h b/llvm/include/llvm/ExecutionEngine/Orc/RPC/RPCUtils.h index ed09363dcecc..f348844f39ce 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/RPC/RPCUtils.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/RPC/RPCUtils.h @@ -184,8 +184,7 @@ template class RPCFunctionIdAllocator; /// This specialization of RPCFunctionIdAllocator provides a default /// implementation for integral types. template -class RPCFunctionIdAllocator< - T, typename std::enable_if::value>::type> { +class RPCFunctionIdAllocator::value>> { public: static T getInvalidId() { return T(0); } static T getResponseId() { return T(1); } @@ -205,8 +204,7 @@ template class FunctionArgsTuple; template class FunctionArgsTuple { public: - using Type = std::tuple::type>::type...>; + using Type = std::tuple>...>; }; // ResultTraits provides typedefs and utilities specific to the return type @@ -483,9 +481,9 @@ public: }; template -class AsyncHandlerTraits : - public AsyncHandlerTraits::type, - ArgTs...)> {}; +class AsyncHandlerTraits + : public AsyncHandlerTraits, + ArgTs...)> {}; // This template class provides utilities related to RPC function handlers. // The base case applies to non-function types (the template class is @@ -524,18 +522,17 @@ public: // Call the given handler with the given arguments. template - static typename std::enable_if< - std::is_void::ReturnType>::value, - Error>::type + static std::enable_if_t< + std::is_void::ReturnType>::value, Error> run(HandlerT &Handler, ArgTs &&... Args) { Handler(std::move(Args)...); return Error::success(); } template - static typename std::enable_if< + static std::enable_if_t< !std::is_void::ReturnType>::value, - typename HandlerTraits::ReturnType>::type + typename HandlerTraits::ReturnType> run(HandlerT &Handler, TArgTs... Args) { return Handler(std::move(Args)...); } @@ -894,12 +891,12 @@ private: using S = SerializationTraits; template - static std::true_type - check(typename std::enable_if< - std::is_same(), - std::declval())), - Error>::value, - void *>::type); + static std::true_type check( + std::enable_if_t(), + std::declval())), + Error>::value, + void *>); template static std::false_type check(...); @@ -914,11 +911,11 @@ private: template static std::true_type - check(typename std::enable_if< - std::is_same(), - std::declval())), - Error>::value, - void *>::type); + check(std::enable_if_t< + std::is_same(), + std::declval())), + Error>::value, + void *>); template static std::false_type check(...); diff --git a/llvm/include/llvm/ExecutionEngine/Orc/RPC/RawByteChannel.h b/llvm/include/llvm/ExecutionEngine/Orc/RPC/RawByteChannel.h index 50e26f8449df..35745993248c 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/RPC/RawByteChannel.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/RPC/RawByteChannel.h @@ -87,13 +87,13 @@ private: template class SerializationTraits< ChannelT, T, T, - typename std::enable_if< + std::enable_if_t< std::is_base_of::value && (std::is_same::value || std::is_same::value || std::is_same::value || std::is_same::value || std::is_same::value || std::is_same::value || std::is_same::value || std::is_same::value || - std::is_same::value)>::type> { + std::is_same::value)>> { public: static Error serialize(ChannelT &C, T V) { support::endian::byte_swap(V); @@ -109,9 +109,9 @@ public: }; template -class SerializationTraits::value>::type> { +class SerializationTraits< + ChannelT, bool, bool, + std::enable_if_t::value>> { public: static Error serialize(ChannelT &C, bool V) { uint8_t Tmp = V ? 1 : 0; @@ -131,9 +131,9 @@ public: }; template -class SerializationTraits::value>::type> { +class SerializationTraits< + ChannelT, std::string, StringRef, + std::enable_if_t::value>> { public: /// RPC channel serialization for std::strings. static Error serialize(RawByteChannel &C, StringRef S) { @@ -144,11 +144,11 @@ public: }; template -class SerializationTraits::value && - (std::is_same::value || - std::is_same::value)>::type> { +class SerializationTraits< + ChannelT, std::string, T, + std::enable_if_t::value && + (std::is_same::value || + std::is_same::value)>> { public: static Error serialize(RawByteChannel &C, const char *S) { return SerializationTraits::serialize(C, @@ -157,9 +157,9 @@ public: }; template -class SerializationTraits::value>::type> { +class SerializationTraits< + ChannelT, std::string, std::string, + std::enable_if_t::value>> { public: /// RPC channel serialization for std::strings. static Error serialize(RawByteChannel &C, const std::string &S) { diff --git a/llvm/include/llvm/FuzzMutate/Random.h b/llvm/include/llvm/FuzzMutate/Random.h index 615b15f04ceb..9d3af3accb15 100644 --- a/llvm/include/llvm/FuzzMutate/Random.h +++ b/llvm/include/llvm/FuzzMutate/Random.h @@ -32,7 +32,7 @@ template T uniform(GenT &Gen) { /// elements, which may each be weighted to be more likely choices. template class ReservoirSampler { GenT &RandGen; - typename std::remove_const::type Selection = {}; + std::remove_const_t Selection = {}; uint64_t TotalWeight = 0; public: @@ -70,8 +70,8 @@ public: }; template ()))>::type> + typename ElT = std::remove_reference_t< + decltype(*std::begin(std::declval()))>> ReservoirSampler makeSampler(GenT &RandGen, RangeT &&Items) { ReservoirSampler RS(RandGen); RS.sample(Items); diff --git a/llvm/include/llvm/IR/Constants.h b/llvm/include/llvm/IR/Constants.h index 9b3c1e723a10..90bf22bd4344 100644 --- a/llvm/include/llvm/IR/Constants.h +++ b/llvm/include/llvm/IR/Constants.h @@ -460,8 +460,7 @@ public: static Constant *get(StructType *T, ArrayRef V); template - static typename std::enable_if::value, - Constant *>::type + static std::enable_if_t::value, Constant *> get(StructType *T, Csts *... Vs) { SmallVector Values({Vs...}); return get(T, Values); diff --git a/llvm/include/llvm/IR/DerivedTypes.h b/llvm/include/llvm/IR/DerivedTypes.h index 20097ef3f31a..3b56da680c6e 100644 --- a/llvm/include/llvm/IR/DerivedTypes.h +++ b/llvm/include/llvm/IR/DerivedTypes.h @@ -267,8 +267,7 @@ public: StringRef Name, bool isPacked = false); static StructType *create(LLVMContext &Context, ArrayRef Elements); template - static typename std::enable_if::value, - StructType *>::type + static std::enable_if_t::value, StructType *> create(StringRef Name, Type *elt1, Tys *... elts) { assert(elt1 && "Cannot create a struct type with no elements with this"); SmallVector StructFields({elt1, elts...}); @@ -286,8 +285,7 @@ public: /// specifying the elements as arguments. Note that this method always returns /// a non-packed struct, and requires at least one element type. template - static typename std::enable_if::value, - StructType *>::type + static std::enable_if_t::value, StructType *> get(Type *elt1, Tys *... elts) { assert(elt1 && "Cannot create a struct type with no elements with this"); LLVMContext &Ctx = elt1->getContext(); @@ -324,7 +322,7 @@ public: void setBody(ArrayRef Elements, bool isPacked = false); template - typename std::enable_if::value, void>::type + std::enable_if_t::value, void> setBody(Type *elt1, Tys *... elts) { assert(elt1 && "Cannot create a struct type with no elements with this"); SmallVector StructFields({elt1, elts...}); diff --git a/llvm/include/llvm/IR/DiagnosticInfo.h b/llvm/include/llvm/IR/DiagnosticInfo.h index ec469982d378..44db0eacca1a 100644 --- a/llvm/include/llvm/IR/DiagnosticInfo.h +++ b/llvm/include/llvm/IR/DiagnosticInfo.h @@ -531,9 +531,10 @@ protected: template RemarkT & operator<<(RemarkT &R, - typename std::enable_if< + std::enable_if_t< std::is_base_of::value, - StringRef>::type S) { + StringRef> + S) { R.insert(S); return R; } @@ -543,9 +544,10 @@ operator<<(RemarkT &R, template RemarkT & operator<<(RemarkT &&R, - typename std::enable_if< + std::enable_if_t< std::is_base_of::value, - StringRef>::type S) { + StringRef> + S) { R.insert(S); return R; } @@ -553,9 +555,10 @@ operator<<(RemarkT &&R, template RemarkT & operator<<(RemarkT &R, - typename std::enable_if< + std::enable_if_t< std::is_base_of::value, - DiagnosticInfoOptimizationBase::Argument>::type A) { + DiagnosticInfoOptimizationBase::Argument> + A) { R.insert(A); return R; } @@ -563,9 +566,10 @@ operator<<(RemarkT &R, template RemarkT & operator<<(RemarkT &&R, - typename std::enable_if< + std::enable_if_t< std::is_base_of::value, - DiagnosticInfoOptimizationBase::Argument>::type A) { + DiagnosticInfoOptimizationBase::Argument> + A) { R.insert(A); return R; } @@ -573,9 +577,10 @@ operator<<(RemarkT &&R, template RemarkT & operator<<(RemarkT &R, - typename std::enable_if< + std::enable_if_t< std::is_base_of::value, - DiagnosticInfoOptimizationBase::setIsVerbose>::type V) { + DiagnosticInfoOptimizationBase::setIsVerbose> + V) { R.insert(V); return R; } @@ -583,9 +588,10 @@ operator<<(RemarkT &R, template RemarkT & operator<<(RemarkT &&R, - typename std::enable_if< + std::enable_if_t< std::is_base_of::value, - DiagnosticInfoOptimizationBase::setIsVerbose>::type V) { + DiagnosticInfoOptimizationBase::setIsVerbose> + V) { R.insert(V); return R; } @@ -593,9 +599,10 @@ operator<<(RemarkT &&R, template RemarkT & operator<<(RemarkT &R, - typename std::enable_if< + std::enable_if_t< std::is_base_of::value, - DiagnosticInfoOptimizationBase::setExtraArgs>::type EA) { + DiagnosticInfoOptimizationBase::setExtraArgs> + EA) { R.insert(EA); return R; } diff --git a/llvm/include/llvm/IR/Metadata.h b/llvm/include/llvm/IR/Metadata.h index dda939b97575..46526c70ea3b 100644 --- a/llvm/include/llvm/IR/Metadata.h +++ b/llvm/include/llvm/IR/Metadata.h @@ -527,7 +527,7 @@ template struct IsValidReference { /// As an analogue to \a isa(), check whether \c MD has an \a Value inside of /// type \c X. template -inline typename std::enable_if::value, bool>::type +inline std::enable_if_t::value, bool> hasa(Y &&MD) { assert(MD && "Null pointer sent into hasa"); if (auto *V = dyn_cast(MD)) @@ -535,9 +535,8 @@ hasa(Y &&MD) { return false; } template -inline - typename std::enable_if::value, bool>::type - hasa(Y &MD) { +inline std::enable_if_t::value, bool> +hasa(Y &MD) { return hasa(&MD); } @@ -545,14 +544,13 @@ inline /// /// As an analogue to \a cast(), extract the \a Value subclass \c X from \c MD. template -inline typename std::enable_if::value, X *>::type +inline std::enable_if_t::value, X *> extract(Y &&MD) { return cast(cast(MD)->getValue()); } template -inline - typename std::enable_if::value, X *>::type - extract(Y &MD) { +inline std::enable_if_t::value, X *> +extract(Y &MD) { return extract(&MD); } @@ -561,7 +559,7 @@ inline /// As an analogue to \a cast_or_null(), extract the \a Value subclass \c X /// from \c MD, allowing \c MD to be null. template -inline typename std::enable_if::value, X *>::type +inline std::enable_if_t::value, X *> extract_or_null(Y &&MD) { if (auto *V = cast_or_null(MD)) return cast(V->getValue()); @@ -574,7 +572,7 @@ extract_or_null(Y &&MD) { /// from \c MD, return null if \c MD doesn't contain a \a Value or if the \a /// Value it does contain is of the wrong subclass. template -inline typename std::enable_if::value, X *>::type +inline std::enable_if_t::value, X *> dyn_extract(Y &&MD) { if (auto *V = dyn_cast(MD)) return dyn_cast(V->getValue()); @@ -587,7 +585,7 @@ dyn_extract(Y &&MD) { /// from \c MD, return null if \c MD doesn't contain a \a Value or if the \a /// Value it does contain is of the wrong subclass, allowing \c MD to be null. template -inline typename std::enable_if::value, X *>::type +inline std::enable_if_t::value, X *> dyn_extract_or_null(Y &&MD) { if (auto *V = dyn_cast_or_null(MD)) return dyn_cast(V->getValue()); @@ -976,7 +974,7 @@ public: /// Try to create a uniqued version of \c N -- in place, if possible -- and /// return it. If \c N cannot be uniqued, return a distinct node instead. template - static typename std::enable_if::value, T *>::type + static std::enable_if_t::value, T *> replaceWithPermanent(std::unique_ptr N) { return cast(N.release()->replaceWithPermanentImpl()); } @@ -988,7 +986,7 @@ public: /// /// \pre N does not self-reference. template - static typename std::enable_if::value, T *>::type + static std::enable_if_t::value, T *> replaceWithUniqued(std::unique_ptr N) { return cast(N.release()->replaceWithUniquedImpl()); } @@ -998,7 +996,7 @@ public: /// Create a distinct version of \c N -- in place, if possible -- and return /// it. Takes ownership of the temporary node. template - static typename std::enable_if::value, T *>::type + static std::enable_if_t::value, T *> replaceWithDistinct(std::unique_ptr N) { return cast(N.release()->replaceWithDistinctImpl()); } @@ -1237,15 +1235,13 @@ public: template MDTupleTypedArrayWrapper( const MDTupleTypedArrayWrapper &Other, - typename std::enable_if::value>::type * = - nullptr) + std::enable_if_t::value> * = nullptr) : N(Other.get()) {} template explicit MDTupleTypedArrayWrapper( const MDTupleTypedArrayWrapper &Other, - typename std::enable_if::value>::type * = - nullptr) + std::enable_if_t::value> * = nullptr) : N(Other.get()) {} explicit operator bool() const { return get(); } diff --git a/llvm/include/llvm/IR/ValueMap.h b/llvm/include/llvm/IR/ValueMap.h index fb5440d5efe8..a5a06b76dbf6 100644 --- a/llvm/include/llvm/IR/ValueMap.h +++ b/llvm/include/llvm/IR/ValueMap.h @@ -243,7 +243,7 @@ class ValueMapCallbackVH final : public CallbackVH { friend struct DenseMapInfo; using ValueMapT = ValueMap; - using KeySansPointerT = typename std::remove_pointer::type; + using KeySansPointerT = std::remove_pointer_t; ValueMapT *Map; diff --git a/llvm/include/llvm/Object/ELFTypes.h b/llvm/include/llvm/Object/ELFTypes.h index 7d1ade4d5437..32ad1e4ea40b 100644 --- a/llvm/include/llvm/Object/ELFTypes.h +++ b/llvm/include/llvm/Object/ELFTypes.h @@ -53,7 +53,7 @@ public: static const endianness TargetEndianness = E; static const bool Is64Bits = Is64; - using uint = typename std::conditional::type; + using uint = std::conditional_t; using Ehdr = Elf_Ehdr_Impl>; using Shdr = Elf_Shdr_Impl>; using Sym = Elf_Sym_Impl>; @@ -346,10 +346,8 @@ template struct Elf_Dyn_Impl : Elf_Dyn_Base { using Elf_Dyn_Base::d_tag; using Elf_Dyn_Base::d_un; - using intX_t = typename std::conditional::type; - using uintX_t = typename std::conditional::type; + using intX_t = std::conditional_t; + using uintX_t = std::conditional_t; intX_t getTag() const { return d_tag; } uintX_t getVal() const { return d_un.d_val; } uintX_t getPtr() const { return d_un.d_ptr; } diff --git a/llvm/include/llvm/Support/AllocatorBase.h b/llvm/include/llvm/Support/AllocatorBase.h index c5a2f03e6bf8..7f430040ddfb 100644 --- a/llvm/include/llvm/Support/AllocatorBase.h +++ b/llvm/include/llvm/Support/AllocatorBase.h @@ -70,8 +70,7 @@ public: /// Deallocate space for a sequence of objects without constructing them. template - typename std::enable_if< - !std::is_same::type, void>::value, void>::type + std::enable_if_t, void>::value, void> Deallocate(T *Ptr, size_t Num = 1) { Deallocate(static_cast(Ptr), Num * sizeof(T)); } diff --git a/llvm/include/llvm/Support/BinaryStreamReader.h b/llvm/include/llvm/Support/BinaryStreamReader.h index c586f865fdc5..b611707807c0 100644 --- a/llvm/include/llvm/Support/BinaryStreamReader.h +++ b/llvm/include/llvm/Support/BinaryStreamReader.h @@ -90,7 +90,7 @@ public: template Error readEnum(T &Dest) { static_assert(std::is_enum::value, "Cannot call readEnum with non-enum value!"); - typename std::underlying_type::type N; + std::underlying_type_t N; if (auto EC = readInteger(N)) return EC; Dest = static_cast(N); diff --git a/llvm/include/llvm/Support/BinaryStreamWriter.h b/llvm/include/llvm/Support/BinaryStreamWriter.h index 86d2389d9182..ceba792e6b26 100644 --- a/llvm/include/llvm/Support/BinaryStreamWriter.h +++ b/llvm/include/llvm/Support/BinaryStreamWriter.h @@ -75,7 +75,7 @@ public: static_assert(std::is_enum::value, "Cannot call writeEnum with non-Enum type"); - using U = typename std::underlying_type::type; + using U = std::underlying_type_t; return writeInteger(static_cast(Num)); } diff --git a/llvm/include/llvm/Support/Casting.h b/llvm/include/llvm/Support/Casting.h index ae7e9fd81219..41f1b6740c6f 100644 --- a/llvm/include/llvm/Support/Casting.h +++ b/llvm/include/llvm/Support/Casting.h @@ -61,8 +61,7 @@ struct isa_impl { /// Always allow upcasts, and perform no dynamic check for them. template -struct isa_impl< - To, From, typename std::enable_if::value>::type> { +struct isa_impl::value>> { static inline bool doit(const From &) { return true; } }; @@ -184,7 +183,7 @@ template struct cast_retty_impl> { private: using PointerType = typename cast_retty_impl::ret_type; - using ResultType = typename std::remove_pointer::type; + using ResultType = std::remove_pointer_t; public: using ret_type = std::unique_ptr; @@ -244,8 +243,8 @@ template struct is_simple_type { // cast(myVal)->getParent() // template -inline typename std::enable_if::value, - typename cast_retty::ret_type>::type +inline std::enable_if_t::value, + typename cast_retty::ret_type> cast(const Y &Val) { assert(isa(Val) && "cast() argument of incompatible type!"); return cast_convert_val< @@ -280,10 +279,9 @@ cast(std::unique_ptr &&Val) { // accepted. // template -LLVM_NODISCARD inline - typename std::enable_if::value, - typename cast_retty::ret_type>::type - cast_or_null(const Y &Val) { +LLVM_NODISCARD inline std::enable_if_t< + !is_simple_type::value, typename cast_retty::ret_type> +cast_or_null(const Y &Val) { if (!Val) return nullptr; assert(isa(Val) && "cast_or_null() argument of incompatible type!"); @@ -291,10 +289,9 @@ LLVM_NODISCARD inline } template -LLVM_NODISCARD inline - typename std::enable_if::value, - typename cast_retty::ret_type>::type - cast_or_null(Y &Val) { +LLVM_NODISCARD inline std::enable_if_t::value, + typename cast_retty::ret_type> +cast_or_null(Y &Val) { if (!Val) return nullptr; assert(isa(Val) && "cast_or_null() argument of incompatible type!"); @@ -326,10 +323,9 @@ cast_or_null(std::unique_ptr &&Val) { // template -LLVM_NODISCARD inline - typename std::enable_if::value, - typename cast_retty::ret_type>::type - dyn_cast(const Y &Val) { +LLVM_NODISCARD inline std::enable_if_t< + !is_simple_type::value, typename cast_retty::ret_type> +dyn_cast(const Y &Val) { return isa(Val) ? cast(Val) : nullptr; } @@ -347,18 +343,16 @@ LLVM_NODISCARD inline typename cast_retty::ret_type dyn_cast(Y *Val) { // value is accepted. // template -LLVM_NODISCARD inline - typename std::enable_if::value, - typename cast_retty::ret_type>::type - dyn_cast_or_null(const Y &Val) { +LLVM_NODISCARD inline std::enable_if_t< + !is_simple_type::value, typename cast_retty::ret_type> +dyn_cast_or_null(const Y &Val) { return (Val && isa(Val)) ? cast(Val) : nullptr; } template -LLVM_NODISCARD inline - typename std::enable_if::value, - typename cast_retty::ret_type>::type - dyn_cast_or_null(Y &Val) { +LLVM_NODISCARD inline std::enable_if_t::value, + typename cast_retty::ret_type> +dyn_cast_or_null(Y &Val) { return (Val && isa(Val)) ? cast(Val) : nullptr; } diff --git a/llvm/include/llvm/Support/CheckedArithmetic.h b/llvm/include/llvm/Support/CheckedArithmetic.h index 8a50e3d5ddf6..035e4533322c 100644 --- a/llvm/include/llvm/Support/CheckedArithmetic.h +++ b/llvm/include/llvm/Support/CheckedArithmetic.h @@ -25,8 +25,8 @@ namespace { /// \p RHS. /// \return Empty optional if the operation overflows, or result otherwise. template -typename std::enable_if::value && sizeof(T) * 8 <= 64, - llvm::Optional>::type +std::enable_if_t::value && sizeof(T) * 8 <= 64, + llvm::Optional> checkedOp(T LHS, T RHS, F Op, bool Signed = true) { llvm::APInt ALHS(/*BitSize=*/sizeof(T) * 8, LHS, Signed); llvm::APInt ARHS(/*BitSize=*/sizeof(T) * 8, RHS, Signed); @@ -44,7 +44,7 @@ namespace llvm { /// \return Optional of sum if no signed overflow occurred, /// \c None otherwise. template -typename std::enable_if::value, llvm::Optional>::type +std::enable_if_t::value, llvm::Optional> checkedAdd(T LHS, T RHS) { return checkedOp(LHS, RHS, &llvm::APInt::sadd_ov); } @@ -53,7 +53,7 @@ checkedAdd(T LHS, T RHS) { /// \return Optional of sum if no signed overflow occurred, /// \c None otherwise. template -typename std::enable_if::value, llvm::Optional>::type +std::enable_if_t::value, llvm::Optional> checkedSub(T LHS, T RHS) { return checkedOp(LHS, RHS, &llvm::APInt::ssub_ov); } @@ -62,7 +62,7 @@ checkedSub(T LHS, T RHS) { /// \return Optional of product if no signed overflow occurred, /// \c None otherwise. template -typename std::enable_if::value, llvm::Optional>::type +std::enable_if_t::value, llvm::Optional> checkedMul(T LHS, T RHS) { return checkedOp(LHS, RHS, &llvm::APInt::smul_ov); } @@ -71,7 +71,7 @@ checkedMul(T LHS, T RHS) { /// \return Optional of result if no signed overflow occurred, /// \c None otherwise. template -typename std::enable_if::value, llvm::Optional>::type +std::enable_if_t::value, llvm::Optional> checkedMulAdd(T A, T B, T C) { if (auto Product = checkedMul(A, B)) return checkedAdd(*Product, C); @@ -82,7 +82,7 @@ checkedMulAdd(T A, T B, T C) { /// \return Optional of sum if no unsigned overflow occurred, /// \c None otherwise. template -typename std::enable_if::value, llvm::Optional>::type +std::enable_if_t::value, llvm::Optional> checkedAddUnsigned(T LHS, T RHS) { return checkedOp(LHS, RHS, &llvm::APInt::uadd_ov, /*Signed=*/false); } @@ -91,7 +91,7 @@ checkedAddUnsigned(T LHS, T RHS) { /// \return Optional of product if no unsigned overflow occurred, /// \c None otherwise. template -typename std::enable_if::value, llvm::Optional>::type +std::enable_if_t::value, llvm::Optional> checkedMulUnsigned(T LHS, T RHS) { return checkedOp(LHS, RHS, &llvm::APInt::umul_ov, /*Signed=*/false); } @@ -100,7 +100,7 @@ checkedMulUnsigned(T LHS, T RHS) { /// \return Optional of result if no unsigned overflow occurred, /// \c None otherwise. template -typename std::enable_if::value, llvm::Optional>::type +std::enable_if_t::value, llvm::Optional> checkedMulAddUnsigned(T A, T B, T C) { if (auto Product = checkedMulUnsigned(A, B)) return checkedAddUnsigned(*Product, C); diff --git a/llvm/include/llvm/Support/Chrono.h b/llvm/include/llvm/Support/Chrono.h index 334ab60835a4..098512dce783 100644 --- a/llvm/include/llvm/Support/Chrono.h +++ b/llvm/include/llvm/Support/Chrono.h @@ -112,8 +112,8 @@ template struct format_provider> { private: typedef std::chrono::duration Dur; - typedef typename std::conditional< - std::chrono::treat_as_floating_point::value, double, intmax_t>::type + typedef std::conditional_t::value, + double, intmax_t> InternalRep; template static InternalRep getAs(const Dur &D) { diff --git a/llvm/include/llvm/Support/CommandLine.h b/llvm/include/llvm/Support/CommandLine.h index 05374e34aa7d..0242e35c05bd 100644 --- a/llvm/include/llvm/Support/CommandLine.h +++ b/llvm/include/llvm/Support/CommandLine.h @@ -488,14 +488,13 @@ struct callback_traits : public callback_traits {}; template struct callback_traits { using result_type = R; - using arg_type = typename std::tuple_element<0, std::tuple>::type; + using arg_type = std::tuple_element_t<0, std::tuple>; static_assert(sizeof...(Args) == 1, "callback function must have one and only one parameter"); static_assert(std::is_same::value, "callback return type must be void"); - static_assert( - std::is_lvalue_reference::value && - std::is_const::type>::value, - "callback arg_type must be a const lvalue reference"); + static_assert(std::is_lvalue_reference::value && + std::is_const>::value, + "callback arg_type must be a const lvalue reference"); }; } // namespace detail @@ -1453,16 +1452,16 @@ class opt : public Option, } } - template ::value>::type> + template ::value>> void setDefaultImpl() { const OptionValue &V = this->getDefault(); if (V.hasValue()) this->setValue(V.getValue()); } - template ::value>::type> + template ::value>> void setDefaultImpl(...) {} void setDefault() override { setDefaultImpl(); } diff --git a/llvm/include/llvm/Support/Endian.h b/llvm/include/llvm/Support/Endian.h index 87aecedd3a4b..0b9f866cd976 100644 --- a/llvm/include/llvm/Support/Endian.h +++ b/llvm/include/llvm/Support/Endian.h @@ -111,7 +111,7 @@ inline void write(void *memory, value_type value) { } template -using make_unsigned_t = typename std::make_unsigned::type; +using make_unsigned_t = std::make_unsigned_t; /// Read a value of a particular endianness from memory, for a location /// that starts at the given bit offset within the first byte. diff --git a/llvm/include/llvm/Support/Error.h b/llvm/include/llvm/Support/Error.h index 44676338808b..f1e3059368d5 100644 --- a/llvm/include/llvm/Support/Error.h +++ b/llvm/include/llvm/Support/Error.h @@ -436,19 +436,19 @@ template class LLVM_NODISCARD Expected { static const bool isRef = std::is_reference::value; - using wrap = std::reference_wrapper::type>; + using wrap = std::reference_wrapper>; using error_type = std::unique_ptr; public: - using storage_type = typename std::conditional::type; + using storage_type = std::conditional_t; using value_type = T; private: - using reference = typename std::remove_reference::type &; - using const_reference = const typename std::remove_reference::type &; - using pointer = typename std::remove_reference::type *; - using const_pointer = const typename std::remove_reference::type *; + using reference = std::remove_reference_t &; + using const_reference = const std::remove_reference_t &; + using pointer = std::remove_reference_t *; + using const_pointer = const std::remove_reference_t *; public: /// Create an Expected error value from the given Error. @@ -472,12 +472,12 @@ public: /// must be convertible to T. template Expected(OtherT &&Val, - typename std::enable_if::value>::type - * = nullptr) + std::enable_if_t::value> * = nullptr) : HasError(false) #if LLVM_ENABLE_ABI_BREAKING_CHECKS // Expected is unchecked upon construction in Debug builds. - , Unchecked(true) + , + Unchecked(true) #endif { new (getStorage()) storage_type(std::forward(Val)); @@ -489,9 +489,9 @@ public: /// Move construct an Expected value from an Expected, where OtherT /// must be convertible to T. template - Expected(Expected &&Other, - typename std::enable_if::value>::type - * = nullptr) { + Expected( + Expected &&Other, + std::enable_if_t::value> * = nullptr) { moveConstruct(std::move(Other)); } @@ -500,8 +500,7 @@ public: template explicit Expected( Expected &&Other, - typename std::enable_if::value>::type * = - nullptr) { + std::enable_if_t::value> * = nullptr) { moveConstruct(std::move(Other)); } diff --git a/llvm/include/llvm/Support/ErrorOr.h b/llvm/include/llvm/Support/ErrorOr.h index 8211f4d8a098..4750cd832ef7 100644 --- a/llvm/include/llvm/Support/ErrorOr.h +++ b/llvm/include/llvm/Support/ErrorOr.h @@ -58,23 +58,23 @@ class ErrorOr { static const bool isRef = std::is_reference::value; - using wrap = std::reference_wrapper::type>; + using wrap = std::reference_wrapper>; public: - using storage_type = typename std::conditional::type; + using storage_type = std::conditional_t; private: - using reference = typename std::remove_reference::type &; - using const_reference = const typename std::remove_reference::type &; - using pointer = typename std::remove_reference::type *; - using const_pointer = const typename std::remove_reference::type *; + using reference = std::remove_reference_t &; + using const_reference = const std::remove_reference_t &; + using pointer = std::remove_reference_t *; + using const_pointer = const std::remove_reference_t *; public: template ErrorOr(E ErrorCode, - typename std::enable_if::value || - std::is_error_condition_enum::value, - void *>::type = nullptr) + std::enable_if_t::value || + std::is_error_condition_enum::value, + void *> = nullptr) : HasError(true) { new (getErrorStorage()) std::error_code(make_error_code(ErrorCode)); } @@ -85,8 +85,7 @@ public: template ErrorOr(OtherT &&Val, - typename std::enable_if::value>::type - * = nullptr) + std::enable_if_t::value> * = nullptr) : HasError(false) { new (getStorage()) storage_type(std::forward(Val)); } @@ -96,18 +95,16 @@ public: } template - ErrorOr( - const ErrorOr &Other, - typename std::enable_if::value>::type * = - nullptr) { + ErrorOr(const ErrorOr &Other, + std::enable_if_t::value> * = nullptr) { copyConstruct(Other); } template explicit ErrorOr( const ErrorOr &Other, - typename std::enable_if< - !std::is_convertible::value>::type * = nullptr) { + std::enable_if_t::value> * = + nullptr) { copyConstruct(Other); } @@ -116,10 +113,8 @@ public: } template - ErrorOr( - ErrorOr &&Other, - typename std::enable_if::value>::type * = - nullptr) { + ErrorOr(ErrorOr &&Other, + std::enable_if_t::value> * = nullptr) { moveConstruct(std::move(Other)); } @@ -128,8 +123,7 @@ public: template explicit ErrorOr( ErrorOr &&Other, - typename std::enable_if::value>::type * = - nullptr) { + std::enable_if_t::value> * = nullptr) { moveConstruct(std::move(Other)); } @@ -266,9 +260,9 @@ private: }; template -typename std::enable_if::value || - std::is_error_condition_enum::value, - bool>::type +std::enable_if_t::value || + std::is_error_condition_enum::value, + bool> operator==(const ErrorOr &Err, E Code) { return Err.getError() == Code; } diff --git a/llvm/include/llvm/Support/FormatProviders.h b/llvm/include/llvm/Support/FormatProviders.h index 629a4845716a..c31481a29259 100644 --- a/llvm/include/llvm/Support/FormatProviders.h +++ b/llvm/include/llvm/Support/FormatProviders.h @@ -124,7 +124,7 @@ protected: template struct format_provider< - T, typename std::enable_if::value>::type> + T, std::enable_if_t::value>> : public detail::HelperFunctions { private: public: @@ -173,7 +173,7 @@ public: /// cases indicates the minimum number of nibbles to print. template struct format_provider< - T, typename std::enable_if::value>::type> + T, std::enable_if_t::value>> : public detail::HelperFunctions { private: public: @@ -198,7 +198,7 @@ public: template struct format_provider< - T, typename std::enable_if::value>::type> { + T, std::enable_if_t::value>> { static void format(const T &V, llvm::raw_ostream &Stream, StringRef Style) { size_t N = StringRef::npos; if (!Style.empty() && Style.getAsInteger(10, N)) { @@ -230,8 +230,8 @@ template <> struct format_provider { /// character. Otherwise, it is treated as an integer options string. /// template -struct format_provider< - T, typename std::enable_if::value>::type> { +struct format_provider::value>> { static void format(const char &V, llvm::raw_ostream &Stream, StringRef Style) { if (Style.empty()) @@ -296,8 +296,8 @@ template <> struct format_provider { /// else. template -struct format_provider< - T, typename std::enable_if::value>::type> +struct format_provider::value>> : public detail::HelperFunctions { static void format(const T &V, llvm::raw_ostream &Stream, StringRef Style) { FloatStyle S; diff --git a/llvm/include/llvm/Support/FormatVariadicDetails.h b/llvm/include/llvm/Support/FormatVariadicDetails.h index e3c185134daa..d5e67b756a47 100644 --- a/llvm/include/llvm/Support/FormatVariadicDetails.h +++ b/llvm/include/llvm/Support/FormatVariadicDetails.h @@ -36,7 +36,7 @@ public: explicit provider_format_adapter(T &&Item) : Item(std::forward(Item)) {} void format(llvm::raw_ostream &S, StringRef Options) override { - format_provider::type>::format(Item, S, Options); + format_provider>::format(Item, S, Options); } }; @@ -59,7 +59,7 @@ template class missing_format_adapter; // template class has_FormatProvider { public: - using Decayed = typename std::decay::type; + using Decayed = std::decay_t; typedef void (*Signature_format)(const Decayed &, llvm::raw_ostream &, StringRef); @@ -75,14 +75,14 @@ public: // Test if raw_ostream& << T -> raw_ostream& is findable via ADL. template class has_StreamOperator { public: - using ConstRefT = const typename std::decay::type &; + using ConstRefT = const std::decay_t &; template - static char test(typename std::enable_if< - std::is_same() - << std::declval()), - llvm::raw_ostream &>::value, - int *>::type); + static char test( + std::enable_if_t() + << std::declval()), + llvm::raw_ostream &>::value, + int *>); template static double test(...); @@ -95,8 +95,8 @@ template struct uses_format_member : public std::integral_constant< bool, - std::is_base_of::type>::value> {}; + std::is_base_of>::value> { +}; // Simple template that decides whether a type T should use the format_provider // based format() invocation. The member function takes priority, so this test @@ -127,34 +127,32 @@ struct uses_missing_provider }; template -typename std::enable_if::value, T>::type +std::enable_if_t::value, T> build_format_adapter(T &&Item) { return std::forward(Item); } template -typename std::enable_if::value, - provider_format_adapter>::type +std::enable_if_t::value, provider_format_adapter> build_format_adapter(T &&Item) { return provider_format_adapter(std::forward(Item)); } template -typename std::enable_if::value, - stream_operator_format_adapter>::type +std::enable_if_t::value, + stream_operator_format_adapter> build_format_adapter(T &&Item) { // If the caller passed an Error by value, then stream_operator_format_adapter // would be responsible for consuming it. // Make the caller opt into this by calling fmt_consume(). static_assert( - !std::is_same::type>::value, + !std::is_same>::value, "llvm::Error-by-value must be wrapped in fmt_consume() for formatv"); return stream_operator_format_adapter(std::forward(Item)); } template -typename std::enable_if::value, - missing_format_adapter>::type +std::enable_if_t::value, missing_format_adapter> build_format_adapter(T &&Item) { return missing_format_adapter(); } diff --git a/llvm/include/llvm/Support/GenericDomTree.h b/llvm/include/llvm/Support/GenericDomTree.h index 2545a075062a..1e1fc1fa2486 100644 --- a/llvm/include/llvm/Support/GenericDomTree.h +++ b/llvm/include/llvm/Support/GenericDomTree.h @@ -225,7 +225,7 @@ class DominatorTreeBase { using ParentPtr = decltype(std::declval()->getParent()); static_assert(std::is_pointer::value, "Currently NodeT's parent must be a pointer type"); - using ParentType = typename std::remove_pointer::type; + using ParentType = std::remove_pointer_t; static constexpr bool IsPostDominator = IsPostDom; using UpdateType = cfg::Update; diff --git a/llvm/include/llvm/Support/GenericIteratedDominanceFrontier.h b/llvm/include/llvm/Support/GenericIteratedDominanceFrontier.h index 25eb7cd7b6d5..ddc0f1c24606 100644 --- a/llvm/include/llvm/Support/GenericIteratedDominanceFrontier.h +++ b/llvm/include/llvm/Support/GenericIteratedDominanceFrontier.h @@ -57,7 +57,7 @@ template struct ChildrenGetterTy { template class IDFCalculatorBase { public: using OrderedNodeTy = - typename std::conditional, NodeTy *>::type; + std::conditional_t, NodeTy *>; using ChildrenGetterTy = IDFCalculatorDetail::ChildrenGetterTy; diff --git a/llvm/include/llvm/Support/JSON.h b/llvm/include/llvm/Support/JSON.h index ad746b62c2a3..8b1c66234fe8 100644 --- a/llvm/include/llvm/Support/JSON.h +++ b/llvm/include/llvm/Support/JSON.h @@ -329,25 +329,21 @@ public: Value(std::nullptr_t) : Type(T_Null) {} // Boolean (disallow implicit conversions). // (The last template parameter is a dummy to keep templates distinct.) - template < - typename T, - typename = typename std::enable_if::value>::type, - bool = false> + template ::value>, + bool = false> Value(T B) : Type(T_Boolean) { create(B); } // Integers (except boolean). Must be non-narrowing convertible to int64_t. - template < - typename T, - typename = typename std::enable_if::value>::type, - typename = typename std::enable_if::value>::type> + template ::value>, + typename = std::enable_if_t::value>> Value(T I) : Type(T_Integer) { create(int64_t{I}); } // Floating point. Must be non-narrowing convertible to double. template ::value>::type, + typename = std::enable_if_t::value>, double * = nullptr> Value(T D) : Type(T_Double) { create(double{D}); diff --git a/llvm/include/llvm/Support/MSVCErrorWorkarounds.h b/llvm/include/llvm/Support/MSVCErrorWorkarounds.h index 30e8febae20b..bf983dc1e406 100644 --- a/llvm/include/llvm/Support/MSVCErrorWorkarounds.h +++ b/llvm/include/llvm/Support/MSVCErrorWorkarounds.h @@ -59,22 +59,19 @@ public: template MSVCPExpected( OtherT &&Val, - typename std::enable_if::value>::type * = - nullptr) + std::enable_if_t::value> * = nullptr) : Expected(std::move(Val)) {} template MSVCPExpected( Expected &&Other, - typename std::enable_if::value>::type * = - nullptr) + std::enable_if_t::value> * = nullptr) : Expected(std::move(Other)) {} template explicit MSVCPExpected( Expected &&Other, - typename std::enable_if::value>::type * = - nullptr) + std::enable_if_t::value> * = nullptr) : Expected(std::move(Other)) {} }; diff --git a/llvm/include/llvm/Support/MathExtras.h b/llvm/include/llvm/Support/MathExtras.h index 37b9669cbeed..5ad055a4f478 100644 --- a/llvm/include/llvm/Support/MathExtras.h +++ b/llvm/include/llvm/Support/MathExtras.h @@ -364,14 +364,12 @@ constexpr inline bool isShiftedInt(int64_t x) { /// to keep MSVC from (incorrectly) warning on isUInt<64> that we're shifting /// left too many places. template -constexpr inline typename std::enable_if<(N < 64), bool>::type -isUInt(uint64_t X) { +constexpr inline std::enable_if_t<(N < 64), bool> isUInt(uint64_t X) { static_assert(N > 0, "isUInt<0> doesn't make sense"); return X < (UINT64_C(1) << (N)); } template -constexpr inline typename std::enable_if= 64, bool>::type -isUInt(uint64_t X) { +constexpr inline std::enable_if_t= 64, bool> isUInt(uint64_t X) { return true; } @@ -780,8 +778,7 @@ inline int64_t SignExtend64(uint64_t X, unsigned B) { /// Subtract two unsigned integers, X and Y, of type T and return the absolute /// value of the result. template -typename std::enable_if::value, T>::type -AbsoluteDifference(T X, T Y) { +std::enable_if_t::value, T> AbsoluteDifference(T X, T Y) { return std::max(X, Y) - std::min(X, Y); } @@ -789,7 +786,7 @@ AbsoluteDifference(T X, T Y) { /// maximum representable value of T on overflow. ResultOverflowed indicates if /// the result is larger than the maximum representable value of type T. template -typename std::enable_if::value, T>::type +std::enable_if_t::value, T> SaturatingAdd(T X, T Y, bool *ResultOverflowed = nullptr) { bool Dummy; bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy; @@ -806,7 +803,7 @@ SaturatingAdd(T X, T Y, bool *ResultOverflowed = nullptr) { /// maximum representable value of T on overflow. ResultOverflowed indicates if /// the result is larger than the maximum representable value of type T. template -typename std::enable_if::value, T>::type +std::enable_if_t::value, T> SaturatingMultiply(T X, T Y, bool *ResultOverflowed = nullptr) { bool Dummy; bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy; @@ -852,7 +849,7 @@ SaturatingMultiply(T X, T Y, bool *ResultOverflowed = nullptr) { /// overflow. ResultOverflowed indicates if the result is larger than the /// maximum representable value of type T. template -typename std::enable_if::value, T>::type +std::enable_if_t::value, T> SaturatingMultiplyAdd(T X, T Y, T A, bool *ResultOverflowed = nullptr) { bool Dummy; bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy; @@ -871,13 +868,12 @@ extern const float huge_valf; /// Add two signed integers, computing the two's complement truncated result, /// returning true if overflow occured. template -typename std::enable_if::value, T>::type -AddOverflow(T X, T Y, T &Result) { +std::enable_if_t::value, T> AddOverflow(T X, T Y, T &Result) { #if __has_builtin(__builtin_add_overflow) return __builtin_add_overflow(X, Y, &Result); #else // Perform the unsigned addition. - using U = typename std::make_unsigned::type; + using U = std::make_unsigned_t; const U UX = static_cast(X); const U UY = static_cast(Y); const U UResult = UX + UY; @@ -898,13 +894,12 @@ AddOverflow(T X, T Y, T &Result) { /// Subtract two signed integers, computing the two's complement truncated /// result, returning true if an overflow ocurred. template -typename std::enable_if::value, T>::type -SubOverflow(T X, T Y, T &Result) { +std::enable_if_t::value, T> SubOverflow(T X, T Y, T &Result) { #if __has_builtin(__builtin_sub_overflow) return __builtin_sub_overflow(X, Y, &Result); #else // Perform the unsigned addition. - using U = typename std::make_unsigned::type; + using U = std::make_unsigned_t; const U UX = static_cast(X); const U UY = static_cast(Y); const U UResult = UX - UY; @@ -922,14 +917,12 @@ SubOverflow(T X, T Y, T &Result) { #endif } - /// Multiply two signed integers, computing the two's complement truncated /// result, returning true if an overflow ocurred. template -typename std::enable_if::value, T>::type -MulOverflow(T X, T Y, T &Result) { +std::enable_if_t::value, T> MulOverflow(T X, T Y, T &Result) { // Perform the unsigned multiplication on absolute values. - using U = typename std::make_unsigned::type; + using U = std::make_unsigned_t; const U UX = X < 0 ? (0 - static_cast(X)) : static_cast(X); const U UY = Y < 0 ? (0 - static_cast(Y)) : static_cast(Y); const U UResult = UX * UY; diff --git a/llvm/include/llvm/Support/SwapByteOrder.h b/llvm/include/llvm/Support/SwapByteOrder.h index 6cec87006c02..700ede7eb589 100644 --- a/llvm/include/llvm/Support/SwapByteOrder.h +++ b/llvm/include/llvm/Support/SwapByteOrder.h @@ -143,10 +143,9 @@ inline double getSwappedBytes(double C) { } template -inline typename std::enable_if::value, T>::type -getSwappedBytes(T C) { +inline std::enable_if_t::value, T> getSwappedBytes(T C) { return static_cast( - getSwappedBytes(static_cast::type>(C))); + getSwappedBytes(static_cast>(C))); } template diff --git a/llvm/include/llvm/Support/TaskQueue.h b/llvm/include/llvm/Support/TaskQueue.h index df2ffdee2cc2..4ceb056391af 100644 --- a/llvm/include/llvm/Support/TaskQueue.h +++ b/llvm/include/llvm/Support/TaskQueue.h @@ -38,7 +38,7 @@ class TaskQueue { // type-specialized domain (before type erasure) and then erase this into a // std::function. template struct Task { - using ResultTy = typename std::result_of::type; + using ResultTy = std::result_of_t; explicit Task(Callable C, TaskQueue &Parent) : C(std::move(C)), P(std::make_shared>()), Parent(&Parent) {} @@ -78,13 +78,13 @@ public: /// used to wait for the task (and all previous tasks that have not yet /// completed) to finish. template - std::future::type> async(Callable &&C) { + std::future> async(Callable &&C) { #if !LLVM_ENABLE_THREADS static_assert(false, "TaskQueue requires building with LLVM_ENABLE_THREADS!"); #endif Task T{std::move(C), *this}; - using ResultTy = typename std::result_of::type; + using ResultTy = std::result_of_t; std::future F = T.P->get_future(); { std::lock_guard Lock(QueueLock); diff --git a/llvm/include/llvm/Support/TrailingObjects.h b/llvm/include/llvm/Support/TrailingObjects.h index 49be89613c43..0d9c4503aa9b 100644 --- a/llvm/include/llvm/Support/TrailingObjects.h +++ b/llvm/include/llvm/Support/TrailingObjects.h @@ -326,8 +326,8 @@ public: /// used in the class; they are supplied here redundantly only so /// that it's clear what the counts are counting in callers. template - static constexpr typename std::enable_if< - std::is_same, Foo>::value, size_t>::type + static constexpr std::enable_if_t< + std::is_same, Foo>::value, size_t> additionalSizeToAlloc(typename trailing_objects_internal::ExtractSecondType< TrailingTys, size_t>::type... Counts) { return ParentType::additionalSizeToAllocImpl(0, Counts...); @@ -338,8 +338,8 @@ public: /// additionalSizeToAlloc, except it *does* include the size of the base /// object. template - static constexpr typename std::enable_if< - std::is_same, Foo>::value, size_t>::type + static constexpr std::enable_if_t< + std::is_same, Foo>::value, size_t> totalSizeToAlloc(typename trailing_objects_internal::ExtractSecondType< TrailingTys, size_t>::type... Counts) { return sizeof(BaseTy) + ParentType::additionalSizeToAllocImpl(0, Counts...); diff --git a/llvm/include/llvm/Support/YAMLTraits.h b/llvm/include/llvm/Support/YAMLTraits.h index 757dc8ea191a..316a6ad5d094 100644 --- a/llvm/include/llvm/Support/YAMLTraits.h +++ b/llvm/include/llvm/Support/YAMLTraits.h @@ -868,7 +868,7 @@ public: } template - typename std::enable_if::value, void>::type + std::enable_if_t::value, void> mapOptionalWithContext(const char *Key, T &Val, Context &Ctx) { // omit key/value instead of outputting empty sequence if (this->canElideEmptySequence() && !(Val.begin() != Val.end())) @@ -883,7 +883,7 @@ public: } template - typename std::enable_if::value, void>::type + std::enable_if_t::value, void> mapOptionalWithContext(const char *Key, T &Val, Context &Ctx) { this->processKey(Key, Val, false, Ctx); } @@ -965,7 +965,7 @@ template void doMapping(IO &io, T &Val, EmptyContext &Ctx) { } // end namespace detail template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { io.beginEnumScalar(); ScalarEnumerationTraits::enumeration(io, Val); @@ -973,7 +973,7 @@ yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { bool DoClear; if ( io.beginBitSetScalar(DoClear) ) { @@ -985,8 +985,8 @@ yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { } template -typename std::enable_if::value, void>::type -yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, + EmptyContext &Ctx) { if ( io.outputting() ) { std::string Storage; raw_string_ostream Buffer(Storage); @@ -1005,7 +1005,7 @@ yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &YamlIO, T &Val, bool, EmptyContext &Ctx) { if (YamlIO.outputting()) { std::string Storage; @@ -1024,7 +1024,7 @@ yamlize(IO &YamlIO, T &Val, bool, EmptyContext &Ctx) { } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { if (io.outputting()) { std::string ScalarStorage, TagStorage; @@ -1049,7 +1049,7 @@ yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, Context &Ctx) { if (has_FlowTraits>::value) io.beginFlowMapping(); @@ -1075,7 +1075,7 @@ yamlize(IO &io, T &Val, bool, Context &Ctx) { } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, Context &Ctx) { if (has_FlowTraits>::value) { io.beginFlowMapping(); @@ -1089,7 +1089,7 @@ yamlize(IO &io, T &Val, bool, Context &Ctx) { } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { if ( io.outputting() ) { io.beginMapping(); @@ -1104,7 +1104,7 @@ yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { switch (io.outputting() ? PolymorphicTraits::getKind(Val) : io.getNodeKind()) { @@ -1118,13 +1118,13 @@ yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Val, bool, EmptyContext &Ctx) { char missing_yaml_trait_for_type[sizeof(MissingTrait)]; } template -typename std::enable_if::value, void>::type +std::enable_if_t::value, void> yamlize(IO &io, T &Seq, bool, Context &Ctx) { if ( has_FlowTraits< SequenceTraits>::value ) { unsigned incnt = io.beginFlowSequence(); @@ -1247,10 +1247,9 @@ struct ScalarTraits { // type. This way endian aware types are supported whenever the traits are // defined for the underlying type. template -struct ScalarTraits< - support::detail::packed_endian_specific_integral, - typename std::enable_if::value>::type> { +struct ScalarTraits, + std::enable_if_t::value>> { using endian_type = support::detail::packed_endian_specific_integral; @@ -1275,8 +1274,7 @@ template struct ScalarEnumerationTraits< support::detail::packed_endian_specific_integral, - typename std::enable_if< - has_ScalarEnumerationTraits::value>::type> { + std::enable_if_t::value>> { using endian_type = support::detail::packed_endian_specific_integral; @@ -1292,7 +1290,7 @@ template struct ScalarBitSetTraits< support::detail::packed_endian_specific_integral, - typename std::enable_if::value>::type> { + std::enable_if_t::value>> { using endian_type = support::detail::packed_endian_specific_integral; @@ -1688,8 +1686,7 @@ struct ScalarTraits { // Define non-member operator>> so that Input can stream in a document list. template -inline -typename std::enable_if::value, Input &>::type +inline std::enable_if_t::value, Input &> operator>>(Input &yin, T &docList) { int i = 0; EmptyContext Ctx; @@ -1705,8 +1702,7 @@ operator>>(Input &yin, T &docList) { // Define non-member operator>> so that Input can stream in a map as a document. template -inline typename std::enable_if::value, - Input &>::type +inline std::enable_if_t::value, Input &> operator>>(Input &yin, T &docMap) { EmptyContext Ctx; yin.setCurrentDocument(); @@ -1717,8 +1713,7 @@ operator>>(Input &yin, T &docMap) { // Define non-member operator>> so that Input can stream in a sequence as // a document. template -inline -typename std::enable_if::value, Input &>::type +inline std::enable_if_t::value, Input &> operator>>(Input &yin, T &docSeq) { EmptyContext Ctx; if (yin.setCurrentDocument()) @@ -1728,8 +1723,7 @@ operator>>(Input &yin, T &docSeq) { // Define non-member operator>> so that Input can stream in a block scalar. template -inline -typename std::enable_if::value, Input &>::type +inline std::enable_if_t::value, Input &> operator>>(Input &In, T &Val) { EmptyContext Ctx; if (In.setCurrentDocument()) @@ -1739,8 +1733,7 @@ operator>>(Input &In, T &Val) { // Define non-member operator>> so that Input can stream in a string map. template -inline -typename std::enable_if::value, Input &>::type +inline std::enable_if_t::value, Input &> operator>>(Input &In, T &Val) { EmptyContext Ctx; if (In.setCurrentDocument()) @@ -1750,7 +1743,7 @@ operator>>(Input &In, T &Val) { // Define non-member operator>> so that Input can stream in a polymorphic type. template -inline typename std::enable_if::value, Input &>::type +inline std::enable_if_t::value, Input &> operator>>(Input &In, T &Val) { EmptyContext Ctx; if (In.setCurrentDocument()) @@ -1760,8 +1753,7 @@ operator>>(Input &In, T &Val) { // Provide better error message about types missing a trait specialization template -inline typename std::enable_if::value, - Input &>::type +inline std::enable_if_t::value, Input &> operator>>(Input &yin, T &docSeq) { char missing_yaml_trait_for_type[sizeof(MissingTrait)]; return yin; @@ -1769,8 +1761,7 @@ operator>>(Input &yin, T &docSeq) { // Define non-member operator<< so that Output can stream out document list. template -inline -typename std::enable_if::value, Output &>::type +inline std::enable_if_t::value, Output &> operator<<(Output &yout, T &docList) { EmptyContext Ctx; yout.beginDocuments(); @@ -1788,8 +1779,7 @@ operator<<(Output &yout, T &docList) { // Define non-member operator<< so that Output can stream out a map. template -inline typename std::enable_if::value, - Output &>::type +inline std::enable_if_t::value, Output &> operator<<(Output &yout, T &map) { EmptyContext Ctx; yout.beginDocuments(); @@ -1803,8 +1793,7 @@ operator<<(Output &yout, T &map) { // Define non-member operator<< so that Output can stream out a sequence. template -inline -typename std::enable_if::value, Output &>::type +inline std::enable_if_t::value, Output &> operator<<(Output &yout, T &seq) { EmptyContext Ctx; yout.beginDocuments(); @@ -1818,8 +1807,7 @@ operator<<(Output &yout, T &seq) { // Define non-member operator<< so that Output can stream out a block scalar. template -inline -typename std::enable_if::value, Output &>::type +inline std::enable_if_t::value, Output &> operator<<(Output &Out, T &Val) { EmptyContext Ctx; Out.beginDocuments(); @@ -1833,8 +1821,7 @@ operator<<(Output &Out, T &Val) { // Define non-member operator<< so that Output can stream out a string map. template -inline -typename std::enable_if::value, Output &>::type +inline std::enable_if_t::value, Output &> operator<<(Output &Out, T &Val) { EmptyContext Ctx; Out.beginDocuments(); @@ -1849,7 +1836,7 @@ operator<<(Output &Out, T &Val) { // Define non-member operator<< so that Output can stream out a polymorphic // type. template -inline typename std::enable_if::value, Output &>::type +inline std::enable_if_t::value, Output &> operator<<(Output &Out, T &Val) { EmptyContext Ctx; Out.beginDocuments(); @@ -1866,8 +1853,7 @@ operator<<(Output &Out, T &Val) { // Provide better error message about types missing a trait specialization template -inline typename std::enable_if::value, - Output &>::type +inline std::enable_if_t::value, Output &> operator<<(Output &yout, T &seq) { char missing_yaml_trait_for_type[sizeof(MissingTrait)]; return yout; @@ -1898,25 +1884,25 @@ template struct CheckIsBool { static const bool value = true; }; // If T has SequenceElementTraits, then vector and SmallVector have // SequenceTraits that do the obvious thing. template -struct SequenceTraits, - typename std::enable_if::flow>::value>::type> +struct SequenceTraits< + std::vector, + std::enable_if_t::flow>::value>> : SequenceTraitsImpl, SequenceElementTraits::flow> {}; template -struct SequenceTraits, - typename std::enable_if::flow>::value>::type> +struct SequenceTraits< + SmallVector, + std::enable_if_t::flow>::value>> : SequenceTraitsImpl, SequenceElementTraits::flow> {}; template -struct SequenceTraits, - typename std::enable_if::flow>::value>::type> +struct SequenceTraits< + SmallVectorImpl, + std::enable_if_t::flow>::value>> : SequenceTraitsImpl, SequenceElementTraits::flow> {}; // Sequences of fundamental types use flow formatting. template -struct SequenceElementTraits< - T, typename std::enable_if::value>::type> { +struct SequenceElementTraits::value>> { static const bool flow = true; }; diff --git a/llvm/include/llvm/Support/raw_ostream.h b/llvm/include/llvm/Support/raw_ostream.h index 12a4ff2540ee..30a1e62330df 100644 --- a/llvm/include/llvm/Support/raw_ostream.h +++ b/llvm/include/llvm/Support/raw_ostream.h @@ -358,9 +358,9 @@ private: /// Call the appropriate insertion operator, given an rvalue reference to a /// raw_ostream object and return a stream of the same type as the argument. template -typename std::enable_if::value && - std::is_base_of::value, - OStream &&>::type +std::enable_if_t::value && + std::is_base_of::value, + OStream &&> operator<<(OStream &&OS, const T &Value) { OS << Value; return std::move(OS); diff --git a/llvm/include/llvm/Support/type_traits.h b/llvm/include/llvm/Support/type_traits.h index b7d48e8e1ade..7b7d5d991f3f 100644 --- a/llvm/include/llvm/Support/type_traits.h +++ b/llvm/include/llvm/Support/type_traits.h @@ -28,7 +28,7 @@ namespace llvm { /// Also note that enum classes aren't implicitly convertible to integral types, /// the value may therefore need to be explicitly converted before being used. template class is_integral_or_enum { - using UnderlyingT = typename std::remove_reference::type; + using UnderlyingT = std::remove_reference_t; public: static const bool value = @@ -45,7 +45,7 @@ struct add_lvalue_reference_if_not_pointer { using type = T &; }; template struct add_lvalue_reference_if_not_pointer< - T, typename std::enable_if::value>::type> { + T, std::enable_if_t::value>> { using type = T; }; @@ -55,9 +55,8 @@ template struct add_const_past_pointer { using type = const T; }; template -struct add_const_past_pointer< - T, typename std::enable_if::value>::type> { - using type = const typename std::remove_pointer::type *; +struct add_const_past_pointer::value>> { + using type = const std::remove_pointer_t *; }; template @@ -65,8 +64,8 @@ struct const_pointer_or_const_ref { using type = const T &; }; template -struct const_pointer_or_const_ref< - T, typename std::enable_if::value>::type> { +struct const_pointer_or_const_ref::value>> { using type = typename add_const_past_pointer::type; }; diff --git a/llvm/include/llvm/XRay/Graph.h b/llvm/include/llvm/XRay/Graph.h index 004681512800..d368f7e724d8 100644 --- a/llvm/include/llvm/XRay/Graph.h +++ b/llvm/include/llvm/XRay/Graph.h @@ -126,14 +126,14 @@ private: /// set. template ::type> + typename T = + std::conditional_t> class NeighborEdgeIteratorT : public iterator_adaptor_base< NeighborEdgeIteratorT, BaseIt, typename std::iterator_traits::iterator_category, T> { using InternalEdgeMapT = - typename std::conditional::type; + std::conditional_t; friend class NeighborEdgeIteratorT; friend class NeighborEdgeIteratorT::type> + typename = std::enable_if> operator NeighborEdgeIteratorT() const { return NeighborEdgeIteratorT; using const_iterator = NeighborEdgeIteratorT; - using GraphT = typename std::conditional::type; + using GraphT = std::conditional_t; using InternalEdgeMapT = - typename std::conditional::type; + std::conditional_t; private: InternalEdgeMapT &M; @@ -272,10 +272,10 @@ public: /// the number of elements in the range and whether the range is empty. template class VertexView { public: - using iterator = typename std::conditional::type; + using iterator = + std::conditional_t; using const_iterator = ConstVertexIterator; - using GraphT = typename std::conditional::type; + using GraphT = std::conditional_t; private: GraphT &G; @@ -309,10 +309,10 @@ public: /// the number of elements in the range and whether the range is empty. template class EdgeView { public: - using iterator = typename std::conditional::type; + using iterator = + std::conditional_t; using const_iterator = ConstEdgeIterator; - using GraphT = typename std::conditional::type; + using GraphT = std::conditional_t; private: GraphT &G; diff --git a/llvm/lib/Demangle/ItaniumDemangle.cpp b/llvm/lib/Demangle/ItaniumDemangle.cpp index e112d5c5ec77..fad9b6b7b63b 100644 --- a/llvm/lib/Demangle/ItaniumDemangle.cpp +++ b/llvm/lib/Demangle/ItaniumDemangle.cpp @@ -107,13 +107,11 @@ struct DumpVisitor { // Overload used when T is exactly 'bool', not merely convertible to 'bool'. void print(bool B) { printStr(B ? "true" : "false"); } - template - typename std::enable_if::value>::type print(T N) { + template std::enable_if_t::value> print(T N) { fprintf(stderr, "%llu", (unsigned long long)N); } - template - typename std::enable_if::value>::type print(T N) { + template std::enable_if_t::value> print(T N) { fprintf(stderr, "%lld", (long long)N); } diff --git a/llvm/lib/Support/ItaniumManglingCanonicalizer.cpp b/llvm/lib/Support/ItaniumManglingCanonicalizer.cpp index bbc06d186fba..7594c74b83b2 100644 --- a/llvm/lib/Support/ItaniumManglingCanonicalizer.cpp +++ b/llvm/lib/Support/ItaniumManglingCanonicalizer.cpp @@ -30,9 +30,8 @@ struct FoldingSetNodeIDBuilder { void operator()(StringView Str) { ID.AddString(llvm::StringRef(Str.begin(), Str.size())); } - template - typename std::enable_if::value || - std::is_enum::value>::type + template + std::enable_if_t::value || std::is_enum::value> operator()(T V) { ID.AddInteger((unsigned long long)V); } diff --git a/llvm/lib/Support/NativeFormatting.cpp b/llvm/lib/Support/NativeFormatting.cpp index 3731e0c56359..9cd494908016 100644 --- a/llvm/lib/Support/NativeFormatting.cpp +++ b/llvm/lib/Support/NativeFormatting.cpp @@ -89,7 +89,7 @@ static void write_signed(raw_ostream &S, T N, size_t MinDigits, IntegerStyle Style) { static_assert(std::is_signed::value, "Value is not signed!"); - using UnsignedT = typename std::make_unsigned::type; + using UnsignedT = std::make_unsigned_t; if (N >= 0) { write_unsigned(S, static_cast(N), MinDigits, Style); diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index 55b09096bb95..fa3d64b4666d 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -757,8 +757,8 @@ public: return false; int64_t Val = MCE->getValue(); - int64_t SVal = typename std::make_signed::type(Val); - int64_t UVal = typename std::make_unsigned::type(Val); + int64_t SVal = std::make_signed_t(Val); + int64_t UVal = std::make_unsigned_t(Val); if (Val != SVal && Val != UVal) return false; @@ -854,8 +854,7 @@ public: if (!isShiftedImm() && (!isImm() || !isa(getImm()))) return DiagnosticPredicateTy::NoMatch; - bool IsByte = - std::is_same::type>::value; + bool IsByte = std::is_same>::value; if (auto ShiftedImm = getShiftedVal<8>()) if (!(IsByte && ShiftedImm->second) && AArch64_AM::isSVECpyImm(uint64_t(ShiftedImm->first) @@ -872,8 +871,7 @@ public: if (!isShiftedImm() && (!isImm() || !isa(getImm()))) return DiagnosticPredicateTy::NoMatch; - bool IsByte = - std::is_same::type>::value; + bool IsByte = std::is_same>::value; if (auto ShiftedImm = getShiftedVal<8>()) if (!(IsByte && ShiftedImm->second) && AArch64_AM::isSVEAddSubImm(ShiftedImm->first @@ -1610,7 +1608,7 @@ public: void addLogicalImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *MCE = cast(getImm()); - typename std::make_unsigned::type Val = MCE->getValue(); + std::make_unsigned_t Val = MCE->getValue(); uint64_t encoding = AArch64_AM::encodeLogicalImmediate(Val, sizeof(T) * 8); Inst.addOperand(MCOperand::createImm(encoding)); } @@ -1619,7 +1617,7 @@ public: void addLogicalImmNotOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *MCE = cast(getImm()); - typename std::make_unsigned::type Val = ~MCE->getValue(); + std::make_unsigned_t Val = ~MCE->getValue(); uint64_t encoding = AArch64_AM::encodeLogicalImmediate(Val, sizeof(T) * 8); Inst.addOperand(MCOperand::createImm(encoding)); } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h index 05a909f1780a..9814f7625853 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h @@ -763,10 +763,10 @@ static inline bool isSVECpyImm(int64_t Imm) { bool IsImm8 = int8_t(Imm) == Imm; bool IsImm16 = int16_t(Imm & ~0xff) == Imm; - if (std::is_same::type>::value) + if (std::is_same>::value) return IsImm8 || uint8_t(Imm) == Imm; - if (std::is_same::type>::value) + if (std::is_same>::value) return IsImm8 || IsImm16 || uint16_t(Imm & ~0xff) == Imm; return IsImm8 || IsImm16; @@ -775,8 +775,7 @@ static inline bool isSVECpyImm(int64_t Imm) { /// Returns true if Imm is valid for ADD/SUB. template static inline bool isSVEAddSubImm(int64_t Imm) { - bool IsInt8t = - std::is_same::type>::value; + bool IsInt8t = std::is_same>::value; return uint8_t(Imm) == Imm || (!IsInt8t && uint16_t(Imm & ~0xff) == Imm); } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index f0a2dd76710a..6a23cdae2083 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -1511,7 +1511,7 @@ void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum, template void AArch64InstPrinter::printImmSVE(T Value, raw_ostream &O) { - typename std::make_unsigned::type HexValue = Value; + std::make_unsigned_t HexValue = Value; if (getPrintImmHex()) O << '#' << formatHex((uint64_t)HexValue); @@ -1556,8 +1556,8 @@ template void AArch64InstPrinter::printSVELogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { - typedef typename std::make_signed::type SignedT; - typedef typename std::make_unsigned::type UnsignedT; + typedef std::make_signed_t SignedT; + typedef std::make_unsigned_t UnsignedT; uint64_t Val = MI->getOperand(OpNum).getImm(); UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64); diff --git a/llvm/lib/XRay/FDRTraceWriter.cpp b/llvm/lib/XRay/FDRTraceWriter.cpp index f50dc19b4be8..71c09bd4fce4 100644 --- a/llvm/lib/XRay/FDRTraceWriter.cpp +++ b/llvm/lib/XRay/FDRTraceWriter.cpp @@ -20,10 +20,9 @@ namespace { template struct IndexedWriter { template < class Tuple, - typename std::enable_if< - (Index < - std::tuple_size::type>::value), - int>::type = 0> + std::enable_if_t<(Index < + std::tuple_size>::value), + int> = 0> static size_t write(support::endian::Writer &OS, Tuple &&T) { OS.write(std::get(T)); return sizeof(std::get(T)) + IndexedWriter::write(OS, T); @@ -31,10 +30,9 @@ template struct IndexedWriter { template < class Tuple, - typename std::enable_if< - (Index >= - std::tuple_size::type>::value), - int>::type = 0> + std::enable_if_t<(Index >= + std::tuple_size>::value), + int> = 0> static size_t write(support::endian::Writer &OS, Tuple &&) { return 0; } diff --git a/llvm/tools/dsymutil/CFBundle.cpp b/llvm/tools/dsymutil/CFBundle.cpp index eb07287b63c6..0625afb18ab6 100644 --- a/llvm/tools/dsymutil/CFBundle.cpp +++ b/llvm/tools/dsymutil/CFBundle.cpp @@ -34,9 +34,8 @@ template struct CFDeleter { /// any valid pointer it owns unless that pointer is explicitly released using /// the release() member function. template -using CFReleaser = - std::unique_ptr::type, - CFDeleter::type>>; +using CFReleaser = std::unique_ptr, + CFDeleter>>; /// RAII wrapper around CFBundleRef. class CFString : public CFReleaser { diff --git a/llvm/tools/llvm-pdbutil/FormatUtil.h b/llvm/tools/llvm-pdbutil/FormatUtil.h index 19ce248f9a6f..1a006844e011 100644 --- a/llvm/tools/llvm-pdbutil/FormatUtil.h +++ b/llvm/tools/llvm-pdbutil/FormatUtil.h @@ -42,8 +42,7 @@ std::string truncateQuotedNameBack(StringRef Label, StringRef Name, return Ret; template std::string formatUnknownEnum(T Value) { - return formatv("unknown ({0})", - static_cast::type>(Value)) + return formatv("unknown ({0})", static_cast>(Value)) .str(); } diff --git a/llvm/tools/llvm-xray/trie-node.h b/llvm/tools/llvm-xray/trie-node.h index 47d4b8f1e78c..7bff81473b5d 100644 --- a/llvm/tools/llvm-xray/trie-node.h +++ b/llvm/tools/llvm-xray/trie-node.h @@ -48,7 +48,7 @@ template TrieNode * mergeTrieNodes(const TrieNode &Left, const TrieNode &Right, /*Non-deduced pointer type for nullptr compatibility*/ - typename std::remove_reference *>::type NewParent, + std::remove_reference_t *> NewParent, std::forward_list> &NodeStore, Callable &&MergeCallable) { llvm::function_ref MergeFn( diff --git a/llvm/unittests/ADT/DenseSetTest.cpp b/llvm/unittests/ADT/DenseSetTest.cpp index e6fe9ca3b318..b080aa7f0c65 100644 --- a/llvm/unittests/ADT/DenseSetTest.cpp +++ b/llvm/unittests/ADT/DenseSetTest.cpp @@ -52,7 +52,7 @@ protected: private: static T GetTestSet() { - typename std::remove_const::type Set; + std::remove_const_t Set; Set.insert(0); Set.insert(1); Set.insert(2); diff --git a/llvm/unittests/IR/PatternMatch.cpp b/llvm/unittests/IR/PatternMatch.cpp index c67e08788791..4cc72c8eeedb 100644 --- a/llvm/unittests/IR/PatternMatch.cpp +++ b/llvm/unittests/IR/PatternMatch.cpp @@ -1319,8 +1319,8 @@ TYPED_TEST_CASE(MutableConstTest, MutableConstTestTypes); TYPED_TEST(MutableConstTest, ICmp) { auto &IRB = PatternMatchTest::IRB; - typedef typename std::tuple_element<0, TypeParam>::type ValueType; - typedef typename std::tuple_element<1, TypeParam>::type InstructionType; + typedef std::tuple_element_t<0, TypeParam> ValueType; + typedef std::tuple_element_t<1, TypeParam> InstructionType; Value *L = IRB.getInt32(1); Value *R = IRB.getInt32(2); diff --git a/llvm/unittests/XRay/GraphTest.cpp b/llvm/unittests/XRay/GraphTest.cpp index 3c82d53492e8..52580b306826 100644 --- a/llvm/unittests/XRay/GraphTest.cpp +++ b/llvm/unittests/XRay/GraphTest.cpp @@ -34,7 +34,7 @@ protected: private: static T getTestGraph() { using std::make_pair; - typename std::remove_const::type G; + std::remove_const_t G; G.insert(make_pair(1u, VAttr({3u}))); G.insert(make_pair(2u, VAttr({5u}))); G.insert(make_pair(3u, VAttr({7u}))); diff --git a/llvm/utils/benchmark/include/benchmark/benchmark.h b/llvm/utils/benchmark/include/benchmark/benchmark.h index af935a6ef3e1..ab61c46e9386 100644 --- a/llvm/utils/benchmark/include/benchmark/benchmark.h +++ b/llvm/utils/benchmark/include/benchmark/benchmark.h @@ -990,8 +990,7 @@ inline internal::Benchmark* RegisterBenchmark(const char* name, #ifdef BENCHMARK_HAS_CXX11 template internal::Benchmark* RegisterBenchmark(const char* name, Lambda&& fn) { - using BenchType = - internal::LambdaBenchmark::type>; + using BenchType = internal::LambdaBenchmark>; return internal::RegisterBenchmarkInternal( ::new BenchType(name, std::forward(fn))); } diff --git a/llvm/utils/benchmark/src/sysinfo.cc b/llvm/utils/benchmark/src/sysinfo.cc index 01dd8a0317b0..04254bbed365 100644 --- a/llvm/utils/benchmark/src/sysinfo.cc +++ b/llvm/utils/benchmark/src/sysinfo.cc @@ -176,9 +176,8 @@ bool GetSysctl(std::string const& Name, std::string* Out) { return true; } -template ::value>::type> -bool GetSysctl(std::string const& Name, Tp* Out) { +template ::value>> +bool GetSysctl(std::string const &Name, Tp *Out) { *Out = 0; auto Buff = GetSysctlImp(Name); if (!Buff) return false; diff --git a/llvm/utils/unittest/googlemock/include/gmock/gmock-matchers.h b/llvm/utils/unittest/googlemock/include/gmock/gmock-matchers.h index 865cdc7da108..755dbb9cdedb 100644 --- a/llvm/utils/unittest/googlemock/include/gmock/gmock-matchers.h +++ b/llvm/utils/unittest/googlemock/include/gmock/gmock-matchers.h @@ -3118,8 +3118,9 @@ class ElementsAreMatcherImpl : public MatcherInterface { typedef typename View::const_reference StlContainerReference; typedef decltype(std::begin( std::declval())) StlContainerConstIterator; - typedef typename std::remove_reference())>::type Element; + typedef std::remove_reference_t())> + Element; // Constructs the matcher from a sequence of element values or // element matchers. @@ -3360,8 +3361,9 @@ class UnorderedElementsAreMatcherImpl typedef typename View::const_reference StlContainerReference; typedef decltype(std::begin( std::declval())) StlContainerConstIterator; - typedef typename std::remove_reference())>::type Element; + typedef std::remove_reference_t())> + Element; // Constructs the matcher from a sequence of element values or // element matchers. @@ -3470,8 +3472,9 @@ class UnorderedElementsAreMatcher { typedef typename View::const_reference StlContainerReference; typedef decltype(std::begin( std::declval())) StlContainerConstIterator; - typedef typename std::remove_reference())>::type Element; + typedef std::remove_reference_t())> + Element; typedef ::std::vector > MatcherVec; MatcherVec matchers; matchers.reserve(::testing::tuple_size::value); @@ -3499,8 +3502,9 @@ class ElementsAreMatcher { typedef typename View::const_reference StlContainerReference; typedef decltype(std::begin( std::declval())) StlContainerConstIterator; - typedef typename std::remove_reference())>::type Element; + typedef std::remove_reference_t())> + Element; typedef ::std::vector > MatcherVec; MatcherVec matchers; matchers.reserve(::testing::tuple_size::value); -- GitLab From b2c44de956cca22efa374cfb587912b38c41ed67 Mon Sep 17 00:00:00 2001 From: Derek Schuff Date: Tue, 11 Feb 2020 15:13:40 -0800 Subject: [PATCH 091/142] [llvm-objcopy][WebAssembly] Add dump/add/remove-section support Add support for adding, removing, and dumping wasm sections to objcopy Differential Revision: https://reviews.llvm.org/D70970 --- .../tools/llvm-objcopy/wasm/add-section.test | 83 +++++++++++++++++++ .../tools/llvm-objcopy/wasm/dump-section.test | 38 +++++++++ .../llvm-objcopy/wasm/remove-section.test | 26 ++++++ llvm/tools/llvm-objcopy/CMakeLists.txt | 1 + llvm/tools/llvm-objcopy/wasm/Object.cpp | 36 ++++++++ llvm/tools/llvm-objcopy/wasm/Object.h | 8 ++ llvm/tools/llvm-objcopy/wasm/WasmObjcopy.cpp | 59 +++++++++++-- .../llvm/tools/llvm-objcopy/BUILD.gn | 1 + 8 files changed, 247 insertions(+), 5 deletions(-) create mode 100644 llvm/test/tools/llvm-objcopy/wasm/add-section.test create mode 100644 llvm/test/tools/llvm-objcopy/wasm/dump-section.test create mode 100644 llvm/test/tools/llvm-objcopy/wasm/remove-section.test create mode 100644 llvm/tools/llvm-objcopy/wasm/Object.cpp diff --git a/llvm/test/tools/llvm-objcopy/wasm/add-section.test b/llvm/test/tools/llvm-objcopy/wasm/add-section.test new file mode 100644 index 000000000000..2f32eaca0ac4 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/wasm/add-section.test @@ -0,0 +1,83 @@ +## Test --add-section. This test dumps and removes the section first and checks +## that adding it back doesn't change the result. +# RUN: yaml2obj %s -o %t +# RUN: llvm-objcopy --dump-section=producers=%t.sec --remove-section=producers %t %t2 +# RUN: llvm-objcopy --add-section=producers=%t.sec %t2 %t3 +# RUN: obj2yaml %t3 | FileCheck %s + +## Check that the producers section has been added back unchanged. +# CHECK: Name: producers +# CHECK-NEXT: Tools: +# CHECK-NEXT: - Name: clang +# CHECK-NEXT: Version: 9.0.0 + +# Check that the section is replaced with new content in one invocation. +# RUN: echo "123" > %t4 +# RUN: llvm-objcopy --remove-section=foo --add-section=foo=%t4 %t %t5 +# RUN: obj2yaml %t5 | FileCheck %s --check-prefix=REPLACE + +# REPLACE: - Type: CUSTOM +# REPLACE: Name: foo +# REPLACE: Payload: 3132330A + +--- !WASM +FileHeader: + Version: 0x00000001 +Sections: + - Type: TYPE + Signatures: + - Index: 0 + ParamTypes: + - I32 + ReturnTypes: + - F32 + - Index: 1 + ParamTypes: + - I32 + - I64 + ReturnTypes: [] + - Type: FUNCTION + FunctionTypes: + - 0 + - 1 + - Type: CODE + Relocations: + - Type: R_WASM_TABLE_INDEX_SLEB + Index: 0 + Offset: 0x00000000 + - Type: R_WASM_FUNCTION_INDEX_LEB + Index: 1 + Offset: 0x0000000 + Functions: + - Index: 0 + Locals: + - Type: I32 + Count: 3 + Body: 010101010B + - Index: 1 + Locals: + - Type: I32 + Count: 1 + Body: 010101010B + - Type: CUSTOM + Name: linking + Version: 2 + SymbolTable: + - Index: 0 + Kind: FUNCTION + Name: func1 + Flags: [ ] + Function: 0 + - Index: 1 + Kind: FUNCTION + Name: func2 + Flags: [ ] + Function: 1 + - Type: CUSTOM + Name: producers + Tools: + - Name: clang + Version: 9.0.0 + - Type: CUSTOM + Name: foo + Payload: ABC123 diff --git a/llvm/test/tools/llvm-objcopy/wasm/dump-section.test b/llvm/test/tools/llvm-objcopy/wasm/dump-section.test new file mode 100644 index 000000000000..19620f7a3d33 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/wasm/dump-section.test @@ -0,0 +1,38 @@ +## Test the contents of a custom section dumped from a binary. +# RUN: yaml2obj %s -o %t +# RUN: llvm-objcopy --dump-section=producers=%t.sec %t +# RUN: od -t x1 %t.sec | FileCheck %s + +# RUN: not llvm-objcopy --dump-section=nonexistent=%t.sec %t 2>&1 | FileCheck --check-prefix=NONEXISTENT %s +# RUN: not llvm-objcopy --dump-section=producers=%t.dir/bar %t 2>&1 | FileCheck --check-prefix=DIROUT %s + +## Raw contents of the producers section. +# CHECK: 0000000 01 0c 70 72 6f 63 65 73 73 65 64 2d 62 79 01 05 +# CHECK: 0000020 63 6c 61 6e 67 05 39 2e 30 2e 30 + +# NONEXISTENT: section 'nonexistent' not found +# DIROUT: error: {{.*}}/bar': {{[nN]}}o such file or directory + +## Check that dumping and removing a section works in the same invocation +# RUN: llvm-objcopy --dump-section=producers=%t.sec --remove-section=producers %t %t2 +# RUN: od -t x1 %t.sec | FileCheck %s +# RUN: obj2yaml %t2 | FileCheck --check-prefix=REMOVED %s + +# REMOVED-NOT: producers + +--- !WASM +FileHeader: + Version: 0x00000001 +Sections: + - Type: TYPE + Signatures: + - Index: 0 + ParamTypes: + - I32 + ReturnTypes: + - F32 + - Type: CUSTOM + Name: producers + Tools: + - Name: clang + Version: 9.0.0 diff --git a/llvm/test/tools/llvm-objcopy/wasm/remove-section.test b/llvm/test/tools/llvm-objcopy/wasm/remove-section.test new file mode 100644 index 000000000000..ad4474f9c195 --- /dev/null +++ b/llvm/test/tools/llvm-objcopy/wasm/remove-section.test @@ -0,0 +1,26 @@ +## Test the --remove-section flag. +# RUN: yaml2obj %s -o %t +# RUN: llvm-objcopy -R producers %t %t2 +# RUN: obj2yaml %t2 | FileCheck --implicit-check-not=producers %s +## Check that the producers section has been removed, but not the type section. +# CHECK: TYPE + +## Requests to remove nonexistent sections are silently ignored. +# RUN: llvm-objcopy --remove-section=nonexistent=%t.sec %t 2&>1 | count 0 + +--- !WASM +FileHeader: + Version: 0x00000001 +Sections: + - Type: TYPE + Signatures: + - Index: 0 + ParamTypes: + - I32 + ReturnTypes: + - F32 + - Type: CUSTOM + Name: producers + Tools: + - Name: clang + Version: 9.0.0 diff --git a/llvm/tools/llvm-objcopy/CMakeLists.txt b/llvm/tools/llvm-objcopy/CMakeLists.txt index b3706bc69177..6aa5197243dc 100644 --- a/llvm/tools/llvm-objcopy/CMakeLists.txt +++ b/llvm/tools/llvm-objcopy/CMakeLists.txt @@ -33,6 +33,7 @@ add_llvm_tool(llvm-objcopy MachO/MachOWriter.cpp MachO/MachOLayoutBuilder.cpp MachO/Object.cpp + wasm/Object.cpp wasm/Reader.cpp wasm/Writer.cpp wasm/WasmObjcopy.cpp diff --git a/llvm/tools/llvm-objcopy/wasm/Object.cpp b/llvm/tools/llvm-objcopy/wasm/Object.cpp new file mode 100644 index 000000000000..0c416483663f --- /dev/null +++ b/llvm/tools/llvm-objcopy/wasm/Object.cpp @@ -0,0 +1,36 @@ +//===- Object.cpp ---------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Object.h" + +#include "llvm/Support/LEB128.h" +#include "llvm/Support/raw_ostream.h" + +namespace llvm { +namespace objcopy { +namespace wasm { + +using namespace object; +using namespace llvm::wasm; + +void Object::addSectionWithOwnedContents( + Section NewSection, std::unique_ptr &&Content) { + Sections.push_back(NewSection); + OwnedContents.emplace_back(std::move(Content)); +} + +void Object::removeSections(function_ref ToRemove) { + // TODO: remove reloc sections for the removed section, handle symbols, etc. + Sections.erase( + std::remove_if(std::begin(Sections), std::end(Sections), ToRemove), + std::end(Sections)); +} + +} // end namespace wasm +} // end namespace objcopy +} // end namespace llvm diff --git a/llvm/tools/llvm-objcopy/wasm/Object.h b/llvm/tools/llvm-objcopy/wasm/Object.h index 78a43be21d47..9db91c41e2e2 100644 --- a/llvm/tools/llvm-objcopy/wasm/Object.h +++ b/llvm/tools/llvm-objcopy/wasm/Object.h @@ -12,6 +12,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/StringRef.h" #include "llvm/Object/Wasm.h" +#include "llvm/Support/MemoryBuffer.h" #include namespace llvm { @@ -30,6 +31,13 @@ struct Object { llvm::wasm::WasmObjectHeader Header; // For now don't discriminate between kinds of sections. std::vector
Sections; + + void addSectionWithOwnedContents(Section NewSection, + std::unique_ptr &&Content); + void removeSections(function_ref ToRemove); + +private: + std::vector> OwnedContents; }; } // end namespace wasm diff --git a/llvm/tools/llvm-objcopy/wasm/WasmObjcopy.cpp b/llvm/tools/llvm-objcopy/wasm/WasmObjcopy.cpp index 41816a0b08ad..20781cef2d33 100644 --- a/llvm/tools/llvm-objcopy/wasm/WasmObjcopy.cpp +++ b/llvm/tools/llvm-objcopy/wasm/WasmObjcopy.cpp @@ -21,7 +21,58 @@ namespace wasm { using namespace object; +static Error dumpSectionToFile(StringRef SecName, StringRef Filename, + Object &Obj) { + for (const Section &Sec : Obj.Sections) { + if (Sec.Name == SecName) { + ArrayRef Contents = Sec.Contents; + Expected> BufferOrErr = + FileOutputBuffer::create(Filename, Contents.size()); + if (!BufferOrErr) + return BufferOrErr.takeError(); + std::unique_ptr Buf = std::move(*BufferOrErr); + std::copy(Contents.begin(), Contents.end(), Buf->getBufferStart()); + if (Error E = Buf->commit()) + return E; + return Error::success(); + } + } + return createStringError(errc::invalid_argument, "section '%s' not found", + SecName.str().c_str()); +} static Error handleArgs(const CopyConfig &Config, Object &Obj) { + // Only support AddSection, DumpSection, RemoveSection for now. + for (StringRef Flag : Config.DumpSection) { + StringRef SecName; + StringRef FileName; + std::tie(SecName, FileName) = Flag.split("="); + if (Error E = dumpSectionToFile(SecName, FileName, Obj)) + return createFileError(FileName, std::move(E)); + } + + Obj.removeSections([&Config](const Section &Sec) { + if (Config.ToRemove.matches(Sec.Name)) + return true; + return false; + }); + + for (StringRef Flag : Config.AddSection) { + StringRef SecName, FileName; + std::tie(SecName, FileName) = Flag.split("="); + ErrorOr> BufOrErr = + MemoryBuffer::getFile(FileName); + if (!BufOrErr) + return createFileError(FileName, errorCodeToError(BufOrErr.getError())); + Section Sec; + Sec.SectionType = llvm::wasm::WASM_SEC_CUSTOM; + Sec.Name = SecName; + std::unique_ptr Buf = std::move(*BufOrErr); + Sec.Contents = makeArrayRef( + reinterpret_cast(Buf->getBufferStart()), + Buf->getBufferSize()); + Obj.addSectionWithOwnedContents(Sec, std::move(Buf)); + } + if (!Config.AddGnuDebugLink.empty() || !Config.BuildIdLinkDir.empty() || Config.BuildIdLinkInput || Config.BuildIdLinkOutput || Config.ExtractPartition || !Config.SplitDWO.empty() || @@ -34,12 +85,10 @@ static Error handleArgs(const CopyConfig &Config, Object &Obj) { !Config.UnneededSymbolsToRemove.empty() || !Config.SymbolsToWeaken.empty() || !Config.SymbolsToKeepGlobal.empty() || !Config.SectionsToRename.empty() || !Config.SetSectionAlignment.empty() || - !Config.SetSectionFlags.empty() || !Config.SymbolsToRename.empty() || - !Config.ToRemove.empty() || !Config.DumpSection.empty() || - !Config.AddSection.empty()) { + !Config.SetSectionFlags.empty() || !Config.SymbolsToRename.empty()) { return createStringError( llvm::errc::invalid_argument, - "no flags are supported yet, only basic copying is allowed"); + "only add-section, dump-section, and remove-section are supported"); } return Error::success(); } @@ -53,7 +102,7 @@ Error executeObjcopyOnBinary(const CopyConfig &Config, Object *Obj = ObjOrErr->get(); assert(Obj && "Unable to deserialize Wasm object"); if (Error E = handleArgs(Config, *Obj)) - return createFileError(Config.InputFilename, std::move(E)); + return E; Writer TheWriter(*Obj, Out); if (Error E = TheWriter.write()) return createFileError(Config.OutputFilename, std::move(E)); diff --git a/llvm/utils/gn/secondary/llvm/tools/llvm-objcopy/BUILD.gn b/llvm/utils/gn/secondary/llvm/tools/llvm-objcopy/BUILD.gn index a186ab941310..c9bc3947456e 100644 --- a/llvm/utils/gn/secondary/llvm/tools/llvm-objcopy/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/tools/llvm-objcopy/BUILD.gn @@ -72,6 +72,7 @@ executable("llvm-objcopy") { "MachO/MachOWriter.cpp", "MachO/Object.cpp", "llvm-objcopy.cpp", + "wasm/Object.cpp", "wasm/Reader.cpp", "wasm/WasmObjcopy.cpp", "wasm/Writer.cpp", -- GitLab From 86f9117d476bcef2f5e0eabae4781e99877ce7b5 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 10 Feb 2020 10:30:34 -0500 Subject: [PATCH 092/142] AMDGPU: Don't report 2-byte alignment as fast This is apparently worse than 1-byte alignment. This does not attempt to decompose 2-byte aligned wide stores, but will stop trying to produce them. Also fix bug in LoadStoreVectorizer which was decreasing the alignment and vectorizing stack accesses. It was assuming a stack object was an alloca that could have its base alignment changed, which is not true if the pointer is derived from a function argument. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 +- .../Vectorize/LoadStoreVectorizer.cpp | 12 +- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 13 +- .../fast-unaligned-load-store.global.ll | 328 ++++++++++++++++++ .../fast-unaligned-load-store.private.ll | 245 +++++++++++++ .../CodeGen/AMDGPU/unaligned-load-store.ll | 21 ++ .../AMDGPU/adjust-alloca-alignment.ll | 51 +++ .../AMDGPU/merge-stores-private.ll | 24 +- .../AMDGPU/merge-stores.ll | 26 +- 9 files changed, 695 insertions(+), 29 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll create mode 100644 llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index b6966e66c36b..55003521b8b2 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1251,9 +1251,11 @@ bool SITargetLowering::allowsMisalignedMemoryAccessesImpl( // If we have an uniform constant load, it still requires using a slow // buffer instruction if unaligned. if (IsFast) { + // Accesses can really be issued as 1-byte aligned or 4-byte aligned, so + // 2-byte alignment is worse than 1 unless doing a 2-byte accesss. *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS || AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ? - (Align % 4 == 0) : true; + Align >= 4 : Align != 2; } return true; diff --git a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp index 3b22f3082c33..8ab03c34335d 100644 --- a/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp @@ -1028,8 +1028,10 @@ bool Vectorizer::vectorizeStoreChain( unsigned NewAlign = getOrEnforceKnownAlignment(S0->getPointerOperand(), StackAdjustedAlignment, DL, S0, nullptr, &DT); - if (NewAlign != 0) + if (NewAlign >= Alignment.value()) Alignment = Align(NewAlign); + else + return false; } if (!TTI.isLegalToVectorizeStoreChain(SzInBytes, Alignment.value(), AS)) { @@ -1168,8 +1170,12 @@ bool Vectorizer::vectorizeLoadChain( vectorizeLoadChain(Chains.second, InstructionsProcessed); } - Alignment = getOrEnforceKnownAlignment( - L0->getPointerOperand(), StackAdjustedAlignment, DL, L0, nullptr, &DT); + unsigned NewAlign = getOrEnforceKnownAlignment( + L0->getPointerOperand(), StackAdjustedAlignment, DL, L0, nullptr, &DT); + if (NewAlign >= Alignment) + Alignment = NewAlign; + else + return false; } if (!TTI.isLegalToVectorizeLoadChain(SzInBytes, Alignment, AS)) { diff --git a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll index 9ec8b7573ceb..0df32537808a 100644 --- a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll +++ b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll @@ -199,14 +199,17 @@ define amdgpu_kernel void @vload2_private(i16 addrspace(1)* nocapture readonly % ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v3, s5 -; GCN-NEXT: global_load_ushort v4, v[2:3], off offset:4 -; GCN-NEXT: global_load_dword v2, v[2:3], off +; GCN-NEXT: global_load_ushort v4, v[2:3], off ; GCN-NEXT: v_mov_b32_e32 v0, s6 ; GCN-NEXT: v_mov_b32_e32 v1, s7 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: buffer_store_short v2, off, s[0:3], s9 offset:4 -; GCN-NEXT: buffer_store_short_d16_hi v2, off, s[0:3], s9 offset:6 -; GCN-NEXT: buffer_store_short v4, off, s[0:3], s9 offset:8 +; GCN-NEXT: buffer_store_short v4, off, s[0:3], s9 offset:4 +; GCN-NEXT: global_load_ushort v4, v[2:3], off offset:2 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_short v4, off, s[0:3], s9 offset:6 +; GCN-NEXT: global_load_ushort v2, v[2:3], off offset:4 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: buffer_store_short v2, off, s[0:3], s9 offset:8 ; GCN-NEXT: buffer_load_ushort v2, off, s[0:3], s9 offset:4 ; GCN-NEXT: buffer_load_ushort v4, off, s[0:3], s9 offset:6 ; GCN-NEXT: s_waitcnt vmcnt(1) diff --git a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll new file mode 100644 index 000000000000..34f8706ac66c --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll @@ -0,0 +1,328 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=-unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7-ALIGNED %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX7-UNALIGNED %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+unaligned-buffer-access < %s | FileCheck -check-prefixes=GCN,GFX9 %s + +; Should not merge this to a dword load +define i32 @global_load_2xi16_align2(i16 addrspace(1)* %p) #0 { +; GFX7-ALIGNED-LABEL: global_load_2xi16_align2: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v2, vcc, 2, v0 +; GFX7-ALIGNED-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc +; GFX7-ALIGNED-NEXT: flat_load_ushort v0, v[0:1] +; GFX7-ALIGNED-NEXT: flat_load_ushort v1, v[2:3] +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-ALIGNED-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX7-ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-UNALIGNED-LABEL: global_load_2xi16_align2: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: v_add_i32_e32 v2, vcc, 2, v0 +; GFX7-UNALIGNED-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc +; GFX7-UNALIGNED-NEXT: flat_load_ushort v0, v[0:1] +; GFX7-UNALIGNED-NEXT: flat_load_ushort v1, v[2:3] +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-UNALIGNED-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: global_load_2xi16_align2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-NEXT: global_load_ushort v0, v[0:1], off offset:2 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v2 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %gep.p = getelementptr i16, i16 addrspace(1)* %p, i64 1 + %p.0 = load i16, i16 addrspace(1)* %p, align 2 + %p.1 = load i16, i16 addrspace(1)* %gep.p, align 2 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + +; Should not merge this to a dword store +define amdgpu_kernel void @global_store_2xi16_align2(i16 addrspace(1)* %p, i16 addrspace(1)* %r) #0 { +; GFX7-ALIGNED-LABEL: global_store_2xi16_align2: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, 1 +; GFX7-ALIGNED-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-ALIGNED-NEXT: s_add_u32 s2, s0, 2 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-ALIGNED-NEXT: flat_store_short v[0:1], v2 +; GFX7-ALIGNED-NEXT: s_addc_u32 s3, s1, 0 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s2 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, 2 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s3 +; GFX7-ALIGNED-NEXT: flat_store_short v[0:1], v2 +; GFX7-ALIGNED-NEXT: s_endpgm +; +; GFX7-UNALIGNED-LABEL: global_store_2xi16_align2: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v2, 1 +; GFX7-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-UNALIGNED-NEXT: s_add_u32 s2, s0, 2 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-UNALIGNED-NEXT: flat_store_short v[0:1], v2 +; GFX7-UNALIGNED-NEXT: s_addc_u32 s3, s1, 0 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v0, s2 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v2, 2 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v1, s3 +; GFX7-UNALIGNED-NEXT: flat_store_short v[0:1], v2 +; GFX7-UNALIGNED-NEXT: s_endpgm +; +; GFX9-LABEL: global_store_2xi16_align2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 +; GFX9-NEXT: v_mov_b32_e32 v2, 1 +; GFX9-NEXT: v_mov_b32_e32 v3, 2 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_short v[0:1], v2, off +; GFX9-NEXT: global_store_short v[0:1], v3, off offset:2 +; GFX9-NEXT: s_endpgm + %gep.r = getelementptr i16, i16 addrspace(1)* %r, i64 1 + store i16 1, i16 addrspace(1)* %r, align 2 + store i16 2, i16 addrspace(1)* %gep.r, align 2 + ret void +} + +; Should produce align 1 dword when legal +define i32 @global_load_2xi16_align1(i16 addrspace(1)* %p) #0 { +; GFX7-ALIGNED-LABEL: global_load_2xi16_align1: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v2, vcc, 2, v0 +; GFX7-ALIGNED-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GFX7-ALIGNED-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GFX7-ALIGNED-NEXT: flat_load_ubyte v6, v[0:1] +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v0, vcc, 3, v0 +; GFX7-ALIGNED-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX7-ALIGNED-NEXT: flat_load_ubyte v2, v[2:3] +; GFX7-ALIGNED-NEXT: flat_load_ubyte v3, v[4:5] +; GFX7-ALIGNED-NEXT: flat_load_ubyte v0, v[0:1] +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1) +; GFX7-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v3 +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_lshlrev_b32_e32 v0, 8, v0 +; GFX7-ALIGNED-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX7-ALIGNED-NEXT: v_or_b32_e32 v1, v1, v6 +; GFX7-ALIGNED-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX7-ALIGNED-NEXT: v_or_b32_e32 v0, v1, v0 +; GFX7-ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-UNALIGNED-LABEL: global_load_2xi16_align1: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: flat_load_dword v0, v[0:1] +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: global_load_2xi16_align1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff +; GFX9-NEXT: s_mov_b32 s4, 0xffff +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_bfi_b32 v1, v1, 0, v0 +; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %gep.p = getelementptr i16, i16 addrspace(1)* %p, i64 1 + %p.0 = load i16, i16 addrspace(1)* %p, align 1 + %p.1 = load i16, i16 addrspace(1)* %gep.p, align 1 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + +; Should produce align 1 dword when legal +define amdgpu_kernel void @global_store_2xi16_align1(i16 addrspace(1)* %p, i16 addrspace(1)* %r) #0 { +; GFX7-ALIGNED-LABEL: global_store_2xi16_align1: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v4, 1 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v5, 0 +; GFX7-ALIGNED-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-ALIGNED-NEXT: s_add_u32 s2, s0, 2 +; GFX7-ALIGNED-NEXT: s_addc_u32 s3, s1, 0 +; GFX7-ALIGNED-NEXT: s_add_u32 s4, s0, 1 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-ALIGNED-NEXT: s_addc_u32 s5, s1, 0 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-ALIGNED-NEXT: s_add_u32 s0, s0, 3 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, s4 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v3, s5 +; GFX7-ALIGNED-NEXT: flat_store_byte v[0:1], v4 +; GFX7-ALIGNED-NEXT: flat_store_byte v[2:3], v5 +; GFX7-ALIGNED-NEXT: s_addc_u32 s1, s1, 0 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, s2 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v4, 2 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v3, s3 +; GFX7-ALIGNED-NEXT: flat_store_byte v[0:1], v5 +; GFX7-ALIGNED-NEXT: flat_store_byte v[2:3], v4 +; GFX7-ALIGNED-NEXT: s_endpgm +; +; GFX7-UNALIGNED-LABEL: global_store_2xi16_align1: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v2, 0x20001 +; GFX7-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-UNALIGNED-NEXT: flat_store_dword v[0:1], v2 +; GFX7-UNALIGNED-NEXT: s_endpgm +; +; GFX9-LABEL: global_store_2xi16_align1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x20001 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NEXT: s_endpgm + %gep.r = getelementptr i16, i16 addrspace(1)* %r, i64 1 + store i16 1, i16 addrspace(1)* %r, align 1 + store i16 2, i16 addrspace(1)* %gep.r, align 1 + ret void +} + +; Should merge this to a dword load +define i32 @global_load_2xi16_align4(i16 addrspace(1)* %p) #0 { +; GFX7-LABEL: load_2xi16_align4: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: flat_load_dword v0, v[0:1] +; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-ALIGNED-LABEL: global_load_2xi16_align4: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: flat_load_dword v0, v[0:1] +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-UNALIGNED-LABEL: global_load_2xi16_align4: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: flat_load_dword v0, v[0:1] +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: global_load_2xi16_align4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dword v0, v[0:1], off +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff +; GFX9-NEXT: s_mov_b32 s4, 0xffff +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_bfi_b32 v1, v1, 0, v0 +; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %gep.p = getelementptr i16, i16 addrspace(1)* %p, i64 1 + %p.0 = load i16, i16 addrspace(1)* %p, align 4 + %p.1 = load i16, i16 addrspace(1)* %gep.p, align 2 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + +; Should merge this to a dword store +define amdgpu_kernel void @global_store_2xi16_align4(i16 addrspace(1)* %p, i16 addrspace(1)* %r) #0 { +; GFX7-LABEL: global_store_2xi16_align4: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2 +; GFX7-NEXT: v_mov_b32_e32 v2, 0x20001 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-NEXT: flat_store_dword v[0:1], v2 +; GFX7-NEXT: s_endpgm +; +; GFX7-ALIGNED-LABEL: global_store_2xi16_align4: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v2, 0x20001 +; GFX7-ALIGNED-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-ALIGNED-NEXT: flat_store_dword v[0:1], v2 +; GFX7-ALIGNED-NEXT: s_endpgm +; +; GFX7-UNALIGNED-LABEL: global_store_2xi16_align4: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v2, 0x20001 +; GFX7-UNALIGNED-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-UNALIGNED-NEXT: flat_store_dword v[0:1], v2 +; GFX7-UNALIGNED-NEXT: s_endpgm +; +; GFX9-LABEL: global_store_2xi16_align4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8 +; GFX9-NEXT: v_mov_b32_e32 v2, 0x20001 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dword v[0:1], v2, off +; GFX9-NEXT: s_endpgm + %gep.r = getelementptr i16, i16 addrspace(1)* %r, i64 1 + store i16 1, i16 addrspace(1)* %r, align 4 + store i16 2, i16 addrspace(1)* %gep.r, align 2 + ret void +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll new file mode 100644 index 000000000000..0053d2f3019d --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll @@ -0,0 +1,245 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=-unaligned-scratch-access < %s | FileCheck -check-prefixes=GCN,GFX7-ALIGNED %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=+unaligned-scratch-access < %s | FileCheck -check-prefixes=GCN,GFX7-UNALIGNED %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+unaligned-scratch-access < %s | FileCheck -check-prefixes=GCN,GFX9 %s + +; Should not merge this to a dword load +define i32 @private_load_2xi16_align2(i16 addrspace(5)* %p) #0 { +; GFX7-ALIGNED-LABEL: private_load_2xi16_align2: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v1, vcc, 2, v0 +; GFX7-ALIGNED-NEXT: buffer_load_ushort v1, v1, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: buffer_load_ushort v0, v0, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(1) +; GFX7-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-ALIGNED-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX7-ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-UNALIGNED-LABEL: private_load_2xi16_align2: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: v_add_i32_e32 v1, vcc, 2, v0 +; GFX7-UNALIGNED-NEXT: buffer_load_ushort v1, v1, s[0:3], s33 offen +; GFX7-UNALIGNED-NEXT: buffer_load_ushort v0, v0, s[0:3], s33 offen +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(1) +; GFX7-UNALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-UNALIGNED-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: private_load_2xi16_align2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_load_ushort v1, v0, s[0:3], s33 offen +; GFX9-NEXT: buffer_load_ushort v0, v0, s[0:3], s33 offen offset:2 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %gep.p = getelementptr i16, i16 addrspace(5)* %p, i64 1 + %p.0 = load i16, i16 addrspace(5)* %p, align 2 + %p.1 = load i16, i16 addrspace(5)* %gep.p, align 2 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + +; Should not merge this to a dword store +define void @private_store_2xi16_align2(i16 addrspace(5)* %p, i16 addrspace(5)* %r) #0 { +; GFX7-ALIGNED-LABEL: private_store_2xi16_align2: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v3, 1 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, 2 +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v2, vcc, 2, v1 +; GFX7-ALIGNED-NEXT: buffer_store_short v3, v1, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: buffer_store_short v0, v2, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-UNALIGNED-LABEL: private_store_2xi16_align2: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v3, 1 +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v0, 2 +; GFX7-UNALIGNED-NEXT: v_add_i32_e32 v2, vcc, 2, v1 +; GFX7-UNALIGNED-NEXT: buffer_store_short v3, v1, s[0:3], s33 offen +; GFX7-UNALIGNED-NEXT: buffer_store_short v0, v2, s[0:3], s33 offen +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: private_store_2xi16_align2: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, 1 +; GFX9-NEXT: buffer_store_short v0, v1, s[0:3], s33 offen +; GFX9-NEXT: v_mov_b32_e32 v0, 2 +; GFX9-NEXT: buffer_store_short v0, v1, s[0:3], s33 offen offset:2 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %gep.r = getelementptr i16, i16 addrspace(5)* %r, i64 1 + store i16 1, i16 addrspace(5)* %r, align 2 + store i16 2, i16 addrspace(5)* %gep.r, align 2 + ret void +} + +; Should produce align 1 dword when legal +define i32 @private_load_2xi16_align1(i16 addrspace(5)* %p) #0 { +; GFX7-ALIGNED-LABEL: private_load_2xi16_align1: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v1, vcc, 3, v0 +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v2, vcc, 2, v0 +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v3, vcc, 1, v0 +; GFX7-ALIGNED-NEXT: buffer_load_ubyte v1, v1, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: buffer_load_ubyte v3, v3, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: buffer_load_ubyte v2, v2, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: buffer_load_ubyte v0, v0, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(3) +; GFX7-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v1 +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(2) +; GFX7-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v3 +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(1) +; GFX7-ALIGNED-NEXT: v_or_b32_e32 v1, v1, v2 +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v0 +; GFX7-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX7-ALIGNED-NEXT: v_or_b32_e32 v0, v0, v1 +; GFX7-ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-UNALIGNED-LABEL: private_load_2xi16_align1: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: buffer_load_dword v0, v0, s[0:3], s33 offen +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: private_load_2xi16_align1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_load_dword v0, v0, s[0:3], s33 offen +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff +; GFX9-NEXT: s_mov_b32 s4, 0xffff +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_bfi_b32 v1, v1, 0, v0 +; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %gep.p = getelementptr i16, i16 addrspace(5)* %p, i64 1 + %p.0 = load i16, i16 addrspace(5)* %p, align 1 + %p.1 = load i16, i16 addrspace(5)* %gep.p, align 1 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + +; Should produce align 1 dword when legal +define void @private_store_2xi16_align1(i16 addrspace(5)* %p, i16 addrspace(5)* %r) #0 { +; GFX7-ALIGNED-LABEL: private_store_2xi16_align1: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v3, 1 +; GFX7-ALIGNED-NEXT: buffer_store_byte v3, v1, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v2, vcc, 2, v1 +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v3, vcc, 1, v1 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v4, 0 +; GFX7-ALIGNED-NEXT: v_add_i32_e32 v1, vcc, 3, v1 +; GFX7-ALIGNED-NEXT: v_mov_b32_e32 v0, 2 +; GFX7-ALIGNED-NEXT: buffer_store_byte v4, v3, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: buffer_store_byte v4, v1, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: buffer_store_byte v0, v2, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-UNALIGNED-LABEL: private_store_2xi16_align1: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: v_mov_b32_e32 v0, 0x20001 +; GFX7-UNALIGNED-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: private_store_2xi16_align1: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, 0x20001 +; GFX9-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %gep.r = getelementptr i16, i16 addrspace(5)* %r, i64 1 + store i16 1, i16 addrspace(5)* %r, align 1 + store i16 2, i16 addrspace(5)* %gep.r, align 1 + ret void +} + +; Should merge this to a dword load +define i32 @private_load_2xi16_align4(i16 addrspace(5)* %p) #0 { +; GFX7-LABEL: load_2xi16_align4: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-NEXT: flat_load_dword v0, v[0:1] +; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-ALIGNED-LABEL: private_load_2xi16_align4: +; GFX7-ALIGNED: ; %bb.0: +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-ALIGNED-NEXT: buffer_load_dword v0, v0, s[0:3], s33 offen +; GFX7-ALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-ALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX7-UNALIGNED-LABEL: private_load_2xi16_align4: +; GFX7-UNALIGNED: ; %bb.0: +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX7-UNALIGNED-NEXT: buffer_load_dword v0, v0, s[0:3], s33 offen +; GFX7-UNALIGNED-NEXT: s_waitcnt vmcnt(0) +; GFX7-UNALIGNED-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: private_load_2xi16_align4: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_load_dword v0, v0, s[0:3], s33 offen +; GFX9-NEXT: v_mov_b32_e32 v1, 0xffff +; GFX9-NEXT: s_mov_b32 s4, 0xffff +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_bfi_b32 v1, v1, 0, v0 +; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v1 +; GFX9-NEXT: s_setpc_b64 s[30:31] + %gep.p = getelementptr i16, i16 addrspace(5)* %p, i64 1 + %p.0 = load i16, i16 addrspace(5)* %p, align 4 + %p.1 = load i16, i16 addrspace(5)* %gep.p, align 2 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + +; Should merge this to a dword store +define void @private_store_2xi16_align4(i16 addrspace(5)* %p, i16 addrspace(5)* %r) #0 { +; GFX7-LABEL: private_store_2xi16_align4: +; GFX7: ; %bb.0: +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2 +; GFX7-NEXT: v_mov_b32_e32 v2, 0x20001 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: v_mov_b32_e32 v0, s0 +; GFX7-NEXT: v_mov_b32_e32 v1, s1 +; GFX7-NEXT: flat_store_dword v[0:1], v2 +; GFX7-NEXT: s_endpgm +; +; GCN-LABEL: private_store_2xi16_align4: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, 0x20001 +; GCN-NEXT: buffer_store_dword v0, v1, s[0:3], s33 offen +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] + %gep.r = getelementptr i16, i16 addrspace(5)* %r, i64 1 + store i16 1, i16 addrspace(5)* %r, align 4 + store i16 2, i16 addrspace(5)* %gep.r, align 2 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll index 9bcf35e13a1b..020f677ee3cf 100644 --- a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll +++ b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll @@ -665,4 +665,25 @@ define void @private_store_align2_f64(double addrspace(5)* %out, double %x) #0 { ret void } +; Should not merge this to a dword store +define amdgpu_kernel void @global_store_2xi16_align2(i16 addrspace(1)* %p, i16 addrspace(1)* %r) #0 { + %gep.r = getelementptr i16, i16 addrspace(1)* %r, i64 1 + %v = load i16, i16 addrspace(1)* %p, align 2 + store i16 1, i16 addrspace(1)* %r, align 2 + store i16 2, i16 addrspace(1)* %gep.r, align 2 + ret void +} + +; Should not merge this to a word load +define i32 @load_2xi16_align2(i16 addrspace(1)* %p) #0 { + %gep.p = getelementptr i16, i16 addrspace(1)* %p, i64 1 + %p.0 = load i16, i16 addrspace(1)* %p, align 2 + %p.1 = load i16, i16 addrspace(1)* %gep.p, align 2 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + attributes #0 = { nounwind } diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll index b0dd5d185c77..9f85fec33ba1 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll @@ -207,4 +207,55 @@ define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i8() { ret void } +; Make sure we don't think the alignment will increase if the base address isn't an alloca +; ALL-LABEL: @private_store_2xi16_align2_not_alloca( +; ALL: store i16 +; ALL: store i16 +define void @private_store_2xi16_align2_not_alloca(i16 addrspace(5)* %p, i16 addrspace(5)* %r) #0 { + %gep.r = getelementptr i16, i16 addrspace(5)* %r, i32 1 + store i16 1, i16 addrspace(5)* %r, align 2 + store i16 2, i16 addrspace(5)* %gep.r, align 2 + ret void +} + +; ALL-LABEL: @private_store_2xi16_align1_not_alloca( +; ALIGNED: store i16 +; ALIGNED: store i16 +; UNALIGNED: store <2 x i16> +define void @private_store_2xi16_align1_not_alloca(i16 addrspace(5)* %p, i16 addrspace(5)* %r) #0 { + %gep.r = getelementptr i16, i16 addrspace(5)* %r, i32 1 + store i16 1, i16 addrspace(5)* %r, align 1 + store i16 2, i16 addrspace(5)* %gep.r, align 1 + ret void +} + +; ALL-LABEL: @private_load_2xi16_align2_not_alloca( +; ALL: load i16 +; ALL: load i16 +define i32 @private_load_2xi16_align2_not_alloca(i16 addrspace(5)* %p) #0 { + %gep.p = getelementptr i16, i16 addrspace(5)* %p, i64 1 + %p.0 = load i16, i16 addrspace(5)* %p, align 2 + %p.1 = load i16, i16 addrspace(5)* %gep.p, align 2 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + +; ALL-LABEL: @private_load_2xi16_align1_not_alloca( +; ALIGNED: load i16 +; ALIGNED: load i16 +; UNALIGNED: load <2 x i16> +define i32 @private_load_2xi16_align1_not_alloca(i16 addrspace(5)* %p) #0 { + %gep.p = getelementptr i16, i16 addrspace(5)* %p, i64 1 + %p.0 = load i16, i16 addrspace(5)* %p, align 1 + %p.1 = load i16, i16 addrspace(5)* %gep.p, align 1 + %zext.0 = zext i16 %p.0 to i32 + %zext.1 = zext i16 %p.1 to i32 + %shl.1 = shl i32 %zext.1, 16 + %or = or i32 %zext.0, %shl.1 + ret i32 %or +} + attributes #0 = { nounwind } diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll index 4292cbcec850..31a1c270bd0e 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll @@ -57,20 +57,10 @@ define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32_align1( } ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32_align2( -; ALIGNED: store i32 9, i32 addrspace(5)* %out, align 2 -; ALIGNED: store i32 1, i32 addrspace(5)* %out.gep.1, align 2 -; ALIGNED: store i32 23, i32 addrspace(5)* %out.gep.2, align 2 -; ALIGNED: store i32 19, i32 addrspace(5)* %out.gep.3, align 2 - -; ELT16-UNALIGNED: store <4 x i32> , <4 x i32> addrspace(5)* %1, align 2 - -; ELT8-UNALIGNED: store <2 x i32> -; ELT8-UNALIGNED: store <2 x i32> - -; ELT4-UNALIGNED: store i32 -; ELT4-UNALIGNED: store i32 -; ELT4-UNALIGNED: store i32 -; ELT4-UNALIGNED: store i32 +; ALL: store i32 +; ALL: store i32 +; ALL: store i32 +; ALL: store i32 define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32_align2(i32 addrspace(5)* %out) #0 { %out.gep.1 = getelementptr i32, i32 addrspace(5)* %out, i32 1 %out.gep.2 = getelementptr i32, i32 addrspace(5)* %out, i32 2 @@ -127,10 +117,8 @@ define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16(i16 add } ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align2( -; ALIGNED: store i16 -; ALIGNED: store i16 - -; UNALIGNED: store <2 x i16> , <2 x i16> addrspace(5)* %1, align 2 +; ALL: store i16 +; ALL: store i16 define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align2(i16 addrspace(5)* %out) #0 { %out.gep.1 = getelementptr i16, i16 addrspace(5)* %out, i32 1 diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll index 0d9a4184e718..8302ad9562f5 100644 --- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll +++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll @@ -49,7 +49,8 @@ define amdgpu_kernel void @merge_global_store_2_constants_0_i16(i16 addrspace(1) } ; CHECK-LABEL: @merge_global_store_2_constants_i16_natural_align -; CHECK: store <2 x i16> +; CHECK: store i16 +; CHECK: store i16 define amdgpu_kernel void @merge_global_store_2_constants_i16_natural_align(i16 addrspace(1)* %out) #0 { %out.gep.1 = getelementptr i16, i16 addrspace(1)* %out, i32 1 @@ -58,8 +59,19 @@ define amdgpu_kernel void @merge_global_store_2_constants_i16_natural_align(i16 ret void } +; CHECK-LABEL: @merge_global_store_2_constants_i16_align_1 +; CHECK: store <2 x i16> +define amdgpu_kernel void @merge_global_store_2_constants_i16_align_1(i16 addrspace(1)* %out) #0 { + %out.gep.1 = getelementptr i16, i16 addrspace(1)* %out, i32 1 + + store i16 123, i16 addrspace(1)* %out.gep.1, align 1 + store i16 456, i16 addrspace(1)* %out, align 1 + ret void +} + ; CHECK-LABEL: @merge_global_store_2_constants_half_natural_align -; CHECK: store <2 x half> +; CHECK: store half +; CHECK: store half define amdgpu_kernel void @merge_global_store_2_constants_half_natural_align(half addrspace(1)* %out) #0 { %out.gep.1 = getelementptr half, half addrspace(1)* %out, i32 1 @@ -68,6 +80,16 @@ define amdgpu_kernel void @merge_global_store_2_constants_half_natural_align(hal ret void } +; CHECK-LABEL: @merge_global_store_2_constants_half_align_1 +; CHECK: store <2 x half> +define amdgpu_kernel void @merge_global_store_2_constants_half_align_1(half addrspace(1)* %out) #0 { + %out.gep.1 = getelementptr half, half addrspace(1)* %out, i32 1 + + store half 2.0, half addrspace(1)* %out.gep.1, align 1 + store half 1.0, half addrspace(1)* %out, align 1 + ret void +} + ; CHECK-LABEL: @merge_global_store_2_constants_i32 ; CHECK: store <2 x i32> , <2 x i32> addrspace(1)* %{{[0-9]+}}, align 4 define amdgpu_kernel void @merge_global_store_2_constants_i32(i32 addrspace(1)* %out) #0 { -- GitLab From 2d3ecade3892fb0d0713350e06522a94734733b7 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Tue, 11 Feb 2020 15:52:41 -0800 Subject: [PATCH 093/142] [lldb/Plugins] Move PlatformRemoteiOS into PlatformMacOSX (NFCI) Move the logic for initialization and termination for PlatformRemoteiOS into PlatformMacOSX, like we did for the other Darwin platforms in a731c6ba94d0464c6a122de1af70ab88ffb5c1a6. --- lldb/source/API/SystemInitializerFull.cpp | 3 --- lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp | 3 +++ lldb/tools/lldb-test/SystemInitializerTest.cpp | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/lldb/source/API/SystemInitializerFull.cpp b/lldb/source/API/SystemInitializerFull.cpp index b14a9a2ccd28..cde820bbb76b 100644 --- a/lldb/source/API/SystemInitializerFull.cpp +++ b/lldb/source/API/SystemInitializerFull.cpp @@ -60,7 +60,6 @@ LLDB_PLUGIN_DECLARE(PlatformNetBSD); LLDB_PLUGIN_DECLARE(PlatformOpenBSD); LLDB_PLUGIN_DECLARE(PlatformWindows); LLDB_PLUGIN_DECLARE(PlatformAndroid); -LLDB_PLUGIN_DECLARE(PlatformRemoteiOS); LLDB_PLUGIN_DECLARE(PlatformMacOSX); LLDB_PLUGIN_DECLARE(TypeSystemClang); LLDB_PLUGIN_DECLARE(ArchitectureArm); @@ -187,7 +186,6 @@ llvm::Error SystemInitializerFull::Initialize() { LLDB_PLUGIN_INITIALIZE(PlatformOpenBSD); LLDB_PLUGIN_INITIALIZE(PlatformWindows); LLDB_PLUGIN_INITIALIZE(PlatformAndroid); - LLDB_PLUGIN_INITIALIZE(PlatformRemoteiOS); LLDB_PLUGIN_INITIALIZE(PlatformMacOSX); // Initialize LLVM and Clang @@ -363,7 +361,6 @@ void SystemInitializerFull::Terminate() { LLDB_PLUGIN_TERMINATE(PlatformOpenBSD); LLDB_PLUGIN_TERMINATE(PlatformWindows); LLDB_PLUGIN_TERMINATE(PlatformAndroid); - LLDB_PLUGIN_TERMINATE(PlatformRemoteiOS); LLDB_PLUGIN_TERMINATE(PlatformMacOSX); LLDB_PLUGIN_TERMINATE(ObjectFileBreakpad); diff --git a/lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp b/lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp index 6cf96eded7aa..c62940f35e5c 100644 --- a/lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp +++ b/lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "PlatformMacOSX.h" +#include "PlatformRemoteiOS.h" #if defined(__APPLE__) #include "PlatformAppleTVSimulator.h" #include "PlatformAppleWatchSimulator.h" @@ -44,6 +45,7 @@ static uint32_t g_initialize_count = 0; void PlatformMacOSX::Initialize() { PlatformDarwin::Initialize(); + PlatformRemoteiOS::Initialize(); #if defined(__APPLE__) PlatformiOSSimulator::Initialize(); PlatformDarwinKernel::Initialize(); @@ -82,6 +84,7 @@ void PlatformMacOSX::Terminate() { PlatformDarwinKernel::Terminate(); PlatformiOSSimulator::Terminate(); #endif + PlatformRemoteiOS::Terminate(); PlatformDarwin::Terminate(); } diff --git a/lldb/tools/lldb-test/SystemInitializerTest.cpp b/lldb/tools/lldb-test/SystemInitializerTest.cpp index 3d8c80db5500..a9b4ba67c2ca 100644 --- a/lldb/tools/lldb-test/SystemInitializerTest.cpp +++ b/lldb/tools/lldb-test/SystemInitializerTest.cpp @@ -46,7 +46,6 @@ LLDB_PLUGIN_DECLARE(PlatformNetBSD); LLDB_PLUGIN_DECLARE(PlatformOpenBSD); LLDB_PLUGIN_DECLARE(PlatformWindows); LLDB_PLUGIN_DECLARE(PlatformAndroid); -LLDB_PLUGIN_DECLARE(PlatformRemoteiOS); LLDB_PLUGIN_DECLARE(PlatformMacOSX); LLDB_PLUGIN_DECLARE(TypeSystemClang); LLDB_PLUGIN_DECLARE(ArchitectureArm); @@ -162,7 +161,6 @@ llvm::Error SystemInitializerTest::Initialize() { LLDB_PLUGIN_INITIALIZE(PlatformOpenBSD); LLDB_PLUGIN_INITIALIZE(PlatformWindows); LLDB_PLUGIN_INITIALIZE(PlatformAndroid); - LLDB_PLUGIN_INITIALIZE(PlatformRemoteiOS); LLDB_PLUGIN_INITIALIZE(PlatformMacOSX); // Initialize LLVM and Clang @@ -338,7 +336,6 @@ void SystemInitializerTest::Terminate() { LLDB_PLUGIN_TERMINATE(PlatformOpenBSD); LLDB_PLUGIN_TERMINATE(PlatformWindows); LLDB_PLUGIN_TERMINATE(PlatformAndroid); - LLDB_PLUGIN_TERMINATE(PlatformRemoteiOS); LLDB_PLUGIN_TERMINATE(PlatformMacOSX); LLDB_PLUGIN_TERMINATE(ObjectFileBreakpad); -- GitLab From a349c09162a8260bdf691c4f7ab72a16c33975f6 Mon Sep 17 00:00:00 2001 From: Reid Kleckner Date: Tue, 11 Feb 2020 15:50:27 -0800 Subject: [PATCH 094/142] Fix MSVC build with C++ EH enabled Mark the CrashRecoveryContextImpl constructor noexcept, so that MSVC won't emit an unwind helper to clean up the allocation from `new` if the constructor throws an exception. Otherwise, MSVC complains: llvm\lib\Support\CrashRecoveryContext.cpp(220): error C2712: \ Cannot use __try in functions that require object unwinding The other simple fix would be to wrap `new` in a static helper or lambda. Users have reported that Tensorflow builds LLVM with /EHsc. --- llvm/lib/Support/CrashRecoveryContext.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Support/CrashRecoveryContext.cpp b/llvm/lib/Support/CrashRecoveryContext.cpp index f708da773f4c..356835609830 100644 --- a/llvm/lib/Support/CrashRecoveryContext.cpp +++ b/llvm/lib/Support/CrashRecoveryContext.cpp @@ -41,7 +41,7 @@ struct CrashRecoveryContextImpl { unsigned ValidJumpBuffer : 1; public: - CrashRecoveryContextImpl(CrashRecoveryContext *CRC) + CrashRecoveryContextImpl(CrashRecoveryContext *CRC) noexcept : CRC(CRC), Failed(false), SwitchedThread(false), ValidJumpBuffer(false) { Next = CurrentContext->get(); CurrentContext->set(this); -- GitLab From b30e1223334b3fb4246acfe0a476a836d788c623 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Feb 2020 14:57:09 -0500 Subject: [PATCH 095/142] AMDGPU: Don't expand more special div cases in IR These have nicer expansions implemented in the DAG. Ideally we would either directly implement all of these special expansions, or stop expanding division in the IR. --- .../Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 48 +++- .../AMDGPU/amdgpu-codegenprepare-idiv.ll | 268 ++---------------- 2 files changed, 73 insertions(+), 243 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index 225cf48d61f8..adf2648441e4 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -67,6 +67,7 @@ class AMDGPUCodeGenPrepare : public FunctionPass, public InstVisitor { const GCNSubtarget *ST = nullptr; AssumptionCache *AC = nullptr; + DominatorTree *DT = nullptr; LegacyDivergenceAnalysis *DA = nullptr; Module *Mod = nullptr; const DataLayout *DL = nullptr; @@ -157,6 +158,9 @@ class AMDGPUCodeGenPrepare : public FunctionPass, /// we expand some divisions here, we need to perform this before obscuring. bool foldBinOpIntoSelect(BinaryOperator &I) const; + bool divHasSpecialOptimization(BinaryOperator &I, + Value *Num, Value *Den) const; + /// Expands 24 bit div or rem. Value* expandDivRem24(IRBuilder<> &Builder, BinaryOperator &I, Value *Num, Value *Den, @@ -909,6 +913,42 @@ Value* AMDGPUCodeGenPrepare::expandDivRem24(IRBuilder<> &Builder, return Res; } +// Try to recognize special cases the DAG will emit special, better expansions +// than the general expansion we do here. + +// TODO: It would be better to just directly handle those optimizations here. +bool AMDGPUCodeGenPrepare::divHasSpecialOptimization( + BinaryOperator &I, Value *Num, Value *Den) const { + if (Constant *C = dyn_cast(Den)) { + // Arbitrary constants get a better expansion as long as a wider mulhi is + // legal. + if (C->getType()->getScalarSizeInBits() <= 32) + return true; + + // TODO: Sdiv check for not exact for some reason. + + // If there's no wider mulhi, there's only a better expansion for powers of + // two. + // TODO: Should really know for each vector element. + if (isKnownToBeAPowerOfTwo(C, *DL, true, 0, AC, &I, DT)) + return true; + + return false; + } + + if (BinaryOperator *BinOpDen = dyn_cast(Den)) { + // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 + if (BinOpDen->getOpcode() == Instruction::Shl && + isa(BinOpDen->getOperand(0)) && + isKnownToBeAPowerOfTwo(BinOpDen->getOperand(0), *DL, true, + 0, AC, &I, DT)) { + return true; + } + } + + return false; +} + Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder, BinaryOperator &I, Value *Num, Value *Den) const { @@ -920,8 +960,8 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder, FMF.setFast(); Builder.setFastMathFlags(FMF); - if (isa(Den)) - return nullptr; // Keep it for optimization + if (divHasSpecialOptimization(I, Num, Den)) + return nullptr; // Keep it for later optimization. bool IsDiv = Opc == Instruction::UDiv || Opc == Instruction::SDiv; bool IsSigned = Opc == Instruction::SRem || Opc == Instruction::SDiv; @@ -1211,6 +1251,10 @@ bool AMDGPUCodeGenPrepare::runOnFunction(Function &F) { ST = &TM.getSubtarget(F); AC = &getAnalysis().getAssumptionCache(F); DA = &getAnalysis(); + + auto *DTWP = getAnalysisIfAvailable(); + DT = DTWP ? &DTWP->getDomTree() : nullptr; + HasUnsafeFPMath = hasUnsafeFPMath(F); HasFP32Denormals = ST->hasFP32Denormals(F); diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index 6ed9d23f64be..6ee3964e77b7 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -4184,80 +4184,20 @@ define amdgpu_kernel void @udiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) define amdgpu_kernel void @udiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-LABEL: @udiv_i32_pow2_shl_denom( ; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[SHL_Y]] to float -; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]]) -; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[SHL_Y]] to i64 -; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i32 -; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP7]], 32 -; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32 -; CHECK-NEXT: [[TMP11:%.*]] = sub i32 0, [[TMP8]] -; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP10]], 0 -; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 [[TMP8]] -; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP4]] to i64 -; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]] -; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32 -; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32 -; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32 -; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP4]], [[TMP19]] -; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[TMP4]], [[TMP19]] -; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP12]], i32 [[TMP20]], i32 [[TMP21]] -; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 -; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[X:%.*]] to i64 -; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]] -; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32 -; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 32 -; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32 -; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[SHL_Y]] -; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[X]], [[TMP29]] -; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[SHL_Y]] -; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP31]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[X]], [[TMP29]] -; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP32]], [[TMP34]] -; CHECK-NEXT: [[TMP36:%.*]] = icmp eq i32 [[TMP35]], 0 -; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP28]], 1 -; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP28]], 1 -; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP28]], i32 [[TMP37]] -; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP33]], i32 [[TMP39]], i32 [[TMP38]] -; CHECK-NEXT: store i32 [[TMP40]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[R:%.*]] = udiv i32 [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: udiv_i32_pow2_shl_denom: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshl_b32 s9, 0x1000, s9 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 -; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 -; GCN-NEXT: v_mul_hi_u32 v2, v0, s9 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] -; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 -; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] -; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 -; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 -; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 -; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 -; GCN-NEXT: v_sub_i32_e32 v4, vcc, s8, v1 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, s8, v1 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 -; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GCN-NEXT: s_add_i32 s1, s1, 12 +; GCN-NEXT: s_lshr_b32 s0, s0, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_endpgm %shl.y = shl i32 4096, %y @@ -4540,80 +4480,21 @@ define amdgpu_kernel void @urem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) define amdgpu_kernel void @urem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-LABEL: @urem_i32_pow2_shl_denom( ; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[SHL_Y]] to float -; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]]) -; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP2]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP4:%.*]] = fptoui float [[TMP3]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 -; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[SHL_Y]] to i64 -; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP5]], [[TMP6]] -; CHECK-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i32 -; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP7]], 32 -; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32 -; CHECK-NEXT: [[TMP11:%.*]] = sub i32 0, [[TMP8]] -; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP10]], 0 -; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP11]], i32 [[TMP8]] -; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64 -; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP4]] to i64 -; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP14]], [[TMP15]] -; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32 -; CHECK-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP16]], 32 -; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32 -; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP4]], [[TMP19]] -; CHECK-NEXT: [[TMP21:%.*]] = sub i32 [[TMP4]], [[TMP19]] -; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP12]], i32 [[TMP20]], i32 [[TMP21]] -; CHECK-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64 -; CHECK-NEXT: [[TMP24:%.*]] = zext i32 [[X:%.*]] to i64 -; CHECK-NEXT: [[TMP25:%.*]] = mul i64 [[TMP23]], [[TMP24]] -; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32 -; CHECK-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP25]], 32 -; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i32 -; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[SHL_Y]] -; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[X]], [[TMP29]] -; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[SHL_Y]] -; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP31]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[X]], [[TMP29]] -; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP32]], [[TMP34]] -; CHECK-NEXT: [[TMP36:%.*]] = icmp eq i32 [[TMP35]], 0 -; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP30]], [[SHL_Y]] -; CHECK-NEXT: [[TMP38:%.*]] = add i32 [[TMP30]], [[SHL_Y]] -; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP30]], i32 [[TMP37]] -; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP33]], i32 [[TMP39]], i32 [[TMP38]] -; CHECK-NEXT: store i32 [[TMP40]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[R:%.*]] = urem i32 [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: urem_i32_pow2_shl_denom: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshl_b32 s9, 0x1000, s9 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 -; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; GCN-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 -; GCN-NEXT: v_mul_hi_u32 v2, v0, s9 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v2 -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[2:3] -; GCN-NEXT: v_mul_hi_u32 v1, v1, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v0 -; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v1, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[2:3] -; GCN-NEXT: v_mul_hi_u32 v0, v0, s8 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s9 -; GCN-NEXT: v_sub_i32_e32 v1, vcc, s8, v0 -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s8, v0 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, s9, v1 -; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s9, v1 -; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] -; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[2:3] +; GCN-NEXT: s_lshl_b32 s1, 0x1000, s1 +; GCN-NEXT: s_add_i32 s1, s1, -1 +; GCN-NEXT: s_and_b32 s0, s0, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_endpgm %shl.y = shl i32 4096, %y @@ -4865,56 +4746,8 @@ define amdgpu_kernel void @sdiv_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-LABEL: @sdiv_i32_pow2_shl_denom( ; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[SHL_Y]], 31 -; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP1]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[X]], [[TMP1]] -; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[SHL_Y]], [[TMP2]] -; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP1]] -; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[TMP5]], [[TMP2]] -; CHECK-NEXT: [[TMP8:%.*]] = uitofp i32 [[TMP7]] to float -; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP8]]) -; CHECK-NEXT: [[TMP10:%.*]] = fmul fast float [[TMP9]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP11:%.*]] = fptoui float [[TMP10]] to i32 -; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64 -; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP7]] to i64 -; CHECK-NEXT: [[TMP14:%.*]] = mul i64 [[TMP12]], [[TMP13]] -; CHECK-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP14]] to i32 -; CHECK-NEXT: [[TMP16:%.*]] = lshr i64 [[TMP14]], 32 -; CHECK-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i32 -; CHECK-NEXT: [[TMP18:%.*]] = sub i32 0, [[TMP15]] -; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[TMP17]], 0 -; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[TMP18]], i32 [[TMP15]] -; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP20]] to i64 -; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP11]] to i64 -; CHECK-NEXT: [[TMP23:%.*]] = mul i64 [[TMP21]], [[TMP22]] -; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 -; CHECK-NEXT: [[TMP25:%.*]] = lshr i64 [[TMP23]], 32 -; CHECK-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32 -; CHECK-NEXT: [[TMP27:%.*]] = add i32 [[TMP11]], [[TMP26]] -; CHECK-NEXT: [[TMP28:%.*]] = sub i32 [[TMP11]], [[TMP26]] -; CHECK-NEXT: [[TMP29:%.*]] = select i1 [[TMP19]], i32 [[TMP27]], i32 [[TMP28]] -; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP29]] to i64 -; CHECK-NEXT: [[TMP31:%.*]] = zext i32 [[TMP6]] to i64 -; CHECK-NEXT: [[TMP32:%.*]] = mul i64 [[TMP30]], [[TMP31]] -; CHECK-NEXT: [[TMP33:%.*]] = trunc i64 [[TMP32]] to i32 -; CHECK-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP32]], 32 -; CHECK-NEXT: [[TMP35:%.*]] = trunc i64 [[TMP34]] to i32 -; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[TMP35]], [[TMP7]] -; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP6]], [[TMP36]] -; CHECK-NEXT: [[TMP38:%.*]] = icmp uge i32 [[TMP37]], [[TMP7]] -; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP40:%.*]] = icmp uge i32 [[TMP6]], [[TMP36]] -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP42:%.*]] = and i32 [[TMP39]], [[TMP41]] -; CHECK-NEXT: [[TMP43:%.*]] = icmp eq i32 [[TMP42]], 0 -; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP35]], 1 -; CHECK-NEXT: [[TMP45:%.*]] = sub i32 [[TMP35]], 1 -; CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP43]], i32 [[TMP35]], i32 [[TMP44]] -; CHECK-NEXT: [[TMP47:%.*]] = select i1 [[TMP40]], i32 [[TMP46]], i32 [[TMP45]] -; CHECK-NEXT: [[TMP48:%.*]] = xor i32 [[TMP47]], [[TMP3]] -; CHECK-NEXT: [[TMP49:%.*]] = sub i32 [[TMP48]], [[TMP3]] -; CHECK-NEXT: store i32 [[TMP49]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[R:%.*]] = sdiv i32 [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: sdiv_i32_pow2_shl_denom: @@ -4949,12 +4782,12 @@ define amdgpu_kernel void @sdiv_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 % ; GCN-NEXT: v_mul_lo_u32 v1, v0, s9 ; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v0 ; GCN-NEXT: v_add_i32_e32 v3, vcc, -1, v0 -; GCN-NEXT: v_sub_i32_e32 v4, vcc, s2, v1 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, s2, v1 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 -; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s2, v1 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, s2, v1 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 +; GCN-NEXT: s_and_b64 vcc, vcc, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1] ; GCN-NEXT: v_xor_b32_e32 v0, s3, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s3, v0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 @@ -5287,55 +5120,8 @@ define amdgpu_kernel void @srem_i32_pow2k_denom(i32 addrspace(1)* %out, i32 %x) define amdgpu_kernel void @srem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-LABEL: @srem_i32_pow2_shl_denom( ; CHECK-NEXT: [[SHL_Y:%.*]] = shl i32 4096, [[Y:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 31 -; CHECK-NEXT: [[TMP2:%.*]] = ashr i32 [[SHL_Y]], 31 -; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[X]], [[TMP1]] -; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[SHL_Y]], [[TMP2]] -; CHECK-NEXT: [[TMP5:%.*]] = xor i32 [[TMP3]], [[TMP1]] -; CHECK-NEXT: [[TMP6:%.*]] = xor i32 [[TMP4]], [[TMP2]] -; CHECK-NEXT: [[TMP7:%.*]] = uitofp i32 [[TMP6]] to float -; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP7]]) -; CHECK-NEXT: [[TMP9:%.*]] = fmul fast float [[TMP8]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP10:%.*]] = fptoui float [[TMP9]] to i32 -; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64 -; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP6]] to i64 -; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP11]], [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = trunc i64 [[TMP13]] to i32 -; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP13]], 32 -; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32 -; CHECK-NEXT: [[TMP17:%.*]] = sub i32 0, [[TMP14]] -; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[TMP16]], 0 -; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP17]], i32 [[TMP14]] -; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64 -; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP10]] to i64 -; CHECK-NEXT: [[TMP22:%.*]] = mul i64 [[TMP20]], [[TMP21]] -; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP22]] to i32 -; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP22]], 32 -; CHECK-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP24]] to i32 -; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP10]], [[TMP25]] -; CHECK-NEXT: [[TMP27:%.*]] = sub i32 [[TMP10]], [[TMP25]] -; CHECK-NEXT: [[TMP28:%.*]] = select i1 [[TMP18]], i32 [[TMP26]], i32 [[TMP27]] -; CHECK-NEXT: [[TMP29:%.*]] = zext i32 [[TMP28]] to i64 -; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP5]] to i64 -; CHECK-NEXT: [[TMP31:%.*]] = mul i64 [[TMP29]], [[TMP30]] -; CHECK-NEXT: [[TMP32:%.*]] = trunc i64 [[TMP31]] to i32 -; CHECK-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP31]], 32 -; CHECK-NEXT: [[TMP34:%.*]] = trunc i64 [[TMP33]] to i32 -; CHECK-NEXT: [[TMP35:%.*]] = mul i32 [[TMP34]], [[TMP6]] -; CHECK-NEXT: [[TMP36:%.*]] = sub i32 [[TMP5]], [[TMP35]] -; CHECK-NEXT: [[TMP37:%.*]] = icmp uge i32 [[TMP36]], [[TMP6]] -; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP39:%.*]] = icmp uge i32 [[TMP5]], [[TMP35]] -; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP39]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP41:%.*]] = and i32 [[TMP38]], [[TMP40]] -; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i32 [[TMP41]], 0 -; CHECK-NEXT: [[TMP43:%.*]] = sub i32 [[TMP36]], [[TMP6]] -; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP36]], [[TMP6]] -; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP42]], i32 [[TMP36]], i32 [[TMP43]] -; CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP39]], i32 [[TMP45]], i32 [[TMP44]] -; CHECK-NEXT: [[TMP47:%.*]] = xor i32 [[TMP46]], [[TMP1]] -; CHECK-NEXT: [[TMP48:%.*]] = sub i32 [[TMP47]], [[TMP1]] -; CHECK-NEXT: store i32 [[TMP48]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[R:%.*]] = srem i32 [[X:%.*]], [[SHL_Y]] +; CHECK-NEXT: store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: srem_i32_pow2_shl_denom: @@ -5368,13 +5154,13 @@ define amdgpu_kernel void @srem_i32_pow2_shl_denom(i32 addrspace(1)* %out, i32 % ; GCN-NEXT: v_mul_hi_u32 v0, v0, s9 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s10 ; GCN-NEXT: v_sub_i32_e32 v1, vcc, s9, v0 -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], s9, v0 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v1 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], s9, v0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, s10, v1 +; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s10, v1 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s10, v1 -; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1] ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[2:3] +; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] ; GCN-NEXT: v_xor_b32_e32 v0, s8, v0 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -- GitLab From f9fdd1172c8b326126463f1efcfee721e5222334 Mon Sep 17 00:00:00 2001 From: Jason Molenda Date: Tue, 11 Feb 2020 16:17:35 -0800 Subject: [PATCH 096/142] Rewrite default "could not attach" msg to point to hints about where more information can be found about why it may have failed. --- lldb/tools/debugserver/source/RNBRemote.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/lldb/tools/debugserver/source/RNBRemote.cpp b/lldb/tools/debugserver/source/RNBRemote.cpp index 87aca91c00c4..8eed06381d3a 100644 --- a/lldb/tools/debugserver/source/RNBRemote.cpp +++ b/lldb/tools/debugserver/source/RNBRemote.cpp @@ -4076,6 +4076,16 @@ rnb_err_t RNBRemote::HandlePacket_v(const char *p) { std::string error_explainer = "attach failed"; if (err_str[0] != '\0') { + // This is not a super helpful message for end users + if (strcmp (err_str, "unable to start the exception thread") == 0) { + snprintf (err_str, sizeof (err_str) - 1, + "Not allowed to attach to process. Look in the console " + "messages (Console.app), near the debugserver entries " + "when the attached failed. The subsystem that denied " + "the attach permission will likely have logged an " + "informative message about why it was denied."); + err_str[sizeof (err_str) - 1] = '\0'; + } error_explainer += " ("; error_explainer += err_str; error_explainer += ")"; -- GitLab From f9219e644ac601ed00487bd6cb285503df5589dd Mon Sep 17 00:00:00 2001 From: Galina Kistanova Date: Tue, 11 Feb 2020 16:20:06 -0800 Subject: [PATCH 097/142] Reverted the remainings of c1c9819ef91aab51b5a23fb3027adac5a2f551cc as it has left broken llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast buildbot for long time. Differential Revision: https://reviews.llvm.org/D73840 --- llvm/examples/Bye/CMakeLists.txt | 4 ---- llvm/tools/bugpoint-passes/CMakeLists.txt | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/llvm/examples/Bye/CMakeLists.txt b/llvm/examples/Bye/CMakeLists.txt index 60eadede8a8d..3206f90d0916 100644 --- a/llvm/examples/Bye/CMakeLists.txt +++ b/llvm/examples/Bye/CMakeLists.txt @@ -7,10 +7,6 @@ add_llvm_pass_plugin(Bye DEPENDS intrinsics_gen BUILDTREE_ONLY - LINK_COMPONENTS - ipo - Core - Support ) install(TARGETS ${name} RUNTIME DESTINATION examples) diff --git a/llvm/tools/bugpoint-passes/CMakeLists.txt b/llvm/tools/bugpoint-passes/CMakeLists.txt index 6df49d7abd88..eea3e239b808 100644 --- a/llvm/tools/bugpoint-passes/CMakeLists.txt +++ b/llvm/tools/bugpoint-passes/CMakeLists.txt @@ -11,7 +11,7 @@ if( NOT LLVM_REQUIRES_RTTI ) endif() if(WIN32 OR CYGWIN) - set(LLVM_LINK_COMPONENTS Core Support) + set(LLVM_LINK_COMPONENTS Core) endif() add_llvm_library( BugpointPasses MODULE BUILDTREE_ONLY -- GitLab From 413307d4560441b47261ced5db5f8e29c8811277 Mon Sep 17 00:00:00 2001 From: Jonas Devlieghere Date: Tue, 11 Feb 2020 16:31:26 -0800 Subject: [PATCH 098/142] [lldb/Plugins] Rename OSPython plugin to OperatingSystemPython (NFC) Rename the plugin to match both the directory structure and the class. --- lldb/source/Plugins/OperatingSystem/Python/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lldb/source/Plugins/OperatingSystem/Python/CMakeLists.txt b/lldb/source/Plugins/OperatingSystem/Python/CMakeLists.txt index e8b0f31d3736..91d7901011bc 100644 --- a/lldb/source/Plugins/OperatingSystem/Python/CMakeLists.txt +++ b/lldb/source/Plugins/OperatingSystem/Python/CMakeLists.txt @@ -1,4 +1,4 @@ -add_lldb_library(lldbPluginOSPython PLUGIN +add_lldb_library(lldbPluginOperatingSystemPython PLUGIN OperatingSystemPython.cpp LINK_LIBS -- GitLab From 2c6a3896ab1de706389f27c921cf58084650f439 Mon Sep 17 00:00:00 2001 From: Reid Kleckner Date: Tue, 11 Feb 2020 16:03:26 -0800 Subject: [PATCH 099/142] Re-land "[MS] Overhaul how clang passes overaligned args on x86_32" This brings back 2af74e27ed7d0832cbdde9cb969aaca7a42e99f9 and reverts eaabaf7e04fe98990a8177a3e053346395efde1c. The changes were correct, the code that was broken contained an ODR violation that assumed that these types are passed equivalently: struct alignas(uint64_t) Wrapper { uint64_t P }; void f(uint64_t p); void f(Wrapper p); MSVC does not pass them the same way, and so clang-cl should not pass them the same way either. --- clang/include/clang/CodeGen/CGFunctionInfo.h | 17 +++- clang/lib/CodeGen/CGCall.cpp | 36 +++++++-- clang/lib/CodeGen/TargetInfo.cpp | 74 +++++++++++------ clang/test/CodeGen/x86_32-arguments-win32.c | 44 +++++++++++ .../test/CodeGenCXX/inalloca-overaligned.cpp | 52 ++++++++++++ clang/test/CodeGenCXX/inalloca-vector.cpp | 79 +++++++++++++++++++ 6 files changed, 269 insertions(+), 33 deletions(-) create mode 100644 clang/test/CodeGenCXX/inalloca-overaligned.cpp create mode 100644 clang/test/CodeGenCXX/inalloca-vector.cpp diff --git a/clang/include/clang/CodeGen/CGFunctionInfo.h b/clang/include/clang/CodeGen/CGFunctionInfo.h index 2a41ab9eece7..588c96afe402 100644 --- a/clang/include/clang/CodeGen/CGFunctionInfo.h +++ b/clang/include/clang/CodeGen/CGFunctionInfo.h @@ -88,6 +88,7 @@ private: Kind TheKind; bool PaddingInReg : 1; bool InAllocaSRet : 1; // isInAlloca() + bool InAllocaIndirect : 1;// isInAlloca() bool IndirectByVal : 1; // isIndirect() bool IndirectRealign : 1; // isIndirect() bool SRetAfterThis : 1; // isIndirect() @@ -110,8 +111,8 @@ private: public: ABIArgInfo(Kind K = Direct) - : TypeData(nullptr), PaddingType(nullptr), DirectOffset(0), - TheKind(K), PaddingInReg(false), InAllocaSRet(false), + : TypeData(nullptr), PaddingType(nullptr), DirectOffset(0), TheKind(K), + PaddingInReg(false), InAllocaSRet(false), InAllocaIndirect(false), IndirectByVal(false), IndirectRealign(false), SRetAfterThis(false), InReg(false), CanBeFlattened(false), SignExt(false) {} @@ -185,9 +186,10 @@ public: AI.setInReg(true); return AI; } - static ABIArgInfo getInAlloca(unsigned FieldIndex) { + static ABIArgInfo getInAlloca(unsigned FieldIndex, bool Indirect = false) { auto AI = ABIArgInfo(InAlloca); AI.setInAllocaFieldIndex(FieldIndex); + AI.setInAllocaIndirect(Indirect); return AI; } static ABIArgInfo getExpand() { @@ -380,6 +382,15 @@ public: AllocaFieldIndex = FieldIndex; } + unsigned getInAllocaIndirect() const { + assert(isInAlloca() && "Invalid kind!"); + return InAllocaIndirect; + } + void setInAllocaIndirect(bool Indirect) { + assert(isInAlloca() && "Invalid kind!"); + InAllocaIndirect = Indirect; + } + /// Return true if this field of an inalloca struct should be returned /// to implement a struct return calling convention. bool getInAllocaSRet() const { diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index e6cb4a1fd93f..c90326362d66 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -2370,6 +2370,9 @@ void CodeGenFunction::EmitFunctionProlog(const CGFunctionInfo &FI, auto FieldIndex = ArgI.getInAllocaFieldIndex(); Address V = Builder.CreateStructGEP(ArgStruct, FieldIndex, Arg->getName()); + if (ArgI.getInAllocaIndirect()) + V = Address(Builder.CreateLoad(V), + getContext().getTypeAlignInChars(Ty)); ArgVals.push_back(ParamValue::forIndirect(V)); break; } @@ -4091,18 +4094,39 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, assert(NumIRArgs == 0); assert(getTarget().getTriple().getArch() == llvm::Triple::x86); if (I->isAggregate()) { - // Replace the placeholder with the appropriate argument slot GEP. Address Addr = I->hasLValue() ? I->getKnownLValue().getAddress(*this) : I->getKnownRValue().getAggregateAddress(); llvm::Instruction *Placeholder = cast(Addr.getPointer()); - CGBuilderTy::InsertPoint IP = Builder.saveIP(); - Builder.SetInsertPoint(Placeholder); - Addr = - Builder.CreateStructGEP(ArgMemory, ArgInfo.getInAllocaFieldIndex()); - Builder.restoreIP(IP); + + if (!ArgInfo.getInAllocaIndirect()) { + // Replace the placeholder with the appropriate argument slot GEP. + CGBuilderTy::InsertPoint IP = Builder.saveIP(); + Builder.SetInsertPoint(Placeholder); + Addr = Builder.CreateStructGEP(ArgMemory, + ArgInfo.getInAllocaFieldIndex()); + Builder.restoreIP(IP); + } else { + // For indirect things such as overaligned structs, replace the + // placeholder with a regular aggregate temporary alloca. Store the + // address of this alloca into the struct. + Addr = CreateMemTemp(info_it->type, "inalloca.indirect.tmp"); + Address ArgSlot = Builder.CreateStructGEP( + ArgMemory, ArgInfo.getInAllocaFieldIndex()); + Builder.CreateStore(Addr.getPointer(), ArgSlot); + } deferPlaceholderReplacement(Placeholder, Addr.getPointer()); + } else if (ArgInfo.getInAllocaIndirect()) { + // Make a temporary alloca and store the address of it into the argument + // struct. + Address Addr = CreateMemTempWithoutCast( + I->Ty, getContext().getTypeAlignInChars(I->Ty), + "indirect-arg-temp"); + I->copyInto(*this, Addr); + Address ArgSlot = + Builder.CreateStructGEP(ArgMemory, ArgInfo.getInAllocaFieldIndex()); + Builder.CreateStore(Addr.getPointer(), ArgSlot); } else { // Store the RValue into the argument struct. Address Addr = diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 29998f361926..905440febb51 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -1702,6 +1702,7 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall; Ty = useFirstFieldIfTransparentUnion(Ty); + TypeInfo TI = getContext().getTypeInfo(Ty); // Check with the C++ ABI first. const RecordType *RT = Ty->getAs(); @@ -1751,7 +1752,7 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, bool NeedsPadding = false; bool InReg; if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) { - unsigned SizeInRegs = (getContext().getTypeSize(Ty) + 31) / 32; + unsigned SizeInRegs = (TI.Width + 31) / 32; SmallVector Elements(SizeInRegs, Int32); llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); if (InReg) @@ -1761,14 +1762,19 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, } llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr; + // Pass over-aligned aggregates on Windows indirectly. This behavior was + // added in MSVC 2015. + if (IsWin32StructABI && TI.AlignIsRequired && TI.Align > 32) + return getIndirectResult(Ty, /*ByVal=*/false, State); + // Expand small (<= 128-bit) record types when we know that the stack layout // of those arguments will match the struct. This is important because the // LLVM backend isn't smart enough to remove byval, which inhibits many // optimizations. // Don't do this for the MCU if there are still free integer registers // (see X86_64 ABI for full explanation). - if (getContext().getTypeSize(Ty) <= 4 * 32 && - (!IsMCUABI || State.FreeRegs == 0) && canExpandIndirectArgument(Ty)) + if (TI.Width <= 4 * 32 && (!IsMCUABI || State.FreeRegs == 0) && + canExpandIndirectArgument(Ty)) return ABIArgInfo::getExpandWithPadding( IsFastCall || IsVectorCall || IsRegCall, PaddingType); @@ -1776,14 +1782,24 @@ ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, } if (const VectorType *VT = Ty->getAs()) { + // On Windows, vectors are passed directly if registers are available, or + // indirectly if not. This avoids the need to align argument memory. Pass + // user-defined vector types larger than 512 bits indirectly for simplicity. + if (IsWin32StructABI) { + if (TI.Width <= 512 && State.FreeSSERegs > 0) { + --State.FreeSSERegs; + return ABIArgInfo::getDirectInReg(); + } + return getIndirectResult(Ty, /*ByVal=*/false, State); + } + // On Darwin, some vectors are passed in memory, we handle this by passing // it as an i8/i16/i32/i64. if (IsDarwinVectorABI) { - uint64_t Size = getContext().getTypeSize(Ty); - if ((Size == 8 || Size == 16 || Size == 32) || - (Size == 64 && VT->getNumElements() == 1)) - return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), - Size)); + if ((TI.Width == 8 || TI.Width == 16 || TI.Width == 32) || + (TI.Width == 64 && VT->getNumElements() == 1)) + return ABIArgInfo::getDirect( + llvm::IntegerType::get(getVMContext(), TI.Width)); } if (IsX86_MMXType(CGT.ConvertType(Ty))) @@ -1813,9 +1829,10 @@ void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const { CCState State(FI); if (IsMCUABI) State.FreeRegs = 3; - else if (State.CC == llvm::CallingConv::X86_FastCall) + else if (State.CC == llvm::CallingConv::X86_FastCall) { State.FreeRegs = 2; - else if (State.CC == llvm::CallingConv::X86_VectorCall) { + State.FreeSSERegs = 3; + } else if (State.CC == llvm::CallingConv::X86_VectorCall) { State.FreeRegs = 2; State.FreeSSERegs = 6; } else if (FI.getHasRegParm()) @@ -1823,6 +1840,11 @@ void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const { else if (State.CC == llvm::CallingConv::X86_RegCall) { State.FreeRegs = 5; State.FreeSSERegs = 8; + } else if (IsWin32StructABI) { + // Since MSVC 2015, the first three SSE vectors have been passed in + // registers. The rest are passed indirectly. + State.FreeRegs = DefaultNumRegisterParameters; + State.FreeSSERegs = 3; } else State.FreeRegs = DefaultNumRegisterParameters; @@ -1869,16 +1891,25 @@ X86_32ABIInfo::addFieldToArgStruct(SmallVector &FrameFields, CharUnits &StackOffset, ABIArgInfo &Info, QualType Type) const { // Arguments are always 4-byte-aligned. - CharUnits FieldAlign = CharUnits::fromQuantity(4); + CharUnits WordSize = CharUnits::fromQuantity(4); + assert(StackOffset.isMultipleOf(WordSize) && "unaligned inalloca struct"); - assert(StackOffset.isMultipleOf(FieldAlign) && "unaligned inalloca struct"); - Info = ABIArgInfo::getInAlloca(FrameFields.size()); - FrameFields.push_back(CGT.ConvertTypeForMem(Type)); - StackOffset += getContext().getTypeSizeInChars(Type); + // sret pointers and indirect things will require an extra pointer + // indirection, unless they are byval. Most things are byval, and will not + // require this indirection. + bool IsIndirect = false; + if (Info.isIndirect() && !Info.getIndirectByVal()) + IsIndirect = true; + Info = ABIArgInfo::getInAlloca(FrameFields.size(), IsIndirect); + llvm::Type *LLTy = CGT.ConvertTypeForMem(Type); + if (IsIndirect) + LLTy = LLTy->getPointerTo(0); + FrameFields.push_back(LLTy); + StackOffset += IsIndirect ? WordSize : getContext().getTypeSizeInChars(Type); // Insert padding bytes to respect alignment. CharUnits FieldEnd = StackOffset; - StackOffset = FieldEnd.alignTo(FieldAlign); + StackOffset = FieldEnd.alignTo(WordSize); if (StackOffset != FieldEnd) { CharUnits NumBytes = StackOffset - FieldEnd; llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext()); @@ -1892,16 +1923,12 @@ static bool isArgInAlloca(const ABIArgInfo &Info) { switch (Info.getKind()) { case ABIArgInfo::InAlloca: return true; - case ABIArgInfo::Indirect: - assert(Info.getIndirectByVal()); - return true; case ABIArgInfo::Ignore: return false; + case ABIArgInfo::Indirect: case ABIArgInfo::Direct: case ABIArgInfo::Extend: - if (Info.getInReg()) - return false; - return true; + return !Info.getInReg(); case ABIArgInfo::Expand: case ABIArgInfo::CoerceAndExpand: // These are aggregate types which are never passed in registers when @@ -1935,8 +1962,7 @@ void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const { // Put the sret parameter into the inalloca struct if it's in memory. if (Ret.isIndirect() && !Ret.getInReg()) { - CanQualType PtrTy = getContext().getPointerType(FI.getReturnType()); - addFieldToArgStruct(FrameFields, StackOffset, Ret, PtrTy); + addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType()); // On Windows, the hidden sret parameter is always returned in eax. Ret.setInAllocaSRet(IsWin32StructABI); } diff --git a/clang/test/CodeGen/x86_32-arguments-win32.c b/clang/test/CodeGen/x86_32-arguments-win32.c index 65e25f32c250..33a6216a62bd 100644 --- a/clang/test/CodeGen/x86_32-arguments-win32.c +++ b/clang/test/CodeGen/x86_32-arguments-win32.c @@ -46,3 +46,47 @@ struct s6 { struct s6 f6_1(void) { while (1) {} } void f6_2(struct s6 a0) {} + +// MSVC passes up to three vectors in registers, and the rest indirectly. We +// (arbitrarily) pass oversized vectors indirectly, since that is the safest way +// to do it. +typedef float __m128 __attribute__((__vector_size__(16), __aligned__(16))); +typedef float __m256 __attribute__((__vector_size__(32), __aligned__(32))); +typedef float __m512 __attribute__((__vector_size__(64), __aligned__(64))); +typedef float __m1024 __attribute__((__vector_size__(128), __aligned__(128))); + +__m128 gv128; +__m256 gv256; +__m512 gv512; +__m1024 gv1024; + +void receive_vec_128(__m128 x, __m128 y, __m128 z, __m128 w, __m128 q) { + gv128 = x + y + z + w + q; +} +void receive_vec_256(__m256 x, __m256 y, __m256 z, __m256 w, __m256 q) { + gv256 = x + y + z + w + q; +} +void receive_vec_512(__m512 x, __m512 y, __m512 z, __m512 w, __m512 q) { + gv512 = x + y + z + w + q; +} +void receive_vec_1024(__m1024 x, __m1024 y, __m1024 z, __m1024 w, __m1024 q) { + gv1024 = x + y + z + w + q; +} +// CHECK-LABEL: define dso_local void @receive_vec_128(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, <4 x float>* %0, <4 x float>* %1) +// CHECK-LABEL: define dso_local void @receive_vec_256(<8 x float> inreg %x, <8 x float> inreg %y, <8 x float> inreg %z, <8 x float>* %0, <8 x float>* %1) +// CHECK-LABEL: define dso_local void @receive_vec_512(<16 x float> inreg %x, <16 x float> inreg %y, <16 x float> inreg %z, <16 x float>* %0, <16 x float>* %1) +// CHECK-LABEL: define dso_local void @receive_vec_1024(<32 x float>* %0, <32 x float>* %1, <32 x float>* %2, <32 x float>* %3, <32 x float>* %4) + +void pass_vec_128() { + __m128 z = {0}; + receive_vec_128(z, z, z, z, z); +} + +// CHECK-LABEL: define dso_local void @pass_vec_128() +// CHECK: call void @receive_vec_128(<4 x float> inreg %{{[^,)]*}}, <4 x float> inreg %{{[^,)]*}}, <4 x float> inreg %{{[^,)]*}}, <4 x float>* %{{[^,)]*}}, <4 x float>* %{{[^,)]*}}) + + +void __fastcall fastcall_indirect_vec(__m128 x, __m128 y, __m128 z, __m128 w, int edx, __m128 q) { + gv128 = x + y + z + w + q; +} +// CHECK-LABEL: define dso_local x86_fastcallcc void @"\01@fastcall_indirect_vec@84"(<4 x float> inreg %x, <4 x float> inreg %y, <4 x float> inreg %z, <4 x float>* inreg %0, i32 inreg %edx, <4 x float>* %1) diff --git a/clang/test/CodeGenCXX/inalloca-overaligned.cpp b/clang/test/CodeGenCXX/inalloca-overaligned.cpp new file mode 100644 index 000000000000..910f0d92895e --- /dev/null +++ b/clang/test/CodeGenCXX/inalloca-overaligned.cpp @@ -0,0 +1,52 @@ +// RUN: %clang_cc1 -fms-extensions -w -triple i386-pc-win32 -emit-llvm -o - %s | FileCheck %s + +// PR44395 +// MSVC passes overaligned types indirectly since MSVC 2015. Make sure that +// works with inalloca. + +// FIXME: Pass non-trivial *and* overaligned types indirectly. Right now the C++ +// ABI rules say to use inalloca, and they take precedence, so it's not easy to +// implement this. + + +struct NonTrivial { + NonTrivial(); + NonTrivial(const NonTrivial &o); + int x; +}; + +struct __declspec(align(64)) OverAligned { + OverAligned(); + int buf[16]; +}; + +extern int gvi32; + +int receive_inalloca_overaligned(NonTrivial nt, OverAligned o) { + return nt.x + o.buf[0]; +} + +// CHECK-LABEL: define dso_local i32 @"?receive_inalloca_overaligned@@Y{{.*}}" +// CHECK-SAME: (<{ %struct.NonTrivial, %struct.OverAligned* }>* inalloca %0) + +int pass_inalloca_overaligned() { + gvi32 = receive_inalloca_overaligned(NonTrivial(), OverAligned()); + return gvi32; +} + +// CHECK-LABEL: define dso_local i32 @"?pass_inalloca_overaligned@@Y{{.*}}" +// CHECK: [[TMP:%[^ ]*]] = alloca %struct.OverAligned, align 64 +// CHECK: call i8* @llvm.stacksave() +// CHECK: alloca inalloca <{ %struct.NonTrivial, %struct.OverAligned* }> + +// Construct OverAligned into TMP. +// CHECK: call x86_thiscallcc %struct.OverAligned* @"??0OverAligned@@QAE@XZ"(%struct.OverAligned* [[TMP]]) + +// Construct NonTrivial into the GEP. +// CHECK: [[GEP:%[^ ]*]] = getelementptr inbounds <{ %struct.NonTrivial, %struct.OverAligned* }>, <{ %struct.NonTrivial, %struct.OverAligned* }>* %{{.*}}, i32 0, i32 0 +// CHECK: call x86_thiscallcc %struct.NonTrivial* @"??0NonTrivial@@QAE@XZ"(%struct.NonTrivial* [[GEP]]) + +// Store the address of an OverAligned temporary into the struct. +// CHECK: getelementptr inbounds <{ %struct.NonTrivial, %struct.OverAligned* }>, <{ %struct.NonTrivial, %struct.OverAligned* }>* %{{.*}}, i32 0, i32 1 +// CHECK: store %struct.OverAligned* [[TMP]], %struct.OverAligned** %{{.*}}, align 4 +// CHECK: call i32 @"?receive_inalloca_overaligned@@Y{{.*}}"(<{ %struct.NonTrivial, %struct.OverAligned* }>* inalloca %argmem) diff --git a/clang/test/CodeGenCXX/inalloca-vector.cpp b/clang/test/CodeGenCXX/inalloca-vector.cpp new file mode 100644 index 000000000000..f3d7f81e9443 --- /dev/null +++ b/clang/test/CodeGenCXX/inalloca-vector.cpp @@ -0,0 +1,79 @@ +// RUN: %clang_cc1 -w -triple i686-pc-win32 -emit-llvm -o - %s | FileCheck %s + +// PR44395 +// MSVC passes up to three vectors in registers, and the rest indirectly. Check +// that both are compatible with an inalloca prototype. + +struct NonTrivial { + NonTrivial(); + NonTrivial(const NonTrivial &o); + unsigned handle; +}; + +typedef float __m128 __attribute__((__vector_size__(16), __aligned__(16))); +__m128 gv128; + +// nt, w, and q will be in the inalloca pack. +void receive_vec_128(NonTrivial nt, __m128 x, __m128 y, __m128 z, __m128 w, __m128 q) { + gv128 = x + y + z + w + q; +} +// CHECK-LABEL: define dso_local void @"?receive_vec_128@@YAXUNonTrivial@@T__m128@@1111@Z" +// CHECK-SAME: (<4 x float> inreg %x, +// CHECK-SAME: <4 x float> inreg %y, +// CHECK-SAME: <4 x float> inreg %z, +// CHECK-SAME: <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* inalloca %0) + +void pass_vec_128() { + __m128 z = {0}; + receive_vec_128(NonTrivial(), z, z, z, z, z); +} +// CHECK-LABEL: define dso_local void @"?pass_vec_128@@YAXXZ"() +// CHECK: getelementptr inbounds <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>, <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* %{{[^,]*}}, i32 0, i32 0 +// CHECK: call x86_thiscallcc %struct.NonTrivial* @"??0NonTrivial@@QAE@XZ"(%struct.NonTrivial* %{{.*}}) + +// Store q, store temp alloca. +// CHECK: store <4 x float> %{{[^,]*}}, <4 x float>* %{{[^,]*}}, align 16 +// CHECK: getelementptr inbounds <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>, <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* %{{[^,]*}}, i32 0, i32 1 +// CHECK: store <4 x float>* %{{[^,]*}}, <4 x float>** %{{[^,]*}}, align 4 + +// Store w, store temp alloca. +// CHECK: store <4 x float> %{{[^,]*}}, <4 x float>* %{{[^,]*}}, align 16 +// CHECK: getelementptr inbounds <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>, <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* %{{[^,]*}}, i32 0, i32 2 +// CHECK: store <4 x float>* %{{[^,]*}}, <4 x float>** %{{[^,]*}}, align 4 + +// CHECK: call void @"?receive_vec_128@@YAXUNonTrivial@@T__m128@@1111@Z" +// CHECK-SAME: (<4 x float> inreg %{{[^,]*}}, +// CHECK-SAME: <4 x float> inreg %{{[^,]*}}, +// CHECK-SAME: <4 x float> inreg %{{[^,]*}}, +// CHECK-SAME: <{ %struct.NonTrivial, <4 x float>*, <4 x float>* }>* inalloca %{{[^,]*}}) + +// w will be passed indirectly by register, and q will be passed indirectly, but +// the pointer will be in memory. +void __fastcall fastcall_receive_vec(__m128 x, __m128 y, __m128 z, __m128 w, int edx, __m128 q, NonTrivial nt) { + gv128 = x + y + z + w + q; +} +// CHECK-LABEL: define dso_local x86_fastcallcc void @"?fastcall_receive_vec@@Y{{[^"]*}}" +// CHECK-SAME: (<4 x float> inreg %x, +// CHECK-SAME: <4 x float> inreg %y, +// CHECK-SAME: <4 x float> inreg %z, +// CHECK-SAME: <4 x float>* inreg %0, +// CHECK-SAME: i32 inreg %edx, +// CHECK-SAME: <{ <4 x float>*, %struct.NonTrivial }>* inalloca %1) + + +void __vectorcall vectorcall_receive_vec(double xmm0, double xmm1, double xmm2, + __m128 x, __m128 y, __m128 z, + __m128 w, int edx, __m128 q, NonTrivial nt) { + gv128 = x + y + z + w + q; +} +// FIXME: Enable these checks, clang generates wrong IR. +// CHECK-LABEL: define dso_local x86_vectorcallcc void @"?vectorcall_receive_vec@@Y{{[^"]*}}" +// CHECKX-SAME: (double inreg %xmm0, +// CHECKX-SAME: double inreg %xmm1, +// CHECKX-SAME: double inreg %xmm2, +// CHECKX-SAME: <4 x float> inreg %x, +// CHECKX-SAME: <4 x float> inreg %y, +// CHECKX-SAME: <4 x float> inreg %z, +// CHECKX-SAME: <4 x float>* inreg %0, +// CHECKX-SAME: i32 inreg %edx, +// CHECKX-SAME: <{ <4 x float>*, %struct.NonTrivial }>* inalloca %1) -- GitLab From 3a312c3ee5f946ca18fb87d25f6f32fd5dc755ac Mon Sep 17 00:00:00 2001 From: Austin Kerbow Date: Fri, 7 Feb 2020 08:29:23 -0800 Subject: [PATCH 100/142] [AMDGPU][GlobalISel] Refactor selectDS1Addr1Offset/selectDS64Bit4ByteAligned Differential Revision: https://reviews.llvm.org/D74261 --- .../AMDGPU/AMDGPUInstructionSelector.cpp | 58 +++++++++---------- .../Target/AMDGPU/AMDGPUInstructionSelector.h | 6 +- .../GlobalISel/llvm.amdgcn.atomic.dec.ll | 20 +++---- .../GlobalISel/llvm.amdgcn.atomic.inc.ll | 30 ++++------ 4 files changed, 51 insertions(+), 63 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 600988a8080f..935db23da635 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -2374,18 +2374,16 @@ AMDGPUInstructionSelector::selectDS1Addr1OffsetImpl(MachineOperand &Root) const return std::make_pair(Root.getReg(), 0); int64_t ConstAddr = 0; - if (isBaseWithConstantOffset(Root, *MRI)) { - const MachineOperand &LHS = RootDef->getOperand(1); - const MachineOperand &RHS = RootDef->getOperand(2); - const MachineInstr *LHSDef = MRI->getVRegDef(LHS.getReg()); - const MachineInstr *RHSDef = MRI->getVRegDef(RHS.getReg()); - if (LHSDef && RHSDef) { - int64_t PossibleOffset = - RHSDef->getOperand(1).getCImm()->getSExtValue(); - if (isDSOffsetLegal(LHS.getReg(), PossibleOffset, 16)) { - // (add n0, c0) - return std::make_pair(LHS.getReg(), PossibleOffset); - } + + Register PtrBase; + int64_t Offset; + std::tie(PtrBase, Offset) = + getPtrBaseWithConstantOffset(Root.getReg(), *MRI); + + if (Offset) { + if (isDSOffsetLegal(PtrBase, Offset, 16)) { + // (add n0, c0) + return std::make_pair(PtrBase, Offset); } } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { // TODO @@ -2401,7 +2399,6 @@ AMDGPUInstructionSelector::selectDS1Addr1OffsetImpl(MachineOperand &Root) const InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectDS1Addr1Offset(MachineOperand &Root) const { - Register Reg; unsigned Offset; std::tie(Reg, Offset) = selectDS1Addr1OffsetImpl(Root); @@ -2413,19 +2410,26 @@ AMDGPUInstructionSelector::selectDS1Addr1Offset(MachineOperand &Root) const { InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectDS64Bit4ByteAligned(MachineOperand &Root) const { + Register Reg; + unsigned Offset; + std::tie(Reg, Offset) = selectDS64Bit4ByteAlignedImpl(Root); + return {{ + [=](MachineInstrBuilder &MIB) { MIB.addReg(Reg); }, + [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset); }, + [=](MachineInstrBuilder &MIB) { MIB.addImm(Offset+1); } + }}; +} + +std::pair +AMDGPUInstructionSelector::selectDS64Bit4ByteAlignedImpl(MachineOperand &Root) const { const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); - if (!RootDef) { - return {{ - [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, - [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, - [=](MachineInstrBuilder &MIB) { MIB.addImm(1); } - }}; - } + if (!RootDef) + return std::make_pair(Root.getReg(), 0); int64_t ConstAddr = 0; + Register PtrBase; int64_t Offset; - std::tie(PtrBase, Offset) = getPtrBaseWithConstantOffset(Root.getReg(), *MRI); @@ -2434,11 +2438,7 @@ AMDGPUInstructionSelector::selectDS64Bit4ByteAligned(MachineOperand &Root) const int64_t DWordOffset1 = DWordOffset0 + 1; if (isDSOffsetLegal(PtrBase, DWordOffset1, 8)) { // (add n0, c0) - return {{ - [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrBase); }, - [=](MachineInstrBuilder &MIB) { MIB.addImm(DWordOffset0); }, - [=](MachineInstrBuilder &MIB) { MIB.addImm(DWordOffset1); } - }}; + return std::make_pair(PtrBase, DWordOffset0); } } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { // TODO @@ -2448,11 +2448,7 @@ AMDGPUInstructionSelector::selectDS64Bit4ByteAligned(MachineOperand &Root) const } - return {{ - [=](MachineInstrBuilder &MIB) { MIB.add(Root); }, - [=](MachineInstrBuilder &MIB) { MIB.addImm(0); }, - [=](MachineInstrBuilder &MIB) { MIB.addImm(1); } - }}; + return std::make_pair(Root.getReg(), 0); } /// If \p Root is a G_PTR_ADD with a G_CONSTANT on the right hand side, return diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h index 38b76a76299f..d440932c72dd 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -175,10 +175,12 @@ private: unsigned OffsetBits) const; std::pair - selectDS1Addr1OffsetImpl(MachineOperand &Src) const; - + selectDS1Addr1OffsetImpl(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns selectDS1Addr1Offset(MachineOperand &Root) const; + + std::pair + selectDS64Bit4ByteAlignedImpl(MachineOperand &Root) const; InstructionSelector::ComplexRendererFns selectDS64Bit4ByteAligned(MachineOperand &Root) const; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll index 32bef20c9ffd..3cad9f11bdba 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll @@ -1141,10 +1141,9 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 ; CI-NEXT: v_add_i32_e32 v2, vcc, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 0, v0 -; CI-NEXT: v_add_i32_e32 v0, vcc, 8, v0 ; CI-NEXT: v_mov_b32_e32 v1, 9 ; CI-NEXT: s_mov_b32 m0, -1 -; CI-NEXT: ds_dec_rtn_u32 v3, v0, v1 +; CI-NEXT: ds_dec_rtn_u32 v3, v0, v1 offset:8 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v0, s2 ; CI-NEXT: v_mov_b32_e32 v1, s3 @@ -1160,10 +1159,9 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 ; VI-NEXT: v_add_u32_e32 v2, vcc, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 0, v0 -; VI-NEXT: v_add_u32_e32 v0, vcc, 8, v0 ; VI-NEXT: v_mov_b32_e32 v1, 9 ; VI-NEXT: s_mov_b32 m0, -1 -; VI-NEXT: ds_dec_rtn_u32 v3, v0, v1 +; VI-NEXT: ds_dec_rtn_u32 v3, v0, v1 offset:8 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v1, s3 @@ -1708,15 +1706,14 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspa define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { ; CI-LABEL: atomic_dec_shl_base_lds_0_i64: ; CI: ; %bb.0: +; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: v_add_i32_e32 v4, vcc, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 -; CI-NEXT: v_add_i32_e32 v0, vcc, 0, v0 -; CI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 +; CI-NEXT: v_add_i32_e32 v2, vcc, 0, v0 ; CI-NEXT: v_mov_b32_e32 v0, 9 ; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: s_mov_b32 m0, -1 -; CI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1] +; CI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1] offset:16 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v2, s2 ; CI-NEXT: v_mov_b32_e32 v3, s3 @@ -1728,15 +1725,14 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, ; ; VI-LABEL: atomic_dec_shl_base_lds_0_i64: ; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 -; VI-NEXT: v_add_u32_e32 v0, vcc, 0, v0 -; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0, v0 ; VI-NEXT: v_mov_b32_e32 v0, 9 ; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: s_mov_b32 m0, -1 -; VI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1] +; VI-NEXT: ds_dec_rtn_u64 v[0:1], v2, v[0:1] offset:16 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v3, s3 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll index 1f42aa8a67bc..f4b01506ad45 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll @@ -506,10 +506,9 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, ; CI-NEXT: v_add_i32_e32 v2, vcc, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 0, v0 -; CI-NEXT: v_add_i32_e32 v0, vcc, 8, v0 ; CI-NEXT: v_mov_b32_e32 v1, 9 ; CI-NEXT: s_mov_b32 m0, -1 -; CI-NEXT: ds_inc_rtn_u32 v3, v0, v1 +; CI-NEXT: ds_inc_rtn_u32 v3, v0, v1 offset:8 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v0, s2 ; CI-NEXT: v_mov_b32_e32 v1, s3 @@ -525,10 +524,9 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, ; VI-NEXT: v_add_u32_e32 v2, vcc, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, 0, v0 -; VI-NEXT: v_add_u32_e32 v0, vcc, 8, v0 ; VI-NEXT: v_mov_b32_e32 v1, 9 ; VI-NEXT: s_mov_b32 m0, -1 -; VI-NEXT: ds_inc_rtn_u32 v3, v0, v1 +; VI-NEXT: ds_inc_rtn_u32 v3, v0, v1 offset:8 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v1, s3 @@ -544,9 +542,8 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, ; GFX9-NEXT: v_add_u32_e32 v2, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, 0, v0 -; GFX9-NEXT: v_add_u32_e32 v0, 8, v0 ; GFX9-NEXT: v_mov_b32_e32 v1, 9 -; GFX9-NEXT: ds_inc_rtn_u32 v3, v0, v1 +; GFX9-NEXT: ds_inc_rtn_u32 v3, v0, v1 offset:8 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 @@ -1279,15 +1276,14 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0 define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { ; CI-LABEL: atomic_inc_shl_base_lds_0_i64: ; CI: ; %bb.0: +; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: v_add_i32_e32 v4, vcc, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 -; CI-NEXT: v_add_i32_e32 v0, vcc, 0, v0 -; CI-NEXT: v_add_i32_e32 v2, vcc, 16, v0 +; CI-NEXT: v_add_i32_e32 v2, vcc, 0, v0 ; CI-NEXT: v_mov_b32_e32 v0, 9 ; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: s_mov_b32 m0, -1 -; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] +; CI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] offset:16 ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v2, s2 ; CI-NEXT: v_mov_b32_e32 v3, s3 @@ -1299,15 +1295,14 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, ; ; VI-LABEL: atomic_inc_shl_base_lds_0_i64: ; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: v_add_u32_e32 v4, vcc, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 -; VI-NEXT: v_add_u32_e32 v0, vcc, 0, v0 -; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0 +; VI-NEXT: v_add_u32_e32 v2, vcc, 0, v0 ; VI-NEXT: v_mov_b32_e32 v0, 9 ; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: s_mov_b32 m0, -1 -; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] +; VI-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] offset:16 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v2, s2 ; VI-NEXT: v_mov_b32_e32 v3, s3 @@ -1319,14 +1314,13 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, ; ; GFX9-LABEL: atomic_inc_shl_base_lds_0_i64: ; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: v_add_u32_e32 v4, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 -; GFX9-NEXT: v_add_u32_e32 v0, 0, v0 -; GFX9-NEXT: v_add_u32_e32 v2, 16, v0 +; GFX9-NEXT: v_add_u32_e32 v2, 0, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, 9 ; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] +; GFX9-NEXT: ds_inc_rtn_u64 v[0:1], v2, v[0:1] offset:16 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s3 -- GitLab From 7096d588d353aea0e619e3f52e887d49f5e8ee55 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 11 Feb 2020 17:17:08 -0800 Subject: [PATCH 101/142] [test] Improve test/CodeGen/X86/linux-preemption.ll --- llvm/test/CodeGen/X86/linux-preemption.ll | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/llvm/test/CodeGen/X86/linux-preemption.ll b/llvm/test/CodeGen/X86/linux-preemption.ll index 5de8587038e7..3bf97112a840 100644 --- a/llvm/test/CodeGen/X86/linux-preemption.ll +++ b/llvm/test/CodeGen/X86/linux-preemption.ll @@ -228,3 +228,16 @@ define void()* @get_external_preemptable_function() { ; COMMON: {{^}}strong_local_global: ; COMMON-NEXT .Lstrong_local_global: + +; COMMON: .globl strong_default_alias +; COMMON-NEXT: .set strong_default_alias, aliasee +; COMMON-NEXT: .weak weak_default_alias +; COMMON-NEXT: .set weak_default_alias, aliasee +; COMMON-NEXT: .globl strong_local_alias +; COMMON-NEXT: .set strong_local_alias, aliasee +; COMMON-NEXT: .weak weak_local_alias +; COMMON-NEXT: .set weak_local_alias, aliasee +; COMMON-NEXT: .globl strong_preemptable_alias +; COMMON-NEXT: .set strong_preemptable_alias, aliasee +; COMMON-NEXT: .weak weak_preemptable_alias +; COMMON-NEXT: .set weak_preemptable_alias, aliasee -- GitLab From 2f172d8d3c10ea7538818cbfffeb54ef30bb1a11 Mon Sep 17 00:00:00 2001 From: Sam Clegg Date: Fri, 7 Feb 2020 18:15:15 -0800 Subject: [PATCH 102/142] [compiler-rt] Compile __powitf2 under wasm See https://github.com/emscripten-core/emscripten/issues/10374 See https://reviews.llvm.org/D74274 Differential Revision: https://reviews.llvm.org/D74275 --- compiler-rt/lib/builtins/powitf2.c | 5 +++-- compiler-rt/test/builtins/Unit/powitf2_test.c | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/compiler-rt/lib/builtins/powitf2.c b/compiler-rt/lib/builtins/powitf2.c index fcbdb4c2ee2a..141a3a0ea727 100644 --- a/compiler-rt/lib/builtins/powitf2.c +++ b/compiler-rt/lib/builtins/powitf2.c @@ -10,9 +10,10 @@ // //===----------------------------------------------------------------------===// -#include "int_lib.h" +#define QUAD_PRECISION +#include "fp_lib.h" -#if _ARCH_PPC +#if defined(CRT_HAS_128BIT) && defined(CRT_LDBL_128BIT) // Returns: a ^ b diff --git a/compiler-rt/test/builtins/Unit/powitf2_test.c b/compiler-rt/test/builtins/Unit/powitf2_test.c index 70bc6dae0d2d..fd25f38d5177 100644 --- a/compiler-rt/test/builtins/Unit/powitf2_test.c +++ b/compiler-rt/test/builtins/Unit/powitf2_test.c @@ -14,7 +14,7 @@ #include -#if _ARCH_PPC +#if __LDBL_MANT_DIG__ == 113 #include "int_lib.h" #include @@ -37,7 +37,7 @@ int test__powitf2(long double a, si_int b, long double expected) int main() { -#if _ARCH_PPC +#if __LDBL_MANT_DIG__ == 113 if (test__powitf2(0, 0, 1)) return 1; if (test__powitf2(1, 0, 1)) -- GitLab From b062fe181625bd1944ca9ca2a58246ffd7cd3536 Mon Sep 17 00:00:00 2001 From: Sam Clegg Date: Thu, 19 Dec 2019 17:30:24 -0800 Subject: [PATCH 103/142] [lld][WebAssembly] Fail if bitcode objects are pulled in after LTO This can happen if lto::LTO::getRuntimeLibcallSymbols doesn't return an complete/accurate list of libcalls. In this case new bitcode object can be linked in after LTO. For example the WebAssembly backend currently calls: setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2"); But `__truncsfhf2` is not part of `getRuntimeLibcallSymbols` so if this symbol is generated during LTO the link will currently fail. Without this change the linker crashes because the bitcode symbol makes it all the way to the output phase. See: https://bugs.llvm.org/show_bug.cgi?id=44353 Differential Revision: https://reviews.llvm.org/D71632 --- .../wasm/lto/Inputs/libcall-truncsfhf2.ll | 6 ++++++ lld/test/wasm/lto/libcall-truncsfhf2.ll | 20 +++++++++++++++++++ lld/wasm/InputFiles.cpp | 8 ++++++++ lld/wasm/InputFiles.h | 4 ++++ lld/wasm/SymbolTable.cpp | 3 +++ 5 files changed, 41 insertions(+) create mode 100644 lld/test/wasm/lto/Inputs/libcall-truncsfhf2.ll create mode 100644 lld/test/wasm/lto/libcall-truncsfhf2.ll diff --git a/lld/test/wasm/lto/Inputs/libcall-truncsfhf2.ll b/lld/test/wasm/lto/Inputs/libcall-truncsfhf2.ll new file mode 100644 index 000000000000..839890ee1d9a --- /dev/null +++ b/lld/test/wasm/lto/Inputs/libcall-truncsfhf2.ll @@ -0,0 +1,6 @@ +target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" +target triple = "wasm32-unknown-unknown" + +define half @__truncsfhf2(float) { + ret half 0.0 +} diff --git a/lld/test/wasm/lto/libcall-truncsfhf2.ll b/lld/test/wasm/lto/libcall-truncsfhf2.ll new file mode 100644 index 000000000000..a427acd139d8 --- /dev/null +++ b/lld/test/wasm/lto/libcall-truncsfhf2.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as %s -o %t.o +; RUN: llvm-as %p/Inputs/libcall-truncsfhf2.ll -o %t.truncsfhf2.o +; RUN: rm -f %t.a +; RUN: llvm-ar rcs %t.a %t.truncsfhf2.o +; RUN: not wasm-ld --export-all %t.o %t.a -o %t.wasm 2>&1 | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" +target triple = "wasm32-unknown-unknown" + +@g_float = global float 0.0 +@g_half = global half 0.0 + +define void @_start() { + %val1 = load float, float* @g_float + %v0 = fptrunc float %val1 to half + store half %v0, half* @g_half + ret void +} + +; CHECK: wasm-ld: error: {{.*}}truncsfhf2.o: attempt to add bitcode file after LTO. diff --git a/lld/wasm/InputFiles.cpp b/lld/wasm/InputFiles.cpp index 2d96062739dc..d71a2b4f083d 100644 --- a/lld/wasm/InputFiles.cpp +++ b/lld/wasm/InputFiles.cpp @@ -536,7 +536,15 @@ static Symbol *createBitcodeSymbol(const std::vector &keptComdats, return symtab->addDefinedData(name, flags, &f, nullptr, 0, 0); } +bool BitcodeFile::doneLTO = false; + void BitcodeFile::parse() { + if (doneLTO) { + error(toString(mb.getBufferIdentifier()) + + ": attempt to add bitcode file after LTO."); + return; + } + obj = check(lto::InputFile::create(MemoryBufferRef( mb.getBuffer(), saver.save(archiveName + mb.getBufferIdentifier())))); Triple t(obj->getTargetTriple()); diff --git a/lld/wasm/InputFiles.h b/lld/wasm/InputFiles.h index d5aebf46b477..bf4a4ec99abf 100644 --- a/lld/wasm/InputFiles.h +++ b/lld/wasm/InputFiles.h @@ -160,6 +160,10 @@ public: void parse(); std::unique_ptr obj; + + // Set to true once LTO is complete in order prevent further bitcode objects + // being added. + static bool doneLTO; }; inline bool isBitcode(MemoryBufferRef mb) { diff --git a/lld/wasm/SymbolTable.cpp b/lld/wasm/SymbolTable.cpp index 3c1acbd2c68f..ce74b6ad7ea5 100644 --- a/lld/wasm/SymbolTable.cpp +++ b/lld/wasm/SymbolTable.cpp @@ -65,6 +65,9 @@ void SymbolTable::addFile(InputFile *file) { // Because all bitcode files that the program consists of are passed // to the compiler at once, it can do whole-program optimization. void SymbolTable::addCombinedLTOObject() { + // Prevent further LTO objects being included + BitcodeFile::doneLTO = true; + if (bitcodeFiles.empty()) return; -- GitLab From d6a5c31c0f739cd401702b898e3da3986466dffa Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Wed, 12 Feb 2020 02:05:31 +0000 Subject: [PATCH 104/142] Removed declared but non-existent createMaterializeVectorsPass() (NFC) --- mlir/include/mlir/Transforms/Passes.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/mlir/include/mlir/Transforms/Passes.h b/mlir/include/mlir/Transforms/Passes.h index 673f3db468d3..133b716e4c59 100644 --- a/mlir/include/mlir/Transforms/Passes.h +++ b/mlir/include/mlir/Transforms/Passes.h @@ -41,10 +41,6 @@ createVectorizePass(ArrayRef virtualVectorSize); /// FileCheck. std::unique_ptr> createVectorizerTestPass(); -/// Creates a pass to lower super-vectors to target-dependent HW vectors. -std::unique_ptr> -createMaterializeVectorsPass(ArrayRef vectorSize); - /// Creates a loop unrolling pass with the provided parameters. /// 'getUnrollFactor' is a function callback for clients to supply a function /// that computes an unroll factor - the callback takes precedence over unroll -- GitLab From 8cedf0e2994c1a258902ed931abdec5f94725a55 Mon Sep 17 00:00:00 2001 From: Yuanfang Chen Date: Mon, 10 Feb 2020 18:33:05 -0800 Subject: [PATCH 105/142] Reland "[Support] make report_fatal_error `abort` instead of `exit`" Summary: Reland D67847 after D73742 is committed. Replace `sys::Process::Exit(1)` with `abort` in `report_fatal_error`. After this patch, for tools turning on `CrashRecoveryContext`, crash handler installed by `CrashRecoveryContext` is called unless they installed a non-returning handler using `llvm::install_fatal_error_handler` like `cc1_main` currently does. Reviewers: rnk, MaskRay, aganea, hans, espindola, jhenderson Subscribers: jholewinski, qcolombet, dschuff, jyknight, emaste, sdardis, nemanjai, jvesely, nhaehnle, sbc100, jgravelle-google, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, steven_wu, rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, PkmX, rupprecht, jocewei, jsji, Jim, dmgreen, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74456 --- .../infrastructure/empty-database.cpp | 2 +- .../libclang/CrashTests/LibclangCrashTest.cpp | 6 ++-- lld/test/ELF/lto/ltopasses-custom.ll | 4 +-- llvm/docs/ProgrammersManual.rst | 4 +-- llvm/include/llvm/Support/ErrorHandling.h | 2 +- llvm/lib/Support/ErrorHandling.cpp | 2 +- ...talayout-invalid-function-ptr-alignment.ll | 2 +- ...alayout-invalid-stack-natural-alignment.ll | 2 +- llvm/test/Assembler/getInt.ll | 2 +- .../invalid-datalayout-alloca-addrspace.ll | 2 +- .../invalid-datalayout-program-addrspace.ll | 2 +- llvm/test/Assembler/invalid-datalayout1.ll | 2 +- llvm/test/Assembler/invalid-datalayout10.ll | 2 +- llvm/test/Assembler/invalid-datalayout11.ll | 2 +- llvm/test/Assembler/invalid-datalayout12.ll | 2 +- llvm/test/Assembler/invalid-datalayout13.ll | 2 +- llvm/test/Assembler/invalid-datalayout14.ll | 2 +- llvm/test/Assembler/invalid-datalayout15.ll | 2 +- llvm/test/Assembler/invalid-datalayout16.ll | 2 +- llvm/test/Assembler/invalid-datalayout17.ll | 2 +- llvm/test/Assembler/invalid-datalayout18.ll | 2 +- llvm/test/Assembler/invalid-datalayout19.ll | 2 +- llvm/test/Assembler/invalid-datalayout2.ll | 2 +- llvm/test/Assembler/invalid-datalayout20.ll | 2 +- llvm/test/Assembler/invalid-datalayout21.ll | 2 +- llvm/test/Assembler/invalid-datalayout22.ll | 2 +- llvm/test/Assembler/invalid-datalayout23.ll | 2 +- llvm/test/Assembler/invalid-datalayout24.ll | 2 +- llvm/test/Assembler/invalid-datalayout3.ll | 2 +- llvm/test/Assembler/invalid-datalayout4.ll | 2 +- llvm/test/Assembler/invalid-datalayout5.ll | 2 +- llvm/test/Assembler/invalid-datalayout6.ll | 2 +- llvm/test/Assembler/invalid-datalayout7.ll | 2 +- llvm/test/Assembler/invalid-datalayout8.ll | 2 +- llvm/test/Assembler/invalid-datalayout9.ll | 2 +- .../function-default-address-spaces.ll | 2 +- .../test/Bitcode/invalid-functionptr-align.ll | 2 +- llvm/test/Bitcode/invalid.test | 12 +++---- .../AArch64/GlobalISel/arm64-fallback.ll | 4 +-- .../GlobalISel/call-translator-musttail.ll | 2 +- .../GlobalISel/legalize-inttoptr-xfail-1.mir | 3 +- .../GlobalISel/legalize-inttoptr-xfail-2.mir | 3 +- .../AArch64/GlobalISel/no-neon-no-fp.ll | 2 +- .../CodeGen/AArch64/arm64-named-reg-alloc.ll | 4 +-- .../AArch64/arm64-named-reg-notareg.ll | 4 +-- .../CodeGen/AArch64/arm64-tls-dynamics.ll | 2 +- .../CodeGen/AArch64/arm64-tls-initial-exec.ll | 2 +- .../CodeGen/AArch64/fast-isel-sp-adjust.ll | 2 +- llvm/test/CodeGen/AArch64/tiny_supported.ll | 6 ++-- .../AMDGPU/GlobalISel/insertelement.ll | 2 +- .../inst-select-pattern-xor3.xfail.mir | 2 +- .../AMDGPU/GlobalISel/lds-zero-initializer.ll | 2 +- .../GlobalISel/legalize-atomicrmw-nand.mir | 2 +- .../legalize-atomicrmw-xchg-flat.mir | 2 +- .../AMDGPU/GlobalISel/legalize-jump-table.mir | 2 +- .../legalize-unmerge-values-xfail.mir | 2 +- .../llvm.amdgcn.ds.gws.sema.release.all.ll | 2 +- .../GlobalISel/regbankselect-illegal-copy.mir | 4 +-- .../AMDGPU/at-least-one-def-value-assert.mir | 2 +- .../test/CodeGen/AMDGPU/branch-relax-spill.ll | 2 +- .../AMDGPU/call-to-kernel-undefined.ll | 2 +- llvm/test/CodeGen/AMDGPU/call-to-kernel.ll | 2 +- .../test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll | 6 ++-- llvm/test/CodeGen/AMDGPU/div_i128.ll | 2 +- .../AMDGPU/flat-error-unsupported-gpu-hsa.ll | 6 ++-- llvm/test/CodeGen/AMDGPU/lds-initializer.ll | 4 +-- .../CodeGen/AMDGPU/lds-zero-initializer.ll | 4 +-- .../llvm.amdgcn.ds.gws.sema.release.all.ll | 2 +- .../AMDGPU/read-register-invalid-subtarget.ll | 2 +- .../AMDGPU/read-register-invalid-type-i32.ll | 2 +- .../AMDGPU/read-register-invalid-type-i64.ll | 2 +- .../CodeGen/AMDGPU/unsupported-image-a16.ll | 2 +- llvm/test/CodeGen/AMDGPU/verify-sop.mir | 2 +- llvm/test/CodeGen/ARM/codemodel.ll | 4 +-- llvm/test/CodeGen/ARM/ldc2l.ll | 4 +-- llvm/test/CodeGen/ARM/machine-verifier.mir | 2 +- llvm/test/CodeGen/ARM/named-reg-alloc.ll | 4 +-- llvm/test/CodeGen/ARM/named-reg-notareg.ll | 4 +-- llvm/test/CodeGen/ARM/special-reg-acore.ll | 2 +- llvm/test/CodeGen/ARM/special-reg-mcore.ll | 4 +-- llvm/test/CodeGen/ARM/special-reg-v8m-base.ll | 2 +- llvm/test/CodeGen/ARM/special-reg-v8m-main.ll | 2 +- llvm/test/CodeGen/ARM/ssat-lower.ll | 4 +-- llvm/test/CodeGen/ARM/ssat-upper.ll | 4 +-- llvm/test/CodeGen/ARM/ssat-v4t.ll | 2 +- llvm/test/CodeGen/ARM/stc2.ll | 4 +-- llvm/test/CodeGen/ARM/usat-lower.ll | 4 +-- llvm/test/CodeGen/ARM/usat-upper.ll | 4 +-- llvm/test/CodeGen/ARM/usat-v4t.ll | 2 +- llvm/test/CodeGen/BPF/sdiv_error.ll | 2 +- llvm/test/CodeGen/BPF/xadd.ll | 8 ++--- .../Generic/llc-start-stop-instance-errors.ll | 2 +- llvm/test/CodeGen/Generic/llc-start-stop.ll | 12 +++---- .../Generic/opt-codegen-no-target-machine.ll | 2 +- .../CodeGen/Hexagon/misaligned-const-load.ll | 2 +- .../CodeGen/Hexagon/misaligned-const-store.ll | 2 +- .../Hexagon/verify-liveness-at-def.mir | 4 +-- llvm/test/CodeGen/Lanai/codemodel.ll | 4 +-- .../test/CodeGen/MIR/X86/machine-verifier.mir | 2 +- .../MIR/X86/tied-physical-regs-match.mir | 2 +- .../test/CodeGen/Mips/Fast-ISel/double-arg.ll | 2 +- .../fast-isel-softfloat-lower-args.ll | 2 +- llvm/test/CodeGen/Mips/cpus-no-mips64.ll | 14 ++++---- llvm/test/CodeGen/Mips/cpus.ll | 4 +-- llvm/test/CodeGen/Mips/fp64a.ll | 6 ++-- llvm/test/CodeGen/Mips/fpxx.ll | 4 +-- .../guards-verify-call.mir | 2 +- .../guards-verify-tailcall.mir | 2 +- .../unsupported-micromips.ll | 2 +- .../unsupported-mips32.ll | 2 +- .../test/CodeGen/Mips/instverify/dext-pos.mir | 2 +- .../CodeGen/Mips/instverify/dext-size.mir | 2 +- .../Mips/instverify/dextm-pos-size.mir | 2 +- .../CodeGen/Mips/instverify/dextm-pos.mir | 2 +- .../CodeGen/Mips/instverify/dextm-size.mir | 2 +- .../Mips/instverify/dextu-pos-size.mir | 2 +- .../CodeGen/Mips/instverify/dextu-pos.mir | 2 +- .../CodeGen/Mips/instverify/dextu-size.mir | 2 +- .../CodeGen/Mips/instverify/dins-pos-size.mir | 2 +- .../test/CodeGen/Mips/instverify/dins-pos.mir | 2 +- .../CodeGen/Mips/instverify/dins-size.mir | 2 +- .../Mips/instverify/dinsm-pos-size.mir | 2 +- .../CodeGen/Mips/instverify/dinsm-pos.mir | 2 +- .../CodeGen/Mips/instverify/dinsm-size.mir | 2 +- .../Mips/instverify/dinsu-pos-size.mir | 2 +- .../CodeGen/Mips/instverify/dinsu-pos.mir | 2 +- .../CodeGen/Mips/instverify/dinsu-size.mir | 2 +- .../CodeGen/Mips/instverify/ext-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ext-pos.mir | 2 +- .../test/CodeGen/Mips/instverify/ext-size.mir | 2 +- .../CodeGen/Mips/instverify/ins-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ins-pos.mir | 2 +- .../test/CodeGen/Mips/instverify/ins-size.mir | 2 +- .../CodeGen/Mips/interrupt-attr-64-error.ll | 2 +- .../CodeGen/Mips/interrupt-attr-args-error.ll | 2 +- .../test/CodeGen/Mips/interrupt-attr-error.ll | 2 +- .../CodeGen/Mips/micromips64-unsupported.ll | 4 +-- .../CodeGen/Mips/mips32r6/compatibility.ll | 2 +- .../CodeGen/Mips/mips64r6/compatibility.ll | 2 +- llvm/test/CodeGen/Mips/msa/3r-a.ll | 2 +- llvm/test/CodeGen/Mips/msa/immediates-bad.ll | 2 +- llvm/test/CodeGen/NVPTX/alias.ll | 2 +- llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll | 2 +- llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll | 2 +- llvm/test/CodeGen/NVPTX/global-ctor.ll | 2 +- llvm/test/CodeGen/NVPTX/global-dtor.ll | 2 +- .../test/CodeGen/NVPTX/libcall-instruction.ll | 2 +- llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-byval-param.ll | 4 +-- llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll | 4 +-- llvm/test/CodeGen/PowerPC/aix-nest-param.ll | 4 +-- llvm/test/CodeGen/PowerPC/aix-trampoline.ll | 4 +-- .../PowerPC/aix-user-defined-memcpy.ll | 2 +- .../PowerPC/aix-xcoff-data-only-notoc.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll | 2 +- llvm/test/CodeGen/PowerPC/codemodel.ll | 4 +-- .../CodeGen/PowerPC/lower-globaladdr32-aix.ll | 2 +- .../CodeGen/PowerPC/lower-globaladdr64-aix.ll | 2 +- .../CodeGen/PowerPC/named-reg-alloc-r0.ll | 6 ++-- .../CodeGen/PowerPC/named-reg-alloc-r2-64.ll | 4 +-- .../CodeGen/PowerPC/named-reg-alloc-r2.ll | 2 +- llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll | 2 +- .../CodeGen/RISCV/get-register-invalid.ll | 2 +- .../CodeGen/RISCV/get-register-reserve.ll | 4 +-- .../RISCV/interrupt-attr-args-error.ll | 4 +-- .../CodeGen/RISCV/interrupt-attr-invalid.ll | 4 +-- .../CodeGen/RISCV/interrupt-attr-ret-error.ll | 4 +-- .../RISCV/mattr-invalid-combination.ll | 2 +- llvm/test/CodeGen/RISCV/module-target-abi.ll | 2 +- llvm/test/CodeGen/RISCV/module-target-abi2.ll | 2 +- llvm/test/CodeGen/RISCV/musttail-call.ll | 8 ++--- llvm/test/CodeGen/RISCV/rv32e.ll | 2 +- llvm/test/CodeGen/RISCV/target-abi-valid.ll | 2 +- llvm/test/CodeGen/RISCV/verify-instr.mir | 2 +- llvm/test/CodeGen/SPARC/codemodel.ll | 4 +-- llvm/test/CodeGen/SPARC/fail-alloca-align.ll | 4 +-- llvm/test/CodeGen/SPARC/sret-secondary.ll | 2 +- llvm/test/CodeGen/SystemZ/codemodel.ll | 4 +-- llvm/test/CodeGen/SystemZ/ghc-cc-02.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-03.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-04.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-05.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-06.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-07.ll | 2 +- llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll | 2 +- .../test/CodeGen/SystemZ/mrecord-mcount-02.ll | 2 +- llvm/test/CodeGen/SystemZ/mverify-optypes.mir | 3 +- .../test/CodeGen/SystemZ/vec-args-error-01.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-02.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-03.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-04.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-05.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-06.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-07.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-08.ll | 2 +- llvm/test/CodeGen/WebAssembly/clear-cache.ll | 2 +- llvm/test/CodeGen/WebAssembly/cpus.ll | 8 ++--- llvm/test/CodeGen/WebAssembly/exception.ll | 2 +- .../CodeGen/WebAssembly/offset-atomics.ll | 2 +- .../WebAssembly/tls-general-dynamic.ll | 4 +-- llvm/test/CodeGen/X86/AppendingLinkage.ll | 2 +- .../X86/GlobalISel/avoid-matchtable-crash.mir | 2 +- ...fi-inserter-verify-inconsistent-offset.mir | 2 +- ...-inserter-verify-inconsistent-register.mir | 2 +- llvm/test/CodeGen/X86/clwb.ll | 2 +- llvm/test/CodeGen/X86/codemodel.ll | 2 +- llvm/test/CodeGen/X86/coff-comdat2.ll | 2 +- llvm/test/CodeGen/X86/coff-comdat3.ll | 2 +- llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll | 18 +++++------ llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll | 32 +++++++++---------- llvm/test/CodeGen/X86/cpus-no-x86_64.ll | 8 ++--- llvm/test/CodeGen/X86/equiv_with_fndef.ll | 2 +- llvm/test/CodeGen/X86/equiv_with_vardef.ll | 2 +- .../expand-integer-x86_64-intrinsic-error.ll | 2 +- llvm/test/CodeGen/X86/fast-isel-args-fail2.ll | 3 +- llvm/test/CodeGen/X86/inalloca-regparm.ll | 2 +- llvm/test/CodeGen/X86/invalid-liveness.mir | 2 +- llvm/test/CodeGen/X86/label-redefinition.ll | 2 +- .../CodeGen/X86/llc-print-machineinstrs.mir | 2 +- llvm/test/CodeGen/X86/macho-comdat.ll | 2 +- llvm/test/CodeGen/X86/named-reg-alloc.ll | 4 +-- llvm/test/CodeGen/X86/named-reg-notareg.ll | 4 +-- llvm/test/CodeGen/X86/nonconst-static-ev.ll | 2 +- llvm/test/CodeGen/X86/nonconst-static-iv.ll | 2 +- .../CodeGen/X86/read-fp-no-frame-pointer.ll | 2 +- llvm/test/CodeGen/X86/segmented-stacks.ll | 4 +-- llvm/test/CodeGen/XCore/alignment.ll | 2 +- llvm/test/CodeGen/XCore/codemodel.ll | 6 ++-- llvm/test/CodeGen/XCore/section-name.ll | 2 +- .../DebugInfo/COFF/types-recursive-unnamed.ll | 2 +- llvm/test/LTO/X86/attrs.ll | 2 +- .../illegal-subtarget-change.s | 2 +- llvm/test/MC/ARM/Windows/invalid-relocation.s | 2 +- llvm/test/MC/COFF/section-comdat-conflict.s | 2 +- llvm/test/MC/COFF/section-comdat-conflict2.s | 2 +- .../MC/Disassembler/AMDGPU/si-support.txt | 2 +- llvm/test/MC/ELF/ARM/bss-non-zero-value.s | 2 +- llvm/test/MC/ELF/common-error3.s | 4 +-- .../MC/ELF/section-numeric-invalid-type.s | 2 +- llvm/test/MC/MachO/variable-errors.s | 2 +- llvm/test/MC/Mips/micromips64-unsupported.s | 8 ++--- llvm/test/MC/Mips/micromips64r6-unsupported.s | 2 +- llvm/test/MC/Mips/nooddspreg-cmdarg.s | 4 +-- .../test/MC/PowerPC/ppc64-localentry-error1.s | 4 +-- .../test/MC/PowerPC/ppc64-localentry-error2.s | 4 +-- llvm/test/MC/PowerPC/pr24686.s | 2 +- .../test/MC/RISCV/mattr-invalid-combination.s | 2 +- llvm/test/MC/WebAssembly/blockaddress.ll | 2 +- .../data-symbol-in-text-section.ll | 2 +- .../bundle-group-too-large-error.s | 4 +-- .../bundle-lock-option-error.s | 2 +- .../bundle-subtarget-change-error.s | 4 +-- .../lock-without-bundle-mode-error.s | 2 +- .../switch-section-locked-error.s | 2 +- .../unlock-without-lock-error.s | 2 +- llvm/test/MC/X86/check-end-of-data-region.s | 2 +- llvm/test/MC/X86/encoder-fail.s | 2 +- llvm/test/MC/X86/invalid-sleb.s | 2 +- llvm/test/MC/X86/reloc-bss.s | 2 +- llvm/test/MachineVerifier/live-ins-01.mir | 2 +- llvm/test/MachineVerifier/live-ins-02.mir | 2 +- llvm/test/MachineVerifier/live-ins-03.mir | 2 +- llvm/test/MachineVerifier/test_copy.mir | 2 +- .../test_copy_mismatch_types.mir | 2 +- llvm/test/MachineVerifier/test_g_add.mir | 2 +- .../MachineVerifier/test_g_addrspacecast.mir | 2 +- llvm/test/MachineVerifier/test_g_bitcast.mir | 2 +- llvm/test/MachineVerifier/test_g_brjt.mir | 2 +- .../MachineVerifier/test_g_build_vector.mir | 2 +- .../test_g_build_vector_trunc.mir | 2 +- .../MachineVerifier/test_g_concat_vectors.mir | 2 +- llvm/test/MachineVerifier/test_g_constant.mir | 2 +- .../MachineVerifier/test_g_dyn_stackalloc.mir | 2 +- llvm/test/MachineVerifier/test_g_extract.mir | 2 +- llvm/test/MachineVerifier/test_g_fcmp.mir | 2 +- .../test/MachineVerifier/test_g_fconstant.mir | 2 +- llvm/test/MachineVerifier/test_g_icmp.mir | 2 +- llvm/test/MachineVerifier/test_g_insert.mir | 2 +- .../test/MachineVerifier/test_g_intrinsic.mir | 2 +- .../test_g_intrinsic_w_side_effects.mir | 2 +- llvm/test/MachineVerifier/test_g_inttoptr.mir | 2 +- .../MachineVerifier/test_g_jump_table.mir | 2 +- llvm/test/MachineVerifier/test_g_load.mir | 2 +- .../MachineVerifier/test_g_merge_values.mir | 2 +- llvm/test/MachineVerifier/test_g_phi.mir | 2 +- llvm/test/MachineVerifier/test_g_ptr_add.mir | 2 +- llvm/test/MachineVerifier/test_g_ptrtoint.mir | 2 +- llvm/test/MachineVerifier/test_g_select.mir | 2 +- .../MachineVerifier/test_g_sext_inreg.mir | 2 +- llvm/test/MachineVerifier/test_g_sextload.mir | 2 +- .../MachineVerifier/test_g_shuffle_vector.mir | 2 +- llvm/test/MachineVerifier/test_g_store.mir | 2 +- llvm/test/MachineVerifier/test_g_trunc.mir | 2 +- llvm/test/MachineVerifier/test_g_zextload.mir | 2 +- .../test_memccpy_intrinsics.mir | 2 +- .../test_phis_precede_nonphis.mir | 2 +- .../verifier-generic-extend-truncate.mir | 2 +- .../verifier-generic-types-1.mir | 2 +- .../verifier-generic-types-2.mir | 2 +- ...licit-virtreg-invalid-physreg-liveness.mir | 2 +- .../MachineVerifier/verifier-phi-fail0.mir | 2 +- .../verifier-pseudo-terminators.mir | 2 +- .../verify-regbankselected.mir | 2 +- llvm/test/MachineVerifier/verify-regops.mir | 2 +- llvm/test/MachineVerifier/verify-selected.mir | 2 +- llvm/test/Object/coff-invalid.test | 2 +- llvm/test/Object/elf-invalid-phdr.test | 4 +-- llvm/test/Object/invalid.test | 2 +- llvm/test/Object/wasm-invalid-file.yaml | 2 +- .../Object/wasm-string-outside-section.test | 2 +- llvm/test/Other/close-stderr.ll | 13 -------- .../test/Other/optimization-remarks-inline.ll | 2 +- llvm/test/TableGen/HwModeSelect.td | 2 +- .../BlockExtractor/invalid-block.ll | 2 +- .../BlockExtractor/invalid-function.ll | 2 +- .../Transforms/BlockExtractor/invalid-line.ll | 2 +- .../FunctionImport/not-prevailing.ll | 2 +- llvm/test/Transforms/GCOVProfiling/version.ll | 4 +-- .../InstCombine/limit-max-iterations.ll | 2 +- llvm/test/tools/llvm-lto2/X86/pipeline.ll | 4 +-- .../llvm-readobj/COFF/arm64-many-epilogs.s | 2 +- .../llvm-readobj/COFF/arm64-win-error2.s | 2 +- 326 files changed, 442 insertions(+), 459 deletions(-) delete mode 100644 llvm/test/Other/close-stderr.ll diff --git a/clang-tools-extra/test/clang-tidy/infrastructure/empty-database.cpp b/clang-tools-extra/test/clang-tidy/infrastructure/empty-database.cpp index b8707d6caaec..54fe8910a9a9 100644 --- a/clang-tools-extra/test/clang-tidy/infrastructure/empty-database.cpp +++ b/clang-tools-extra/test/clang-tidy/infrastructure/empty-database.cpp @@ -1,5 +1,5 @@ // UNSUPPORTED: system-windows -// RUN: not clang-tidy -p %S/Inputs/empty-database %s 2>&1 | FileCheck %s +// RUN: not --crash clang-tidy -p %S/Inputs/empty-database %s 2>&1 | FileCheck %s // CHECK: LLVM ERROR: Cannot chdir into ""! diff --git a/clang/unittests/libclang/CrashTests/LibclangCrashTest.cpp b/clang/unittests/libclang/CrashTests/LibclangCrashTest.cpp index 3ccdb16cce4e..26c63cfbd427 100644 --- a/clang/unittests/libclang/CrashTests/LibclangCrashTest.cpp +++ b/clang/unittests/libclang/CrashTests/LibclangCrashTest.cpp @@ -31,7 +31,7 @@ TEST_F(LibclangParseTest, UninstallAbortingLLVMFatalErrorHandler) { std::string Main = "main.h"; WriteFile(Main, "#pragma clang __debug llvm_fatal_error"); - EXPECT_EXIT(clang_parseTranslationUnit( - Index, Main.c_str(), nullptr, 0, nullptr, 0, TUFlags), - ::testing::ExitedWithCode(1), "ERROR"); + EXPECT_DEATH(clang_parseTranslationUnit(Index, Main.c_str(), nullptr, 0, + nullptr, 0, TUFlags), + "ERROR"); } diff --git a/lld/test/ELF/lto/ltopasses-custom.ll b/lld/test/ELF/lto/ltopasses-custom.ll index f0322f8e4175..fd73f14d6571 100644 --- a/lld/test/ELF/lto/ltopasses-custom.ll +++ b/lld/test/ELF/lto/ltopasses-custom.ll @@ -24,13 +24,13 @@ define void @barrier() { ; ATOMIC-NEXT: ret void ; Check that invalid passes are rejected gracefully. -; RUN: not ld.lld -m elf_x86_64 %t.o -o %t2.so \ +; RUN: not --crash ld.lld -m elf_x86_64 %t.o -o %t2.so \ ; RUN: --lto-newpm-passes=iamnotapass -shared 2>&1 | \ ; RUN: FileCheck %s --check-prefix=INVALID ; INVALID: unable to parse pass pipeline description 'iamnotapass': unknown pass name 'iamnotapass' ; Check that invalid AA pipelines are rejected gracefully. -; RUN: not ld.lld -m elf_x86_64 %t.o -o %t2.so \ +; RUN: not --crash ld.lld -m elf_x86_64 %t.o -o %t2.so \ ; RUN: --lto-newpm-passes=globaldce --lto-aa-pipeline=patatino \ ; RUN: -shared 2>&1 | \ ; RUN: FileCheck %s --check-prefix=INVALIDAA diff --git a/llvm/docs/ProgrammersManual.rst b/llvm/docs/ProgrammersManual.rst index 98002f687a57..8f8fec611c48 100644 --- a/llvm/docs/ProgrammersManual.rst +++ b/llvm/docs/ProgrammersManual.rst @@ -453,8 +453,8 @@ recovery. LLVM, there are places where this hasn't been practical to apply. In situations where you absolutely must emit a non-programmatic error and the ``Error`` model isn't workable you can call ``report_fatal_error``, - which will call installed error handlers, print a message, and exit the - program. + which will call installed error handlers, print a message, and abort the + program. The use of `report_fatal_error` in this case is discouraged. Recoverable errors are modeled using LLVM's ``Error`` scheme. This scheme represents errors using function return values, similar to classic C integer diff --git a/llvm/include/llvm/Support/ErrorHandling.h b/llvm/include/llvm/Support/ErrorHandling.h index f75c2984a9ff..7678d8d6ba91 100644 --- a/llvm/include/llvm/Support/ErrorHandling.h +++ b/llvm/include/llvm/Support/ErrorHandling.h @@ -66,7 +66,7 @@ class StringRef; /// /// If no error handler is installed the default is to print the message to /// standard error, followed by a newline. -/// After the error handler is called this function will call exit(1), it +/// After the error handler is called this function will call abort(), it /// does not return. LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag = true); diff --git a/llvm/lib/Support/ErrorHandling.cpp b/llvm/lib/Support/ErrorHandling.cpp index a9463024c420..f70a6921a41a 100644 --- a/llvm/lib/Support/ErrorHandling.cpp +++ b/llvm/lib/Support/ErrorHandling.cpp @@ -123,7 +123,7 @@ void llvm::report_fatal_error(const Twine &Reason, bool GenCrashDiag) { // files registered with RemoveFileOnSignal. sys::RunInterruptHandlers(); - sys::Process::Exit(1); + abort(); } void llvm::install_bad_alloc_error_handler(fatal_error_handler_t handler, diff --git a/llvm/test/Assembler/datalayout-invalid-function-ptr-alignment.ll b/llvm/test/Assembler/datalayout-invalid-function-ptr-alignment.ll index 21cd6a6dc782..4203c5546c20 100644 --- a/llvm/test/Assembler/datalayout-invalid-function-ptr-alignment.ll +++ b/llvm/test/Assembler/datalayout-invalid-function-ptr-alignment.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2 diff --git a/llvm/test/Assembler/datalayout-invalid-stack-natural-alignment.ll b/llvm/test/Assembler/datalayout-invalid-stack-natural-alignment.ll index c8d7ba62ab80..8fc18d86b1fa 100644 --- a/llvm/test/Assembler/datalayout-invalid-stack-natural-alignment.ll +++ b/llvm/test/Assembler/datalayout-invalid-stack-natural-alignment.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2 diff --git a/llvm/test/Assembler/getInt.ll b/llvm/test/Assembler/getInt.ll index 8e2537ae6cf1..02f312b1bc6c 100644 --- a/llvm/test/Assembler/getInt.ll +++ b/llvm/test/Assembler/getInt.ll @@ -1,3 +1,3 @@ -; RUN: not opt < %s 2>&1 | grep 'not a number, or does not fit in an unsigned int' +; RUN: not --crash opt < %s 2>&1 | grep 'not a number, or does not fit in an unsigned int' target datalayout = "p:4294967296:64:64" diff --git a/llvm/test/Assembler/invalid-datalayout-alloca-addrspace.ll b/llvm/test/Assembler/invalid-datalayout-alloca-addrspace.ll index f0407da73e4f..16670259ccf4 100644 --- a/llvm/test/Assembler/invalid-datalayout-alloca-addrspace.ll +++ b/llvm/test/Assembler/invalid-datalayout-alloca-addrspace.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "A16777216" ; CHECK: Invalid address space, must be a 24-bit integer diff --git a/llvm/test/Assembler/invalid-datalayout-program-addrspace.ll b/llvm/test/Assembler/invalid-datalayout-program-addrspace.ll index e636b75dee4d..fe0ab5c6087b 100644 --- a/llvm/test/Assembler/invalid-datalayout-program-addrspace.ll +++ b/llvm/test/Assembler/invalid-datalayout-program-addrspace.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s ; CHECK: Invalid address space, must be a 24-bit integer target datalayout = "P16777216" diff --git a/llvm/test/Assembler/invalid-datalayout1.ll b/llvm/test/Assembler/invalid-datalayout1.ll index d1befdcdf294..5cf088b785b5 100644 --- a/llvm/test/Assembler/invalid-datalayout1.ll +++ b/llvm/test/Assembler/invalid-datalayout1.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "^" ; CHECK: Unknown specifier in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout10.ll b/llvm/test/Assembler/invalid-datalayout10.ll index 9f19688f852b..80e5d4026d9b 100644 --- a/llvm/test/Assembler/invalid-datalayout10.ll +++ b/llvm/test/Assembler/invalid-datalayout10.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "m" ; CHECK: Expected mangling specifier in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout11.ll b/llvm/test/Assembler/invalid-datalayout11.ll index f8fed8ff9ff3..0fa99c5f7c29 100644 --- a/llvm/test/Assembler/invalid-datalayout11.ll +++ b/llvm/test/Assembler/invalid-datalayout11.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "m." ; CHECK: Unexpected trailing characters after mangling specifier in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout12.ll b/llvm/test/Assembler/invalid-datalayout12.ll index d79c196baab1..9a7535f7b6ca 100644 --- a/llvm/test/Assembler/invalid-datalayout12.ll +++ b/llvm/test/Assembler/invalid-datalayout12.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "f" ; CHECK: Missing alignment specification in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout13.ll b/llvm/test/Assembler/invalid-datalayout13.ll index 5ac719dbb7a9..26dbf44f1928 100644 --- a/llvm/test/Assembler/invalid-datalayout13.ll +++ b/llvm/test/Assembler/invalid-datalayout13.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = ":32" ; CHECK: Expected token before separator in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout14.ll b/llvm/test/Assembler/invalid-datalayout14.ll index 84634b52a146..3ca2da41743d 100644 --- a/llvm/test/Assembler/invalid-datalayout14.ll +++ b/llvm/test/Assembler/invalid-datalayout14.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i64:64:16" ; CHECK: Preferred alignment cannot be less than the ABI alignment diff --git a/llvm/test/Assembler/invalid-datalayout15.ll b/llvm/test/Assembler/invalid-datalayout15.ll index ea240b73fd25..8fdfcbf1ee83 100644 --- a/llvm/test/Assembler/invalid-datalayout15.ll +++ b/llvm/test/Assembler/invalid-datalayout15.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i64:16:16777216" ; CHECK: Invalid preferred alignment, must be a 16bit integer diff --git a/llvm/test/Assembler/invalid-datalayout16.ll b/llvm/test/Assembler/invalid-datalayout16.ll index 0dd1abb629b6..23f3e17e6d15 100644 --- a/llvm/test/Assembler/invalid-datalayout16.ll +++ b/llvm/test/Assembler/invalid-datalayout16.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i64:16777216:16777216" ; CHECK: Invalid ABI alignment, must be a 16bit integer diff --git a/llvm/test/Assembler/invalid-datalayout17.ll b/llvm/test/Assembler/invalid-datalayout17.ll index 519f5c10ab3c..75c9b005c30d 100644 --- a/llvm/test/Assembler/invalid-datalayout17.ll +++ b/llvm/test/Assembler/invalid-datalayout17.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i16777216:16:16" ; CHECK: Invalid bit width, must be a 24bit integer diff --git a/llvm/test/Assembler/invalid-datalayout18.ll b/llvm/test/Assembler/invalid-datalayout18.ll index b9956f98c9c6..dc6e722445f4 100644 --- a/llvm/test/Assembler/invalid-datalayout18.ll +++ b/llvm/test/Assembler/invalid-datalayout18.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:32:32:16" ; CHECK: Preferred alignment cannot be less than the ABI alignment diff --git a/llvm/test/Assembler/invalid-datalayout19.ll b/llvm/test/Assembler/invalid-datalayout19.ll index fc0fc4685209..dc3fa2bde1b0 100644 --- a/llvm/test/Assembler/invalid-datalayout19.ll +++ b/llvm/test/Assembler/invalid-datalayout19.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:0:32:32" diff --git a/llvm/test/Assembler/invalid-datalayout2.ll b/llvm/test/Assembler/invalid-datalayout2.ll index a435612bf854..1f7db4e605af 100644 --- a/llvm/test/Assembler/invalid-datalayout2.ll +++ b/llvm/test/Assembler/invalid-datalayout2.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "m:v" ; CHECK: Unknown mangling in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout20.ll b/llvm/test/Assembler/invalid-datalayout20.ll index a9ac1d7fe098..811488e945c8 100644 --- a/llvm/test/Assembler/invalid-datalayout20.ll +++ b/llvm/test/Assembler/invalid-datalayout20.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:64:24:64" diff --git a/llvm/test/Assembler/invalid-datalayout21.ll b/llvm/test/Assembler/invalid-datalayout21.ll index a39d1d7a14a8..0db99d254b13 100644 --- a/llvm/test/Assembler/invalid-datalayout21.ll +++ b/llvm/test/Assembler/invalid-datalayout21.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:64:64:24" diff --git a/llvm/test/Assembler/invalid-datalayout22.ll b/llvm/test/Assembler/invalid-datalayout22.ll index 14e4c2822ce4..3db71d7d1b2d 100644 --- a/llvm/test/Assembler/invalid-datalayout22.ll +++ b/llvm/test/Assembler/invalid-datalayout22.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "v128:0:128" diff --git a/llvm/test/Assembler/invalid-datalayout23.ll b/llvm/test/Assembler/invalid-datalayout23.ll index 430326327bc1..308b0140cd98 100644 --- a/llvm/test/Assembler/invalid-datalayout23.ll +++ b/llvm/test/Assembler/invalid-datalayout23.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i32:24:32" diff --git a/llvm/test/Assembler/invalid-datalayout24.ll b/llvm/test/Assembler/invalid-datalayout24.ll index 616ec64518a5..0c38103c9057 100644 --- a/llvm/test/Assembler/invalid-datalayout24.ll +++ b/llvm/test/Assembler/invalid-datalayout24.ll @@ -1,4 +1,4 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i32:32:24" diff --git a/llvm/test/Assembler/invalid-datalayout3.ll b/llvm/test/Assembler/invalid-datalayout3.ll index 44535fd055b5..613d619c5a05 100644 --- a/llvm/test/Assembler/invalid-datalayout3.ll +++ b/llvm/test/Assembler/invalid-datalayout3.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "n0" ; CHECK: Zero width native integer type in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout4.ll b/llvm/test/Assembler/invalid-datalayout4.ll index 2d946d32609d..5b174ff06184 100644 --- a/llvm/test/Assembler/invalid-datalayout4.ll +++ b/llvm/test/Assembler/invalid-datalayout4.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p16777216:64:64:64" ; CHECK: Invalid address space, must be a 24bit integer diff --git a/llvm/test/Assembler/invalid-datalayout5.ll b/llvm/test/Assembler/invalid-datalayout5.ll index 3ce8791c0870..6ca188a4fd57 100644 --- a/llvm/test/Assembler/invalid-datalayout5.ll +++ b/llvm/test/Assembler/invalid-datalayout5.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "a1:64" ; CHECK: Sized aggregate specification in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout6.ll b/llvm/test/Assembler/invalid-datalayout6.ll index 425099f7cad8..f8ea6392a359 100644 --- a/llvm/test/Assembler/invalid-datalayout6.ll +++ b/llvm/test/Assembler/invalid-datalayout6.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "a:" ; CHECK: Trailing separator in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout7.ll b/llvm/test/Assembler/invalid-datalayout7.ll index 097227ae6ae8..66eb7643d114 100644 --- a/llvm/test/Assembler/invalid-datalayout7.ll +++ b/llvm/test/Assembler/invalid-datalayout7.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:52" ; CHECK: number of bits must be a byte width multiple diff --git a/llvm/test/Assembler/invalid-datalayout8.ll b/llvm/test/Assembler/invalid-datalayout8.ll index 28832ffb17dd..2f7f18c7af5b 100644 --- a/llvm/test/Assembler/invalid-datalayout8.ll +++ b/llvm/test/Assembler/invalid-datalayout8.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "e-p" ; CHECK: Missing size specification for pointer in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout9.ll b/llvm/test/Assembler/invalid-datalayout9.ll index dfeac65cf604..74b9dbacbf06 100644 --- a/llvm/test/Assembler/invalid-datalayout9.ll +++ b/llvm/test/Assembler/invalid-datalayout9.ll @@ -1,3 +1,3 @@ -; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s target datalayout = "e-p:64" ; CHECK: Missing alignment specification for pointer in datalayout string diff --git a/llvm/test/Bitcode/function-default-address-spaces.ll b/llvm/test/Bitcode/function-default-address-spaces.ll index e008f43501a0..72b727924b42 100644 --- a/llvm/test/Bitcode/function-default-address-spaces.ll +++ b/llvm/test/Bitcode/function-default-address-spaces.ll @@ -1,6 +1,6 @@ ; RUN: llvm-as %s -o - | llvm-dis - | FileCheck %s -check-prefixes CHECK,PROG-AS0 ; RUN: llvm-as -data-layout "P200" %s -o - | llvm-dis | FileCheck %s -check-prefixes CHECK,PROG-AS200 -; RUN: not llvm-as -data-layout "P123456789" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix BAD-DATALAYOUT +; RUN: not --crash llvm-as -data-layout "P123456789" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix BAD-DATALAYOUT ; BAD-DATALAYOUT: LLVM ERROR: Invalid address space, must be a 24-bit integer ; PROG-AS0-NOT: target datalayout diff --git a/llvm/test/Bitcode/invalid-functionptr-align.ll b/llvm/test/Bitcode/invalid-functionptr-align.ll index 4ff797a4b014..be7ce49e4d53 100644 --- a/llvm/test/Bitcode/invalid-functionptr-align.ll +++ b/llvm/test/Bitcode/invalid-functionptr-align.ll @@ -1,5 +1,5 @@ ; Bitcode with invalid function pointer alignment. -; RUN: not llvm-dis %s.bc -o - 2>&1 | FileCheck %s +; RUN: not --crash llvm-dis %s.bc -o - 2>&1 | FileCheck %s CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2 diff --git a/llvm/test/Bitcode/invalid.test b/llvm/test/Bitcode/invalid.test index 8260ac862576..90303586ec3b 100644 --- a/llvm/test/Bitcode/invalid.test +++ b/llvm/test/Bitcode/invalid.test @@ -1,6 +1,6 @@ RUN: not llvm-dis -disable-output %p/Inputs/invalid-empty.bc 2>&1 | \ RUN: FileCheck --check-prefix=INVALID-EMPTY %s -RUN: not llvm-dis -disable-output %p/Inputs/invalid-pr20485.bc 2>&1 | \ +RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-pr20485.bc 2>&1 | \ RUN: FileCheck --check-prefix=INVALID-ENCODING %s RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev.bc 2>&1 | \ RUN: FileCheck --check-prefix=BAD-ABBREV %s @@ -71,14 +71,14 @@ RUN: FileCheck --check-prefix=FP-SHIFT %s FP-SHIFT: Invalid record -RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-vbr-size-too-big.bc 2>&1 | \ +RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-vbr-size-too-big.bc 2>&1 | \ RUN: FileCheck --check-prefix=HUGE-ABBREV-OP %s -RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-fixed-size-too-big.bc 2>&1 | \ +RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-fixed-size-too-big.bc 2>&1 | \ RUN: FileCheck --check-prefix=HUGE-ABBREV-OP %s HUGE-ABBREV-OP: Fixed or VBR abbrev record with size > MaxChunkData -RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-type.bc 2>&1 | \ +RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-array-type.bc 2>&1 | \ RUN: FileCheck --check-prefix=ARRAY-TYPE %s ARRAY-TYPE: Array element type can't be an Array or a Blob @@ -116,7 +116,7 @@ RUN: FileCheck --check-prefix=INVALID-CAST %s INVALID-CAST: Invalid cast -RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-op-not-2nd-to-last.bc 2>&1 | \ +RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-array-op-not-2nd-to-last.bc 2>&1 | \ RUN: FileCheck --check-prefix=ARRAY-NOT-2LAST %s ARRAY-NOT-2LAST: Array op not second to last @@ -176,7 +176,7 @@ RUN: FileCheck --check-prefix=INVALID-GVCOMDAT-ID %s INVALID-GVCOMDAT-ID: Invalid global variable comdat ID -RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-no-operands.bc 2>&1 | \ +RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-no-operands.bc 2>&1 | \ RUN: FileCheck --check-prefix=ABBREV-NO-OPS %s ABBREV-NO-OPS: Abbrev record with no operands diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index bbe8ea0da25b..661bd0d121e0 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -1,9 +1,9 @@ -; RUN: not llc -O0 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR +; RUN: not --crash llc -O0 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR ; RUN: llc -O0 -global-isel -global-isel-abort=0 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=FALLBACK ; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err ; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out ; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err -; RUN: not llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN +; RUN: not --crash llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN ; This file checks that the fallback path to selection dag works. ; The test is fragile in the sense that it must be updated to expose ; something that fails with global-isel. diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll index 72af098a8946..0894fbeb34a9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll @@ -1,4 +1,4 @@ -; RUN: not llc %s -mtriple aarch64-apple-darwin -debug-only=aarch64-call-lowering -global-isel -global-isel-abort=2 -o - 2>&1 | FileCheck %s +; RUN: not --crash llc %s -mtriple aarch64-apple-darwin -debug-only=aarch64-call-lowering -global-isel -global-isel-abort=2 -o - 2>&1 | FileCheck %s ; REQUIRES: asserts ; Verify that we fall back to SelectionDAG, and error out when we can't tail call musttail functions diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir index 7661626f6c1c..9c318b7574b8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir @@ -1,5 +1,4 @@ -# RUN: not llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s -# REQUIRES: asserts +# RUN: not --crash llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s # This is to demonstrate what kind of bugs we're missing w/o some kind # of validation for LegalizerInfo: G_INTTOPTR could only be legal / diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir index 0b5b7b440f29..bbdc54a51219 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir @@ -1,5 +1,4 @@ -# RUN: not llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s -# REQUIRES: asserts +# RUN: not --crash llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s # This is to demonstrate what kind of bugs we're missing w/o some kind # of validation for LegalizerInfo: G_INTTOPTR could only be legal / diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll index f2e6fbce0d7a..6408f2e0b0d5 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll @@ -1,4 +1,4 @@ -; RUN: not llc -o - -verify-machineinstrs -global-isel -global-isel-abort=1 -stop-after=legalizer %s 2>&1 | FileCheck %s +; RUN: not --crash llc -o - -verify-machineinstrs -global-isel -global-isel-abort=1 -stop-after=legalizer %s 2>&1 | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-unknown" diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll index 5d48c17e1286..bd14ec61b55c 100644 --- a/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll +++ b/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll index 8a5fd6f1ac8b..fe5f000a393e 100644 --- a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll +++ b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll b/llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll index 7ef51d7d4c01..9a24d6acfa11 100644 --- a/llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll +++ b/llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll @@ -9,7 +9,7 @@ ; FIXME: We currently produce "small" code for the tiny model ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=tiny -verify-machineinstrs < %s | FileCheck %s ; FIXME: We currently error for the large code model -; RUN: not llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=large -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE +; RUN: not --crash llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=large -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE ; CHECK-LARGE: ELF TLS only supported in small memory model diff --git a/llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll b/llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll index 4f169678974f..d6df1a3907bc 100644 --- a/llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll +++ b/llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll @@ -3,7 +3,7 @@ ; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=tiny < %s | FileCheck %s --check-prefix=CHECK-TINY ; RUN: llc -mtriple=arm64-none-linux-gnu -filetype=obj < %s -code-model=tiny | llvm-objdump -r - | FileCheck --check-prefix=CHECK-TINY-RELOC %s ; FIXME: We currently error for the large code model -; RUN: not llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=large < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE +; RUN: not --crash llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=large < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE ; CHECK-LARGE: ELF TLS only supported in small memory model diff --git a/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll b/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll index 62815daa6c51..8d62fb355666 100644 --- a/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll +++ b/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll @@ -1,5 +1,5 @@ ; RUN: llc -O0 -fast-isel -mtriple=aarch64-apple-ios -o - %s | FileCheck %s -; RUN: not llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t +; RUN: not --crash llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t ; RUN: FileCheck %s --check-prefix=CHECK-ERRORS < %t ; The issue here is that FastISel cannot emit an ADDrr where one of the inputs diff --git a/llvm/test/CodeGen/AArch64/tiny_supported.ll b/llvm/test/CodeGen/AArch64/tiny_supported.ll index 50f4a9c344a7..400fde0aa0a9 100644 --- a/llvm/test/CodeGen/AArch64/tiny_supported.ll +++ b/llvm/test/CodeGen/AArch64/tiny_supported.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s ; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s -; RUN: not llc -verify-machineinstrs -o - -mtriple=arm64-apple-darwin -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY -; RUN: not llc -verify-machineinstrs -o - -mtriple=arm64-apple-ios -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY -; RUN: not llc -verify-machineinstrs -o - -mtriple=aarch64-unknown-windows-msvc -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm64-apple-darwin -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm64-apple-ios -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=aarch64-unknown-windows-msvc -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY ; CHECK-NOT: tiny code model is only supported on ELF ; CHECK-LABEL: foo diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll index 8eee33af24ad..5243076ea8b0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GPRIDX %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=MOVREL %s -; RUN: not llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s +; RUN: not --crash llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s ; FIXME: Need constant bus fixup pre-gfx10 for movrel ; ERR: Bad machine code: VOP* instruction violates constant bus restriction diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir index 2c7a03c0064c..8ea1d4b659ad 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s +# RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s # ERR: *** Bad machine code: VOP* instruction violates constant bus restriction *** diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll index 02f77141b411..8c84c1c5e306 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll @@ -1,3 +1,3 @@ -; RUN: not llc -global-isel -march=amdgcn -mcpu=tonga < %S/../lds-zero-initializer.ll 2>&1 | FileCheck %s +; RUN: not --crash llc -global-isel -march=amdgcn -mcpu=tonga < %S/../lds-zero-initializer.ll 2>&1 | FileCheck %s ; CHECK: error: :0:0: in function load_zeroinit_lds_global void (i32 addrspace(1)*, i1): unsupported initializer for address space diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir index ccce93db415f..845bffd1d9f3 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s 2>&1| FileCheck -check-prefix=ERROR %s +# RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s 2>&1| FileCheck -check-prefix=ERROR %s # This needs to be expanded into a cmpxchg loop. # TODO: Will AtomicExpand still do this? diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir index 96b33c1b768a..9f2be730569c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer -o - %s | FileCheck %s -# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +# RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s # ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_XCHG %0:_(p0), %1:_ :: (load store seq_cst 4) (in function: atomicrmw_xchg_flat_i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir index 40e5ccd2c1ea..7a880f86c089 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=amdgcn -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: unable to legalize instruction: %3:_(p0) = G_JUMP_TABLE %jump-table.0 (in function: jt_test) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir index 5ffbeab9872d..6f7ef466394c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -o - %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -o - %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: unable to legalize instruction: %1:_(s1), %2:_(s1) = G_UNMERGE_VALUES %0:_(<2 x s1>) (in function: test_unmerge_v2s1) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll index 550a7312cbe1..806a16eb7640 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll @@ -1,4 +1,4 @@ -; RUN: not llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-GISEL %s +; RUN: not --crash llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-GISEL %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.sema.release.all.ll ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %S/../llvm.amdgcn.ds.gws.sema.release.all.ll ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %S/../llvm.amdgcn.ds.gws.sema.release.all.ll diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir index 32968c0250b4..7e1d3871616a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir @@ -1,5 +1,5 @@ -# RUN: not llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast %s -o /dev/null 2>&1 | FileCheck %s -# RUN: not llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy %s -o /dev/null 2>&1 | FileCheck %s +# RUN: not --crash llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast %s -o /dev/null 2>&1 | FileCheck %s +# RUN: not --crash llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy %s -o /dev/null 2>&1 | FileCheck %s # Check behavior for illegal copies. diff --git a/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir b/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir index 95e0ada80040..eb244190e562 100644 --- a/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir +++ b/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s # CHECK: *** Bad machine code: No live subrange at use *** # CHECK-NEXT: - function: at_least_one_value_should_be_defined_by_this_mask diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll index e4d3df91d59d..6ea73ed8c7a9 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s +; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s ; FIXME: This should be able to compile, but requires inserting an ; extra block to restore the scavenged register. diff --git a/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll b/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll index 2d9183e6a99e..1c5da794a5f3 100644 --- a/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll +++ b/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s ; FIXME: It should be invalid IR to have a call to a kernel, but this ; is currently relied on, but should be eliminated before codegen. diff --git a/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll b/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll index 6b457cfd4bf2..24b019ccefe3 100644 --- a/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll +++ b/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s ; FIXME: It should be invalid IR to have a call to a kernel, but this ; is currently relied on, but should be eliminated before codegen. diff --git a/llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll b/llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll index 72c6cfee28df..a37db5a27240 100644 --- a/llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll +++ b/llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll @@ -1,6 +1,6 @@ -; RUN: not llc -march=amdgcn -mcpu=verde -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -; RUN: not llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=verde -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s ;CHECK: LLVM ERROR: unable to allocate function argument define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } @_amdgpu_gs_sgpr_i32 (i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg) { diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll index 80acf6804ccc..68fe7ec62342 100644 --- a/llvm/test/CodeGen/AMDGPU/div_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: unsupported libcall legalization define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { diff --git a/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll b/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll index 25b21326d570..8881d9e7088c 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll @@ -1,8 +1,8 @@ -; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s -; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -o - %s | FileCheck -check-prefix=HSA-DEFAULT %s -; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s ; Flat instructions should not select if the target device doesn't ; support them. The default device should be able to select for HSA. diff --git a/llvm/test/CodeGen/AMDGPU/lds-initializer.ll b/llvm/test/CodeGen/AMDGPU/lds-initializer.ll index 7cfe013b8453..42a9782ad0b7 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-initializer.ll @@ -1,5 +1,5 @@ -; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s -; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s ; CHECK: lds: unsupported initializer for address space diff --git a/llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll b/llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll index 367dd173f781..70bf4e951b99 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll @@ -1,5 +1,5 @@ -; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s -; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s ; CHECK: lds: unsupported initializer for address space diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll index 2d690ec76233..8ba2b0e53698 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR %s +; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll index 34cbe3963361..6b169e0f18f6 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s ; CHECK: invalid register "flat_scratch_lo" for subtarget. diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll index 6417d28e7aad..178b22f329b1 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s ; CHECK: invalid type for register "exec". diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll index 8e248fdfea4c..f05d900b39d6 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s ; CHECK: invalid type for register "m0". diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll b/llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll index e7346c4c1d4c..c028adf5d938 100644 --- a/llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll +++ b/llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s +; RUN: not --crash llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s ; Make sure this doesn't assert on targets without the r128-16 ; feature, and instead generates a slection error. diff --git a/llvm/test/CodeGen/AMDGPU/verify-sop.mir b/llvm/test/CodeGen/AMDGPU/verify-sop.mir index 53d749f71196..040cd58f28c9 100644 --- a/llvm/test/CodeGen/AMDGPU/verify-sop.mir +++ b/llvm/test/CodeGen/AMDGPU/verify-sop.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants # CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32 diff --git a/llvm/test/CodeGen/ARM/codemodel.ll b/llvm/test/CodeGen/ARM/codemodel.ll index ec9982faba12..ee435986c611 100644 --- a/llvm/test/CodeGen/ARM/codemodel.ll +++ b/llvm/test/CodeGen/ARM/codemodel.ll @@ -1,5 +1,5 @@ -; RUN: not llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY -; RUN: not llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL ; TINY: Target does not support the tiny CodeModel ; KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/ARM/ldc2l.ll b/llvm/test/CodeGen/ARM/ldc2l.ll index 58d9509b1672..bdfcbbf7df25 100644 --- a/llvm/test/CodeGen/ARM/ldc2l.ll +++ b/llvm/test/CodeGen/ARM/ldc2l.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ldc2l define void @ldc2l(i8* %i) nounwind { diff --git a/llvm/test/CodeGen/ARM/machine-verifier.mir b/llvm/test/CodeGen/ARM/machine-verifier.mir index c5d678c38cfa..eab4d45e5ab0 100644 --- a/llvm/test/CodeGen/ARM/machine-verifier.mir +++ b/llvm/test/CodeGen/ARM/machine-verifier.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser runs the machine verifier after parsing. --- | diff --git a/llvm/test/CodeGen/ARM/named-reg-alloc.ll b/llvm/test/CodeGen/ARM/named-reg-alloc.ll index d41fa64882c8..535149a67455 100644 --- a/llvm/test/CodeGen/ARM/named-reg-alloc.ll +++ b/llvm/test/CodeGen/ARM/named-reg-alloc.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/named-reg-notareg.ll b/llvm/test/CodeGen/ARM/named-reg-notareg.ll index 45cb38f30f35..0af948250050 100644 --- a/llvm/test/CodeGen/ARM/named-reg-notareg.ll +++ b/llvm/test/CodeGen/ARM/named-reg-notareg.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/special-reg-acore.ll b/llvm/test/CodeGen/ARM/special-reg-acore.ll index 3d65ff44bfb0..30e59b14685f 100644 --- a/llvm/test/CodeGen/ARM/special-reg-acore.ll +++ b/llvm/test/CodeGen/ARM/special-reg-acore.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE -; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE +; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE ; MCORE: LLVM ERROR: Invalid register name "cpsr". diff --git a/llvm/test/CodeGen/ARM/special-reg-mcore.ll b/llvm/test/CodeGen/ARM/special-reg-mcore.ll index 1ecf8dc77a70..dff02ce2ea44 100644 --- a/llvm/test/CodeGen/ARM/special-reg-mcore.ll +++ b/llvm/test/CodeGen/ARM/special-reg-mcore.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 --show-mc-encoding 2>&1 | FileCheck %s --check-prefix=MCORE -; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE -; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE +; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE +; RUN: not --crash llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE ; ACORE: LLVM ERROR: Invalid register name "control". ; M3CORE: LLVM ERROR: Invalid register name "xpsr_nzcvqg". diff --git a/llvm/test/CodeGen/ARM/special-reg-v8m-base.ll b/llvm/test/CodeGen/ARM/special-reg-v8m-base.ll index 20284daa0463..5b74a55fe8c8 100644 --- a/llvm/test/CodeGen/ARM/special-reg-v8m-base.ll +++ b/llvm/test/CodeGen/ARM/special-reg-v8m-base.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M +; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M ; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s ; V7M: LLVM ERROR: Invalid register name "sp_ns". diff --git a/llvm/test/CodeGen/ARM/special-reg-v8m-main.ll b/llvm/test/CodeGen/ARM/special-reg-v8m-main.ll index 88f238cb83a0..9a314fa4c771 100644 --- a/llvm/test/CodeGen/ARM/special-reg-v8m-main.ll +++ b/llvm/test/CodeGen/ARM/special-reg-v8m-main.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE +; RUN: not --crash llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE ; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE ; BASELINE: LLVM ERROR: Invalid register name "faultmask_ns". diff --git a/llvm/test/CodeGen/ARM/ssat-lower.ll b/llvm/test/CodeGen/ARM/ssat-lower.ll index 9f0cd0364bcf..93930298fb48 100644 --- a/llvm/test/CodeGen/ARM/ssat-lower.ll +++ b/llvm/test/CodeGen/ARM/ssat-lower.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s -; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s ; immediate argument < lower-bound ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat diff --git a/llvm/test/CodeGen/ARM/ssat-upper.ll b/llvm/test/CodeGen/ARM/ssat-upper.ll index e53f82b3efa3..9fcab67b4a73 100644 --- a/llvm/test/CodeGen/ARM/ssat-upper.ll +++ b/llvm/test/CodeGen/ARM/ssat-upper.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s -; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s ; immediate argument > upper-bound ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat diff --git a/llvm/test/CodeGen/ARM/ssat-v4t.ll b/llvm/test/CodeGen/ARM/ssat-v4t.ll index 3d74c88da827..42511f92fdc5 100644 --- a/llvm/test/CodeGen/ARM/ssat-v4t.ll +++ b/llvm/test/CodeGen/ARM/ssat-v4t.ll @@ -1,4 +1,4 @@ -; RUN: not llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s +; RUN: not --crash llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s ; CHECK: Cannot select: intrinsic %llvm.arm.ssat define i32 @ssat() nounwind { diff --git a/llvm/test/CodeGen/ARM/stc2.ll b/llvm/test/CodeGen/ARM/stc2.ll index 1127796387bb..c4d7ff007f51 100644 --- a/llvm/test/CodeGen/ARM/stc2.ll +++ b/llvm/test/CodeGen/ARM/stc2.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.stc2 define void @stc2(i8* %i) nounwind { diff --git a/llvm/test/CodeGen/ARM/usat-lower.ll b/llvm/test/CodeGen/ARM/usat-lower.ll index 58d3bba5a1f8..3d7b24d9373e 100644 --- a/llvm/test/CodeGen/ARM/usat-lower.ll +++ b/llvm/test/CodeGen/ARM/usat-lower.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s -; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s ; immediate argument < lower-bound ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat diff --git a/llvm/test/CodeGen/ARM/usat-upper.ll b/llvm/test/CodeGen/ARM/usat-upper.ll index 84ad694725b4..4f186a013cd8 100644 --- a/llvm/test/CodeGen/ARM/usat-upper.ll +++ b/llvm/test/CodeGen/ARM/usat-upper.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s -; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s ; immediate argument > upper-bound ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat diff --git a/llvm/test/CodeGen/ARM/usat-v4t.ll b/llvm/test/CodeGen/ARM/usat-v4t.ll index 572c760e3ae6..9cc75846ca36 100644 --- a/llvm/test/CodeGen/ARM/usat-v4t.ll +++ b/llvm/test/CodeGen/ARM/usat-v4t.ll @@ -1,4 +1,4 @@ -; RUN: not llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s +; RUN: not --crash llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat define i32 @usat1() nounwind { diff --git a/llvm/test/CodeGen/BPF/sdiv_error.ll b/llvm/test/CodeGen/BPF/sdiv_error.ll index 053b82dd98fa..fc79a1d44c16 100644 --- a/llvm/test/CodeGen/BPF/sdiv_error.ll +++ b/llvm/test/CodeGen/BPF/sdiv_error.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=bpf < %s 2> %t1 +; RUN: not --crash llc -march=bpf < %s 2> %t1 ; RUN: FileCheck %s < %t1 ; CHECK: Unsupport signed division diff --git a/llvm/test/CodeGen/BPF/xadd.ll b/llvm/test/CodeGen/BPF/xadd.ll index 0bf8576df1c7..6fd0a1f644bb 100644 --- a/llvm/test/CodeGen/BPF/xadd.ll +++ b/llvm/test/CodeGen/BPF/xadd.ll @@ -1,7 +1,7 @@ -; RUN: not llc -march=bpfel < %s 2>&1 | FileCheck %s -; RUN: not llc -march=bpfeb < %s 2>&1 | FileCheck %s -; RUN: not llc -march=bpfel -mattr=+alu32 < %s 2>&1 | FileCheck %s -; RUN: not llc -march=bpfeb -mattr=+alu32 < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=bpfel < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=bpfeb < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=bpfel -mattr=+alu32 < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=bpfeb -mattr=+alu32 < %s 2>&1 | FileCheck %s ; This file is generated with the source command and source ; $ clang -target bpf -O2 -g -S -emit-llvm t.c diff --git a/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll b/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll index cb1b30f3a819..76cc8b681b6a 100644 --- a/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll +++ b/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll @@ -1,4 +1,4 @@ -; RUN: not llc -debug-pass=Structure -stop-after=dead-mi-elimination,arst %s -o /dev/null 2>&1 \ +; RUN: not --crash llc -debug-pass=Structure -stop-after=dead-mi-elimination,arst %s -o /dev/null 2>&1 \ ; RUN: | FileCheck -check-prefix=NOT-NUM %s ; NOT-NUM: LLVM ERROR: invalid pass instance specifier dead-mi-elimination,arst diff --git a/llvm/test/CodeGen/Generic/llc-start-stop.ll b/llvm/test/CodeGen/Generic/llc-start-stop.ll index fa34838a411f..4f2e708c4f2e 100644 --- a/llvm/test/CodeGen/Generic/llc-start-stop.ll +++ b/llvm/test/CodeGen/Generic/llc-start-stop.ll @@ -23,16 +23,16 @@ ; START-BEFORE: Loop Strength Reduction ; START-BEFORE-NEXT: Basic Alias Analysis (stateless AA impl) -; RUN: not llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE -; RUN: not llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE -; RUN: not llc < %s -start-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-AFTER -; RUN: not llc < %s -stop-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-AFTER +; RUN: not --crash llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE +; RUN: not --crash llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE +; RUN: not --crash llc < %s -start-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-AFTER +; RUN: not --crash llc < %s -stop-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-AFTER ; NONEXISTENT-START-BEFORE: "nonexistent" pass is not registered. ; NONEXISTENT-STOP-BEFORE: "nonexistent" pass is not registered. ; NONEXISTENT-START-AFTER: "nonexistent" pass is not registered. ; NONEXISTENT-STOP-AFTER: "nonexistent" pass is not registered. -; RUN: not llc < %s -start-before=loop-reduce -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-START -; RUN: not llc < %s -stop-before=loop-reduce -stop-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-STOP +; RUN: not --crash llc < %s -start-before=loop-reduce -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-START +; RUN: not --crash llc < %s -stop-before=loop-reduce -stop-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-STOP ; DOUBLE-START: start-before and start-after specified! ; DOUBLE-STOP: stop-before and stop-after specified! diff --git a/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll b/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll index c6cb1c2b657b..413f09ba55dd 100644 --- a/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll +++ b/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll @@ -1,3 +1,3 @@ -; RUN: not opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s +; RUN: not --crash opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s ; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass without a target triple set? diff --git a/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll b/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll index 37d1155ca275..74b744305a07 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=hexagon < %s 2>&1 | FileCheck %s ; Check that the misaligned load is diagnosed. ; CHECK: LLVM ERROR: Misaligned constant address: 0x00012345 has alignment 1, but the memory access requires 4, at misaligned-const-load.c:2:10 diff --git a/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll b/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll index 311a56e13a75..0a5b1aafcc01 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -march=hexagon < %s 2>&1 | FileCheck %s ; Check that the misaligned store is diagnosed. ; CHECK: LLVM ERROR: Misaligned constant address: 0x00012345 has alignment 1, but the memory access requires 4, at misaligned-const-store.c:2:10 diff --git a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir index 149790c98638..fefe24514099 100644 --- a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir +++ b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir @@ -1,8 +1,8 @@ # Using a trick to run simple-register-coalescing twice, that way # liveintervals should be preserved while running the machine verifier. # -# RUN: not llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s -# RUN: not llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-SUB %s +# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s +# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-SUB %s --- name: test_pass diff --git a/llvm/test/CodeGen/Lanai/codemodel.ll b/llvm/test/CodeGen/Lanai/codemodel.ll index 72d1d65daf52..acfbabacf33c 100644 --- a/llvm/test/CodeGen/Lanai/codemodel.ll +++ b/llvm/test/CodeGen/Lanai/codemodel.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=lanai < %s | FileCheck %s ; RUN: llc -march=lanai < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s -; RUN: not llc -march=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s -; RUN: not llc -march=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s +; RUN: not --crash llc -march=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s +; RUN: not --crash llc -march=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s ; CHECK-TINY: Target does not support the tiny CodeModel ; CHECK-KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir index 16a55ea5fea8..17aa16b4a431 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser runs the machine verifier after parsing. --- | diff --git a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir index 8f531d96d1d9..3d842f66f0aa 100644 --- a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir +++ b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the Machine Verifier detects tied physical registers # that doesn't match. diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll index eb592189e601..84a284a5bf21 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \ +; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \ ; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s ; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll index 24161ca82382..18bc397480e3 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \ +; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \ ; RUN: -O0 -fast-isel-abort=3 -relocation-model=pic < %s ; Test that FastISel aborts instead of trying to lower arguments for soft-float. diff --git a/llvm/test/CodeGen/Mips/cpus-no-mips64.ll b/llvm/test/CodeGen/Mips/cpus-no-mips64.ll index 301f6c2152e7..63b0140a8a60 100644 --- a/llvm/test/CodeGen/Mips/cpus-no-mips64.ll +++ b/llvm/test/CodeGen/Mips/cpus-no-mips64.ll @@ -1,13 +1,13 @@ ; Check that we reject 64-bit mode on 32-bit only CPUs. -; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips1 2>&1 | FileCheck %s -; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips2 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips1 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips2 2>&1 | FileCheck %s -; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32 2>&1 | FileCheck %s -; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r2 2>&1 | FileCheck %s -; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r3 2>&1 | FileCheck %s -; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r5 2>&1 | FileCheck %s -; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r6 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r2 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r3 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r5 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r6 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it! diff --git a/llvm/test/CodeGen/Mips/cpus.ll b/llvm/test/CodeGen/Mips/cpus.ll index d9377044dca1..182d13b1c7e3 100644 --- a/llvm/test/CodeGen/Mips/cpus.ll +++ b/llvm/test/CodeGen/Mips/cpus.ll @@ -57,9 +57,9 @@ ; Check that we reject CPUs that are not implemented. -; RUN: not llc < %s -o /dev/null -mtriple=mips -mcpu=mips1 2>&1 \ +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips -mcpu=mips1 2>&1 \ ; RUN: | FileCheck %s --check-prefix=ERROR -; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \ +; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \ ; RUN: | FileCheck %s --check-prefix=ERROR ; ERROR: LLVM ERROR: Code generation for MIPS-{{.}} is not implemented diff --git a/llvm/test/CodeGen/Mips/fp64a.ll b/llvm/test/CodeGen/Mips/fp64a.ll index 317afd7003bb..2bf59052761d 100644 --- a/llvm/test/CodeGen/Mips/fp64a.ll +++ b/llvm/test/CodeGen/Mips/fp64a.ll @@ -7,16 +7,16 @@ ; We don't test MIPS32r1 since support for 64-bit coprocessors (such as a 64-bit ; FPU) on a 32-bit architecture was added in MIPS32r2. -; RUN: not llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64 +; RUN: not --crash llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A -; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A +; RUN: not --crash llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A -; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A +; RUN: not --crash llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A ; 32R1-FP64: LLVM ERROR: FPU with 64-bit registers is not available on MIPS32 pre revision 2. Use -mcpu=mips32r2 or greater. ; 64-FP64A: LLVM ERROR: -mattr=+nooddspreg requires the O32 ABI. diff --git a/llvm/test/CodeGen/Mips/fpxx.ll b/llvm/test/CodeGen/Mips/fpxx.ll index 6fdb95efe8ec..075eff1e580f 100644 --- a/llvm/test/CodeGen/Mips/fpxx.ll +++ b/llvm/test/CodeGen/Mips/fpxx.ll @@ -5,10 +5,10 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FPXX ; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,4-NOFPXX -; RUN: not llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX +; RUN: not --crash llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX ; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64-NOFPXX -; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX +; RUN: not --crash llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX ; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,4-O32-NOFPXX ; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,4-O32-FPXX diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir index b1d177a22eaa..02fef74eeefb 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ +# RUN: not --crash llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ # RUN: -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir index e13c93bec248..d313cad4d8d5 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ +# RUN: not --crash llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ # RUN: -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll index 99612525ae3c..23841d31e0b4 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=mips-unknown-linux -mcpu=mips32r2 -mattr=+micromips,+use-indirect-jump-hazard %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=mips-unknown-linux -mcpu=mips32r2 -mattr=+micromips,+use-indirect-jump-hazard %s 2>&1 | FileCheck %s ; Test that microMIPS and indirect jump with hazard barriers is not supported. diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll index 48baedf53eaa..be27eea5dacb 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=mips-unknown-linux -mcpu=mips32 -mattr=+use-indirect-jump-hazard %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=mips-unknown-linux -mcpu=mips32 -mattr=+use-indirect-jump-hazard %s 2>&1 | FileCheck %s ; Test that mips32 and indirect jump with hazard barriers is not supported. diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir index a93231b72a00..02dd9085c31e 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir index 6ba7243cdfb5..97cb085eac50 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir index fbf84819a0f6..e76af1be9493 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir index d4cf55bf6ca0..264968382447 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir index cd9fd2de915a..fc24a2756c6a 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir index 782596ec4ece..7001221bb0db 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir index 418c98f44fdf..b9e3b8c169e4 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir index 70f12dd1a91c..8407a7a836f7 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir index ec6f24aed187..d72837850cfb 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir index 13a7c6536da1..71d4242c948c 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir index 63e6f9193c9a..35848a936e5c 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir index bec2fc034316..a00d3cf715a7 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir index 90dced0435d4..0bbbdd232245 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir index 9c8c247f9ea3..c1f5f044bdee 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir index 4209a8ddf61e..9f9953a85565 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir index 7d4828d92947..12e999d5d488 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir index d4c2f56c408e..f204a3373f76 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir index b9c1d6193c90..c7b16fd50ab0 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir index 23cede00d319..ce2abeb3cdcf 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir index 8b8ae45ded40..57737ea60283 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir index 9220bbdb7472..1e48f1e8a236 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir index 3932d174be91..c72e6f5a3be3 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir index 4f5348c29515..92319bd3ff8a 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/interrupt-attr-64-error.ll b/llvm/test/CodeGen/Mips/interrupt-attr-64-error.ll index 9626bda45f51..02c0e3d5b776 100644 --- a/llvm/test/CodeGen/Mips/interrupt-attr-64-error.ll +++ b/llvm/test/CodeGen/Mips/interrupt-attr-64-error.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mcpu=mips64r6 -march=mipsel -target-abi n64 -relocation-model=static < %s 2>%t +; RUN: not --crash llc -mcpu=mips64r6 -march=mipsel -target-abi n64 -relocation-model=static < %s 2>%t ; RUN: FileCheck %s < %t ; CHECK: LLVM ERROR: "interrupt" attribute is only supported for the O32 ABI on MIPS32R2+ at the present time. diff --git a/llvm/test/CodeGen/Mips/interrupt-attr-args-error.ll b/llvm/test/CodeGen/Mips/interrupt-attr-args-error.ll index 993629bdbcd6..dd2cf443c7ce 100644 --- a/llvm/test/CodeGen/Mips/interrupt-attr-args-error.ll +++ b/llvm/test/CodeGen/Mips/interrupt-attr-args-error.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mcpu=mips32r2 -march=mipsel -relocation-model=static < %s 2> %t +; RUN: not --crash llc -mcpu=mips32r2 -march=mipsel -relocation-model=static < %s 2> %t ; RUN: FileCheck %s < %t ; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments! diff --git a/llvm/test/CodeGen/Mips/interrupt-attr-error.ll b/llvm/test/CodeGen/Mips/interrupt-attr-error.ll index f35e98ea14bf..d84e511a23f1 100644 --- a/llvm/test/CodeGen/Mips/interrupt-attr-error.ll +++ b/llvm/test/CodeGen/Mips/interrupt-attr-error.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mcpu=mips32 -march=mipsel -relocation-model=static < %s 2>%t +; RUN: not --crash llc -mcpu=mips32 -march=mipsel -relocation-model=static < %s 2>%t ; RUN: FileCheck %s < %t ; CHECK: LLVM ERROR: "interrupt" attribute is not supported on pre-MIPS32R2 or MIPS16 targets. diff --git a/llvm/test/CodeGen/Mips/micromips64-unsupported.ll b/llvm/test/CodeGen/Mips/micromips64-unsupported.ll index 713722ea1200..0f24167e3150 100644 --- a/llvm/test/CodeGen/Mips/micromips64-unsupported.ll +++ b/llvm/test/CodeGen/Mips/micromips64-unsupported.ll @@ -1,5 +1,5 @@ -; RUN: not llc -mtriple=mips64-unknown-linux -mcpu=mips64r6 -mattr=+micromips %s 2>&1 | FileCheck %s --check-prefix=MICROMIPS64R6 -; RUN: not llc -mtriple=mips64-unknown-linux -mcpu=mips64 -mattr=+micromips %s 2>&1 | FileCheck %s --check-prefix=MICROMIPS64 +; RUN: not --crash llc -mtriple=mips64-unknown-linux -mcpu=mips64r6 -mattr=+micromips %s 2>&1 | FileCheck %s --check-prefix=MICROMIPS64R6 +; RUN: not --crash llc -mtriple=mips64-unknown-linux -mcpu=mips64 -mattr=+micromips %s 2>&1 | FileCheck %s --check-prefix=MICROMIPS64 ; Test that microMIPS64(R6) is not supported. diff --git a/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll b/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll index 8eac8d4683d1..1adb1bc944e1 100644 --- a/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll +++ b/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -; RUN: not llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s +; RUN: not --crash llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s ; CHECK: foo: ; DSP: MIPS32r6 is not compatible with the DSP ASE diff --git a/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll b/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll index 174f4ce1771a..8b7607eccc75 100644 --- a/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll +++ b/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -; RUN: not llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s +; RUN: not --crash llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s ; CHECK: foo: ; DSP: MIPS64r6 is not compatible with the DSP ASE diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll index 933c4ed6946d..47d8eaa68beb 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-a.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll @@ -5,7 +5,7 @@ ; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s ; It should fail to compile without fp64. -; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ +; RUN: not --crash llc -march=mips -mattr=+msa < %s 2>&1 | \ ; RUN: FileCheck -check-prefix=FP32ERROR %s ; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). diff --git a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll index efb3dfc4be4e..cd0ef21d0022 100644 --- a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll +++ b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1 +; RUN: not --crash llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1 ; RUN: FileCheck %s < %t1 ; Test that the immediate intrinsics with out of range values trigger an error. diff --git a/llvm/test/CodeGen/NVPTX/alias.ll b/llvm/test/CodeGen/NVPTX/alias.ll index a27851927696..6dad3845b086 100644 --- a/llvm/test/CodeGen/NVPTX/alias.ll +++ b/llvm/test/CodeGen/NVPTX/alias.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that llc dies gracefully when given an alias. diff --git a/llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll b/llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll index d435c1d14fee..7294958dcd7a 100644 --- a/llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll +++ b/llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that we fail to select fcos without fast-math enabled diff --git a/llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll b/llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll index 56396b849250..083aa1da3e22 100644 --- a/llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll +++ b/llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that we fail to select fsin without fast-math enabled diff --git a/llvm/test/CodeGen/NVPTX/global-ctor.ll b/llvm/test/CodeGen/NVPTX/global-ctor.ll index 89155db08ea5..b7206dce6612 100644 --- a/llvm/test/CodeGen/NVPTX/global-ctor.ll +++ b/llvm/test/CodeGen/NVPTX/global-ctor.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that llc dies when given a nonempty global ctor. @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }] diff --git a/llvm/test/CodeGen/NVPTX/global-dtor.ll b/llvm/test/CodeGen/NVPTX/global-dtor.ll index 9d01f9bd387c..6125b65c4091 100644 --- a/llvm/test/CodeGen/NVPTX/global-dtor.ll +++ b/llvm/test/CodeGen/NVPTX/global-dtor.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that llc dies when given a nonempty global dtor. @llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }] diff --git a/llvm/test/CodeGen/NVPTX/libcall-instruction.ll b/llvm/test/CodeGen/NVPTX/libcall-instruction.ll index a40a504c94cb..33bd9a4c8e38 100644 --- a/llvm/test/CodeGen/NVPTX/libcall-instruction.ll +++ b/llvm/test/CodeGen/NVPTX/libcall-instruction.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=nvptx 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=nvptx 2>&1 | FileCheck %s ; used to panic on failed assertion and now fails with an "Undefined external symbol" ; CHECK: LLVM ERROR: Undefined external symbol "__umodti3" diff --git a/llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll b/llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll index 0b5e0224399d..4778667002c4 100644 --- a/llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll +++ b/llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=nvptx 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=nvptx 2>&1 | FileCheck %s ; used to seqfault and now fails with an "Undefined external symbol" ; CHECK: LLVM ERROR: Undefined external symbol "__powidf2" diff --git a/llvm/test/CodeGen/PowerPC/aix-byval-param.ll b/llvm/test/CodeGen/PowerPC/aix-byval-param.ll index 951475438d56..2dfdf7f8535f 100644 --- a/llvm/test/CodeGen/PowerPC/aix-byval-param.ll +++ b/llvm/test/CodeGen/PowerPC/aix-byval-param.ll @@ -1,5 +1,5 @@ -; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s -; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s %struct.S = type { i32, i32 } diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll b/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll index 59ad57e1bbaf..5be6213398da 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s ; This test expects a compiler diagnostic for an AIX limitation on Altivec ; support. When the Altivec limitation diagnostic is removed, this test diff --git a/llvm/test/CodeGen/PowerPC/aix-nest-param.ll b/llvm/test/CodeGen/PowerPC/aix-nest-param.ll index 8534c80ca643..f768eba31d58 100644 --- a/llvm/test/CodeGen/PowerPC/aix-nest-param.ll +++ b/llvm/test/CodeGen/PowerPC/aix-nest-param.ll @@ -1,5 +1,5 @@ -; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s -; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s define i8* @nest_receiver(i8* nest %arg) nounwind { ret i8* %arg diff --git a/llvm/test/CodeGen/PowerPC/aix-trampoline.ll b/llvm/test/CodeGen/PowerPC/aix-trampoline.ll index 5c45dc588969..4e5cbb6a7e6e 100644 --- a/llvm/test/CodeGen/PowerPC/aix-trampoline.ll +++ b/llvm/test/CodeGen/PowerPC/aix-trampoline.ll @@ -1,5 +1,5 @@ -; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s -; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: INIT_TRAMPOLINE operation is not supported on AIX. diff --git a/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll b/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll index 9116ea4e8d9d..b179b86c896a 100644 --- a/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll +++ b/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll @@ -8,7 +8,7 @@ ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=32-DIS %s -; RUN: not llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: not --crash llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -mcpu=pwr4 -mattr=-altivec -filetype=obj < %s 2>&1 | FileCheck \ ; RUN: --check-prefix=64-CHECK %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll index d6e772ffc928..a1f1f12f9687 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s -; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ +; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=OBJ64 %s ; OBJ64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll index d911383dcff9..44a740c7c7ac 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -9,7 +9,7 @@ ; RUN: FileCheck --check-prefix=OBJ %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s -; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ +; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll index 536229fc8c45..ad77eeb349d4 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll @@ -6,7 +6,7 @@ ; RUN: FileCheck --check-prefix=OBJ %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s -; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ +; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=OBJ64 %s ; OBJ64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll index 8b7032af6600..0b8f43f9c791 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll @@ -5,7 +5,7 @@ ; RUN: llvm-readobj -t %t.o | FileCheck --check-prefix=SYM %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s -; RUN: not llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -mattr=-altivec -filetype=obj < %s 2>&1 | \ +; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -mattr=-altivec -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll index e846b39f07c4..05fde17c9527 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll @@ -7,7 +7,7 @@ ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s -; RUN: not llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ +; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll index 543cca720293..feab85f87bc9 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll @@ -6,7 +6,7 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: not llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \ +; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \ ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/codemodel.ll b/llvm/test/CodeGen/PowerPC/codemodel.ll index ee3ceae6df23..cbceaf78b176 100644 --- a/llvm/test/CodeGen/PowerPC/codemodel.ll +++ b/llvm/test/CodeGen/PowerPC/codemodel.ll @@ -1,5 +1,5 @@ -; RUN: not llc -verify-machineinstrs -o - -mtriple=powerpc-pc-linux -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY -; RUN: not llc -verify-machineinstrs -o - -mtriple=powerpc-pc-linux -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=powerpc-pc-linux -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=powerpc-pc-linux -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL ; TINY: Target does not support the tiny CodeModel ; KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll index 3f02d4f6c3ef..78cf10ebe688 100644 --- a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll +++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll @@ -2,7 +2,7 @@ ; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \ ; RUN: %s | FileCheck --check-prefix=SMALL %s -; RUN: not llc -mtriple powerpc-ibm-aix-xcoff -code-model=medium \ +; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff -code-model=medium \ ; RUN: -stop-after=machine-cp 2>&1 < %s | FileCheck --check-prefix=MEDIUM %s ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=large \ diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll index 7e00a595c60a..29119f3257ad 100644 --- a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll +++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll @@ -2,7 +2,7 @@ ; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \ ; RUN: %s | FileCheck --check-prefix=SMALL %s -; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -code-model=medium \ +; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -code-model=medium \ ; RUN: -stop-after=machine-cp 2>&1 < %s | FileCheck --check-prefix=MEDIUM %s ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=large \ diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll index 2506f474cb23..11cb72296e2c 100644 --- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll +++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll @@ -1,6 +1,6 @@ -; RUN: not llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s define i32 @get_reg() nounwind { entry: diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll index de251350861f..3df778f445c7 100644 --- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll +++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s define i64 @get_reg() nounwind { entry: diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll index 0083f47fd2a5..ca79f857548e 100644 --- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll +++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32 +; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32 define i32 @get_reg() nounwind { entry: diff --git a/llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll b/llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll index 65b45ea555ae..e0ff14e60bb0 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll @@ -1,6 +1,6 @@ ; Test the ICBT instruction is not emitted on POWER7 ; Based on the ppc64-prefetch.ll test -; RUN: not llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 | FileCheck %s declare void @llvm.prefetch(i8*, i32, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/get-register-invalid.ll b/llvm/test/CodeGen/RISCV/get-register-invalid.ll index ee8ec44cef51..1f23445b4f73 100644 --- a/llvm/test/CodeGen/RISCV/get-register-invalid.ll +++ b/llvm/test/CodeGen/RISCV/get-register-invalid.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -mtriple=riscv32 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=riscv32 2>&1 | FileCheck %s define i32 @get_invalid_reg() nounwind { entry: diff --git a/llvm/test/CodeGen/RISCV/get-register-reserve.ll b/llvm/test/CodeGen/RISCV/get-register-reserve.ll index 7549b4dd3f68..87acd70ec62f 100644 --- a/llvm/test/CodeGen/RISCV/get-register-reserve.ll +++ b/llvm/test/CodeGen/RISCV/get-register-reserve.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: not llc < %s -mtriple=riscv32 -mattr +reserve-x8 2>&1 \ +; RUN: not --crash llc < %s -mtriple=riscv32 -mattr +reserve-x8 2>&1 \ ; RUN: | FileCheck -check-prefix=NO-RESERVE-A1 %s -; RUN: not llc < %s -mtriple=riscv32 -mattr +reserve-x11 2>&1 \ +; RUN: not --crash llc < %s -mtriple=riscv32 -mattr +reserve-x11 2>&1 \ ; RUN: | FileCheck -check-prefix=NO-RESERVE-FP %s ; RUN: llc < %s -mtriple=riscv32 -mattr +reserve-x8 -mattr +reserve-x11 \ ; RUN: | FileCheck -check-prefix=RESERVE %s diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll index 5f246cd66298..3458780bfc57 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll @@ -1,6 +1,6 @@ -; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \ +; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \ +; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments! diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll index bddca8af7468..2bcec1589df0 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll @@ -1,6 +1,6 @@ -; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \ +; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \ +; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Function interrupt attribute argument not supported! diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll index 58827a860608..a865090546fe 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll @@ -1,6 +1,6 @@ -; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \ +; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \ +; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type! diff --git a/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll b/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll index cb24405b1606..fe4d570b9d90 100644 --- a/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll +++ b/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \ +; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64E %s ; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target diff --git a/llvm/test/CodeGen/RISCV/module-target-abi.ll b/llvm/test/CodeGen/RISCV/module-target-abi.ll index b2930a06ab74..bc61c50b0822 100644 --- a/llvm/test/CodeGen/RISCV/module-target-abi.ll +++ b/llvm/test/CodeGen/RISCV/module-target-abi.ll @@ -2,7 +2,7 @@ ; RUN: | FileCheck -check-prefix=DEFAULT %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s -; RUN: not llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ +; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s ; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck -check-prefixes=FLAGS %s diff --git a/llvm/test/CodeGen/RISCV/module-target-abi2.ll b/llvm/test/CodeGen/RISCV/module-target-abi2.ll index f07f2770ace7..8664c9add069 100644 --- a/llvm/test/CodeGen/RISCV/module-target-abi2.ll +++ b/llvm/test/CodeGen/RISCV/module-target-abi2.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=riscv32 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=DEFAULT %s -; RUN: not llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ +; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s diff --git a/llvm/test/CodeGen/RISCV/musttail-call.ll b/llvm/test/CodeGen/RISCV/musttail-call.ll index 551aa7245ce6..37b0ab456928 100644 --- a/llvm/test/CodeGen/RISCV/musttail-call.ll +++ b/llvm/test/CodeGen/RISCV/musttail-call.ll @@ -1,12 +1,12 @@ ; Check that we error out if tail is not possible but call is marked as mustail. -; RUN: not llc -mtriple riscv32-unknown-linux-gnu -o - %s \ +; RUN: not --crash llc -mtriple riscv32-unknown-linux-gnu -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \ +; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not llc -mtriple riscv64-unknown-linux-gnu -o - %s \ +; RUN: not --crash llc -mtriple riscv64-unknown-linux-gnu -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \ +; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s %struct.A = type { i32 } diff --git a/llvm/test/CodeGen/RISCV/rv32e.ll b/llvm/test/CodeGen/RISCV/rv32e.ll index 2416639dc93c..88379ab43872 100644 --- a/llvm/test/CodeGen/RISCV/rv32e.ll +++ b/llvm/test/CodeGen/RISCV/rv32e.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=riscv32 -mattr=+e < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=riscv32 -mattr=+e < %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Codegen not yet implemented for RV32E diff --git a/llvm/test/CodeGen/RISCV/target-abi-valid.ll b/llvm/test/CodeGen/RISCV/target-abi-valid.ll index 2bd7dde3cd8e..2d4079601f7b 100644 --- a/llvm/test/CodeGen/RISCV/target-abi-valid.ll +++ b/llvm/test/CodeGen/RISCV/target-abi-valid.ll @@ -34,7 +34,7 @@ define void @nothing() nounwind { ret void } -; RUN: not llc -mtriple=riscv32 -target-abi ilp32e < %s 2>&1 \ +; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32e < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=CHECK-UNIMP %s ; CHECK-UNIMP: LLVM ERROR: Don't know how to lower this ABI diff --git a/llvm/test/CodeGen/RISCV/verify-instr.mir b/llvm/test/CodeGen/RISCV/verify-instr.mir index ed31126b53d4..58fcbc3e47de 100644 --- a/llvm/test/CodeGen/RISCV/verify-instr.mir +++ b/llvm/test/CodeGen/RISCV/verify-instr.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llc -march=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s # CHECK: *** Bad machine code: Invalid immediate *** # CHECK: - instruction: $x2 = ADDI $x1, 10000 diff --git a/llvm/test/CodeGen/SPARC/codemodel.ll b/llvm/test/CodeGen/SPARC/codemodel.ll index 68da48a0e950..fae56b801c9c 100644 --- a/llvm/test/CodeGen/SPARC/codemodel.ll +++ b/llvm/test/CodeGen/SPARC/codemodel.ll @@ -1,5 +1,5 @@ -; RUN: not llc -verify-machineinstrs -o - -mtriple=sparc64-unknown-linux -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY -; RUN: not llc -verify-machineinstrs -o - -mtriple=sparc64-unknown-linux -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=sparc64-unknown-linux -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=sparc64-unknown-linux -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL ; TINY: Target does not support the tiny CodeModel ; KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/SPARC/fail-alloca-align.ll b/llvm/test/CodeGen/SPARC/fail-alloca-align.ll index b8d84a901f56..062e3a4489f2 100644 --- a/llvm/test/CodeGen/SPARC/fail-alloca-align.ll +++ b/llvm/test/CodeGen/SPARC/fail-alloca-align.ll @@ -2,8 +2,8 @@ ;; alignment greater than the stack alignment. This code ought to ;; compile, but doesn't currently. -;; RUN: not llc -march=sparc < %s 2>&1 | FileCheck %s -;; RUN: not llc -march=sparcv9 < %s 2>&1 | FileCheck %s +;; RUN: not --crash llc -march=sparc < %s 2>&1 | FileCheck %s +;; RUN: not --crash llc -march=sparcv9 < %s 2>&1 | FileCheck %s ;; CHECK: ERROR: Function {{.*}} required stack re-alignment define void @variable_alloca_with_overalignment(i32 %num) { diff --git a/llvm/test/CodeGen/SPARC/sret-secondary.ll b/llvm/test/CodeGen/SPARC/sret-secondary.ll index 4efcabfc6fb3..8f334e823834 100644 --- a/llvm/test/CodeGen/SPARC/sret-secondary.ll +++ b/llvm/test/CodeGen/SPARC/sret-secondary.ll @@ -1,4 +1,4 @@ -; RUN: not llc -march=sparc < %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not --crash llc -march=sparc < %s -o /dev/null 2>&1 | FileCheck %s ; CHECK: sparc only supports sret on the first parameter diff --git a/llvm/test/CodeGen/SystemZ/codemodel.ll b/llvm/test/CodeGen/SystemZ/codemodel.ll index 4375366cfd79..a96a28a5167c 100644 --- a/llvm/test/CodeGen/SystemZ/codemodel.ll +++ b/llvm/test/CodeGen/SystemZ/codemodel.ll @@ -1,5 +1,5 @@ -; RUN: not llc -verify-machineinstrs -o - -mtriple=s390x-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY -; RUN: not llc -verify-machineinstrs -o - -mtriple=s390x-linux-gnu -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=s390x-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY +; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=s390x-linux-gnu -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL ; TINY: Target does not support the tiny CodeModel ; KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-02.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-02.ll index 1d13429d2084..dfe3b2694172 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-02.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-02.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; Check that no more than 12 integer arguments are passed ; -; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc void @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-03.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-03.ll index 1db7a3ff3dbb..1761cc4f09b7 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-03.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-03.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; In GHC calling convention the only allowed return type is void ; -; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc i64 @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-04.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-04.ll index 0dbe5472207a..d6b089808cf7 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-04.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-04.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; Thread local storage is not supported in GHC calling convention ; -; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s @x = thread_local global i32 0 diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-05.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-05.ll index be2cc67807bf..68c0ee2e9ed9 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-05.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-05.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; Variable-sized stack allocations are not supported in GHC calling convention ; -; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc void @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-06.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-06.ll index 04df248c29f8..e0213e925936 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-06.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-06.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; At most 2048*sizeof(long)=16384 bytes of stack space may be used ; -; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc void @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-07.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-07.ll index e9bb3b5e18a3..278e64303803 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-07.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-07.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; In GHC calling convention a frame pointer is not supported ; -; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc void @foo(i64 %0) nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll b/llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll index 4a3629111318..d6bb1ae7150a 100644 --- a/llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll +++ b/llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll @@ -1,4 +1,4 @@ -; RUN: not llc %s -mtriple=s390x-linux-gnu -o - 2>&1 | FileCheck %s +; RUN: not --crash llc %s -mtriple=s390x-linux-gnu -o - 2>&1 | FileCheck %s ; ; CHECK: LLVM ERROR: mnop-mcount only supported with fentry-call diff --git a/llvm/test/CodeGen/SystemZ/mrecord-mcount-02.ll b/llvm/test/CodeGen/SystemZ/mrecord-mcount-02.ll index 9ce7cdd418e3..e1f4a3748b76 100644 --- a/llvm/test/CodeGen/SystemZ/mrecord-mcount-02.ll +++ b/llvm/test/CodeGen/SystemZ/mrecord-mcount-02.ll @@ -1,4 +1,4 @@ -; RUN: not llc %s -mtriple=s390x-linux-gnu -o - 2>&1 | FileCheck %s +; RUN: not --crash llc %s -mtriple=s390x-linux-gnu -o - 2>&1 | FileCheck %s ; ; CHECK: LLVM ERROR: mrecord-mcount only supported with fentry-call diff --git a/llvm/test/CodeGen/SystemZ/mverify-optypes.mir b/llvm/test/CodeGen/SystemZ/mverify-optypes.mir index aebafd395623..cc0be4423348 100644 --- a/llvm/test/CodeGen/SystemZ/mverify-optypes.mir +++ b/llvm/test/CodeGen/SystemZ/mverify-optypes.mir @@ -1,6 +1,5 @@ -# RUN: not llc -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass=none -o - %s \ +# RUN: not --crash llc -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass=none -o - %s \ # RUN: 2>&1 | FileCheck %s -# REQUIRES: asserts # # Test that the machine verifier catches wrong operand types. diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-01.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-01.ll index e2f537949595..5680873fb8ee 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-01.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-01.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s define void @foo(<1 x i128>) { ret void diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-02.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-02.ll index a5ae1102a748..7c0efe5b8afe 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-02.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-02.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s define <1 x i128> @foo() { ret <1 x i128> diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-03.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-03.ll index 14698aae43bc..7c8be0136345 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-03.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-03.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s declare void @bar(<1 x i128>) diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-04.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-04.ll index a54ee90022c8..f0b248c93486 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-04.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-04.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s declare <1 x i128> @bar() diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-05.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-05.ll index 067deb1c88b8..c04095e7a737 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-05.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-05.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s define void @foo(<1 x fp128>) { ret void diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-06.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-06.ll index a9184d735750..73891be036a8 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-06.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-06.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s define <1 x fp128> @foo() { ret <1 x fp128> diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-07.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-07.ll index 4e9140093915..4914217f0026 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-07.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-07.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s declare void @bar(<1 x fp128>) diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-08.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-08.ll index 7b16b9f46e39..8670b8fa4c78 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-08.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-08.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s declare <1 x fp128> @bar() diff --git a/llvm/test/CodeGen/WebAssembly/clear-cache.ll b/llvm/test/CodeGen/WebAssembly/clear-cache.ll index cab948828233..4e1aee438ebe 100644 --- a/llvm/test/CodeGen/WebAssembly/clear-cache.ll +++ b/llvm/test/CodeGen/WebAssembly/clear-cache.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -asm-verbose=false 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -asm-verbose=false 2>&1 | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target triple = "wasm32-unknown-unknown" diff --git a/llvm/test/CodeGen/WebAssembly/cpus.ll b/llvm/test/CodeGen/WebAssembly/cpus.ll index 01964e9c85ab..b9210bd4d7f9 100644 --- a/llvm/test/CodeGen/WebAssembly/cpus.ll +++ b/llvm/test/CodeGen/WebAssembly/cpus.ll @@ -1,13 +1,13 @@ ; This tests that llc accepts all valid WebAssembly CPUs. ; RUN: llc < %s -asm-verbose=false -mtriple=wasm32-unknown-unknown -mcpu=mvp 2>&1 | FileCheck %s -; RUN: not llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=mvp 2>&1 | FileCheck %s --check-prefix=WASM64 +; RUN: not --crash llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=mvp 2>&1 | FileCheck %s --check-prefix=WASM64 ; RUN: llc < %s -asm-verbose=false -mtriple=wasm32-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s -; RUN: not llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=generic 2>&1 | FileCheck %s --check-prefix=WASM64 +; RUN: not --crash llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=generic 2>&1 | FileCheck %s --check-prefix=WASM64 ; RUN: llc < %s -asm-verbose=false -mtriple=wasm32-unknown-unknown -mcpu=bleeding-edge 2>&1 | FileCheck %s -; RUN: not llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=bleeding-edge 2>&1 | FileCheck %s --check-prefix=WASM64 +; RUN: not --crash llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=bleeding-edge 2>&1 | FileCheck %s --check-prefix=WASM64 ; RUN: llc < %s -asm-verbose=false -mtriple=wasm32-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID -; RUN: not llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=WASM64 +; RUN: not --crash llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=WASM64 ; CHECK-NOT: is not a recognized processor for this target ; INVALID: {{.+}} is not a recognized processor for this target diff --git a/llvm/test/CodeGen/WebAssembly/exception.ll b/llvm/test/CodeGen/WebAssembly/exception.ll index af470b27e89d..375b4c0c4376 100644 --- a/llvm/test/CodeGen/WebAssembly/exception.ll +++ b/llvm/test/CodeGen/WebAssembly/exception.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm +; RUN: not --crash llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -exception-model=wasm -mattr=+exception-handling -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap %s ; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm -mattr=+exception-handling diff --git a/llvm/test/CodeGen/WebAssembly/offset-atomics.ll b/llvm/test/CodeGen/WebAssembly/offset-atomics.ll index 6884b6a56ee7..43966a80ba4e 100644 --- a/llvm/test/CodeGen/WebAssembly/offset-atomics.ll +++ b/llvm/test/CodeGen/WebAssembly/offset-atomics.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt +; RUN: not --crash llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics,+sign-ext | FileCheck %s ; Test that atomic loads are assembled properly. diff --git a/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll b/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll index 41dbd476b065..1ce100b8653c 100644 --- a/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll +++ b/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory 2>&1 | FileCheck %s --check-prefix=ERROR -; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory -fast-isel 2>&1 | FileCheck %s --check-prefix=ERROR +; RUN: not --crash llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory 2>&1 | FileCheck %s --check-prefix=ERROR +; RUN: not --crash llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory -fast-isel 2>&1 | FileCheck %s --check-prefix=ERROR ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory --mtriple wasm32-unknown-emscripten | FileCheck %s --check-prefixes=CHECK,TLS ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory --mtriple wasm32-unknown-emscripten -fast-isel | FileCheck %s --check-prefixes=CHECK,TLS ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-bulk-memory | FileCheck %s --check-prefixes=CHECK,NO-TLS diff --git a/llvm/test/CodeGen/X86/AppendingLinkage.ll b/llvm/test/CodeGen/X86/AppendingLinkage.ll index 5ab49a28e96d..83bfbe85240a 100644 --- a/llvm/test/CodeGen/X86/AppendingLinkage.ll +++ b/llvm/test/CodeGen/X86/AppendingLinkage.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -mtriple=i686-- 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=i686-- 2>&1 | FileCheck %s ; CHECK: unknown special variable @foo = appending constant [1 x i32 ]zeroinitializer diff --git a/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir b/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir index 31f1da5c674f..2c70ed3b0451 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -run-pass=instruction-select -pass-remarks-missed=gisel %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -run-pass=instruction-select -pass-remarks-missed=gisel %s 2>&1 | FileCheck %s --- | target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64--linux-gnu" diff --git a/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir b/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir index 77962d7fbfa3..fd726b882b56 100644 --- a/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir +++ b/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ +# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ # RUN: -run-pass=cfi-instr-inserter 2>&1 | FileCheck %s # Test that CFI verifier finds inconsistent offset between bb.end and one of # its precedessors. diff --git a/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir b/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir index 1a247824bc9e..30344edc259c 100644 --- a/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir +++ b/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ +# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ # RUN: -run-pass=cfi-instr-inserter 2>&1 | FileCheck %s # Test that CFI verifier finds inconsistent register between bb.end and one of # its precedessors. diff --git a/llvm/test/CodeGen/X86/clwb.ll b/llvm/test/CodeGen/X86/clwb.ll index 90862343d31c..75ca48329eed 100644 --- a/llvm/test/CodeGen/X86/clwb.ll +++ b/llvm/test/CodeGen/X86/clwb.ll @@ -3,7 +3,7 @@ ; NOTE: Cannon Lake arch, but available again in the newer Ice Lake arch. ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=clwb | FileCheck %s ; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=skx | FileCheck %s -; RUN: not llc < %s -mtriple=i686-apple-darwin -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CNL +; RUN: not --crash llc < %s -mtriple=i686-apple-darwin -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CNL ; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=icelake-client | FileCheck %s ; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=icelake-server | FileCheck %s diff --git a/llvm/test/CodeGen/X86/codemodel.ll b/llvm/test/CodeGen/X86/codemodel.ll index d7ed7c460889..9aba38ab3a26 100644 --- a/llvm/test/CodeGen/X86/codemodel.ll +++ b/llvm/test/CodeGen/X86/codemodel.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s ; RUN: llc < %s -code-model=kernel | FileCheck -check-prefix CHECK-KERNEL %s -; RUN: not llc < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s +; RUN: not --crash llc < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/coff-comdat2.ll b/llvm/test/CodeGen/X86/coff-comdat2.ll index a417d096c47d..3538e7ec1017 100644 --- a/llvm/test/CodeGen/X86/coff-comdat2.ll +++ b/llvm/test/CodeGen/X86/coff-comdat2.ll @@ -1,4 +1,4 @@ -; RUN: not llc %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not --crash llc %s -o /dev/null 2>&1 | FileCheck %s target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32" target triple = "i686-pc-windows-msvc" diff --git a/llvm/test/CodeGen/X86/coff-comdat3.ll b/llvm/test/CodeGen/X86/coff-comdat3.ll index 01651ce4820a..95a23742efae 100644 --- a/llvm/test/CodeGen/X86/coff-comdat3.ll +++ b/llvm/test/CodeGen/X86/coff-comdat3.ll @@ -1,4 +1,4 @@ -; RUN: not llc %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not --crash llc %s -o /dev/null 2>&1 | FileCheck %s target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32" target triple = "i686-pc-windows-msvc" diff --git a/llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll b/llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll index 0dadc599abdb..cb5c8f714321 100644 --- a/llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll +++ b/llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll @@ -2,15 +2,15 @@ ; CHECK-NO-ERROR-NOT: not a recognized processor for this target ; CHECK-ERROR64: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it! -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-tbird 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-mp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=geode 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-tbird 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-mp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=geode 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 define void @foo() { ret void diff --git a/llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll b/llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll index d28ac9a83fd8..cf133aea6359 100644 --- a/llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll +++ b/llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll @@ -2,22 +2,22 @@ ; CHECK-NO-ERROR-NOT: not a recognized processor for this target ; CHECK-ERROR64: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it! -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i386 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i486 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i386 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i486 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 define void @foo() { ret void diff --git a/llvm/test/CodeGen/X86/cpus-no-x86_64.ll b/llvm/test/CodeGen/X86/cpus-no-x86_64.ll index e2e000386717..6f74d4b29dab 100644 --- a/llvm/test/CodeGen/X86/cpus-no-x86_64.ll +++ b/llvm/test/CodeGen/X86/cpus-no-x86_64.ll @@ -2,10 +2,10 @@ ; CHECK-NO-ERROR-NOT: not a recognized processor for this target ; CHECK-ERROR64: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it! -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip-c6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip-c6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR define void @foo() { ret void diff --git a/llvm/test/CodeGen/X86/equiv_with_fndef.ll b/llvm/test/CodeGen/X86/equiv_with_fndef.ll index efbb8ab3da69..3da0aa60250c 100644 --- a/llvm/test/CodeGen/X86/equiv_with_fndef.ll +++ b/llvm/test/CodeGen/X86/equiv_with_fndef.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s 2>&1 | FileCheck %s +; RUN: not --crash llc < %s 2>&1 | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/equiv_with_vardef.ll b/llvm/test/CodeGen/X86/equiv_with_vardef.ll index 29c19a107ec3..e5ea3673b6d7 100644 --- a/llvm/test/CodeGen/X86/equiv_with_vardef.ll +++ b/llvm/test/CodeGen/X86/equiv_with_vardef.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s 2>&1 | FileCheck %s +; RUN: not --crash llc < %s 2>&1 | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/expand-integer-x86_64-intrinsic-error.ll b/llvm/test/CodeGen/X86/expand-integer-x86_64-intrinsic-error.ll index 34f3c258f738..d0d28db04f44 100644 --- a/llvm/test/CodeGen/X86/expand-integer-x86_64-intrinsic-error.ll +++ b/llvm/test/CodeGen/X86/expand-integer-x86_64-intrinsic-error.ll @@ -1,4 +1,4 @@ -;RUN: not llc < %s -mtriple=i686-unknown-unknown -mattr=sse2 2>&1 | FileCheck %s --check-prefix=CHECK +; RUN: not --crash llc < %s -mtriple=i686-unknown-unknown -mattr=sse2 2>&1 | FileCheck %s --check-prefix=CHECK ; Make sure we generate fatal error from the type legalizer for using a 64-bit ; mode intrinsics in 32-bit mode. We used to use an llvm_unreachable. diff --git a/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll b/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll index f7066577f2de..007ac1d9a3c2 100644 --- a/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll +++ b/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll @@ -1,5 +1,4 @@ -; RUN: not llc < %s -fast-isel -fast-isel-abort=2 -mtriple=x86_64-apple-darwin10 -; REQUIRES: asserts +; RUN: not --crash llc < %s -fast-isel -fast-isel-abort=2 -mtriple=x86_64-apple-darwin10 %struct.s0 = type { x86_fp80, x86_fp80 } diff --git a/llvm/test/CodeGen/X86/inalloca-regparm.ll b/llvm/test/CodeGen/X86/inalloca-regparm.ll index 9dd916bfbb37..d379333a962f 100644 --- a/llvm/test/CodeGen/X86/inalloca-regparm.ll +++ b/llvm/test/CodeGen/X86/inalloca-regparm.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=i686-windows-msvc < %s -o /dev/null -; RUN: not llc -mtriple=x86_64-windows-msvc %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not --crash llc -mtriple=x86_64-windows-msvc %s -o /dev/null 2>&1 | FileCheck %s ; This will compile successfully on x86 but not x86_64, because %b will become a ; register parameter. diff --git a/llvm/test/CodeGen/X86/invalid-liveness.mir b/llvm/test/CodeGen/X86/invalid-liveness.mir index c324241805ad..416921ddcd01 100644 --- a/llvm/test/CodeGen/X86/invalid-liveness.mir +++ b/llvm/test/CodeGen/X86/invalid-liveness.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=i686-- -run-pass liveintervals -o - %s 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=i686-- -run-pass liveintervals -o - %s 2>&1 | FileCheck %s # REQUIRES: asserts --- | diff --git a/llvm/test/CodeGen/X86/label-redefinition.ll b/llvm/test/CodeGen/X86/label-redefinition.ll index 9e88a18e8732..b5570e6931b9 100644 --- a/llvm/test/CodeGen/X86/label-redefinition.ll +++ b/llvm/test/CodeGen/X86/label-redefinition.ll @@ -1,5 +1,5 @@ ; PR7054 -; RUN: not llc %s -o - 2>&1 | grep "'_foo' label emitted multiple times to assembly" +; RUN: not --crash llc %s -o - 2>&1 | grep "'_foo' label emitted multiple times to assembly" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target triple = "i386-apple-darwin10.0.0" diff --git a/llvm/test/CodeGen/X86/llc-print-machineinstrs.mir b/llvm/test/CodeGen/X86/llc-print-machineinstrs.mir index a890840a478a..c3f8df031337 100644 --- a/llvm/test/CodeGen/X86/llc-print-machineinstrs.mir +++ b/llvm/test/CodeGen/X86/llc-print-machineinstrs.mir @@ -1,6 +1,6 @@ # Check that -print-machineinstrs doesn't assert when it's passed an unknown pass name. # RUN: llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=greedy %s -o /dev/null -# RUN: not llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=unknown %s -o /dev/null 2>&1 | FileCheck %s +# RUN: not --crash llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=unknown %s -o /dev/null 2>&1 | FileCheck %s # CHECK: LLVM ERROR: "unknown" pass is not registered. ... diff --git a/llvm/test/CodeGen/X86/macho-comdat.ll b/llvm/test/CodeGen/X86/macho-comdat.ll index 60560470ed5b..c96212127dba 100644 --- a/llvm/test/CodeGen/X86/macho-comdat.ll +++ b/llvm/test/CodeGen/X86/macho-comdat.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple x86_64-apple-darwin < %s 2> %t +; RUN: not --crash llc -mtriple x86_64-apple-darwin < %s 2> %t ; RUN: FileCheck < %t %s $f = comdat any diff --git a/llvm/test/CodeGen/X86/named-reg-alloc.ll b/llvm/test/CodeGen/X86/named-reg-alloc.ll index c33b4eb75d04..34c5ea99f94c 100644 --- a/llvm/test/CodeGen/X86/named-reg-alloc.ll +++ b/llvm/test/CodeGen/X86/named-reg-alloc.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/X86/named-reg-notareg.ll b/llvm/test/CodeGen/X86/named-reg-notareg.ll index 18c517d87810..6da65e2dfd02 100644 --- a/llvm/test/CodeGen/X86/named-reg-notareg.ll +++ b/llvm/test/CodeGen/X86/named-reg-notareg.ll @@ -1,5 +1,5 @@ -; RUN: not llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s -; RUN: not llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/X86/nonconst-static-ev.ll b/llvm/test/CodeGen/X86/nonconst-static-ev.ll index a0aa6152bd47..23643a2aafdf 100644 --- a/llvm/test/CodeGen/X86/nonconst-static-ev.ll +++ b/llvm/test/CodeGen/X86/nonconst-static-ev.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=i686-linux-gnu < %s 2> %t +; RUN: not --crash llc -mtriple=i686-linux-gnu < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s @0 = global i8 extractvalue ([1 x i8] select (i1 ptrtoint (i32* @1 to i1), [1 x i8] [ i8 1 ], [1 x i8] [ i8 2 ]), 0) diff --git a/llvm/test/CodeGen/X86/nonconst-static-iv.ll b/llvm/test/CodeGen/X86/nonconst-static-iv.ll index b1a03cf8b2e5..0e35116e3f8a 100644 --- a/llvm/test/CodeGen/X86/nonconst-static-iv.ll +++ b/llvm/test/CodeGen/X86/nonconst-static-iv.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=i686-linux-gnu < %s 2> %t +; RUN: not --crash llc -mtriple=i686-linux-gnu < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s @0 = global i8 insertvalue( { i8 } select (i1 ptrtoint (i32* @1 to i1), { i8 } { i8 1 }, { i8 } { i8 2 }), i8 0, 0) diff --git a/llvm/test/CodeGen/X86/read-fp-no-frame-pointer.ll b/llvm/test/CodeGen/X86/read-fp-no-frame-pointer.ll index 9f78c294ce88..f59388e450ba 100644 --- a/llvm/test/CodeGen/X86/read-fp-no-frame-pointer.ll +++ b/llvm/test/CodeGen/X86/read-fp-no-frame-pointer.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_frame() nounwind { entry: diff --git a/llvm/test/CodeGen/X86/segmented-stacks.ll b/llvm/test/CodeGen/X86/segmented-stacks.ll index c4539f7b1255..467182c9f407 100644 --- a/llvm/test/CodeGen/X86/segmented-stacks.ll +++ b/llvm/test/CodeGen/X86/segmented-stacks.ll @@ -22,9 +22,9 @@ ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-dragonfly -filetype=obj -o /dev/null ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-mingw32 -filetype=obj -o /dev/null -; RUN: not llc < %s -mcpu=generic -mtriple=x86_64-solaris 2> %t.log +; RUN: not --crash llc < %s -mcpu=generic -mtriple=x86_64-solaris 2> %t.log ; RUN: FileCheck %s -input-file=%t.log -check-prefix=X64-Solaris -; RUN: not llc < %s -mcpu=generic -mtriple=i686-freebsd 2> %t.log +; RUN: not --crash llc < %s -mcpu=generic -mtriple=i686-freebsd 2> %t.log ; RUN: FileCheck %s -input-file=%t.log -check-prefix=X32-FreeBSD ; X64-Solaris: Segmented stacks not supported on this platform diff --git a/llvm/test/CodeGen/XCore/alignment.ll b/llvm/test/CodeGen/XCore/alignment.ll index 28bdf3b74208..0c561ee4f6c6 100644 --- a/llvm/test/CodeGen/XCore/alignment.ll +++ b/llvm/test/CodeGen/XCore/alignment.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=xcore 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=xcore 2>&1 | FileCheck %s ; CHECK: emitPrologue unsupported alignment: 8 define void @f() nounwind { diff --git a/llvm/test/CodeGen/XCore/codemodel.ll b/llvm/test/CodeGen/XCore/codemodel.ll index 93b9d6d911df..fdc0d086c679 100644 --- a/llvm/test/CodeGen/XCore/codemodel.ll +++ b/llvm/test/CodeGen/XCore/codemodel.ll @@ -1,7 +1,7 @@ -; RUN: not llc < %s -march=xcore -code-model=medium 2>&1 | FileCheck %s -check-prefix=BAD_CM -; RUN: not llc < %s -march=xcore -code-model=kernel 2>&1 | FileCheck %s -check-prefix=BAD_CM -; RUN: not llc < %s -march=xcore -code-model=tiny 2>&1 | FileCheck %s -check-prefix=BAD_CM +; RUN: not --crash llc < %s -march=xcore -code-model=medium 2>&1 | FileCheck %s -check-prefix=BAD_CM +; RUN: not --crash llc < %s -march=xcore -code-model=kernel 2>&1 | FileCheck %s -check-prefix=BAD_CM +; RUN: not --crash llc < %s -march=xcore -code-model=tiny 2>&1 | FileCheck %s -check-prefix=BAD_CM ; BAD_CM: Target only supports CodeModel Small or Large diff --git a/llvm/test/CodeGen/XCore/section-name.ll b/llvm/test/CodeGen/XCore/section-name.ll index 65161db34bea..4bf6aa1fc67a 100644 --- a/llvm/test/CodeGen/XCore/section-name.ll +++ b/llvm/test/CodeGen/XCore/section-name.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -march=xcore 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -march=xcore 2>&1 | FileCheck %s @bar = internal global i32 zeroinitializer diff --git a/llvm/test/DebugInfo/COFF/types-recursive-unnamed.ll b/llvm/test/DebugInfo/COFF/types-recursive-unnamed.ll index 5e8edf5eb4f5..3f0a584b0e34 100644 --- a/llvm/test/DebugInfo/COFF/types-recursive-unnamed.ll +++ b/llvm/test/DebugInfo/COFF/types-recursive-unnamed.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -filetype=obj 2>&1 | FileCheck %s +; RUN: not --crash llc < %s -filetype=obj 2>&1 | FileCheck %s ; ; Verify the compiler produces an error message when trying to emit circular ; references to unnamed structs which are not supported in CodeView debug diff --git a/llvm/test/LTO/X86/attrs.ll b/llvm/test/LTO/X86/attrs.ll index d1967470cdd3..4444735188fb 100644 --- a/llvm/test/LTO/X86/attrs.ll +++ b/llvm/test/LTO/X86/attrs.ll @@ -1,7 +1,7 @@ ; RUN: llvm-as < %s >%t1 ; RUN: llvm-lto -exported-symbol=test_x86_aesni_aeskeygenassist -mattr=+aes -o %t2 %t1 ; RUN: llvm-objdump -d %t2 | FileCheck -check-prefix=WITH_AES %s -; RUN: not llvm-lto -exported-symbol=test_x86_aesni_aeskeygenassist -mattr=-aes -o %t3 %t1 2>&1 | FileCheck -check-prefix=WITHOUT_AES %s +; RUN: not --crash llvm-lto -exported-symbol=test_x86_aesni_aeskeygenassist -mattr=-aes -o %t3 %t1 2>&1 | FileCheck -check-prefix=WITHOUT_AES %s target triple = "x86_64-unknown-linux-gnu" declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) diff --git a/llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s b/llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s index 34d88918a349..e831ac5c2af0 100644 --- a/llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s +++ b/llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -filetype=obj -triple armv7-linux-gnueabi %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple armv7-linux-gnueabi %s -o - 2>&1 | FileCheck %s # We cannot switch subtargets mid-bundle .syntax unified diff --git a/llvm/test/MC/ARM/Windows/invalid-relocation.s b/llvm/test/MC/ARM/Windows/invalid-relocation.s index c3e74e97634b..61d11fb6a6b3 100644 --- a/llvm/test/MC/ARM/Windows/invalid-relocation.s +++ b/llvm/test/MC/ARM/Windows/invalid-relocation.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple thumbv7-windows -incremental-linker-compatible -filetype obj -o /dev/null 2>&1 %s \ +# RUN: not --crash llvm-mc -triple thumbv7-windows -incremental-linker-compatible -filetype obj -o /dev/null 2>&1 %s \ # RUN: | FileCheck %s .def invalid_relocation diff --git a/llvm/test/MC/COFF/section-comdat-conflict.s b/llvm/test/MC/COFF/section-comdat-conflict.s index 7ed452a5cdcb..2710b76be565 100644 --- a/llvm/test/MC/COFF/section-comdat-conflict.s +++ b/llvm/test/MC/COFF/section-comdat-conflict.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s +// RUN: not --crash llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s // CHECK: conflicting sections for symbol diff --git a/llvm/test/MC/COFF/section-comdat-conflict2.s b/llvm/test/MC/COFF/section-comdat-conflict2.s index e2dfc2d68b2f..2b863299561c 100644 --- a/llvm/test/MC/COFF/section-comdat-conflict2.s +++ b/llvm/test/MC/COFF/section-comdat-conflict2.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s +// RUN: not --crash llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s // CHECK: two sections have the same comdat diff --git a/llvm/test/MC/Disassembler/AMDGPU/si-support.txt b/llvm/test/MC/Disassembler/AMDGPU/si-support.txt index f3f5ab946eb3..5538983597f7 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/si-support.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/si-support.txt @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -disassemble < %s 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -arch=amdgcn -mcpu=tahiti -disassemble < %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: Disassembly not yet supported for subtarget 0x00 0x00 0x00 0x7e diff --git a/llvm/test/MC/ELF/ARM/bss-non-zero-value.s b/llvm/test/MC/ELF/ARM/bss-non-zero-value.s index 999b8b019c9c..da946f1c95d9 100644 --- a/llvm/test/MC/ELF/ARM/bss-non-zero-value.s +++ b/llvm/test/MC/ELF/ARM/bss-non-zero-value.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -filetype=obj -triple arm-linux-gnu %s -o %t 2>%t.out +// RUN: not --crash llvm-mc -filetype=obj -triple arm-linux-gnu %s -o %t 2>%t.out // RUN: FileCheck --input-file=%t.out %s // CHECK: non-zero initializer found in section '.bss' .bss diff --git a/llvm/test/MC/ELF/common-error3.s b/llvm/test/MC/ELF/common-error3.s index a84779e653e0..e5204914970e 100644 --- a/llvm/test/MC/ELF/common-error3.s +++ b/llvm/test/MC/ELF/common-error3.s @@ -1,5 +1,5 @@ -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux %s 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux %s 2>&1 | FileCheck %s # CHECK: Symbol: C redeclared as different type .comm C,4,4 - .comm C,8,4 \ No newline at end of file + .comm C,8,4 diff --git a/llvm/test/MC/ELF/section-numeric-invalid-type.s b/llvm/test/MC/ELF/section-numeric-invalid-type.s index 19796dc64ac1..0e721099ff7c 100644 --- a/llvm/test/MC/ELF/section-numeric-invalid-type.s +++ b/llvm/test/MC/ELF/section-numeric-invalid-type.s @@ -1,7 +1,7 @@ // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux-gnu %s -o - \ // RUN: | llvm-readobj -S --symbols | FileCheck --check-prefix=OBJ %s -// RUN: not llvm-mc -filetype=asm -triple=x86_64-pc-linux-gnu %s -o - 2>&1 \ +// RUN: not --crash llvm-mc -filetype=asm -triple=x86_64-pc-linux-gnu %s -o - 2>&1 \ // RUN: | FileCheck --check-prefix=ASM %s .section .sec,"a",@0x7fffffff diff --git a/llvm/test/MC/MachO/variable-errors.s b/llvm/test/MC/MachO/variable-errors.s index 28308c691d91..952212041d56 100644 --- a/llvm/test/MC/MachO/variable-errors.s +++ b/llvm/test/MC/MachO/variable-errors.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o %t.o 2> %t.err +// RUN: not --crash llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o %t.o 2> %t.err // RUN: FileCheck < %t.err %s .data diff --git a/llvm/test/MC/Mips/micromips64-unsupported.s b/llvm/test/MC/Mips/micromips64-unsupported.s index bc38cfb41f74..05c4bc9df043 100644 --- a/llvm/test/MC/Mips/micromips64-unsupported.s +++ b/llvm/test/MC/Mips/micromips64-unsupported.s @@ -1,8 +1,8 @@ -# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6 -# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6 +# RUN: not --crash llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6 +# RUN: not --crash llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6 -# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64 -# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64 +# RUN: not --crash llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64 +# RUN: not --crash llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64 # 64R6: microMIPS64R6 is not supported # 64: microMIPS64 is not supported diff --git a/llvm/test/MC/Mips/micromips64r6-unsupported.s b/llvm/test/MC/Mips/micromips64r6-unsupported.s index 402e66724e46..d2afff72aa71 100644 --- a/llvm/test/MC/Mips/micromips64r6-unsupported.s +++ b/llvm/test/MC/Mips/micromips64r6-unsupported.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -filetype=obj -triple=mips64-unknown-linux -mattr=+micromips \ +# RUN: not --crash llvm-mc -filetype=obj -triple=mips64-unknown-linux -mattr=+micromips \ # RUN: -mcpu=mips64r6 %s 2>&1 | FileCheck %s -check-prefix=CHECK-OPTION # RUN: not llvm-mc -filetype=obj -triple=mips64-unknown-linux -mcpu=mips64r6 \ # RUN: %s 2>&1 | FileCheck %s -check-prefix=CHECK-MM-DIRECTIVE diff --git a/llvm/test/MC/Mips/nooddspreg-cmdarg.s b/llvm/test/MC/Mips/nooddspreg-cmdarg.s index 2ccce74a5f15..ef38331b5163 100644 --- a/llvm/test/MC/Mips/nooddspreg-cmdarg.s +++ b/llvm/test/MC/Mips/nooddspreg-cmdarg.s @@ -5,10 +5,10 @@ # RUN: llvm-readobj --sections --section-data --section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ -# RUN: not llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -mattr=+nooddspreg 2> %t0 +# RUN: not --crash llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -mattr=+nooddspreg 2> %t0 # RUN: FileCheck %s -check-prefix=INVALID < %t0 # -# RUN: not llvm-mc %s -triple mips64-unknown-linux-gnu -mattr=+nooddspreg 2> %t0 +# RUN: not --crash llvm-mc %s -triple mips64-unknown-linux-gnu -mattr=+nooddspreg 2> %t0 # RUN: FileCheck %s -check-prefix=INVALID < %t0 # # CHECK-ASM-NOT: .module nooddspreg diff --git a/llvm/test/MC/PowerPC/ppc64-localentry-error1.s b/llvm/test/MC/PowerPC/ppc64-localentry-error1.s index e47640fbeb05..c028da8ce619 100644 --- a/llvm/test/MC/PowerPC/ppc64-localentry-error1.s +++ b/llvm/test/MC/PowerPC/ppc64-localentry-error1.s @@ -1,7 +1,7 @@ -# RUN: not llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t +# RUN: not --crash llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t # RUN: FileCheck < %t %s -# RUN: not llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t +# RUN: not --crash llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t # RUN: FileCheck < %t %s sym: diff --git a/llvm/test/MC/PowerPC/ppc64-localentry-error2.s b/llvm/test/MC/PowerPC/ppc64-localentry-error2.s index b05687fe7b6f..89a30ee4c8ac 100644 --- a/llvm/test/MC/PowerPC/ppc64-localentry-error2.s +++ b/llvm/test/MC/PowerPC/ppc64-localentry-error2.s @@ -1,7 +1,7 @@ -# RUN: not llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t +# RUN: not --crash llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t # RUN: FileCheck < %t %s -# RUN: not llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t +# RUN: not --crash llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t # RUN: FileCheck < %t %s .globl remote_sym diff --git a/llvm/test/MC/PowerPC/pr24686.s b/llvm/test/MC/PowerPC/pr24686.s index 28cba230b8c4..35a379c697ea 100644 --- a/llvm/test/MC/PowerPC/pr24686.s +++ b/llvm/test/MC/PowerPC/pr24686.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple=powerpc64le-unknown-linux-gnu -filetype=obj %s \ +# RUN: not --crash llvm-mc -triple=powerpc64le-unknown-linux-gnu -filetype=obj %s \ # RUN: 2>&1 | FileCheck %s _stext: diff --git a/llvm/test/MC/RISCV/mattr-invalid-combination.s b/llvm/test/MC/RISCV/mattr-invalid-combination.s index 340a2f257875..f75fd3723ed4 100644 --- a/llvm/test/MC/RISCV/mattr-invalid-combination.s +++ b/llvm/test/MC/RISCV/mattr-invalid-combination.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \ +# RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \ # RUN: | FileCheck %s -check-prefix=RV64E # RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target diff --git a/llvm/test/MC/WebAssembly/blockaddress.ll b/llvm/test/MC/WebAssembly/blockaddress.ll index 52127ab27c84..2b733e0d37c8 100644 --- a/llvm/test/MC/WebAssembly/blockaddress.ll +++ b/llvm/test/MC/WebAssembly/blockaddress.ll @@ -1,6 +1,6 @@ ; TODO(sbc): Make this test pass by adding support for unnamed tempoaries ; in wasm relocations. -; RUN: not llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not --crash llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s target triple = "wasm32-unknown-unknown" diff --git a/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll b/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll index 7e9b28ac243b..84d7c537a4f4 100644 --- a/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll +++ b/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll @@ -1,4 +1,4 @@ -; RUN: not llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not --crash llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s ; CHECK: data symbols must live in a data section: data_symbol target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" diff --git a/llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s b/llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s index 5ce788098f36..697b8bf6ab6c 100644 --- a/llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s +++ b/llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s @@ -1,5 +1,5 @@ -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - 2>&1 | FileCheck %s # CHECK: ERROR: Fragment can't be larger than a bundle size diff --git a/llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s b/llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s index b0b595f4812f..b849d2b33300 100644 --- a/llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s +++ b/llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s # Missing .bundle_align_mode argument # CHECK: error: invalid option diff --git a/llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s b/llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s index 67ac55ed2f03..c02d0d6b19b4 100644 --- a/llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s +++ b/llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s @@ -1,5 +1,5 @@ -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - 2>&1 | FileCheck %s -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - 2>&1 | FileCheck %s # Switching mode will change subtarget, which we can't do within a bundle .text diff --git a/llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s b/llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s index 2f716544b154..65ee2d5b9f38 100644 --- a/llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s +++ b/llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s # .bundle_lock can't come without a .bundle_align_mode before it diff --git a/llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s b/llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s index a5812fd28ab1..6ea3c36beb1c 100644 --- a/llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s +++ b/llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s # This test invokes .bundle_lock and then switches to a different section # w/o the appropriate unlock. diff --git a/llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s b/llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s index a73f19ea4836..811ef95a451d 100644 --- a/llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s +++ b/llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s # .bundle_unlock can't come without a .bundle_lock before it diff --git a/llvm/test/MC/X86/check-end-of-data-region.s b/llvm/test/MC/X86/check-end-of-data-region.s index 3f7d9b617ef6..50f5dab73d35 100644 --- a/llvm/test/MC/X86/check-end-of-data-region.s +++ b/llvm/test/MC/X86/check-end-of-data-region.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=x86_64-apple-darwin -filetype=obj -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not --crash llvm-mc -triple=x86_64-apple-darwin -filetype=obj -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR .align 4 .data_region jt32 diff --git a/llvm/test/MC/X86/encoder-fail.s b/llvm/test/MC/X86/encoder-fail.s index 3e845fe7561b..d8d321fa8a1a 100644 --- a/llvm/test/MC/X86/encoder-fail.s +++ b/llvm/test/MC/X86/encoder-fail.s @@ -1,3 +1,3 @@ -// RUN: not llvm-mc -triple x86_64-unknown-unknown --show-encoding %s 2>&1 | FileCheck %s +// RUN: not --crash llvm-mc -triple x86_64-unknown-unknown --show-encoding %s 2>&1 | FileCheck %s // CHECK: LLVM ERROR: Cannot encode high byte register in REX-prefixed instruction movzx %dh, %rsi diff --git a/llvm/test/MC/X86/invalid-sleb.s b/llvm/test/MC/X86/invalid-sleb.s index ad27444d608f..7d7df351ce4e 100644 --- a/llvm/test/MC/X86/invalid-sleb.s +++ b/llvm/test/MC/X86/invalid-sleb.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux %s -o %t 2>&1 | FileCheck %s +// RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux %s -o %t 2>&1 | FileCheck %s // CHECK: sleb128 and uleb128 expressions must be absolute diff --git a/llvm/test/MC/X86/reloc-bss.s b/llvm/test/MC/X86/reloc-bss.s index 3cf26d8b28e5..6463b866f095 100644 --- a/llvm/test/MC/X86/reloc-bss.s +++ b/llvm/test/MC/X86/reloc-bss.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -filetype=obj -triple=x86_64-linux-gnu %s 2>&1 | FileCheck %s +# RUN: not --crash llvm-mc -filetype=obj -triple=x86_64-linux-gnu %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: cannot have fixups in virtual section! .section .init_array,"awT",@nobits diff --git a/llvm/test/MachineVerifier/live-ins-01.mir b/llvm/test/MachineVerifier/live-ins-01.mir index 51c05dacf055..5d6d2fa399e7 100644 --- a/llvm/test/MachineVerifier/live-ins-01.mir +++ b/llvm/test/MachineVerifier/live-ins-01.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s +# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s # REQUIRES: systemz-registered-target # Test that a the machine verifier reports an error when a register in diff --git a/llvm/test/MachineVerifier/live-ins-02.mir b/llvm/test/MachineVerifier/live-ins-02.mir index d76325cdd108..2cc63ac0cd21 100644 --- a/llvm/test/MachineVerifier/live-ins-02.mir +++ b/llvm/test/MachineVerifier/live-ins-02.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s +# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s # REQUIRES: systemz-registered-target # Test that a the machine verifier reports an error when a register in diff --git a/llvm/test/MachineVerifier/live-ins-03.mir b/llvm/test/MachineVerifier/live-ins-03.mir index b5345ccdc3b6..ae640c439d3e 100644 --- a/llvm/test/MachineVerifier/live-ins-03.mir +++ b/llvm/test/MachineVerifier/live-ins-03.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s +# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s # REQUIRES: systemz-registered-target # Test that a the machine verifier reports an error when a register in diff --git a/llvm/test/MachineVerifier/test_copy.mir b/llvm/test/MachineVerifier/test_copy.mir index e234f45287ef..64c2761e7ea7 100644 --- a/llvm/test/MachineVerifier/test_copy.mir +++ b/llvm/test/MachineVerifier/test_copy.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | ; ModuleID = 'test.ll' diff --git a/llvm/test/MachineVerifier/test_copy_mismatch_types.mir b/llvm/test/MachineVerifier/test_copy_mismatch_types.mir index 905977938d51..3b7e54e0c1c4 100644 --- a/llvm/test/MachineVerifier/test_copy_mismatch_types.mir +++ b/llvm/test/MachineVerifier/test_copy_mismatch_types.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | ; ModuleID = 'test.ll' diff --git a/llvm/test/MachineVerifier/test_g_add.mir b/llvm/test/MachineVerifier/test_g_add.mir index 9cd990bb8cc1..331f4bf351ab 100644 --- a/llvm/test/MachineVerifier/test_g_add.mir +++ b/llvm/test/MachineVerifier/test_g_add.mir @@ -1,4 +1,4 @@ -#RUN: not llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_addrspacecast.mir b/llvm/test/MachineVerifier/test_g_addrspacecast.mir index 88b411378792..fb71057c585c 100644 --- a/llvm/test/MachineVerifier/test_g_addrspacecast.mir +++ b/llvm/test/MachineVerifier/test_g_addrspacecast.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_bitcast.mir b/llvm/test/MachineVerifier/test_g_bitcast.mir index 3446d5fc86eb..a399c859404f 100644 --- a/llvm/test/MachineVerifier/test_g_bitcast.mir +++ b/llvm/test/MachineVerifier/test_g_bitcast.mir @@ -1,4 +1,4 @@ -#RUN: not llc -mtriple=amdgcn-amd-amdhsa -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, amdgpu-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_brjt.mir b/llvm/test/MachineVerifier/test_g_brjt.mir index e05dd5fadbc2..7a8417efab85 100644 --- a/llvm/test/MachineVerifier/test_g_brjt.mir +++ b/llvm/test/MachineVerifier/test_g_brjt.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_build_vector.mir b/llvm/test/MachineVerifier/test_g_build_vector.mir index 77b5beb2fdd8..0c013dfa4778 100644 --- a/llvm/test/MachineVerifier/test_g_build_vector.mir +++ b/llvm/test/MachineVerifier/test_g_build_vector.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- name: g_build_vector diff --git a/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir b/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir index d73e37e1e6e3..296713fce9fe 100644 --- a/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir +++ b/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/MachineVerifier/test_g_concat_vectors.mir b/llvm/test/MachineVerifier/test_g_concat_vectors.mir index 640c4a4ceedb..53e2eca00808 100644 --- a/llvm/test/MachineVerifier/test_g_concat_vectors.mir +++ b/llvm/test/MachineVerifier/test_g_concat_vectors.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/MachineVerifier/test_g_constant.mir b/llvm/test/MachineVerifier/test_g_constant.mir index fa5daff870b0..cfdcae929ce1 100644 --- a/llvm/test/MachineVerifier/test_g_constant.mir +++ b/llvm/test/MachineVerifier/test_g_constant.mir @@ -1,4 +1,4 @@ -#RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir b/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir index e798f23e789c..51c74e5992d2 100644 --- a/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir +++ b/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_extract.mir b/llvm/test/MachineVerifier/test_g_extract.mir index 62064ae80217..2f326cb56ccf 100644 --- a/llvm/test/MachineVerifier/test_g_extract.mir +++ b/llvm/test/MachineVerifier/test_g_extract.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_fcmp.mir b/llvm/test/MachineVerifier/test_g_fcmp.mir index c7416d47dcd4..15373f8ff387 100644 --- a/llvm/test/MachineVerifier/test_g_fcmp.mir +++ b/llvm/test/MachineVerifier/test_g_fcmp.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_fconstant.mir b/llvm/test/MachineVerifier/test_g_fconstant.mir index d917d9c846ff..249a74a50157 100644 --- a/llvm/test/MachineVerifier/test_g_fconstant.mir +++ b/llvm/test/MachineVerifier/test_g_fconstant.mir @@ -1,4 +1,4 @@ -#RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_icmp.mir b/llvm/test/MachineVerifier/test_g_icmp.mir index 9582a1795123..74448e736fd6 100644 --- a/llvm/test/MachineVerifier/test_g_icmp.mir +++ b/llvm/test/MachineVerifier/test_g_icmp.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_insert.mir b/llvm/test/MachineVerifier/test_g_insert.mir index 0785370ec174..d12a2206c6c4 100644 --- a/llvm/test/MachineVerifier/test_g_insert.mir +++ b/llvm/test/MachineVerifier/test_g_insert.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_intrinsic.mir b/llvm/test/MachineVerifier/test_g_intrinsic.mir index 157edc09b801..aac733a3bdf6 100644 --- a/llvm/test/MachineVerifier/test_g_intrinsic.mir +++ b/llvm/test/MachineVerifier/test_g_intrinsic.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=amdgcn -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=amdgcn -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: amdgpu-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir b/llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir index 8e8627d2e723..75e4e623c3e1 100644 --- a/llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir +++ b/llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=amdgcn -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=amdgcn -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: amdgpu-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_inttoptr.mir b/llvm/test/MachineVerifier/test_g_inttoptr.mir index 2769c66c8cc7..d0d356a1d7b6 100644 --- a/llvm/test/MachineVerifier/test_g_inttoptr.mir +++ b/llvm/test/MachineVerifier/test_g_inttoptr.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_jump_table.mir b/llvm/test/MachineVerifier/test_g_jump_table.mir index 406edcbea5c2..3c837c295140 100644 --- a/llvm/test/MachineVerifier/test_g_jump_table.mir +++ b/llvm/test/MachineVerifier/test_g_jump_table.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_load.mir b/llvm/test/MachineVerifier/test_g_load.mir index 18a7718b71b7..ac28b513c1d8 100644 --- a/llvm/test/MachineVerifier/test_g_load.mir +++ b/llvm/test/MachineVerifier/test_g_load.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_merge_values.mir b/llvm/test/MachineVerifier/test_g_merge_values.mir index 4829e8f13173..21b4079b5e1f 100644 --- a/llvm/test/MachineVerifier/test_g_merge_values.mir +++ b/llvm/test/MachineVerifier/test_g_merge_values.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- name: g_merge_values diff --git a/llvm/test/MachineVerifier/test_g_phi.mir b/llvm/test/MachineVerifier/test_g_phi.mir index c108ea613543..11e18e2220ad 100644 --- a/llvm/test/MachineVerifier/test_g_phi.mir +++ b/llvm/test/MachineVerifier/test_g_phi.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | ; ModuleID = 'test.ll' diff --git a/llvm/test/MachineVerifier/test_g_ptr_add.mir b/llvm/test/MachineVerifier/test_g_ptr_add.mir index fd60a08e99c7..9a918d2fc7f9 100644 --- a/llvm/test/MachineVerifier/test_g_ptr_add.mir +++ b/llvm/test/MachineVerifier/test_g_ptr_add.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_ptrtoint.mir b/llvm/test/MachineVerifier/test_g_ptrtoint.mir index c9a50bbded71..f289a3d1dbed 100644 --- a/llvm/test/MachineVerifier/test_g_ptrtoint.mir +++ b/llvm/test/MachineVerifier/test_g_ptrtoint.mir @@ -1,4 +1,4 @@ -#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_select.mir b/llvm/test/MachineVerifier/test_g_select.mir index d40b276c9ba2..ca0a94d6bc97 100644 --- a/llvm/test/MachineVerifier/test_g_select.mir +++ b/llvm/test/MachineVerifier/test_g_select.mir @@ -1,4 +1,4 @@ -#RUN: not llc -march=aarch64 -run-pass=none -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +#RUN: not --crash llc -march=aarch64 -run-pass=none -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_sext_inreg.mir b/llvm/test/MachineVerifier/test_g_sext_inreg.mir index 32573cc9e0ce..120f9995d87d 100644 --- a/llvm/test/MachineVerifier/test_g_sext_inreg.mir +++ b/llvm/test/MachineVerifier/test_g_sext_inreg.mir @@ -1,4 +1,4 @@ -# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | diff --git a/llvm/test/MachineVerifier/test_g_sextload.mir b/llvm/test/MachineVerifier/test_g_sextload.mir index ee822ea1104b..f12fe1cb6bf0 100644 --- a/llvm/test/MachineVerifier/test_g_sextload.mir +++ b/llvm/test/MachineVerifier/test_g_sextload.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir index 7e07fa9d4fca..740293e79247 100644 --- a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir +++ b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- name: g_shuffle_vector diff --git a/llvm/test/MachineVerifier/test_g_store.mir b/llvm/test/MachineVerifier/test_g_store.mir index bb82042d6691..183935f052df 100644 --- a/llvm/test/MachineVerifier/test_g_store.mir +++ b/llvm/test/MachineVerifier/test_g_store.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_trunc.mir b/llvm/test/MachineVerifier/test_g_trunc.mir index fd97b09af15c..9dbeab2c6039 100644 --- a/llvm/test/MachineVerifier/test_g_trunc.mir +++ b/llvm/test/MachineVerifier/test_g_trunc.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_zextload.mir b/llvm/test/MachineVerifier/test_g_zextload.mir index bcb96e3875f9..3b65bf9c1726 100644 --- a/llvm/test/MachineVerifier/test_g_zextload.mir +++ b/llvm/test/MachineVerifier/test_g_zextload.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_memccpy_intrinsics.mir b/llvm/test/MachineVerifier/test_memccpy_intrinsics.mir index acdd9dd2b28c..03ba9e0d06f2 100644 --- a/llvm/test/MachineVerifier/test_memccpy_intrinsics.mir +++ b/llvm/test/MachineVerifier/test_memccpy_intrinsics.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - -march=aarch64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not --crash llc -o - -march=aarch64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir b/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir index fa69b40fddf1..0253e6ab952c 100644 --- a/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir +++ b/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir @@ -1,4 +1,4 @@ -# RUN: not llc -run-pass=machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not --crash llc -run-pass=machineverifier %s -o - 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- | diff --git a/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir b/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir index 8390d9bf3ce1..38cf1859e6d1 100644 --- a/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir +++ b/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s +# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s # REQUIRES: x86-registered-target # CHECK: Bad machine code: Generic extend/truncate can not operate on pointers diff --git a/llvm/test/MachineVerifier/verifier-generic-types-1.mir b/llvm/test/MachineVerifier/verifier-generic-types-1.mir index bc2d2580ed17..884209f17362 100644 --- a/llvm/test/MachineVerifier/verifier-generic-types-1.mir +++ b/llvm/test/MachineVerifier/verifier-generic-types-1.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s +# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s # REQUIRES: x86-registered-target # CHECK-NOT: Type mismatch diff --git a/llvm/test/MachineVerifier/verifier-generic-types-2.mir b/llvm/test/MachineVerifier/verifier-generic-types-2.mir index 27a14c222c6e..5558a2b654ac 100644 --- a/llvm/test/MachineVerifier/verifier-generic-types-2.mir +++ b/llvm/test/MachineVerifier/verifier-generic-types-2.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s +# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s # REQUIRES: x86-registered-target # CHECK: Bad machine code: Generic instruction is missing a virtual register type diff --git a/llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir b/llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir index fb4777898edd..a723ee205ef0 100644 --- a/llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir +++ b/llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s # REQUIRES: amdgpu-registered-target # When the verifier was detecting the invalid liveness for vcc, it would assert when trying to iterate the subregisters of the implicit virtual register use. diff --git a/llvm/test/MachineVerifier/verifier-phi-fail0.mir b/llvm/test/MachineVerifier/verifier-phi-fail0.mir index 80a50b50937c..aa488f064cc6 100644 --- a/llvm/test/MachineVerifier/verifier-phi-fail0.mir +++ b/llvm/test/MachineVerifier/verifier-phi-fail0.mir @@ -1,4 +1,4 @@ -# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s +# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s # REQUIRES: x86-registered-target --- diff --git a/llvm/test/MachineVerifier/verifier-pseudo-terminators.mir b/llvm/test/MachineVerifier/verifier-pseudo-terminators.mir index 831ca83baa28..6e9ec9c0887f 100644 --- a/llvm/test/MachineVerifier/verifier-pseudo-terminators.mir +++ b/llvm/test/MachineVerifier/verifier-pseudo-terminators.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -run-pass=verify -o - %s 2>&1 | FileCheck %s +# RUN: not --crash llc -march=amdgcn -run-pass=verify -o - %s 2>&1 | FileCheck %s # REQUIRES: amdgpu-registered-target # Make sure that mismatched successors are caught when a _term diff --git a/llvm/test/MachineVerifier/verify-regbankselected.mir b/llvm/test/MachineVerifier/verify-regbankselected.mir index 027fc6664573..ed022ed5eaf9 100644 --- a/llvm/test/MachineVerifier/verify-regbankselected.mir +++ b/llvm/test/MachineVerifier/verify-regbankselected.mir @@ -1,4 +1,4 @@ -# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- | diff --git a/llvm/test/MachineVerifier/verify-regops.mir b/llvm/test/MachineVerifier/verify-regops.mir index 9219586ffc03..ec17c3d0558b 100644 --- a/llvm/test/MachineVerifier/verify-regops.mir +++ b/llvm/test/MachineVerifier/verify-regops.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86 -o - %s -run-pass=none -verify-machineinstrs \ +# RUN: not --crash llc -march=x86 -o - %s -run-pass=none -verify-machineinstrs \ # RUN: 2>&1 | FileCheck %s # REQUIRES: x86-registered-target # diff --git a/llvm/test/MachineVerifier/verify-selected.mir b/llvm/test/MachineVerifier/verify-selected.mir index a38f67ca6e67..b14f977caf14 100644 --- a/llvm/test/MachineVerifier/verify-selected.mir +++ b/llvm/test/MachineVerifier/verify-selected.mir @@ -1,4 +1,4 @@ -# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- | diff --git a/llvm/test/Object/coff-invalid.test b/llvm/test/Object/coff-invalid.test index 3ab3f41b15fe..da5d687c6e20 100644 --- a/llvm/test/Object/coff-invalid.test +++ b/llvm/test/Object/coff-invalid.test @@ -7,7 +7,7 @@ SECTIONS-NEXT: Name: .text (2E 74 65 78 74 00 00 00) SECTIONS-NEXT: VirtualSize: 0x0 SECTIONS-NEXT: VirtualAddress: 0x1000000 -RUN: not llvm-readobj -r %p/Inputs/invalid-bad-section-address.coff 2>&1 | \ +RUN: not --crash llvm-readobj -r %p/Inputs/invalid-bad-section-address.coff 2>&1 | \ RUN: FileCheck %s CHECK: Sections with relocations should have an address of 0 diff --git a/llvm/test/Object/elf-invalid-phdr.test b/llvm/test/Object/elf-invalid-phdr.test index b779171dfbb3..68a26788e118 100644 --- a/llvm/test/Object/elf-invalid-phdr.test +++ b/llvm/test/Object/elf-invalid-phdr.test @@ -20,7 +20,7 @@ # - Section: .text # # Then editing the e_phoff in with a hexeditor to set it to 0xffffff -RUN: not llvm-objdump -private-headers %p/Inputs/invalid-phdr.elf 2>&1 \ +RUN: not --crash llvm-objdump -private-headers %p/Inputs/invalid-phdr.elf 2>&1 \ RUN: | FileCheck %s -CHECK: LLVM ERROR: program headers are longer than binary of size 4162: e_phoff = 0xffffff, e_phnum = 1, e_phentsize = 56 \ No newline at end of file +CHECK: LLVM ERROR: program headers are longer than binary of size 4162: e_phoff = 0xffffff, e_phnum = 1, e_phentsize = 56 diff --git a/llvm/test/Object/invalid.test b/llvm/test/Object/invalid.test index 4d19b66238cc..442d38d46d06 100644 --- a/llvm/test/Object/invalid.test +++ b/llvm/test/Object/invalid.test @@ -47,7 +47,7 @@ Sections: ## when instead of expected SHT_RELA section it locates a section of a different type. # RUN: yaml2obj %s --docnum=3 -o %t3 -# RUN: not llvm-dwarfdump -debug-line %t3 2>&1 | FileCheck --check-prefix=RELA %s +# RUN: not --crash llvm-dwarfdump -debug-line %t3 2>&1 | FileCheck --check-prefix=RELA %s # RELA: LLVM ERROR: Section is not SHT_RELA diff --git a/llvm/test/Object/wasm-invalid-file.yaml b/llvm/test/Object/wasm-invalid-file.yaml index 5ea192d66177..9870b47ee85c 100644 --- a/llvm/test/Object/wasm-invalid-file.yaml +++ b/llvm/test/Object/wasm-invalid-file.yaml @@ -1,7 +1,7 @@ # RUN: yaml2obj %s -o %t.wasm # RUN: echo -e -n "\x01" >> %t.wasm # Append a new section but truncate the encoding of the section size -# RUN: not llvm-objdump -h %t.wasm 2>&1 | FileCheck %s -check-prefix=CHECK-LEB-DECODE +# RUN: not --crash llvm-objdump -h %t.wasm 2>&1 | FileCheck %s -check-prefix=CHECK-LEB-DECODE !WASM FileHeader: diff --git a/llvm/test/Object/wasm-string-outside-section.test b/llvm/test/Object/wasm-string-outside-section.test index 5f618228dc96..3fa6217bae8e 100644 --- a/llvm/test/Object/wasm-string-outside-section.test +++ b/llvm/test/Object/wasm-string-outside-section.test @@ -1,3 +1,3 @@ -RUN: not llvm-objdump -s %p/Inputs/WASM/string-outside-section.wasm 2>&1 | FileCheck %s +RUN: not --crash llvm-objdump -s %p/Inputs/WASM/string-outside-section.wasm 2>&1 | FileCheck %s CHECK: LLVM ERROR: EOF while reading string diff --git a/llvm/test/Other/close-stderr.ll b/llvm/test/Other/close-stderr.ll deleted file mode 100644 index b310bc2c0424..000000000000 --- a/llvm/test/Other/close-stderr.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: sh -c 'opt --reject-this-option 2>&-; echo $?; opt -o /dev/null /dev/null 2>&-; echo $?;' \ -; RUN: | FileCheck %s - -; CHECK: {{^1$}} -; On valgrind, we got 127 here. -; XFAIL: valgrind - -; CHECK: {{^0$}} -; XFAIL: vg_leak -; REQUIRES: shell - -; Test that the error handling when writing to stderr fails exits the -; program cleanly rather than aborting. diff --git a/llvm/test/Other/optimization-remarks-inline.ll b/llvm/test/Other/optimization-remarks-inline.ll index bcd90bc28d32..bc2200545bb0 100644 --- a/llvm/test/Other/optimization-remarks-inline.ll +++ b/llvm/test/Other/optimization-remarks-inline.ll @@ -10,7 +10,7 @@ ; RUN: opt < %s -inline -pass-remarks='inl' -pass-remarks='vector' -S 2>&1 | FileCheck --check-prefix=REMARKS %s ; RUN: opt < %s -inline -S 2>&1 | FileCheck --check-prefix=REMARKS %s -; RUN: not opt < %s -pass-remarks='(' 2>&1 | FileCheck --check-prefix=BAD-REGEXP %s +; RUN: not --crash opt < %s -pass-remarks='(' 2>&1 | FileCheck --check-prefix=BAD-REGEXP %s define i32 @foo(i32 %x, i32 %y) #0 { entry: diff --git a/llvm/test/TableGen/HwModeSelect.td b/llvm/test/TableGen/HwModeSelect.td index 6480268f3b3d..0c63e140f390 100644 --- a/llvm/test/TableGen/HwModeSelect.td +++ b/llvm/test/TableGen/HwModeSelect.td @@ -1,4 +1,4 @@ -// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s +// RUN: not --crash llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s // The HwModeSelect class is intended to serve as a base class for other // classes that are then used to select a value based on the HW mode. diff --git a/llvm/test/Transforms/BlockExtractor/invalid-block.ll b/llvm/test/Transforms/BlockExtractor/invalid-block.ll index f444764e991d..4b284ddbcdba 100644 --- a/llvm/test/Transforms/BlockExtractor/invalid-block.ll +++ b/llvm/test/Transforms/BlockExtractor/invalid-block.ll @@ -1,5 +1,5 @@ ; RUN: echo 'bar invalidbb' > %t -; RUN: not opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s +; RUN: not --crash opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s ; CHECK: Invalid block define void @bar() { diff --git a/llvm/test/Transforms/BlockExtractor/invalid-function.ll b/llvm/test/Transforms/BlockExtractor/invalid-function.ll index 4044815893e5..9af46ef2dcf9 100644 --- a/llvm/test/Transforms/BlockExtractor/invalid-function.ll +++ b/llvm/test/Transforms/BlockExtractor/invalid-function.ll @@ -1,5 +1,5 @@ ; RUN: echo 'foo bb' > %t -; RUN: not opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s +; RUN: not --crash opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s ; CHECK: Invalid function define void @bar() { diff --git a/llvm/test/Transforms/BlockExtractor/invalid-line.ll b/llvm/test/Transforms/BlockExtractor/invalid-line.ll index 7e409d35916f..f0a4231660d7 100644 --- a/llvm/test/Transforms/BlockExtractor/invalid-line.ll +++ b/llvm/test/Transforms/BlockExtractor/invalid-line.ll @@ -1,5 +1,5 @@ ; RUN: echo 'foo' > %t -; RUN: not opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s +; RUN: not --crash opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s ; CHECK: Invalid line define void @bar() { diff --git a/llvm/test/Transforms/FunctionImport/not-prevailing.ll b/llvm/test/Transforms/FunctionImport/not-prevailing.ll index 0e0dd53950ae..043b3a89adc2 100644 --- a/llvm/test/Transforms/FunctionImport/not-prevailing.ll +++ b/llvm/test/Transforms/FunctionImport/not-prevailing.ll @@ -1,6 +1,6 @@ ; RUN: opt -module-summary %s -o %t1.bc ; RUN: opt -module-summary -o %t2.bc %S/Inputs/not-prevailing.ll -; RUN: not llvm-lto2 run -o %t3.bc %t1.bc %t2.bc -r %t1.bc,bar,px \ +; RUN: not --crash llvm-lto2 run -o %t3.bc %t1.bc %t2.bc -r %t1.bc,bar,px \ ; RUN: -r %t1.bc,foo,x -r %t2.bc,foo,x -save-temps 2>&1 | FileCheck %s ; CHECK: Interposable and available_externally/linkonce_odr/weak_odr symbol diff --git a/llvm/test/Transforms/GCOVProfiling/version.ll b/llvm/test/Transforms/GCOVProfiling/version.ll index 239c62f4a6bb..c72b64260ffa 100644 --- a/llvm/test/Transforms/GCOVProfiling/version.ll +++ b/llvm/test/Transforms/GCOVProfiling/version.ll @@ -4,7 +4,7 @@ ; RUN: opt -insert-gcov-profiling -disable-output < %t/2 ; RUN: head -c8 %t/version.gcno | grep '^oncg.204' ; RUN: rm %t/version.gcno -; RUN: not opt -insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t/2 +; RUN: not --crash opt -insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t/2 ; RUN: opt -insert-gcov-profiling -default-gcov-version=407* -disable-output < %t/2 ; RUN: head -c8 %t/version.gcno | grep '^oncg.704' ; RUN: rm %t/version.gcno @@ -12,7 +12,7 @@ ; RUN: opt -passes=insert-gcov-profiling -disable-output < %t/2 ; RUN: head -c8 %t/version.gcno | grep '^oncg.204' ; RUN: rm %t/version.gcno -; RUN: not opt -passes=insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t/2 +; RUN: not --crash opt -passes=insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t/2 ; RUN: opt -passes=insert-gcov-profiling -default-gcov-version=407* -disable-output < %t/2 ; RUN: head -c8 %t/version.gcno | grep '^oncg.704' ; RUN: rm %t/version.gcno diff --git a/llvm/test/Transforms/InstCombine/limit-max-iterations.ll b/llvm/test/Transforms/InstCombine/limit-max-iterations.ll index a2ef4ebcbb50..af027998edac 100644 --- a/llvm/test/Transforms/InstCombine/limit-max-iterations.ll +++ b/llvm/test/Transforms/InstCombine/limit-max-iterations.ll @@ -2,7 +2,7 @@ ; RUN: opt < %s -instcombine --instcombine-max-iterations=0 -S | FileCheck %s --check-prefix=ZERO ; RUN: opt < %s -instcombine --instcombine-max-iterations=1 -S | FileCheck %s --check-prefix=ONE ; RUN: opt < %s -instcombine -S | FileCheck %s --check-prefix=FIXPOINT -; RUN: not opt < %s -instcombine -S --instcombine-infinite-loop-threshold=3 2>&1 | FileCheck %s --check-prefix=LOOP +; RUN: not --crash opt < %s -instcombine -S --instcombine-infinite-loop-threshold=3 2>&1 | FileCheck %s --check-prefix=LOOP ; Based on xor-of-icmps-with-extra-uses.ll. This requires multiple iterations of ; InstCombine to reach a fixpoint. diff --git a/llvm/test/tools/llvm-lto2/X86/pipeline.ll b/llvm/test/tools/llvm-lto2/X86/pipeline.ll index f9759b590857..abc2f20a0725 100644 --- a/llvm/test/tools/llvm-lto2/X86/pipeline.ll +++ b/llvm/test/tools/llvm-lto2/X86/pipeline.ll @@ -28,13 +28,13 @@ define void @patatino() { ; CUSTOM-NEXT: } ; Check that invalid pipelines are caught as errors. -; RUN: not llvm-lto2 run %t1.bc -o %t.o \ +; RUN: not --crash llvm-lto2 run %t1.bc -o %t.o \ ; RUN: -r %t1.bc,patatino,px -opt-pipeline foogoo 2>&1 | \ ; RUN: FileCheck %s --check-prefix=ERR ; ERR: LLVM ERROR: unable to parse pass pipeline description 'foogoo': unknown pass name 'foogoo' -; RUN: not llvm-lto2 run %t1.bc -o %t.o \ +; RUN: not --crash llvm-lto2 run %t1.bc -o %t.o \ ; RUN: -r %t1.bc,patatino,px -aa-pipeline patatino \ ; RUN: -opt-pipeline loweratomic 2>&1 | \ ; RUN: FileCheck %s --check-prefix=AAERR diff --git a/llvm/test/tools/llvm-readobj/COFF/arm64-many-epilogs.s b/llvm/test/tools/llvm-readobj/COFF/arm64-many-epilogs.s index a1b53980936d..50b5fab93513 100644 --- a/llvm/test/tools/llvm-readobj/COFF/arm64-many-epilogs.s +++ b/llvm/test/tools/llvm-readobj/COFF/arm64-many-epilogs.s @@ -1,6 +1,6 @@ // REQUIRES: aarch64-registered-target // RUN: llvm-mc -filetype=obj -triple aarch64-windows %s -o - \ -// RUN: | not llvm-readobj --unwind - | FileCheck %s +// RUN: | not --crash llvm-readobj --unwind - 2>&1 | FileCheck %s // Older versions of LLVM had a bug where we would accidentally // truncate the number of epilogue scopes to a uint8_t; make diff --git a/llvm/test/tools/llvm-readobj/COFF/arm64-win-error2.s b/llvm/test/tools/llvm-readobj/COFF/arm64-win-error2.s index 74a61dd02019..5256de05cb24 100644 --- a/llvm/test/tools/llvm-readobj/COFF/arm64-win-error2.s +++ b/llvm/test/tools/llvm-readobj/COFF/arm64-win-error2.s @@ -6,7 +6,7 @@ // REQUIRES: aarch64-registered-target // RUN: llvm-mc -filetype=obj -triple aarch64-windows %s -o - \ -// RUN: | not llvm-readobj --unwind - 2>&1 | FileCheck %s +// RUN: | not --crash llvm-readobj --unwind - 2>&1 | FileCheck %s // CHECK: LLVM ERROR: Malformed unwind data -- GitLab From 62c6f98899c8e537f5c5c5bca3daaa03a3d6646c Mon Sep 17 00:00:00 2001 From: Yuanfang Chen Date: Tue, 11 Feb 2020 18:34:34 -0800 Subject: [PATCH 106/142] Fix two more test cases for https://reviews.llvm.org/D74456. --- llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll | 2 +- llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll b/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll index c4bdfb6a1038..3eb6d0d90cf3 100644 --- a/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll +++ b/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx -o /dev/null 2> %t +; RUN: not --crash llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx -o /dev/null 2> %t ; RUN: FileCheck %s --input-file %t define <4 x float> @testxmm_1(<4 x float> %_xmm0, i32 %_l) { diff --git a/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll b/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll index 7278089348e2..999117e0df4b 100644 --- a/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll +++ b/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll @@ -1,4 +1,4 @@ -; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx512vl -o /dev/null 2> %t +; RUN: not --crash llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx512vl -o /dev/null 2> %t ; RUN: FileCheck %s --input-file %t define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) { -- GitLab From cd5b308b828ef42327c39f24a3e30c5407879c42 Mon Sep 17 00:00:00 2001 From: Yuanfang Chen Date: Tue, 11 Feb 2020 19:18:23 -0800 Subject: [PATCH 107/142] Temporarily XFAIL these two tests. llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll --- llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll | 4 +++- .../CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll b/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll index 3eb6d0d90cf3..c8074dfa295e 100644 --- a/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll +++ b/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll @@ -1,5 +1,7 @@ -; RUN: not --crash llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx -o /dev/null 2> %t +; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx -o /dev/null 2> %t ; RUN: FileCheck %s --input-file %t +; XFAIL: * +; Temporarily disable this since the llc return code depents on bots. define <4 x float> @testxmm_1(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available diff --git a/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll b/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll index 999117e0df4b..bd8022f8e515 100644 --- a/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll +++ b/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll @@ -1,5 +1,7 @@ -; RUN: not --crash llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx512vl -o /dev/null 2> %t +; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx512vl -o /dev/null 2> %t ; RUN: FileCheck %s --input-file %t +; XFAIL: * +; Temporarily disable this since the llc return code depents on bots. define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available -- GitLab From a5153dbc368e1a484e179fafce7a260410d20569 Mon Sep 17 00:00:00 2001 From: Johannes Doerfert Date: Tue, 11 Feb 2020 22:06:32 -0600 Subject: [PATCH 108/142] [OpenMP][Offloading] Added support for multiple streams so that multiple kernels can be executed concurrently Reviewed By: jdoerfert Differential Revision: https://reviews.llvm.org/D74145 --- openmp/libomptarget/plugins/cuda/src/rtl.cpp | 108 ++++++++++++++++-- .../test/offloading/parallel_offloading_map.c | 41 +++++++ 2 files changed, 141 insertions(+), 8 deletions(-) create mode 100644 openmp/libomptarget/test/offloading/parallel_offloading_map.c diff --git a/openmp/libomptarget/plugins/cuda/src/rtl.cpp b/openmp/libomptarget/plugins/cuda/src/rtl.cpp index 49acb6cacbfe..54248daa7f19 100644 --- a/openmp/libomptarget/plugins/cuda/src/rtl.cpp +++ b/openmp/libomptarget/plugins/cuda/src/rtl.cpp @@ -10,10 +10,12 @@ // //===----------------------------------------------------------------------===// +#include #include #include #include #include +#include #include #include @@ -90,11 +92,13 @@ std::list KernelsList; /// Class containing all the device information. class RTLDeviceInfoTy { std::vector> FuncGblEntries; + std::vector> NextStreamId; public: int NumberOfDevices; std::vector Modules; std::vector Contexts; + std::vector> Streams; // Device properties std::vector ThreadsPerBlock; @@ -108,6 +112,7 @@ public: // OpenMP Environment properties int EnvNumTeams; int EnvTeamLimit; + int EnvNumStreams; // OpenMP Requires Flags int64_t RequiresFlags; @@ -173,6 +178,15 @@ public: E.Table.EntriesBegin = E.Table.EntriesEnd = 0; } + // Get the next stream on a given device in a round robin manner + CUstream &getNextStream(const int DeviceId) { + assert(DeviceId >= 0 && + static_cast(DeviceId) < NextStreamId.size() && + "Unexpected device id!"); + const unsigned int Id = NextStreamId[DeviceId]->fetch_add(1); + return Streams[DeviceId][Id % EnvNumStreams]; + } + RTLDeviceInfoTy() { #ifdef OMPTARGET_DEBUG if (char *envStr = getenv("LIBOMPTARGET_DEBUG")) { @@ -205,6 +219,8 @@ public: FuncGblEntries.resize(NumberOfDevices); Contexts.resize(NumberOfDevices); + Streams.resize(NumberOfDevices); + NextStreamId.resize(NumberOfDevices); ThreadsPerBlock.resize(NumberOfDevices); BlocksPerGrid.resize(NumberOfDevices); WarpSize.resize(NumberOfDevices); @@ -229,6 +245,23 @@ public: EnvNumTeams = -1; } + // By default let's create 256 streams per device + EnvNumStreams = 256; + envStr = getenv("LIBOMPTARGET_NUM_STREAMS"); + if (envStr) { + EnvNumStreams = std::stoi(envStr); + } + + // Initialize streams for each device + for (std::vector &S : Streams) { + S.resize(EnvNumStreams); + } + + // Initialize the next stream id + for (std::unique_ptr &Ptr : NextStreamId) { + Ptr = std::make_unique(0); + } + // Default state. RequiresFlags = OMP_REQ_UNDEFINED; } @@ -244,6 +277,24 @@ public: } } + // Destroy streams before contexts + for (int I = 0; I < NumberOfDevices; ++I) { + CUresult err = cuCtxSetCurrent(Contexts[I]); + if (err != CUDA_SUCCESS) { + DP("Error when setting current CUDA context\n"); + CUDA_ERR_STRING(err); + } + + for (auto &S : Streams[I]) + if (S) { + err = cuStreamDestroy(S); + if (err != CUDA_SUCCESS) { + DP("Error when destroying CUDA stream\n"); + CUDA_ERR_STRING(err); + } + } + } + // Destroy contexts for (auto &ctx : Contexts) if (ctx) { @@ -294,6 +345,20 @@ int32_t __tgt_rtl_init_device(int32_t device_id) { return OFFLOAD_FAIL; } + err = cuCtxSetCurrent(DeviceInfo.Contexts[device_id]); + if (err != CUDA_SUCCESS) { + DP("Error when setting current CUDA context\n"); + CUDA_ERR_STRING(err); + } + + for (CUstream &Stream : DeviceInfo.Streams[device_id]) { + err = cuStreamCreate(&Stream, CU_STREAM_NON_BLOCKING); + if (err != CUDA_SUCCESS) { + DP("Error when creating CUDA stream\n"); + CUDA_ERR_STRING(err); + } + } + // Query attributes to determine number of threads/block and blocks/grid. int maxGridDimX; err = cuDeviceGetAttribute(&maxGridDimX, CU_DEVICE_ATTRIBUTE_MAX_GRID_DIM_X, @@ -607,14 +672,26 @@ int32_t __tgt_rtl_data_submit(int32_t device_id, void *tgt_ptr, void *hst_ptr, return OFFLOAD_FAIL; } - err = cuMemcpyHtoD((CUdeviceptr)tgt_ptr, hst_ptr, size); + CUstream &Stream = DeviceInfo.getNextStream(device_id); + + err = cuMemcpyHtoDAsync((CUdeviceptr)tgt_ptr, hst_ptr, size, Stream); if (err != CUDA_SUCCESS) { DP("Error when copying data from host to device. Pointers: host = " DPxMOD - ", device = " DPxMOD ", size = %" PRId64 "\n", DPxPTR(hst_ptr), - DPxPTR(tgt_ptr), size); + ", device = " DPxMOD ", size = %" PRId64 "\n", + DPxPTR(hst_ptr), DPxPTR(tgt_ptr), size); + CUDA_ERR_STRING(err); + return OFFLOAD_FAIL; + } + + err = cuStreamSynchronize(Stream); + if (err != CUDA_SUCCESS) { + DP("Error when synchronizing async data transfer from host to device. " + "Pointers: host = " DPxMOD ", device = " DPxMOD ", size = %" PRId64 "\n", + DPxPTR(hst_ptr), DPxPTR(tgt_ptr), size); CUDA_ERR_STRING(err); return OFFLOAD_FAIL; } + return OFFLOAD_SUCCESS; } @@ -628,14 +705,26 @@ int32_t __tgt_rtl_data_retrieve(int32_t device_id, void *hst_ptr, void *tgt_ptr, return OFFLOAD_FAIL; } - err = cuMemcpyDtoH(hst_ptr, (CUdeviceptr)tgt_ptr, size); + CUstream &Stream = DeviceInfo.getNextStream(device_id); + + err = cuMemcpyDtoHAsync(hst_ptr, (CUdeviceptr)tgt_ptr, size, Stream); if (err != CUDA_SUCCESS) { DP("Error when copying data from device to host. Pointers: host = " DPxMOD - ", device = " DPxMOD ", size = %" PRId64 "\n", DPxPTR(hst_ptr), - DPxPTR(tgt_ptr), size); + ", device = " DPxMOD ", size = %" PRId64 "\n", + DPxPTR(hst_ptr), DPxPTR(tgt_ptr), size); + CUDA_ERR_STRING(err); + return OFFLOAD_FAIL; + } + + err = cuStreamSynchronize(Stream); + if (err != CUDA_SUCCESS) { + DP("Error when synchronizing async data transfer from device to host. " + "Pointers: host = " DPxMOD ", device = " DPxMOD ", size = %" PRId64 "\n", + DPxPTR(hst_ptr), DPxPTR(tgt_ptr), size); CUDA_ERR_STRING(err); return OFFLOAD_FAIL; } + return OFFLOAD_SUCCESS; } @@ -755,8 +844,11 @@ int32_t __tgt_rtl_run_target_team_region(int32_t device_id, void *tgt_entry_ptr, DP("Launch kernel with %d blocks and %d threads\n", cudaBlocksPerGrid, cudaThreadsPerBlock); + CUstream &Stream = DeviceInfo.getNextStream(device_id); + err = cuLaunchKernel(KernelInfo->Func, cudaBlocksPerGrid, 1, 1, - cudaThreadsPerBlock, 1, 1, 0 /*bytes of shared memory*/, 0, &args[0], 0); + cudaThreadsPerBlock, 1, 1, 0 /*bytes of shared memory*/, + Stream, &args[0], 0); if (err != CUDA_SUCCESS) { DP("Device kernel launch failed!\n"); CUDA_ERR_STRING(err); @@ -766,7 +858,7 @@ int32_t __tgt_rtl_run_target_team_region(int32_t device_id, void *tgt_entry_ptr, DP("Launch of entry point at " DPxMOD " successful!\n", DPxPTR(tgt_entry_ptr)); - CUresult sync_err = cuCtxSynchronize(); + CUresult sync_err = cuStreamSynchronize(Stream); if (sync_err != CUDA_SUCCESS) { DP("Kernel execution error at " DPxMOD "!\n", DPxPTR(tgt_entry_ptr)); CUDA_ERR_STRING(sync_err); diff --git a/openmp/libomptarget/test/offloading/parallel_offloading_map.c b/openmp/libomptarget/test/offloading/parallel_offloading_map.c new file mode 100644 index 000000000000..bcdc6f96f4d0 --- /dev/null +++ b/openmp/libomptarget/test/offloading/parallel_offloading_map.c @@ -0,0 +1,41 @@ +// RUN: %libomptarget-compilexx-run-and-check-aarch64-unknown-linux-gnu +// RUN: %libomptarget-compilexx-run-and-check-powerpc64-ibm-linux-gnu +// RUN: %libomptarget-compilexx-run-and-check-powerpc64le-ibm-linux-gnu +// RUN: %libomptarget-compilexx-run-and-check-x86_64-pc-linux-gnu +#include +#include + +int main(int argc, char *argv[]) { + const int num_threads = 64, N = 128; + int array[num_threads] = {0}; + +#pragma omp parallel for + for (int i = 0; i < num_threads; ++i) { + int tmp[N]; + + for (int j = 0; j < N; ++j) { + tmp[j] = i; + } + +#pragma omp target teams distribute parallel for map(tofrom : tmp) + for (int j = 0; j < N; ++j) { + tmp[j] += j; + } + + for (int j = 0; j < N; ++j) { + array[i] += tmp[j]; + } + } + + // Verify + for (int i = 0; i < num_threads; ++i) { + const int ref = (0 + N - 1) * N / 2 + i * N; + assert(array[i] == ref); + } + + printf("PASS\n"); + + return 0; +} + +// CHECK: PASS -- GitLab From 6d4ebada797f22f1bdb9bf07f7e51671d6af458c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 11 Feb 2020 15:13:42 -0500 Subject: [PATCH 109/142] AMDGPU: Use conditions directly in division expansion This was creating a select on true/false values, and then comparing that later. This produced more work for later combines, which can be avoided by just using the boolean values. This was copied from the original DAG expansion, which also has the same problem. This doesn't have a observable change using SelectionDAG, but since GlobalISel is missing these optimizations, the final code was noticeably longer. --- .../Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 29 +- ...amdgpu-codegenprepare-fold-binop-select.ll | 42 +- .../AMDGPU/amdgpu-codegenprepare-idiv.ll | 1628 ++++++++--------- 3 files changed, 802 insertions(+), 897 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index adf2648441e4..8840b0a180c0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -987,7 +987,6 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder, ConstantInt *Zero = Builder.getInt32(0); ConstantInt *One = Builder.getInt32(1); - ConstantInt *MinusOne = Builder.getInt32(~0); Value *Sign = nullptr; if (IsSigned) { @@ -1048,18 +1047,14 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder, // Remainder = Num - Num_S_Remainder Value *Remainder = Builder.CreateSub(Num, Num_S_Remainder); - // Remainder_GE_Den = (Remainder >= Den ? -1 : 0) - Value *Rem_GE_Den_CC = Builder.CreateICmpUGE(Remainder, Den); - Value *Remainder_GE_Den = Builder.CreateSelect(Rem_GE_Den_CC, MinusOne, Zero); + // Remainder_GE_Den = Remainder >= Den; + Value *Remainder_GE_Den = Builder.CreateICmpUGE(Remainder, Den); - // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0) - Value *Num_GE_Num_S_Rem_CC = Builder.CreateICmpUGE(Num, Num_S_Remainder); - Value *Remainder_GE_Zero = Builder.CreateSelect(Num_GE_Num_S_Rem_CC, - MinusOne, Zero); + // Remainder_GE_Zero = Num >= Num_S_Remainder + Value *Remainder_GE_Zero = Builder.CreateICmpUGE(Num, Num_S_Remainder); // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero Value *Tmp1 = Builder.CreateAnd(Remainder_GE_Den, Remainder_GE_Zero); - Value *Tmp1_0_CC = Builder.CreateICmpEQ(Tmp1, Zero); Value *Res; if (IsDiv) { @@ -1069,11 +1064,11 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder, // Quotient_S_One = Quotient - 1 Value *Quotient_S_One = Builder.CreateSub(Quotient, One); - // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One) - Value *Div = Builder.CreateSelect(Tmp1_0_CC, Quotient, Quotient_A_One); + // Div = (Tmp1 ? Quotient_A_One : Quotient) + Value *Div = Builder.CreateSelect(Tmp1, Quotient_A_One, Quotient); - // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div) - Res = Builder.CreateSelect(Num_GE_Num_S_Rem_CC, Div, Quotient_S_One); + // Div = (Remainder_GE_Zero ? Div : Quotient_S_One) + Res = Builder.CreateSelect(Remainder_GE_Zero, Div, Quotient_S_One); } else { // Remainder_S_Den = Remainder - Den Value *Remainder_S_Den = Builder.CreateSub(Remainder, Den); @@ -1081,11 +1076,11 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder, // Remainder_A_Den = Remainder + Den Value *Remainder_A_Den = Builder.CreateAdd(Remainder, Den); - // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den) - Value *Rem = Builder.CreateSelect(Tmp1_0_CC, Remainder, Remainder_S_Den); + // Rem = (Tmp1 ? Remainder_S_Den : Remainder) + Value *Rem = Builder.CreateSelect(Tmp1, Remainder_S_Den, Remainder); - // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem) - Res = Builder.CreateSelect(Num_GE_Num_S_Rem_CC, Rem, Remainder_A_Den); + // Rem = (Remainder_GE_Zero ? Rem : Remainder_A_Den) + Res = Builder.CreateSelect(Remainder_GE_Zero, Rem, Remainder_A_Den); } if (IsSigned) { diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll index fbe9f525300e..1b6a1a7427d6 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll @@ -121,18 +121,15 @@ define i32 @select_sdiv_lhs_opaque_const0_i32(i1 %cond) { ; IR-NEXT: [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP4]] ; IR-NEXT: [[TMP33:%.*]] = sub i32 1000000, [[TMP32]] ; IR-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP4]] -; IR-NEXT: [[TMP35:%.*]] = select i1 [[TMP34]], i32 -1, i32 0 -; IR-NEXT: [[TMP36:%.*]] = icmp uge i32 1000000, [[TMP32]] -; IR-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 -1, i32 0 -; IR-NEXT: [[TMP38:%.*]] = and i32 [[TMP35]], [[TMP37]] -; IR-NEXT: [[TMP39:%.*]] = icmp eq i32 [[TMP38]], 0 -; IR-NEXT: [[TMP40:%.*]] = add i32 [[TMP31]], 1 -; IR-NEXT: [[TMP41:%.*]] = sub i32 [[TMP31]], 1 -; IR-NEXT: [[TMP42:%.*]] = select i1 [[TMP39]], i32 [[TMP31]], i32 [[TMP40]] -; IR-NEXT: [[TMP43:%.*]] = select i1 [[TMP36]], i32 [[TMP42]], i32 [[TMP41]] -; IR-NEXT: [[TMP44:%.*]] = xor i32 [[TMP43]], [[TMP2]] -; IR-NEXT: [[TMP45:%.*]] = sub i32 [[TMP44]], [[TMP2]] -; IR-NEXT: ret i32 [[TMP45]] +; IR-NEXT: [[TMP35:%.*]] = icmp uge i32 1000000, [[TMP32]] +; IR-NEXT: [[TMP36:%.*]] = and i1 [[TMP34]], [[TMP35]] +; IR-NEXT: [[TMP37:%.*]] = add i32 [[TMP31]], 1 +; IR-NEXT: [[TMP38:%.*]] = sub i32 [[TMP31]], 1 +; IR-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP31]] +; IR-NEXT: [[TMP40:%.*]] = select i1 [[TMP35]], i32 [[TMP39]], i32 [[TMP38]] +; IR-NEXT: [[TMP41:%.*]] = xor i32 [[TMP40]], [[TMP2]] +; IR-NEXT: [[TMP42:%.*]] = sub i32 [[TMP41]], [[TMP2]] +; IR-NEXT: ret i32 [[TMP42]] ; ; GCN-LABEL: select_sdiv_lhs_opaque_const0_i32: ; GCN: ; %bb.0: @@ -219,18 +216,15 @@ define i32 @select_sdiv_lhs_opaque_const1_i32(i1 %cond) { ; IR-NEXT: [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP4]] ; IR-NEXT: [[TMP33:%.*]] = sub i32 1000000, [[TMP32]] ; IR-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP4]] -; IR-NEXT: [[TMP35:%.*]] = select i1 [[TMP34]], i32 -1, i32 0 -; IR-NEXT: [[TMP36:%.*]] = icmp uge i32 1000000, [[TMP32]] -; IR-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 -1, i32 0 -; IR-NEXT: [[TMP38:%.*]] = and i32 [[TMP35]], [[TMP37]] -; IR-NEXT: [[TMP39:%.*]] = icmp eq i32 [[TMP38]], 0 -; IR-NEXT: [[TMP40:%.*]] = add i32 [[TMP31]], 1 -; IR-NEXT: [[TMP41:%.*]] = sub i32 [[TMP31]], 1 -; IR-NEXT: [[TMP42:%.*]] = select i1 [[TMP39]], i32 [[TMP31]], i32 [[TMP40]] -; IR-NEXT: [[TMP43:%.*]] = select i1 [[TMP36]], i32 [[TMP42]], i32 [[TMP41]] -; IR-NEXT: [[TMP44:%.*]] = xor i32 [[TMP43]], [[TMP2]] -; IR-NEXT: [[TMP45:%.*]] = sub i32 [[TMP44]], [[TMP2]] -; IR-NEXT: ret i32 [[TMP45]] +; IR-NEXT: [[TMP35:%.*]] = icmp uge i32 1000000, [[TMP32]] +; IR-NEXT: [[TMP36:%.*]] = and i1 [[TMP34]], [[TMP35]] +; IR-NEXT: [[TMP37:%.*]] = add i32 [[TMP31]], 1 +; IR-NEXT: [[TMP38:%.*]] = sub i32 [[TMP31]], 1 +; IR-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP31]] +; IR-NEXT: [[TMP40:%.*]] = select i1 [[TMP35]], i32 [[TMP39]], i32 [[TMP38]] +; IR-NEXT: [[TMP41:%.*]] = xor i32 [[TMP40]], [[TMP2]] +; IR-NEXT: [[TMP42:%.*]] = sub i32 [[TMP41]], [[TMP2]] +; IR-NEXT: ret i32 [[TMP42]] ; ; GCN-LABEL: select_sdiv_lhs_opaque_const1_i32: ; GCN: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index 6ee3964e77b7..daf56e41522a 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -36,16 +36,13 @@ define amdgpu_kernel void @udiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[Y]] ; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[X]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[Y]] -; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP31]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[X]], [[TMP29]] -; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP32]], [[TMP34]] -; CHECK-NEXT: [[TMP36:%.*]] = icmp eq i32 [[TMP35]], 0 -; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP28]], 1 -; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP28]], 1 -; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP28]], i32 [[TMP37]] -; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP33]], i32 [[TMP39]], i32 [[TMP38]] -; CHECK-NEXT: store i32 [[TMP40]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP32:%.*]] = icmp uge i32 [[X]], [[TMP29]] +; CHECK-NEXT: [[TMP33:%.*]] = and i1 [[TMP31]], [[TMP32]] +; CHECK-NEXT: [[TMP34:%.*]] = add i32 [[TMP28]], 1 +; CHECK-NEXT: [[TMP35:%.*]] = sub i32 [[TMP28]], 1 +; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP28]] +; CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP32]], i32 [[TMP36]], i32 [[TMP35]] +; CHECK-NEXT: store i32 [[TMP37]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: udiv_i32: @@ -118,16 +115,13 @@ define amdgpu_kernel void @urem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: [[TMP29:%.*]] = mul i32 [[TMP28]], [[Y]] ; CHECK-NEXT: [[TMP30:%.*]] = sub i32 [[X]], [[TMP29]] ; CHECK-NEXT: [[TMP31:%.*]] = icmp uge i32 [[TMP30]], [[Y]] -; CHECK-NEXT: [[TMP32:%.*]] = select i1 [[TMP31]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[X]], [[TMP29]] -; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP35:%.*]] = and i32 [[TMP32]], [[TMP34]] -; CHECK-NEXT: [[TMP36:%.*]] = icmp eq i32 [[TMP35]], 0 -; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP30]], [[Y]] -; CHECK-NEXT: [[TMP38:%.*]] = add i32 [[TMP30]], [[Y]] -; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP30]], i32 [[TMP37]] -; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP33]], i32 [[TMP39]], i32 [[TMP38]] -; CHECK-NEXT: store i32 [[TMP40]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP32:%.*]] = icmp uge i32 [[X]], [[TMP29]] +; CHECK-NEXT: [[TMP33:%.*]] = and i1 [[TMP31]], [[TMP32]] +; CHECK-NEXT: [[TMP34:%.*]] = sub i32 [[TMP30]], [[Y]] +; CHECK-NEXT: [[TMP35:%.*]] = add i32 [[TMP30]], [[Y]] +; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP33]], i32 [[TMP34]], i32 [[TMP30]] +; CHECK-NEXT: [[TMP37:%.*]] = select i1 [[TMP32]], i32 [[TMP36]], i32 [[TMP35]] +; CHECK-NEXT: store i32 [[TMP37]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: urem_i32: @@ -207,18 +201,15 @@ define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: [[TMP36:%.*]] = mul i32 [[TMP35]], [[TMP7]] ; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP6]], [[TMP36]] ; CHECK-NEXT: [[TMP38:%.*]] = icmp uge i32 [[TMP37]], [[TMP7]] -; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP38]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP40:%.*]] = icmp uge i32 [[TMP6]], [[TMP36]] -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP42:%.*]] = and i32 [[TMP39]], [[TMP41]] -; CHECK-NEXT: [[TMP43:%.*]] = icmp eq i32 [[TMP42]], 0 -; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP35]], 1 -; CHECK-NEXT: [[TMP45:%.*]] = sub i32 [[TMP35]], 1 -; CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP43]], i32 [[TMP35]], i32 [[TMP44]] -; CHECK-NEXT: [[TMP47:%.*]] = select i1 [[TMP40]], i32 [[TMP46]], i32 [[TMP45]] -; CHECK-NEXT: [[TMP48:%.*]] = xor i32 [[TMP47]], [[TMP3]] -; CHECK-NEXT: [[TMP49:%.*]] = sub i32 [[TMP48]], [[TMP3]] -; CHECK-NEXT: store i32 [[TMP49]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP39:%.*]] = icmp uge i32 [[TMP6]], [[TMP36]] +; CHECK-NEXT: [[TMP40:%.*]] = and i1 [[TMP38]], [[TMP39]] +; CHECK-NEXT: [[TMP41:%.*]] = add i32 [[TMP35]], 1 +; CHECK-NEXT: [[TMP42:%.*]] = sub i32 [[TMP35]], 1 +; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP40]], i32 [[TMP41]], i32 [[TMP35]] +; CHECK-NEXT: [[TMP44:%.*]] = select i1 [[TMP39]], i32 [[TMP43]], i32 [[TMP42]] +; CHECK-NEXT: [[TMP45:%.*]] = xor i32 [[TMP44]], [[TMP3]] +; CHECK-NEXT: [[TMP46:%.*]] = sub i32 [[TMP45]], [[TMP3]] +; CHECK-NEXT: store i32 [[TMP46]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: sdiv_i32: @@ -306,18 +297,15 @@ define amdgpu_kernel void @srem_i32(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; CHECK-NEXT: [[TMP35:%.*]] = mul i32 [[TMP34]], [[TMP6]] ; CHECK-NEXT: [[TMP36:%.*]] = sub i32 [[TMP5]], [[TMP35]] ; CHECK-NEXT: [[TMP37:%.*]] = icmp uge i32 [[TMP36]], [[TMP6]] -; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP37]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP39:%.*]] = icmp uge i32 [[TMP5]], [[TMP35]] -; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP39]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP41:%.*]] = and i32 [[TMP38]], [[TMP40]] -; CHECK-NEXT: [[TMP42:%.*]] = icmp eq i32 [[TMP41]], 0 -; CHECK-NEXT: [[TMP43:%.*]] = sub i32 [[TMP36]], [[TMP6]] -; CHECK-NEXT: [[TMP44:%.*]] = add i32 [[TMP36]], [[TMP6]] -; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP42]], i32 [[TMP36]], i32 [[TMP43]] -; CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP39]], i32 [[TMP45]], i32 [[TMP44]] -; CHECK-NEXT: [[TMP47:%.*]] = xor i32 [[TMP46]], [[TMP1]] -; CHECK-NEXT: [[TMP48:%.*]] = sub i32 [[TMP47]], [[TMP1]] -; CHECK-NEXT: store i32 [[TMP48]], i32 addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP38:%.*]] = icmp uge i32 [[TMP5]], [[TMP35]] +; CHECK-NEXT: [[TMP39:%.*]] = and i1 [[TMP37]], [[TMP38]] +; CHECK-NEXT: [[TMP40:%.*]] = sub i32 [[TMP36]], [[TMP6]] +; CHECK-NEXT: [[TMP41:%.*]] = add i32 [[TMP36]], [[TMP6]] +; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP39]], i32 [[TMP40]], i32 [[TMP36]] +; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP38]], i32 [[TMP42]], i32 [[TMP41]] +; CHECK-NEXT: [[TMP44:%.*]] = xor i32 [[TMP43]], [[TMP1]] +; CHECK-NEXT: [[TMP45:%.*]] = sub i32 [[TMP44]], [[TMP1]] +; CHECK-NEXT: store i32 [[TMP45]], i32 addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: srem_i32: @@ -827,146 +815,134 @@ define amdgpu_kernel void @udiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[TMP2]] ; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP1]], [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP2]] -; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP35:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] -; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP37:%.*]] = and i32 [[TMP34]], [[TMP36]] -; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i32 [[TMP37]], 0 -; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[TMP30]], 1 -; CHECK-NEXT: [[TMP40:%.*]] = sub i32 [[TMP30]], 1 -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP38]], i32 [[TMP30]], i32 [[TMP39]] -; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], i32 [[TMP41]], i32 [[TMP40]] -; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x i32> undef, i32 [[TMP42]], i64 0 -; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[X]], i64 1 -; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[Y]], i64 1 -; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP45]] to float -; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) -; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP47]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP49:%.*]] = fptoui float [[TMP48]] to i32 -; CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 -; CHECK-NEXT: [[TMP51:%.*]] = zext i32 [[TMP45]] to i64 -; CHECK-NEXT: [[TMP52:%.*]] = mul i64 [[TMP50]], [[TMP51]] -; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32 -; CHECK-NEXT: [[TMP54:%.*]] = lshr i64 [[TMP52]], 32 -; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i32 -; CHECK-NEXT: [[TMP56:%.*]] = sub i32 0, [[TMP53]] -; CHECK-NEXT: [[TMP57:%.*]] = icmp eq i32 [[TMP55]], 0 -; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], i32 [[TMP56]], i32 [[TMP53]] -; CHECK-NEXT: [[TMP59:%.*]] = zext i32 [[TMP58]] to i64 -; CHECK-NEXT: [[TMP60:%.*]] = zext i32 [[TMP49]] to i64 -; CHECK-NEXT: [[TMP61:%.*]] = mul i64 [[TMP59]], [[TMP60]] -; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32 -; CHECK-NEXT: [[TMP63:%.*]] = lshr i64 [[TMP61]], 32 -; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[TMP63]] to i32 -; CHECK-NEXT: [[TMP65:%.*]] = add i32 [[TMP49]], [[TMP64]] -; CHECK-NEXT: [[TMP66:%.*]] = sub i32 [[TMP49]], [[TMP64]] -; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP57]], i32 [[TMP65]], i32 [[TMP66]] -; CHECK-NEXT: [[TMP68:%.*]] = zext i32 [[TMP67]] to i64 -; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP44]] to i64 -; CHECK-NEXT: [[TMP70:%.*]] = mul i64 [[TMP68]], [[TMP69]] -; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 -; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP70]], 32 -; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP72]] to i32 -; CHECK-NEXT: [[TMP74:%.*]] = mul i32 [[TMP73]], [[TMP45]] -; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP44]], [[TMP74]] -; CHECK-NEXT: [[TMP76:%.*]] = icmp uge i32 [[TMP75]], [[TMP45]] -; CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP78:%.*]] = icmp uge i32 [[TMP44]], [[TMP74]] -; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP78]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP80:%.*]] = and i32 [[TMP77]], [[TMP79]] -; CHECK-NEXT: [[TMP81:%.*]] = icmp eq i32 [[TMP80]], 0 -; CHECK-NEXT: [[TMP82:%.*]] = add i32 [[TMP73]], 1 -; CHECK-NEXT: [[TMP83:%.*]] = sub i32 [[TMP73]], 1 -; CHECK-NEXT: [[TMP84:%.*]] = select i1 [[TMP81]], i32 [[TMP73]], i32 [[TMP82]] -; CHECK-NEXT: [[TMP85:%.*]] = select i1 [[TMP78]], i32 [[TMP84]], i32 [[TMP83]] -; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[TMP85]], i64 1 -; CHECK-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[X]], i64 2 -; CHECK-NEXT: [[TMP88:%.*]] = extractelement <4 x i32> [[Y]], i64 2 -; CHECK-NEXT: [[TMP89:%.*]] = uitofp i32 [[TMP88]] to float -; CHECK-NEXT: [[TMP90:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP89]]) -; CHECK-NEXT: [[TMP91:%.*]] = fmul fast float [[TMP90]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP92:%.*]] = fptoui float [[TMP91]] to i32 -; CHECK-NEXT: [[TMP93:%.*]] = zext i32 [[TMP92]] to i64 -; CHECK-NEXT: [[TMP94:%.*]] = zext i32 [[TMP88]] to i64 -; CHECK-NEXT: [[TMP95:%.*]] = mul i64 [[TMP93]], [[TMP94]] -; CHECK-NEXT: [[TMP96:%.*]] = trunc i64 [[TMP95]] to i32 -; CHECK-NEXT: [[TMP97:%.*]] = lshr i64 [[TMP95]], 32 -; CHECK-NEXT: [[TMP98:%.*]] = trunc i64 [[TMP97]] to i32 -; CHECK-NEXT: [[TMP99:%.*]] = sub i32 0, [[TMP96]] -; CHECK-NEXT: [[TMP100:%.*]] = icmp eq i32 [[TMP98]], 0 -; CHECK-NEXT: [[TMP101:%.*]] = select i1 [[TMP100]], i32 [[TMP99]], i32 [[TMP96]] -; CHECK-NEXT: [[TMP102:%.*]] = zext i32 [[TMP101]] to i64 -; CHECK-NEXT: [[TMP103:%.*]] = zext i32 [[TMP92]] to i64 -; CHECK-NEXT: [[TMP104:%.*]] = mul i64 [[TMP102]], [[TMP103]] -; CHECK-NEXT: [[TMP105:%.*]] = trunc i64 [[TMP104]] to i32 -; CHECK-NEXT: [[TMP106:%.*]] = lshr i64 [[TMP104]], 32 -; CHECK-NEXT: [[TMP107:%.*]] = trunc i64 [[TMP106]] to i32 -; CHECK-NEXT: [[TMP108:%.*]] = add i32 [[TMP92]], [[TMP107]] -; CHECK-NEXT: [[TMP109:%.*]] = sub i32 [[TMP92]], [[TMP107]] -; CHECK-NEXT: [[TMP110:%.*]] = select i1 [[TMP100]], i32 [[TMP108]], i32 [[TMP109]] -; CHECK-NEXT: [[TMP111:%.*]] = zext i32 [[TMP110]] to i64 -; CHECK-NEXT: [[TMP112:%.*]] = zext i32 [[TMP87]] to i64 -; CHECK-NEXT: [[TMP113:%.*]] = mul i64 [[TMP111]], [[TMP112]] -; CHECK-NEXT: [[TMP114:%.*]] = trunc i64 [[TMP113]] to i32 -; CHECK-NEXT: [[TMP115:%.*]] = lshr i64 [[TMP113]], 32 -; CHECK-NEXT: [[TMP116:%.*]] = trunc i64 [[TMP115]] to i32 -; CHECK-NEXT: [[TMP117:%.*]] = mul i32 [[TMP116]], [[TMP88]] -; CHECK-NEXT: [[TMP118:%.*]] = sub i32 [[TMP87]], [[TMP117]] -; CHECK-NEXT: [[TMP119:%.*]] = icmp uge i32 [[TMP118]], [[TMP88]] -; CHECK-NEXT: [[TMP120:%.*]] = select i1 [[TMP119]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP121:%.*]] = icmp uge i32 [[TMP87]], [[TMP117]] -; CHECK-NEXT: [[TMP122:%.*]] = select i1 [[TMP121]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP123:%.*]] = and i32 [[TMP120]], [[TMP122]] -; CHECK-NEXT: [[TMP124:%.*]] = icmp eq i32 [[TMP123]], 0 -; CHECK-NEXT: [[TMP125:%.*]] = add i32 [[TMP116]], 1 -; CHECK-NEXT: [[TMP126:%.*]] = sub i32 [[TMP116]], 1 -; CHECK-NEXT: [[TMP127:%.*]] = select i1 [[TMP124]], i32 [[TMP116]], i32 [[TMP125]] -; CHECK-NEXT: [[TMP128:%.*]] = select i1 [[TMP121]], i32 [[TMP127]], i32 [[TMP126]] -; CHECK-NEXT: [[TMP129:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP128]], i64 2 -; CHECK-NEXT: [[TMP130:%.*]] = extractelement <4 x i32> [[X]], i64 3 -; CHECK-NEXT: [[TMP131:%.*]] = extractelement <4 x i32> [[Y]], i64 3 -; CHECK-NEXT: [[TMP132:%.*]] = uitofp i32 [[TMP131]] to float -; CHECK-NEXT: [[TMP133:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP132]]) -; CHECK-NEXT: [[TMP134:%.*]] = fmul fast float [[TMP133]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP135:%.*]] = fptoui float [[TMP134]] to i32 +; CHECK-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] +; CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP33]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = add i32 [[TMP30]], 1 +; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP30]], 1 +; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP35]], i32 [[TMP36]], i32 [[TMP30]] +; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP34]], i32 [[TMP38]], i32 [[TMP37]] +; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i32> undef, i32 [[TMP39]], i64 0 +; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[Y]], i64 1 +; CHECK-NEXT: [[TMP43:%.*]] = uitofp i32 [[TMP42]] to float +; CHECK-NEXT: [[TMP44:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP43]]) +; CHECK-NEXT: [[TMP45:%.*]] = fmul fast float [[TMP44]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP46:%.*]] = fptoui float [[TMP45]] to i32 +; CHECK-NEXT: [[TMP47:%.*]] = zext i32 [[TMP46]] to i64 +; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP42]] to i64 +; CHECK-NEXT: [[TMP49:%.*]] = mul i64 [[TMP47]], [[TMP48]] +; CHECK-NEXT: [[TMP50:%.*]] = trunc i64 [[TMP49]] to i32 +; CHECK-NEXT: [[TMP51:%.*]] = lshr i64 [[TMP49]], 32 +; CHECK-NEXT: [[TMP52:%.*]] = trunc i64 [[TMP51]] to i32 +; CHECK-NEXT: [[TMP53:%.*]] = sub i32 0, [[TMP50]] +; CHECK-NEXT: [[TMP54:%.*]] = icmp eq i32 [[TMP52]], 0 +; CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP53]], i32 [[TMP50]] +; CHECK-NEXT: [[TMP56:%.*]] = zext i32 [[TMP55]] to i64 +; CHECK-NEXT: [[TMP57:%.*]] = zext i32 [[TMP46]] to i64 +; CHECK-NEXT: [[TMP58:%.*]] = mul i64 [[TMP56]], [[TMP57]] +; CHECK-NEXT: [[TMP59:%.*]] = trunc i64 [[TMP58]] to i32 +; CHECK-NEXT: [[TMP60:%.*]] = lshr i64 [[TMP58]], 32 +; CHECK-NEXT: [[TMP61:%.*]] = trunc i64 [[TMP60]] to i32 +; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP46]], [[TMP61]] +; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP46]], [[TMP61]] +; CHECK-NEXT: [[TMP64:%.*]] = select i1 [[TMP54]], i32 [[TMP62]], i32 [[TMP63]] +; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP64]] to i64 +; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP41]] to i64 +; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[TMP65]], [[TMP66]] +; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i32 +; CHECK-NEXT: [[TMP69:%.*]] = lshr i64 [[TMP67]], 32 +; CHECK-NEXT: [[TMP70:%.*]] = trunc i64 [[TMP69]] to i32 +; CHECK-NEXT: [[TMP71:%.*]] = mul i32 [[TMP70]], [[TMP42]] +; CHECK-NEXT: [[TMP72:%.*]] = sub i32 [[TMP41]], [[TMP71]] +; CHECK-NEXT: [[TMP73:%.*]] = icmp uge i32 [[TMP72]], [[TMP42]] +; CHECK-NEXT: [[TMP74:%.*]] = icmp uge i32 [[TMP41]], [[TMP71]] +; CHECK-NEXT: [[TMP75:%.*]] = and i1 [[TMP73]], [[TMP74]] +; CHECK-NEXT: [[TMP76:%.*]] = add i32 [[TMP70]], 1 +; CHECK-NEXT: [[TMP77:%.*]] = sub i32 [[TMP70]], 1 +; CHECK-NEXT: [[TMP78:%.*]] = select i1 [[TMP75]], i32 [[TMP76]], i32 [[TMP70]] +; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP74]], i32 [[TMP78]], i32 [[TMP77]] +; CHECK-NEXT: [[TMP80:%.*]] = insertelement <4 x i32> [[TMP40]], i32 [[TMP79]], i64 1 +; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i32> [[X]], i64 2 +; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i32> [[Y]], i64 2 +; CHECK-NEXT: [[TMP83:%.*]] = uitofp i32 [[TMP82]] to float +; CHECK-NEXT: [[TMP84:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP83]]) +; CHECK-NEXT: [[TMP85:%.*]] = fmul fast float [[TMP84]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP86:%.*]] = fptoui float [[TMP85]] to i32 +; CHECK-NEXT: [[TMP87:%.*]] = zext i32 [[TMP86]] to i64 +; CHECK-NEXT: [[TMP88:%.*]] = zext i32 [[TMP82]] to i64 +; CHECK-NEXT: [[TMP89:%.*]] = mul i64 [[TMP87]], [[TMP88]] +; CHECK-NEXT: [[TMP90:%.*]] = trunc i64 [[TMP89]] to i32 +; CHECK-NEXT: [[TMP91:%.*]] = lshr i64 [[TMP89]], 32 +; CHECK-NEXT: [[TMP92:%.*]] = trunc i64 [[TMP91]] to i32 +; CHECK-NEXT: [[TMP93:%.*]] = sub i32 0, [[TMP90]] +; CHECK-NEXT: [[TMP94:%.*]] = icmp eq i32 [[TMP92]], 0 +; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP94]], i32 [[TMP93]], i32 [[TMP90]] +; CHECK-NEXT: [[TMP96:%.*]] = zext i32 [[TMP95]] to i64 +; CHECK-NEXT: [[TMP97:%.*]] = zext i32 [[TMP86]] to i64 +; CHECK-NEXT: [[TMP98:%.*]] = mul i64 [[TMP96]], [[TMP97]] +; CHECK-NEXT: [[TMP99:%.*]] = trunc i64 [[TMP98]] to i32 +; CHECK-NEXT: [[TMP100:%.*]] = lshr i64 [[TMP98]], 32 +; CHECK-NEXT: [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32 +; CHECK-NEXT: [[TMP102:%.*]] = add i32 [[TMP86]], [[TMP101]] +; CHECK-NEXT: [[TMP103:%.*]] = sub i32 [[TMP86]], [[TMP101]] +; CHECK-NEXT: [[TMP104:%.*]] = select i1 [[TMP94]], i32 [[TMP102]], i32 [[TMP103]] +; CHECK-NEXT: [[TMP105:%.*]] = zext i32 [[TMP104]] to i64 +; CHECK-NEXT: [[TMP106:%.*]] = zext i32 [[TMP81]] to i64 +; CHECK-NEXT: [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]] +; CHECK-NEXT: [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32 +; CHECK-NEXT: [[TMP109:%.*]] = lshr i64 [[TMP107]], 32 +; CHECK-NEXT: [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32 +; CHECK-NEXT: [[TMP111:%.*]] = mul i32 [[TMP110]], [[TMP82]] +; CHECK-NEXT: [[TMP112:%.*]] = sub i32 [[TMP81]], [[TMP111]] +; CHECK-NEXT: [[TMP113:%.*]] = icmp uge i32 [[TMP112]], [[TMP82]] +; CHECK-NEXT: [[TMP114:%.*]] = icmp uge i32 [[TMP81]], [[TMP111]] +; CHECK-NEXT: [[TMP115:%.*]] = and i1 [[TMP113]], [[TMP114]] +; CHECK-NEXT: [[TMP116:%.*]] = add i32 [[TMP110]], 1 +; CHECK-NEXT: [[TMP117:%.*]] = sub i32 [[TMP110]], 1 +; CHECK-NEXT: [[TMP118:%.*]] = select i1 [[TMP115]], i32 [[TMP116]], i32 [[TMP110]] +; CHECK-NEXT: [[TMP119:%.*]] = select i1 [[TMP114]], i32 [[TMP118]], i32 [[TMP117]] +; CHECK-NEXT: [[TMP120:%.*]] = insertelement <4 x i32> [[TMP80]], i32 [[TMP119]], i64 2 +; CHECK-NEXT: [[TMP121:%.*]] = extractelement <4 x i32> [[X]], i64 3 +; CHECK-NEXT: [[TMP122:%.*]] = extractelement <4 x i32> [[Y]], i64 3 +; CHECK-NEXT: [[TMP123:%.*]] = uitofp i32 [[TMP122]] to float +; CHECK-NEXT: [[TMP124:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP123]]) +; CHECK-NEXT: [[TMP125:%.*]] = fmul fast float [[TMP124]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP126:%.*]] = fptoui float [[TMP125]] to i32 +; CHECK-NEXT: [[TMP127:%.*]] = zext i32 [[TMP126]] to i64 +; CHECK-NEXT: [[TMP128:%.*]] = zext i32 [[TMP122]] to i64 +; CHECK-NEXT: [[TMP129:%.*]] = mul i64 [[TMP127]], [[TMP128]] +; CHECK-NEXT: [[TMP130:%.*]] = trunc i64 [[TMP129]] to i32 +; CHECK-NEXT: [[TMP131:%.*]] = lshr i64 [[TMP129]], 32 +; CHECK-NEXT: [[TMP132:%.*]] = trunc i64 [[TMP131]] to i32 +; CHECK-NEXT: [[TMP133:%.*]] = sub i32 0, [[TMP130]] +; CHECK-NEXT: [[TMP134:%.*]] = icmp eq i32 [[TMP132]], 0 +; CHECK-NEXT: [[TMP135:%.*]] = select i1 [[TMP134]], i32 [[TMP133]], i32 [[TMP130]] ; CHECK-NEXT: [[TMP136:%.*]] = zext i32 [[TMP135]] to i64 -; CHECK-NEXT: [[TMP137:%.*]] = zext i32 [[TMP131]] to i64 +; CHECK-NEXT: [[TMP137:%.*]] = zext i32 [[TMP126]] to i64 ; CHECK-NEXT: [[TMP138:%.*]] = mul i64 [[TMP136]], [[TMP137]] ; CHECK-NEXT: [[TMP139:%.*]] = trunc i64 [[TMP138]] to i32 ; CHECK-NEXT: [[TMP140:%.*]] = lshr i64 [[TMP138]], 32 ; CHECK-NEXT: [[TMP141:%.*]] = trunc i64 [[TMP140]] to i32 -; CHECK-NEXT: [[TMP142:%.*]] = sub i32 0, [[TMP139]] -; CHECK-NEXT: [[TMP143:%.*]] = icmp eq i32 [[TMP141]], 0 -; CHECK-NEXT: [[TMP144:%.*]] = select i1 [[TMP143]], i32 [[TMP142]], i32 [[TMP139]] +; CHECK-NEXT: [[TMP142:%.*]] = add i32 [[TMP126]], [[TMP141]] +; CHECK-NEXT: [[TMP143:%.*]] = sub i32 [[TMP126]], [[TMP141]] +; CHECK-NEXT: [[TMP144:%.*]] = select i1 [[TMP134]], i32 [[TMP142]], i32 [[TMP143]] ; CHECK-NEXT: [[TMP145:%.*]] = zext i32 [[TMP144]] to i64 -; CHECK-NEXT: [[TMP146:%.*]] = zext i32 [[TMP135]] to i64 +; CHECK-NEXT: [[TMP146:%.*]] = zext i32 [[TMP121]] to i64 ; CHECK-NEXT: [[TMP147:%.*]] = mul i64 [[TMP145]], [[TMP146]] ; CHECK-NEXT: [[TMP148:%.*]] = trunc i64 [[TMP147]] to i32 ; CHECK-NEXT: [[TMP149:%.*]] = lshr i64 [[TMP147]], 32 ; CHECK-NEXT: [[TMP150:%.*]] = trunc i64 [[TMP149]] to i32 -; CHECK-NEXT: [[TMP151:%.*]] = add i32 [[TMP135]], [[TMP150]] -; CHECK-NEXT: [[TMP152:%.*]] = sub i32 [[TMP135]], [[TMP150]] -; CHECK-NEXT: [[TMP153:%.*]] = select i1 [[TMP143]], i32 [[TMP151]], i32 [[TMP152]] -; CHECK-NEXT: [[TMP154:%.*]] = zext i32 [[TMP153]] to i64 -; CHECK-NEXT: [[TMP155:%.*]] = zext i32 [[TMP130]] to i64 -; CHECK-NEXT: [[TMP156:%.*]] = mul i64 [[TMP154]], [[TMP155]] -; CHECK-NEXT: [[TMP157:%.*]] = trunc i64 [[TMP156]] to i32 -; CHECK-NEXT: [[TMP158:%.*]] = lshr i64 [[TMP156]], 32 -; CHECK-NEXT: [[TMP159:%.*]] = trunc i64 [[TMP158]] to i32 -; CHECK-NEXT: [[TMP160:%.*]] = mul i32 [[TMP159]], [[TMP131]] -; CHECK-NEXT: [[TMP161:%.*]] = sub i32 [[TMP130]], [[TMP160]] -; CHECK-NEXT: [[TMP162:%.*]] = icmp uge i32 [[TMP161]], [[TMP131]] -; CHECK-NEXT: [[TMP163:%.*]] = select i1 [[TMP162]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP164:%.*]] = icmp uge i32 [[TMP130]], [[TMP160]] -; CHECK-NEXT: [[TMP165:%.*]] = select i1 [[TMP164]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP166:%.*]] = and i32 [[TMP163]], [[TMP165]] -; CHECK-NEXT: [[TMP167:%.*]] = icmp eq i32 [[TMP166]], 0 -; CHECK-NEXT: [[TMP168:%.*]] = add i32 [[TMP159]], 1 -; CHECK-NEXT: [[TMP169:%.*]] = sub i32 [[TMP159]], 1 -; CHECK-NEXT: [[TMP170:%.*]] = select i1 [[TMP167]], i32 [[TMP159]], i32 [[TMP168]] -; CHECK-NEXT: [[TMP171:%.*]] = select i1 [[TMP164]], i32 [[TMP170]], i32 [[TMP169]] -; CHECK-NEXT: [[TMP172:%.*]] = insertelement <4 x i32> [[TMP129]], i32 [[TMP171]], i64 3 -; CHECK-NEXT: store <4 x i32> [[TMP172]], <4 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP151:%.*]] = mul i32 [[TMP150]], [[TMP122]] +; CHECK-NEXT: [[TMP152:%.*]] = sub i32 [[TMP121]], [[TMP151]] +; CHECK-NEXT: [[TMP153:%.*]] = icmp uge i32 [[TMP152]], [[TMP122]] +; CHECK-NEXT: [[TMP154:%.*]] = icmp uge i32 [[TMP121]], [[TMP151]] +; CHECK-NEXT: [[TMP155:%.*]] = and i1 [[TMP153]], [[TMP154]] +; CHECK-NEXT: [[TMP156:%.*]] = add i32 [[TMP150]], 1 +; CHECK-NEXT: [[TMP157:%.*]] = sub i32 [[TMP150]], 1 +; CHECK-NEXT: [[TMP158:%.*]] = select i1 [[TMP155]], i32 [[TMP156]], i32 [[TMP150]] +; CHECK-NEXT: [[TMP159:%.*]] = select i1 [[TMP154]], i32 [[TMP158]], i32 [[TMP157]] +; CHECK-NEXT: [[TMP160:%.*]] = insertelement <4 x i32> [[TMP120]], i32 [[TMP159]], i64 3 +; CHECK-NEXT: store <4 x i32> [[TMP160]], <4 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: udiv_v4i32: @@ -1111,146 +1087,134 @@ define amdgpu_kernel void @urem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[TMP2]] ; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP1]], [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP2]] -; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP35:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] -; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP37:%.*]] = and i32 [[TMP34]], [[TMP36]] -; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i32 [[TMP37]], 0 -; CHECK-NEXT: [[TMP39:%.*]] = sub i32 [[TMP32]], [[TMP2]] -; CHECK-NEXT: [[TMP40:%.*]] = add i32 [[TMP32]], [[TMP2]] -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP38]], i32 [[TMP32]], i32 [[TMP39]] -; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], i32 [[TMP41]], i32 [[TMP40]] -; CHECK-NEXT: [[TMP43:%.*]] = insertelement <4 x i32> undef, i32 [[TMP42]], i64 0 -; CHECK-NEXT: [[TMP44:%.*]] = extractelement <4 x i32> [[X]], i64 1 -; CHECK-NEXT: [[TMP45:%.*]] = extractelement <4 x i32> [[Y]], i64 1 -; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP45]] to float -; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) -; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP47]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP49:%.*]] = fptoui float [[TMP48]] to i32 -; CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 -; CHECK-NEXT: [[TMP51:%.*]] = zext i32 [[TMP45]] to i64 -; CHECK-NEXT: [[TMP52:%.*]] = mul i64 [[TMP50]], [[TMP51]] -; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32 -; CHECK-NEXT: [[TMP54:%.*]] = lshr i64 [[TMP52]], 32 -; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i32 -; CHECK-NEXT: [[TMP56:%.*]] = sub i32 0, [[TMP53]] -; CHECK-NEXT: [[TMP57:%.*]] = icmp eq i32 [[TMP55]], 0 -; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], i32 [[TMP56]], i32 [[TMP53]] -; CHECK-NEXT: [[TMP59:%.*]] = zext i32 [[TMP58]] to i64 -; CHECK-NEXT: [[TMP60:%.*]] = zext i32 [[TMP49]] to i64 -; CHECK-NEXT: [[TMP61:%.*]] = mul i64 [[TMP59]], [[TMP60]] -; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32 -; CHECK-NEXT: [[TMP63:%.*]] = lshr i64 [[TMP61]], 32 -; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[TMP63]] to i32 -; CHECK-NEXT: [[TMP65:%.*]] = add i32 [[TMP49]], [[TMP64]] -; CHECK-NEXT: [[TMP66:%.*]] = sub i32 [[TMP49]], [[TMP64]] -; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP57]], i32 [[TMP65]], i32 [[TMP66]] -; CHECK-NEXT: [[TMP68:%.*]] = zext i32 [[TMP67]] to i64 -; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP44]] to i64 -; CHECK-NEXT: [[TMP70:%.*]] = mul i64 [[TMP68]], [[TMP69]] -; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 -; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP70]], 32 -; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP72]] to i32 -; CHECK-NEXT: [[TMP74:%.*]] = mul i32 [[TMP73]], [[TMP45]] -; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP44]], [[TMP74]] -; CHECK-NEXT: [[TMP76:%.*]] = icmp uge i32 [[TMP75]], [[TMP45]] -; CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP78:%.*]] = icmp uge i32 [[TMP44]], [[TMP74]] -; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP78]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP80:%.*]] = and i32 [[TMP77]], [[TMP79]] -; CHECK-NEXT: [[TMP81:%.*]] = icmp eq i32 [[TMP80]], 0 -; CHECK-NEXT: [[TMP82:%.*]] = sub i32 [[TMP75]], [[TMP45]] -; CHECK-NEXT: [[TMP83:%.*]] = add i32 [[TMP75]], [[TMP45]] -; CHECK-NEXT: [[TMP84:%.*]] = select i1 [[TMP81]], i32 [[TMP75]], i32 [[TMP82]] -; CHECK-NEXT: [[TMP85:%.*]] = select i1 [[TMP78]], i32 [[TMP84]], i32 [[TMP83]] -; CHECK-NEXT: [[TMP86:%.*]] = insertelement <4 x i32> [[TMP43]], i32 [[TMP85]], i64 1 -; CHECK-NEXT: [[TMP87:%.*]] = extractelement <4 x i32> [[X]], i64 2 -; CHECK-NEXT: [[TMP88:%.*]] = extractelement <4 x i32> [[Y]], i64 2 -; CHECK-NEXT: [[TMP89:%.*]] = uitofp i32 [[TMP88]] to float -; CHECK-NEXT: [[TMP90:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP89]]) -; CHECK-NEXT: [[TMP91:%.*]] = fmul fast float [[TMP90]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP92:%.*]] = fptoui float [[TMP91]] to i32 -; CHECK-NEXT: [[TMP93:%.*]] = zext i32 [[TMP92]] to i64 -; CHECK-NEXT: [[TMP94:%.*]] = zext i32 [[TMP88]] to i64 -; CHECK-NEXT: [[TMP95:%.*]] = mul i64 [[TMP93]], [[TMP94]] -; CHECK-NEXT: [[TMP96:%.*]] = trunc i64 [[TMP95]] to i32 -; CHECK-NEXT: [[TMP97:%.*]] = lshr i64 [[TMP95]], 32 -; CHECK-NEXT: [[TMP98:%.*]] = trunc i64 [[TMP97]] to i32 -; CHECK-NEXT: [[TMP99:%.*]] = sub i32 0, [[TMP96]] -; CHECK-NEXT: [[TMP100:%.*]] = icmp eq i32 [[TMP98]], 0 -; CHECK-NEXT: [[TMP101:%.*]] = select i1 [[TMP100]], i32 [[TMP99]], i32 [[TMP96]] -; CHECK-NEXT: [[TMP102:%.*]] = zext i32 [[TMP101]] to i64 -; CHECK-NEXT: [[TMP103:%.*]] = zext i32 [[TMP92]] to i64 -; CHECK-NEXT: [[TMP104:%.*]] = mul i64 [[TMP102]], [[TMP103]] -; CHECK-NEXT: [[TMP105:%.*]] = trunc i64 [[TMP104]] to i32 -; CHECK-NEXT: [[TMP106:%.*]] = lshr i64 [[TMP104]], 32 -; CHECK-NEXT: [[TMP107:%.*]] = trunc i64 [[TMP106]] to i32 -; CHECK-NEXT: [[TMP108:%.*]] = add i32 [[TMP92]], [[TMP107]] -; CHECK-NEXT: [[TMP109:%.*]] = sub i32 [[TMP92]], [[TMP107]] -; CHECK-NEXT: [[TMP110:%.*]] = select i1 [[TMP100]], i32 [[TMP108]], i32 [[TMP109]] -; CHECK-NEXT: [[TMP111:%.*]] = zext i32 [[TMP110]] to i64 -; CHECK-NEXT: [[TMP112:%.*]] = zext i32 [[TMP87]] to i64 -; CHECK-NEXT: [[TMP113:%.*]] = mul i64 [[TMP111]], [[TMP112]] -; CHECK-NEXT: [[TMP114:%.*]] = trunc i64 [[TMP113]] to i32 -; CHECK-NEXT: [[TMP115:%.*]] = lshr i64 [[TMP113]], 32 -; CHECK-NEXT: [[TMP116:%.*]] = trunc i64 [[TMP115]] to i32 -; CHECK-NEXT: [[TMP117:%.*]] = mul i32 [[TMP116]], [[TMP88]] -; CHECK-NEXT: [[TMP118:%.*]] = sub i32 [[TMP87]], [[TMP117]] -; CHECK-NEXT: [[TMP119:%.*]] = icmp uge i32 [[TMP118]], [[TMP88]] -; CHECK-NEXT: [[TMP120:%.*]] = select i1 [[TMP119]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP121:%.*]] = icmp uge i32 [[TMP87]], [[TMP117]] -; CHECK-NEXT: [[TMP122:%.*]] = select i1 [[TMP121]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP123:%.*]] = and i32 [[TMP120]], [[TMP122]] -; CHECK-NEXT: [[TMP124:%.*]] = icmp eq i32 [[TMP123]], 0 -; CHECK-NEXT: [[TMP125:%.*]] = sub i32 [[TMP118]], [[TMP88]] -; CHECK-NEXT: [[TMP126:%.*]] = add i32 [[TMP118]], [[TMP88]] -; CHECK-NEXT: [[TMP127:%.*]] = select i1 [[TMP124]], i32 [[TMP118]], i32 [[TMP125]] -; CHECK-NEXT: [[TMP128:%.*]] = select i1 [[TMP121]], i32 [[TMP127]], i32 [[TMP126]] -; CHECK-NEXT: [[TMP129:%.*]] = insertelement <4 x i32> [[TMP86]], i32 [[TMP128]], i64 2 -; CHECK-NEXT: [[TMP130:%.*]] = extractelement <4 x i32> [[X]], i64 3 -; CHECK-NEXT: [[TMP131:%.*]] = extractelement <4 x i32> [[Y]], i64 3 -; CHECK-NEXT: [[TMP132:%.*]] = uitofp i32 [[TMP131]] to float -; CHECK-NEXT: [[TMP133:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP132]]) -; CHECK-NEXT: [[TMP134:%.*]] = fmul fast float [[TMP133]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP135:%.*]] = fptoui float [[TMP134]] to i32 +; CHECK-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] +; CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP33]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = sub i32 [[TMP32]], [[TMP2]] +; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP2]] +; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP35]], i32 [[TMP36]], i32 [[TMP32]] +; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP34]], i32 [[TMP38]], i32 [[TMP37]] +; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i32> undef, i32 [[TMP39]], i64 0 +; CHECK-NEXT: [[TMP41:%.*]] = extractelement <4 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP42:%.*]] = extractelement <4 x i32> [[Y]], i64 1 +; CHECK-NEXT: [[TMP43:%.*]] = uitofp i32 [[TMP42]] to float +; CHECK-NEXT: [[TMP44:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP43]]) +; CHECK-NEXT: [[TMP45:%.*]] = fmul fast float [[TMP44]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP46:%.*]] = fptoui float [[TMP45]] to i32 +; CHECK-NEXT: [[TMP47:%.*]] = zext i32 [[TMP46]] to i64 +; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP42]] to i64 +; CHECK-NEXT: [[TMP49:%.*]] = mul i64 [[TMP47]], [[TMP48]] +; CHECK-NEXT: [[TMP50:%.*]] = trunc i64 [[TMP49]] to i32 +; CHECK-NEXT: [[TMP51:%.*]] = lshr i64 [[TMP49]], 32 +; CHECK-NEXT: [[TMP52:%.*]] = trunc i64 [[TMP51]] to i32 +; CHECK-NEXT: [[TMP53:%.*]] = sub i32 0, [[TMP50]] +; CHECK-NEXT: [[TMP54:%.*]] = icmp eq i32 [[TMP52]], 0 +; CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP53]], i32 [[TMP50]] +; CHECK-NEXT: [[TMP56:%.*]] = zext i32 [[TMP55]] to i64 +; CHECK-NEXT: [[TMP57:%.*]] = zext i32 [[TMP46]] to i64 +; CHECK-NEXT: [[TMP58:%.*]] = mul i64 [[TMP56]], [[TMP57]] +; CHECK-NEXT: [[TMP59:%.*]] = trunc i64 [[TMP58]] to i32 +; CHECK-NEXT: [[TMP60:%.*]] = lshr i64 [[TMP58]], 32 +; CHECK-NEXT: [[TMP61:%.*]] = trunc i64 [[TMP60]] to i32 +; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP46]], [[TMP61]] +; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP46]], [[TMP61]] +; CHECK-NEXT: [[TMP64:%.*]] = select i1 [[TMP54]], i32 [[TMP62]], i32 [[TMP63]] +; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP64]] to i64 +; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP41]] to i64 +; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[TMP65]], [[TMP66]] +; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i32 +; CHECK-NEXT: [[TMP69:%.*]] = lshr i64 [[TMP67]], 32 +; CHECK-NEXT: [[TMP70:%.*]] = trunc i64 [[TMP69]] to i32 +; CHECK-NEXT: [[TMP71:%.*]] = mul i32 [[TMP70]], [[TMP42]] +; CHECK-NEXT: [[TMP72:%.*]] = sub i32 [[TMP41]], [[TMP71]] +; CHECK-NEXT: [[TMP73:%.*]] = icmp uge i32 [[TMP72]], [[TMP42]] +; CHECK-NEXT: [[TMP74:%.*]] = icmp uge i32 [[TMP41]], [[TMP71]] +; CHECK-NEXT: [[TMP75:%.*]] = and i1 [[TMP73]], [[TMP74]] +; CHECK-NEXT: [[TMP76:%.*]] = sub i32 [[TMP72]], [[TMP42]] +; CHECK-NEXT: [[TMP77:%.*]] = add i32 [[TMP72]], [[TMP42]] +; CHECK-NEXT: [[TMP78:%.*]] = select i1 [[TMP75]], i32 [[TMP76]], i32 [[TMP72]] +; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP74]], i32 [[TMP78]], i32 [[TMP77]] +; CHECK-NEXT: [[TMP80:%.*]] = insertelement <4 x i32> [[TMP40]], i32 [[TMP79]], i64 1 +; CHECK-NEXT: [[TMP81:%.*]] = extractelement <4 x i32> [[X]], i64 2 +; CHECK-NEXT: [[TMP82:%.*]] = extractelement <4 x i32> [[Y]], i64 2 +; CHECK-NEXT: [[TMP83:%.*]] = uitofp i32 [[TMP82]] to float +; CHECK-NEXT: [[TMP84:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP83]]) +; CHECK-NEXT: [[TMP85:%.*]] = fmul fast float [[TMP84]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP86:%.*]] = fptoui float [[TMP85]] to i32 +; CHECK-NEXT: [[TMP87:%.*]] = zext i32 [[TMP86]] to i64 +; CHECK-NEXT: [[TMP88:%.*]] = zext i32 [[TMP82]] to i64 +; CHECK-NEXT: [[TMP89:%.*]] = mul i64 [[TMP87]], [[TMP88]] +; CHECK-NEXT: [[TMP90:%.*]] = trunc i64 [[TMP89]] to i32 +; CHECK-NEXT: [[TMP91:%.*]] = lshr i64 [[TMP89]], 32 +; CHECK-NEXT: [[TMP92:%.*]] = trunc i64 [[TMP91]] to i32 +; CHECK-NEXT: [[TMP93:%.*]] = sub i32 0, [[TMP90]] +; CHECK-NEXT: [[TMP94:%.*]] = icmp eq i32 [[TMP92]], 0 +; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP94]], i32 [[TMP93]], i32 [[TMP90]] +; CHECK-NEXT: [[TMP96:%.*]] = zext i32 [[TMP95]] to i64 +; CHECK-NEXT: [[TMP97:%.*]] = zext i32 [[TMP86]] to i64 +; CHECK-NEXT: [[TMP98:%.*]] = mul i64 [[TMP96]], [[TMP97]] +; CHECK-NEXT: [[TMP99:%.*]] = trunc i64 [[TMP98]] to i32 +; CHECK-NEXT: [[TMP100:%.*]] = lshr i64 [[TMP98]], 32 +; CHECK-NEXT: [[TMP101:%.*]] = trunc i64 [[TMP100]] to i32 +; CHECK-NEXT: [[TMP102:%.*]] = add i32 [[TMP86]], [[TMP101]] +; CHECK-NEXT: [[TMP103:%.*]] = sub i32 [[TMP86]], [[TMP101]] +; CHECK-NEXT: [[TMP104:%.*]] = select i1 [[TMP94]], i32 [[TMP102]], i32 [[TMP103]] +; CHECK-NEXT: [[TMP105:%.*]] = zext i32 [[TMP104]] to i64 +; CHECK-NEXT: [[TMP106:%.*]] = zext i32 [[TMP81]] to i64 +; CHECK-NEXT: [[TMP107:%.*]] = mul i64 [[TMP105]], [[TMP106]] +; CHECK-NEXT: [[TMP108:%.*]] = trunc i64 [[TMP107]] to i32 +; CHECK-NEXT: [[TMP109:%.*]] = lshr i64 [[TMP107]], 32 +; CHECK-NEXT: [[TMP110:%.*]] = trunc i64 [[TMP109]] to i32 +; CHECK-NEXT: [[TMP111:%.*]] = mul i32 [[TMP110]], [[TMP82]] +; CHECK-NEXT: [[TMP112:%.*]] = sub i32 [[TMP81]], [[TMP111]] +; CHECK-NEXT: [[TMP113:%.*]] = icmp uge i32 [[TMP112]], [[TMP82]] +; CHECK-NEXT: [[TMP114:%.*]] = icmp uge i32 [[TMP81]], [[TMP111]] +; CHECK-NEXT: [[TMP115:%.*]] = and i1 [[TMP113]], [[TMP114]] +; CHECK-NEXT: [[TMP116:%.*]] = sub i32 [[TMP112]], [[TMP82]] +; CHECK-NEXT: [[TMP117:%.*]] = add i32 [[TMP112]], [[TMP82]] +; CHECK-NEXT: [[TMP118:%.*]] = select i1 [[TMP115]], i32 [[TMP116]], i32 [[TMP112]] +; CHECK-NEXT: [[TMP119:%.*]] = select i1 [[TMP114]], i32 [[TMP118]], i32 [[TMP117]] +; CHECK-NEXT: [[TMP120:%.*]] = insertelement <4 x i32> [[TMP80]], i32 [[TMP119]], i64 2 +; CHECK-NEXT: [[TMP121:%.*]] = extractelement <4 x i32> [[X]], i64 3 +; CHECK-NEXT: [[TMP122:%.*]] = extractelement <4 x i32> [[Y]], i64 3 +; CHECK-NEXT: [[TMP123:%.*]] = uitofp i32 [[TMP122]] to float +; CHECK-NEXT: [[TMP124:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP123]]) +; CHECK-NEXT: [[TMP125:%.*]] = fmul fast float [[TMP124]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP126:%.*]] = fptoui float [[TMP125]] to i32 +; CHECK-NEXT: [[TMP127:%.*]] = zext i32 [[TMP126]] to i64 +; CHECK-NEXT: [[TMP128:%.*]] = zext i32 [[TMP122]] to i64 +; CHECK-NEXT: [[TMP129:%.*]] = mul i64 [[TMP127]], [[TMP128]] +; CHECK-NEXT: [[TMP130:%.*]] = trunc i64 [[TMP129]] to i32 +; CHECK-NEXT: [[TMP131:%.*]] = lshr i64 [[TMP129]], 32 +; CHECK-NEXT: [[TMP132:%.*]] = trunc i64 [[TMP131]] to i32 +; CHECK-NEXT: [[TMP133:%.*]] = sub i32 0, [[TMP130]] +; CHECK-NEXT: [[TMP134:%.*]] = icmp eq i32 [[TMP132]], 0 +; CHECK-NEXT: [[TMP135:%.*]] = select i1 [[TMP134]], i32 [[TMP133]], i32 [[TMP130]] ; CHECK-NEXT: [[TMP136:%.*]] = zext i32 [[TMP135]] to i64 -; CHECK-NEXT: [[TMP137:%.*]] = zext i32 [[TMP131]] to i64 +; CHECK-NEXT: [[TMP137:%.*]] = zext i32 [[TMP126]] to i64 ; CHECK-NEXT: [[TMP138:%.*]] = mul i64 [[TMP136]], [[TMP137]] ; CHECK-NEXT: [[TMP139:%.*]] = trunc i64 [[TMP138]] to i32 ; CHECK-NEXT: [[TMP140:%.*]] = lshr i64 [[TMP138]], 32 ; CHECK-NEXT: [[TMP141:%.*]] = trunc i64 [[TMP140]] to i32 -; CHECK-NEXT: [[TMP142:%.*]] = sub i32 0, [[TMP139]] -; CHECK-NEXT: [[TMP143:%.*]] = icmp eq i32 [[TMP141]], 0 -; CHECK-NEXT: [[TMP144:%.*]] = select i1 [[TMP143]], i32 [[TMP142]], i32 [[TMP139]] +; CHECK-NEXT: [[TMP142:%.*]] = add i32 [[TMP126]], [[TMP141]] +; CHECK-NEXT: [[TMP143:%.*]] = sub i32 [[TMP126]], [[TMP141]] +; CHECK-NEXT: [[TMP144:%.*]] = select i1 [[TMP134]], i32 [[TMP142]], i32 [[TMP143]] ; CHECK-NEXT: [[TMP145:%.*]] = zext i32 [[TMP144]] to i64 -; CHECK-NEXT: [[TMP146:%.*]] = zext i32 [[TMP135]] to i64 +; CHECK-NEXT: [[TMP146:%.*]] = zext i32 [[TMP121]] to i64 ; CHECK-NEXT: [[TMP147:%.*]] = mul i64 [[TMP145]], [[TMP146]] ; CHECK-NEXT: [[TMP148:%.*]] = trunc i64 [[TMP147]] to i32 ; CHECK-NEXT: [[TMP149:%.*]] = lshr i64 [[TMP147]], 32 ; CHECK-NEXT: [[TMP150:%.*]] = trunc i64 [[TMP149]] to i32 -; CHECK-NEXT: [[TMP151:%.*]] = add i32 [[TMP135]], [[TMP150]] -; CHECK-NEXT: [[TMP152:%.*]] = sub i32 [[TMP135]], [[TMP150]] -; CHECK-NEXT: [[TMP153:%.*]] = select i1 [[TMP143]], i32 [[TMP151]], i32 [[TMP152]] -; CHECK-NEXT: [[TMP154:%.*]] = zext i32 [[TMP153]] to i64 -; CHECK-NEXT: [[TMP155:%.*]] = zext i32 [[TMP130]] to i64 -; CHECK-NEXT: [[TMP156:%.*]] = mul i64 [[TMP154]], [[TMP155]] -; CHECK-NEXT: [[TMP157:%.*]] = trunc i64 [[TMP156]] to i32 -; CHECK-NEXT: [[TMP158:%.*]] = lshr i64 [[TMP156]], 32 -; CHECK-NEXT: [[TMP159:%.*]] = trunc i64 [[TMP158]] to i32 -; CHECK-NEXT: [[TMP160:%.*]] = mul i32 [[TMP159]], [[TMP131]] -; CHECK-NEXT: [[TMP161:%.*]] = sub i32 [[TMP130]], [[TMP160]] -; CHECK-NEXT: [[TMP162:%.*]] = icmp uge i32 [[TMP161]], [[TMP131]] -; CHECK-NEXT: [[TMP163:%.*]] = select i1 [[TMP162]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP164:%.*]] = icmp uge i32 [[TMP130]], [[TMP160]] -; CHECK-NEXT: [[TMP165:%.*]] = select i1 [[TMP164]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP166:%.*]] = and i32 [[TMP163]], [[TMP165]] -; CHECK-NEXT: [[TMP167:%.*]] = icmp eq i32 [[TMP166]], 0 -; CHECK-NEXT: [[TMP168:%.*]] = sub i32 [[TMP161]], [[TMP131]] -; CHECK-NEXT: [[TMP169:%.*]] = add i32 [[TMP161]], [[TMP131]] -; CHECK-NEXT: [[TMP170:%.*]] = select i1 [[TMP167]], i32 [[TMP161]], i32 [[TMP168]] -; CHECK-NEXT: [[TMP171:%.*]] = select i1 [[TMP164]], i32 [[TMP170]], i32 [[TMP169]] -; CHECK-NEXT: [[TMP172:%.*]] = insertelement <4 x i32> [[TMP129]], i32 [[TMP171]], i64 3 -; CHECK-NEXT: store <4 x i32> [[TMP172]], <4 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP151:%.*]] = mul i32 [[TMP150]], [[TMP122]] +; CHECK-NEXT: [[TMP152:%.*]] = sub i32 [[TMP121]], [[TMP151]] +; CHECK-NEXT: [[TMP153:%.*]] = icmp uge i32 [[TMP152]], [[TMP122]] +; CHECK-NEXT: [[TMP154:%.*]] = icmp uge i32 [[TMP121]], [[TMP151]] +; CHECK-NEXT: [[TMP155:%.*]] = and i1 [[TMP153]], [[TMP154]] +; CHECK-NEXT: [[TMP156:%.*]] = sub i32 [[TMP152]], [[TMP122]] +; CHECK-NEXT: [[TMP157:%.*]] = add i32 [[TMP152]], [[TMP122]] +; CHECK-NEXT: [[TMP158:%.*]] = select i1 [[TMP155]], i32 [[TMP156]], i32 [[TMP152]] +; CHECK-NEXT: [[TMP159:%.*]] = select i1 [[TMP154]], i32 [[TMP158]], i32 [[TMP157]] +; CHECK-NEXT: [[TMP160:%.*]] = insertelement <4 x i32> [[TMP120]], i32 [[TMP159]], i64 3 +; CHECK-NEXT: store <4 x i32> [[TMP160]], <4 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: urem_v4i32: @@ -1402,175 +1366,163 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP9]] ; CHECK-NEXT: [[TMP39:%.*]] = sub i32 [[TMP8]], [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = icmp uge i32 [[TMP39]], [[TMP9]] -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP42:%.*]] = icmp uge i32 [[TMP8]], [[TMP38]] -; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP44:%.*]] = and i32 [[TMP41]], [[TMP43]] -; CHECK-NEXT: [[TMP45:%.*]] = icmp eq i32 [[TMP44]], 0 -; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP37]], 1 -; CHECK-NEXT: [[TMP47:%.*]] = sub i32 [[TMP37]], 1 -; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP45]], i32 [[TMP37]], i32 [[TMP46]] -; CHECK-NEXT: [[TMP49:%.*]] = select i1 [[TMP42]], i32 [[TMP48]], i32 [[TMP47]] -; CHECK-NEXT: [[TMP50:%.*]] = xor i32 [[TMP49]], [[TMP5]] -; CHECK-NEXT: [[TMP51:%.*]] = sub i32 [[TMP50]], [[TMP5]] -; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i32> undef, i32 [[TMP51]], i64 0 -; CHECK-NEXT: [[TMP53:%.*]] = extractelement <4 x i32> [[X]], i64 1 -; CHECK-NEXT: [[TMP54:%.*]] = extractelement <4 x i32> [[Y]], i64 1 -; CHECK-NEXT: [[TMP55:%.*]] = ashr i32 [[TMP53]], 31 -; CHECK-NEXT: [[TMP56:%.*]] = ashr i32 [[TMP54]], 31 -; CHECK-NEXT: [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]] -; CHECK-NEXT: [[TMP58:%.*]] = add i32 [[TMP53]], [[TMP55]] -; CHECK-NEXT: [[TMP59:%.*]] = add i32 [[TMP54]], [[TMP56]] -; CHECK-NEXT: [[TMP60:%.*]] = xor i32 [[TMP58]], [[TMP55]] -; CHECK-NEXT: [[TMP61:%.*]] = xor i32 [[TMP59]], [[TMP56]] -; CHECK-NEXT: [[TMP62:%.*]] = uitofp i32 [[TMP61]] to float -; CHECK-NEXT: [[TMP63:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP62]]) -; CHECK-NEXT: [[TMP64:%.*]] = fmul fast float [[TMP63]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP65:%.*]] = fptoui float [[TMP64]] to i32 -; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP65]] to i64 -; CHECK-NEXT: [[TMP67:%.*]] = zext i32 [[TMP61]] to i64 -; CHECK-NEXT: [[TMP68:%.*]] = mul i64 [[TMP66]], [[TMP67]] -; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32 -; CHECK-NEXT: [[TMP70:%.*]] = lshr i64 [[TMP68]], 32 -; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 -; CHECK-NEXT: [[TMP72:%.*]] = sub i32 0, [[TMP69]] -; CHECK-NEXT: [[TMP73:%.*]] = icmp eq i32 [[TMP71]], 0 -; CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP73]], i32 [[TMP72]], i32 [[TMP69]] -; CHECK-NEXT: [[TMP75:%.*]] = zext i32 [[TMP74]] to i64 -; CHECK-NEXT: [[TMP76:%.*]] = zext i32 [[TMP65]] to i64 -; CHECK-NEXT: [[TMP77:%.*]] = mul i64 [[TMP75]], [[TMP76]] -; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32 -; CHECK-NEXT: [[TMP79:%.*]] = lshr i64 [[TMP77]], 32 -; CHECK-NEXT: [[TMP80:%.*]] = trunc i64 [[TMP79]] to i32 -; CHECK-NEXT: [[TMP81:%.*]] = add i32 [[TMP65]], [[TMP80]] -; CHECK-NEXT: [[TMP82:%.*]] = sub i32 [[TMP65]], [[TMP80]] -; CHECK-NEXT: [[TMP83:%.*]] = select i1 [[TMP73]], i32 [[TMP81]], i32 [[TMP82]] -; CHECK-NEXT: [[TMP84:%.*]] = zext i32 [[TMP83]] to i64 -; CHECK-NEXT: [[TMP85:%.*]] = zext i32 [[TMP60]] to i64 -; CHECK-NEXT: [[TMP86:%.*]] = mul i64 [[TMP84]], [[TMP85]] -; CHECK-NEXT: [[TMP87:%.*]] = trunc i64 [[TMP86]] to i32 -; CHECK-NEXT: [[TMP88:%.*]] = lshr i64 [[TMP86]], 32 -; CHECK-NEXT: [[TMP89:%.*]] = trunc i64 [[TMP88]] to i32 -; CHECK-NEXT: [[TMP90:%.*]] = mul i32 [[TMP89]], [[TMP61]] -; CHECK-NEXT: [[TMP91:%.*]] = sub i32 [[TMP60]], [[TMP90]] -; CHECK-NEXT: [[TMP92:%.*]] = icmp uge i32 [[TMP91]], [[TMP61]] -; CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP94:%.*]] = icmp uge i32 [[TMP60]], [[TMP90]] -; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP94]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP96:%.*]] = and i32 [[TMP93]], [[TMP95]] -; CHECK-NEXT: [[TMP97:%.*]] = icmp eq i32 [[TMP96]], 0 -; CHECK-NEXT: [[TMP98:%.*]] = add i32 [[TMP89]], 1 -; CHECK-NEXT: [[TMP99:%.*]] = sub i32 [[TMP89]], 1 -; CHECK-NEXT: [[TMP100:%.*]] = select i1 [[TMP97]], i32 [[TMP89]], i32 [[TMP98]] -; CHECK-NEXT: [[TMP101:%.*]] = select i1 [[TMP94]], i32 [[TMP100]], i32 [[TMP99]] -; CHECK-NEXT: [[TMP102:%.*]] = xor i32 [[TMP101]], [[TMP57]] -; CHECK-NEXT: [[TMP103:%.*]] = sub i32 [[TMP102]], [[TMP57]] -; CHECK-NEXT: [[TMP104:%.*]] = insertelement <4 x i32> [[TMP52]], i32 [[TMP103]], i64 1 -; CHECK-NEXT: [[TMP105:%.*]] = extractelement <4 x i32> [[X]], i64 2 -; CHECK-NEXT: [[TMP106:%.*]] = extractelement <4 x i32> [[Y]], i64 2 -; CHECK-NEXT: [[TMP107:%.*]] = ashr i32 [[TMP105]], 31 -; CHECK-NEXT: [[TMP108:%.*]] = ashr i32 [[TMP106]], 31 -; CHECK-NEXT: [[TMP109:%.*]] = xor i32 [[TMP107]], [[TMP108]] -; CHECK-NEXT: [[TMP110:%.*]] = add i32 [[TMP105]], [[TMP107]] -; CHECK-NEXT: [[TMP111:%.*]] = add i32 [[TMP106]], [[TMP108]] -; CHECK-NEXT: [[TMP112:%.*]] = xor i32 [[TMP110]], [[TMP107]] -; CHECK-NEXT: [[TMP113:%.*]] = xor i32 [[TMP111]], [[TMP108]] -; CHECK-NEXT: [[TMP114:%.*]] = uitofp i32 [[TMP113]] to float -; CHECK-NEXT: [[TMP115:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP114]]) -; CHECK-NEXT: [[TMP116:%.*]] = fmul fast float [[TMP115]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP117:%.*]] = fptoui float [[TMP116]] to i32 -; CHECK-NEXT: [[TMP118:%.*]] = zext i32 [[TMP117]] to i64 -; CHECK-NEXT: [[TMP119:%.*]] = zext i32 [[TMP113]] to i64 -; CHECK-NEXT: [[TMP120:%.*]] = mul i64 [[TMP118]], [[TMP119]] -; CHECK-NEXT: [[TMP121:%.*]] = trunc i64 [[TMP120]] to i32 -; CHECK-NEXT: [[TMP122:%.*]] = lshr i64 [[TMP120]], 32 -; CHECK-NEXT: [[TMP123:%.*]] = trunc i64 [[TMP122]] to i32 -; CHECK-NEXT: [[TMP124:%.*]] = sub i32 0, [[TMP121]] -; CHECK-NEXT: [[TMP125:%.*]] = icmp eq i32 [[TMP123]], 0 -; CHECK-NEXT: [[TMP126:%.*]] = select i1 [[TMP125]], i32 [[TMP124]], i32 [[TMP121]] -; CHECK-NEXT: [[TMP127:%.*]] = zext i32 [[TMP126]] to i64 -; CHECK-NEXT: [[TMP128:%.*]] = zext i32 [[TMP117]] to i64 -; CHECK-NEXT: [[TMP129:%.*]] = mul i64 [[TMP127]], [[TMP128]] -; CHECK-NEXT: [[TMP130:%.*]] = trunc i64 [[TMP129]] to i32 -; CHECK-NEXT: [[TMP131:%.*]] = lshr i64 [[TMP129]], 32 -; CHECK-NEXT: [[TMP132:%.*]] = trunc i64 [[TMP131]] to i32 -; CHECK-NEXT: [[TMP133:%.*]] = add i32 [[TMP117]], [[TMP132]] -; CHECK-NEXT: [[TMP134:%.*]] = sub i32 [[TMP117]], [[TMP132]] -; CHECK-NEXT: [[TMP135:%.*]] = select i1 [[TMP125]], i32 [[TMP133]], i32 [[TMP134]] -; CHECK-NEXT: [[TMP136:%.*]] = zext i32 [[TMP135]] to i64 -; CHECK-NEXT: [[TMP137:%.*]] = zext i32 [[TMP112]] to i64 -; CHECK-NEXT: [[TMP138:%.*]] = mul i64 [[TMP136]], [[TMP137]] -; CHECK-NEXT: [[TMP139:%.*]] = trunc i64 [[TMP138]] to i32 -; CHECK-NEXT: [[TMP140:%.*]] = lshr i64 [[TMP138]], 32 -; CHECK-NEXT: [[TMP141:%.*]] = trunc i64 [[TMP140]] to i32 -; CHECK-NEXT: [[TMP142:%.*]] = mul i32 [[TMP141]], [[TMP113]] -; CHECK-NEXT: [[TMP143:%.*]] = sub i32 [[TMP112]], [[TMP142]] -; CHECK-NEXT: [[TMP144:%.*]] = icmp uge i32 [[TMP143]], [[TMP113]] -; CHECK-NEXT: [[TMP145:%.*]] = select i1 [[TMP144]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP146:%.*]] = icmp uge i32 [[TMP112]], [[TMP142]] -; CHECK-NEXT: [[TMP147:%.*]] = select i1 [[TMP146]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP148:%.*]] = and i32 [[TMP145]], [[TMP147]] -; CHECK-NEXT: [[TMP149:%.*]] = icmp eq i32 [[TMP148]], 0 -; CHECK-NEXT: [[TMP150:%.*]] = add i32 [[TMP141]], 1 -; CHECK-NEXT: [[TMP151:%.*]] = sub i32 [[TMP141]], 1 -; CHECK-NEXT: [[TMP152:%.*]] = select i1 [[TMP149]], i32 [[TMP141]], i32 [[TMP150]] -; CHECK-NEXT: [[TMP153:%.*]] = select i1 [[TMP146]], i32 [[TMP152]], i32 [[TMP151]] -; CHECK-NEXT: [[TMP154:%.*]] = xor i32 [[TMP153]], [[TMP109]] -; CHECK-NEXT: [[TMP155:%.*]] = sub i32 [[TMP154]], [[TMP109]] -; CHECK-NEXT: [[TMP156:%.*]] = insertelement <4 x i32> [[TMP104]], i32 [[TMP155]], i64 2 -; CHECK-NEXT: [[TMP157:%.*]] = extractelement <4 x i32> [[X]], i64 3 -; CHECK-NEXT: [[TMP158:%.*]] = extractelement <4 x i32> [[Y]], i64 3 -; CHECK-NEXT: [[TMP159:%.*]] = ashr i32 [[TMP157]], 31 -; CHECK-NEXT: [[TMP160:%.*]] = ashr i32 [[TMP158]], 31 -; CHECK-NEXT: [[TMP161:%.*]] = xor i32 [[TMP159]], [[TMP160]] -; CHECK-NEXT: [[TMP162:%.*]] = add i32 [[TMP157]], [[TMP159]] -; CHECK-NEXT: [[TMP163:%.*]] = add i32 [[TMP158]], [[TMP160]] -; CHECK-NEXT: [[TMP164:%.*]] = xor i32 [[TMP162]], [[TMP159]] -; CHECK-NEXT: [[TMP165:%.*]] = xor i32 [[TMP163]], [[TMP160]] -; CHECK-NEXT: [[TMP166:%.*]] = uitofp i32 [[TMP165]] to float -; CHECK-NEXT: [[TMP167:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP166]]) -; CHECK-NEXT: [[TMP168:%.*]] = fmul fast float [[TMP167]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP169:%.*]] = fptoui float [[TMP168]] to i32 +; CHECK-NEXT: [[TMP41:%.*]] = icmp uge i32 [[TMP8]], [[TMP38]] +; CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP40]], [[TMP41]] +; CHECK-NEXT: [[TMP43:%.*]] = add i32 [[TMP37]], 1 +; CHECK-NEXT: [[TMP44:%.*]] = sub i32 [[TMP37]], 1 +; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP42]], i32 [[TMP43]], i32 [[TMP37]] +; CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP41]], i32 [[TMP45]], i32 [[TMP44]] +; CHECK-NEXT: [[TMP47:%.*]] = xor i32 [[TMP46]], [[TMP5]] +; CHECK-NEXT: [[TMP48:%.*]] = sub i32 [[TMP47]], [[TMP5]] +; CHECK-NEXT: [[TMP49:%.*]] = insertelement <4 x i32> undef, i32 [[TMP48]], i64 0 +; CHECK-NEXT: [[TMP50:%.*]] = extractelement <4 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP51:%.*]] = extractelement <4 x i32> [[Y]], i64 1 +; CHECK-NEXT: [[TMP52:%.*]] = ashr i32 [[TMP50]], 31 +; CHECK-NEXT: [[TMP53:%.*]] = ashr i32 [[TMP51]], 31 +; CHECK-NEXT: [[TMP54:%.*]] = xor i32 [[TMP52]], [[TMP53]] +; CHECK-NEXT: [[TMP55:%.*]] = add i32 [[TMP50]], [[TMP52]] +; CHECK-NEXT: [[TMP56:%.*]] = add i32 [[TMP51]], [[TMP53]] +; CHECK-NEXT: [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP52]] +; CHECK-NEXT: [[TMP58:%.*]] = xor i32 [[TMP56]], [[TMP53]] +; CHECK-NEXT: [[TMP59:%.*]] = uitofp i32 [[TMP58]] to float +; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP59]]) +; CHECK-NEXT: [[TMP61:%.*]] = fmul fast float [[TMP60]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP62:%.*]] = fptoui float [[TMP61]] to i32 +; CHECK-NEXT: [[TMP63:%.*]] = zext i32 [[TMP62]] to i64 +; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[TMP58]] to i64 +; CHECK-NEXT: [[TMP65:%.*]] = mul i64 [[TMP63]], [[TMP64]] +; CHECK-NEXT: [[TMP66:%.*]] = trunc i64 [[TMP65]] to i32 +; CHECK-NEXT: [[TMP67:%.*]] = lshr i64 [[TMP65]], 32 +; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i32 +; CHECK-NEXT: [[TMP69:%.*]] = sub i32 0, [[TMP66]] +; CHECK-NEXT: [[TMP70:%.*]] = icmp eq i32 [[TMP68]], 0 +; CHECK-NEXT: [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP69]], i32 [[TMP66]] +; CHECK-NEXT: [[TMP72:%.*]] = zext i32 [[TMP71]] to i64 +; CHECK-NEXT: [[TMP73:%.*]] = zext i32 [[TMP62]] to i64 +; CHECK-NEXT: [[TMP74:%.*]] = mul i64 [[TMP72]], [[TMP73]] +; CHECK-NEXT: [[TMP75:%.*]] = trunc i64 [[TMP74]] to i32 +; CHECK-NEXT: [[TMP76:%.*]] = lshr i64 [[TMP74]], 32 +; CHECK-NEXT: [[TMP77:%.*]] = trunc i64 [[TMP76]] to i32 +; CHECK-NEXT: [[TMP78:%.*]] = add i32 [[TMP62]], [[TMP77]] +; CHECK-NEXT: [[TMP79:%.*]] = sub i32 [[TMP62]], [[TMP77]] +; CHECK-NEXT: [[TMP80:%.*]] = select i1 [[TMP70]], i32 [[TMP78]], i32 [[TMP79]] +; CHECK-NEXT: [[TMP81:%.*]] = zext i32 [[TMP80]] to i64 +; CHECK-NEXT: [[TMP82:%.*]] = zext i32 [[TMP57]] to i64 +; CHECK-NEXT: [[TMP83:%.*]] = mul i64 [[TMP81]], [[TMP82]] +; CHECK-NEXT: [[TMP84:%.*]] = trunc i64 [[TMP83]] to i32 +; CHECK-NEXT: [[TMP85:%.*]] = lshr i64 [[TMP83]], 32 +; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i32 +; CHECK-NEXT: [[TMP87:%.*]] = mul i32 [[TMP86]], [[TMP58]] +; CHECK-NEXT: [[TMP88:%.*]] = sub i32 [[TMP57]], [[TMP87]] +; CHECK-NEXT: [[TMP89:%.*]] = icmp uge i32 [[TMP88]], [[TMP58]] +; CHECK-NEXT: [[TMP90:%.*]] = icmp uge i32 [[TMP57]], [[TMP87]] +; CHECK-NEXT: [[TMP91:%.*]] = and i1 [[TMP89]], [[TMP90]] +; CHECK-NEXT: [[TMP92:%.*]] = add i32 [[TMP86]], 1 +; CHECK-NEXT: [[TMP93:%.*]] = sub i32 [[TMP86]], 1 +; CHECK-NEXT: [[TMP94:%.*]] = select i1 [[TMP91]], i32 [[TMP92]], i32 [[TMP86]] +; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP90]], i32 [[TMP94]], i32 [[TMP93]] +; CHECK-NEXT: [[TMP96:%.*]] = xor i32 [[TMP95]], [[TMP54]] +; CHECK-NEXT: [[TMP97:%.*]] = sub i32 [[TMP96]], [[TMP54]] +; CHECK-NEXT: [[TMP98:%.*]] = insertelement <4 x i32> [[TMP49]], i32 [[TMP97]], i64 1 +; CHECK-NEXT: [[TMP99:%.*]] = extractelement <4 x i32> [[X]], i64 2 +; CHECK-NEXT: [[TMP100:%.*]] = extractelement <4 x i32> [[Y]], i64 2 +; CHECK-NEXT: [[TMP101:%.*]] = ashr i32 [[TMP99]], 31 +; CHECK-NEXT: [[TMP102:%.*]] = ashr i32 [[TMP100]], 31 +; CHECK-NEXT: [[TMP103:%.*]] = xor i32 [[TMP101]], [[TMP102]] +; CHECK-NEXT: [[TMP104:%.*]] = add i32 [[TMP99]], [[TMP101]] +; CHECK-NEXT: [[TMP105:%.*]] = add i32 [[TMP100]], [[TMP102]] +; CHECK-NEXT: [[TMP106:%.*]] = xor i32 [[TMP104]], [[TMP101]] +; CHECK-NEXT: [[TMP107:%.*]] = xor i32 [[TMP105]], [[TMP102]] +; CHECK-NEXT: [[TMP108:%.*]] = uitofp i32 [[TMP107]] to float +; CHECK-NEXT: [[TMP109:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP108]]) +; CHECK-NEXT: [[TMP110:%.*]] = fmul fast float [[TMP109]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP111:%.*]] = fptoui float [[TMP110]] to i32 +; CHECK-NEXT: [[TMP112:%.*]] = zext i32 [[TMP111]] to i64 +; CHECK-NEXT: [[TMP113:%.*]] = zext i32 [[TMP107]] to i64 +; CHECK-NEXT: [[TMP114:%.*]] = mul i64 [[TMP112]], [[TMP113]] +; CHECK-NEXT: [[TMP115:%.*]] = trunc i64 [[TMP114]] to i32 +; CHECK-NEXT: [[TMP116:%.*]] = lshr i64 [[TMP114]], 32 +; CHECK-NEXT: [[TMP117:%.*]] = trunc i64 [[TMP116]] to i32 +; CHECK-NEXT: [[TMP118:%.*]] = sub i32 0, [[TMP115]] +; CHECK-NEXT: [[TMP119:%.*]] = icmp eq i32 [[TMP117]], 0 +; CHECK-NEXT: [[TMP120:%.*]] = select i1 [[TMP119]], i32 [[TMP118]], i32 [[TMP115]] +; CHECK-NEXT: [[TMP121:%.*]] = zext i32 [[TMP120]] to i64 +; CHECK-NEXT: [[TMP122:%.*]] = zext i32 [[TMP111]] to i64 +; CHECK-NEXT: [[TMP123:%.*]] = mul i64 [[TMP121]], [[TMP122]] +; CHECK-NEXT: [[TMP124:%.*]] = trunc i64 [[TMP123]] to i32 +; CHECK-NEXT: [[TMP125:%.*]] = lshr i64 [[TMP123]], 32 +; CHECK-NEXT: [[TMP126:%.*]] = trunc i64 [[TMP125]] to i32 +; CHECK-NEXT: [[TMP127:%.*]] = add i32 [[TMP111]], [[TMP126]] +; CHECK-NEXT: [[TMP128:%.*]] = sub i32 [[TMP111]], [[TMP126]] +; CHECK-NEXT: [[TMP129:%.*]] = select i1 [[TMP119]], i32 [[TMP127]], i32 [[TMP128]] +; CHECK-NEXT: [[TMP130:%.*]] = zext i32 [[TMP129]] to i64 +; CHECK-NEXT: [[TMP131:%.*]] = zext i32 [[TMP106]] to i64 +; CHECK-NEXT: [[TMP132:%.*]] = mul i64 [[TMP130]], [[TMP131]] +; CHECK-NEXT: [[TMP133:%.*]] = trunc i64 [[TMP132]] to i32 +; CHECK-NEXT: [[TMP134:%.*]] = lshr i64 [[TMP132]], 32 +; CHECK-NEXT: [[TMP135:%.*]] = trunc i64 [[TMP134]] to i32 +; CHECK-NEXT: [[TMP136:%.*]] = mul i32 [[TMP135]], [[TMP107]] +; CHECK-NEXT: [[TMP137:%.*]] = sub i32 [[TMP106]], [[TMP136]] +; CHECK-NEXT: [[TMP138:%.*]] = icmp uge i32 [[TMP137]], [[TMP107]] +; CHECK-NEXT: [[TMP139:%.*]] = icmp uge i32 [[TMP106]], [[TMP136]] +; CHECK-NEXT: [[TMP140:%.*]] = and i1 [[TMP138]], [[TMP139]] +; CHECK-NEXT: [[TMP141:%.*]] = add i32 [[TMP135]], 1 +; CHECK-NEXT: [[TMP142:%.*]] = sub i32 [[TMP135]], 1 +; CHECK-NEXT: [[TMP143:%.*]] = select i1 [[TMP140]], i32 [[TMP141]], i32 [[TMP135]] +; CHECK-NEXT: [[TMP144:%.*]] = select i1 [[TMP139]], i32 [[TMP143]], i32 [[TMP142]] +; CHECK-NEXT: [[TMP145:%.*]] = xor i32 [[TMP144]], [[TMP103]] +; CHECK-NEXT: [[TMP146:%.*]] = sub i32 [[TMP145]], [[TMP103]] +; CHECK-NEXT: [[TMP147:%.*]] = insertelement <4 x i32> [[TMP98]], i32 [[TMP146]], i64 2 +; CHECK-NEXT: [[TMP148:%.*]] = extractelement <4 x i32> [[X]], i64 3 +; CHECK-NEXT: [[TMP149:%.*]] = extractelement <4 x i32> [[Y]], i64 3 +; CHECK-NEXT: [[TMP150:%.*]] = ashr i32 [[TMP148]], 31 +; CHECK-NEXT: [[TMP151:%.*]] = ashr i32 [[TMP149]], 31 +; CHECK-NEXT: [[TMP152:%.*]] = xor i32 [[TMP150]], [[TMP151]] +; CHECK-NEXT: [[TMP153:%.*]] = add i32 [[TMP148]], [[TMP150]] +; CHECK-NEXT: [[TMP154:%.*]] = add i32 [[TMP149]], [[TMP151]] +; CHECK-NEXT: [[TMP155:%.*]] = xor i32 [[TMP153]], [[TMP150]] +; CHECK-NEXT: [[TMP156:%.*]] = xor i32 [[TMP154]], [[TMP151]] +; CHECK-NEXT: [[TMP157:%.*]] = uitofp i32 [[TMP156]] to float +; CHECK-NEXT: [[TMP158:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP157]]) +; CHECK-NEXT: [[TMP159:%.*]] = fmul fast float [[TMP158]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP160:%.*]] = fptoui float [[TMP159]] to i32 +; CHECK-NEXT: [[TMP161:%.*]] = zext i32 [[TMP160]] to i64 +; CHECK-NEXT: [[TMP162:%.*]] = zext i32 [[TMP156]] to i64 +; CHECK-NEXT: [[TMP163:%.*]] = mul i64 [[TMP161]], [[TMP162]] +; CHECK-NEXT: [[TMP164:%.*]] = trunc i64 [[TMP163]] to i32 +; CHECK-NEXT: [[TMP165:%.*]] = lshr i64 [[TMP163]], 32 +; CHECK-NEXT: [[TMP166:%.*]] = trunc i64 [[TMP165]] to i32 +; CHECK-NEXT: [[TMP167:%.*]] = sub i32 0, [[TMP164]] +; CHECK-NEXT: [[TMP168:%.*]] = icmp eq i32 [[TMP166]], 0 +; CHECK-NEXT: [[TMP169:%.*]] = select i1 [[TMP168]], i32 [[TMP167]], i32 [[TMP164]] ; CHECK-NEXT: [[TMP170:%.*]] = zext i32 [[TMP169]] to i64 -; CHECK-NEXT: [[TMP171:%.*]] = zext i32 [[TMP165]] to i64 +; CHECK-NEXT: [[TMP171:%.*]] = zext i32 [[TMP160]] to i64 ; CHECK-NEXT: [[TMP172:%.*]] = mul i64 [[TMP170]], [[TMP171]] ; CHECK-NEXT: [[TMP173:%.*]] = trunc i64 [[TMP172]] to i32 ; CHECK-NEXT: [[TMP174:%.*]] = lshr i64 [[TMP172]], 32 ; CHECK-NEXT: [[TMP175:%.*]] = trunc i64 [[TMP174]] to i32 -; CHECK-NEXT: [[TMP176:%.*]] = sub i32 0, [[TMP173]] -; CHECK-NEXT: [[TMP177:%.*]] = icmp eq i32 [[TMP175]], 0 -; CHECK-NEXT: [[TMP178:%.*]] = select i1 [[TMP177]], i32 [[TMP176]], i32 [[TMP173]] +; CHECK-NEXT: [[TMP176:%.*]] = add i32 [[TMP160]], [[TMP175]] +; CHECK-NEXT: [[TMP177:%.*]] = sub i32 [[TMP160]], [[TMP175]] +; CHECK-NEXT: [[TMP178:%.*]] = select i1 [[TMP168]], i32 [[TMP176]], i32 [[TMP177]] ; CHECK-NEXT: [[TMP179:%.*]] = zext i32 [[TMP178]] to i64 -; CHECK-NEXT: [[TMP180:%.*]] = zext i32 [[TMP169]] to i64 +; CHECK-NEXT: [[TMP180:%.*]] = zext i32 [[TMP155]] to i64 ; CHECK-NEXT: [[TMP181:%.*]] = mul i64 [[TMP179]], [[TMP180]] ; CHECK-NEXT: [[TMP182:%.*]] = trunc i64 [[TMP181]] to i32 ; CHECK-NEXT: [[TMP183:%.*]] = lshr i64 [[TMP181]], 32 ; CHECK-NEXT: [[TMP184:%.*]] = trunc i64 [[TMP183]] to i32 -; CHECK-NEXT: [[TMP185:%.*]] = add i32 [[TMP169]], [[TMP184]] -; CHECK-NEXT: [[TMP186:%.*]] = sub i32 [[TMP169]], [[TMP184]] -; CHECK-NEXT: [[TMP187:%.*]] = select i1 [[TMP177]], i32 [[TMP185]], i32 [[TMP186]] -; CHECK-NEXT: [[TMP188:%.*]] = zext i32 [[TMP187]] to i64 -; CHECK-NEXT: [[TMP189:%.*]] = zext i32 [[TMP164]] to i64 -; CHECK-NEXT: [[TMP190:%.*]] = mul i64 [[TMP188]], [[TMP189]] -; CHECK-NEXT: [[TMP191:%.*]] = trunc i64 [[TMP190]] to i32 -; CHECK-NEXT: [[TMP192:%.*]] = lshr i64 [[TMP190]], 32 -; CHECK-NEXT: [[TMP193:%.*]] = trunc i64 [[TMP192]] to i32 -; CHECK-NEXT: [[TMP194:%.*]] = mul i32 [[TMP193]], [[TMP165]] -; CHECK-NEXT: [[TMP195:%.*]] = sub i32 [[TMP164]], [[TMP194]] -; CHECK-NEXT: [[TMP196:%.*]] = icmp uge i32 [[TMP195]], [[TMP165]] -; CHECK-NEXT: [[TMP197:%.*]] = select i1 [[TMP196]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP198:%.*]] = icmp uge i32 [[TMP164]], [[TMP194]] -; CHECK-NEXT: [[TMP199:%.*]] = select i1 [[TMP198]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP200:%.*]] = and i32 [[TMP197]], [[TMP199]] -; CHECK-NEXT: [[TMP201:%.*]] = icmp eq i32 [[TMP200]], 0 -; CHECK-NEXT: [[TMP202:%.*]] = add i32 [[TMP193]], 1 -; CHECK-NEXT: [[TMP203:%.*]] = sub i32 [[TMP193]], 1 -; CHECK-NEXT: [[TMP204:%.*]] = select i1 [[TMP201]], i32 [[TMP193]], i32 [[TMP202]] -; CHECK-NEXT: [[TMP205:%.*]] = select i1 [[TMP198]], i32 [[TMP204]], i32 [[TMP203]] -; CHECK-NEXT: [[TMP206:%.*]] = xor i32 [[TMP205]], [[TMP161]] -; CHECK-NEXT: [[TMP207:%.*]] = sub i32 [[TMP206]], [[TMP161]] -; CHECK-NEXT: [[TMP208:%.*]] = insertelement <4 x i32> [[TMP156]], i32 [[TMP207]], i64 3 -; CHECK-NEXT: store <4 x i32> [[TMP208]], <4 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP185:%.*]] = mul i32 [[TMP184]], [[TMP156]] +; CHECK-NEXT: [[TMP186:%.*]] = sub i32 [[TMP155]], [[TMP185]] +; CHECK-NEXT: [[TMP187:%.*]] = icmp uge i32 [[TMP186]], [[TMP156]] +; CHECK-NEXT: [[TMP188:%.*]] = icmp uge i32 [[TMP155]], [[TMP185]] +; CHECK-NEXT: [[TMP189:%.*]] = and i1 [[TMP187]], [[TMP188]] +; CHECK-NEXT: [[TMP190:%.*]] = add i32 [[TMP184]], 1 +; CHECK-NEXT: [[TMP191:%.*]] = sub i32 [[TMP184]], 1 +; CHECK-NEXT: [[TMP192:%.*]] = select i1 [[TMP189]], i32 [[TMP190]], i32 [[TMP184]] +; CHECK-NEXT: [[TMP193:%.*]] = select i1 [[TMP188]], i32 [[TMP192]], i32 [[TMP191]] +; CHECK-NEXT: [[TMP194:%.*]] = xor i32 [[TMP193]], [[TMP152]] +; CHECK-NEXT: [[TMP195:%.*]] = sub i32 [[TMP194]], [[TMP152]] +; CHECK-NEXT: [[TMP196:%.*]] = insertelement <4 x i32> [[TMP147]], i32 [[TMP195]], i64 3 +; CHECK-NEXT: store <4 x i32> [[TMP196]], <4 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: sdiv_v4i32: @@ -1757,172 +1709,160 @@ define amdgpu_kernel void @srem_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %x ; CHECK-NEXT: [[TMP37:%.*]] = mul i32 [[TMP36]], [[TMP8]] ; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP7]], [[TMP37]] ; CHECK-NEXT: [[TMP39:%.*]] = icmp uge i32 [[TMP38]], [[TMP8]] -; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP39]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP41:%.*]] = icmp uge i32 [[TMP7]], [[TMP37]] -; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP43:%.*]] = and i32 [[TMP40]], [[TMP42]] -; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], 0 -; CHECK-NEXT: [[TMP45:%.*]] = sub i32 [[TMP38]], [[TMP8]] -; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP38]], [[TMP8]] -; CHECK-NEXT: [[TMP47:%.*]] = select i1 [[TMP44]], i32 [[TMP38]], i32 [[TMP45]] -; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP41]], i32 [[TMP47]], i32 [[TMP46]] -; CHECK-NEXT: [[TMP49:%.*]] = xor i32 [[TMP48]], [[TMP3]] -; CHECK-NEXT: [[TMP50:%.*]] = sub i32 [[TMP49]], [[TMP3]] -; CHECK-NEXT: [[TMP51:%.*]] = insertelement <4 x i32> undef, i32 [[TMP50]], i64 0 -; CHECK-NEXT: [[TMP52:%.*]] = extractelement <4 x i32> [[X]], i64 1 -; CHECK-NEXT: [[TMP53:%.*]] = extractelement <4 x i32> [[Y]], i64 1 -; CHECK-NEXT: [[TMP54:%.*]] = ashr i32 [[TMP52]], 31 -; CHECK-NEXT: [[TMP55:%.*]] = ashr i32 [[TMP53]], 31 -; CHECK-NEXT: [[TMP56:%.*]] = add i32 [[TMP52]], [[TMP54]] -; CHECK-NEXT: [[TMP57:%.*]] = add i32 [[TMP53]], [[TMP55]] -; CHECK-NEXT: [[TMP58:%.*]] = xor i32 [[TMP56]], [[TMP54]] -; CHECK-NEXT: [[TMP59:%.*]] = xor i32 [[TMP57]], [[TMP55]] -; CHECK-NEXT: [[TMP60:%.*]] = uitofp i32 [[TMP59]] to float -; CHECK-NEXT: [[TMP61:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP60]]) -; CHECK-NEXT: [[TMP62:%.*]] = fmul fast float [[TMP61]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP63:%.*]] = fptoui float [[TMP62]] to i32 -; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[TMP63]] to i64 -; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP59]] to i64 -; CHECK-NEXT: [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]] -; CHECK-NEXT: [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32 -; CHECK-NEXT: [[TMP68:%.*]] = lshr i64 [[TMP66]], 32 -; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32 -; CHECK-NEXT: [[TMP70:%.*]] = sub i32 0, [[TMP67]] -; CHECK-NEXT: [[TMP71:%.*]] = icmp eq i32 [[TMP69]], 0 -; CHECK-NEXT: [[TMP72:%.*]] = select i1 [[TMP71]], i32 [[TMP70]], i32 [[TMP67]] -; CHECK-NEXT: [[TMP73:%.*]] = zext i32 [[TMP72]] to i64 -; CHECK-NEXT: [[TMP74:%.*]] = zext i32 [[TMP63]] to i64 -; CHECK-NEXT: [[TMP75:%.*]] = mul i64 [[TMP73]], [[TMP74]] -; CHECK-NEXT: [[TMP76:%.*]] = trunc i64 [[TMP75]] to i32 -; CHECK-NEXT: [[TMP77:%.*]] = lshr i64 [[TMP75]], 32 -; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32 -; CHECK-NEXT: [[TMP79:%.*]] = add i32 [[TMP63]], [[TMP78]] -; CHECK-NEXT: [[TMP80:%.*]] = sub i32 [[TMP63]], [[TMP78]] -; CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP71]], i32 [[TMP79]], i32 [[TMP80]] -; CHECK-NEXT: [[TMP82:%.*]] = zext i32 [[TMP81]] to i64 -; CHECK-NEXT: [[TMP83:%.*]] = zext i32 [[TMP58]] to i64 -; CHECK-NEXT: [[TMP84:%.*]] = mul i64 [[TMP82]], [[TMP83]] -; CHECK-NEXT: [[TMP85:%.*]] = trunc i64 [[TMP84]] to i32 -; CHECK-NEXT: [[TMP86:%.*]] = lshr i64 [[TMP84]], 32 -; CHECK-NEXT: [[TMP87:%.*]] = trunc i64 [[TMP86]] to i32 -; CHECK-NEXT: [[TMP88:%.*]] = mul i32 [[TMP87]], [[TMP59]] -; CHECK-NEXT: [[TMP89:%.*]] = sub i32 [[TMP58]], [[TMP88]] -; CHECK-NEXT: [[TMP90:%.*]] = icmp uge i32 [[TMP89]], [[TMP59]] -; CHECK-NEXT: [[TMP91:%.*]] = select i1 [[TMP90]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP92:%.*]] = icmp uge i32 [[TMP58]], [[TMP88]] -; CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP94:%.*]] = and i32 [[TMP91]], [[TMP93]] -; CHECK-NEXT: [[TMP95:%.*]] = icmp eq i32 [[TMP94]], 0 -; CHECK-NEXT: [[TMP96:%.*]] = sub i32 [[TMP89]], [[TMP59]] -; CHECK-NEXT: [[TMP97:%.*]] = add i32 [[TMP89]], [[TMP59]] -; CHECK-NEXT: [[TMP98:%.*]] = select i1 [[TMP95]], i32 [[TMP89]], i32 [[TMP96]] -; CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP92]], i32 [[TMP98]], i32 [[TMP97]] -; CHECK-NEXT: [[TMP100:%.*]] = xor i32 [[TMP99]], [[TMP54]] -; CHECK-NEXT: [[TMP101:%.*]] = sub i32 [[TMP100]], [[TMP54]] -; CHECK-NEXT: [[TMP102:%.*]] = insertelement <4 x i32> [[TMP51]], i32 [[TMP101]], i64 1 -; CHECK-NEXT: [[TMP103:%.*]] = extractelement <4 x i32> [[X]], i64 2 -; CHECK-NEXT: [[TMP104:%.*]] = extractelement <4 x i32> [[Y]], i64 2 -; CHECK-NEXT: [[TMP105:%.*]] = ashr i32 [[TMP103]], 31 -; CHECK-NEXT: [[TMP106:%.*]] = ashr i32 [[TMP104]], 31 -; CHECK-NEXT: [[TMP107:%.*]] = add i32 [[TMP103]], [[TMP105]] -; CHECK-NEXT: [[TMP108:%.*]] = add i32 [[TMP104]], [[TMP106]] -; CHECK-NEXT: [[TMP109:%.*]] = xor i32 [[TMP107]], [[TMP105]] -; CHECK-NEXT: [[TMP110:%.*]] = xor i32 [[TMP108]], [[TMP106]] -; CHECK-NEXT: [[TMP111:%.*]] = uitofp i32 [[TMP110]] to float -; CHECK-NEXT: [[TMP112:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP111]]) -; CHECK-NEXT: [[TMP113:%.*]] = fmul fast float [[TMP112]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP114:%.*]] = fptoui float [[TMP113]] to i32 -; CHECK-NEXT: [[TMP115:%.*]] = zext i32 [[TMP114]] to i64 -; CHECK-NEXT: [[TMP116:%.*]] = zext i32 [[TMP110]] to i64 -; CHECK-NEXT: [[TMP117:%.*]] = mul i64 [[TMP115]], [[TMP116]] -; CHECK-NEXT: [[TMP118:%.*]] = trunc i64 [[TMP117]] to i32 -; CHECK-NEXT: [[TMP119:%.*]] = lshr i64 [[TMP117]], 32 -; CHECK-NEXT: [[TMP120:%.*]] = trunc i64 [[TMP119]] to i32 -; CHECK-NEXT: [[TMP121:%.*]] = sub i32 0, [[TMP118]] -; CHECK-NEXT: [[TMP122:%.*]] = icmp eq i32 [[TMP120]], 0 -; CHECK-NEXT: [[TMP123:%.*]] = select i1 [[TMP122]], i32 [[TMP121]], i32 [[TMP118]] -; CHECK-NEXT: [[TMP124:%.*]] = zext i32 [[TMP123]] to i64 -; CHECK-NEXT: [[TMP125:%.*]] = zext i32 [[TMP114]] to i64 -; CHECK-NEXT: [[TMP126:%.*]] = mul i64 [[TMP124]], [[TMP125]] -; CHECK-NEXT: [[TMP127:%.*]] = trunc i64 [[TMP126]] to i32 -; CHECK-NEXT: [[TMP128:%.*]] = lshr i64 [[TMP126]], 32 -; CHECK-NEXT: [[TMP129:%.*]] = trunc i64 [[TMP128]] to i32 -; CHECK-NEXT: [[TMP130:%.*]] = add i32 [[TMP114]], [[TMP129]] -; CHECK-NEXT: [[TMP131:%.*]] = sub i32 [[TMP114]], [[TMP129]] -; CHECK-NEXT: [[TMP132:%.*]] = select i1 [[TMP122]], i32 [[TMP130]], i32 [[TMP131]] -; CHECK-NEXT: [[TMP133:%.*]] = zext i32 [[TMP132]] to i64 -; CHECK-NEXT: [[TMP134:%.*]] = zext i32 [[TMP109]] to i64 -; CHECK-NEXT: [[TMP135:%.*]] = mul i64 [[TMP133]], [[TMP134]] -; CHECK-NEXT: [[TMP136:%.*]] = trunc i64 [[TMP135]] to i32 -; CHECK-NEXT: [[TMP137:%.*]] = lshr i64 [[TMP135]], 32 -; CHECK-NEXT: [[TMP138:%.*]] = trunc i64 [[TMP137]] to i32 -; CHECK-NEXT: [[TMP139:%.*]] = mul i32 [[TMP138]], [[TMP110]] -; CHECK-NEXT: [[TMP140:%.*]] = sub i32 [[TMP109]], [[TMP139]] -; CHECK-NEXT: [[TMP141:%.*]] = icmp uge i32 [[TMP140]], [[TMP110]] -; CHECK-NEXT: [[TMP142:%.*]] = select i1 [[TMP141]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP143:%.*]] = icmp uge i32 [[TMP109]], [[TMP139]] -; CHECK-NEXT: [[TMP144:%.*]] = select i1 [[TMP143]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP145:%.*]] = and i32 [[TMP142]], [[TMP144]] -; CHECK-NEXT: [[TMP146:%.*]] = icmp eq i32 [[TMP145]], 0 -; CHECK-NEXT: [[TMP147:%.*]] = sub i32 [[TMP140]], [[TMP110]] -; CHECK-NEXT: [[TMP148:%.*]] = add i32 [[TMP140]], [[TMP110]] -; CHECK-NEXT: [[TMP149:%.*]] = select i1 [[TMP146]], i32 [[TMP140]], i32 [[TMP147]] -; CHECK-NEXT: [[TMP150:%.*]] = select i1 [[TMP143]], i32 [[TMP149]], i32 [[TMP148]] -; CHECK-NEXT: [[TMP151:%.*]] = xor i32 [[TMP150]], [[TMP105]] -; CHECK-NEXT: [[TMP152:%.*]] = sub i32 [[TMP151]], [[TMP105]] -; CHECK-NEXT: [[TMP153:%.*]] = insertelement <4 x i32> [[TMP102]], i32 [[TMP152]], i64 2 -; CHECK-NEXT: [[TMP154:%.*]] = extractelement <4 x i32> [[X]], i64 3 -; CHECK-NEXT: [[TMP155:%.*]] = extractelement <4 x i32> [[Y]], i64 3 -; CHECK-NEXT: [[TMP156:%.*]] = ashr i32 [[TMP154]], 31 -; CHECK-NEXT: [[TMP157:%.*]] = ashr i32 [[TMP155]], 31 -; CHECK-NEXT: [[TMP158:%.*]] = add i32 [[TMP154]], [[TMP156]] -; CHECK-NEXT: [[TMP159:%.*]] = add i32 [[TMP155]], [[TMP157]] -; CHECK-NEXT: [[TMP160:%.*]] = xor i32 [[TMP158]], [[TMP156]] -; CHECK-NEXT: [[TMP161:%.*]] = xor i32 [[TMP159]], [[TMP157]] -; CHECK-NEXT: [[TMP162:%.*]] = uitofp i32 [[TMP161]] to float -; CHECK-NEXT: [[TMP163:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP162]]) -; CHECK-NEXT: [[TMP164:%.*]] = fmul fast float [[TMP163]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP165:%.*]] = fptoui float [[TMP164]] to i32 +; CHECK-NEXT: [[TMP40:%.*]] = icmp uge i32 [[TMP7]], [[TMP37]] +; CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP39]], [[TMP40]] +; CHECK-NEXT: [[TMP42:%.*]] = sub i32 [[TMP38]], [[TMP8]] +; CHECK-NEXT: [[TMP43:%.*]] = add i32 [[TMP38]], [[TMP8]] +; CHECK-NEXT: [[TMP44:%.*]] = select i1 [[TMP41]], i32 [[TMP42]], i32 [[TMP38]] +; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP40]], i32 [[TMP44]], i32 [[TMP43]] +; CHECK-NEXT: [[TMP46:%.*]] = xor i32 [[TMP45]], [[TMP3]] +; CHECK-NEXT: [[TMP47:%.*]] = sub i32 [[TMP46]], [[TMP3]] +; CHECK-NEXT: [[TMP48:%.*]] = insertelement <4 x i32> undef, i32 [[TMP47]], i64 0 +; CHECK-NEXT: [[TMP49:%.*]] = extractelement <4 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP50:%.*]] = extractelement <4 x i32> [[Y]], i64 1 +; CHECK-NEXT: [[TMP51:%.*]] = ashr i32 [[TMP49]], 31 +; CHECK-NEXT: [[TMP52:%.*]] = ashr i32 [[TMP50]], 31 +; CHECK-NEXT: [[TMP53:%.*]] = add i32 [[TMP49]], [[TMP51]] +; CHECK-NEXT: [[TMP54:%.*]] = add i32 [[TMP50]], [[TMP52]] +; CHECK-NEXT: [[TMP55:%.*]] = xor i32 [[TMP53]], [[TMP51]] +; CHECK-NEXT: [[TMP56:%.*]] = xor i32 [[TMP54]], [[TMP52]] +; CHECK-NEXT: [[TMP57:%.*]] = uitofp i32 [[TMP56]] to float +; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]]) +; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP58]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP60:%.*]] = fptoui float [[TMP59]] to i32 +; CHECK-NEXT: [[TMP61:%.*]] = zext i32 [[TMP60]] to i64 +; CHECK-NEXT: [[TMP62:%.*]] = zext i32 [[TMP56]] to i64 +; CHECK-NEXT: [[TMP63:%.*]] = mul i64 [[TMP61]], [[TMP62]] +; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[TMP63]] to i32 +; CHECK-NEXT: [[TMP65:%.*]] = lshr i64 [[TMP63]], 32 +; CHECK-NEXT: [[TMP66:%.*]] = trunc i64 [[TMP65]] to i32 +; CHECK-NEXT: [[TMP67:%.*]] = sub i32 0, [[TMP64]] +; CHECK-NEXT: [[TMP68:%.*]] = icmp eq i32 [[TMP66]], 0 +; CHECK-NEXT: [[TMP69:%.*]] = select i1 [[TMP68]], i32 [[TMP67]], i32 [[TMP64]] +; CHECK-NEXT: [[TMP70:%.*]] = zext i32 [[TMP69]] to i64 +; CHECK-NEXT: [[TMP71:%.*]] = zext i32 [[TMP60]] to i64 +; CHECK-NEXT: [[TMP72:%.*]] = mul i64 [[TMP70]], [[TMP71]] +; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP72]] to i32 +; CHECK-NEXT: [[TMP74:%.*]] = lshr i64 [[TMP72]], 32 +; CHECK-NEXT: [[TMP75:%.*]] = trunc i64 [[TMP74]] to i32 +; CHECK-NEXT: [[TMP76:%.*]] = add i32 [[TMP60]], [[TMP75]] +; CHECK-NEXT: [[TMP77:%.*]] = sub i32 [[TMP60]], [[TMP75]] +; CHECK-NEXT: [[TMP78:%.*]] = select i1 [[TMP68]], i32 [[TMP76]], i32 [[TMP77]] +; CHECK-NEXT: [[TMP79:%.*]] = zext i32 [[TMP78]] to i64 +; CHECK-NEXT: [[TMP80:%.*]] = zext i32 [[TMP55]] to i64 +; CHECK-NEXT: [[TMP81:%.*]] = mul i64 [[TMP79]], [[TMP80]] +; CHECK-NEXT: [[TMP82:%.*]] = trunc i64 [[TMP81]] to i32 +; CHECK-NEXT: [[TMP83:%.*]] = lshr i64 [[TMP81]], 32 +; CHECK-NEXT: [[TMP84:%.*]] = trunc i64 [[TMP83]] to i32 +; CHECK-NEXT: [[TMP85:%.*]] = mul i32 [[TMP84]], [[TMP56]] +; CHECK-NEXT: [[TMP86:%.*]] = sub i32 [[TMP55]], [[TMP85]] +; CHECK-NEXT: [[TMP87:%.*]] = icmp uge i32 [[TMP86]], [[TMP56]] +; CHECK-NEXT: [[TMP88:%.*]] = icmp uge i32 [[TMP55]], [[TMP85]] +; CHECK-NEXT: [[TMP89:%.*]] = and i1 [[TMP87]], [[TMP88]] +; CHECK-NEXT: [[TMP90:%.*]] = sub i32 [[TMP86]], [[TMP56]] +; CHECK-NEXT: [[TMP91:%.*]] = add i32 [[TMP86]], [[TMP56]] +; CHECK-NEXT: [[TMP92:%.*]] = select i1 [[TMP89]], i32 [[TMP90]], i32 [[TMP86]] +; CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP88]], i32 [[TMP92]], i32 [[TMP91]] +; CHECK-NEXT: [[TMP94:%.*]] = xor i32 [[TMP93]], [[TMP51]] +; CHECK-NEXT: [[TMP95:%.*]] = sub i32 [[TMP94]], [[TMP51]] +; CHECK-NEXT: [[TMP96:%.*]] = insertelement <4 x i32> [[TMP48]], i32 [[TMP95]], i64 1 +; CHECK-NEXT: [[TMP97:%.*]] = extractelement <4 x i32> [[X]], i64 2 +; CHECK-NEXT: [[TMP98:%.*]] = extractelement <4 x i32> [[Y]], i64 2 +; CHECK-NEXT: [[TMP99:%.*]] = ashr i32 [[TMP97]], 31 +; CHECK-NEXT: [[TMP100:%.*]] = ashr i32 [[TMP98]], 31 +; CHECK-NEXT: [[TMP101:%.*]] = add i32 [[TMP97]], [[TMP99]] +; CHECK-NEXT: [[TMP102:%.*]] = add i32 [[TMP98]], [[TMP100]] +; CHECK-NEXT: [[TMP103:%.*]] = xor i32 [[TMP101]], [[TMP99]] +; CHECK-NEXT: [[TMP104:%.*]] = xor i32 [[TMP102]], [[TMP100]] +; CHECK-NEXT: [[TMP105:%.*]] = uitofp i32 [[TMP104]] to float +; CHECK-NEXT: [[TMP106:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP105]]) +; CHECK-NEXT: [[TMP107:%.*]] = fmul fast float [[TMP106]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP108:%.*]] = fptoui float [[TMP107]] to i32 +; CHECK-NEXT: [[TMP109:%.*]] = zext i32 [[TMP108]] to i64 +; CHECK-NEXT: [[TMP110:%.*]] = zext i32 [[TMP104]] to i64 +; CHECK-NEXT: [[TMP111:%.*]] = mul i64 [[TMP109]], [[TMP110]] +; CHECK-NEXT: [[TMP112:%.*]] = trunc i64 [[TMP111]] to i32 +; CHECK-NEXT: [[TMP113:%.*]] = lshr i64 [[TMP111]], 32 +; CHECK-NEXT: [[TMP114:%.*]] = trunc i64 [[TMP113]] to i32 +; CHECK-NEXT: [[TMP115:%.*]] = sub i32 0, [[TMP112]] +; CHECK-NEXT: [[TMP116:%.*]] = icmp eq i32 [[TMP114]], 0 +; CHECK-NEXT: [[TMP117:%.*]] = select i1 [[TMP116]], i32 [[TMP115]], i32 [[TMP112]] +; CHECK-NEXT: [[TMP118:%.*]] = zext i32 [[TMP117]] to i64 +; CHECK-NEXT: [[TMP119:%.*]] = zext i32 [[TMP108]] to i64 +; CHECK-NEXT: [[TMP120:%.*]] = mul i64 [[TMP118]], [[TMP119]] +; CHECK-NEXT: [[TMP121:%.*]] = trunc i64 [[TMP120]] to i32 +; CHECK-NEXT: [[TMP122:%.*]] = lshr i64 [[TMP120]], 32 +; CHECK-NEXT: [[TMP123:%.*]] = trunc i64 [[TMP122]] to i32 +; CHECK-NEXT: [[TMP124:%.*]] = add i32 [[TMP108]], [[TMP123]] +; CHECK-NEXT: [[TMP125:%.*]] = sub i32 [[TMP108]], [[TMP123]] +; CHECK-NEXT: [[TMP126:%.*]] = select i1 [[TMP116]], i32 [[TMP124]], i32 [[TMP125]] +; CHECK-NEXT: [[TMP127:%.*]] = zext i32 [[TMP126]] to i64 +; CHECK-NEXT: [[TMP128:%.*]] = zext i32 [[TMP103]] to i64 +; CHECK-NEXT: [[TMP129:%.*]] = mul i64 [[TMP127]], [[TMP128]] +; CHECK-NEXT: [[TMP130:%.*]] = trunc i64 [[TMP129]] to i32 +; CHECK-NEXT: [[TMP131:%.*]] = lshr i64 [[TMP129]], 32 +; CHECK-NEXT: [[TMP132:%.*]] = trunc i64 [[TMP131]] to i32 +; CHECK-NEXT: [[TMP133:%.*]] = mul i32 [[TMP132]], [[TMP104]] +; CHECK-NEXT: [[TMP134:%.*]] = sub i32 [[TMP103]], [[TMP133]] +; CHECK-NEXT: [[TMP135:%.*]] = icmp uge i32 [[TMP134]], [[TMP104]] +; CHECK-NEXT: [[TMP136:%.*]] = icmp uge i32 [[TMP103]], [[TMP133]] +; CHECK-NEXT: [[TMP137:%.*]] = and i1 [[TMP135]], [[TMP136]] +; CHECK-NEXT: [[TMP138:%.*]] = sub i32 [[TMP134]], [[TMP104]] +; CHECK-NEXT: [[TMP139:%.*]] = add i32 [[TMP134]], [[TMP104]] +; CHECK-NEXT: [[TMP140:%.*]] = select i1 [[TMP137]], i32 [[TMP138]], i32 [[TMP134]] +; CHECK-NEXT: [[TMP141:%.*]] = select i1 [[TMP136]], i32 [[TMP140]], i32 [[TMP139]] +; CHECK-NEXT: [[TMP142:%.*]] = xor i32 [[TMP141]], [[TMP99]] +; CHECK-NEXT: [[TMP143:%.*]] = sub i32 [[TMP142]], [[TMP99]] +; CHECK-NEXT: [[TMP144:%.*]] = insertelement <4 x i32> [[TMP96]], i32 [[TMP143]], i64 2 +; CHECK-NEXT: [[TMP145:%.*]] = extractelement <4 x i32> [[X]], i64 3 +; CHECK-NEXT: [[TMP146:%.*]] = extractelement <4 x i32> [[Y]], i64 3 +; CHECK-NEXT: [[TMP147:%.*]] = ashr i32 [[TMP145]], 31 +; CHECK-NEXT: [[TMP148:%.*]] = ashr i32 [[TMP146]], 31 +; CHECK-NEXT: [[TMP149:%.*]] = add i32 [[TMP145]], [[TMP147]] +; CHECK-NEXT: [[TMP150:%.*]] = add i32 [[TMP146]], [[TMP148]] +; CHECK-NEXT: [[TMP151:%.*]] = xor i32 [[TMP149]], [[TMP147]] +; CHECK-NEXT: [[TMP152:%.*]] = xor i32 [[TMP150]], [[TMP148]] +; CHECK-NEXT: [[TMP153:%.*]] = uitofp i32 [[TMP152]] to float +; CHECK-NEXT: [[TMP154:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP153]]) +; CHECK-NEXT: [[TMP155:%.*]] = fmul fast float [[TMP154]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP156:%.*]] = fptoui float [[TMP155]] to i32 +; CHECK-NEXT: [[TMP157:%.*]] = zext i32 [[TMP156]] to i64 +; CHECK-NEXT: [[TMP158:%.*]] = zext i32 [[TMP152]] to i64 +; CHECK-NEXT: [[TMP159:%.*]] = mul i64 [[TMP157]], [[TMP158]] +; CHECK-NEXT: [[TMP160:%.*]] = trunc i64 [[TMP159]] to i32 +; CHECK-NEXT: [[TMP161:%.*]] = lshr i64 [[TMP159]], 32 +; CHECK-NEXT: [[TMP162:%.*]] = trunc i64 [[TMP161]] to i32 +; CHECK-NEXT: [[TMP163:%.*]] = sub i32 0, [[TMP160]] +; CHECK-NEXT: [[TMP164:%.*]] = icmp eq i32 [[TMP162]], 0 +; CHECK-NEXT: [[TMP165:%.*]] = select i1 [[TMP164]], i32 [[TMP163]], i32 [[TMP160]] ; CHECK-NEXT: [[TMP166:%.*]] = zext i32 [[TMP165]] to i64 -; CHECK-NEXT: [[TMP167:%.*]] = zext i32 [[TMP161]] to i64 +; CHECK-NEXT: [[TMP167:%.*]] = zext i32 [[TMP156]] to i64 ; CHECK-NEXT: [[TMP168:%.*]] = mul i64 [[TMP166]], [[TMP167]] ; CHECK-NEXT: [[TMP169:%.*]] = trunc i64 [[TMP168]] to i32 ; CHECK-NEXT: [[TMP170:%.*]] = lshr i64 [[TMP168]], 32 ; CHECK-NEXT: [[TMP171:%.*]] = trunc i64 [[TMP170]] to i32 -; CHECK-NEXT: [[TMP172:%.*]] = sub i32 0, [[TMP169]] -; CHECK-NEXT: [[TMP173:%.*]] = icmp eq i32 [[TMP171]], 0 -; CHECK-NEXT: [[TMP174:%.*]] = select i1 [[TMP173]], i32 [[TMP172]], i32 [[TMP169]] +; CHECK-NEXT: [[TMP172:%.*]] = add i32 [[TMP156]], [[TMP171]] +; CHECK-NEXT: [[TMP173:%.*]] = sub i32 [[TMP156]], [[TMP171]] +; CHECK-NEXT: [[TMP174:%.*]] = select i1 [[TMP164]], i32 [[TMP172]], i32 [[TMP173]] ; CHECK-NEXT: [[TMP175:%.*]] = zext i32 [[TMP174]] to i64 -; CHECK-NEXT: [[TMP176:%.*]] = zext i32 [[TMP165]] to i64 +; CHECK-NEXT: [[TMP176:%.*]] = zext i32 [[TMP151]] to i64 ; CHECK-NEXT: [[TMP177:%.*]] = mul i64 [[TMP175]], [[TMP176]] ; CHECK-NEXT: [[TMP178:%.*]] = trunc i64 [[TMP177]] to i32 ; CHECK-NEXT: [[TMP179:%.*]] = lshr i64 [[TMP177]], 32 ; CHECK-NEXT: [[TMP180:%.*]] = trunc i64 [[TMP179]] to i32 -; CHECK-NEXT: [[TMP181:%.*]] = add i32 [[TMP165]], [[TMP180]] -; CHECK-NEXT: [[TMP182:%.*]] = sub i32 [[TMP165]], [[TMP180]] -; CHECK-NEXT: [[TMP183:%.*]] = select i1 [[TMP173]], i32 [[TMP181]], i32 [[TMP182]] -; CHECK-NEXT: [[TMP184:%.*]] = zext i32 [[TMP183]] to i64 -; CHECK-NEXT: [[TMP185:%.*]] = zext i32 [[TMP160]] to i64 -; CHECK-NEXT: [[TMP186:%.*]] = mul i64 [[TMP184]], [[TMP185]] -; CHECK-NEXT: [[TMP187:%.*]] = trunc i64 [[TMP186]] to i32 -; CHECK-NEXT: [[TMP188:%.*]] = lshr i64 [[TMP186]], 32 -; CHECK-NEXT: [[TMP189:%.*]] = trunc i64 [[TMP188]] to i32 -; CHECK-NEXT: [[TMP190:%.*]] = mul i32 [[TMP189]], [[TMP161]] -; CHECK-NEXT: [[TMP191:%.*]] = sub i32 [[TMP160]], [[TMP190]] -; CHECK-NEXT: [[TMP192:%.*]] = icmp uge i32 [[TMP191]], [[TMP161]] -; CHECK-NEXT: [[TMP193:%.*]] = select i1 [[TMP192]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP194:%.*]] = icmp uge i32 [[TMP160]], [[TMP190]] -; CHECK-NEXT: [[TMP195:%.*]] = select i1 [[TMP194]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP196:%.*]] = and i32 [[TMP193]], [[TMP195]] -; CHECK-NEXT: [[TMP197:%.*]] = icmp eq i32 [[TMP196]], 0 -; CHECK-NEXT: [[TMP198:%.*]] = sub i32 [[TMP191]], [[TMP161]] -; CHECK-NEXT: [[TMP199:%.*]] = add i32 [[TMP191]], [[TMP161]] -; CHECK-NEXT: [[TMP200:%.*]] = select i1 [[TMP197]], i32 [[TMP191]], i32 [[TMP198]] -; CHECK-NEXT: [[TMP201:%.*]] = select i1 [[TMP194]], i32 [[TMP200]], i32 [[TMP199]] -; CHECK-NEXT: [[TMP202:%.*]] = xor i32 [[TMP201]], [[TMP156]] -; CHECK-NEXT: [[TMP203:%.*]] = sub i32 [[TMP202]], [[TMP156]] -; CHECK-NEXT: [[TMP204:%.*]] = insertelement <4 x i32> [[TMP153]], i32 [[TMP203]], i64 3 -; CHECK-NEXT: store <4 x i32> [[TMP204]], <4 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP181:%.*]] = mul i32 [[TMP180]], [[TMP152]] +; CHECK-NEXT: [[TMP182:%.*]] = sub i32 [[TMP151]], [[TMP181]] +; CHECK-NEXT: [[TMP183:%.*]] = icmp uge i32 [[TMP182]], [[TMP152]] +; CHECK-NEXT: [[TMP184:%.*]] = icmp uge i32 [[TMP151]], [[TMP181]] +; CHECK-NEXT: [[TMP185:%.*]] = and i1 [[TMP183]], [[TMP184]] +; CHECK-NEXT: [[TMP186:%.*]] = sub i32 [[TMP182]], [[TMP152]] +; CHECK-NEXT: [[TMP187:%.*]] = add i32 [[TMP182]], [[TMP152]] +; CHECK-NEXT: [[TMP188:%.*]] = select i1 [[TMP185]], i32 [[TMP186]], i32 [[TMP182]] +; CHECK-NEXT: [[TMP189:%.*]] = select i1 [[TMP184]], i32 [[TMP188]], i32 [[TMP187]] +; CHECK-NEXT: [[TMP190:%.*]] = xor i32 [[TMP189]], [[TMP147]] +; CHECK-NEXT: [[TMP191:%.*]] = sub i32 [[TMP190]], [[TMP147]] +; CHECK-NEXT: [[TMP192:%.*]] = insertelement <4 x i32> [[TMP144]], i32 [[TMP191]], i64 3 +; CHECK-NEXT: store <4 x i32> [[TMP192]], <4 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: srem_v4i32: @@ -4304,60 +4244,54 @@ define amdgpu_kernel void @udiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %ou ; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[TMP2]] ; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP1]], [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP2]] -; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP35:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] -; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP37:%.*]] = and i32 [[TMP34]], [[TMP36]] -; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i32 [[TMP37]], 0 -; CHECK-NEXT: [[TMP39:%.*]] = add i32 [[TMP30]], 1 -; CHECK-NEXT: [[TMP40:%.*]] = sub i32 [[TMP30]], 1 -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP38]], i32 [[TMP30]], i32 [[TMP39]] -; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], i32 [[TMP41]], i32 [[TMP40]] -; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x i32> undef, i32 [[TMP42]], i64 0 -; CHECK-NEXT: [[TMP44:%.*]] = extractelement <2 x i32> [[X]], i64 1 -; CHECK-NEXT: [[TMP45:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 -; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP45]] to float -; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) -; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP47]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP49:%.*]] = fptoui float [[TMP48]] to i32 -; CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 -; CHECK-NEXT: [[TMP51:%.*]] = zext i32 [[TMP45]] to i64 -; CHECK-NEXT: [[TMP52:%.*]] = mul i64 [[TMP50]], [[TMP51]] -; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32 -; CHECK-NEXT: [[TMP54:%.*]] = lshr i64 [[TMP52]], 32 -; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i32 -; CHECK-NEXT: [[TMP56:%.*]] = sub i32 0, [[TMP53]] -; CHECK-NEXT: [[TMP57:%.*]] = icmp eq i32 [[TMP55]], 0 -; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], i32 [[TMP56]], i32 [[TMP53]] -; CHECK-NEXT: [[TMP59:%.*]] = zext i32 [[TMP58]] to i64 -; CHECK-NEXT: [[TMP60:%.*]] = zext i32 [[TMP49]] to i64 -; CHECK-NEXT: [[TMP61:%.*]] = mul i64 [[TMP59]], [[TMP60]] -; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32 -; CHECK-NEXT: [[TMP63:%.*]] = lshr i64 [[TMP61]], 32 -; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[TMP63]] to i32 -; CHECK-NEXT: [[TMP65:%.*]] = add i32 [[TMP49]], [[TMP64]] -; CHECK-NEXT: [[TMP66:%.*]] = sub i32 [[TMP49]], [[TMP64]] -; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP57]], i32 [[TMP65]], i32 [[TMP66]] -; CHECK-NEXT: [[TMP68:%.*]] = zext i32 [[TMP67]] to i64 -; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP44]] to i64 -; CHECK-NEXT: [[TMP70:%.*]] = mul i64 [[TMP68]], [[TMP69]] -; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 -; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP70]], 32 -; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP72]] to i32 -; CHECK-NEXT: [[TMP74:%.*]] = mul i32 [[TMP73]], [[TMP45]] -; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP44]], [[TMP74]] -; CHECK-NEXT: [[TMP76:%.*]] = icmp uge i32 [[TMP75]], [[TMP45]] -; CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP78:%.*]] = icmp uge i32 [[TMP44]], [[TMP74]] -; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP78]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP80:%.*]] = and i32 [[TMP77]], [[TMP79]] -; CHECK-NEXT: [[TMP81:%.*]] = icmp eq i32 [[TMP80]], 0 -; CHECK-NEXT: [[TMP82:%.*]] = add i32 [[TMP73]], 1 -; CHECK-NEXT: [[TMP83:%.*]] = sub i32 [[TMP73]], 1 -; CHECK-NEXT: [[TMP84:%.*]] = select i1 [[TMP81]], i32 [[TMP73]], i32 [[TMP82]] -; CHECK-NEXT: [[TMP85:%.*]] = select i1 [[TMP78]], i32 [[TMP84]], i32 [[TMP83]] -; CHECK-NEXT: [[TMP86:%.*]] = insertelement <2 x i32> [[TMP43]], i32 [[TMP85]], i64 1 -; CHECK-NEXT: store <2 x i32> [[TMP86]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] +; CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP33]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = add i32 [[TMP30]], 1 +; CHECK-NEXT: [[TMP37:%.*]] = sub i32 [[TMP30]], 1 +; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP35]], i32 [[TMP36]], i32 [[TMP30]] +; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP34]], i32 [[TMP38]], i32 [[TMP37]] +; CHECK-NEXT: [[TMP40:%.*]] = insertelement <2 x i32> undef, i32 [[TMP39]], i64 0 +; CHECK-NEXT: [[TMP41:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 +; CHECK-NEXT: [[TMP43:%.*]] = uitofp i32 [[TMP42]] to float +; CHECK-NEXT: [[TMP44:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP43]]) +; CHECK-NEXT: [[TMP45:%.*]] = fmul fast float [[TMP44]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP46:%.*]] = fptoui float [[TMP45]] to i32 +; CHECK-NEXT: [[TMP47:%.*]] = zext i32 [[TMP46]] to i64 +; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP42]] to i64 +; CHECK-NEXT: [[TMP49:%.*]] = mul i64 [[TMP47]], [[TMP48]] +; CHECK-NEXT: [[TMP50:%.*]] = trunc i64 [[TMP49]] to i32 +; CHECK-NEXT: [[TMP51:%.*]] = lshr i64 [[TMP49]], 32 +; CHECK-NEXT: [[TMP52:%.*]] = trunc i64 [[TMP51]] to i32 +; CHECK-NEXT: [[TMP53:%.*]] = sub i32 0, [[TMP50]] +; CHECK-NEXT: [[TMP54:%.*]] = icmp eq i32 [[TMP52]], 0 +; CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP53]], i32 [[TMP50]] +; CHECK-NEXT: [[TMP56:%.*]] = zext i32 [[TMP55]] to i64 +; CHECK-NEXT: [[TMP57:%.*]] = zext i32 [[TMP46]] to i64 +; CHECK-NEXT: [[TMP58:%.*]] = mul i64 [[TMP56]], [[TMP57]] +; CHECK-NEXT: [[TMP59:%.*]] = trunc i64 [[TMP58]] to i32 +; CHECK-NEXT: [[TMP60:%.*]] = lshr i64 [[TMP58]], 32 +; CHECK-NEXT: [[TMP61:%.*]] = trunc i64 [[TMP60]] to i32 +; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP46]], [[TMP61]] +; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP46]], [[TMP61]] +; CHECK-NEXT: [[TMP64:%.*]] = select i1 [[TMP54]], i32 [[TMP62]], i32 [[TMP63]] +; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP64]] to i64 +; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP41]] to i64 +; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[TMP65]], [[TMP66]] +; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i32 +; CHECK-NEXT: [[TMP69:%.*]] = lshr i64 [[TMP67]], 32 +; CHECK-NEXT: [[TMP70:%.*]] = trunc i64 [[TMP69]] to i32 +; CHECK-NEXT: [[TMP71:%.*]] = mul i32 [[TMP70]], [[TMP42]] +; CHECK-NEXT: [[TMP72:%.*]] = sub i32 [[TMP41]], [[TMP71]] +; CHECK-NEXT: [[TMP73:%.*]] = icmp uge i32 [[TMP72]], [[TMP42]] +; CHECK-NEXT: [[TMP74:%.*]] = icmp uge i32 [[TMP41]], [[TMP71]] +; CHECK-NEXT: [[TMP75:%.*]] = and i1 [[TMP73]], [[TMP74]] +; CHECK-NEXT: [[TMP76:%.*]] = add i32 [[TMP70]], 1 +; CHECK-NEXT: [[TMP77:%.*]] = sub i32 [[TMP70]], 1 +; CHECK-NEXT: [[TMP78:%.*]] = select i1 [[TMP75]], i32 [[TMP76]], i32 [[TMP70]] +; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP74]], i32 [[TMP78]], i32 [[TMP77]] +; CHECK-NEXT: [[TMP80:%.*]] = insertelement <2 x i32> [[TMP40]], i32 [[TMP79]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP80]], <2 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: udiv_v2i32_pow2_shl_denom: @@ -4569,60 +4503,54 @@ define amdgpu_kernel void @urem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %ou ; CHECK-NEXT: [[TMP31:%.*]] = mul i32 [[TMP30]], [[TMP2]] ; CHECK-NEXT: [[TMP32:%.*]] = sub i32 [[TMP1]], [[TMP31]] ; CHECK-NEXT: [[TMP33:%.*]] = icmp uge i32 [[TMP32]], [[TMP2]] -; CHECK-NEXT: [[TMP34:%.*]] = select i1 [[TMP33]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP35:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] -; CHECK-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP37:%.*]] = and i32 [[TMP34]], [[TMP36]] -; CHECK-NEXT: [[TMP38:%.*]] = icmp eq i32 [[TMP37]], 0 -; CHECK-NEXT: [[TMP39:%.*]] = sub i32 [[TMP32]], [[TMP2]] -; CHECK-NEXT: [[TMP40:%.*]] = add i32 [[TMP32]], [[TMP2]] -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP38]], i32 [[TMP32]], i32 [[TMP39]] -; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP35]], i32 [[TMP41]], i32 [[TMP40]] -; CHECK-NEXT: [[TMP43:%.*]] = insertelement <2 x i32> undef, i32 [[TMP42]], i64 0 -; CHECK-NEXT: [[TMP44:%.*]] = extractelement <2 x i32> [[X]], i64 1 -; CHECK-NEXT: [[TMP45:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 -; CHECK-NEXT: [[TMP46:%.*]] = uitofp i32 [[TMP45]] to float -; CHECK-NEXT: [[TMP47:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP46]]) -; CHECK-NEXT: [[TMP48:%.*]] = fmul fast float [[TMP47]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP49:%.*]] = fptoui float [[TMP48]] to i32 -; CHECK-NEXT: [[TMP50:%.*]] = zext i32 [[TMP49]] to i64 -; CHECK-NEXT: [[TMP51:%.*]] = zext i32 [[TMP45]] to i64 -; CHECK-NEXT: [[TMP52:%.*]] = mul i64 [[TMP50]], [[TMP51]] -; CHECK-NEXT: [[TMP53:%.*]] = trunc i64 [[TMP52]] to i32 -; CHECK-NEXT: [[TMP54:%.*]] = lshr i64 [[TMP52]], 32 -; CHECK-NEXT: [[TMP55:%.*]] = trunc i64 [[TMP54]] to i32 -; CHECK-NEXT: [[TMP56:%.*]] = sub i32 0, [[TMP53]] -; CHECK-NEXT: [[TMP57:%.*]] = icmp eq i32 [[TMP55]], 0 -; CHECK-NEXT: [[TMP58:%.*]] = select i1 [[TMP57]], i32 [[TMP56]], i32 [[TMP53]] -; CHECK-NEXT: [[TMP59:%.*]] = zext i32 [[TMP58]] to i64 -; CHECK-NEXT: [[TMP60:%.*]] = zext i32 [[TMP49]] to i64 -; CHECK-NEXT: [[TMP61:%.*]] = mul i64 [[TMP59]], [[TMP60]] -; CHECK-NEXT: [[TMP62:%.*]] = trunc i64 [[TMP61]] to i32 -; CHECK-NEXT: [[TMP63:%.*]] = lshr i64 [[TMP61]], 32 -; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[TMP63]] to i32 -; CHECK-NEXT: [[TMP65:%.*]] = add i32 [[TMP49]], [[TMP64]] -; CHECK-NEXT: [[TMP66:%.*]] = sub i32 [[TMP49]], [[TMP64]] -; CHECK-NEXT: [[TMP67:%.*]] = select i1 [[TMP57]], i32 [[TMP65]], i32 [[TMP66]] -; CHECK-NEXT: [[TMP68:%.*]] = zext i32 [[TMP67]] to i64 -; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP44]] to i64 -; CHECK-NEXT: [[TMP70:%.*]] = mul i64 [[TMP68]], [[TMP69]] -; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 -; CHECK-NEXT: [[TMP72:%.*]] = lshr i64 [[TMP70]], 32 -; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP72]] to i32 -; CHECK-NEXT: [[TMP74:%.*]] = mul i32 [[TMP73]], [[TMP45]] -; CHECK-NEXT: [[TMP75:%.*]] = sub i32 [[TMP44]], [[TMP74]] -; CHECK-NEXT: [[TMP76:%.*]] = icmp uge i32 [[TMP75]], [[TMP45]] -; CHECK-NEXT: [[TMP77:%.*]] = select i1 [[TMP76]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP78:%.*]] = icmp uge i32 [[TMP44]], [[TMP74]] -; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP78]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP80:%.*]] = and i32 [[TMP77]], [[TMP79]] -; CHECK-NEXT: [[TMP81:%.*]] = icmp eq i32 [[TMP80]], 0 -; CHECK-NEXT: [[TMP82:%.*]] = sub i32 [[TMP75]], [[TMP45]] -; CHECK-NEXT: [[TMP83:%.*]] = add i32 [[TMP75]], [[TMP45]] -; CHECK-NEXT: [[TMP84:%.*]] = select i1 [[TMP81]], i32 [[TMP75]], i32 [[TMP82]] -; CHECK-NEXT: [[TMP85:%.*]] = select i1 [[TMP78]], i32 [[TMP84]], i32 [[TMP83]] -; CHECK-NEXT: [[TMP86:%.*]] = insertelement <2 x i32> [[TMP43]], i32 [[TMP85]], i64 1 -; CHECK-NEXT: store <2 x i32> [[TMP86]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP1]], [[TMP31]] +; CHECK-NEXT: [[TMP35:%.*]] = and i1 [[TMP33]], [[TMP34]] +; CHECK-NEXT: [[TMP36:%.*]] = sub i32 [[TMP32]], [[TMP2]] +; CHECK-NEXT: [[TMP37:%.*]] = add i32 [[TMP32]], [[TMP2]] +; CHECK-NEXT: [[TMP38:%.*]] = select i1 [[TMP35]], i32 [[TMP36]], i32 [[TMP32]] +; CHECK-NEXT: [[TMP39:%.*]] = select i1 [[TMP34]], i32 [[TMP38]], i32 [[TMP37]] +; CHECK-NEXT: [[TMP40:%.*]] = insertelement <2 x i32> undef, i32 [[TMP39]], i64 0 +; CHECK-NEXT: [[TMP41:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP42:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 +; CHECK-NEXT: [[TMP43:%.*]] = uitofp i32 [[TMP42]] to float +; CHECK-NEXT: [[TMP44:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP43]]) +; CHECK-NEXT: [[TMP45:%.*]] = fmul fast float [[TMP44]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP46:%.*]] = fptoui float [[TMP45]] to i32 +; CHECK-NEXT: [[TMP47:%.*]] = zext i32 [[TMP46]] to i64 +; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP42]] to i64 +; CHECK-NEXT: [[TMP49:%.*]] = mul i64 [[TMP47]], [[TMP48]] +; CHECK-NEXT: [[TMP50:%.*]] = trunc i64 [[TMP49]] to i32 +; CHECK-NEXT: [[TMP51:%.*]] = lshr i64 [[TMP49]], 32 +; CHECK-NEXT: [[TMP52:%.*]] = trunc i64 [[TMP51]] to i32 +; CHECK-NEXT: [[TMP53:%.*]] = sub i32 0, [[TMP50]] +; CHECK-NEXT: [[TMP54:%.*]] = icmp eq i32 [[TMP52]], 0 +; CHECK-NEXT: [[TMP55:%.*]] = select i1 [[TMP54]], i32 [[TMP53]], i32 [[TMP50]] +; CHECK-NEXT: [[TMP56:%.*]] = zext i32 [[TMP55]] to i64 +; CHECK-NEXT: [[TMP57:%.*]] = zext i32 [[TMP46]] to i64 +; CHECK-NEXT: [[TMP58:%.*]] = mul i64 [[TMP56]], [[TMP57]] +; CHECK-NEXT: [[TMP59:%.*]] = trunc i64 [[TMP58]] to i32 +; CHECK-NEXT: [[TMP60:%.*]] = lshr i64 [[TMP58]], 32 +; CHECK-NEXT: [[TMP61:%.*]] = trunc i64 [[TMP60]] to i32 +; CHECK-NEXT: [[TMP62:%.*]] = add i32 [[TMP46]], [[TMP61]] +; CHECK-NEXT: [[TMP63:%.*]] = sub i32 [[TMP46]], [[TMP61]] +; CHECK-NEXT: [[TMP64:%.*]] = select i1 [[TMP54]], i32 [[TMP62]], i32 [[TMP63]] +; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP64]] to i64 +; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP41]] to i64 +; CHECK-NEXT: [[TMP67:%.*]] = mul i64 [[TMP65]], [[TMP66]] +; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i32 +; CHECK-NEXT: [[TMP69:%.*]] = lshr i64 [[TMP67]], 32 +; CHECK-NEXT: [[TMP70:%.*]] = trunc i64 [[TMP69]] to i32 +; CHECK-NEXT: [[TMP71:%.*]] = mul i32 [[TMP70]], [[TMP42]] +; CHECK-NEXT: [[TMP72:%.*]] = sub i32 [[TMP41]], [[TMP71]] +; CHECK-NEXT: [[TMP73:%.*]] = icmp uge i32 [[TMP72]], [[TMP42]] +; CHECK-NEXT: [[TMP74:%.*]] = icmp uge i32 [[TMP41]], [[TMP71]] +; CHECK-NEXT: [[TMP75:%.*]] = and i1 [[TMP73]], [[TMP74]] +; CHECK-NEXT: [[TMP76:%.*]] = sub i32 [[TMP72]], [[TMP42]] +; CHECK-NEXT: [[TMP77:%.*]] = add i32 [[TMP72]], [[TMP42]] +; CHECK-NEXT: [[TMP78:%.*]] = select i1 [[TMP75]], i32 [[TMP76]], i32 [[TMP72]] +; CHECK-NEXT: [[TMP79:%.*]] = select i1 [[TMP74]], i32 [[TMP78]], i32 [[TMP77]] +; CHECK-NEXT: [[TMP80:%.*]] = insertelement <2 x i32> [[TMP40]], i32 [[TMP79]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP80]], <2 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: urem_v2i32_pow2_shl_denom: @@ -4912,71 +4840,65 @@ define amdgpu_kernel void @sdiv_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %ou ; CHECK-NEXT: [[TMP38:%.*]] = mul i32 [[TMP37]], [[TMP9]] ; CHECK-NEXT: [[TMP39:%.*]] = sub i32 [[TMP8]], [[TMP38]] ; CHECK-NEXT: [[TMP40:%.*]] = icmp uge i32 [[TMP39]], [[TMP9]] -; CHECK-NEXT: [[TMP41:%.*]] = select i1 [[TMP40]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP42:%.*]] = icmp uge i32 [[TMP8]], [[TMP38]] -; CHECK-NEXT: [[TMP43:%.*]] = select i1 [[TMP42]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP44:%.*]] = and i32 [[TMP41]], [[TMP43]] -; CHECK-NEXT: [[TMP45:%.*]] = icmp eq i32 [[TMP44]], 0 -; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP37]], 1 -; CHECK-NEXT: [[TMP47:%.*]] = sub i32 [[TMP37]], 1 -; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP45]], i32 [[TMP37]], i32 [[TMP46]] -; CHECK-NEXT: [[TMP49:%.*]] = select i1 [[TMP42]], i32 [[TMP48]], i32 [[TMP47]] -; CHECK-NEXT: [[TMP50:%.*]] = xor i32 [[TMP49]], [[TMP5]] -; CHECK-NEXT: [[TMP51:%.*]] = sub i32 [[TMP50]], [[TMP5]] -; CHECK-NEXT: [[TMP52:%.*]] = insertelement <2 x i32> undef, i32 [[TMP51]], i64 0 -; CHECK-NEXT: [[TMP53:%.*]] = extractelement <2 x i32> [[X]], i64 1 -; CHECK-NEXT: [[TMP54:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 -; CHECK-NEXT: [[TMP55:%.*]] = ashr i32 [[TMP53]], 31 -; CHECK-NEXT: [[TMP56:%.*]] = ashr i32 [[TMP54]], 31 -; CHECK-NEXT: [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP56]] -; CHECK-NEXT: [[TMP58:%.*]] = add i32 [[TMP53]], [[TMP55]] -; CHECK-NEXT: [[TMP59:%.*]] = add i32 [[TMP54]], [[TMP56]] -; CHECK-NEXT: [[TMP60:%.*]] = xor i32 [[TMP58]], [[TMP55]] -; CHECK-NEXT: [[TMP61:%.*]] = xor i32 [[TMP59]], [[TMP56]] -; CHECK-NEXT: [[TMP62:%.*]] = uitofp i32 [[TMP61]] to float -; CHECK-NEXT: [[TMP63:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP62]]) -; CHECK-NEXT: [[TMP64:%.*]] = fmul fast float [[TMP63]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP65:%.*]] = fptoui float [[TMP64]] to i32 -; CHECK-NEXT: [[TMP66:%.*]] = zext i32 [[TMP65]] to i64 -; CHECK-NEXT: [[TMP67:%.*]] = zext i32 [[TMP61]] to i64 -; CHECK-NEXT: [[TMP68:%.*]] = mul i64 [[TMP66]], [[TMP67]] -; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32 -; CHECK-NEXT: [[TMP70:%.*]] = lshr i64 [[TMP68]], 32 -; CHECK-NEXT: [[TMP71:%.*]] = trunc i64 [[TMP70]] to i32 -; CHECK-NEXT: [[TMP72:%.*]] = sub i32 0, [[TMP69]] -; CHECK-NEXT: [[TMP73:%.*]] = icmp eq i32 [[TMP71]], 0 -; CHECK-NEXT: [[TMP74:%.*]] = select i1 [[TMP73]], i32 [[TMP72]], i32 [[TMP69]] -; CHECK-NEXT: [[TMP75:%.*]] = zext i32 [[TMP74]] to i64 -; CHECK-NEXT: [[TMP76:%.*]] = zext i32 [[TMP65]] to i64 -; CHECK-NEXT: [[TMP77:%.*]] = mul i64 [[TMP75]], [[TMP76]] -; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32 -; CHECK-NEXT: [[TMP79:%.*]] = lshr i64 [[TMP77]], 32 -; CHECK-NEXT: [[TMP80:%.*]] = trunc i64 [[TMP79]] to i32 -; CHECK-NEXT: [[TMP81:%.*]] = add i32 [[TMP65]], [[TMP80]] -; CHECK-NEXT: [[TMP82:%.*]] = sub i32 [[TMP65]], [[TMP80]] -; CHECK-NEXT: [[TMP83:%.*]] = select i1 [[TMP73]], i32 [[TMP81]], i32 [[TMP82]] -; CHECK-NEXT: [[TMP84:%.*]] = zext i32 [[TMP83]] to i64 -; CHECK-NEXT: [[TMP85:%.*]] = zext i32 [[TMP60]] to i64 -; CHECK-NEXT: [[TMP86:%.*]] = mul i64 [[TMP84]], [[TMP85]] -; CHECK-NEXT: [[TMP87:%.*]] = trunc i64 [[TMP86]] to i32 -; CHECK-NEXT: [[TMP88:%.*]] = lshr i64 [[TMP86]], 32 -; CHECK-NEXT: [[TMP89:%.*]] = trunc i64 [[TMP88]] to i32 -; CHECK-NEXT: [[TMP90:%.*]] = mul i32 [[TMP89]], [[TMP61]] -; CHECK-NEXT: [[TMP91:%.*]] = sub i32 [[TMP60]], [[TMP90]] -; CHECK-NEXT: [[TMP92:%.*]] = icmp uge i32 [[TMP91]], [[TMP61]] -; CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP94:%.*]] = icmp uge i32 [[TMP60]], [[TMP90]] -; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP94]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP96:%.*]] = and i32 [[TMP93]], [[TMP95]] -; CHECK-NEXT: [[TMP97:%.*]] = icmp eq i32 [[TMP96]], 0 -; CHECK-NEXT: [[TMP98:%.*]] = add i32 [[TMP89]], 1 -; CHECK-NEXT: [[TMP99:%.*]] = sub i32 [[TMP89]], 1 -; CHECK-NEXT: [[TMP100:%.*]] = select i1 [[TMP97]], i32 [[TMP89]], i32 [[TMP98]] -; CHECK-NEXT: [[TMP101:%.*]] = select i1 [[TMP94]], i32 [[TMP100]], i32 [[TMP99]] -; CHECK-NEXT: [[TMP102:%.*]] = xor i32 [[TMP101]], [[TMP57]] -; CHECK-NEXT: [[TMP103:%.*]] = sub i32 [[TMP102]], [[TMP57]] -; CHECK-NEXT: [[TMP104:%.*]] = insertelement <2 x i32> [[TMP52]], i32 [[TMP103]], i64 1 -; CHECK-NEXT: store <2 x i32> [[TMP104]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP41:%.*]] = icmp uge i32 [[TMP8]], [[TMP38]] +; CHECK-NEXT: [[TMP42:%.*]] = and i1 [[TMP40]], [[TMP41]] +; CHECK-NEXT: [[TMP43:%.*]] = add i32 [[TMP37]], 1 +; CHECK-NEXT: [[TMP44:%.*]] = sub i32 [[TMP37]], 1 +; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP42]], i32 [[TMP43]], i32 [[TMP37]] +; CHECK-NEXT: [[TMP46:%.*]] = select i1 [[TMP41]], i32 [[TMP45]], i32 [[TMP44]] +; CHECK-NEXT: [[TMP47:%.*]] = xor i32 [[TMP46]], [[TMP5]] +; CHECK-NEXT: [[TMP48:%.*]] = sub i32 [[TMP47]], [[TMP5]] +; CHECK-NEXT: [[TMP49:%.*]] = insertelement <2 x i32> undef, i32 [[TMP48]], i64 0 +; CHECK-NEXT: [[TMP50:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP51:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 +; CHECK-NEXT: [[TMP52:%.*]] = ashr i32 [[TMP50]], 31 +; CHECK-NEXT: [[TMP53:%.*]] = ashr i32 [[TMP51]], 31 +; CHECK-NEXT: [[TMP54:%.*]] = xor i32 [[TMP52]], [[TMP53]] +; CHECK-NEXT: [[TMP55:%.*]] = add i32 [[TMP50]], [[TMP52]] +; CHECK-NEXT: [[TMP56:%.*]] = add i32 [[TMP51]], [[TMP53]] +; CHECK-NEXT: [[TMP57:%.*]] = xor i32 [[TMP55]], [[TMP52]] +; CHECK-NEXT: [[TMP58:%.*]] = xor i32 [[TMP56]], [[TMP53]] +; CHECK-NEXT: [[TMP59:%.*]] = uitofp i32 [[TMP58]] to float +; CHECK-NEXT: [[TMP60:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP59]]) +; CHECK-NEXT: [[TMP61:%.*]] = fmul fast float [[TMP60]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP62:%.*]] = fptoui float [[TMP61]] to i32 +; CHECK-NEXT: [[TMP63:%.*]] = zext i32 [[TMP62]] to i64 +; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[TMP58]] to i64 +; CHECK-NEXT: [[TMP65:%.*]] = mul i64 [[TMP63]], [[TMP64]] +; CHECK-NEXT: [[TMP66:%.*]] = trunc i64 [[TMP65]] to i32 +; CHECK-NEXT: [[TMP67:%.*]] = lshr i64 [[TMP65]], 32 +; CHECK-NEXT: [[TMP68:%.*]] = trunc i64 [[TMP67]] to i32 +; CHECK-NEXT: [[TMP69:%.*]] = sub i32 0, [[TMP66]] +; CHECK-NEXT: [[TMP70:%.*]] = icmp eq i32 [[TMP68]], 0 +; CHECK-NEXT: [[TMP71:%.*]] = select i1 [[TMP70]], i32 [[TMP69]], i32 [[TMP66]] +; CHECK-NEXT: [[TMP72:%.*]] = zext i32 [[TMP71]] to i64 +; CHECK-NEXT: [[TMP73:%.*]] = zext i32 [[TMP62]] to i64 +; CHECK-NEXT: [[TMP74:%.*]] = mul i64 [[TMP72]], [[TMP73]] +; CHECK-NEXT: [[TMP75:%.*]] = trunc i64 [[TMP74]] to i32 +; CHECK-NEXT: [[TMP76:%.*]] = lshr i64 [[TMP74]], 32 +; CHECK-NEXT: [[TMP77:%.*]] = trunc i64 [[TMP76]] to i32 +; CHECK-NEXT: [[TMP78:%.*]] = add i32 [[TMP62]], [[TMP77]] +; CHECK-NEXT: [[TMP79:%.*]] = sub i32 [[TMP62]], [[TMP77]] +; CHECK-NEXT: [[TMP80:%.*]] = select i1 [[TMP70]], i32 [[TMP78]], i32 [[TMP79]] +; CHECK-NEXT: [[TMP81:%.*]] = zext i32 [[TMP80]] to i64 +; CHECK-NEXT: [[TMP82:%.*]] = zext i32 [[TMP57]] to i64 +; CHECK-NEXT: [[TMP83:%.*]] = mul i64 [[TMP81]], [[TMP82]] +; CHECK-NEXT: [[TMP84:%.*]] = trunc i64 [[TMP83]] to i32 +; CHECK-NEXT: [[TMP85:%.*]] = lshr i64 [[TMP83]], 32 +; CHECK-NEXT: [[TMP86:%.*]] = trunc i64 [[TMP85]] to i32 +; CHECK-NEXT: [[TMP87:%.*]] = mul i32 [[TMP86]], [[TMP58]] +; CHECK-NEXT: [[TMP88:%.*]] = sub i32 [[TMP57]], [[TMP87]] +; CHECK-NEXT: [[TMP89:%.*]] = icmp uge i32 [[TMP88]], [[TMP58]] +; CHECK-NEXT: [[TMP90:%.*]] = icmp uge i32 [[TMP57]], [[TMP87]] +; CHECK-NEXT: [[TMP91:%.*]] = and i1 [[TMP89]], [[TMP90]] +; CHECK-NEXT: [[TMP92:%.*]] = add i32 [[TMP86]], 1 +; CHECK-NEXT: [[TMP93:%.*]] = sub i32 [[TMP86]], 1 +; CHECK-NEXT: [[TMP94:%.*]] = select i1 [[TMP91]], i32 [[TMP92]], i32 [[TMP86]] +; CHECK-NEXT: [[TMP95:%.*]] = select i1 [[TMP90]], i32 [[TMP94]], i32 [[TMP93]] +; CHECK-NEXT: [[TMP96:%.*]] = xor i32 [[TMP95]], [[TMP54]] +; CHECK-NEXT: [[TMP97:%.*]] = sub i32 [[TMP96]], [[TMP54]] +; CHECK-NEXT: [[TMP98:%.*]] = insertelement <2 x i32> [[TMP49]], i32 [[TMP97]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP98]], <2 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: sdiv_v2i32_pow2_shl_denom: @@ -5252,70 +5174,64 @@ define amdgpu_kernel void @srem_v2i32_pow2_shl_denom(<2 x i32> addrspace(1)* %ou ; CHECK-NEXT: [[TMP37:%.*]] = mul i32 [[TMP36]], [[TMP8]] ; CHECK-NEXT: [[TMP38:%.*]] = sub i32 [[TMP7]], [[TMP37]] ; CHECK-NEXT: [[TMP39:%.*]] = icmp uge i32 [[TMP38]], [[TMP8]] -; CHECK-NEXT: [[TMP40:%.*]] = select i1 [[TMP39]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP41:%.*]] = icmp uge i32 [[TMP7]], [[TMP37]] -; CHECK-NEXT: [[TMP42:%.*]] = select i1 [[TMP41]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP43:%.*]] = and i32 [[TMP40]], [[TMP42]] -; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i32 [[TMP43]], 0 -; CHECK-NEXT: [[TMP45:%.*]] = sub i32 [[TMP38]], [[TMP8]] -; CHECK-NEXT: [[TMP46:%.*]] = add i32 [[TMP38]], [[TMP8]] -; CHECK-NEXT: [[TMP47:%.*]] = select i1 [[TMP44]], i32 [[TMP38]], i32 [[TMP45]] -; CHECK-NEXT: [[TMP48:%.*]] = select i1 [[TMP41]], i32 [[TMP47]], i32 [[TMP46]] -; CHECK-NEXT: [[TMP49:%.*]] = xor i32 [[TMP48]], [[TMP3]] -; CHECK-NEXT: [[TMP50:%.*]] = sub i32 [[TMP49]], [[TMP3]] -; CHECK-NEXT: [[TMP51:%.*]] = insertelement <2 x i32> undef, i32 [[TMP50]], i64 0 -; CHECK-NEXT: [[TMP52:%.*]] = extractelement <2 x i32> [[X]], i64 1 -; CHECK-NEXT: [[TMP53:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 -; CHECK-NEXT: [[TMP54:%.*]] = ashr i32 [[TMP52]], 31 -; CHECK-NEXT: [[TMP55:%.*]] = ashr i32 [[TMP53]], 31 -; CHECK-NEXT: [[TMP56:%.*]] = add i32 [[TMP52]], [[TMP54]] -; CHECK-NEXT: [[TMP57:%.*]] = add i32 [[TMP53]], [[TMP55]] -; CHECK-NEXT: [[TMP58:%.*]] = xor i32 [[TMP56]], [[TMP54]] -; CHECK-NEXT: [[TMP59:%.*]] = xor i32 [[TMP57]], [[TMP55]] -; CHECK-NEXT: [[TMP60:%.*]] = uitofp i32 [[TMP59]] to float -; CHECK-NEXT: [[TMP61:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP60]]) -; CHECK-NEXT: [[TMP62:%.*]] = fmul fast float [[TMP61]], 0x41F0000000000000 -; CHECK-NEXT: [[TMP63:%.*]] = fptoui float [[TMP62]] to i32 -; CHECK-NEXT: [[TMP64:%.*]] = zext i32 [[TMP63]] to i64 -; CHECK-NEXT: [[TMP65:%.*]] = zext i32 [[TMP59]] to i64 -; CHECK-NEXT: [[TMP66:%.*]] = mul i64 [[TMP64]], [[TMP65]] -; CHECK-NEXT: [[TMP67:%.*]] = trunc i64 [[TMP66]] to i32 -; CHECK-NEXT: [[TMP68:%.*]] = lshr i64 [[TMP66]], 32 -; CHECK-NEXT: [[TMP69:%.*]] = trunc i64 [[TMP68]] to i32 -; CHECK-NEXT: [[TMP70:%.*]] = sub i32 0, [[TMP67]] -; CHECK-NEXT: [[TMP71:%.*]] = icmp eq i32 [[TMP69]], 0 -; CHECK-NEXT: [[TMP72:%.*]] = select i1 [[TMP71]], i32 [[TMP70]], i32 [[TMP67]] -; CHECK-NEXT: [[TMP73:%.*]] = zext i32 [[TMP72]] to i64 -; CHECK-NEXT: [[TMP74:%.*]] = zext i32 [[TMP63]] to i64 -; CHECK-NEXT: [[TMP75:%.*]] = mul i64 [[TMP73]], [[TMP74]] -; CHECK-NEXT: [[TMP76:%.*]] = trunc i64 [[TMP75]] to i32 -; CHECK-NEXT: [[TMP77:%.*]] = lshr i64 [[TMP75]], 32 -; CHECK-NEXT: [[TMP78:%.*]] = trunc i64 [[TMP77]] to i32 -; CHECK-NEXT: [[TMP79:%.*]] = add i32 [[TMP63]], [[TMP78]] -; CHECK-NEXT: [[TMP80:%.*]] = sub i32 [[TMP63]], [[TMP78]] -; CHECK-NEXT: [[TMP81:%.*]] = select i1 [[TMP71]], i32 [[TMP79]], i32 [[TMP80]] -; CHECK-NEXT: [[TMP82:%.*]] = zext i32 [[TMP81]] to i64 -; CHECK-NEXT: [[TMP83:%.*]] = zext i32 [[TMP58]] to i64 -; CHECK-NEXT: [[TMP84:%.*]] = mul i64 [[TMP82]], [[TMP83]] -; CHECK-NEXT: [[TMP85:%.*]] = trunc i64 [[TMP84]] to i32 -; CHECK-NEXT: [[TMP86:%.*]] = lshr i64 [[TMP84]], 32 -; CHECK-NEXT: [[TMP87:%.*]] = trunc i64 [[TMP86]] to i32 -; CHECK-NEXT: [[TMP88:%.*]] = mul i32 [[TMP87]], [[TMP59]] -; CHECK-NEXT: [[TMP89:%.*]] = sub i32 [[TMP58]], [[TMP88]] -; CHECK-NEXT: [[TMP90:%.*]] = icmp uge i32 [[TMP89]], [[TMP59]] -; CHECK-NEXT: [[TMP91:%.*]] = select i1 [[TMP90]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP92:%.*]] = icmp uge i32 [[TMP58]], [[TMP88]] -; CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP92]], i32 -1, i32 0 -; CHECK-NEXT: [[TMP94:%.*]] = and i32 [[TMP91]], [[TMP93]] -; CHECK-NEXT: [[TMP95:%.*]] = icmp eq i32 [[TMP94]], 0 -; CHECK-NEXT: [[TMP96:%.*]] = sub i32 [[TMP89]], [[TMP59]] -; CHECK-NEXT: [[TMP97:%.*]] = add i32 [[TMP89]], [[TMP59]] -; CHECK-NEXT: [[TMP98:%.*]] = select i1 [[TMP95]], i32 [[TMP89]], i32 [[TMP96]] -; CHECK-NEXT: [[TMP99:%.*]] = select i1 [[TMP92]], i32 [[TMP98]], i32 [[TMP97]] -; CHECK-NEXT: [[TMP100:%.*]] = xor i32 [[TMP99]], [[TMP54]] -; CHECK-NEXT: [[TMP101:%.*]] = sub i32 [[TMP100]], [[TMP54]] -; CHECK-NEXT: [[TMP102:%.*]] = insertelement <2 x i32> [[TMP51]], i32 [[TMP101]], i64 1 -; CHECK-NEXT: store <2 x i32> [[TMP102]], <2 x i32> addrspace(1)* [[OUT:%.*]] +; CHECK-NEXT: [[TMP40:%.*]] = icmp uge i32 [[TMP7]], [[TMP37]] +; CHECK-NEXT: [[TMP41:%.*]] = and i1 [[TMP39]], [[TMP40]] +; CHECK-NEXT: [[TMP42:%.*]] = sub i32 [[TMP38]], [[TMP8]] +; CHECK-NEXT: [[TMP43:%.*]] = add i32 [[TMP38]], [[TMP8]] +; CHECK-NEXT: [[TMP44:%.*]] = select i1 [[TMP41]], i32 [[TMP42]], i32 [[TMP38]] +; CHECK-NEXT: [[TMP45:%.*]] = select i1 [[TMP40]], i32 [[TMP44]], i32 [[TMP43]] +; CHECK-NEXT: [[TMP46:%.*]] = xor i32 [[TMP45]], [[TMP3]] +; CHECK-NEXT: [[TMP47:%.*]] = sub i32 [[TMP46]], [[TMP3]] +; CHECK-NEXT: [[TMP48:%.*]] = insertelement <2 x i32> undef, i32 [[TMP47]], i64 0 +; CHECK-NEXT: [[TMP49:%.*]] = extractelement <2 x i32> [[X]], i64 1 +; CHECK-NEXT: [[TMP50:%.*]] = extractelement <2 x i32> [[SHL_Y]], i64 1 +; CHECK-NEXT: [[TMP51:%.*]] = ashr i32 [[TMP49]], 31 +; CHECK-NEXT: [[TMP52:%.*]] = ashr i32 [[TMP50]], 31 +; CHECK-NEXT: [[TMP53:%.*]] = add i32 [[TMP49]], [[TMP51]] +; CHECK-NEXT: [[TMP54:%.*]] = add i32 [[TMP50]], [[TMP52]] +; CHECK-NEXT: [[TMP55:%.*]] = xor i32 [[TMP53]], [[TMP51]] +; CHECK-NEXT: [[TMP56:%.*]] = xor i32 [[TMP54]], [[TMP52]] +; CHECK-NEXT: [[TMP57:%.*]] = uitofp i32 [[TMP56]] to float +; CHECK-NEXT: [[TMP58:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP57]]) +; CHECK-NEXT: [[TMP59:%.*]] = fmul fast float [[TMP58]], 0x41F0000000000000 +; CHECK-NEXT: [[TMP60:%.*]] = fptoui float [[TMP59]] to i32 +; CHECK-NEXT: [[TMP61:%.*]] = zext i32 [[TMP60]] to i64 +; CHECK-NEXT: [[TMP62:%.*]] = zext i32 [[TMP56]] to i64 +; CHECK-NEXT: [[TMP63:%.*]] = mul i64 [[TMP61]], [[TMP62]] +; CHECK-NEXT: [[TMP64:%.*]] = trunc i64 [[TMP63]] to i32 +; CHECK-NEXT: [[TMP65:%.*]] = lshr i64 [[TMP63]], 32 +; CHECK-NEXT: [[TMP66:%.*]] = trunc i64 [[TMP65]] to i32 +; CHECK-NEXT: [[TMP67:%.*]] = sub i32 0, [[TMP64]] +; CHECK-NEXT: [[TMP68:%.*]] = icmp eq i32 [[TMP66]], 0 +; CHECK-NEXT: [[TMP69:%.*]] = select i1 [[TMP68]], i32 [[TMP67]], i32 [[TMP64]] +; CHECK-NEXT: [[TMP70:%.*]] = zext i32 [[TMP69]] to i64 +; CHECK-NEXT: [[TMP71:%.*]] = zext i32 [[TMP60]] to i64 +; CHECK-NEXT: [[TMP72:%.*]] = mul i64 [[TMP70]], [[TMP71]] +; CHECK-NEXT: [[TMP73:%.*]] = trunc i64 [[TMP72]] to i32 +; CHECK-NEXT: [[TMP74:%.*]] = lshr i64 [[TMP72]], 32 +; CHECK-NEXT: [[TMP75:%.*]] = trunc i64 [[TMP74]] to i32 +; CHECK-NEXT: [[TMP76:%.*]] = add i32 [[TMP60]], [[TMP75]] +; CHECK-NEXT: [[TMP77:%.*]] = sub i32 [[TMP60]], [[TMP75]] +; CHECK-NEXT: [[TMP78:%.*]] = select i1 [[TMP68]], i32 [[TMP76]], i32 [[TMP77]] +; CHECK-NEXT: [[TMP79:%.*]] = zext i32 [[TMP78]] to i64 +; CHECK-NEXT: [[TMP80:%.*]] = zext i32 [[TMP55]] to i64 +; CHECK-NEXT: [[TMP81:%.*]] = mul i64 [[TMP79]], [[TMP80]] +; CHECK-NEXT: [[TMP82:%.*]] = trunc i64 [[TMP81]] to i32 +; CHECK-NEXT: [[TMP83:%.*]] = lshr i64 [[TMP81]], 32 +; CHECK-NEXT: [[TMP84:%.*]] = trunc i64 [[TMP83]] to i32 +; CHECK-NEXT: [[TMP85:%.*]] = mul i32 [[TMP84]], [[TMP56]] +; CHECK-NEXT: [[TMP86:%.*]] = sub i32 [[TMP55]], [[TMP85]] +; CHECK-NEXT: [[TMP87:%.*]] = icmp uge i32 [[TMP86]], [[TMP56]] +; CHECK-NEXT: [[TMP88:%.*]] = icmp uge i32 [[TMP55]], [[TMP85]] +; CHECK-NEXT: [[TMP89:%.*]] = and i1 [[TMP87]], [[TMP88]] +; CHECK-NEXT: [[TMP90:%.*]] = sub i32 [[TMP86]], [[TMP56]] +; CHECK-NEXT: [[TMP91:%.*]] = add i32 [[TMP86]], [[TMP56]] +; CHECK-NEXT: [[TMP92:%.*]] = select i1 [[TMP89]], i32 [[TMP90]], i32 [[TMP86]] +; CHECK-NEXT: [[TMP93:%.*]] = select i1 [[TMP88]], i32 [[TMP92]], i32 [[TMP91]] +; CHECK-NEXT: [[TMP94:%.*]] = xor i32 [[TMP93]], [[TMP51]] +; CHECK-NEXT: [[TMP95:%.*]] = sub i32 [[TMP94]], [[TMP51]] +; CHECK-NEXT: [[TMP96:%.*]] = insertelement <2 x i32> [[TMP48]], i32 [[TMP95]], i64 1 +; CHECK-NEXT: store <2 x i32> [[TMP96]], <2 x i32> addrspace(1)* [[OUT:%.*]] ; CHECK-NEXT: ret void ; ; GCN-LABEL: srem_v2i32_pow2_shl_denom: -- GitLab From d797e33cc083c186103e0cb9aeb016913b96fd08 Mon Sep 17 00:00:00 2001 From: Davide Italiano Date: Tue, 11 Feb 2020 20:30:12 -0800 Subject: [PATCH 110/142] [TestConstVariable] Clean-up XFAIL lists. These versions of `clang` are ancient history. --- .../API/lang/c/const_variables/TestConstVariables.py | 9 --------- 1 file changed, 9 deletions(-) diff --git a/lldb/test/API/lang/c/const_variables/TestConstVariables.py b/lldb/test/API/lang/c/const_variables/TestConstVariables.py index 59fa6bcb0a1b..2cc94369f38d 100644 --- a/lldb/test/API/lang/c/const_variables/TestConstVariables.py +++ b/lldb/test/API/lang/c/const_variables/TestConstVariables.py @@ -12,15 +12,6 @@ class ConstVariableTestCase(TestBase): mydir = TestBase.compute_mydir(__file__) - @expectedFailureAll( - oslist=["freebsd", "linux"], - compiler="clang", compiler_version=["<", "3.5"]) - @expectedFailureAll( - oslist=["freebsd", "linux"], - compiler="clang", compiler_version=["=", "3.7"]) - @expectedFailureAll( - oslist=["freebsd", "linux"], - compiler="clang", compiler_version=["=", "3.8"]) @expectedFailureAll(oslist=["freebsd", "linux"], compiler="icc") @expectedFailureAll(archs=['mips', 'mipsel', 'mips64', 'mips64el']) @expectedFailureAll( -- GitLab From 80a34ae31125aa46dcad47162ba45b152aed968d Mon Sep 17 00:00:00 2001 From: Yuanfang Chen Date: Tue, 11 Feb 2020 20:39:34 -0800 Subject: [PATCH 111/142] Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"" This reverts commit rGcd5b308b828e, rGcd5b308b828e, rG8cedf0e2994c. There are issues to be investigated for polly bots and bots turning on EXPENSIVE_CHECKS. --- .../infrastructure/empty-database.cpp | 2 +- .../libclang/CrashTests/LibclangCrashTest.cpp | 6 ++-- lld/test/ELF/lto/ltopasses-custom.ll | 4 +-- llvm/docs/ProgrammersManual.rst | 4 +-- llvm/include/llvm/Support/ErrorHandling.h | 2 +- llvm/lib/Support/ErrorHandling.cpp | 2 +- ...talayout-invalid-function-ptr-alignment.ll | 2 +- ...alayout-invalid-stack-natural-alignment.ll | 2 +- llvm/test/Assembler/getInt.ll | 2 +- .../invalid-datalayout-alloca-addrspace.ll | 2 +- .../invalid-datalayout-program-addrspace.ll | 2 +- llvm/test/Assembler/invalid-datalayout1.ll | 2 +- llvm/test/Assembler/invalid-datalayout10.ll | 2 +- llvm/test/Assembler/invalid-datalayout11.ll | 2 +- llvm/test/Assembler/invalid-datalayout12.ll | 2 +- llvm/test/Assembler/invalid-datalayout13.ll | 2 +- llvm/test/Assembler/invalid-datalayout14.ll | 2 +- llvm/test/Assembler/invalid-datalayout15.ll | 2 +- llvm/test/Assembler/invalid-datalayout16.ll | 2 +- llvm/test/Assembler/invalid-datalayout17.ll | 2 +- llvm/test/Assembler/invalid-datalayout18.ll | 2 +- llvm/test/Assembler/invalid-datalayout19.ll | 2 +- llvm/test/Assembler/invalid-datalayout2.ll | 2 +- llvm/test/Assembler/invalid-datalayout20.ll | 2 +- llvm/test/Assembler/invalid-datalayout21.ll | 2 +- llvm/test/Assembler/invalid-datalayout22.ll | 2 +- llvm/test/Assembler/invalid-datalayout23.ll | 2 +- llvm/test/Assembler/invalid-datalayout24.ll | 2 +- llvm/test/Assembler/invalid-datalayout3.ll | 2 +- llvm/test/Assembler/invalid-datalayout4.ll | 2 +- llvm/test/Assembler/invalid-datalayout5.ll | 2 +- llvm/test/Assembler/invalid-datalayout6.ll | 2 +- llvm/test/Assembler/invalid-datalayout7.ll | 2 +- llvm/test/Assembler/invalid-datalayout8.ll | 2 +- llvm/test/Assembler/invalid-datalayout9.ll | 2 +- .../function-default-address-spaces.ll | 2 +- .../test/Bitcode/invalid-functionptr-align.ll | 2 +- llvm/test/Bitcode/invalid.test | 12 +++---- .../AArch64/GlobalISel/arm64-fallback.ll | 4 +-- .../GlobalISel/call-translator-musttail.ll | 2 +- .../GlobalISel/legalize-inttoptr-xfail-1.mir | 3 +- .../GlobalISel/legalize-inttoptr-xfail-2.mir | 3 +- .../AArch64/GlobalISel/no-neon-no-fp.ll | 2 +- .../CodeGen/AArch64/arm64-named-reg-alloc.ll | 4 +-- .../AArch64/arm64-named-reg-notareg.ll | 4 +-- .../CodeGen/AArch64/arm64-tls-dynamics.ll | 2 +- .../CodeGen/AArch64/arm64-tls-initial-exec.ll | 2 +- .../CodeGen/AArch64/fast-isel-sp-adjust.ll | 2 +- llvm/test/CodeGen/AArch64/tiny_supported.ll | 6 ++-- .../AMDGPU/GlobalISel/insertelement.ll | 2 +- .../inst-select-pattern-xor3.xfail.mir | 2 +- .../AMDGPU/GlobalISel/lds-zero-initializer.ll | 2 +- .../GlobalISel/legalize-atomicrmw-nand.mir | 2 +- .../legalize-atomicrmw-xchg-flat.mir | 2 +- .../AMDGPU/GlobalISel/legalize-jump-table.mir | 2 +- .../legalize-unmerge-values-xfail.mir | 2 +- .../llvm.amdgcn.ds.gws.sema.release.all.ll | 2 +- .../GlobalISel/regbankselect-illegal-copy.mir | 4 +-- .../AMDGPU/at-least-one-def-value-assert.mir | 2 +- .../test/CodeGen/AMDGPU/branch-relax-spill.ll | 2 +- .../AMDGPU/call-to-kernel-undefined.ll | 2 +- llvm/test/CodeGen/AMDGPU/call-to-kernel.ll | 2 +- .../test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll | 6 ++-- llvm/test/CodeGen/AMDGPU/div_i128.ll | 2 +- .../AMDGPU/flat-error-unsupported-gpu-hsa.ll | 6 ++-- llvm/test/CodeGen/AMDGPU/lds-initializer.ll | 4 +-- .../CodeGen/AMDGPU/lds-zero-initializer.ll | 4 +-- .../llvm.amdgcn.ds.gws.sema.release.all.ll | 2 +- .../AMDGPU/read-register-invalid-subtarget.ll | 2 +- .../AMDGPU/read-register-invalid-type-i32.ll | 2 +- .../AMDGPU/read-register-invalid-type-i64.ll | 2 +- .../CodeGen/AMDGPU/unsupported-image-a16.ll | 2 +- llvm/test/CodeGen/AMDGPU/verify-sop.mir | 2 +- llvm/test/CodeGen/ARM/codemodel.ll | 4 +-- llvm/test/CodeGen/ARM/ldc2l.ll | 4 +-- llvm/test/CodeGen/ARM/machine-verifier.mir | 2 +- llvm/test/CodeGen/ARM/named-reg-alloc.ll | 4 +-- llvm/test/CodeGen/ARM/named-reg-notareg.ll | 4 +-- llvm/test/CodeGen/ARM/special-reg-acore.ll | 2 +- llvm/test/CodeGen/ARM/special-reg-mcore.ll | 4 +-- llvm/test/CodeGen/ARM/special-reg-v8m-base.ll | 2 +- llvm/test/CodeGen/ARM/special-reg-v8m-main.ll | 2 +- llvm/test/CodeGen/ARM/ssat-lower.ll | 4 +-- llvm/test/CodeGen/ARM/ssat-upper.ll | 4 +-- llvm/test/CodeGen/ARM/ssat-v4t.ll | 2 +- llvm/test/CodeGen/ARM/stc2.ll | 4 +-- llvm/test/CodeGen/ARM/usat-lower.ll | 4 +-- llvm/test/CodeGen/ARM/usat-upper.ll | 4 +-- llvm/test/CodeGen/ARM/usat-v4t.ll | 2 +- llvm/test/CodeGen/BPF/sdiv_error.ll | 2 +- llvm/test/CodeGen/BPF/xadd.ll | 8 ++--- .../Generic/llc-start-stop-instance-errors.ll | 2 +- llvm/test/CodeGen/Generic/llc-start-stop.ll | 12 +++---- .../Generic/opt-codegen-no-target-machine.ll | 2 +- .../CodeGen/Hexagon/misaligned-const-load.ll | 2 +- .../CodeGen/Hexagon/misaligned-const-store.ll | 2 +- .../Hexagon/verify-liveness-at-def.mir | 4 +-- llvm/test/CodeGen/Lanai/codemodel.ll | 4 +-- .../test/CodeGen/MIR/X86/machine-verifier.mir | 2 +- .../MIR/X86/tied-physical-regs-match.mir | 2 +- .../test/CodeGen/Mips/Fast-ISel/double-arg.ll | 2 +- .../fast-isel-softfloat-lower-args.ll | 2 +- llvm/test/CodeGen/Mips/cpus-no-mips64.ll | 14 ++++---- llvm/test/CodeGen/Mips/cpus.ll | 4 +-- llvm/test/CodeGen/Mips/fp64a.ll | 6 ++-- llvm/test/CodeGen/Mips/fpxx.ll | 4 +-- .../guards-verify-call.mir | 2 +- .../guards-verify-tailcall.mir | 2 +- .../unsupported-micromips.ll | 2 +- .../unsupported-mips32.ll | 2 +- .../test/CodeGen/Mips/instverify/dext-pos.mir | 2 +- .../CodeGen/Mips/instverify/dext-size.mir | 2 +- .../Mips/instverify/dextm-pos-size.mir | 2 +- .../CodeGen/Mips/instverify/dextm-pos.mir | 2 +- .../CodeGen/Mips/instverify/dextm-size.mir | 2 +- .../Mips/instverify/dextu-pos-size.mir | 2 +- .../CodeGen/Mips/instverify/dextu-pos.mir | 2 +- .../CodeGen/Mips/instverify/dextu-size.mir | 2 +- .../CodeGen/Mips/instverify/dins-pos-size.mir | 2 +- .../test/CodeGen/Mips/instverify/dins-pos.mir | 2 +- .../CodeGen/Mips/instverify/dins-size.mir | 2 +- .../Mips/instverify/dinsm-pos-size.mir | 2 +- .../CodeGen/Mips/instverify/dinsm-pos.mir | 2 +- .../CodeGen/Mips/instverify/dinsm-size.mir | 2 +- .../Mips/instverify/dinsu-pos-size.mir | 2 +- .../CodeGen/Mips/instverify/dinsu-pos.mir | 2 +- .../CodeGen/Mips/instverify/dinsu-size.mir | 2 +- .../CodeGen/Mips/instverify/ext-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ext-pos.mir | 2 +- .../test/CodeGen/Mips/instverify/ext-size.mir | 2 +- .../CodeGen/Mips/instverify/ins-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ins-pos.mir | 2 +- .../test/CodeGen/Mips/instverify/ins-size.mir | 2 +- .../CodeGen/Mips/interrupt-attr-64-error.ll | 2 +- .../CodeGen/Mips/interrupt-attr-args-error.ll | 2 +- .../test/CodeGen/Mips/interrupt-attr-error.ll | 2 +- .../CodeGen/Mips/micromips64-unsupported.ll | 4 +-- .../CodeGen/Mips/mips32r6/compatibility.ll | 2 +- .../CodeGen/Mips/mips64r6/compatibility.ll | 2 +- llvm/test/CodeGen/Mips/msa/3r-a.ll | 2 +- llvm/test/CodeGen/Mips/msa/immediates-bad.ll | 2 +- llvm/test/CodeGen/NVPTX/alias.ll | 2 +- llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll | 2 +- llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll | 2 +- llvm/test/CodeGen/NVPTX/global-ctor.ll | 2 +- llvm/test/CodeGen/NVPTX/global-dtor.ll | 2 +- .../test/CodeGen/NVPTX/libcall-instruction.ll | 2 +- llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-byval-param.ll | 4 +-- llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll | 4 +-- llvm/test/CodeGen/PowerPC/aix-nest-param.ll | 4 +-- llvm/test/CodeGen/PowerPC/aix-trampoline.ll | 4 +-- .../PowerPC/aix-user-defined-memcpy.ll | 2 +- .../PowerPC/aix-xcoff-data-only-notoc.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll | 2 +- llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll | 2 +- llvm/test/CodeGen/PowerPC/codemodel.ll | 4 +-- .../CodeGen/PowerPC/lower-globaladdr32-aix.ll | 2 +- .../CodeGen/PowerPC/lower-globaladdr64-aix.ll | 2 +- .../CodeGen/PowerPC/named-reg-alloc-r0.ll | 6 ++-- .../CodeGen/PowerPC/named-reg-alloc-r2-64.ll | 4 +-- .../CodeGen/PowerPC/named-reg-alloc-r2.ll | 2 +- llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll | 2 +- .../CodeGen/RISCV/get-register-invalid.ll | 2 +- .../CodeGen/RISCV/get-register-reserve.ll | 4 +-- .../RISCV/interrupt-attr-args-error.ll | 4 +-- .../CodeGen/RISCV/interrupt-attr-invalid.ll | 4 +-- .../CodeGen/RISCV/interrupt-attr-ret-error.ll | 4 +-- .../RISCV/mattr-invalid-combination.ll | 2 +- llvm/test/CodeGen/RISCV/module-target-abi.ll | 2 +- llvm/test/CodeGen/RISCV/module-target-abi2.ll | 2 +- llvm/test/CodeGen/RISCV/musttail-call.ll | 8 ++--- llvm/test/CodeGen/RISCV/rv32e.ll | 2 +- llvm/test/CodeGen/RISCV/target-abi-valid.ll | 2 +- llvm/test/CodeGen/RISCV/verify-instr.mir | 2 +- llvm/test/CodeGen/SPARC/codemodel.ll | 4 +-- llvm/test/CodeGen/SPARC/fail-alloca-align.ll | 4 +-- llvm/test/CodeGen/SPARC/sret-secondary.ll | 2 +- llvm/test/CodeGen/SystemZ/codemodel.ll | 4 +-- llvm/test/CodeGen/SystemZ/ghc-cc-02.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-03.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-04.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-05.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-06.ll | 2 +- llvm/test/CodeGen/SystemZ/ghc-cc-07.ll | 2 +- llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll | 2 +- .../test/CodeGen/SystemZ/mrecord-mcount-02.ll | 2 +- llvm/test/CodeGen/SystemZ/mverify-optypes.mir | 3 +- .../test/CodeGen/SystemZ/vec-args-error-01.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-02.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-03.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-04.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-05.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-06.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-07.ll | 2 +- .../test/CodeGen/SystemZ/vec-args-error-08.ll | 2 +- llvm/test/CodeGen/WebAssembly/clear-cache.ll | 2 +- llvm/test/CodeGen/WebAssembly/cpus.ll | 8 ++--- llvm/test/CodeGen/WebAssembly/exception.ll | 2 +- .../CodeGen/WebAssembly/offset-atomics.ll | 2 +- .../WebAssembly/tls-general-dynamic.ll | 4 +-- llvm/test/CodeGen/X86/AppendingLinkage.ll | 2 +- .../X86/GlobalISel/avoid-matchtable-crash.mir | 2 +- ...fi-inserter-verify-inconsistent-offset.mir | 2 +- ...-inserter-verify-inconsistent-register.mir | 2 +- llvm/test/CodeGen/X86/clwb.ll | 2 +- llvm/test/CodeGen/X86/codemodel.ll | 2 +- llvm/test/CodeGen/X86/coff-comdat2.ll | 2 +- llvm/test/CodeGen/X86/coff-comdat3.ll | 2 +- llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll | 18 +++++------ llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll | 32 +++++++++---------- llvm/test/CodeGen/X86/cpus-no-x86_64.ll | 8 ++--- llvm/test/CodeGen/X86/equiv_with_fndef.ll | 2 +- llvm/test/CodeGen/X86/equiv_with_vardef.ll | 2 +- .../expand-integer-x86_64-intrinsic-error.ll | 2 +- llvm/test/CodeGen/X86/fast-isel-args-fail2.ll | 3 +- llvm/test/CodeGen/X86/inalloca-regparm.ll | 2 +- .../X86/inline-asm-avx-v-constraint-32bit.ll | 2 -- .../inline-asm-avx512vl-v-constraint-32bit.ll | 2 -- llvm/test/CodeGen/X86/invalid-liveness.mir | 2 +- llvm/test/CodeGen/X86/label-redefinition.ll | 2 +- .../CodeGen/X86/llc-print-machineinstrs.mir | 2 +- llvm/test/CodeGen/X86/macho-comdat.ll | 2 +- llvm/test/CodeGen/X86/named-reg-alloc.ll | 4 +-- llvm/test/CodeGen/X86/named-reg-notareg.ll | 4 +-- llvm/test/CodeGen/X86/nonconst-static-ev.ll | 2 +- llvm/test/CodeGen/X86/nonconst-static-iv.ll | 2 +- .../CodeGen/X86/read-fp-no-frame-pointer.ll | 2 +- llvm/test/CodeGen/X86/segmented-stacks.ll | 4 +-- llvm/test/CodeGen/XCore/alignment.ll | 2 +- llvm/test/CodeGen/XCore/codemodel.ll | 6 ++-- llvm/test/CodeGen/XCore/section-name.ll | 2 +- .../DebugInfo/COFF/types-recursive-unnamed.ll | 2 +- llvm/test/LTO/X86/attrs.ll | 2 +- .../illegal-subtarget-change.s | 2 +- llvm/test/MC/ARM/Windows/invalid-relocation.s | 2 +- llvm/test/MC/COFF/section-comdat-conflict.s | 2 +- llvm/test/MC/COFF/section-comdat-conflict2.s | 2 +- .../MC/Disassembler/AMDGPU/si-support.txt | 2 +- llvm/test/MC/ELF/ARM/bss-non-zero-value.s | 2 +- llvm/test/MC/ELF/common-error3.s | 4 +-- .../MC/ELF/section-numeric-invalid-type.s | 2 +- llvm/test/MC/MachO/variable-errors.s | 2 +- llvm/test/MC/Mips/micromips64-unsupported.s | 8 ++--- llvm/test/MC/Mips/micromips64r6-unsupported.s | 2 +- llvm/test/MC/Mips/nooddspreg-cmdarg.s | 4 +-- .../test/MC/PowerPC/ppc64-localentry-error1.s | 4 +-- .../test/MC/PowerPC/ppc64-localentry-error2.s | 4 +-- llvm/test/MC/PowerPC/pr24686.s | 2 +- .../test/MC/RISCV/mattr-invalid-combination.s | 2 +- llvm/test/MC/WebAssembly/blockaddress.ll | 2 +- .../data-symbol-in-text-section.ll | 2 +- .../bundle-group-too-large-error.s | 4 +-- .../bundle-lock-option-error.s | 2 +- .../bundle-subtarget-change-error.s | 4 +-- .../lock-without-bundle-mode-error.s | 2 +- .../switch-section-locked-error.s | 2 +- .../unlock-without-lock-error.s | 2 +- llvm/test/MC/X86/check-end-of-data-region.s | 2 +- llvm/test/MC/X86/encoder-fail.s | 2 +- llvm/test/MC/X86/invalid-sleb.s | 2 +- llvm/test/MC/X86/reloc-bss.s | 2 +- llvm/test/MachineVerifier/live-ins-01.mir | 2 +- llvm/test/MachineVerifier/live-ins-02.mir | 2 +- llvm/test/MachineVerifier/live-ins-03.mir | 2 +- llvm/test/MachineVerifier/test_copy.mir | 2 +- .../test_copy_mismatch_types.mir | 2 +- llvm/test/MachineVerifier/test_g_add.mir | 2 +- .../MachineVerifier/test_g_addrspacecast.mir | 2 +- llvm/test/MachineVerifier/test_g_bitcast.mir | 2 +- llvm/test/MachineVerifier/test_g_brjt.mir | 2 +- .../MachineVerifier/test_g_build_vector.mir | 2 +- .../test_g_build_vector_trunc.mir | 2 +- .../MachineVerifier/test_g_concat_vectors.mir | 2 +- llvm/test/MachineVerifier/test_g_constant.mir | 2 +- .../MachineVerifier/test_g_dyn_stackalloc.mir | 2 +- llvm/test/MachineVerifier/test_g_extract.mir | 2 +- llvm/test/MachineVerifier/test_g_fcmp.mir | 2 +- .../test/MachineVerifier/test_g_fconstant.mir | 2 +- llvm/test/MachineVerifier/test_g_icmp.mir | 2 +- llvm/test/MachineVerifier/test_g_insert.mir | 2 +- .../test/MachineVerifier/test_g_intrinsic.mir | 2 +- .../test_g_intrinsic_w_side_effects.mir | 2 +- llvm/test/MachineVerifier/test_g_inttoptr.mir | 2 +- .../MachineVerifier/test_g_jump_table.mir | 2 +- llvm/test/MachineVerifier/test_g_load.mir | 2 +- .../MachineVerifier/test_g_merge_values.mir | 2 +- llvm/test/MachineVerifier/test_g_phi.mir | 2 +- llvm/test/MachineVerifier/test_g_ptr_add.mir | 2 +- llvm/test/MachineVerifier/test_g_ptrtoint.mir | 2 +- llvm/test/MachineVerifier/test_g_select.mir | 2 +- .../MachineVerifier/test_g_sext_inreg.mir | 2 +- llvm/test/MachineVerifier/test_g_sextload.mir | 2 +- .../MachineVerifier/test_g_shuffle_vector.mir | 2 +- llvm/test/MachineVerifier/test_g_store.mir | 2 +- llvm/test/MachineVerifier/test_g_trunc.mir | 2 +- llvm/test/MachineVerifier/test_g_zextload.mir | 2 +- .../test_memccpy_intrinsics.mir | 2 +- .../test_phis_precede_nonphis.mir | 2 +- .../verifier-generic-extend-truncate.mir | 2 +- .../verifier-generic-types-1.mir | 2 +- .../verifier-generic-types-2.mir | 2 +- ...licit-virtreg-invalid-physreg-liveness.mir | 2 +- .../MachineVerifier/verifier-phi-fail0.mir | 2 +- .../verifier-pseudo-terminators.mir | 2 +- .../verify-regbankselected.mir | 2 +- llvm/test/MachineVerifier/verify-regops.mir | 2 +- llvm/test/MachineVerifier/verify-selected.mir | 2 +- llvm/test/Object/coff-invalid.test | 2 +- llvm/test/Object/elf-invalid-phdr.test | 4 +-- llvm/test/Object/invalid.test | 2 +- llvm/test/Object/wasm-invalid-file.yaml | 2 +- .../Object/wasm-string-outside-section.test | 2 +- llvm/test/Other/close-stderr.ll | 13 ++++++++ .../test/Other/optimization-remarks-inline.ll | 2 +- llvm/test/TableGen/HwModeSelect.td | 2 +- .../BlockExtractor/invalid-block.ll | 2 +- .../BlockExtractor/invalid-function.ll | 2 +- .../Transforms/BlockExtractor/invalid-line.ll | 2 +- .../FunctionImport/not-prevailing.ll | 2 +- llvm/test/Transforms/GCOVProfiling/version.ll | 4 +-- .../InstCombine/limit-max-iterations.ll | 2 +- llvm/test/tools/llvm-lto2/X86/pipeline.ll | 4 +-- .../llvm-readobj/COFF/arm64-many-epilogs.s | 2 +- .../llvm-readobj/COFF/arm64-win-error2.s | 2 +- 328 files changed, 459 insertions(+), 446 deletions(-) create mode 100644 llvm/test/Other/close-stderr.ll diff --git a/clang-tools-extra/test/clang-tidy/infrastructure/empty-database.cpp b/clang-tools-extra/test/clang-tidy/infrastructure/empty-database.cpp index 54fe8910a9a9..b8707d6caaec 100644 --- a/clang-tools-extra/test/clang-tidy/infrastructure/empty-database.cpp +++ b/clang-tools-extra/test/clang-tidy/infrastructure/empty-database.cpp @@ -1,5 +1,5 @@ // UNSUPPORTED: system-windows -// RUN: not --crash clang-tidy -p %S/Inputs/empty-database %s 2>&1 | FileCheck %s +// RUN: not clang-tidy -p %S/Inputs/empty-database %s 2>&1 | FileCheck %s // CHECK: LLVM ERROR: Cannot chdir into ""! diff --git a/clang/unittests/libclang/CrashTests/LibclangCrashTest.cpp b/clang/unittests/libclang/CrashTests/LibclangCrashTest.cpp index 26c63cfbd427..3ccdb16cce4e 100644 --- a/clang/unittests/libclang/CrashTests/LibclangCrashTest.cpp +++ b/clang/unittests/libclang/CrashTests/LibclangCrashTest.cpp @@ -31,7 +31,7 @@ TEST_F(LibclangParseTest, UninstallAbortingLLVMFatalErrorHandler) { std::string Main = "main.h"; WriteFile(Main, "#pragma clang __debug llvm_fatal_error"); - EXPECT_DEATH(clang_parseTranslationUnit(Index, Main.c_str(), nullptr, 0, - nullptr, 0, TUFlags), - "ERROR"); + EXPECT_EXIT(clang_parseTranslationUnit( + Index, Main.c_str(), nullptr, 0, nullptr, 0, TUFlags), + ::testing::ExitedWithCode(1), "ERROR"); } diff --git a/lld/test/ELF/lto/ltopasses-custom.ll b/lld/test/ELF/lto/ltopasses-custom.ll index fd73f14d6571..f0322f8e4175 100644 --- a/lld/test/ELF/lto/ltopasses-custom.ll +++ b/lld/test/ELF/lto/ltopasses-custom.ll @@ -24,13 +24,13 @@ define void @barrier() { ; ATOMIC-NEXT: ret void ; Check that invalid passes are rejected gracefully. -; RUN: not --crash ld.lld -m elf_x86_64 %t.o -o %t2.so \ +; RUN: not ld.lld -m elf_x86_64 %t.o -o %t2.so \ ; RUN: --lto-newpm-passes=iamnotapass -shared 2>&1 | \ ; RUN: FileCheck %s --check-prefix=INVALID ; INVALID: unable to parse pass pipeline description 'iamnotapass': unknown pass name 'iamnotapass' ; Check that invalid AA pipelines are rejected gracefully. -; RUN: not --crash ld.lld -m elf_x86_64 %t.o -o %t2.so \ +; RUN: not ld.lld -m elf_x86_64 %t.o -o %t2.so \ ; RUN: --lto-newpm-passes=globaldce --lto-aa-pipeline=patatino \ ; RUN: -shared 2>&1 | \ ; RUN: FileCheck %s --check-prefix=INVALIDAA diff --git a/llvm/docs/ProgrammersManual.rst b/llvm/docs/ProgrammersManual.rst index 8f8fec611c48..98002f687a57 100644 --- a/llvm/docs/ProgrammersManual.rst +++ b/llvm/docs/ProgrammersManual.rst @@ -453,8 +453,8 @@ recovery. LLVM, there are places where this hasn't been practical to apply. In situations where you absolutely must emit a non-programmatic error and the ``Error`` model isn't workable you can call ``report_fatal_error``, - which will call installed error handlers, print a message, and abort the - program. The use of `report_fatal_error` in this case is discouraged. + which will call installed error handlers, print a message, and exit the + program. Recoverable errors are modeled using LLVM's ``Error`` scheme. This scheme represents errors using function return values, similar to classic C integer diff --git a/llvm/include/llvm/Support/ErrorHandling.h b/llvm/include/llvm/Support/ErrorHandling.h index 7678d8d6ba91..f75c2984a9ff 100644 --- a/llvm/include/llvm/Support/ErrorHandling.h +++ b/llvm/include/llvm/Support/ErrorHandling.h @@ -66,7 +66,7 @@ class StringRef; /// /// If no error handler is installed the default is to print the message to /// standard error, followed by a newline. -/// After the error handler is called this function will call abort(), it +/// After the error handler is called this function will call exit(1), it /// does not return. LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag = true); diff --git a/llvm/lib/Support/ErrorHandling.cpp b/llvm/lib/Support/ErrorHandling.cpp index f70a6921a41a..a9463024c420 100644 --- a/llvm/lib/Support/ErrorHandling.cpp +++ b/llvm/lib/Support/ErrorHandling.cpp @@ -123,7 +123,7 @@ void llvm::report_fatal_error(const Twine &Reason, bool GenCrashDiag) { // files registered with RemoveFileOnSignal. sys::RunInterruptHandlers(); - abort(); + sys::Process::Exit(1); } void llvm::install_bad_alloc_error_handler(fatal_error_handler_t handler, diff --git a/llvm/test/Assembler/datalayout-invalid-function-ptr-alignment.ll b/llvm/test/Assembler/datalayout-invalid-function-ptr-alignment.ll index 4203c5546c20..21cd6a6dc782 100644 --- a/llvm/test/Assembler/datalayout-invalid-function-ptr-alignment.ll +++ b/llvm/test/Assembler/datalayout-invalid-function-ptr-alignment.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as %s 2>&1 | FileCheck %s +; RUN: not llvm-as %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2 diff --git a/llvm/test/Assembler/datalayout-invalid-stack-natural-alignment.ll b/llvm/test/Assembler/datalayout-invalid-stack-natural-alignment.ll index 8fc18d86b1fa..c8d7ba62ab80 100644 --- a/llvm/test/Assembler/datalayout-invalid-stack-natural-alignment.ll +++ b/llvm/test/Assembler/datalayout-invalid-stack-natural-alignment.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as %s 2>&1 | FileCheck %s +; RUN: not llvm-as %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2 diff --git a/llvm/test/Assembler/getInt.ll b/llvm/test/Assembler/getInt.ll index 02f312b1bc6c..8e2537ae6cf1 100644 --- a/llvm/test/Assembler/getInt.ll +++ b/llvm/test/Assembler/getInt.ll @@ -1,3 +1,3 @@ -; RUN: not --crash opt < %s 2>&1 | grep 'not a number, or does not fit in an unsigned int' +; RUN: not opt < %s 2>&1 | grep 'not a number, or does not fit in an unsigned int' target datalayout = "p:4294967296:64:64" diff --git a/llvm/test/Assembler/invalid-datalayout-alloca-addrspace.ll b/llvm/test/Assembler/invalid-datalayout-alloca-addrspace.ll index 16670259ccf4..f0407da73e4f 100644 --- a/llvm/test/Assembler/invalid-datalayout-alloca-addrspace.ll +++ b/llvm/test/Assembler/invalid-datalayout-alloca-addrspace.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "A16777216" ; CHECK: Invalid address space, must be a 24-bit integer diff --git a/llvm/test/Assembler/invalid-datalayout-program-addrspace.ll b/llvm/test/Assembler/invalid-datalayout-program-addrspace.ll index fe0ab5c6087b..e636b75dee4d 100644 --- a/llvm/test/Assembler/invalid-datalayout-program-addrspace.ll +++ b/llvm/test/Assembler/invalid-datalayout-program-addrspace.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s ; CHECK: Invalid address space, must be a 24-bit integer target datalayout = "P16777216" diff --git a/llvm/test/Assembler/invalid-datalayout1.ll b/llvm/test/Assembler/invalid-datalayout1.ll index 5cf088b785b5..d1befdcdf294 100644 --- a/llvm/test/Assembler/invalid-datalayout1.ll +++ b/llvm/test/Assembler/invalid-datalayout1.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "^" ; CHECK: Unknown specifier in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout10.ll b/llvm/test/Assembler/invalid-datalayout10.ll index 80e5d4026d9b..9f19688f852b 100644 --- a/llvm/test/Assembler/invalid-datalayout10.ll +++ b/llvm/test/Assembler/invalid-datalayout10.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "m" ; CHECK: Expected mangling specifier in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout11.ll b/llvm/test/Assembler/invalid-datalayout11.ll index 0fa99c5f7c29..f8fed8ff9ff3 100644 --- a/llvm/test/Assembler/invalid-datalayout11.ll +++ b/llvm/test/Assembler/invalid-datalayout11.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "m." ; CHECK: Unexpected trailing characters after mangling specifier in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout12.ll b/llvm/test/Assembler/invalid-datalayout12.ll index 9a7535f7b6ca..d79c196baab1 100644 --- a/llvm/test/Assembler/invalid-datalayout12.ll +++ b/llvm/test/Assembler/invalid-datalayout12.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "f" ; CHECK: Missing alignment specification in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout13.ll b/llvm/test/Assembler/invalid-datalayout13.ll index 26dbf44f1928..5ac719dbb7a9 100644 --- a/llvm/test/Assembler/invalid-datalayout13.ll +++ b/llvm/test/Assembler/invalid-datalayout13.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = ":32" ; CHECK: Expected token before separator in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout14.ll b/llvm/test/Assembler/invalid-datalayout14.ll index 3ca2da41743d..84634b52a146 100644 --- a/llvm/test/Assembler/invalid-datalayout14.ll +++ b/llvm/test/Assembler/invalid-datalayout14.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i64:64:16" ; CHECK: Preferred alignment cannot be less than the ABI alignment diff --git a/llvm/test/Assembler/invalid-datalayout15.ll b/llvm/test/Assembler/invalid-datalayout15.ll index 8fdfcbf1ee83..ea240b73fd25 100644 --- a/llvm/test/Assembler/invalid-datalayout15.ll +++ b/llvm/test/Assembler/invalid-datalayout15.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i64:16:16777216" ; CHECK: Invalid preferred alignment, must be a 16bit integer diff --git a/llvm/test/Assembler/invalid-datalayout16.ll b/llvm/test/Assembler/invalid-datalayout16.ll index 23f3e17e6d15..0dd1abb629b6 100644 --- a/llvm/test/Assembler/invalid-datalayout16.ll +++ b/llvm/test/Assembler/invalid-datalayout16.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i64:16777216:16777216" ; CHECK: Invalid ABI alignment, must be a 16bit integer diff --git a/llvm/test/Assembler/invalid-datalayout17.ll b/llvm/test/Assembler/invalid-datalayout17.ll index 75c9b005c30d..519f5c10ab3c 100644 --- a/llvm/test/Assembler/invalid-datalayout17.ll +++ b/llvm/test/Assembler/invalid-datalayout17.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i16777216:16:16" ; CHECK: Invalid bit width, must be a 24bit integer diff --git a/llvm/test/Assembler/invalid-datalayout18.ll b/llvm/test/Assembler/invalid-datalayout18.ll index dc6e722445f4..b9956f98c9c6 100644 --- a/llvm/test/Assembler/invalid-datalayout18.ll +++ b/llvm/test/Assembler/invalid-datalayout18.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:32:32:16" ; CHECK: Preferred alignment cannot be less than the ABI alignment diff --git a/llvm/test/Assembler/invalid-datalayout19.ll b/llvm/test/Assembler/invalid-datalayout19.ll index dc3fa2bde1b0..fc0fc4685209 100644 --- a/llvm/test/Assembler/invalid-datalayout19.ll +++ b/llvm/test/Assembler/invalid-datalayout19.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:0:32:32" diff --git a/llvm/test/Assembler/invalid-datalayout2.ll b/llvm/test/Assembler/invalid-datalayout2.ll index 1f7db4e605af..a435612bf854 100644 --- a/llvm/test/Assembler/invalid-datalayout2.ll +++ b/llvm/test/Assembler/invalid-datalayout2.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "m:v" ; CHECK: Unknown mangling in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout20.ll b/llvm/test/Assembler/invalid-datalayout20.ll index 811488e945c8..a9ac1d7fe098 100644 --- a/llvm/test/Assembler/invalid-datalayout20.ll +++ b/llvm/test/Assembler/invalid-datalayout20.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:64:24:64" diff --git a/llvm/test/Assembler/invalid-datalayout21.ll b/llvm/test/Assembler/invalid-datalayout21.ll index 0db99d254b13..a39d1d7a14a8 100644 --- a/llvm/test/Assembler/invalid-datalayout21.ll +++ b/llvm/test/Assembler/invalid-datalayout21.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:64:64:24" diff --git a/llvm/test/Assembler/invalid-datalayout22.ll b/llvm/test/Assembler/invalid-datalayout22.ll index 3db71d7d1b2d..14e4c2822ce4 100644 --- a/llvm/test/Assembler/invalid-datalayout22.ll +++ b/llvm/test/Assembler/invalid-datalayout22.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "v128:0:128" diff --git a/llvm/test/Assembler/invalid-datalayout23.ll b/llvm/test/Assembler/invalid-datalayout23.ll index 308b0140cd98..430326327bc1 100644 --- a/llvm/test/Assembler/invalid-datalayout23.ll +++ b/llvm/test/Assembler/invalid-datalayout23.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i32:24:32" diff --git a/llvm/test/Assembler/invalid-datalayout24.ll b/llvm/test/Assembler/invalid-datalayout24.ll index 0c38103c9057..616ec64518a5 100644 --- a/llvm/test/Assembler/invalid-datalayout24.ll +++ b/llvm/test/Assembler/invalid-datalayout24.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "i32:32:24" diff --git a/llvm/test/Assembler/invalid-datalayout3.ll b/llvm/test/Assembler/invalid-datalayout3.ll index 613d619c5a05..44535fd055b5 100644 --- a/llvm/test/Assembler/invalid-datalayout3.ll +++ b/llvm/test/Assembler/invalid-datalayout3.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "n0" ; CHECK: Zero width native integer type in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout4.ll b/llvm/test/Assembler/invalid-datalayout4.ll index 5b174ff06184..2d946d32609d 100644 --- a/llvm/test/Assembler/invalid-datalayout4.ll +++ b/llvm/test/Assembler/invalid-datalayout4.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p16777216:64:64:64" ; CHECK: Invalid address space, must be a 24bit integer diff --git a/llvm/test/Assembler/invalid-datalayout5.ll b/llvm/test/Assembler/invalid-datalayout5.ll index 6ca188a4fd57..3ce8791c0870 100644 --- a/llvm/test/Assembler/invalid-datalayout5.ll +++ b/llvm/test/Assembler/invalid-datalayout5.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "a1:64" ; CHECK: Sized aggregate specification in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout6.ll b/llvm/test/Assembler/invalid-datalayout6.ll index f8ea6392a359..425099f7cad8 100644 --- a/llvm/test/Assembler/invalid-datalayout6.ll +++ b/llvm/test/Assembler/invalid-datalayout6.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "a:" ; CHECK: Trailing separator in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout7.ll b/llvm/test/Assembler/invalid-datalayout7.ll index 66eb7643d114..097227ae6ae8 100644 --- a/llvm/test/Assembler/invalid-datalayout7.ll +++ b/llvm/test/Assembler/invalid-datalayout7.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "p:52" ; CHECK: number of bits must be a byte width multiple diff --git a/llvm/test/Assembler/invalid-datalayout8.ll b/llvm/test/Assembler/invalid-datalayout8.ll index 2f7f18c7af5b..28832ffb17dd 100644 --- a/llvm/test/Assembler/invalid-datalayout8.ll +++ b/llvm/test/Assembler/invalid-datalayout8.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "e-p" ; CHECK: Missing size specification for pointer in datalayout string diff --git a/llvm/test/Assembler/invalid-datalayout9.ll b/llvm/test/Assembler/invalid-datalayout9.ll index 74b9dbacbf06..dfeac65cf604 100644 --- a/llvm/test/Assembler/invalid-datalayout9.ll +++ b/llvm/test/Assembler/invalid-datalayout9.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llvm-as < %s 2>&1 | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck %s target datalayout = "e-p:64" ; CHECK: Missing alignment specification for pointer in datalayout string diff --git a/llvm/test/Bitcode/function-default-address-spaces.ll b/llvm/test/Bitcode/function-default-address-spaces.ll index 72b727924b42..e008f43501a0 100644 --- a/llvm/test/Bitcode/function-default-address-spaces.ll +++ b/llvm/test/Bitcode/function-default-address-spaces.ll @@ -1,6 +1,6 @@ ; RUN: llvm-as %s -o - | llvm-dis - | FileCheck %s -check-prefixes CHECK,PROG-AS0 ; RUN: llvm-as -data-layout "P200" %s -o - | llvm-dis | FileCheck %s -check-prefixes CHECK,PROG-AS200 -; RUN: not --crash llvm-as -data-layout "P123456789" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix BAD-DATALAYOUT +; RUN: not llvm-as -data-layout "P123456789" %s -o /dev/null 2>&1 | FileCheck %s -check-prefix BAD-DATALAYOUT ; BAD-DATALAYOUT: LLVM ERROR: Invalid address space, must be a 24-bit integer ; PROG-AS0-NOT: target datalayout diff --git a/llvm/test/Bitcode/invalid-functionptr-align.ll b/llvm/test/Bitcode/invalid-functionptr-align.ll index be7ce49e4d53..4ff797a4b014 100644 --- a/llvm/test/Bitcode/invalid-functionptr-align.ll +++ b/llvm/test/Bitcode/invalid-functionptr-align.ll @@ -1,5 +1,5 @@ ; Bitcode with invalid function pointer alignment. -; RUN: not --crash llvm-dis %s.bc -o - 2>&1 | FileCheck %s +; RUN: not llvm-dis %s.bc -o - 2>&1 | FileCheck %s CHECK: LLVM ERROR: Alignment is neither 0 nor a power of 2 diff --git a/llvm/test/Bitcode/invalid.test b/llvm/test/Bitcode/invalid.test index 90303586ec3b..8260ac862576 100644 --- a/llvm/test/Bitcode/invalid.test +++ b/llvm/test/Bitcode/invalid.test @@ -1,6 +1,6 @@ RUN: not llvm-dis -disable-output %p/Inputs/invalid-empty.bc 2>&1 | \ RUN: FileCheck --check-prefix=INVALID-EMPTY %s -RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-pr20485.bc 2>&1 | \ +RUN: not llvm-dis -disable-output %p/Inputs/invalid-pr20485.bc 2>&1 | \ RUN: FileCheck --check-prefix=INVALID-ENCODING %s RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev.bc 2>&1 | \ RUN: FileCheck --check-prefix=BAD-ABBREV %s @@ -71,14 +71,14 @@ RUN: FileCheck --check-prefix=FP-SHIFT %s FP-SHIFT: Invalid record -RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-vbr-size-too-big.bc 2>&1 | \ +RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-vbr-size-too-big.bc 2>&1 | \ RUN: FileCheck --check-prefix=HUGE-ABBREV-OP %s -RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-fixed-size-too-big.bc 2>&1 | \ +RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-fixed-size-too-big.bc 2>&1 | \ RUN: FileCheck --check-prefix=HUGE-ABBREV-OP %s HUGE-ABBREV-OP: Fixed or VBR abbrev record with size > MaxChunkData -RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-array-type.bc 2>&1 | \ +RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-type.bc 2>&1 | \ RUN: FileCheck --check-prefix=ARRAY-TYPE %s ARRAY-TYPE: Array element type can't be an Array or a Blob @@ -116,7 +116,7 @@ RUN: FileCheck --check-prefix=INVALID-CAST %s INVALID-CAST: Invalid cast -RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-array-op-not-2nd-to-last.bc 2>&1 | \ +RUN: not llvm-dis -disable-output %p/Inputs/invalid-array-op-not-2nd-to-last.bc 2>&1 | \ RUN: FileCheck --check-prefix=ARRAY-NOT-2LAST %s ARRAY-NOT-2LAST: Array op not second to last @@ -176,7 +176,7 @@ RUN: FileCheck --check-prefix=INVALID-GVCOMDAT-ID %s INVALID-GVCOMDAT-ID: Invalid global variable comdat ID -RUN: not --crash llvm-dis -disable-output %p/Inputs/invalid-abbrev-no-operands.bc 2>&1 | \ +RUN: not llvm-dis -disable-output %p/Inputs/invalid-abbrev-no-operands.bc 2>&1 | \ RUN: FileCheck --check-prefix=ABBREV-NO-OPS %s ABBREV-NO-OPS: Abbrev record with no operands diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 661bd0d121e0..bbe8ea0da25b 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -1,9 +1,9 @@ -; RUN: not --crash llc -O0 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR +; RUN: not llc -O0 -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR ; RUN: llc -O0 -global-isel -global-isel-abort=0 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=FALLBACK ; RUN: llc -O0 -global-isel -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o %t.out 2> %t.err ; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-OUT < %t.out ; RUN: FileCheck %s --check-prefix=FALLBACK-WITH-REPORT-ERR < %t.err -; RUN: not --crash llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN +; RUN: not llc -global-isel -mtriple aarch64_be %s -o - 2>&1 | FileCheck %s --check-prefix=BIG-ENDIAN ; This file checks that the fallback path to selection dag works. ; The test is fragile in the sense that it must be updated to expose ; something that fails with global-isel. diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll index 0894fbeb34a9..72af098a8946 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator-musttail.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc %s -mtriple aarch64-apple-darwin -debug-only=aarch64-call-lowering -global-isel -global-isel-abort=2 -o - 2>&1 | FileCheck %s +; RUN: not llc %s -mtriple aarch64-apple-darwin -debug-only=aarch64-call-lowering -global-isel -global-isel-abort=2 -o - 2>&1 | FileCheck %s ; REQUIRES: asserts ; Verify that we fall back to SelectionDAG, and error out when we can't tail call musttail functions diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir index 9c318b7574b8..7661626f6c1c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-1.mir @@ -1,4 +1,5 @@ -# RUN: not --crash llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s +# RUN: not llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s +# REQUIRES: asserts # This is to demonstrate what kind of bugs we're missing w/o some kind # of validation for LegalizerInfo: G_INTTOPTR could only be legal / diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir index bbdc54a51219..0b5b7b440f29 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-inttoptr-xfail-2.mir @@ -1,4 +1,5 @@ -# RUN: not --crash llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s +# RUN: not llc -mtriple=aarch64-- -run-pass=legalizer %s -o - 2>&1 | FileCheck %s +# REQUIRES: asserts # This is to demonstrate what kind of bugs we're missing w/o some kind # of validation for LegalizerInfo: G_INTTOPTR could only be legal / diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll index 6408f2e0b0d5..f2e6fbce0d7a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -o - -verify-machineinstrs -global-isel -global-isel-abort=1 -stop-after=legalizer %s 2>&1 | FileCheck %s +; RUN: not llc -o - -verify-machineinstrs -global-isel -global-isel-abort=1 -stop-after=legalizer %s 2>&1 | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-unknown" diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll index bd14ec61b55c..5d48c17e1286 100644 --- a/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll +++ b/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll index fe5f000a393e..8a5fd6f1ac8b 100644 --- a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll +++ b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll b/llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll index 9a24d6acfa11..7ef51d7d4c01 100644 --- a/llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll +++ b/llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll @@ -9,7 +9,7 @@ ; FIXME: We currently produce "small" code for the tiny model ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=tiny -verify-machineinstrs < %s | FileCheck %s ; FIXME: We currently error for the large code model -; RUN: not --crash llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=large -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE +; RUN: not llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -code-model=large -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE ; CHECK-LARGE: ELF TLS only supported in small memory model diff --git a/llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll b/llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll index d6df1a3907bc..4f169678974f 100644 --- a/llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll +++ b/llvm/test/CodeGen/AArch64/arm64-tls-initial-exec.ll @@ -3,7 +3,7 @@ ; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=tiny < %s | FileCheck %s --check-prefix=CHECK-TINY ; RUN: llc -mtriple=arm64-none-linux-gnu -filetype=obj < %s -code-model=tiny | llvm-objdump -r - | FileCheck --check-prefix=CHECK-TINY-RELOC %s ; FIXME: We currently error for the large code model -; RUN: not --crash llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=large < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE +; RUN: not llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -show-mc-encoding -code-model=large < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LARGE ; CHECK-LARGE: ELF TLS only supported in small memory model diff --git a/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll b/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll index 8d62fb355666..62815daa6c51 100644 --- a/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll +++ b/llvm/test/CodeGen/AArch64/fast-isel-sp-adjust.ll @@ -1,5 +1,5 @@ ; RUN: llc -O0 -fast-isel -mtriple=aarch64-apple-ios -o - %s | FileCheck %s -; RUN: not --crash llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t +; RUN: not llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel -fast-isel-abort=3 %s 2> %t ; RUN: FileCheck %s --check-prefix=CHECK-ERRORS < %t ; The issue here is that FastISel cannot emit an ADDrr where one of the inputs diff --git a/llvm/test/CodeGen/AArch64/tiny_supported.ll b/llvm/test/CodeGen/AArch64/tiny_supported.ll index 400fde0aa0a9..50f4a9c344a7 100644 --- a/llvm/test/CodeGen/AArch64/tiny_supported.ll +++ b/llvm/test/CodeGen/AArch64/tiny_supported.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s ; RUN: llc -verify-machineinstrs -o - -mtriple=aarch64-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm64-apple-darwin -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm64-apple-ios -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=aarch64-unknown-windows-msvc -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY +; RUN: not llc -verify-machineinstrs -o - -mtriple=arm64-apple-darwin -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY +; RUN: not llc -verify-machineinstrs -o - -mtriple=arm64-apple-ios -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY +; RUN: not llc -verify-machineinstrs -o - -mtriple=aarch64-unknown-windows-msvc -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=NOTINY ; CHECK-NOT: tiny code model is only supported on ELF ; CHECK-LABEL: foo diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll index 5243076ea8b0..8eee33af24ad 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GPRIDX %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=MOVREL %s -; RUN: not --crash llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s +; RUN: not llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s ; FIXME: Need constant bus fixup pre-gfx10 for movrel ; ERR: Bad machine code: VOP* instruction violates constant bus restriction diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir index 8ea1d4b659ad..2c7a03c0064c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.xfail.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s +# RUN: not llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s # ERR: *** Bad machine code: VOP* instruction violates constant bus restriction *** diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll index 8c84c1c5e306..02f77141b411 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll @@ -1,3 +1,3 @@ -; RUN: not --crash llc -global-isel -march=amdgcn -mcpu=tonga < %S/../lds-zero-initializer.ll 2>&1 | FileCheck %s +; RUN: not llc -global-isel -march=amdgcn -mcpu=tonga < %S/../lds-zero-initializer.ll 2>&1 | FileCheck %s ; CHECK: error: :0:0: in function load_zeroinit_lds_global void (i32 addrspace(1)*, i1): unsupported initializer for address space diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir index 845bffd1d9f3..ccce93db415f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-nand.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s 2>&1| FileCheck -check-prefix=ERROR %s +# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o - %s 2>&1| FileCheck -check-prefix=ERROR %s # This needs to be expanded into a cmpxchg loop. # TODO: Will AtomicExpand still do this? diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir index 9f2be730569c..96b33c1b768a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire -O0 -run-pass=legalizer -o - %s | FileCheck %s -# RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +# RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s # ERROR: LLVM ERROR: unable to legalize instruction: %2:_(s32) = G_ATOMICRMW_XCHG %0:_(p0), %1:_ :: (load store seq_cst 4) (in function: atomicrmw_xchg_flat_i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir index 7a880f86c089..40e5ccd2c1ea 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=amdgcn -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass=legalizer -o /dev/null %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: unable to legalize instruction: %3:_(p0) = G_JUMP_TABLE %jump-table.0 (in function: jt_test) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir index 6f7ef466394c..5ffbeab9872d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values-xfail.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -o - %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -o - %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: unable to legalize instruction: %1:_(s1), %2:_(s1) = G_UNMERGE_VALUES %0:_(<2 x s1>) (in function: test_unmerge_v2s1) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll index 806a16eb7640..550a7312cbe1 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.sema.release.all.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-GISEL %s +; RUN: not llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR-GISEL %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %S/../llvm.amdgcn.ds.gws.sema.release.all.ll ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %S/../llvm.amdgcn.ds.gws.sema.release.all.ll ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.release.all.ll | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %S/../llvm.amdgcn.ds.gws.sema.release.all.ll diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir index 7e1d3871616a..32968c0250b4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir @@ -1,5 +1,5 @@ -# RUN: not --crash llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast %s -o /dev/null 2>&1 | FileCheck %s -# RUN: not --crash llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy %s -o /dev/null 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast %s -o /dev/null 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy %s -o /dev/null 2>&1 | FileCheck %s # Check behavior for illegal copies. diff --git a/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir b/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir index eb244190e562..95e0ada80040 100644 --- a/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir +++ b/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s # CHECK: *** Bad machine code: No live subrange at use *** # CHECK-NEXT: - function: at_least_one_value_should_be_defined_by_this_mask diff --git a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll index 6ea73ed8c7a9..e4d3df91d59d 100644 --- a/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll +++ b/llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s +; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s 2>&1 | FileCheck -check-prefix=FAIL %s ; FIXME: This should be able to compile, but requires inserting an ; extra block to restore the scavenged register. diff --git a/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll b/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll index 1c5da794a5f3..2d9183e6a99e 100644 --- a/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll +++ b/llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s ; FIXME: It should be invalid IR to have a call to a kernel, but this ; is currently relied on, but should be eliminated before codegen. diff --git a/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll b/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll index 24b019ccefe3..6b457cfd4bf2 100644 --- a/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll +++ b/llvm/test/CodeGen/AMDGPU/call-to-kernel.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s ; FIXME: It should be invalid IR to have a call to a kernel, but this ; is currently relied on, but should be eliminated before codegen. diff --git a/llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll b/llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll index a37db5a27240..72c6cfee28df 100644 --- a/llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll +++ b/llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll @@ -1,6 +1,6 @@ -; RUN: not --crash llc -march=amdgcn -mcpu=verde -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -; RUN: not --crash llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -; RUN: not --crash llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=verde -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s ;CHECK: LLVM ERROR: unable to allocate function argument define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } @_amdgpu_gs_sgpr_i32 (i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg) { diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll index 68fe7ec62342..80acf6804ccc 100644 --- a/llvm/test/CodeGen/AMDGPU/div_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: unsupported libcall legalization define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { diff --git a/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll b/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll index 8881d9e7088c..25b21326d570 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-error-unsupported-gpu-hsa.ll @@ -1,8 +1,8 @@ -; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s -; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -o - %s | FileCheck -check-prefix=HSA-DEFAULT %s -; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx600 -filetype=obj -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s ; Flat instructions should not select if the target device doesn't ; support them. The default device should be able to select for HSA. diff --git a/llvm/test/CodeGen/AMDGPU/lds-initializer.ll b/llvm/test/CodeGen/AMDGPU/lds-initializer.ll index 42a9782ad0b7..7cfe013b8453 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-initializer.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s ; CHECK: lds: unsupported initializer for address space diff --git a/llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll b/llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll index 70bf4e951b99..367dd173f781 100644 --- a/llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-zero-initializer.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s ; CHECK: lds: unsupported initializer for address space diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll index 8ba2b0e53698..2d690ec76233 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR %s +; RUN: not llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - < %s 2>&1 | FileCheck -enable-var-scope -check-prefix=GFX6ERR %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP,GFX8 %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll index 6b169e0f18f6..34cbe3963361 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s ; CHECK: invalid register "flat_scratch_lo" for subtarget. diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll index 178b22f329b1..6417d28e7aad 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s ; CHECK: invalid type for register "exec". diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll index f05d900b39d6..8e248fdfea4c 100644 --- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll +++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s ; CHECK: invalid type for register "m0". diff --git a/llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll b/llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll index c028adf5d938..e7346c4c1d4c 100644 --- a/llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll +++ b/llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s +; RUN: not llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s ; Make sure this doesn't assert on targets without the r128-16 ; feature, and instead generates a slection error. diff --git a/llvm/test/CodeGen/AMDGPU/verify-sop.mir b/llvm/test/CodeGen/AMDGPU/verify-sop.mir index 040cd58f28c9..53d749f71196 100644 --- a/llvm/test/CodeGen/AMDGPU/verify-sop.mir +++ b/llvm/test/CodeGen/AMDGPU/verify-sop.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass machineverifier %s -o - 2>&1 | FileCheck %s # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants # CHECK: - instruction: %0:sreg_32_xm0 = S_ADD_I32 diff --git a/llvm/test/CodeGen/ARM/codemodel.ll b/llvm/test/CodeGen/ARM/codemodel.ll index ee435986c611..ec9982faba12 100644 --- a/llvm/test/CodeGen/ARM/codemodel.ll +++ b/llvm/test/CodeGen/ARM/codemodel.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL +; RUN: not llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY +; RUN: not llc -verify-machineinstrs -o - -mtriple=arm-none-eabi -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL ; TINY: Target does not support the tiny CodeModel ; KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/ARM/ldc2l.ll b/llvm/test/CodeGen/ARM/ldc2l.ll index bdfcbbf7df25..58d9509b1672 100644 --- a/llvm/test/CodeGen/ARM/ldc2l.ll +++ b/llvm/test/CodeGen/ARM/ldc2l.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ldc2l define void @ldc2l(i8* %i) nounwind { diff --git a/llvm/test/CodeGen/ARM/machine-verifier.mir b/llvm/test/CodeGen/ARM/machine-verifier.mir index eab4d45e5ab0..c5d678c38cfa 100644 --- a/llvm/test/CodeGen/ARM/machine-verifier.mir +++ b/llvm/test/CodeGen/ARM/machine-verifier.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=thumb -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser runs the machine verifier after parsing. --- | diff --git a/llvm/test/CodeGen/ARM/named-reg-alloc.ll b/llvm/test/CodeGen/ARM/named-reg-alloc.ll index 535149a67455..d41fa64882c8 100644 --- a/llvm/test/CodeGen/ARM/named-reg-alloc.ll +++ b/llvm/test/CodeGen/ARM/named-reg-alloc.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/named-reg-notareg.ll b/llvm/test/CodeGen/ARM/named-reg-notareg.ll index 0af948250050..45cb38f30f35 100644 --- a/llvm/test/CodeGen/ARM/named-reg-notareg.ll +++ b/llvm/test/CodeGen/ARM/named-reg-notareg.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=arm-apple-darwin 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=arm-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/special-reg-acore.ll b/llvm/test/CodeGen/ARM/special-reg-acore.ll index 30e59b14685f..3d65ff44bfb0 100644 --- a/llvm/test/CodeGen/ARM/special-reg-acore.ll +++ b/llvm/test/CodeGen/ARM/special-reg-acore.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE -; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE +; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=MCORE ; MCORE: LLVM ERROR: Invalid register name "cpsr". diff --git a/llvm/test/CodeGen/ARM/special-reg-mcore.ll b/llvm/test/CodeGen/ARM/special-reg-mcore.ll index dff02ce2ea44..1ecf8dc77a70 100644 --- a/llvm/test/CodeGen/ARM/special-reg-mcore.ll +++ b/llvm/test/CodeGen/ARM/special-reg-mcore.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 --show-mc-encoding 2>&1 | FileCheck %s --check-prefix=MCORE -; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE -; RUN: not --crash llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE +; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m3 2>&1 | FileCheck %s --check-prefix=M3CORE +; RUN: not llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s --check-prefix=ACORE ; ACORE: LLVM ERROR: Invalid register name "control". ; M3CORE: LLVM ERROR: Invalid register name "xpsr_nzcvqg". diff --git a/llvm/test/CodeGen/ARM/special-reg-v8m-base.ll b/llvm/test/CodeGen/ARM/special-reg-v8m-base.ll index 5b74a55fe8c8..20284daa0463 100644 --- a/llvm/test/CodeGen/ARM/special-reg-v8m-base.ll +++ b/llvm/test/CodeGen/ARM/special-reg-v8m-base.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M +; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M ; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s ; V7M: LLVM ERROR: Invalid register name "sp_ns". diff --git a/llvm/test/CodeGen/ARM/special-reg-v8m-main.ll b/llvm/test/CodeGen/ARM/special-reg-v8m-main.ll index 9a314fa4c771..88f238cb83a0 100644 --- a/llvm/test/CodeGen/ARM/special-reg-v8m-main.ll +++ b/llvm/test/CodeGen/ARM/special-reg-v8m-main.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE +; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE ; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE ; BASELINE: LLVM ERROR: Invalid register name "faultmask_ns". diff --git a/llvm/test/CodeGen/ARM/ssat-lower.ll b/llvm/test/CodeGen/ARM/ssat-lower.ll index 93930298fb48..9f0cd0364bcf 100644 --- a/llvm/test/CodeGen/ARM/ssat-lower.ll +++ b/llvm/test/CodeGen/ARM/ssat-lower.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s ; immediate argument < lower-bound ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat diff --git a/llvm/test/CodeGen/ARM/ssat-upper.ll b/llvm/test/CodeGen/ARM/ssat-upper.ll index 9fcab67b4a73..e53f82b3efa3 100644 --- a/llvm/test/CodeGen/ARM/ssat-upper.ll +++ b/llvm/test/CodeGen/ARM/ssat-upper.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s ; immediate argument > upper-bound ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ssat diff --git a/llvm/test/CodeGen/ARM/ssat-v4t.ll b/llvm/test/CodeGen/ARM/ssat-v4t.ll index 42511f92fdc5..3d74c88da827 100644 --- a/llvm/test/CodeGen/ARM/ssat-v4t.ll +++ b/llvm/test/CodeGen/ARM/ssat-v4t.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s +; RUN: not llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s ; CHECK: Cannot select: intrinsic %llvm.arm.ssat define i32 @ssat() nounwind { diff --git a/llvm/test/CodeGen/ARM/stc2.ll b/llvm/test/CodeGen/ARM/stc2.ll index c4d7ff007f51..1127796387bb 100644 --- a/llvm/test/CodeGen/ARM/stc2.ll +++ b/llvm/test/CodeGen/ARM/stc2.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.stc2 define void @stc2(i8* %i) nounwind { diff --git a/llvm/test/CodeGen/ARM/usat-lower.ll b/llvm/test/CodeGen/ARM/usat-lower.ll index 3d7b24d9373e..58d3bba5a1f8 100644 --- a/llvm/test/CodeGen/ARM/usat-lower.ll +++ b/llvm/test/CodeGen/ARM/usat-lower.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s ; immediate argument < lower-bound ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat diff --git a/llvm/test/CodeGen/ARM/usat-upper.ll b/llvm/test/CodeGen/ARM/usat-upper.ll index 4f186a013cd8..84ad694725b4 100644 --- a/llvm/test/CodeGen/ARM/usat-upper.ll +++ b/llvm/test/CodeGen/ARM/usat-upper.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=armv6-none-none-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -O1 -mtriple=thumbv7-none-none-eabi 2>&1 | FileCheck %s ; immediate argument > upper-bound ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat diff --git a/llvm/test/CodeGen/ARM/usat-v4t.ll b/llvm/test/CodeGen/ARM/usat-v4t.ll index 9cc75846ca36..572c760e3ae6 100644 --- a/llvm/test/CodeGen/ARM/usat-v4t.ll +++ b/llvm/test/CodeGen/ARM/usat-v4t.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s +; RUN: not llc -O1 -mtriple=armv4t-none-none-eabi %s -o - 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.usat define i32 @usat1() nounwind { diff --git a/llvm/test/CodeGen/BPF/sdiv_error.ll b/llvm/test/CodeGen/BPF/sdiv_error.ll index fc79a1d44c16..053b82dd98fa 100644 --- a/llvm/test/CodeGen/BPF/sdiv_error.ll +++ b/llvm/test/CodeGen/BPF/sdiv_error.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=bpf < %s 2> %t1 +; RUN: not llc -march=bpf < %s 2> %t1 ; RUN: FileCheck %s < %t1 ; CHECK: Unsupport signed division diff --git a/llvm/test/CodeGen/BPF/xadd.ll b/llvm/test/CodeGen/BPF/xadd.ll index 6fd0a1f644bb..0bf8576df1c7 100644 --- a/llvm/test/CodeGen/BPF/xadd.ll +++ b/llvm/test/CodeGen/BPF/xadd.ll @@ -1,7 +1,7 @@ -; RUN: not --crash llc -march=bpfel < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -march=bpfeb < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -march=bpfel -mattr=+alu32 < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -march=bpfeb -mattr=+alu32 < %s 2>&1 | FileCheck %s +; RUN: not llc -march=bpfel < %s 2>&1 | FileCheck %s +; RUN: not llc -march=bpfeb < %s 2>&1 | FileCheck %s +; RUN: not llc -march=bpfel -mattr=+alu32 < %s 2>&1 | FileCheck %s +; RUN: not llc -march=bpfeb -mattr=+alu32 < %s 2>&1 | FileCheck %s ; This file is generated with the source command and source ; $ clang -target bpf -O2 -g -S -emit-llvm t.c diff --git a/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll b/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll index 76cc8b681b6a..cb1b30f3a819 100644 --- a/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll +++ b/llvm/test/CodeGen/Generic/llc-start-stop-instance-errors.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -debug-pass=Structure -stop-after=dead-mi-elimination,arst %s -o /dev/null 2>&1 \ +; RUN: not llc -debug-pass=Structure -stop-after=dead-mi-elimination,arst %s -o /dev/null 2>&1 \ ; RUN: | FileCheck -check-prefix=NOT-NUM %s ; NOT-NUM: LLVM ERROR: invalid pass instance specifier dead-mi-elimination,arst diff --git a/llvm/test/CodeGen/Generic/llc-start-stop.ll b/llvm/test/CodeGen/Generic/llc-start-stop.ll index 4f2e708c4f2e..fa34838a411f 100644 --- a/llvm/test/CodeGen/Generic/llc-start-stop.ll +++ b/llvm/test/CodeGen/Generic/llc-start-stop.ll @@ -23,16 +23,16 @@ ; START-BEFORE: Loop Strength Reduction ; START-BEFORE-NEXT: Basic Alias Analysis (stateless AA impl) -; RUN: not --crash llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE -; RUN: not --crash llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE -; RUN: not --crash llc < %s -start-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-AFTER -; RUN: not --crash llc < %s -stop-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-AFTER +; RUN: not llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE +; RUN: not llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE +; RUN: not llc < %s -start-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-AFTER +; RUN: not llc < %s -stop-after=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-AFTER ; NONEXISTENT-START-BEFORE: "nonexistent" pass is not registered. ; NONEXISTENT-STOP-BEFORE: "nonexistent" pass is not registered. ; NONEXISTENT-START-AFTER: "nonexistent" pass is not registered. ; NONEXISTENT-STOP-AFTER: "nonexistent" pass is not registered. -; RUN: not --crash llc < %s -start-before=loop-reduce -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-START -; RUN: not --crash llc < %s -stop-before=loop-reduce -stop-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-STOP +; RUN: not llc < %s -start-before=loop-reduce -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-START +; RUN: not llc < %s -stop-before=loop-reduce -stop-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=DOUBLE-STOP ; DOUBLE-START: start-before and start-after specified! ; DOUBLE-STOP: stop-before and stop-after specified! diff --git a/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll b/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll index 413f09ba55dd..c6cb1c2b657b 100644 --- a/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll +++ b/llvm/test/CodeGen/Generic/opt-codegen-no-target-machine.ll @@ -1,3 +1,3 @@ -; RUN: not --crash opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s +; RUN: not opt %s -dwarfehprepare -o - 2>&1 | FileCheck %s ; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass without a target triple set? diff --git a/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll b/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll index 74b744305a07..37d1155ca275 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned-const-load.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s ; Check that the misaligned load is diagnosed. ; CHECK: LLVM ERROR: Misaligned constant address: 0x00012345 has alignment 1, but the memory access requires 4, at misaligned-const-load.c:2:10 diff --git a/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll b/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll index 0a5b1aafcc01..311a56e13a75 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned-const-store.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=hexagon < %s 2>&1 | FileCheck %s +; RUN: not llc -march=hexagon < %s 2>&1 | FileCheck %s ; Check that the misaligned store is diagnosed. ; CHECK: LLVM ERROR: Misaligned constant address: 0x00012345 has alignment 1, but the memory access requires 4, at misaligned-const-store.c:2:10 diff --git a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir index fefe24514099..149790c98638 100644 --- a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir +++ b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir @@ -1,8 +1,8 @@ # Using a trick to run simple-register-coalescing twice, that way # liveintervals should be preserved while running the machine verifier. # -# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s -# RUN: not --crash llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-SUB %s +# RUN: not llc -o - %s -march=hexagon -hexagon-subreg-liveness=false -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-NOSUB %s +# RUN: not llc -o - %s -march=hexagon -hexagon-subreg-liveness=true -run-pass simple-register-coalescing -verify-machineinstrs -run-pass simple-register-coalescing 2>&1 | FileCheck -check-prefix=CHECK-SUB %s --- name: test_pass diff --git a/llvm/test/CodeGen/Lanai/codemodel.ll b/llvm/test/CodeGen/Lanai/codemodel.ll index acfbabacf33c..72d1d65daf52 100644 --- a/llvm/test/CodeGen/Lanai/codemodel.ll +++ b/llvm/test/CodeGen/Lanai/codemodel.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=lanai < %s | FileCheck %s ; RUN: llc -march=lanai < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s -; RUN: not --crash llc -march=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s -; RUN: not --crash llc -march=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s +; RUN: not llc -march=lanai < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s +; RUN: not llc -march=lanai < %s -code-model=kernel 2>&1 | FileCheck -check-prefix CHECK-KERNEL %s ; CHECK-TINY: Target does not support the tiny CodeModel ; CHECK-KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir index 17aa16b4a431..16a55ea5fea8 100644 --- a/llvm/test/CodeGen/MIR/X86/machine-verifier.mir +++ b/llvm/test/CodeGen/MIR/X86/machine-verifier.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser runs the machine verifier after parsing. --- | diff --git a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir index 3d842f66f0aa..8f531d96d1d9 100644 --- a/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir +++ b/llvm/test/CodeGen/MIR/X86/tied-physical-regs-match.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the Machine Verifier detects tied physical registers # that doesn't match. diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll index 84a284a5bf21..eb592189e601 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/double-arg.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \ +; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \ ; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s ; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll index 18bc397480e3..24161ca82382 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fast-isel-softfloat-lower-args.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \ +; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+soft-float \ ; RUN: -O0 -fast-isel-abort=3 -relocation-model=pic < %s ; Test that FastISel aborts instead of trying to lower arguments for soft-float. diff --git a/llvm/test/CodeGen/Mips/cpus-no-mips64.ll b/llvm/test/CodeGen/Mips/cpus-no-mips64.ll index 63b0140a8a60..301f6c2152e7 100644 --- a/llvm/test/CodeGen/Mips/cpus-no-mips64.ll +++ b/llvm/test/CodeGen/Mips/cpus-no-mips64.ll @@ -1,13 +1,13 @@ ; Check that we reject 64-bit mode on 32-bit only CPUs. -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips1 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips2 2>&1 | FileCheck %s +; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips1 2>&1 | FileCheck %s +; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips2 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r2 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r3 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r5 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r6 2>&1 | FileCheck %s +; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32 2>&1 | FileCheck %s +; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r2 2>&1 | FileCheck %s +; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r3 2>&1 | FileCheck %s +; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r5 2>&1 | FileCheck %s +; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips32r6 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it! diff --git a/llvm/test/CodeGen/Mips/cpus.ll b/llvm/test/CodeGen/Mips/cpus.ll index 182d13b1c7e3..d9377044dca1 100644 --- a/llvm/test/CodeGen/Mips/cpus.ll +++ b/llvm/test/CodeGen/Mips/cpus.ll @@ -57,9 +57,9 @@ ; Check that we reject CPUs that are not implemented. -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips -mcpu=mips1 2>&1 \ +; RUN: not llc < %s -o /dev/null -mtriple=mips -mcpu=mips1 2>&1 \ ; RUN: | FileCheck %s --check-prefix=ERROR -; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \ +; RUN: not llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \ ; RUN: | FileCheck %s --check-prefix=ERROR ; ERROR: LLVM ERROR: Code generation for MIPS-{{.}} is not implemented diff --git a/llvm/test/CodeGen/Mips/fp64a.ll b/llvm/test/CodeGen/Mips/fp64a.ll index 2bf59052761d..317afd7003bb 100644 --- a/llvm/test/CodeGen/Mips/fp64a.ll +++ b/llvm/test/CodeGen/Mips/fp64a.ll @@ -7,16 +7,16 @@ ; We don't test MIPS32r1 since support for 64-bit coprocessors (such as a 64-bit ; FPU) on a 32-bit architecture was added in MIPS32r2. -; RUN: not --crash llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64 +; RUN: not llc -march=mips -mcpu=mips32 -mattr=fp64 < %s 2>&1 | FileCheck %s -check-prefix=32R1-FP64 ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE ; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A ; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A -; RUN: not --crash llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A +; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A ; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A -; RUN: not --crash llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A +; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A ; 32R1-FP64: LLVM ERROR: FPU with 64-bit registers is not available on MIPS32 pre revision 2. Use -mcpu=mips32r2 or greater. ; 64-FP64A: LLVM ERROR: -mattr=+nooddspreg requires the O32 ABI. diff --git a/llvm/test/CodeGen/Mips/fpxx.ll b/llvm/test/CodeGen/Mips/fpxx.ll index 075eff1e580f..6fdb95efe8ec 100644 --- a/llvm/test/CodeGen/Mips/fpxx.ll +++ b/llvm/test/CodeGen/Mips/fpxx.ll @@ -5,10 +5,10 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FPXX ; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,4-NOFPXX -; RUN: not --crash llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX +; RUN: not llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX ; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64-NOFPXX -; RUN: not --crash llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX +; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX ; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,4-O32-NOFPXX ; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,4-O32-FPXX diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir index 02fef74eeefb..b1d177a22eaa 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ +# RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ # RUN: -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir index d313cad4d8d5..e13c93bec248 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ +# RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \ # RUN: -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \ # RUN: | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll index 23841d31e0b4..99612525ae3c 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=mips-unknown-linux -mcpu=mips32r2 -mattr=+micromips,+use-indirect-jump-hazard %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=mips-unknown-linux -mcpu=mips32r2 -mattr=+micromips,+use-indirect-jump-hazard %s 2>&1 | FileCheck %s ; Test that microMIPS and indirect jump with hazard barriers is not supported. diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll index be27eea5dacb..48baedf53eaa 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=mips-unknown-linux -mcpu=mips32 -mattr=+use-indirect-jump-hazard %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=mips-unknown-linux -mcpu=mips32 -mattr=+use-indirect-jump-hazard %s 2>&1 | FileCheck %s ; Test that mips32 and indirect jump with hazard barriers is not supported. diff --git a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir index 02dd9085c31e..a93231b72a00 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dext-size.mir b/llvm/test/CodeGen/Mips/instverify/dext-size.mir index 97cb085eac50..6ba7243cdfb5 100644 --- a/llvm/test/CodeGen/Mips/instverify/dext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dext-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir index e76af1be9493..fbf84819a0f6 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir index 264968382447..d4cf55bf6ca0 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir index fc24a2756c6a..cd9fd2de915a 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextm-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir index 7001221bb0db..782596ec4ece 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir index b9e3b8c169e4..418c98f44fdf 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir index 8407a7a836f7..70f12dd1a91c 100644 --- a/llvm/test/CodeGen/Mips/instverify/dextu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dextu-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir index d72837850cfb..ec6f24aed187 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir index 71d4242c948c..13a7c6536da1 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dins-size.mir b/llvm/test/CodeGen/Mips/instverify/dins-size.mir index 35848a936e5c..63e6f9193c9a 100644 --- a/llvm/test/CodeGen/Mips/instverify/dins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dins-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir index a00d3cf715a7..bec2fc034316 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir index 0bbbdd232245..90dced0435d4 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir index c1f5f044bdee..9c8c247f9ea3 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsm-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir index 9f9953a85565..4209a8ddf61e 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir index 12e999d5d488..7d4828d92947 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir index f204a3373f76..d4c2f56c408e 100644 --- a/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/dinsu-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir index c7b16fd50ab0..b9c1d6193c90 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir index ce2abeb3cdcf..23cede00d319 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ext-size.mir b/llvm/test/CodeGen/Mips/instverify/ext-size.mir index 57737ea60283..8b8ae45ded40 100644 --- a/llvm/test/CodeGen/Mips/instverify/ext-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ext-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir index 1e48f1e8a236..9220bbdb7472 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position + Size is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir index c72e6f5a3be3..3932d174be91 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-pos.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-pos.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Position operand is out of range! diff --git a/llvm/test/CodeGen/Mips/instverify/ins-size.mir b/llvm/test/CodeGen/Mips/instverify/ins-size.mir index 92319bd3ff8a..4f5348c29515 100644 --- a/llvm/test/CodeGen/Mips/instverify/ins-size.mir +++ b/llvm/test/CodeGen/Mips/instverify/ins-size.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ +# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=finalize-isel -stop-after=finalize-isel \ # RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s # CHECK: Size operand is out of range! diff --git a/llvm/test/CodeGen/Mips/interrupt-attr-64-error.ll b/llvm/test/CodeGen/Mips/interrupt-attr-64-error.ll index 02c0e3d5b776..9626bda45f51 100644 --- a/llvm/test/CodeGen/Mips/interrupt-attr-64-error.ll +++ b/llvm/test/CodeGen/Mips/interrupt-attr-64-error.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mcpu=mips64r6 -march=mipsel -target-abi n64 -relocation-model=static < %s 2>%t +; RUN: not llc -mcpu=mips64r6 -march=mipsel -target-abi n64 -relocation-model=static < %s 2>%t ; RUN: FileCheck %s < %t ; CHECK: LLVM ERROR: "interrupt" attribute is only supported for the O32 ABI on MIPS32R2+ at the present time. diff --git a/llvm/test/CodeGen/Mips/interrupt-attr-args-error.ll b/llvm/test/CodeGen/Mips/interrupt-attr-args-error.ll index dd2cf443c7ce..993629bdbcd6 100644 --- a/llvm/test/CodeGen/Mips/interrupt-attr-args-error.ll +++ b/llvm/test/CodeGen/Mips/interrupt-attr-args-error.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mcpu=mips32r2 -march=mipsel -relocation-model=static < %s 2> %t +; RUN: not llc -mcpu=mips32r2 -march=mipsel -relocation-model=static < %s 2> %t ; RUN: FileCheck %s < %t ; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments! diff --git a/llvm/test/CodeGen/Mips/interrupt-attr-error.ll b/llvm/test/CodeGen/Mips/interrupt-attr-error.ll index d84e511a23f1..f35e98ea14bf 100644 --- a/llvm/test/CodeGen/Mips/interrupt-attr-error.ll +++ b/llvm/test/CodeGen/Mips/interrupt-attr-error.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mcpu=mips32 -march=mipsel -relocation-model=static < %s 2>%t +; RUN: not llc -mcpu=mips32 -march=mipsel -relocation-model=static < %s 2>%t ; RUN: FileCheck %s < %t ; CHECK: LLVM ERROR: "interrupt" attribute is not supported on pre-MIPS32R2 or MIPS16 targets. diff --git a/llvm/test/CodeGen/Mips/micromips64-unsupported.ll b/llvm/test/CodeGen/Mips/micromips64-unsupported.ll index 0f24167e3150..713722ea1200 100644 --- a/llvm/test/CodeGen/Mips/micromips64-unsupported.ll +++ b/llvm/test/CodeGen/Mips/micromips64-unsupported.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -mtriple=mips64-unknown-linux -mcpu=mips64r6 -mattr=+micromips %s 2>&1 | FileCheck %s --check-prefix=MICROMIPS64R6 -; RUN: not --crash llc -mtriple=mips64-unknown-linux -mcpu=mips64 -mattr=+micromips %s 2>&1 | FileCheck %s --check-prefix=MICROMIPS64 +; RUN: not llc -mtriple=mips64-unknown-linux -mcpu=mips64r6 -mattr=+micromips %s 2>&1 | FileCheck %s --check-prefix=MICROMIPS64R6 +; RUN: not llc -mtriple=mips64-unknown-linux -mcpu=mips64 -mattr=+micromips %s 2>&1 | FileCheck %s --check-prefix=MICROMIPS64 ; Test that microMIPS64(R6) is not supported. diff --git a/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll b/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll index 1adb1bc944e1..8eac8d4683d1 100644 --- a/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll +++ b/llvm/test/CodeGen/Mips/mips32r6/compatibility.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -; RUN: not --crash llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s +; RUN: not llc -march=mipsel -mcpu=mips32r6 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s ; CHECK: foo: ; DSP: MIPS32r6 is not compatible with the DSP ASE diff --git a/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll b/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll index 8b7607eccc75..174f4ce1771a 100644 --- a/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll +++ b/llvm/test/CodeGen/Mips/mips64r6/compatibility.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -; RUN: not --crash llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s +; RUN: not llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s ; CHECK: foo: ; DSP: MIPS64r6 is not compatible with the DSP ASE diff --git a/llvm/test/CodeGen/Mips/msa/3r-a.ll b/llvm/test/CodeGen/Mips/msa/3r-a.ll index 47d8eaa68beb..933c4ed6946d 100644 --- a/llvm/test/CodeGen/Mips/msa/3r-a.ll +++ b/llvm/test/CodeGen/Mips/msa/3r-a.ll @@ -5,7 +5,7 @@ ; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s | FileCheck %s ; It should fail to compile without fp64. -; RUN: not --crash llc -march=mips -mattr=+msa < %s 2>&1 | \ +; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ ; RUN: FileCheck -check-prefix=FP32ERROR %s ; FP32ERROR: LLVM ERROR: MSA requires a 64-bit FPU register file (FR=1 mode). diff --git a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll index cd0ef21d0022..efb3dfc4be4e 100644 --- a/llvm/test/CodeGen/Mips/msa/immediates-bad.ll +++ b/llvm/test/CodeGen/Mips/msa/immediates-bad.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1 +; RUN: not llc -march=mips -mattr=+msa,+fp64,+mips32r2 -relocation-model=pic < %s 2> %t1 ; RUN: FileCheck %s < %t1 ; Test that the immediate intrinsics with out of range values trigger an error. diff --git a/llvm/test/CodeGen/NVPTX/alias.ll b/llvm/test/CodeGen/NVPTX/alias.ll index 6dad3845b086..a27851927696 100644 --- a/llvm/test/CodeGen/NVPTX/alias.ll +++ b/llvm/test/CodeGen/NVPTX/alias.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that llc dies gracefully when given an alias. diff --git a/llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll b/llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll index 7294958dcd7a..d435c1d14fee 100644 --- a/llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll +++ b/llvm/test/CodeGen/NVPTX/fcos-no-fast-math.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that we fail to select fcos without fast-math enabled diff --git a/llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll b/llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll index 083aa1da3e22..56396b849250 100644 --- a/llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll +++ b/llvm/test/CodeGen/NVPTX/fsin-no-fast-math.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that we fail to select fsin without fast-math enabled diff --git a/llvm/test/CodeGen/NVPTX/global-ctor.ll b/llvm/test/CodeGen/NVPTX/global-ctor.ll index b7206dce6612..89155db08ea5 100644 --- a/llvm/test/CodeGen/NVPTX/global-ctor.ll +++ b/llvm/test/CodeGen/NVPTX/global-ctor.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that llc dies when given a nonempty global ctor. @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }] diff --git a/llvm/test/CodeGen/NVPTX/global-dtor.ll b/llvm/test/CodeGen/NVPTX/global-dtor.ll index 6125b65c4091..9d01f9bd387c 100644 --- a/llvm/test/CodeGen/NVPTX/global-dtor.ll +++ b/llvm/test/CodeGen/NVPTX/global-dtor.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s +; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s ; Check that llc dies when given a nonempty global dtor. @llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }] diff --git a/llvm/test/CodeGen/NVPTX/libcall-instruction.ll b/llvm/test/CodeGen/NVPTX/libcall-instruction.ll index 33bd9a4c8e38..a40a504c94cb 100644 --- a/llvm/test/CodeGen/NVPTX/libcall-instruction.ll +++ b/llvm/test/CodeGen/NVPTX/libcall-instruction.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=nvptx 2>&1 | FileCheck %s +; RUN: not llc < %s -march=nvptx 2>&1 | FileCheck %s ; used to panic on failed assertion and now fails with an "Undefined external symbol" ; CHECK: LLVM ERROR: Undefined external symbol "__umodti3" diff --git a/llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll b/llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll index 4778667002c4..0b5e0224399d 100644 --- a/llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll +++ b/llvm/test/CodeGen/NVPTX/libcall-intrinsic.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=nvptx 2>&1 | FileCheck %s +; RUN: not llc < %s -march=nvptx 2>&1 | FileCheck %s ; used to seqfault and now fails with an "Undefined external symbol" ; CHECK: LLVM ERROR: Undefined external symbol "__powidf2" diff --git a/llvm/test/CodeGen/PowerPC/aix-byval-param.ll b/llvm/test/CodeGen/PowerPC/aix-byval-param.ll index 2dfdf7f8535f..951475438d56 100644 --- a/llvm/test/CodeGen/PowerPC/aix-byval-param.ll +++ b/llvm/test/CodeGen/PowerPC/aix-byval-param.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s %struct.S = type { i32, i32 } diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll b/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll index 5be6213398da..59ad57e1bbaf 100644 --- a/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll +++ b/llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s ; This test expects a compiler diagnostic for an AIX limitation on Altivec ; support. When the Altivec limitation diagnostic is removed, this test diff --git a/llvm/test/CodeGen/PowerPC/aix-nest-param.ll b/llvm/test/CodeGen/PowerPC/aix-nest-param.ll index f768eba31d58..8534c80ca643 100644 --- a/llvm/test/CodeGen/PowerPC/aix-nest-param.ll +++ b/llvm/test/CodeGen/PowerPC/aix-nest-param.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s define i8* @nest_receiver(i8* nest %arg) nounwind { ret i8* %arg diff --git a/llvm/test/CodeGen/PowerPC/aix-trampoline.ll b/llvm/test/CodeGen/PowerPC/aix-trampoline.ll index 4e5cbb6a7e6e..5c45dc588969 100644 --- a/llvm/test/CodeGen/PowerPC/aix-trampoline.ll +++ b/llvm/test/CodeGen/PowerPC/aix-trampoline.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple powerpc-ibm-aix-xcoff < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff < %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: INIT_TRAMPOLINE operation is not supported on AIX. diff --git a/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll b/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll index b179b86c896a..9116ea4e8d9d 100644 --- a/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll +++ b/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll @@ -8,7 +8,7 @@ ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=32-DIS %s -; RUN: not --crash llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \ +; RUN: not llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -mcpu=pwr4 -mattr=-altivec -filetype=obj < %s 2>&1 | FileCheck \ ; RUN: --check-prefix=64-CHECK %s diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll index a1f1f12f9687..d6e772ffc928 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-only-notoc.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ +; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=OBJ64 %s ; OBJ64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll index 44a740c7c7ac..d911383dcff9 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -9,7 +9,7 @@ ; RUN: FileCheck --check-prefix=OBJ %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ +; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll index ad77eeb349d4..536229fc8c45 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll @@ -6,7 +6,7 @@ ; RUN: FileCheck --check-prefix=OBJ %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ +; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=OBJ64 %s ; OBJ64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll index 0b8f43f9c791..8b7032af6600 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll @@ -5,7 +5,7 @@ ; RUN: llvm-readobj -t %t.o | FileCheck --check-prefix=SYM %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s -; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -mattr=-altivec -filetype=obj < %s 2>&1 | \ +; RUN: not llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -mattr=-altivec -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll index 05fde17c9527..e846b39f07c4 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll @@ -7,7 +7,7 @@ ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s -; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ +; RUN: not llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \ ; RUN: FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll index feab85f87bc9..543cca720293 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll @@ -6,7 +6,7 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \ +; RUN: not llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o 2>&1 \ ; RUN: < %s | FileCheck --check-prefix=XCOFF64 %s ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet. diff --git a/llvm/test/CodeGen/PowerPC/codemodel.ll b/llvm/test/CodeGen/PowerPC/codemodel.ll index cbceaf78b176..ee3ceae6df23 100644 --- a/llvm/test/CodeGen/PowerPC/codemodel.ll +++ b/llvm/test/CodeGen/PowerPC/codemodel.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=powerpc-pc-linux -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=powerpc-pc-linux -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL +; RUN: not llc -verify-machineinstrs -o - -mtriple=powerpc-pc-linux -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY +; RUN: not llc -verify-machineinstrs -o - -mtriple=powerpc-pc-linux -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL ; TINY: Target does not support the tiny CodeModel ; KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll index 78cf10ebe688..3f02d4f6c3ef 100644 --- a/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll +++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix.ll @@ -2,7 +2,7 @@ ; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \ ; RUN: %s | FileCheck --check-prefix=SMALL %s -; RUN: not --crash llc -mtriple powerpc-ibm-aix-xcoff -code-model=medium \ +; RUN: not llc -mtriple powerpc-ibm-aix-xcoff -code-model=medium \ ; RUN: -stop-after=machine-cp 2>&1 < %s | FileCheck --check-prefix=MEDIUM %s ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=large \ diff --git a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll index 29119f3257ad..7e00a595c60a 100644 --- a/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll +++ b/llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix.ll @@ -2,7 +2,7 @@ ; RUN: -stop-after=machine-cp -print-before=simple-register-coalescing 2>&1 < \ ; RUN: %s | FileCheck --check-prefix=SMALL %s -; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -code-model=medium \ +; RUN: not llc -mtriple powerpc64-ibm-aix-xcoff -code-model=medium \ ; RUN: -stop-after=machine-cp 2>&1 < %s | FileCheck --check-prefix=MEDIUM %s ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -code-model=large \ diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll index 11cb72296e2c..2506f474cb23 100644 --- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll +++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r0.ll @@ -1,6 +1,6 @@ -; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s define i32 @get_reg() nounwind { entry: diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll index 3df778f445c7..de251350861f 100644 --- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll +++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s define i64 @get_reg() nounwind { entry: diff --git a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll index ca79f857548e..0083f47fd2a5 100644 --- a/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll +++ b/llvm/test/CodeGen/PowerPC/named-reg-alloc-r2.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32 +; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32 define i32 @get_reg() nounwind { entry: diff --git a/llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll b/llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll index e0ff14e60bb0..65b45ea555ae 100644 --- a/llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll @@ -1,6 +1,6 @@ ; Test the ICBT instruction is not emitted on POWER7 ; Based on the ppc64-prefetch.ll test -; RUN: not --crash llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 | FileCheck %s declare void @llvm.prefetch(i8*, i32, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/get-register-invalid.ll b/llvm/test/CodeGen/RISCV/get-register-invalid.ll index 1f23445b4f73..ee8ec44cef51 100644 --- a/llvm/test/CodeGen/RISCV/get-register-invalid.ll +++ b/llvm/test/CodeGen/RISCV/get-register-invalid.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -mtriple=riscv32 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=riscv32 2>&1 | FileCheck %s define i32 @get_invalid_reg() nounwind { entry: diff --git a/llvm/test/CodeGen/RISCV/get-register-reserve.ll b/llvm/test/CodeGen/RISCV/get-register-reserve.ll index 87acd70ec62f..7549b4dd3f68 100644 --- a/llvm/test/CodeGen/RISCV/get-register-reserve.ll +++ b/llvm/test/CodeGen/RISCV/get-register-reserve.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: not --crash llc < %s -mtriple=riscv32 -mattr +reserve-x8 2>&1 \ +; RUN: not llc < %s -mtriple=riscv32 -mattr +reserve-x8 2>&1 \ ; RUN: | FileCheck -check-prefix=NO-RESERVE-A1 %s -; RUN: not --crash llc < %s -mtriple=riscv32 -mattr +reserve-x11 2>&1 \ +; RUN: not llc < %s -mtriple=riscv32 -mattr +reserve-x11 2>&1 \ ; RUN: | FileCheck -check-prefix=NO-RESERVE-FP %s ; RUN: llc < %s -mtriple=riscv32 -mattr +reserve-x8 -mattr +reserve-x11 \ ; RUN: | FileCheck -check-prefix=RESERVE %s diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll index 3458780bfc57..5f246cd66298 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll @@ -1,6 +1,6 @@ -; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \ +; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \ +; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments! diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll index 2bcec1589df0..bddca8af7468 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-invalid.ll @@ -1,6 +1,6 @@ -; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \ +; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \ +; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Function interrupt attribute argument not supported! diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll index a865090546fe..58827a860608 100644 --- a/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll @@ -1,6 +1,6 @@ -; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \ +; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \ +; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type! diff --git a/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll b/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll index fe4d570b9d90..cb24405b1606 100644 --- a/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll +++ b/llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \ +; RUN: not llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV64E %s ; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target diff --git a/llvm/test/CodeGen/RISCV/module-target-abi.ll b/llvm/test/CodeGen/RISCV/module-target-abi.ll index bc61c50b0822..b2930a06ab74 100644 --- a/llvm/test/CodeGen/RISCV/module-target-abi.ll +++ b/llvm/test/CodeGen/RISCV/module-target-abi.ll @@ -2,7 +2,7 @@ ; RUN: | FileCheck -check-prefix=DEFAULT %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s -; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ +; RUN: not llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s ; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck -check-prefixes=FLAGS %s diff --git a/llvm/test/CodeGen/RISCV/module-target-abi2.ll b/llvm/test/CodeGen/RISCV/module-target-abi2.ll index 8664c9add069..f07f2770ace7 100644 --- a/llvm/test/CodeGen/RISCV/module-target-abi2.ll +++ b/llvm/test/CodeGen/RISCV/module-target-abi2.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=riscv32 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=DEFAULT %s -; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ +; RUN: not llc -mtriple=riscv32 -target-abi ilp32 < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32 %s ; RUN: llc -mtriple=riscv32 -target-abi ilp32f < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=RV32IF-ILP32F %s diff --git a/llvm/test/CodeGen/RISCV/musttail-call.ll b/llvm/test/CodeGen/RISCV/musttail-call.ll index 37b0ab456928..551aa7245ce6 100644 --- a/llvm/test/CodeGen/RISCV/musttail-call.ll +++ b/llvm/test/CodeGen/RISCV/musttail-call.ll @@ -1,12 +1,12 @@ ; Check that we error out if tail is not possible but call is marked as mustail. -; RUN: not --crash llc -mtriple riscv32-unknown-linux-gnu -o - %s \ +; RUN: not llc -mtriple riscv32-unknown-linux-gnu -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple riscv32-unknown-elf -o - %s \ +; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple riscv64-unknown-linux-gnu -o - %s \ +; RUN: not llc -mtriple riscv64-unknown-linux-gnu -o - %s \ ; RUN: 2>&1 | FileCheck %s -; RUN: not --crash llc -mtriple riscv64-unknown-elf -o - %s \ +; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \ ; RUN: 2>&1 | FileCheck %s %struct.A = type { i32 } diff --git a/llvm/test/CodeGen/RISCV/rv32e.ll b/llvm/test/CodeGen/RISCV/rv32e.ll index 88379ab43872..2416639dc93c 100644 --- a/llvm/test/CodeGen/RISCV/rv32e.ll +++ b/llvm/test/CodeGen/RISCV/rv32e.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=riscv32 -mattr=+e < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=riscv32 -mattr=+e < %s 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Codegen not yet implemented for RV32E diff --git a/llvm/test/CodeGen/RISCV/target-abi-valid.ll b/llvm/test/CodeGen/RISCV/target-abi-valid.ll index 2d4079601f7b..2bd7dde3cd8e 100644 --- a/llvm/test/CodeGen/RISCV/target-abi-valid.ll +++ b/llvm/test/CodeGen/RISCV/target-abi-valid.ll @@ -34,7 +34,7 @@ define void @nothing() nounwind { ret void } -; RUN: not --crash llc -mtriple=riscv32 -target-abi ilp32e < %s 2>&1 \ +; RUN: not llc -mtriple=riscv32 -target-abi ilp32e < %s 2>&1 \ ; RUN: | FileCheck -check-prefix=CHECK-UNIMP %s ; CHECK-UNIMP: LLVM ERROR: Don't know how to lower this ABI diff --git a/llvm/test/CodeGen/RISCV/verify-instr.mir b/llvm/test/CodeGen/RISCV/verify-instr.mir index 58fcbc3e47de..ed31126b53d4 100644 --- a/llvm/test/CodeGen/RISCV/verify-instr.mir +++ b/llvm/test/CodeGen/RISCV/verify-instr.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not llc -march=riscv32 -run-pass machineverifier %s -o - 2>&1 | FileCheck %s # CHECK: *** Bad machine code: Invalid immediate *** # CHECK: - instruction: $x2 = ADDI $x1, 10000 diff --git a/llvm/test/CodeGen/SPARC/codemodel.ll b/llvm/test/CodeGen/SPARC/codemodel.ll index fae56b801c9c..68da48a0e950 100644 --- a/llvm/test/CodeGen/SPARC/codemodel.ll +++ b/llvm/test/CodeGen/SPARC/codemodel.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=sparc64-unknown-linux -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=sparc64-unknown-linux -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL +; RUN: not llc -verify-machineinstrs -o - -mtriple=sparc64-unknown-linux -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY +; RUN: not llc -verify-machineinstrs -o - -mtriple=sparc64-unknown-linux -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL ; TINY: Target does not support the tiny CodeModel ; KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/SPARC/fail-alloca-align.ll b/llvm/test/CodeGen/SPARC/fail-alloca-align.ll index 062e3a4489f2..b8d84a901f56 100644 --- a/llvm/test/CodeGen/SPARC/fail-alloca-align.ll +++ b/llvm/test/CodeGen/SPARC/fail-alloca-align.ll @@ -2,8 +2,8 @@ ;; alignment greater than the stack alignment. This code ought to ;; compile, but doesn't currently. -;; RUN: not --crash llc -march=sparc < %s 2>&1 | FileCheck %s -;; RUN: not --crash llc -march=sparcv9 < %s 2>&1 | FileCheck %s +;; RUN: not llc -march=sparc < %s 2>&1 | FileCheck %s +;; RUN: not llc -march=sparcv9 < %s 2>&1 | FileCheck %s ;; CHECK: ERROR: Function {{.*}} required stack re-alignment define void @variable_alloca_with_overalignment(i32 %num) { diff --git a/llvm/test/CodeGen/SPARC/sret-secondary.ll b/llvm/test/CodeGen/SPARC/sret-secondary.ll index 8f334e823834..4efcabfc6fb3 100644 --- a/llvm/test/CodeGen/SPARC/sret-secondary.ll +++ b/llvm/test/CodeGen/SPARC/sret-secondary.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -march=sparc < %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not llc -march=sparc < %s -o /dev/null 2>&1 | FileCheck %s ; CHECK: sparc only supports sret on the first parameter diff --git a/llvm/test/CodeGen/SystemZ/codemodel.ll b/llvm/test/CodeGen/SystemZ/codemodel.ll index a96a28a5167c..4375366cfd79 100644 --- a/llvm/test/CodeGen/SystemZ/codemodel.ll +++ b/llvm/test/CodeGen/SystemZ/codemodel.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=s390x-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY -; RUN: not --crash llc -verify-machineinstrs -o - -mtriple=s390x-linux-gnu -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL +; RUN: not llc -verify-machineinstrs -o - -mtriple=s390x-linux-gnu -code-model=tiny < %s 2>&1 | FileCheck %s --check-prefix=TINY +; RUN: not llc -verify-machineinstrs -o - -mtriple=s390x-linux-gnu -code-model=kernel < %s 2>&1 | FileCheck %s --check-prefix=KERNEL ; TINY: Target does not support the tiny CodeModel ; KERNEL: Target does not support the kernel CodeModel diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-02.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-02.ll index dfe3b2694172..1d13429d2084 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-02.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-02.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; Check that no more than 12 integer arguments are passed ; -; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc void @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-03.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-03.ll index 1761cc4f09b7..1db7a3ff3dbb 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-03.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-03.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; In GHC calling convention the only allowed return type is void ; -; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc i64 @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-04.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-04.ll index d6b089808cf7..0dbe5472207a 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-04.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-04.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; Thread local storage is not supported in GHC calling convention ; -; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s @x = thread_local global i32 0 diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-05.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-05.ll index 68c0ee2e9ed9..be2cc67807bf 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-05.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-05.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; Variable-sized stack allocations are not supported in GHC calling convention ; -; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc void @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-06.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-06.ll index e0213e925936..04df248c29f8 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-06.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-06.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; At most 2048*sizeof(long)=16384 bytes of stack space may be used ; -; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc void @foo() nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/ghc-cc-07.ll b/llvm/test/CodeGen/SystemZ/ghc-cc-07.ll index 278e64303803..e9bb3b5e18a3 100644 --- a/llvm/test/CodeGen/SystemZ/ghc-cc-07.ll +++ b/llvm/test/CodeGen/SystemZ/ghc-cc-07.ll @@ -1,7 +1,7 @@ ; Check that the GHC calling convention works (s390x) ; In GHC calling convention a frame pointer is not supported ; -; RUN: not --crash llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s +; RUN: not llc -mtriple=s390x-ibm-linux < %s 2>&1 | FileCheck %s define ghccc void @foo(i64 %0) nounwind { entry: diff --git a/llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll b/llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll index d6bb1ae7150a..4a3629111318 100644 --- a/llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll +++ b/llvm/test/CodeGen/SystemZ/mnop-mcount-02.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc %s -mtriple=s390x-linux-gnu -o - 2>&1 | FileCheck %s +; RUN: not llc %s -mtriple=s390x-linux-gnu -o - 2>&1 | FileCheck %s ; ; CHECK: LLVM ERROR: mnop-mcount only supported with fentry-call diff --git a/llvm/test/CodeGen/SystemZ/mrecord-mcount-02.ll b/llvm/test/CodeGen/SystemZ/mrecord-mcount-02.ll index e1f4a3748b76..9ce7cdd418e3 100644 --- a/llvm/test/CodeGen/SystemZ/mrecord-mcount-02.ll +++ b/llvm/test/CodeGen/SystemZ/mrecord-mcount-02.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc %s -mtriple=s390x-linux-gnu -o - 2>&1 | FileCheck %s +; RUN: not llc %s -mtriple=s390x-linux-gnu -o - 2>&1 | FileCheck %s ; ; CHECK: LLVM ERROR: mrecord-mcount only supported with fentry-call diff --git a/llvm/test/CodeGen/SystemZ/mverify-optypes.mir b/llvm/test/CodeGen/SystemZ/mverify-optypes.mir index cc0be4423348..aebafd395623 100644 --- a/llvm/test/CodeGen/SystemZ/mverify-optypes.mir +++ b/llvm/test/CodeGen/SystemZ/mverify-optypes.mir @@ -1,5 +1,6 @@ -# RUN: not --crash llc -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass=none -o - %s \ +# RUN: not llc -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass=none -o - %s \ # RUN: 2>&1 | FileCheck %s +# REQUIRES: asserts # # Test that the machine verifier catches wrong operand types. diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-01.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-01.ll index 5680873fb8ee..e2f537949595 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-01.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-01.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s define void @foo(<1 x i128>) { ret void diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-02.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-02.ll index 7c0efe5b8afe..a5ae1102a748 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-02.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-02.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s define <1 x i128> @foo() { ret <1 x i128> diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-03.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-03.ll index 7c8be0136345..14698aae43bc 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-03.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-03.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s declare void @bar(<1 x i128>) diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-04.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-04.ll index f0b248c93486..a54ee90022c8 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-04.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-04.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s declare <1 x i128> @bar() diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-05.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-05.ll index c04095e7a737..067deb1c88b8 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-05.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-05.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s define void @foo(<1 x fp128>) { ret void diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-06.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-06.ll index 73891be036a8..a9184d735750 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-06.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-06.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s define <1 x fp128> @foo() { ret <1 x fp128> diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-07.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-07.ll index 4914217f0026..4e9140093915 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-07.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-07.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s declare void @bar(<1 x fp128>) diff --git a/llvm/test/CodeGen/SystemZ/vec-args-error-08.ll b/llvm/test/CodeGen/SystemZ/vec-args-error-08.ll index 8670b8fa4c78..7b16b9f46e39 100644 --- a/llvm/test/CodeGen/SystemZ/vec-args-error-08.ll +++ b/llvm/test/CodeGen/SystemZ/vec-args-error-08.ll @@ -1,6 +1,6 @@ ; Verify that we detect unsupported single-element vector types. -; RUN: not --crash llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 2>&1 | FileCheck %s declare <1 x fp128> @bar() diff --git a/llvm/test/CodeGen/WebAssembly/clear-cache.ll b/llvm/test/CodeGen/WebAssembly/clear-cache.ll index 4e1aee438ebe..cab948828233 100644 --- a/llvm/test/CodeGen/WebAssembly/clear-cache.ll +++ b/llvm/test/CodeGen/WebAssembly/clear-cache.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -asm-verbose=false 2>&1 | FileCheck %s +; RUN: not llc < %s -asm-verbose=false 2>&1 | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target triple = "wasm32-unknown-unknown" diff --git a/llvm/test/CodeGen/WebAssembly/cpus.ll b/llvm/test/CodeGen/WebAssembly/cpus.ll index b9210bd4d7f9..01964e9c85ab 100644 --- a/llvm/test/CodeGen/WebAssembly/cpus.ll +++ b/llvm/test/CodeGen/WebAssembly/cpus.ll @@ -1,13 +1,13 @@ ; This tests that llc accepts all valid WebAssembly CPUs. ; RUN: llc < %s -asm-verbose=false -mtriple=wasm32-unknown-unknown -mcpu=mvp 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=mvp 2>&1 | FileCheck %s --check-prefix=WASM64 +; RUN: not llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=mvp 2>&1 | FileCheck %s --check-prefix=WASM64 ; RUN: llc < %s -asm-verbose=false -mtriple=wasm32-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=generic 2>&1 | FileCheck %s --check-prefix=WASM64 +; RUN: not llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=generic 2>&1 | FileCheck %s --check-prefix=WASM64 ; RUN: llc < %s -asm-verbose=false -mtriple=wasm32-unknown-unknown -mcpu=bleeding-edge 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=bleeding-edge 2>&1 | FileCheck %s --check-prefix=WASM64 +; RUN: not llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=bleeding-edge 2>&1 | FileCheck %s --check-prefix=WASM64 ; RUN: llc < %s -asm-verbose=false -mtriple=wasm32-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID -; RUN: not --crash llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=WASM64 +; RUN: not llc < %s -asm-verbose=false -mtriple=wasm64-unknown-unknown-wasm -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=WASM64 ; CHECK-NOT: is not a recognized processor for this target ; INVALID: {{.+}} is not a recognized processor for this target diff --git a/llvm/test/CodeGen/WebAssembly/exception.ll b/llvm/test/CodeGen/WebAssembly/exception.ll index 375b4c0c4376..af470b27e89d 100644 --- a/llvm/test/CodeGen/WebAssembly/exception.ll +++ b/llvm/test/CodeGen/WebAssembly/exception.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm +; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -exception-model=wasm -mattr=+exception-handling -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap %s ; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-keep-registers -exception-model=wasm -mattr=+exception-handling diff --git a/llvm/test/CodeGen/WebAssembly/offset-atomics.ll b/llvm/test/CodeGen/WebAssembly/offset-atomics.ll index 43966a80ba4e..6884b6a56ee7 100644 --- a/llvm/test/CodeGen/WebAssembly/offset-atomics.ll +++ b/llvm/test/CodeGen/WebAssembly/offset-atomics.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt +; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+atomics,+sign-ext | FileCheck %s ; Test that atomic loads are assembled properly. diff --git a/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll b/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll index 1ce100b8653c..41dbd476b065 100644 --- a/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll +++ b/llvm/test/CodeGen/WebAssembly/tls-general-dynamic.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory 2>&1 | FileCheck %s --check-prefix=ERROR -; RUN: not --crash llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory -fast-isel 2>&1 | FileCheck %s --check-prefix=ERROR +; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory 2>&1 | FileCheck %s --check-prefix=ERROR +; RUN: not llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory -fast-isel 2>&1 | FileCheck %s --check-prefix=ERROR ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory --mtriple wasm32-unknown-emscripten | FileCheck %s --check-prefixes=CHECK,TLS ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=+bulk-memory --mtriple wasm32-unknown-emscripten -fast-isel | FileCheck %s --check-prefixes=CHECK,TLS ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -mattr=-bulk-memory | FileCheck %s --check-prefixes=CHECK,NO-TLS diff --git a/llvm/test/CodeGen/X86/AppendingLinkage.ll b/llvm/test/CodeGen/X86/AppendingLinkage.ll index 83bfbe85240a..5ab49a28e96d 100644 --- a/llvm/test/CodeGen/X86/AppendingLinkage.ll +++ b/llvm/test/CodeGen/X86/AppendingLinkage.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -mtriple=i686-- 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=i686-- 2>&1 | FileCheck %s ; CHECK: unknown special variable @foo = appending constant [1 x i32 ]zeroinitializer diff --git a/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir b/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir index 2c70ed3b0451..31f1da5c674f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -run-pass=instruction-select -pass-remarks-missed=gisel %s 2>&1 | FileCheck %s +# RUN: not llc -o - -run-pass=instruction-select -pass-remarks-missed=gisel %s 2>&1 | FileCheck %s --- | target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64--linux-gnu" diff --git a/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir b/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir index fd726b882b56..77962d7fbfa3 100644 --- a/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir +++ b/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-offset.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ +# RUN: not llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ # RUN: -run-pass=cfi-instr-inserter 2>&1 | FileCheck %s # Test that CFI verifier finds inconsistent offset between bb.end and one of # its precedessors. diff --git a/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir b/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir index 30344edc259c..1a247824bc9e 100644 --- a/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir +++ b/llvm/test/CodeGen/X86/cfi-inserter-verify-inconsistent-register.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ +# RUN: not llc -o - %s -mtriple=x86_64-- -verify-cfiinstrs \ # RUN: -run-pass=cfi-instr-inserter 2>&1 | FileCheck %s # Test that CFI verifier finds inconsistent register between bb.end and one of # its precedessors. diff --git a/llvm/test/CodeGen/X86/clwb.ll b/llvm/test/CodeGen/X86/clwb.ll index 75ca48329eed..90862343d31c 100644 --- a/llvm/test/CodeGen/X86/clwb.ll +++ b/llvm/test/CodeGen/X86/clwb.ll @@ -3,7 +3,7 @@ ; NOTE: Cannon Lake arch, but available again in the newer Ice Lake arch. ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=clwb | FileCheck %s ; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=skx | FileCheck %s -; RUN: not --crash llc < %s -mtriple=i686-apple-darwin -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CNL +; RUN: not llc < %s -mtriple=i686-apple-darwin -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CNL ; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=icelake-client | FileCheck %s ; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=icelake-server | FileCheck %s diff --git a/llvm/test/CodeGen/X86/codemodel.ll b/llvm/test/CodeGen/X86/codemodel.ll index 9aba38ab3a26..d7ed7c460889 100644 --- a/llvm/test/CodeGen/X86/codemodel.ll +++ b/llvm/test/CodeGen/X86/codemodel.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s ; RUN: llc < %s -code-model=kernel | FileCheck -check-prefix CHECK-KERNEL %s -; RUN: not --crash llc < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s +; RUN: not llc < %s -code-model=tiny 2>&1 | FileCheck -check-prefix CHECK-TINY %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/coff-comdat2.ll b/llvm/test/CodeGen/X86/coff-comdat2.ll index 3538e7ec1017..a417d096c47d 100644 --- a/llvm/test/CodeGen/X86/coff-comdat2.ll +++ b/llvm/test/CodeGen/X86/coff-comdat2.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not llc %s -o /dev/null 2>&1 | FileCheck %s target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32" target triple = "i686-pc-windows-msvc" diff --git a/llvm/test/CodeGen/X86/coff-comdat3.ll b/llvm/test/CodeGen/X86/coff-comdat3.ll index 95a23742efae..01651ce4820a 100644 --- a/llvm/test/CodeGen/X86/coff-comdat3.ll +++ b/llvm/test/CodeGen/X86/coff-comdat3.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not llc %s -o /dev/null 2>&1 | FileCheck %s target datalayout = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32" target triple = "i686-pc-windows-msvc" diff --git a/llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll b/llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll index cb5c8f714321..0dadc599abdb 100644 --- a/llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll +++ b/llvm/test/CodeGen/X86/cpus-amd-no-x86_64.ll @@ -2,15 +2,15 @@ ; CHECK-NO-ERROR-NOT: not a recognized processor for this target ; CHECK-ERROR64: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it! -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-tbird 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-mp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=geode 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=k6-3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-tbird 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-xp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=athlon-mp 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=geode 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 define void @foo() { ret void diff --git a/llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll b/llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll index cf133aea6359..d28ac9a83fd8 100644 --- a/llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll +++ b/llvm/test/CodeGen/X86/cpus-intel-no-x86_64.ll @@ -2,22 +2,22 @@ ; CHECK-NO-ERROR-NOT: not a recognized processor for this target ; CHECK-ERROR64: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it! -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i386 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i486 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i386 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i486 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i586 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-mmx 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=i686 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentiumpro 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium3m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium-m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=pentium4m 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=yonah 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=prescott 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=lakemont 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 define void @foo() { ret void diff --git a/llvm/test/CodeGen/X86/cpus-no-x86_64.ll b/llvm/test/CodeGen/X86/cpus-no-x86_64.ll index 6f74d4b29dab..e2e000386717 100644 --- a/llvm/test/CodeGen/X86/cpus-no-x86_64.ll +++ b/llvm/test/CodeGen/X86/cpus-no-x86_64.ll @@ -2,10 +2,10 @@ ; CHECK-NO-ERROR-NOT: not a recognized processor for this target ; CHECK-ERROR64: LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it! -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip-c6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 -; RUN: not --crash llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip-c6 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=winchip2 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR64 +; RUN: not llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=c3-2 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR define void @foo() { ret void diff --git a/llvm/test/CodeGen/X86/equiv_with_fndef.ll b/llvm/test/CodeGen/X86/equiv_with_fndef.ll index 3da0aa60250c..efbb8ab3da69 100644 --- a/llvm/test/CodeGen/X86/equiv_with_fndef.ll +++ b/llvm/test/CodeGen/X86/equiv_with_fndef.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s 2>&1 | FileCheck %s +; RUN: not llc < %s 2>&1 | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/equiv_with_vardef.ll b/llvm/test/CodeGen/X86/equiv_with_vardef.ll index e5ea3673b6d7..29c19a107ec3 100644 --- a/llvm/test/CodeGen/X86/equiv_with_vardef.ll +++ b/llvm/test/CodeGen/X86/equiv_with_vardef.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s 2>&1 | FileCheck %s +; RUN: not llc < %s 2>&1 | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/CodeGen/X86/expand-integer-x86_64-intrinsic-error.ll b/llvm/test/CodeGen/X86/expand-integer-x86_64-intrinsic-error.ll index d0d28db04f44..34f3c258f738 100644 --- a/llvm/test/CodeGen/X86/expand-integer-x86_64-intrinsic-error.ll +++ b/llvm/test/CodeGen/X86/expand-integer-x86_64-intrinsic-error.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -mtriple=i686-unknown-unknown -mattr=sse2 2>&1 | FileCheck %s --check-prefix=CHECK +;RUN: not llc < %s -mtriple=i686-unknown-unknown -mattr=sse2 2>&1 | FileCheck %s --check-prefix=CHECK ; Make sure we generate fatal error from the type legalizer for using a 64-bit ; mode intrinsics in 32-bit mode. We used to use an llvm_unreachable. diff --git a/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll b/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll index 007ac1d9a3c2..f7066577f2de 100644 --- a/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll +++ b/llvm/test/CodeGen/X86/fast-isel-args-fail2.ll @@ -1,4 +1,5 @@ -; RUN: not --crash llc < %s -fast-isel -fast-isel-abort=2 -mtriple=x86_64-apple-darwin10 +; RUN: not llc < %s -fast-isel -fast-isel-abort=2 -mtriple=x86_64-apple-darwin10 +; REQUIRES: asserts %struct.s0 = type { x86_fp80, x86_fp80 } diff --git a/llvm/test/CodeGen/X86/inalloca-regparm.ll b/llvm/test/CodeGen/X86/inalloca-regparm.ll index d379333a962f..9dd916bfbb37 100644 --- a/llvm/test/CodeGen/X86/inalloca-regparm.ll +++ b/llvm/test/CodeGen/X86/inalloca-regparm.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=i686-windows-msvc < %s -o /dev/null -; RUN: not --crash llc -mtriple=x86_64-windows-msvc %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not llc -mtriple=x86_64-windows-msvc %s -o /dev/null 2>&1 | FileCheck %s ; This will compile successfully on x86 but not x86_64, because %b will become a ; register parameter. diff --git a/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll b/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll index c8074dfa295e..c4bdfb6a1038 100644 --- a/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll +++ b/llvm/test/CodeGen/X86/inline-asm-avx-v-constraint-32bit.ll @@ -1,7 +1,5 @@ ; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx -o /dev/null 2> %t ; RUN: FileCheck %s --input-file %t -; XFAIL: * -; Temporarily disable this since the llc return code depents on bots. define <4 x float> @testxmm_1(<4 x float> %_xmm0, i32 %_l) { ; CHECK: error: inline assembly requires more registers than available diff --git a/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll b/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll index bd8022f8e515..7278089348e2 100644 --- a/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll +++ b/llvm/test/CodeGen/X86/inline-asm-avx512vl-v-constraint-32bit.ll @@ -1,7 +1,5 @@ ; RUN: not llc < %s -mtriple i386-unknown-linux-gnu -mattr +avx512vl -o /dev/null 2> %t ; RUN: FileCheck %s --input-file %t -; XFAIL: * -; Temporarily disable this since the llc return code depents on bots. define <4 x float> @testxmm_1(<4 x float> %_xmm0, i64 %_l) { ; CHECK: error: inline assembly requires more registers than available diff --git a/llvm/test/CodeGen/X86/invalid-liveness.mir b/llvm/test/CodeGen/X86/invalid-liveness.mir index 416921ddcd01..c324241805ad 100644 --- a/llvm/test/CodeGen/X86/invalid-liveness.mir +++ b/llvm/test/CodeGen/X86/invalid-liveness.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=i686-- -run-pass liveintervals -o - %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=i686-- -run-pass liveintervals -o - %s 2>&1 | FileCheck %s # REQUIRES: asserts --- | diff --git a/llvm/test/CodeGen/X86/label-redefinition.ll b/llvm/test/CodeGen/X86/label-redefinition.ll index b5570e6931b9..9e88a18e8732 100644 --- a/llvm/test/CodeGen/X86/label-redefinition.ll +++ b/llvm/test/CodeGen/X86/label-redefinition.ll @@ -1,5 +1,5 @@ ; PR7054 -; RUN: not --crash llc %s -o - 2>&1 | grep "'_foo' label emitted multiple times to assembly" +; RUN: not llc %s -o - 2>&1 | grep "'_foo' label emitted multiple times to assembly" target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target triple = "i386-apple-darwin10.0.0" diff --git a/llvm/test/CodeGen/X86/llc-print-machineinstrs.mir b/llvm/test/CodeGen/X86/llc-print-machineinstrs.mir index c3f8df031337..a890840a478a 100644 --- a/llvm/test/CodeGen/X86/llc-print-machineinstrs.mir +++ b/llvm/test/CodeGen/X86/llc-print-machineinstrs.mir @@ -1,6 +1,6 @@ # Check that -print-machineinstrs doesn't assert when it's passed an unknown pass name. # RUN: llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=greedy %s -o /dev/null -# RUN: not --crash llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=unknown %s -o /dev/null 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64-- -start-before=greedy -print-machineinstrs=unknown %s -o /dev/null 2>&1 | FileCheck %s # CHECK: LLVM ERROR: "unknown" pass is not registered. ... diff --git a/llvm/test/CodeGen/X86/macho-comdat.ll b/llvm/test/CodeGen/X86/macho-comdat.ll index c96212127dba..60560470ed5b 100644 --- a/llvm/test/CodeGen/X86/macho-comdat.ll +++ b/llvm/test/CodeGen/X86/macho-comdat.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple x86_64-apple-darwin < %s 2> %t +; RUN: not llc -mtriple x86_64-apple-darwin < %s 2> %t ; RUN: FileCheck < %t %s $f = comdat any diff --git a/llvm/test/CodeGen/X86/named-reg-alloc.ll b/llvm/test/CodeGen/X86/named-reg-alloc.ll index 34c5ea99f94c..c33b4eb75d04 100644 --- a/llvm/test/CodeGen/X86/named-reg-alloc.ll +++ b/llvm/test/CodeGen/X86/named-reg-alloc.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/X86/named-reg-notareg.ll b/llvm/test/CodeGen/X86/named-reg-notareg.ll index 6da65e2dfd02..18c517d87810 100644 --- a/llvm/test/CodeGen/X86/named-reg-notareg.ll +++ b/llvm/test/CodeGen/X86/named-reg-notareg.ll @@ -1,5 +1,5 @@ -; RUN: not --crash llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s -; RUN: not --crash llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-apple-darwin 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_stack() nounwind { entry: diff --git a/llvm/test/CodeGen/X86/nonconst-static-ev.ll b/llvm/test/CodeGen/X86/nonconst-static-ev.ll index 23643a2aafdf..a0aa6152bd47 100644 --- a/llvm/test/CodeGen/X86/nonconst-static-ev.ll +++ b/llvm/test/CodeGen/X86/nonconst-static-ev.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=i686-linux-gnu < %s 2> %t +; RUN: not llc -mtriple=i686-linux-gnu < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s @0 = global i8 extractvalue ([1 x i8] select (i1 ptrtoint (i32* @1 to i1), [1 x i8] [ i8 1 ], [1 x i8] [ i8 2 ]), 0) diff --git a/llvm/test/CodeGen/X86/nonconst-static-iv.ll b/llvm/test/CodeGen/X86/nonconst-static-iv.ll index 0e35116e3f8a..b1a03cf8b2e5 100644 --- a/llvm/test/CodeGen/X86/nonconst-static-iv.ll +++ b/llvm/test/CodeGen/X86/nonconst-static-iv.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -mtriple=i686-linux-gnu < %s 2> %t +; RUN: not llc -mtriple=i686-linux-gnu < %s 2> %t ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s @0 = global i8 insertvalue( { i8 } select (i1 ptrtoint (i32* @1 to i1), { i8 } { i8 1 }, { i8 } { i8 2 }), i8 0, 0) diff --git a/llvm/test/CodeGen/X86/read-fp-no-frame-pointer.ll b/llvm/test/CodeGen/X86/read-fp-no-frame-pointer.ll index f59388e450ba..9f78c294ce88 100644 --- a/llvm/test/CodeGen/X86/read-fp-no-frame-pointer.ll +++ b/llvm/test/CodeGen/X86/read-fp-no-frame-pointer.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=x86_64-linux-gnueabi 2>&1 | FileCheck %s define i32 @get_frame() nounwind { entry: diff --git a/llvm/test/CodeGen/X86/segmented-stacks.ll b/llvm/test/CodeGen/X86/segmented-stacks.ll index 467182c9f407..c4539f7b1255 100644 --- a/llvm/test/CodeGen/X86/segmented-stacks.ll +++ b/llvm/test/CodeGen/X86/segmented-stacks.ll @@ -22,9 +22,9 @@ ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-dragonfly -filetype=obj -o /dev/null ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-mingw32 -filetype=obj -o /dev/null -; RUN: not --crash llc < %s -mcpu=generic -mtriple=x86_64-solaris 2> %t.log +; RUN: not llc < %s -mcpu=generic -mtriple=x86_64-solaris 2> %t.log ; RUN: FileCheck %s -input-file=%t.log -check-prefix=X64-Solaris -; RUN: not --crash llc < %s -mcpu=generic -mtriple=i686-freebsd 2> %t.log +; RUN: not llc < %s -mcpu=generic -mtriple=i686-freebsd 2> %t.log ; RUN: FileCheck %s -input-file=%t.log -check-prefix=X32-FreeBSD ; X64-Solaris: Segmented stacks not supported on this platform diff --git a/llvm/test/CodeGen/XCore/alignment.ll b/llvm/test/CodeGen/XCore/alignment.ll index 0c561ee4f6c6..28bdf3b74208 100644 --- a/llvm/test/CodeGen/XCore/alignment.ll +++ b/llvm/test/CodeGen/XCore/alignment.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=xcore 2>&1 | FileCheck %s +; RUN: not llc < %s -march=xcore 2>&1 | FileCheck %s ; CHECK: emitPrologue unsupported alignment: 8 define void @f() nounwind { diff --git a/llvm/test/CodeGen/XCore/codemodel.ll b/llvm/test/CodeGen/XCore/codemodel.ll index fdc0d086c679..93b9d6d911df 100644 --- a/llvm/test/CodeGen/XCore/codemodel.ll +++ b/llvm/test/CodeGen/XCore/codemodel.ll @@ -1,7 +1,7 @@ -; RUN: not --crash llc < %s -march=xcore -code-model=medium 2>&1 | FileCheck %s -check-prefix=BAD_CM -; RUN: not --crash llc < %s -march=xcore -code-model=kernel 2>&1 | FileCheck %s -check-prefix=BAD_CM -; RUN: not --crash llc < %s -march=xcore -code-model=tiny 2>&1 | FileCheck %s -check-prefix=BAD_CM +; RUN: not llc < %s -march=xcore -code-model=medium 2>&1 | FileCheck %s -check-prefix=BAD_CM +; RUN: not llc < %s -march=xcore -code-model=kernel 2>&1 | FileCheck %s -check-prefix=BAD_CM +; RUN: not llc < %s -march=xcore -code-model=tiny 2>&1 | FileCheck %s -check-prefix=BAD_CM ; BAD_CM: Target only supports CodeModel Small or Large diff --git a/llvm/test/CodeGen/XCore/section-name.ll b/llvm/test/CodeGen/XCore/section-name.ll index 4bf6aa1fc67a..65161db34bea 100644 --- a/llvm/test/CodeGen/XCore/section-name.ll +++ b/llvm/test/CodeGen/XCore/section-name.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -march=xcore 2>&1 | FileCheck %s +; RUN: not llc < %s -march=xcore 2>&1 | FileCheck %s @bar = internal global i32 zeroinitializer diff --git a/llvm/test/DebugInfo/COFF/types-recursive-unnamed.ll b/llvm/test/DebugInfo/COFF/types-recursive-unnamed.ll index 3f0a584b0e34..5e8edf5eb4f5 100644 --- a/llvm/test/DebugInfo/COFF/types-recursive-unnamed.ll +++ b/llvm/test/DebugInfo/COFF/types-recursive-unnamed.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc < %s -filetype=obj 2>&1 | FileCheck %s +; RUN: not llc < %s -filetype=obj 2>&1 | FileCheck %s ; ; Verify the compiler produces an error message when trying to emit circular ; references to unnamed structs which are not supported in CodeView debug diff --git a/llvm/test/LTO/X86/attrs.ll b/llvm/test/LTO/X86/attrs.ll index 4444735188fb..d1967470cdd3 100644 --- a/llvm/test/LTO/X86/attrs.ll +++ b/llvm/test/LTO/X86/attrs.ll @@ -1,7 +1,7 @@ ; RUN: llvm-as < %s >%t1 ; RUN: llvm-lto -exported-symbol=test_x86_aesni_aeskeygenassist -mattr=+aes -o %t2 %t1 ; RUN: llvm-objdump -d %t2 | FileCheck -check-prefix=WITH_AES %s -; RUN: not --crash llvm-lto -exported-symbol=test_x86_aesni_aeskeygenassist -mattr=-aes -o %t3 %t1 2>&1 | FileCheck -check-prefix=WITHOUT_AES %s +; RUN: not llvm-lto -exported-symbol=test_x86_aesni_aeskeygenassist -mattr=-aes -o %t3 %t1 2>&1 | FileCheck -check-prefix=WITHOUT_AES %s target triple = "x86_64-unknown-linux-gnu" declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8) diff --git a/llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s b/llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s index e831ac5c2af0..34d88918a349 100644 --- a/llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s +++ b/llvm/test/MC/ARM/AlignedBundling/illegal-subtarget-change.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple armv7-linux-gnueabi %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple armv7-linux-gnueabi %s -o - 2>&1 | FileCheck %s # We cannot switch subtargets mid-bundle .syntax unified diff --git a/llvm/test/MC/ARM/Windows/invalid-relocation.s b/llvm/test/MC/ARM/Windows/invalid-relocation.s index 61d11fb6a6b3..c3e74e97634b 100644 --- a/llvm/test/MC/ARM/Windows/invalid-relocation.s +++ b/llvm/test/MC/ARM/Windows/invalid-relocation.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -triple thumbv7-windows -incremental-linker-compatible -filetype obj -o /dev/null 2>&1 %s \ +# RUN: not llvm-mc -triple thumbv7-windows -incremental-linker-compatible -filetype obj -o /dev/null 2>&1 %s \ # RUN: | FileCheck %s .def invalid_relocation diff --git a/llvm/test/MC/COFF/section-comdat-conflict.s b/llvm/test/MC/COFF/section-comdat-conflict.s index 2710b76be565..7ed452a5cdcb 100644 --- a/llvm/test/MC/COFF/section-comdat-conflict.s +++ b/llvm/test/MC/COFF/section-comdat-conflict.s @@ -1,4 +1,4 @@ -// RUN: not --crash llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s // CHECK: conflicting sections for symbol diff --git a/llvm/test/MC/COFF/section-comdat-conflict2.s b/llvm/test/MC/COFF/section-comdat-conflict2.s index 2b863299561c..e2dfc2d68b2f 100644 --- a/llvm/test/MC/COFF/section-comdat-conflict2.s +++ b/llvm/test/MC/COFF/section-comdat-conflict2.s @@ -1,4 +1,4 @@ -// RUN: not --crash llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple i386-pc-win32 -filetype=obj < %s 2>&1 | FileCheck %s // CHECK: two sections have the same comdat diff --git a/llvm/test/MC/Disassembler/AMDGPU/si-support.txt b/llvm/test/MC/Disassembler/AMDGPU/si-support.txt index 5538983597f7..f3f5ab946eb3 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/si-support.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/si-support.txt @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -arch=amdgcn -mcpu=tahiti -disassemble < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -disassemble < %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: Disassembly not yet supported for subtarget 0x00 0x00 0x00 0x7e diff --git a/llvm/test/MC/ELF/ARM/bss-non-zero-value.s b/llvm/test/MC/ELF/ARM/bss-non-zero-value.s index da946f1c95d9..999b8b019c9c 100644 --- a/llvm/test/MC/ELF/ARM/bss-non-zero-value.s +++ b/llvm/test/MC/ELF/ARM/bss-non-zero-value.s @@ -1,4 +1,4 @@ -// RUN: not --crash llvm-mc -filetype=obj -triple arm-linux-gnu %s -o %t 2>%t.out +// RUN: not llvm-mc -filetype=obj -triple arm-linux-gnu %s -o %t 2>%t.out // RUN: FileCheck --input-file=%t.out %s // CHECK: non-zero initializer found in section '.bss' .bss diff --git a/llvm/test/MC/ELF/common-error3.s b/llvm/test/MC/ELF/common-error3.s index e5204914970e..a84779e653e0 100644 --- a/llvm/test/MC/ELF/common-error3.s +++ b/llvm/test/MC/ELF/common-error3.s @@ -1,5 +1,5 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux %s 2>&1 | FileCheck %s # CHECK: Symbol: C redeclared as different type .comm C,4,4 - .comm C,8,4 + .comm C,8,4 \ No newline at end of file diff --git a/llvm/test/MC/ELF/section-numeric-invalid-type.s b/llvm/test/MC/ELF/section-numeric-invalid-type.s index 0e721099ff7c..19796dc64ac1 100644 --- a/llvm/test/MC/ELF/section-numeric-invalid-type.s +++ b/llvm/test/MC/ELF/section-numeric-invalid-type.s @@ -1,7 +1,7 @@ // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux-gnu %s -o - \ // RUN: | llvm-readobj -S --symbols | FileCheck --check-prefix=OBJ %s -// RUN: not --crash llvm-mc -filetype=asm -triple=x86_64-pc-linux-gnu %s -o - 2>&1 \ +// RUN: not llvm-mc -filetype=asm -triple=x86_64-pc-linux-gnu %s -o - 2>&1 \ // RUN: | FileCheck --check-prefix=ASM %s .section .sec,"a",@0x7fffffff diff --git a/llvm/test/MC/MachO/variable-errors.s b/llvm/test/MC/MachO/variable-errors.s index 952212041d56..28308c691d91 100644 --- a/llvm/test/MC/MachO/variable-errors.s +++ b/llvm/test/MC/MachO/variable-errors.s @@ -1,4 +1,4 @@ -// RUN: not --crash llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o %t.o 2> %t.err +// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o %t.o 2> %t.err // RUN: FileCheck < %t.err %s .data diff --git a/llvm/test/MC/Mips/micromips64-unsupported.s b/llvm/test/MC/Mips/micromips64-unsupported.s index 05c4bc9df043..bc38cfb41f74 100644 --- a/llvm/test/MC/Mips/micromips64-unsupported.s +++ b/llvm/test/MC/Mips/micromips64-unsupported.s @@ -1,8 +1,8 @@ -# RUN: not --crash llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6 -# RUN: not --crash llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6 +# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6 +# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64R6 -# RUN: not --crash llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64 -# RUN: not --crash llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64 +# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n64 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64 +# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 2>&1 -mattr=+micromips | FileCheck %s --check-prefix=64 # 64R6: microMIPS64R6 is not supported # 64: microMIPS64 is not supported diff --git a/llvm/test/MC/Mips/micromips64r6-unsupported.s b/llvm/test/MC/Mips/micromips64r6-unsupported.s index d2afff72aa71..402e66724e46 100644 --- a/llvm/test/MC/Mips/micromips64r6-unsupported.s +++ b/llvm/test/MC/Mips/micromips64r6-unsupported.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple=mips64-unknown-linux -mattr=+micromips \ +# RUN: not llvm-mc -filetype=obj -triple=mips64-unknown-linux -mattr=+micromips \ # RUN: -mcpu=mips64r6 %s 2>&1 | FileCheck %s -check-prefix=CHECK-OPTION # RUN: not llvm-mc -filetype=obj -triple=mips64-unknown-linux -mcpu=mips64r6 \ # RUN: %s 2>&1 | FileCheck %s -check-prefix=CHECK-MM-DIRECTIVE diff --git a/llvm/test/MC/Mips/nooddspreg-cmdarg.s b/llvm/test/MC/Mips/nooddspreg-cmdarg.s index ef38331b5163..2ccce74a5f15 100644 --- a/llvm/test/MC/Mips/nooddspreg-cmdarg.s +++ b/llvm/test/MC/Mips/nooddspreg-cmdarg.s @@ -5,10 +5,10 @@ # RUN: llvm-readobj --sections --section-data --section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ -# RUN: not --crash llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -mattr=+nooddspreg 2> %t0 +# RUN: not llvm-mc %s -triple mips64-unknown-linux-gnuabin32 -mattr=+nooddspreg 2> %t0 # RUN: FileCheck %s -check-prefix=INVALID < %t0 # -# RUN: not --crash llvm-mc %s -triple mips64-unknown-linux-gnu -mattr=+nooddspreg 2> %t0 +# RUN: not llvm-mc %s -triple mips64-unknown-linux-gnu -mattr=+nooddspreg 2> %t0 # RUN: FileCheck %s -check-prefix=INVALID < %t0 # # CHECK-ASM-NOT: .module nooddspreg diff --git a/llvm/test/MC/PowerPC/ppc64-localentry-error1.s b/llvm/test/MC/PowerPC/ppc64-localentry-error1.s index c028da8ce619..e47640fbeb05 100644 --- a/llvm/test/MC/PowerPC/ppc64-localentry-error1.s +++ b/llvm/test/MC/PowerPC/ppc64-localentry-error1.s @@ -1,7 +1,7 @@ -# RUN: not --crash llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t +# RUN: not llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t # RUN: FileCheck < %t %s -# RUN: not --crash llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t +# RUN: not llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t # RUN: FileCheck < %t %s sym: diff --git a/llvm/test/MC/PowerPC/ppc64-localentry-error2.s b/llvm/test/MC/PowerPC/ppc64-localentry-error2.s index 89a30ee4c8ac..b05687fe7b6f 100644 --- a/llvm/test/MC/PowerPC/ppc64-localentry-error2.s +++ b/llvm/test/MC/PowerPC/ppc64-localentry-error2.s @@ -1,7 +1,7 @@ -# RUN: not --crash llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t +# RUN: not llvm-mc -triple powerpc64-unknown-unknown -filetype=obj < %s 2> %t # RUN: FileCheck < %t %s -# RUN: not --crash llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t +# RUN: not llvm-mc -triple powerpc64le-unknown-unknown -filetype=obj < %s 2> %t # RUN: FileCheck < %t %s .globl remote_sym diff --git a/llvm/test/MC/PowerPC/pr24686.s b/llvm/test/MC/PowerPC/pr24686.s index 35a379c697ea..28cba230b8c4 100644 --- a/llvm/test/MC/PowerPC/pr24686.s +++ b/llvm/test/MC/PowerPC/pr24686.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -triple=powerpc64le-unknown-linux-gnu -filetype=obj %s \ +# RUN: not llvm-mc -triple=powerpc64le-unknown-linux-gnu -filetype=obj %s \ # RUN: 2>&1 | FileCheck %s _stext: diff --git a/llvm/test/MC/RISCV/mattr-invalid-combination.s b/llvm/test/MC/RISCV/mattr-invalid-combination.s index f75fd3723ed4..340a2f257875 100644 --- a/llvm/test/MC/RISCV/mattr-invalid-combination.s +++ b/llvm/test/MC/RISCV/mattr-invalid-combination.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \ # RUN: | FileCheck %s -check-prefix=RV64E # RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target diff --git a/llvm/test/MC/WebAssembly/blockaddress.ll b/llvm/test/MC/WebAssembly/blockaddress.ll index 2b733e0d37c8..52127ab27c84 100644 --- a/llvm/test/MC/WebAssembly/blockaddress.ll +++ b/llvm/test/MC/WebAssembly/blockaddress.ll @@ -1,6 +1,6 @@ ; TODO(sbc): Make this test pass by adding support for unnamed tempoaries ; in wasm relocations. -; RUN: not --crash llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s target triple = "wasm32-unknown-unknown" diff --git a/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll b/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll index 84d7c537a4f4..7e9b28ac243b 100644 --- a/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll +++ b/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll @@ -1,4 +1,4 @@ -; RUN: not --crash llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s ; CHECK: data symbols must live in a data section: data_symbol target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" diff --git a/llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s b/llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s index 697b8bf6ab6c..5ce788098f36 100644 --- a/llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s +++ b/llvm/test/MC/X86/AlignedBundling/bundle-group-too-large-error.s @@ -1,5 +1,5 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mc-relax-all %s -o - 2>&1 | FileCheck %s # CHECK: ERROR: Fragment can't be larger than a bundle size diff --git a/llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s b/llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s index b849d2b33300..b0b595f4812f 100644 --- a/llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s +++ b/llvm/test/MC/X86/AlignedBundling/bundle-lock-option-error.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s # Missing .bundle_align_mode argument # CHECK: error: invalid option diff --git a/llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s b/llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s index c02d0d6b19b4..67ac55ed2f03 100644 --- a/llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s +++ b/llvm/test/MC/X86/AlignedBundling/bundle-subtarget-change-error.s @@ -1,5 +1,5 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - 2>&1 | FileCheck %s -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu -mcpu=pentiumpro -mc-relax-all %s -o - 2>&1 | FileCheck %s # Switching mode will change subtarget, which we can't do within a bundle .text diff --git a/llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s b/llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s index 65ee2d5b9f38..2f716544b154 100644 --- a/llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s +++ b/llvm/test/MC/X86/AlignedBundling/lock-without-bundle-mode-error.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s # .bundle_lock can't come without a .bundle_align_mode before it diff --git a/llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s b/llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s index 6ea3c36beb1c..a5812fd28ab1 100644 --- a/llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s +++ b/llvm/test/MC/X86/AlignedBundling/switch-section-locked-error.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s # This test invokes .bundle_lock and then switches to a different section # w/o the appropriate unlock. diff --git a/llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s b/llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s index 811ef95a451d..a73f19ea4836 100644 --- a/llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s +++ b/llvm/test/MC/X86/AlignedBundling/unlock-without-lock-error.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - 2>&1 | FileCheck %s # .bundle_unlock can't come without a .bundle_lock before it diff --git a/llvm/test/MC/X86/check-end-of-data-region.s b/llvm/test/MC/X86/check-end-of-data-region.s index 50f5dab73d35..3f7d9b617ef6 100644 --- a/llvm/test/MC/X86/check-end-of-data-region.s +++ b/llvm/test/MC/X86/check-end-of-data-region.s @@ -1,4 +1,4 @@ -// RUN: not --crash llvm-mc -triple=x86_64-apple-darwin -filetype=obj -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not llvm-mc -triple=x86_64-apple-darwin -filetype=obj -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR .align 4 .data_region jt32 diff --git a/llvm/test/MC/X86/encoder-fail.s b/llvm/test/MC/X86/encoder-fail.s index d8d321fa8a1a..3e845fe7561b 100644 --- a/llvm/test/MC/X86/encoder-fail.s +++ b/llvm/test/MC/X86/encoder-fail.s @@ -1,3 +1,3 @@ -// RUN: not --crash llvm-mc -triple x86_64-unknown-unknown --show-encoding %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple x86_64-unknown-unknown --show-encoding %s 2>&1 | FileCheck %s // CHECK: LLVM ERROR: Cannot encode high byte register in REX-prefixed instruction movzx %dh, %rsi diff --git a/llvm/test/MC/X86/invalid-sleb.s b/llvm/test/MC/X86/invalid-sleb.s index 7d7df351ce4e..ad27444d608f 100644 --- a/llvm/test/MC/X86/invalid-sleb.s +++ b/llvm/test/MC/X86/invalid-sleb.s @@ -1,4 +1,4 @@ -// RUN: not --crash llvm-mc -filetype=obj -triple x86_64-pc-linux %s -o %t 2>&1 | FileCheck %s +// RUN: not llvm-mc -filetype=obj -triple x86_64-pc-linux %s -o %t 2>&1 | FileCheck %s // CHECK: sleb128 and uleb128 expressions must be absolute diff --git a/llvm/test/MC/X86/reloc-bss.s b/llvm/test/MC/X86/reloc-bss.s index 6463b866f095..3cf26d8b28e5 100644 --- a/llvm/test/MC/X86/reloc-bss.s +++ b/llvm/test/MC/X86/reloc-bss.s @@ -1,4 +1,4 @@ -# RUN: not --crash llvm-mc -filetype=obj -triple=x86_64-linux-gnu %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple=x86_64-linux-gnu %s 2>&1 | FileCheck %s # CHECK: LLVM ERROR: cannot have fixups in virtual section! .section .init_array,"awT",@nobits diff --git a/llvm/test/MachineVerifier/live-ins-01.mir b/llvm/test/MachineVerifier/live-ins-01.mir index 5d6d2fa399e7..51c05dacf055 100644 --- a/llvm/test/MachineVerifier/live-ins-01.mir +++ b/llvm/test/MachineVerifier/live-ins-01.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s +# RUN: not llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s # REQUIRES: systemz-registered-target # Test that a the machine verifier reports an error when a register in diff --git a/llvm/test/MachineVerifier/live-ins-02.mir b/llvm/test/MachineVerifier/live-ins-02.mir index 2cc63ac0cd21..d76325cdd108 100644 --- a/llvm/test/MachineVerifier/live-ins-02.mir +++ b/llvm/test/MachineVerifier/live-ins-02.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s +# RUN: not llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s # REQUIRES: systemz-registered-target # Test that a the machine verifier reports an error when a register in diff --git a/llvm/test/MachineVerifier/live-ins-03.mir b/llvm/test/MachineVerifier/live-ins-03.mir index ae640c439d3e..b5345ccdc3b6 100644 --- a/llvm/test/MachineVerifier/live-ins-03.mir +++ b/llvm/test/MachineVerifier/live-ins-03.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s +# RUN: not llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z14 -run-pass none 2>&1 | FileCheck %s # REQUIRES: systemz-registered-target # Test that a the machine verifier reports an error when a register in diff --git a/llvm/test/MachineVerifier/test_copy.mir b/llvm/test/MachineVerifier/test_copy.mir index 64c2761e7ea7..e234f45287ef 100644 --- a/llvm/test/MachineVerifier/test_copy.mir +++ b/llvm/test/MachineVerifier/test_copy.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | ; ModuleID = 'test.ll' diff --git a/llvm/test/MachineVerifier/test_copy_mismatch_types.mir b/llvm/test/MachineVerifier/test_copy_mismatch_types.mir index 3b7e54e0c1c4..905977938d51 100644 --- a/llvm/test/MachineVerifier/test_copy_mismatch_types.mir +++ b/llvm/test/MachineVerifier/test_copy_mismatch_types.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | ; ModuleID = 'test.ll' diff --git a/llvm/test/MachineVerifier/test_g_add.mir b/llvm/test/MachineVerifier/test_g_add.mir index 331f4bf351ab..9cd990bb8cc1 100644 --- a/llvm/test/MachineVerifier/test_g_add.mir +++ b/llvm/test/MachineVerifier/test_g_add.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_addrspacecast.mir b/llvm/test/MachineVerifier/test_g_addrspacecast.mir index fb71057c585c..88b411378792 100644 --- a/llvm/test/MachineVerifier/test_g_addrspacecast.mir +++ b/llvm/test/MachineVerifier/test_g_addrspacecast.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_bitcast.mir b/llvm/test/MachineVerifier/test_g_bitcast.mir index a399c859404f..3446d5fc86eb 100644 --- a/llvm/test/MachineVerifier/test_g_bitcast.mir +++ b/llvm/test/MachineVerifier/test_g_bitcast.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -mtriple=amdgcn-amd-amdhsa -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, amdgpu-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_brjt.mir b/llvm/test/MachineVerifier/test_g_brjt.mir index 7a8417efab85..e05dd5fadbc2 100644 --- a/llvm/test/MachineVerifier/test_g_brjt.mir +++ b/llvm/test/MachineVerifier/test_g_brjt.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_build_vector.mir b/llvm/test/MachineVerifier/test_g_build_vector.mir index 0c013dfa4778..77b5beb2fdd8 100644 --- a/llvm/test/MachineVerifier/test_g_build_vector.mir +++ b/llvm/test/MachineVerifier/test_g_build_vector.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- name: g_build_vector diff --git a/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir b/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir index 296713fce9fe..d73e37e1e6e3 100644 --- a/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir +++ b/llvm/test/MachineVerifier/test_g_build_vector_trunc.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/MachineVerifier/test_g_concat_vectors.mir b/llvm/test/MachineVerifier/test_g_concat_vectors.mir index 53e2eca00808..640c4a4ceedb 100644 --- a/llvm/test/MachineVerifier/test_g_concat_vectors.mir +++ b/llvm/test/MachineVerifier/test_g_concat_vectors.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/MachineVerifier/test_g_constant.mir b/llvm/test/MachineVerifier/test_g_constant.mir index cfdcae929ce1..fa5daff870b0 100644 --- a/llvm/test/MachineVerifier/test_g_constant.mir +++ b/llvm/test/MachineVerifier/test_g_constant.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir b/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir index 51c74e5992d2..e798f23e789c 100644 --- a/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir +++ b/llvm/test/MachineVerifier/test_g_dyn_stackalloc.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_extract.mir b/llvm/test/MachineVerifier/test_g_extract.mir index 2f326cb56ccf..62064ae80217 100644 --- a/llvm/test/MachineVerifier/test_g_extract.mir +++ b/llvm/test/MachineVerifier/test_g_extract.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_fcmp.mir b/llvm/test/MachineVerifier/test_g_fcmp.mir index 15373f8ff387..c7416d47dcd4 100644 --- a/llvm/test/MachineVerifier/test_g_fcmp.mir +++ b/llvm/test/MachineVerifier/test_g_fcmp.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_fconstant.mir b/llvm/test/MachineVerifier/test_g_fconstant.mir index 249a74a50157..d917d9c846ff 100644 --- a/llvm/test/MachineVerifier/test_g_fconstant.mir +++ b/llvm/test/MachineVerifier/test_g_fconstant.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_icmp.mir b/llvm/test/MachineVerifier/test_g_icmp.mir index 74448e736fd6..9582a1795123 100644 --- a/llvm/test/MachineVerifier/test_g_icmp.mir +++ b/llvm/test/MachineVerifier/test_g_icmp.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_insert.mir b/llvm/test/MachineVerifier/test_g_insert.mir index d12a2206c6c4..0785370ec174 100644 --- a/llvm/test/MachineVerifier/test_g_insert.mir +++ b/llvm/test/MachineVerifier/test_g_insert.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_intrinsic.mir b/llvm/test/MachineVerifier/test_g_intrinsic.mir index aac733a3bdf6..157edc09b801 100644 --- a/llvm/test/MachineVerifier/test_g_intrinsic.mir +++ b/llvm/test/MachineVerifier/test_g_intrinsic.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=amdgcn -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=amdgcn -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: amdgpu-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir b/llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir index 75e4e623c3e1..8e8627d2e723 100644 --- a/llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir +++ b/llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=amdgcn -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=amdgcn -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: amdgpu-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_inttoptr.mir b/llvm/test/MachineVerifier/test_g_inttoptr.mir index d0d356a1d7b6..2769c66c8cc7 100644 --- a/llvm/test/MachineVerifier/test_g_inttoptr.mir +++ b/llvm/test/MachineVerifier/test_g_inttoptr.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_jump_table.mir b/llvm/test/MachineVerifier/test_g_jump_table.mir index 3c837c295140..406edcbea5c2 100644 --- a/llvm/test/MachineVerifier/test_g_jump_table.mir +++ b/llvm/test/MachineVerifier/test_g_jump_table.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -march=aarch64 -o /dev/null -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_load.mir b/llvm/test/MachineVerifier/test_g_load.mir index ac28b513c1d8..18a7718b71b7 100644 --- a/llvm/test/MachineVerifier/test_g_load.mir +++ b/llvm/test/MachineVerifier/test_g_load.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_merge_values.mir b/llvm/test/MachineVerifier/test_g_merge_values.mir index 21b4079b5e1f..4829e8f13173 100644 --- a/llvm/test/MachineVerifier/test_g_merge_values.mir +++ b/llvm/test/MachineVerifier/test_g_merge_values.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- name: g_merge_values diff --git a/llvm/test/MachineVerifier/test_g_phi.mir b/llvm/test/MachineVerifier/test_g_phi.mir index 11e18e2220ad..c108ea613543 100644 --- a/llvm/test/MachineVerifier/test_g_phi.mir +++ b/llvm/test/MachineVerifier/test_g_phi.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | ; ModuleID = 'test.ll' diff --git a/llvm/test/MachineVerifier/test_g_ptr_add.mir b/llvm/test/MachineVerifier/test_g_ptr_add.mir index 9a918d2fc7f9..fd60a08e99c7 100644 --- a/llvm/test/MachineVerifier/test_g_ptr_add.mir +++ b/llvm/test/MachineVerifier/test_g_ptr_add.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_ptrtoint.mir b/llvm/test/MachineVerifier/test_g_ptrtoint.mir index f289a3d1dbed..c9a50bbded71 100644 --- a/llvm/test/MachineVerifier/test_g_ptrtoint.mir +++ b/llvm/test/MachineVerifier/test_g_ptrtoint.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +#RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_select.mir b/llvm/test/MachineVerifier/test_g_select.mir index ca0a94d6bc97..d40b276c9ba2 100644 --- a/llvm/test/MachineVerifier/test_g_select.mir +++ b/llvm/test/MachineVerifier/test_g_select.mir @@ -1,4 +1,4 @@ -#RUN: not --crash llc -march=aarch64 -run-pass=none -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s +#RUN: not llc -march=aarch64 -run-pass=none -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_sext_inreg.mir b/llvm/test/MachineVerifier/test_g_sext_inreg.mir index 120f9995d87d..32573cc9e0ce 100644 --- a/llvm/test/MachineVerifier/test_g_sext_inreg.mir +++ b/llvm/test/MachineVerifier/test_g_sext_inreg.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- | diff --git a/llvm/test/MachineVerifier/test_g_sextload.mir b/llvm/test/MachineVerifier/test_g_sextload.mir index f12fe1cb6bf0..ee822ea1104b 100644 --- a/llvm/test/MachineVerifier/test_g_sextload.mir +++ b/llvm/test/MachineVerifier/test_g_sextload.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir index 740293e79247..7e07fa9d4fca 100644 --- a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir +++ b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- name: g_shuffle_vector diff --git a/llvm/test/MachineVerifier/test_g_store.mir b/llvm/test/MachineVerifier/test_g_store.mir index 183935f052df..bb82042d6691 100644 --- a/llvm/test/MachineVerifier/test_g_store.mir +++ b/llvm/test/MachineVerifier/test_g_store.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_trunc.mir b/llvm/test/MachineVerifier/test_g_trunc.mir index 9dbeab2c6039..fd97b09af15c 100644 --- a/llvm/test/MachineVerifier/test_g_trunc.mir +++ b/llvm/test/MachineVerifier/test_g_trunc.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_g_zextload.mir b/llvm/test/MachineVerifier/test_g_zextload.mir index 3b65bf9c1726..bcb96e3875f9 100644 --- a/llvm/test/MachineVerifier/test_g_zextload.mir +++ b/llvm/test/MachineVerifier/test_g_zextload.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: global-isel, aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_memccpy_intrinsics.mir b/llvm/test/MachineVerifier/test_memccpy_intrinsics.mir index 03ba9e0d06f2..acdd9dd2b28c 100644 --- a/llvm/test/MachineVerifier/test_memccpy_intrinsics.mir +++ b/llvm/test/MachineVerifier/test_memccpy_intrinsics.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - -march=aarch64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# RUN: not llc -o - -march=aarch64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- diff --git a/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir b/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir index 0253e6ab952c..fa69b40fddf1 100644 --- a/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir +++ b/llvm/test/MachineVerifier/test_phis_precede_nonphis.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -run-pass=machineverifier %s -o - 2>&1 | FileCheck %s +# RUN: not llc -run-pass=machineverifier %s -o - 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- | diff --git a/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir b/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir index 38cf1859e6d1..8390d9bf3ce1 100644 --- a/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir +++ b/llvm/test/MachineVerifier/verifier-generic-extend-truncate.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s +# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s # REQUIRES: x86-registered-target # CHECK: Bad machine code: Generic extend/truncate can not operate on pointers diff --git a/llvm/test/MachineVerifier/verifier-generic-types-1.mir b/llvm/test/MachineVerifier/verifier-generic-types-1.mir index 884209f17362..bc2d2580ed17 100644 --- a/llvm/test/MachineVerifier/verifier-generic-types-1.mir +++ b/llvm/test/MachineVerifier/verifier-generic-types-1.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s +# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s # REQUIRES: x86-registered-target # CHECK-NOT: Type mismatch diff --git a/llvm/test/MachineVerifier/verifier-generic-types-2.mir b/llvm/test/MachineVerifier/verifier-generic-types-2.mir index 5558a2b654ac..27a14c222c6e 100644 --- a/llvm/test/MachineVerifier/verifier-generic-types-2.mir +++ b/llvm/test/MachineVerifier/verifier-generic-types-2.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s +# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s # REQUIRES: x86-registered-target # CHECK: Bad machine code: Generic instruction is missing a virtual register type diff --git a/llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir b/llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir index a723ee205ef0..fb4777898edd 100644 --- a/llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir +++ b/llvm/test/MachineVerifier/verifier-implicit-virtreg-invalid-physreg-liveness.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s +# RUN: not llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s # REQUIRES: amdgpu-registered-target # When the verifier was detecting the invalid liveness for vcc, it would assert when trying to iterate the subregisters of the implicit virtual register use. diff --git a/llvm/test/MachineVerifier/verifier-phi-fail0.mir b/llvm/test/MachineVerifier/verifier-phi-fail0.mir index aa488f064cc6..80a50b50937c 100644 --- a/llvm/test/MachineVerifier/verifier-phi-fail0.mir +++ b/llvm/test/MachineVerifier/verifier-phi-fail0.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s +# RUN: not llc -o - %s -mtriple=x86_64-- -verify-machineinstrs -run-pass=none 2>&1 | FileCheck %s # REQUIRES: x86-registered-target --- diff --git a/llvm/test/MachineVerifier/verifier-pseudo-terminators.mir b/llvm/test/MachineVerifier/verifier-pseudo-terminators.mir index 6e9ec9c0887f..831ca83baa28 100644 --- a/llvm/test/MachineVerifier/verifier-pseudo-terminators.mir +++ b/llvm/test/MachineVerifier/verifier-pseudo-terminators.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=amdgcn -run-pass=verify -o - %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -run-pass=verify -o - %s 2>&1 | FileCheck %s # REQUIRES: amdgpu-registered-target # Make sure that mismatched successors are caught when a _term diff --git a/llvm/test/MachineVerifier/verify-regbankselected.mir b/llvm/test/MachineVerifier/verify-regbankselected.mir index ed022ed5eaf9..027fc6664573 100644 --- a/llvm/test/MachineVerifier/verify-regbankselected.mir +++ b/llvm/test/MachineVerifier/verify-regbankselected.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- | diff --git a/llvm/test/MachineVerifier/verify-regops.mir b/llvm/test/MachineVerifier/verify-regops.mir index ec17c3d0558b..9219586ffc03 100644 --- a/llvm/test/MachineVerifier/verify-regops.mir +++ b/llvm/test/MachineVerifier/verify-regops.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -march=x86 -o - %s -run-pass=none -verify-machineinstrs \ +# RUN: not llc -march=x86 -o - %s -run-pass=none -verify-machineinstrs \ # RUN: 2>&1 | FileCheck %s # REQUIRES: x86-registered-target # diff --git a/llvm/test/MachineVerifier/verify-selected.mir b/llvm/test/MachineVerifier/verify-selected.mir index b14f977caf14..a38f67ca6e67 100644 --- a/llvm/test/MachineVerifier/verify-selected.mir +++ b/llvm/test/MachineVerifier/verify-selected.mir @@ -1,4 +1,4 @@ -# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # REQUIRES: aarch64-registered-target --- | diff --git a/llvm/test/Object/coff-invalid.test b/llvm/test/Object/coff-invalid.test index da5d687c6e20..3ab3f41b15fe 100644 --- a/llvm/test/Object/coff-invalid.test +++ b/llvm/test/Object/coff-invalid.test @@ -7,7 +7,7 @@ SECTIONS-NEXT: Name: .text (2E 74 65 78 74 00 00 00) SECTIONS-NEXT: VirtualSize: 0x0 SECTIONS-NEXT: VirtualAddress: 0x1000000 -RUN: not --crash llvm-readobj -r %p/Inputs/invalid-bad-section-address.coff 2>&1 | \ +RUN: not llvm-readobj -r %p/Inputs/invalid-bad-section-address.coff 2>&1 | \ RUN: FileCheck %s CHECK: Sections with relocations should have an address of 0 diff --git a/llvm/test/Object/elf-invalid-phdr.test b/llvm/test/Object/elf-invalid-phdr.test index 68a26788e118..b779171dfbb3 100644 --- a/llvm/test/Object/elf-invalid-phdr.test +++ b/llvm/test/Object/elf-invalid-phdr.test @@ -20,7 +20,7 @@ # - Section: .text # # Then editing the e_phoff in with a hexeditor to set it to 0xffffff -RUN: not --crash llvm-objdump -private-headers %p/Inputs/invalid-phdr.elf 2>&1 \ +RUN: not llvm-objdump -private-headers %p/Inputs/invalid-phdr.elf 2>&1 \ RUN: | FileCheck %s -CHECK: LLVM ERROR: program headers are longer than binary of size 4162: e_phoff = 0xffffff, e_phnum = 1, e_phentsize = 56 +CHECK: LLVM ERROR: program headers are longer than binary of size 4162: e_phoff = 0xffffff, e_phnum = 1, e_phentsize = 56 \ No newline at end of file diff --git a/llvm/test/Object/invalid.test b/llvm/test/Object/invalid.test index 442d38d46d06..4d19b66238cc 100644 --- a/llvm/test/Object/invalid.test +++ b/llvm/test/Object/invalid.test @@ -47,7 +47,7 @@ Sections: ## when instead of expected SHT_RELA section it locates a section of a different type. # RUN: yaml2obj %s --docnum=3 -o %t3 -# RUN: not --crash llvm-dwarfdump -debug-line %t3 2>&1 | FileCheck --check-prefix=RELA %s +# RUN: not llvm-dwarfdump -debug-line %t3 2>&1 | FileCheck --check-prefix=RELA %s # RELA: LLVM ERROR: Section is not SHT_RELA diff --git a/llvm/test/Object/wasm-invalid-file.yaml b/llvm/test/Object/wasm-invalid-file.yaml index 9870b47ee85c..5ea192d66177 100644 --- a/llvm/test/Object/wasm-invalid-file.yaml +++ b/llvm/test/Object/wasm-invalid-file.yaml @@ -1,7 +1,7 @@ # RUN: yaml2obj %s -o %t.wasm # RUN: echo -e -n "\x01" >> %t.wasm # Append a new section but truncate the encoding of the section size -# RUN: not --crash llvm-objdump -h %t.wasm 2>&1 | FileCheck %s -check-prefix=CHECK-LEB-DECODE +# RUN: not llvm-objdump -h %t.wasm 2>&1 | FileCheck %s -check-prefix=CHECK-LEB-DECODE !WASM FileHeader: diff --git a/llvm/test/Object/wasm-string-outside-section.test b/llvm/test/Object/wasm-string-outside-section.test index 3fa6217bae8e..5f618228dc96 100644 --- a/llvm/test/Object/wasm-string-outside-section.test +++ b/llvm/test/Object/wasm-string-outside-section.test @@ -1,3 +1,3 @@ -RUN: not --crash llvm-objdump -s %p/Inputs/WASM/string-outside-section.wasm 2>&1 | FileCheck %s +RUN: not llvm-objdump -s %p/Inputs/WASM/string-outside-section.wasm 2>&1 | FileCheck %s CHECK: LLVM ERROR: EOF while reading string diff --git a/llvm/test/Other/close-stderr.ll b/llvm/test/Other/close-stderr.ll new file mode 100644 index 000000000000..b310bc2c0424 --- /dev/null +++ b/llvm/test/Other/close-stderr.ll @@ -0,0 +1,13 @@ +; RUN: sh -c 'opt --reject-this-option 2>&-; echo $?; opt -o /dev/null /dev/null 2>&-; echo $?;' \ +; RUN: | FileCheck %s + +; CHECK: {{^1$}} +; On valgrind, we got 127 here. +; XFAIL: valgrind + +; CHECK: {{^0$}} +; XFAIL: vg_leak +; REQUIRES: shell + +; Test that the error handling when writing to stderr fails exits the +; program cleanly rather than aborting. diff --git a/llvm/test/Other/optimization-remarks-inline.ll b/llvm/test/Other/optimization-remarks-inline.ll index bc2200545bb0..bcd90bc28d32 100644 --- a/llvm/test/Other/optimization-remarks-inline.ll +++ b/llvm/test/Other/optimization-remarks-inline.ll @@ -10,7 +10,7 @@ ; RUN: opt < %s -inline -pass-remarks='inl' -pass-remarks='vector' -S 2>&1 | FileCheck --check-prefix=REMARKS %s ; RUN: opt < %s -inline -S 2>&1 | FileCheck --check-prefix=REMARKS %s -; RUN: not --crash opt < %s -pass-remarks='(' 2>&1 | FileCheck --check-prefix=BAD-REGEXP %s +; RUN: not opt < %s -pass-remarks='(' 2>&1 | FileCheck --check-prefix=BAD-REGEXP %s define i32 @foo(i32 %x, i32 %y) #0 { entry: diff --git a/llvm/test/TableGen/HwModeSelect.td b/llvm/test/TableGen/HwModeSelect.td index 0c63e140f390..6480268f3b3d 100644 --- a/llvm/test/TableGen/HwModeSelect.td +++ b/llvm/test/TableGen/HwModeSelect.td @@ -1,4 +1,4 @@ -// RUN: not --crash llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s +// RUN: not llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s // The HwModeSelect class is intended to serve as a base class for other // classes that are then used to select a value based on the HW mode. diff --git a/llvm/test/Transforms/BlockExtractor/invalid-block.ll b/llvm/test/Transforms/BlockExtractor/invalid-block.ll index 4b284ddbcdba..f444764e991d 100644 --- a/llvm/test/Transforms/BlockExtractor/invalid-block.ll +++ b/llvm/test/Transforms/BlockExtractor/invalid-block.ll @@ -1,5 +1,5 @@ ; RUN: echo 'bar invalidbb' > %t -; RUN: not --crash opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s +; RUN: not opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s ; CHECK: Invalid block define void @bar() { diff --git a/llvm/test/Transforms/BlockExtractor/invalid-function.ll b/llvm/test/Transforms/BlockExtractor/invalid-function.ll index 9af46ef2dcf9..4044815893e5 100644 --- a/llvm/test/Transforms/BlockExtractor/invalid-function.ll +++ b/llvm/test/Transforms/BlockExtractor/invalid-function.ll @@ -1,5 +1,5 @@ ; RUN: echo 'foo bb' > %t -; RUN: not --crash opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s +; RUN: not opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s ; CHECK: Invalid function define void @bar() { diff --git a/llvm/test/Transforms/BlockExtractor/invalid-line.ll b/llvm/test/Transforms/BlockExtractor/invalid-line.ll index f0a4231660d7..7e409d35916f 100644 --- a/llvm/test/Transforms/BlockExtractor/invalid-line.ll +++ b/llvm/test/Transforms/BlockExtractor/invalid-line.ll @@ -1,5 +1,5 @@ ; RUN: echo 'foo' > %t -; RUN: not --crash opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s +; RUN: not opt -S -extract-blocks -extract-blocks-file=%t %s 2>&1 | FileCheck %s ; CHECK: Invalid line define void @bar() { diff --git a/llvm/test/Transforms/FunctionImport/not-prevailing.ll b/llvm/test/Transforms/FunctionImport/not-prevailing.ll index 043b3a89adc2..0e0dd53950ae 100644 --- a/llvm/test/Transforms/FunctionImport/not-prevailing.ll +++ b/llvm/test/Transforms/FunctionImport/not-prevailing.ll @@ -1,6 +1,6 @@ ; RUN: opt -module-summary %s -o %t1.bc ; RUN: opt -module-summary -o %t2.bc %S/Inputs/not-prevailing.ll -; RUN: not --crash llvm-lto2 run -o %t3.bc %t1.bc %t2.bc -r %t1.bc,bar,px \ +; RUN: not llvm-lto2 run -o %t3.bc %t1.bc %t2.bc -r %t1.bc,bar,px \ ; RUN: -r %t1.bc,foo,x -r %t2.bc,foo,x -save-temps 2>&1 | FileCheck %s ; CHECK: Interposable and available_externally/linkonce_odr/weak_odr symbol diff --git a/llvm/test/Transforms/GCOVProfiling/version.ll b/llvm/test/Transforms/GCOVProfiling/version.ll index c72b64260ffa..239c62f4a6bb 100644 --- a/llvm/test/Transforms/GCOVProfiling/version.ll +++ b/llvm/test/Transforms/GCOVProfiling/version.ll @@ -4,7 +4,7 @@ ; RUN: opt -insert-gcov-profiling -disable-output < %t/2 ; RUN: head -c8 %t/version.gcno | grep '^oncg.204' ; RUN: rm %t/version.gcno -; RUN: not --crash opt -insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t/2 +; RUN: not opt -insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t/2 ; RUN: opt -insert-gcov-profiling -default-gcov-version=407* -disable-output < %t/2 ; RUN: head -c8 %t/version.gcno | grep '^oncg.704' ; RUN: rm %t/version.gcno @@ -12,7 +12,7 @@ ; RUN: opt -passes=insert-gcov-profiling -disable-output < %t/2 ; RUN: head -c8 %t/version.gcno | grep '^oncg.204' ; RUN: rm %t/version.gcno -; RUN: not --crash opt -passes=insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t/2 +; RUN: not opt -passes=insert-gcov-profiling -default-gcov-version=asdfasdf -disable-output < %t/2 ; RUN: opt -passes=insert-gcov-profiling -default-gcov-version=407* -disable-output < %t/2 ; RUN: head -c8 %t/version.gcno | grep '^oncg.704' ; RUN: rm %t/version.gcno diff --git a/llvm/test/Transforms/InstCombine/limit-max-iterations.ll b/llvm/test/Transforms/InstCombine/limit-max-iterations.ll index af027998edac..a2ef4ebcbb50 100644 --- a/llvm/test/Transforms/InstCombine/limit-max-iterations.ll +++ b/llvm/test/Transforms/InstCombine/limit-max-iterations.ll @@ -2,7 +2,7 @@ ; RUN: opt < %s -instcombine --instcombine-max-iterations=0 -S | FileCheck %s --check-prefix=ZERO ; RUN: opt < %s -instcombine --instcombine-max-iterations=1 -S | FileCheck %s --check-prefix=ONE ; RUN: opt < %s -instcombine -S | FileCheck %s --check-prefix=FIXPOINT -; RUN: not --crash opt < %s -instcombine -S --instcombine-infinite-loop-threshold=3 2>&1 | FileCheck %s --check-prefix=LOOP +; RUN: not opt < %s -instcombine -S --instcombine-infinite-loop-threshold=3 2>&1 | FileCheck %s --check-prefix=LOOP ; Based on xor-of-icmps-with-extra-uses.ll. This requires multiple iterations of ; InstCombine to reach a fixpoint. diff --git a/llvm/test/tools/llvm-lto2/X86/pipeline.ll b/llvm/test/tools/llvm-lto2/X86/pipeline.ll index abc2f20a0725..f9759b590857 100644 --- a/llvm/test/tools/llvm-lto2/X86/pipeline.ll +++ b/llvm/test/tools/llvm-lto2/X86/pipeline.ll @@ -28,13 +28,13 @@ define void @patatino() { ; CUSTOM-NEXT: } ; Check that invalid pipelines are caught as errors. -; RUN: not --crash llvm-lto2 run %t1.bc -o %t.o \ +; RUN: not llvm-lto2 run %t1.bc -o %t.o \ ; RUN: -r %t1.bc,patatino,px -opt-pipeline foogoo 2>&1 | \ ; RUN: FileCheck %s --check-prefix=ERR ; ERR: LLVM ERROR: unable to parse pass pipeline description 'foogoo': unknown pass name 'foogoo' -; RUN: not --crash llvm-lto2 run %t1.bc -o %t.o \ +; RUN: not llvm-lto2 run %t1.bc -o %t.o \ ; RUN: -r %t1.bc,patatino,px -aa-pipeline patatino \ ; RUN: -opt-pipeline loweratomic 2>&1 | \ ; RUN: FileCheck %s --check-prefix=AAERR diff --git a/llvm/test/tools/llvm-readobj/COFF/arm64-many-epilogs.s b/llvm/test/tools/llvm-readobj/COFF/arm64-many-epilogs.s index 50b5fab93513..a1b53980936d 100644 --- a/llvm/test/tools/llvm-readobj/COFF/arm64-many-epilogs.s +++ b/llvm/test/tools/llvm-readobj/COFF/arm64-many-epilogs.s @@ -1,6 +1,6 @@ // REQUIRES: aarch64-registered-target // RUN: llvm-mc -filetype=obj -triple aarch64-windows %s -o - \ -// RUN: | not --crash llvm-readobj --unwind - 2>&1 | FileCheck %s +// RUN: | not llvm-readobj --unwind - | FileCheck %s // Older versions of LLVM had a bug where we would accidentally // truncate the number of epilogue scopes to a uint8_t; make diff --git a/llvm/test/tools/llvm-readobj/COFF/arm64-win-error2.s b/llvm/test/tools/llvm-readobj/COFF/arm64-win-error2.s index 5256de05cb24..74a61dd02019 100644 --- a/llvm/test/tools/llvm-readobj/COFF/arm64-win-error2.s +++ b/llvm/test/tools/llvm-readobj/COFF/arm64-win-error2.s @@ -6,7 +6,7 @@ // REQUIRES: aarch64-registered-target // RUN: llvm-mc -filetype=obj -triple aarch64-windows %s -o - \ -// RUN: | not --crash llvm-readobj --unwind - 2>&1 | FileCheck %s +// RUN: | not llvm-readobj --unwind - 2>&1 | FileCheck %s // CHECK: LLVM ERROR: Malformed unwind data -- GitLab From 04b4866ba4596e5605574bf7d4dd7847e5acc4b2 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Tue, 11 Feb 2020 20:45:05 -0800 Subject: [PATCH 112/142] [CMake] Delete llvm_add_go_executable and a reference to TARGET llvm-go llvm-go was deleted by 102814b4d36ad004a2e37cd2a1e84bd2c3593d29. --- llvm/cmake/modules/AddLLVM.cmake | 30 ------------------------------ llvm/test/CMakeLists.txt | 4 ---- 2 files changed, 34 deletions(-) diff --git a/llvm/cmake/modules/AddLLVM.cmake b/llvm/cmake/modules/AddLLVM.cmake index 740523d6d70e..2693f041811d 100644 --- a/llvm/cmake/modules/AddLLVM.cmake +++ b/llvm/cmake/modules/AddLLVM.cmake @@ -1327,36 +1327,6 @@ function(add_benchmark benchmark_name) target_link_libraries(${benchmark_name} PRIVATE benchmark) endfunction() -function(llvm_add_go_executable binary pkgpath) - cmake_parse_arguments(ARG "ALL" "" "DEPENDS;GOFLAGS" ${ARGN}) - - if(LLVM_BINDINGS MATCHES "go") - # FIXME: This should depend only on the libraries Go needs. - get_property(llvmlibs GLOBAL PROPERTY LLVM_LIBS) - set(binpath ${CMAKE_BINARY_DIR}/bin/${binary}${CMAKE_EXECUTABLE_SUFFIX}) - set(cc "${CMAKE_C_COMPILER} ${CMAKE_C_COMPILER_ARG1}") - set(cxx "${CMAKE_CXX_COMPILER} ${CMAKE_CXX_COMPILER_ARG1}") - set(cppflags "") - get_property(include_dirs DIRECTORY PROPERTY INCLUDE_DIRECTORIES) - foreach(d ${include_dirs}) - set(cppflags "${cppflags} -I${d}") - endforeach(d) - set(ldflags "${CMAKE_EXE_LINKER_FLAGS}") - add_custom_command(OUTPUT ${binpath} - COMMAND ${CMAKE_BINARY_DIR}/bin/llvm-go "go=${GO_EXECUTABLE}" "cc=${cc}" "cxx=${cxx}" "cppflags=${cppflags}" "ldflags=${ldflags}" "packages=${LLVM_GO_PACKAGES}" - ${ARG_GOFLAGS} build -o ${binpath} ${pkgpath} - DEPENDS llvm-config ${CMAKE_BINARY_DIR}/bin/llvm-go${CMAKE_EXECUTABLE_SUFFIX} - ${llvmlibs} ${ARG_DEPENDS} - COMMENT "Building Go executable ${binary}" - VERBATIM) - if (ARG_ALL) - add_custom_target(${binary} ALL DEPENDS ${binpath}) - else() - add_custom_target(${binary} DEPENDS ${binpath}) - endif() - endif() -endfunction() - # This function canonicalize the CMake variables passed by names # from CMake boolean to 0/1 suitable for passing into Python or C++, # in place. diff --git a/llvm/test/CMakeLists.txt b/llvm/test/CMakeLists.txt index 2f19963fe1b6..fb19741de44b 100644 --- a/llvm/test/CMakeLists.txt +++ b/llvm/test/CMakeLists.txt @@ -122,10 +122,6 @@ if(TARGET LLVMgold) set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} LLVMgold) endif() -if(TARGET llvm-go) - set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} llvm-go) -endif() - if(TARGET LTO) set(LLVM_TEST_DEPENDS ${LLVM_TEST_DEPENDS} LTO) endif() -- GitLab From 346cb7b50f7f892b33b46313742eef86bfde7943 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Wed, 12 Feb 2020 07:13:48 +0100 Subject: [PATCH 113/142] [lldb] Remove skipIfFreeBSD from TestCompletion This was skipped because of an pexpect issue (http://llvm.org/pr22784), but this test is no longer using pexpect and is running fine on FreeBSD. --- .../completion/TestCompletion.py | 49 ------------------- 1 file changed, 49 deletions(-) diff --git a/lldb/test/API/functionalities/completion/TestCompletion.py b/lldb/test/API/functionalities/completion/TestCompletion.py index 538c626d60fd..9e15b5d3f557 100644 --- a/lldb/test/API/functionalities/completion/TestCompletion.py +++ b/lldb/test/API/functionalities/completion/TestCompletion.py @@ -27,17 +27,14 @@ class CommandLineCompletionTestCase(TestBase): except: pass - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_at(self): """Test that 'at' completes to 'attach '.""" self.complete_from_to('at', 'attach ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_de(self): """Test that 'de' completes to 'detach '.""" self.complete_from_to('de', 'detach ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_frame_variable(self): self.build() self.main_source = "main.cpp" @@ -76,95 +73,79 @@ class CommandLineCompletionTestCase(TestBase): self.complete_from_to('frame variable ptr_container->Mem', 'frame variable ptr_container->MemberVar') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_process_attach_dash_dash_con(self): """Test that 'process attach --con' completes to 'process attach --continue '.""" self.complete_from_to( 'process attach --con', 'process attach --continue ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_process_launch_arch(self): self.complete_from_to('process launch --arch ', ['mips', 'arm64']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_ambiguous_long_opt(self): self.completions_match('breakpoint modify --th', ['--thread-id', '--thread-index', '--thread-name']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_plugin_load(self): self.complete_from_to('plugin load ', []) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_log_enable(self): self.complete_from_to('log enable ll', ['lldb']) self.complete_from_to('log enable dw', ['dwarf']) self.complete_from_to('log enable lldb al', ['all']) self.complete_from_to('log enable lldb sym', ['symbol']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_log_enable(self): self.complete_from_to('log disable ll', ['lldb']) self.complete_from_to('log disable dw', ['dwarf']) self.complete_from_to('log disable lldb al', ['all']) self.complete_from_to('log disable lldb sym', ['symbol']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_log_list(self): self.complete_from_to('log list ll', ['lldb']) self.complete_from_to('log list dw', ['dwarf']) self.complete_from_to('log list ll', ['lldb']) self.complete_from_to('log list lldb dwa', ['dwarf']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_quoted_command(self): self.complete_from_to('"set', ['"settings" ']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_quoted_arg_with_quoted_command(self): self.complete_from_to('"settings" "repl', ['"replace" ']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_quoted_arg_without_quoted_command(self): self.complete_from_to('settings "repl', ['"replace" ']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_single_quote_command(self): self.complete_from_to("'set", ["'settings' "]) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_terminated_quote_command(self): # This should not crash, but we don't get any # reasonable completions from this. self.complete_from_to("'settings'", []) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_process_launch_arch_arm(self): self.complete_from_to('process launch --arch arm', ['arm64']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_target_symbols_add_shlib(self): # Doesn't seem to work, but at least it shouldn't crash. self.complete_from_to('target symbols add --shlib ', []) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_log_file(self): # Complete in our source directory which contains a 'main.cpp' file. src_dir = os.path.dirname(os.path.realpath(__file__)) + '/' self.complete_from_to('log enable lldb expr -f ' + src_dir, ['main.cpp']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_log_dir(self): # Complete our source directory. src_dir = os.path.dirname(os.path.realpath(__file__)) @@ -172,140 +153,118 @@ class CommandLineCompletionTestCase(TestBase): [src_dir + os.sep], turn_off_re_match=True) # - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_infinite_loop_while_completing(self): """Test that 'process print hello\' completes to itself and does not infinite loop.""" self.complete_from_to('process print hello\\', 'process print hello\\', turn_off_re_match=True) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_watchpoint_co(self): """Test that 'watchpoint co' completes to 'watchpoint command '.""" self.complete_from_to('watchpoint co', 'watchpoint command ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_watchpoint_command_space(self): """Test that 'watchpoint command ' completes to ['add', 'delete', 'list'].""" self.complete_from_to( 'watchpoint command ', [ 'add', 'delete', 'list']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_watchpoint_command_a(self): """Test that 'watchpoint command a' completes to 'watchpoint command add '.""" self.complete_from_to( 'watchpoint command a', 'watchpoint command add ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_watchpoint_set_ex(self): """Test that 'watchpoint set ex' completes to 'watchpoint set expression '.""" self.complete_from_to( 'watchpoint set ex', 'watchpoint set expression ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_watchpoint_set_var(self): """Test that 'watchpoint set var' completes to 'watchpoint set variable '.""" self.complete_from_to('watchpoint set var', 'watchpoint set variable ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_help_fi(self): """Test that 'help fi' completes to ['file', 'finish'].""" self.complete_from_to( 'help fi', [ 'file', 'finish']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_help_watchpoint_s(self): """Test that 'help watchpoint s' completes to 'help watchpoint set '.""" self.complete_from_to('help watchpoint s', 'help watchpoint set ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_append_target_er(self): """Test that 'settings append target.er' completes to 'settings append target.error-path'.""" self.complete_from_to( 'settings append target.er', 'settings append target.error-path') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_insert_after_target_en(self): """Test that 'settings insert-after target.env' completes to 'settings insert-after target.env-vars'.""" self.complete_from_to( 'settings insert-after target.env', 'settings insert-after target.env-vars') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_insert_before_target_en(self): """Test that 'settings insert-before target.env' completes to 'settings insert-before target.env-vars'.""" self.complete_from_to( 'settings insert-before target.env', 'settings insert-before target.env-vars') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_replace_target_ru(self): """Test that 'settings replace target.ru' completes to 'settings replace target.run-args'.""" self.complete_from_to( 'settings replace target.ru', 'settings replace target.run-args') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_show_term(self): self.complete_from_to( 'settings show term-', 'settings show term-width') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_list_term(self): self.complete_from_to( 'settings list term-', 'settings list term-width') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_remove_term(self): self.complete_from_to( 'settings remove term-', 'settings remove term-width') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_s(self): """Test that 'settings s' completes to ['set', 'show'].""" self.complete_from_to( 'settings s', [ 'set', 'show']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_set_th(self): """Test that 'settings set thread-f' completes to 'settings set thread-format'.""" self.complete_from_to('settings set thread-f', 'settings set thread-format') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_s_dash(self): """Test that 'settings set --g' completes to 'settings set --global'.""" self.complete_from_to('settings set --g', 'settings set --global') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_clear_th(self): """Test that 'settings clear thread-f' completes to 'settings clear thread-format'.""" self.complete_from_to( 'settings clear thread-f', 'settings clear thread-format') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_set_ta(self): """Test that 'settings set ta' completes to 'settings set target.'.""" self.complete_from_to( 'settings set target.ma', 'settings set target.max-') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_set_target_exec(self): """Test that 'settings set target.exec' completes to 'settings set target.exec-search-paths '.""" self.complete_from_to( 'settings set target.exec', 'settings set target.exec-search-paths') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_set_target_pr(self): """Test that 'settings set target.pr' completes to [ 'target.prefer-dynamic-value', 'target.process.'].""" @@ -313,21 +272,18 @@ class CommandLineCompletionTestCase(TestBase): ['target.prefer-dynamic-value', 'target.process.']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_set_target_process(self): """Test that 'settings set target.process' completes to 'settings set target.process.'.""" self.complete_from_to( 'settings set target.process', 'settings set target.process.') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_set_target_process_dot(self): """Test that 'settings set target.process.t' completes to 'settings set target.process.thread.'.""" self.complete_from_to( 'settings set target.process.t', 'settings set target.process.thread.') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_settings_set_target_process_thread_dot(self): """Test that 'settings set target.process.thread.' completes to [ 'target.process.thread.step-avoid-regexp', 'target.process.thread.trace-thread'].""" @@ -335,7 +291,6 @@ class CommandLineCompletionTestCase(TestBase): ['target.process.thread.step-avoid-regexp', 'target.process.thread.trace-thread']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_target_space(self): """Test that 'target ' completes to ['create', 'delete', 'list', 'modules', 'select', 'stop-hook', 'variable'].""" @@ -348,7 +303,6 @@ class CommandLineCompletionTestCase(TestBase): 'stop-hook', 'variable']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_target_modules_dump_line_table(self): """Tests source file completion by completing the line-table argument.""" self.build() @@ -356,7 +310,6 @@ class CommandLineCompletionTestCase(TestBase): self.complete_from_to('target modules dump line-table main.cp', ['main.cpp']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_target_modules_load_aout(self): """Tests modules completion by completing the target modules load argument.""" self.build() @@ -364,12 +317,10 @@ class CommandLineCompletionTestCase(TestBase): self.complete_from_to('target modules load a.ou', ['a.out']) - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_target_create_dash_co(self): """Test that 'target create --co' completes to 'target variable --core '.""" self.complete_from_to('target create --co', 'target create --core ') - @skipIfFreeBSD # timing out on the FreeBSD buildbot def test_target_va(self): """Test that 'target va' completes to 'target variable '.""" self.complete_from_to('target va', 'target variable ') -- GitLab From 0daf9b8e41327b1511b2bbc272184ff4fdb8de79 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 11 Feb 2020 20:24:51 -0800 Subject: [PATCH 114/142] [X86][LegalizeTypes] Add SoftPromoteHalf support STRICT_FP_EXTEND and STRICT_FP_ROUND This adds a strict version of FP16_TO_FP and FP_TO_FP16 and uses them to implement soft promotion for the half type. This is enough to provide basic support for __fp16 with strictfp. Add the necessary X86 support to use VCVTPS2PH/VCVTPH2PS when F16C is enabled. --- llvm/include/llvm/CodeGen/ISDOpcodes.h | 1 + llvm/include/llvm/CodeGen/SelectionDAGNodes.h | 2 + llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 40 ++++++++ .../SelectionDAG/LegalizeFloatTypes.cpp | 23 ++++- .../SelectionDAG/SelectionDAGDumper.cpp | 2 + llvm/lib/Target/X86/X86ISelLowering.cpp | 91 ++++++++++++++----- llvm/lib/Target/X86/X86ISelLowering.h | 3 + llvm/lib/Target/X86/X86InstrAVX512.td | 23 ++--- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 32 ++++--- llvm/lib/Target/X86/X86InstrSSE.td | 16 ++-- 10 files changed, 180 insertions(+), 53 deletions(-) diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index b5a434bc3817..afeaf5e2c26f 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -633,6 +633,7 @@ namespace ISD { /// form a semi-softened interface for dealing with f16 (as an i16), which /// is often a storage-only type but has native conversions. FP16_TO_FP, FP_TO_FP16, + STRICT_FP16_TO_FP, STRICT_FP_TO_FP16, /// Perform various unary floating-point operations inspired by libm. For /// FPOWI, the result is undefined if if the integer operand doesn't fit diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 28a4653b34fe..4ef7b177e8c1 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -701,6 +701,8 @@ public: switch (NodeType) { default: return false; + case ISD::STRICT_FP16_TO_FP: + case ISD::STRICT_FP_TO_FP16: #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ case ISD::STRICT_##DAGN: #include "llvm/IR/ConstrainedOps.def" diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index d03f765a5779..6fd048a911b4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1009,6 +1009,7 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { Action = TLI.getOperationAction(Node->getOpcode(), Node->getOperand(0).getValueType()); break; + case ISD::STRICT_FP_TO_FP16: case ISD::STRICT_SINT_TO_FP: case ISD::STRICT_UINT_TO_FP: case ISD::STRICT_LRINT: @@ -3272,6 +3273,21 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res)); } break; + case ISD::STRICT_FP16_TO_FP: + if (Node->getValueType(0) != MVT::f32) { + // We can extend to types bigger than f32 in two steps without changing + // the result. Since "f16 -> f32" is much more commonly available, give + // CodeGen the option of emitting that before resorting to a libcall. + SDValue Res = + DAG.getNode(ISD::STRICT_FP16_TO_FP, dl, {MVT::f32, MVT::Other}, + {Node->getOperand(0), Node->getOperand(1)}); + Res = DAG.getNode(ISD::STRICT_FP_EXTEND, dl, + {Node->getValueType(0), MVT::Other}, + {Res.getValue(1), Res}); + Results.push_back(Res); + Results.push_back(Res.getValue(1)); + } + break; case ISD::FP_TO_FP16: LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n"); if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) { @@ -4234,6 +4250,17 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) { Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); } break; + case ISD::STRICT_FP16_TO_FP: { + if (Node->getValueType(0) == MVT::f32) { + TargetLowering::MakeLibCallOptions CallOptions; + std::pair Tmp = TLI.makeLibCall( + DAG, RTLIB::FPEXT_F16_F32, MVT::f32, Node->getOperand(1), CallOptions, + SDLoc(Node), Node->getOperand(0)); + Results.push_back(Tmp.first); + Results.push_back(Tmp.second); + } + break; + } case ISD::FP_TO_FP16: { RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16); @@ -4241,6 +4268,19 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) { Results.push_back(ExpandLibCall(LC, Node, false)); break; } + case ISD::STRICT_FP_TO_FP16: { + RTLIB::Libcall LC = + RTLIB::getFPROUND(Node->getOperand(1).getValueType(), MVT::f16); + assert(LC != RTLIB::UNKNOWN_LIBCALL && + "Unable to expand strict_fp_to_fp16"); + TargetLowering::MakeLibCallOptions CallOptions; + std::pair Tmp = + TLI.makeLibCall(DAG, LC, Node->getValueType(0), Node->getOperand(1), + CallOptions, SDLoc(Node), Node->getOperand(0)); + Results.push_back(Tmp.first); + Results.push_back(Tmp.second); + break; + } case ISD::FSUB: case ISD::STRICT_FSUB: ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64, diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 12fef02267ec..428dc83e2fd3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -2440,6 +2440,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) { case ISD::EXTRACT_VECTOR_ELT: R = SoftPromoteHalfRes_EXTRACT_VECTOR_ELT(N); break; case ISD::FCOPYSIGN: R = SoftPromoteHalfRes_FCOPYSIGN(N); break; + case ISD::STRICT_FP_ROUND: case ISD::FP_ROUND: R = SoftPromoteHalfRes_FP_ROUND(N); break; // Unary FP Operations @@ -2592,6 +2593,14 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FPOWI(SDNode *N) { } SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FP_ROUND(SDNode *N) { + if (N->isStrictFPOpcode()) { + SDValue Res = + DAG.getNode(ISD::STRICT_FP_TO_FP16, SDLoc(N), {MVT::i16, MVT::Other}, + {N->getOperand(0), N->getOperand(1)}); + ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); + return Res; + } + return DAG.getNode(ISD::FP_TO_FP16, SDLoc(N), MVT::i16, N->getOperand(0)); } @@ -2701,6 +2710,7 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) { case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break; case ISD::FP_TO_SINT: case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break; + case ISD::STRICT_FP_EXTEND: case ISD::FP_EXTEND: Res = SoftPromoteHalfOp_FP_EXTEND(N); break; case ISD::SELECT_CC: Res = SoftPromoteHalfOp_SELECT_CC(N, OpNo); break; case ISD::SETCC: Res = SoftPromoteHalfOp_SETCC(N); break; @@ -2741,7 +2751,18 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FCOPYSIGN(SDNode *N, } SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) { - SDValue Op = GetSoftPromotedHalf(N->getOperand(0)); + bool IsStrict = N->isStrictFPOpcode(); + SDValue Op = GetSoftPromotedHalf(N->getOperand(IsStrict ? 1 : 0)); + + if (IsStrict) { + SDValue Res = + DAG.getNode(ISD::STRICT_FP16_TO_FP, SDLoc(N), + {N->getValueType(0), MVT::Other}, {N->getOperand(0), Op}); + ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); + ReplaceValueWith(SDValue(N, 0), Res); + return SDValue(); + } + return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0), Op); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index 8736ee23b8ea..f57852ced660 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -342,7 +342,9 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::BITCAST: return "bitcast"; case ISD::ADDRSPACECAST: return "addrspacecast"; case ISD::FP16_TO_FP: return "fp16_to_fp"; + case ISD::STRICT_FP16_TO_FP: return "strict_fp16_to_fp"; case ISD::FP_TO_FP16: return "fp_to_fp16"; + case ISD::STRICT_FP_TO_FP16: return "strict_fp_to_fp16"; case ISD::LROUND: return "lround"; case ISD::STRICT_LROUND: return "strict_lround"; case ISD::LLROUND: return "llround"; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4321bb79d857..8cd177aa302f 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -374,20 +374,30 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, // If we don't have F16C support, then lower half float conversions // into library calls. if (!Subtarget.useSoftFloat() && Subtarget.hasF16C()) { - setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom); - setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); + setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom); + setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f32, Custom); + setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); + setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f32, Custom); } else { - setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); - setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); + setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); + setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f32, Expand); + setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); + setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f32, Expand); } // There's never any support for operations beyond MVT::f32. setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand); setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand); + setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f64, Expand); + setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f80, Expand); + setOperationAction(ISD::STRICT_FP16_TO_FP, MVT::f128, Expand); setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand); setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand); + setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f64, Expand); + setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f80, Expand); + setOperationAction(ISD::STRICT_FP_TO_FP16, MVT::f128, Expand); setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); @@ -20553,29 +20563,64 @@ SDValue X86TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const { } static SDValue LowerFP16_TO_FP(SDValue Op, SelectionDAG &DAG) { - assert(Op.getOperand(0).getValueType() == MVT::i16 && - Op.getValueType() == MVT::f32 && "Unexpected VT!"); + bool IsStrict = Op->isStrictFPOpcode(); + SDValue Src = Op.getOperand(IsStrict ? 1 : 0); + assert(Src.getValueType() == MVT::i16 && Op.getValueType() == MVT::f32 && + "Unexpected VT!"); SDLoc dl(Op); SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, - DAG.getConstant(0, dl, MVT::v8i16), - Op.getOperand(0), DAG.getIntPtrConstant(0, dl)); - Res = DAG.getNode(X86ISD::CVTPH2PS, dl, MVT::v4f32, Res); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, - DAG.getIntPtrConstant(0, dl)); + DAG.getConstant(0, dl, MVT::v8i16), Src, + DAG.getIntPtrConstant(0, dl)); + + SDValue Chain; + if (IsStrict) { + Res = DAG.getNode(X86ISD::STRICT_CVTPH2PS, dl, {MVT::v4f32, MVT::Other}, + {Op.getOperand(0), Res}); + Chain = Res.getValue(1); + } else { + Res = DAG.getNode(X86ISD::CVTPH2PS, dl, MVT::v4f32, Res); + } + + Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, + DAG.getIntPtrConstant(0, dl)); + + if (IsStrict) + return DAG.getMergeValues({Res, Chain}, dl); + + return Res; } static SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) { - assert(Op.getOperand(0).getValueType() == MVT::f32 && - Op.getValueType() == MVT::i16 && "Unexpected VT!"); + bool IsStrict = Op->isStrictFPOpcode(); + SDValue Src = Op.getOperand(IsStrict ? 1 : 0); + assert(Src.getValueType() == MVT::f32 && Op.getValueType() == MVT::i16 && + "Unexpected VT!"); SDLoc dl(Op); - SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, - Op.getOperand(0)); - Res = DAG.getNode(X86ISD::CVTPS2PH, dl, MVT::v8i16, Res, - DAG.getTargetConstant(4, dl, MVT::i32)); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Res, - DAG.getIntPtrConstant(0, dl)); + SDValue Res, Chain; + if (IsStrict) { + Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v4f32, + DAG.getConstantFP(0, dl, MVT::v4f32), Src, + DAG.getIntPtrConstant(0, dl)); + Res = DAG.getNode( + X86ISD::STRICT_CVTPS2PH, dl, {MVT::v8i16, MVT::Other}, + {Op.getOperand(0), Res, DAG.getTargetConstant(4, dl, MVT::i32)}); + Chain = Res.getValue(1); + } else { + // FIXME: Should we use zeros for upper elements for non-strict? + Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, Src); + Res = DAG.getNode(X86ISD::CVTPS2PH, dl, MVT::v8i16, Res, + DAG.getTargetConstant(4, dl, MVT::i32)); + } + + Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Res, + DAG.getIntPtrConstant(0, dl)); + + if (IsStrict) + return DAG.getMergeValues({Res, Chain}, dl); + + return Res; } /// Depending on uarch and/or optimizing for size, we might prefer to use a @@ -28821,8 +28866,10 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::STRICT_FP_EXTEND: return LowerFP_EXTEND(Op, DAG); case ISD::FP_ROUND: case ISD::STRICT_FP_ROUND: return LowerFP_ROUND(Op, DAG); - case ISD::FP16_TO_FP: return LowerFP16_TO_FP(Op, DAG); - case ISD::FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); + case ISD::FP16_TO_FP: + case ISD::STRICT_FP16_TO_FP: return LowerFP16_TO_FP(Op, DAG); + case ISD::FP_TO_FP16: + case ISD::STRICT_FP_TO_FP16: return LowerFP_TO_FP16(Op, DAG); case ISD::LOAD: return LowerLoad(Op, Subtarget, DAG); case ISD::STORE: return LowerStore(Op, Subtarget, DAG); case ISD::FADD: @@ -30162,8 +30209,10 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(SCALAR_UINT_TO_FP) NODE_NAME_CASE(SCALAR_UINT_TO_FP_RND) NODE_NAME_CASE(CVTPS2PH) + NODE_NAME_CASE(STRICT_CVTPS2PH) NODE_NAME_CASE(MCVTPS2PH) NODE_NAME_CASE(CVTPH2PS) + NODE_NAME_CASE(STRICT_CVTPH2PS) NODE_NAME_CASE(CVTPH2PS_SAE) NODE_NAME_CASE(CVTP2SI) NODE_NAME_CASE(CVTP2UI) diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index cf88ec8ae413..8c085c7f77f3 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -627,6 +627,9 @@ namespace llvm { // Strict FMA nodes. STRICT_FNMADD, STRICT_FMSUB, STRICT_FNMSUB, + // Conversions between float and half-float. + STRICT_CVTPS2PH, STRICT_CVTPH2PS, + // Compare and swap. LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, LCMPXCHG8_DAG, diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 9ce695730046..f07f5687cf37 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -8568,14 +8568,15 @@ let Uses = [MXCSR], mayRaiseFPException = 1 in multiclass avx512_cvtph2ps { - defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), + defm rr : AVX512_maskable_split<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src), "vcvtph2ps", "$src", "$src", + (X86any_cvtph2ps (_src.VT _src.RC:$src)), (X86cvtph2ps (_src.VT _src.RC:$src))>, T8PD, Sched<[sched]>; - defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), + defm rm : AVX512_maskable_split<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src), "vcvtph2ps", "$src", "$src", - (X86cvtph2ps (_src.VT - (ld_frag addr:$src)))>, + (X86any_cvtph2ps (_src.VT (ld_frag addr:$src))), + (X86cvtph2ps (_src.VT (ld_frag addr:$src)))>, T8PD, Sched<[sched.Folded]>; } @@ -8604,9 +8605,9 @@ let Predicates = [HasVLX] in { EVEX_CD8<32, CD8VH>; // Pattern match vcvtph2ps of a scalar i64 load. - def : Pat<(v4f32 (X86cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))), + def : Pat<(v4f32 (X86any_cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))), (VCVTPH2PSZ128rm addr:$src)>; - def : Pat<(v4f32 (X86cvtph2ps (v8i16 (bitconvert + def : Pat<(v4f32 (X86any_cvtph2ps (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))), (VCVTPH2PSZ128rm addr:$src)>; } @@ -8618,7 +8619,7 @@ let ExeDomain = GenericDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { (ins _src.RC:$src1, i32u8imm:$src2), "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", [(set _dest.RC:$dst, - (X86cvtps2ph (_src.VT _src.RC:$src1), (i32 timm:$src2)))]>, + (X86any_cvtps2ph (_src.VT _src.RC:$src1), (i32 timm:$src2)))]>, Sched<[RR]>; let Constraints = "$src0 = $dst" in def rrk : AVX512AIi8<0x1D, MRMDestReg, (outs _dest.RC:$dst), @@ -8673,16 +8674,16 @@ let Predicates = [HasAVX512] in { } def : Pat<(store (f64 (extractelt - (bc_v2f64 (v8i16 (X86cvtps2ph VR128X:$src1, timm:$src2))), + (bc_v2f64 (v8i16 (X86any_cvtps2ph VR128X:$src1, timm:$src2))), (iPTR 0))), addr:$dst), (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, timm:$src2)>; def : Pat<(store (i64 (extractelt - (bc_v2i64 (v8i16 (X86cvtps2ph VR128X:$src1, timm:$src2))), + (bc_v2i64 (v8i16 (X86any_cvtps2ph VR128X:$src1, timm:$src2))), (iPTR 0))), addr:$dst), (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, timm:$src2)>; - def : Pat<(store (v8i16 (X86cvtps2ph VR256X:$src1, timm:$src2)), addr:$dst), + def : Pat<(store (v8i16 (X86any_cvtps2ph VR256X:$src1, timm:$src2)), addr:$dst), (VCVTPS2PHZ256mr addr:$dst, VR256X:$src1, timm:$src2)>; - def : Pat<(store (v16i16 (X86cvtps2ph VR512:$src1, timm:$src2)), addr:$dst), + def : Pat<(store (v16i16 (X86any_cvtps2ph VR512:$src1, timm:$src2)), addr:$dst), (VCVTPS2PHZmr addr:$dst, VR512:$src1, timm:$src2)>; } diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td index 5c5ddae0d029..3fc63e85fee4 100644 --- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td +++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td @@ -721,19 +721,27 @@ def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>; def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>; def X86mcvttp2ui : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>; +def SDTcvtph2ps : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, + SDTCVecEltisVT<1, i16>]>; +def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", SDTcvtph2ps>; +def X86strict_cvtph2ps : SDNode<"X86ISD::STRICT_CVTPH2PS", SDTcvtph2ps, + [SDNPHasChain]>; +def X86any_cvtph2ps : PatFrags<(ops node:$src), + [(X86strict_cvtph2ps node:$src), + (X86cvtph2ps node:$src)]>; + +def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE", SDTcvtph2ps>; + +def SDTcvtps2ph : SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, + SDTCVecEltisVT<1, f32>, + SDTCisVT<2, i32>]>; +def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", SDTcvtps2ph>; +def X86strict_cvtps2ph : SDNode<"X86ISD::STRICT_CVTPS2PH", SDTcvtps2ph, + [SDNPHasChain]>; +def X86any_cvtps2ph : PatFrags<(ops node:$src1, node:$src2), + [(X86strict_cvtps2ph node:$src1, node:$src2), + (X86cvtps2ph node:$src1, node:$src2)]>; -def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS", - SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, - SDTCVecEltisVT<1, i16>]> >; - -def X86cvtph2psSAE : SDNode<"X86ISD::CVTPH2PS_SAE", - SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>, - SDTCVecEltisVT<1, i16>]> >; - -def X86cvtps2ph : SDNode<"X86ISD::CVTPS2PH", - SDTypeProfile<1, 2, [SDTCVecEltisVT<0, i16>, - SDTCVecEltisVT<1, f32>, - SDTCisVT<2, i32>]> >; def X86mcvtps2ph : SDNode<"X86ISD::MCVTPS2PH", SDTypeProfile<1, 4, [SDTCVecEltisVT<0, i16>, SDTCVecEltisVT<1, f32>, diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index b519e4a42e9d..54cb78d72ddc 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -7337,12 +7337,12 @@ multiclass f16c_ph2ps { def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src), "vcvtph2ps\t{$src, $dst|$dst, $src}", - [(set RC:$dst, (X86cvtph2ps VR128:$src))]>, + [(set RC:$dst, (X86any_cvtph2ps VR128:$src))]>, T8PD, VEX, Sched<[sched]>; let hasSideEffects = 0, mayLoad = 1 in def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), "vcvtph2ps\t{$src, $dst|$dst, $src}", - [(set RC:$dst, (X86cvtph2ps (loadv8i16 addr:$src)))]>, + [(set RC:$dst, (X86any_cvtph2ps (loadv8i16 addr:$src)))]>, T8PD, VEX, Sched<[sched.Folded]>; } @@ -7351,7 +7351,7 @@ multiclass f16c_ps2ph, + [(set VR128:$dst, (X86any_cvtps2ph RC:$src1, timm:$src2))]>, TAPD, VEX, Sched<[RR]>; let hasSideEffects = 0, mayStore = 1 in def mr : Ii8<0x1D, MRMDestMem, (outs), @@ -7369,21 +7369,21 @@ let Predicates = [HasF16C, NoVLX] in { WriteCvtPS2PHYSt>, VEX_L, SIMD_EXC; // Pattern match vcvtph2ps of a scalar i64 load. - def : Pat<(v4f32 (X86cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))), + def : Pat<(v4f32 (X86any_cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))), (VCVTPH2PSrm addr:$src)>; - def : Pat<(v4f32 (X86cvtph2ps (bc_v8i16 + def : Pat<(v4f32 (X86any_cvtph2ps (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))), (VCVTPH2PSrm addr:$src)>; def : Pat<(store (f64 (extractelt - (bc_v2f64 (v8i16 (X86cvtps2ph VR128:$src1, timm:$src2))), + (bc_v2f64 (v8i16 (X86any_cvtps2ph VR128:$src1, timm:$src2))), (iPTR 0))), addr:$dst), (VCVTPS2PHmr addr:$dst, VR128:$src1, timm:$src2)>; def : Pat<(store (i64 (extractelt - (bc_v2i64 (v8i16 (X86cvtps2ph VR128:$src1, timm:$src2))), + (bc_v2i64 (v8i16 (X86any_cvtps2ph VR128:$src1, timm:$src2))), (iPTR 0))), addr:$dst), (VCVTPS2PHmr addr:$dst, VR128:$src1, timm:$src2)>; - def : Pat<(store (v8i16 (X86cvtps2ph VR256:$src1, timm:$src2)), addr:$dst), + def : Pat<(store (v8i16 (X86any_cvtps2ph VR256:$src1, timm:$src2)), addr:$dst), (VCVTPS2PHYmr addr:$dst, VR256:$src1, timm:$src2)>; } -- GitLab From 5d58eb9f4f71292d9c67517d8cb0eb05e9fe82a3 Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Tue, 11 Feb 2020 19:43:20 +0700 Subject: [PATCH 115/142] [DebugInfo] Fix reading addresses in DWARFDebugAddr. As addresses in the address tables may have relocations, thus, the relocations should be resolved to read the correct address. That is especially important for targets that use RELA relocations because in that case addends are stored in relocation sections. Differential Revision: https://reviews.llvm.org/D74404 --- llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp | 5 +--- .../llvm-dwarfdump/X86/debug_addr_rela.s | 28 +++++++++++++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) create mode 100644 llvm/test/tools/llvm-dwarfdump/X86/debug_addr_rela.s diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp index 02b8b8ee4bfe..ba2c17749091 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp @@ -131,10 +131,7 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, Data.setAddressSize(HeaderData.AddrSize); uint32_t AddrCount = DataSize / HeaderData.AddrSize; for (uint32_t I = 0; I < AddrCount; ++I) - if (HeaderData.AddrSize == 4) - Addrs.push_back(Data.getU32(OffsetPtr)); - else - Addrs.push_back(Data.getU64(OffsetPtr)); + Addrs.push_back(Data.getRelocatedAddress(OffsetPtr)); return Error::success(); } diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_rela.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_rela.s new file mode 100644 index 000000000000..f0058b95475b --- /dev/null +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_rela.s @@ -0,0 +1,28 @@ +# RUN: llvm-mc %s -filetype obj -triple x86_64-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - | \ +# RUN: FileCheck %s + +## This checks that we use DWARFDataExtractor::getRelocatedAddress() to read +## addresses of an address table. In this test, the raw data in the .debug_addr +## section does not contain the full address, thus, it is required to resolve +## a RELA relocation to recover the real value. + +# CHECK: .debug_addr contents +# CHECK-NEXT: length = 0x0000000c, version = 0x0005, addr_size = 0x08, seg_size = 0x00 +# CHECK-NEXT: Addrs: [ +# CHECK-NEXT: 0x000000000000002a +# CHECK-NEXT: ] + + .text + .space 0x2a +.Lfoo: + + .section .debug_addr,"",@progbits + .long .LAddr0end-.LAddr0version # Length +.LAddr0version: + .short 5 # Version + .byte 8 # Address size + .byte 0 # Segment selector size +.LAddr0table: + .quad .Lfoo +.LAddr0end: -- GitLab From 675c4bebaffc0c6b28ac85602b278677c07e03e5 Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Thu, 6 Feb 2020 20:34:10 +0700 Subject: [PATCH 116/142] [DebugInfo] Do not dump header field for pre-DWARFv5 address tables. As there is no header in pre-DWARFv5 address tables, and we fill the class data members with some artificial values, we should not dump them as that might be misleading. Differential Revision: https://reviews.llvm.org/D74195 --- llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp | 11 ++++++----- llvm/test/DebugInfo/X86/debug_addr.ll | 3 +-- .../test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s | 1 - 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp index ba2c17749091..591c35b8532f 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp @@ -138,11 +138,12 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, void DWARFDebugAddrTable::dump(raw_ostream &OS, DIDumpOptions DumpOpts) const { if (DumpOpts.Verbose) OS << format("0x%8.8" PRIx32 ": ", HeaderOffset); - OS << format("Addr Section: length = 0x%8.8" PRIx32 - ", version = 0x%4.4" PRIx16 ", " - "addr_size = 0x%2.2" PRIx8 ", seg_size = 0x%2.2" PRIx8 "\n", - HeaderData.Length, HeaderData.Version, HeaderData.AddrSize, - HeaderData.SegSize); + if (HeaderData.Length) + OS << format("Address table header: length = 0x%8.8" PRIx32 + ", version = 0x%4.4" PRIx16 ", " + "addr_size = 0x%2.2" PRIx8 ", seg_size = 0x%2.2" PRIx8 "\n", + HeaderData.Length, HeaderData.Version, HeaderData.AddrSize, + HeaderData.SegSize); if (Addrs.size() > 0) { const char *AddrFmt = (HeaderData.AddrSize == 4) ? "0x%8.8" PRIx64 "\n" diff --git a/llvm/test/DebugInfo/X86/debug_addr.ll b/llvm/test/DebugInfo/X86/debug_addr.ll index 1fa797efd5fb..a9efba0d1bc8 100644 --- a/llvm/test/DebugInfo/X86/debug_addr.ll +++ b/llvm/test/DebugInfo/X86/debug_addr.ll @@ -22,7 +22,6 @@ ; DWARF4: DW_TAG_GNU_call_site ; DWARF4: DW_AT_low_pc [DW_FORM_GNU_addr_index] (indexed (00000002) address = 0x0000000000000018 ".text") ; DWARF4: .debug_addr contents: -; DWARF4-NEXT: 0x00000000: Addr Section: length = 0x00000000, version = 0x0004, addr_size = 0x04, seg_size = 0x00 ; DWARF4-NEXT: Addrs: [ ; DWARF4-NEXT: 0x00000000 ; DWARF4-NEXT: 0x00000010 @@ -39,7 +38,7 @@ ; DWARF5: DW_AT_low_pc [DW_FORM_addrx] (indexed (00000000) address = 0x0000000000000000 ".text") ; DWARF5: DW_AT_call_return_pc [DW_FORM_addrx] (indexed (00000002) address = 0x0000000000000018 ".text") ; DWARF5: .debug_addr contents: -; DWARF5-NEXT: 0x00000000: Addr Section: length = 0x00000010, version = 0x0005, addr_size = 0x04, seg_size = 0x00 +; DWARF5-NEXT: 0x00000000: Address table header: length = 0x00000010, version = 0x0005, addr_size = 0x04, seg_size = 0x00 ; DWARF5-NEXT: Addrs: [ ; DWARF5-NEXT: 0x00000000 ; DWARF5-NEXT: 0x00000010 diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s index 57e9dd3c5193..ff6364dab70c 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf4.s @@ -2,7 +2,6 @@ # RUN: llvm-dwarfdump --debug-addr %t.o | FileCheck %s # CHECK: .debug_addr contents -# CHECK-NEXT: length = 0x00000000, version = 0x0004, addr_size = 0x04, seg_size = 0x00 # CHECK-NEXT: Addrs: [ # CHECK-NEXT: 0x00000000 # CHECK-NEXT: 0x00000001 -- GitLab From 292b67f99310d10229e14dc0ece18855e22d11cc Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Tue, 11 Feb 2020 15:55:12 +0700 Subject: [PATCH 117/142] [DebugInfo] Use "an address table" in diagnostic messages of DWARFDebugAddr. This replaces a collocation "a .debug_addr table" with "an address table" because the latter sounds more accurate. Differential Revision: https://reviews.llvm.org/D74407 --- llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp | 22 +++++++++---------- .../X86/debug_addr_address_size_mismatch.s | 2 +- .../debug_addr_address_size_not_multiple.s | 2 +- .../X86/debug_addr_segment_selector.s | 2 +- .../X86/debug_addr_small_length_field.s | 2 +- .../debug_addr_too_small_for_length_field.s | 2 +- .../X86/debug_addr_too_small_for_section.s | 2 +- .../X86/debug_addr_version_mismatch.s | 2 +- 8 files changed, 18 insertions(+), 18 deletions(-) diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp index 591c35b8532f..72aadda8c600 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp @@ -28,8 +28,8 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, // Read and verify the length field. if (!Data.isValidOffsetForDataOfSize(*OffsetPtr, sizeof(uint32_t))) return createStringError(errc::invalid_argument, - "section is not large enough to contain a " - ".debug_addr table length at offset 0x%" + "section is not large enough to contain an " + "address table length at offset 0x%" PRIx64, *OffsetPtr); uint16_t UnitVersion; if (Version == 0) { @@ -54,7 +54,7 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, uint32_t TmpLength = getLength(); invalidateLength(); return createStringError(errc::invalid_argument, - ".debug_addr table at offset 0x%" PRIx64 + "address table at offset 0x%" PRIx64 " has too small length (0x%" PRIx32 ") to contain a complete header", HeaderOffset, TmpLength); @@ -64,7 +64,7 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, uint32_t TmpLength = getLength(); invalidateLength(); return createStringError(errc::invalid_argument, - "section is not large enough to contain a .debug_addr table " + "section is not large enough to contain an address table " "of length 0x%" PRIx32 " at offset 0x%" PRIx64, TmpLength, HeaderOffset); } @@ -97,33 +97,33 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, // attribute in the info table. if (HeaderData.Version != UnitVersion) return createStringError(errc::invalid_argument, - ".debug_addr table at offset 0x%" PRIx64 + "address table at offset 0x%" PRIx64 " has version %" PRIu16 " which is different from the version suggested" " by the DWARF unit header: %" PRIu16, HeaderOffset, HeaderData.Version, UnitVersion); if (HeaderData.AddrSize != 4 && HeaderData.AddrSize != 8) return createStringError(errc::not_supported, - ".debug_addr table at offset 0x%" PRIx64 + "address table at offset 0x%" PRIx64 " has unsupported address size %" PRIu8, HeaderOffset, HeaderData.AddrSize); if (HeaderData.AddrSize != AddrSize && AddrSize != 0) WarnCallback(createStringError( errc::invalid_argument, - ".debug_addr table at offset 0x%" PRIx64 " has address size %" PRIu8 + "address table at offset 0x%" PRIx64 " has address size %" PRIu8 " which is different from CU address size %" PRIu8, HeaderOffset, HeaderData.AddrSize, AddrSize)); // TODO: add support for non-zero segment selector size. if (HeaderData.SegSize != 0) return createStringError(errc::not_supported, - ".debug_addr table at offset 0x%" PRIx64 + "address table at offset 0x%" PRIx64 " has unsupported segment selector size %" PRIu8, HeaderOffset, HeaderData.SegSize); if (DataSize % HeaderData.AddrSize != 0) { invalidateLength(); return createStringError(errc::invalid_argument, - ".debug_addr table at offset 0x%" PRIx64 + "address table at offset 0x%" PRIx64 " contains data of size %" PRIu32 " which is not a multiple of addr size %" PRIu8, HeaderOffset, DataSize, HeaderData.AddrSize); @@ -159,8 +159,8 @@ Expected DWARFDebugAddrTable::getAddrEntry(uint32_t Index) const { if (Index < Addrs.size()) return Addrs[Index]; return createStringError(errc::invalid_argument, - "Index %" PRIu32 " is out of range of the " - ".debug_addr table at offset 0x%" PRIx64, + "Index %" PRIu32 " is out of range in the " + "address table at offset 0x%" PRIx64, Index, HeaderOffset); } diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_mismatch.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_mismatch.s index fca66237ee00..d5fdf5dc3d88 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_mismatch.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_mismatch.s @@ -2,7 +2,7 @@ # RUN: llvm-dwarfdump -debug-addr - 2> %t.warn | FileCheck %s # RUN: FileCheck %s -input-file %t.warn -check-prefix=WARN -# WARN: .debug_addr table at offset 0x0 has address size 8 which is different from CU address size 4 +# WARN: address table at offset 0x0 has address size 8 which is different from CU address size 4 # WARN-NOT: {{.}} # CHECK: .debug_addr contents diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s index e8835e087962..eaae931898bf 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: .debug_addr table at offset 0x0 contains data of size 7 which is not a multiple of addr size 4 +# ERR: address table at offset 0x0 contains data of size 7 which is not a multiple of addr size 4 # ERR-NOT: {{.}} # data size is not multiple of address_size diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_segment_selector.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_segment_selector.s index 21f0322fd2ec..3200b4f2da3b 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_segment_selector.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_segment_selector.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: .debug_addr table at offset 0x0 has unsupported segment selector size 1 +# ERR: address table at offset 0x0 has unsupported segment selector size 1 # ERR-NOT: {{.}} # non-zero segment_selector_size diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s index cbecb98e6bec..50c865f207dc 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: .debug_addr table at offset 0x0 has too small length (0x5) to contain a complete header +# ERR: address table at offset 0x0 has too small length (0x5) to contain a complete header # ERR-NOT: {{.}} # too small length value diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_length_field.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_length_field.s index c26bfcb02e0a..dcec7dad5f9e 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_length_field.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_length_field.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: section is not large enough to contain a .debug_addr table length at offset 0x0 +# ERR: section is not large enough to contain an address table length at offset 0x0 # ERR-NOT: {{.}} # too small section to contain length field diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s index facffee69fb6..98468fa36812 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: section is not large enough to contain a .debug_addr table of length 0x10 at offset 0x0 +# ERR: section is not large enough to contain an address table of length 0x10 at offset 0x0 # ERR-NOT: {{.}} # too small section to contain section of given length diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s index e349f3386a6c..788e102f4f02 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s @@ -2,7 +2,7 @@ # RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s # RUN: FileCheck %s -input-file %t.err -check-prefix=ERR -# ERR: .debug_addr table at offset 0x0 has version 4 which is different from the version suggested by the DWARF unit header: 5 +# ERR: address table at offset 0x0 has version 4 which is different from the version suggested by the DWARF unit header: 5 # ERR-NOT: {{.}} # CHECK: .debug_addr contents -- GitLab From de9604232a7c9e346faadf3708b61431bb441c1b Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Thu, 6 Feb 2020 16:30:30 +0700 Subject: [PATCH 118/142] [DebugInfo] Refine error messages in DWARFDebugAddr. As a preparation for the subsequent patches, this updates the wordings of some error messages in DWARFDebugAddr. Differential Revision: https://reviews.llvm.org/D74196 --- llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp | 25 +++++++++++-------- .../X86/debug_addr_invalid_addr_size.s | 2 +- .../X86/debug_addr_small_length_field.s | 2 +- .../X86/debug_addr_too_small_for_section.s | 2 +- .../X86/debug_addr_unsupported_version.s | 2 +- 5 files changed, 18 insertions(+), 15 deletions(-) diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp index 72aadda8c600..eb7070f55ca6 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp @@ -51,22 +51,23 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, HeaderOffset); } if (HeaderData.Length + sizeof(uint32_t) < sizeof(Header)) { - uint32_t TmpLength = getLength(); + uint32_t TmpLength = HeaderData.Length; invalidateLength(); return createStringError(errc::invalid_argument, "address table at offset 0x%" PRIx64 - " has too small length (0x%" PRIx32 - ") to contain a complete header", + " has a unit_length value of 0x%" PRIx32 + ", which is too small to contain a complete header", HeaderOffset, TmpLength); } uint64_t End = HeaderOffset + getLength(); if (!Data.isValidOffsetForDataOfSize(HeaderOffset, End - HeaderOffset)) { - uint32_t TmpLength = getLength(); + uint32_t TmpLength = HeaderData.Length; invalidateLength(); - return createStringError(errc::invalid_argument, + return createStringError( + errc::invalid_argument, "section is not large enough to contain an address table " - "of length 0x%" PRIx32 " at offset 0x%" PRIx64, - TmpLength, HeaderOffset); + "at offset 0x%" PRIx64 " with a unit_length value of 0x%" PRIx32, + HeaderOffset, TmpLength); } HeaderData.Version = Data.getU16(OffsetPtr); @@ -87,9 +88,10 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, // implementations of .debug_addr table, which doesn't contain a header // and consists only of a series of addresses. if (HeaderData.Version > 5) { - return createStringError(errc::not_supported, "version %" PRIu16 - " of .debug_addr section at offset 0x%" PRIx64 " is not supported", - HeaderData.Version, HeaderOffset); + return createStringError(errc::not_supported, + "address table at offset 0x%" PRIx64 + " has unsupported version %" PRIu16, + HeaderOffset, HeaderData.Version); } // FIXME: For now we just treat version mismatch as an error, // however the correct way to associate a .debug_addr table @@ -105,7 +107,8 @@ Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, if (HeaderData.AddrSize != 4 && HeaderData.AddrSize != 8) return createStringError(errc::not_supported, "address table at offset 0x%" PRIx64 - " has unsupported address size %" PRIu8, + " has unsupported address size %" PRIu8 + " (4 and 8 are supported)", HeaderOffset, HeaderData.AddrSize); if (HeaderData.AddrSize != AddrSize && AddrSize != 0) WarnCallback(createStringError( diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_invalid_addr_size.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_invalid_addr_size.s index 1ba1afebf5da..0ad055b2753d 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_invalid_addr_size.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_invalid_addr_size.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: unsupported address size 3 +# ERR: unsupported address size 3 (4 and 8 are supported) # ERR-NOT: {{.}} # invalid addr size diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s index 50c865f207dc..3b12737ddf59 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_small_length_field.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: address table at offset 0x0 has too small length (0x5) to contain a complete header +# ERR: address table at offset 0x0 has a unit_length value of 0x1, which is too small to contain a complete header # ERR-NOT: {{.}} # too small length value diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s index 98468fa36812..5bd90617e259 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_section.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: section is not large enough to contain an address table of length 0x10 at offset 0x0 +# ERR: section is not large enough to contain an address table at offset 0x0 with a unit_length value of 0xc # ERR-NOT: {{.}} # too small section to contain section of given length diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s index f30dd8f0b979..c2afea30e5a0 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s @@ -2,7 +2,7 @@ # RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s # RUN: FileCheck %s -input-file %t.err -check-prefix=ERR -# ERR: version 6 of .debug_addr section at offset 0x0 is not supported +# ERR: address table at offset 0x0 has unsupported version 6 # ERR-NOT: {{.}} # CHECK: .debug_addr contents -- GitLab From dc1661239358efb8144a179d6706d7faec7fec2f Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Thu, 6 Feb 2020 14:14:12 +0700 Subject: [PATCH 119/142] [DebugInfo] Simplify DWARFDebugAddr. The patch removes unnecessary members of DWARFDebugAddr and further simplifies the implementation by separating parsing methods of tables in the DWARFv5 and pre-standard formats. Differential Revision: https://reviews.llvm.org/D74197 --- .../llvm/DebugInfo/DWARF/DWARFDebugAddr.h | 86 +++--- llvm/lib/DebugInfo/DWARF/DWARFContext.cpp | 11 +- llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp | 246 +++++++++--------- .../debug_addr_address_size_not_multiple.s | 2 +- .../X86/debug_addr_unsupported_version.s | 11 + .../X86/debug_addr_version_mismatch.s | 42 --- 6 files changed, 173 insertions(+), 225 deletions(-) delete mode 100644 llvm/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h index 4539b9c9d581..fd9c5dc55c02 100644 --- a/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h +++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h @@ -27,69 +27,53 @@ class raw_ostream; /// The table consists of a header followed by an array of address values from /// .debug_addr section. class DWARFDebugAddrTable { -public: - struct Header { - /// The total length of the entries for this table, not including the length - /// field itself. - uint32_t Length = 0; - /// The DWARF version number. - uint16_t Version = 5; - /// The size in bytes of an address on the target architecture. For - /// segmented addressing, this is the size of the offset portion of the - /// address. - uint8_t AddrSize; - /// The size in bytes of a segment selector on the target architecture. - /// If the target system uses a flat address space, this value is 0. - uint8_t SegSize = 0; - }; - -private: dwarf::DwarfFormat Format; - uint64_t HeaderOffset; - Header HeaderData; - uint32_t DataSize = 0; + uint64_t Offset; + /// The total length of the entries for this table, not including the length + /// field itself. + uint32_t Length = 0; + /// The DWARF version number. + uint16_t Version; + /// The size in bytes of an address on the target architecture. For + /// segmented addressing, this is the size of the offset portion of the + /// address. + uint8_t AddrSize; + /// The size in bytes of a segment selector on the target architecture. + /// If the target system uses a flat address space, this value is 0. + uint8_t SegSize; std::vector Addrs; + /// Invalidate Length field to stop further processing. + void invalidateLength() { Length = 0; } + + Error extractAddresses(const DWARFDataExtractor &Data, uint64_t *OffsetPtr, + uint64_t EndOffset); + public: - void clear(); - /// Extract an entire table, including all addresses. - Error extract(DWARFDataExtractor Data, uint64_t *OffsetPtr, - uint16_t Version, uint8_t AddrSize, + /// Extract the entire table, including all addresses. + Error extract(const DWARFDataExtractor &Data, uint64_t *OffsetPtr, + uint16_t CUVersion, uint8_t CUAddrSize, std::function WarnCallback); - uint64_t getHeaderOffset() const { return HeaderOffset; } - uint8_t getAddrSize() const { return HeaderData.AddrSize; } + /// Extract a DWARFv5 address table. + Error extractV5(const DWARFDataExtractor &Data, uint64_t *OffsetPtr, + uint8_t CUAddrSize, std::function WarnCallback); + + /// Extract a pre-DWARFv5 address table. Such tables do not have a header + /// and consist only of a series of addresses. + /// See https://gcc.gnu.org/wiki/DebugFission for details. + Error extractPreStandard(const DWARFDataExtractor &Data, uint64_t *OffsetPtr, + uint16_t CUVersion, uint8_t CUAddrSize); + void dump(raw_ostream &OS, DIDumpOptions DumpOpts = {}) const; /// Return the address based on a given index. Expected getAddrEntry(uint32_t Index) const; - /// Return the size of the table header including the length - /// but not including the addresses. - uint8_t getHeaderSize() const { - switch (Format) { - case dwarf::DwarfFormat::DWARF32: - return 8; // 4 + 2 + 1 + 1 - case dwarf::DwarfFormat::DWARF64: - return 16; // 12 + 2 + 1 + 1 - } - llvm_unreachable("Invalid DWARF format (expected DWARF32 or DWARF64)"); - } - - /// Returns the length of this table, including the length field, or 0 if the - /// length has not been determined (e.g. because the table has not yet been - /// parsed, or there was a problem in parsing). - uint32_t getLength() const; - - /// Verify that the given length is valid for this table. - bool hasValidLength() const { return getLength() != 0; } - - /// Invalidate Length field to stop further processing. - void invalidateLength() { HeaderData.Length = 0; } - - /// Returns the length of the array of addresses. - uint32_t getDataSize() const; + /// Return the full length of this table, including the length field. + /// Return None if the length cannot be identified reliably. + Optional getFullLength() const; }; } // end namespace llvm diff --git a/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp b/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp index eb736b39d7d2..62bc5138e32a 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp @@ -252,12 +252,13 @@ static void dumpAddrSection(raw_ostream &OS, DWARFDataExtractor &AddrData, WithColor::error() << toString(std::move(Err)) << '\n'; // Keep going after an error, if we can, assuming that the length field // could be read. If it couldn't, stop reading the section. - if (!AddrTable.hasValidLength()) - break; - Offset = TableOffset + AddrTable.getLength(); - } else { - AddrTable.dump(OS, DumpOpts); + if (auto TableLength = AddrTable.getFullLength()) { + Offset = TableOffset + *TableLength; + continue; + } + break; } + AddrTable.dump(OS, DumpOpts); } } diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp index eb7070f55ca6..d2344e7e4f5d 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp @@ -12,145 +12,146 @@ using namespace llvm; -void DWARFDebugAddrTable::clear() { - HeaderData = {}; +Error DWARFDebugAddrTable::extractAddresses(const DWARFDataExtractor &Data, + uint64_t *OffsetPtr, + uint64_t EndOffset) { + assert(EndOffset >= *OffsetPtr); + uint64_t DataSize = EndOffset - *OffsetPtr; + assert(Data.isValidOffsetForDataOfSize(*OffsetPtr, DataSize)); + if (AddrSize != 4 && AddrSize != 8) + return createStringError(errc::not_supported, + "address table at offset 0x%" PRIx64 + " has unsupported address size %" PRIu8 + " (4 and 8 are supported)", + Offset, AddrSize); + if (DataSize % AddrSize != 0) { + invalidateLength(); + return createStringError(errc::invalid_argument, + "address table at offset 0x%" PRIx64 + " contains data of size 0x%" PRIx64 + " which is not a multiple of addr size %" PRIu8, + Offset, DataSize, AddrSize); + } Addrs.clear(); - invalidateLength(); + size_t Count = DataSize / AddrSize; + Addrs.reserve(Count); + while (Count--) + Addrs.push_back(Data.getRelocatedValue(AddrSize, OffsetPtr)); + return Error::success(); } -Error DWARFDebugAddrTable::extract(DWARFDataExtractor Data, - uint64_t *OffsetPtr, - uint16_t Version, - uint8_t AddrSize, - std::function WarnCallback) { - clear(); - HeaderOffset = *OffsetPtr; - // Read and verify the length field. - if (!Data.isValidOffsetForDataOfSize(*OffsetPtr, sizeof(uint32_t))) +Error DWARFDebugAddrTable::extractV5(const DWARFDataExtractor &Data, + uint64_t *OffsetPtr, uint8_t CUAddrSize, + std::function WarnCallback) { + Offset = *OffsetPtr; + // Check that we can read the unit length field. + if (!Data.isValidOffsetForDataOfSize(Offset, 4)) return createStringError(errc::invalid_argument, - "section is not large enough to contain an " - "address table length at offset 0x%" - PRIx64, *OffsetPtr); - uint16_t UnitVersion; - if (Version == 0) { - WarnCallback(createStringError(errc::invalid_argument, - "DWARF version is not defined in CU," - " assuming version 5")); - UnitVersion = 5; - } else { - UnitVersion = Version; - } + "section is not large enough to contain an " + "address table length at offset 0x%" PRIx64, + Offset); // TODO: Add support for DWARF64. Format = dwarf::DwarfFormat::DWARF32; - if (UnitVersion >= 5) { - HeaderData.Length = Data.getU32(OffsetPtr); - if (HeaderData.Length == dwarf::DW_LENGTH_DWARF64) { - invalidateLength(); - return createStringError(errc::not_supported, - "DWARF64 is not supported in .debug_addr at offset 0x%" PRIx64, - HeaderOffset); - } - if (HeaderData.Length + sizeof(uint32_t) < sizeof(Header)) { - uint32_t TmpLength = HeaderData.Length; - invalidateLength(); - return createStringError(errc::invalid_argument, - "address table at offset 0x%" PRIx64 - " has a unit_length value of 0x%" PRIx32 - ", which is too small to contain a complete header", - HeaderOffset, TmpLength); - } - uint64_t End = HeaderOffset + getLength(); - if (!Data.isValidOffsetForDataOfSize(HeaderOffset, End - HeaderOffset)) { - uint32_t TmpLength = HeaderData.Length; - invalidateLength(); - return createStringError( - errc::invalid_argument, - "section is not large enough to contain an address table " - "at offset 0x%" PRIx64 " with a unit_length value of 0x%" PRIx32, - HeaderOffset, TmpLength); - } - - HeaderData.Version = Data.getU16(OffsetPtr); - HeaderData.AddrSize = Data.getU8(OffsetPtr); - HeaderData.SegSize = Data.getU8(OffsetPtr); - DataSize = getDataSize(); - } else { - HeaderData.Version = UnitVersion; - HeaderData.AddrSize = AddrSize; - // TODO: Support for non-zero SegSize. - HeaderData.SegSize = 0; - DataSize = Data.size(); + Length = Data.getU32(OffsetPtr); + if (Length == dwarf::DW_LENGTH_DWARF64) { + invalidateLength(); + return createStringError( + errc::not_supported, + "DWARF64 is not supported in .debug_addr at offset 0x%" PRIx64, Offset); + } + + if (!Data.isValidOffsetForDataOfSize(*OffsetPtr, Length)) { + uint32_t DiagnosticLength = Length; + invalidateLength(); + return createStringError( + errc::invalid_argument, + "section is not large enough to contain an address table " + "at offset 0x%" PRIx64 " with a unit_length value of 0x%" PRIx32, + Offset, DiagnosticLength); + } + uint64_t EndOffset = *OffsetPtr + Length; + // Ensure that we can read the remaining header fields. + if (Length < 4) { + uint32_t DiagnosticLength = Length; + invalidateLength(); + return createStringError( + errc::invalid_argument, + "address table at offset 0x%" PRIx64 + " has a unit_length value of 0x%" PRIx32 + ", which is too small to contain a complete header", + Offset, DiagnosticLength); } - // Perform basic validation of the remaining header fields. + Version = Data.getU16(OffsetPtr); + AddrSize = Data.getU8(OffsetPtr); + SegSize = Data.getU8(OffsetPtr); - // We support DWARF version 5 for now as well as pre-DWARF5 - // implementations of .debug_addr table, which doesn't contain a header - // and consists only of a series of addresses. - if (HeaderData.Version > 5) { + // Perform a basic validation of the header fields. + if (Version != 5) return createStringError(errc::not_supported, "address table at offset 0x%" PRIx64 " has unsupported version %" PRIu16, - HeaderOffset, HeaderData.Version); - } - // FIXME: For now we just treat version mismatch as an error, - // however the correct way to associate a .debug_addr table - // with a .debug_info table is to look at the DW_AT_addr_base - // attribute in the info table. - if (HeaderData.Version != UnitVersion) - return createStringError(errc::invalid_argument, - "address table at offset 0x%" PRIx64 - " has version %" PRIu16 - " which is different from the version suggested" - " by the DWARF unit header: %" PRIu16, - HeaderOffset, HeaderData.Version, UnitVersion); - if (HeaderData.AddrSize != 4 && HeaderData.AddrSize != 8) + Offset, Version); + // TODO: add support for non-zero segment selector size. + if (SegSize != 0) return createStringError(errc::not_supported, - "address table at offset 0x%" PRIx64 - " has unsupported address size %" PRIu8 - " (4 and 8 are supported)", - HeaderOffset, HeaderData.AddrSize); - if (HeaderData.AddrSize != AddrSize && AddrSize != 0) + "address table at offset 0x%" PRIx64 + " has unsupported segment selector size %" PRIu8, + Offset, SegSize); + + if (Error Err = extractAddresses(Data, OffsetPtr, EndOffset)) + return Err; + if (CUAddrSize && AddrSize != CUAddrSize) { WarnCallback(createStringError( errc::invalid_argument, "address table at offset 0x%" PRIx64 " has address size %" PRIu8 " which is different from CU address size %" PRIu8, - HeaderOffset, HeaderData.AddrSize, AddrSize)); - - // TODO: add support for non-zero segment selector size. - if (HeaderData.SegSize != 0) - return createStringError(errc::not_supported, - "address table at offset 0x%" PRIx64 - " has unsupported segment selector size %" PRIu8, - HeaderOffset, HeaderData.SegSize); - if (DataSize % HeaderData.AddrSize != 0) { - invalidateLength(); - return createStringError(errc::invalid_argument, - "address table at offset 0x%" PRIx64 - " contains data of size %" PRIu32 - " which is not a multiple of addr size %" PRIu8, - HeaderOffset, DataSize, HeaderData.AddrSize); + Offset, AddrSize, CUAddrSize)); } - Data.setAddressSize(HeaderData.AddrSize); - uint32_t AddrCount = DataSize / HeaderData.AddrSize; - for (uint32_t I = 0; I < AddrCount; ++I) - Addrs.push_back(Data.getRelocatedAddress(OffsetPtr)); return Error::success(); } +Error DWARFDebugAddrTable::extractPreStandard(const DWARFDataExtractor &Data, + uint64_t *OffsetPtr, + uint16_t CUVersion, + uint8_t CUAddrSize) { + assert(CUVersion > 0 && CUVersion < 5); + + Offset = *OffsetPtr; + Length = 0; + Version = CUVersion; + AddrSize = CUAddrSize; + SegSize = 0; + + return extractAddresses(Data, OffsetPtr, Data.size()); +} + +Error DWARFDebugAddrTable::extract(const DWARFDataExtractor &Data, + uint64_t *OffsetPtr, + uint16_t CUVersion, + uint8_t CUAddrSize, + std::function WarnCallback) { + if (CUVersion > 0 && CUVersion < 5) + return extractPreStandard(Data, OffsetPtr, CUVersion, CUAddrSize); + if (CUVersion == 0) + WarnCallback(createStringError(errc::invalid_argument, + "DWARF version is not defined in CU," + " assuming version 5")); + return extractV5(Data, OffsetPtr, CUAddrSize, WarnCallback); +} + void DWARFDebugAddrTable::dump(raw_ostream &OS, DIDumpOptions DumpOpts) const { if (DumpOpts.Verbose) - OS << format("0x%8.8" PRIx32 ": ", HeaderOffset); - if (HeaderData.Length) + OS << format("0x%8.8" PRIx32 ": ", Offset); + if (Length) OS << format("Address table header: length = 0x%8.8" PRIx32 - ", version = 0x%4.4" PRIx16 ", " - "addr_size = 0x%2.2" PRIx8 ", seg_size = 0x%2.2" PRIx8 "\n", - HeaderData.Length, HeaderData.Version, HeaderData.AddrSize, - HeaderData.SegSize); + ", version = 0x%4.4" PRIx16 ", addr_size = 0x%2.2" PRIx8 + ", seg_size = 0x%2.2" PRIx8 "\n", + Length, Version, AddrSize, SegSize); if (Addrs.size() > 0) { - const char *AddrFmt = (HeaderData.AddrSize == 4) ? "0x%8.8" PRIx64 "\n" - : "0x%16.16" PRIx64 "\n"; + const char *AddrFmt = + (AddrSize == 4) ? "0x%8.8" PRIx64 "\n" : "0x%16.16" PRIx64 "\n"; OS << "Addrs: [\n"; for (uint64_t Addr : Addrs) OS << format(AddrFmt, Addr); @@ -162,22 +163,15 @@ Expected DWARFDebugAddrTable::getAddrEntry(uint32_t Index) const { if (Index < Addrs.size()) return Addrs[Index]; return createStringError(errc::invalid_argument, - "Index %" PRIu32 " is out of range in the " + "Index %" PRIu32 " is out of range of the " "address table at offset 0x%" PRIx64, - Index, HeaderOffset); + Index, Offset); } -uint32_t DWARFDebugAddrTable::getLength() const { - if (HeaderData.Length == 0) - return 0; +Optional DWARFDebugAddrTable::getFullLength() const { + if (Length == 0) + return None; // TODO: DWARF64 support. - return HeaderData.Length + sizeof(uint32_t); + return Length + sizeof(uint32_t); } -uint32_t DWARFDebugAddrTable::getDataSize() const { - if (DataSize != 0) - return DataSize; - if (getLength() == 0) - return 0; - return getLength() - getHeaderSize(); -} diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s index eaae931898bf..d758709c6703 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_address_size_not_multiple.s @@ -4,7 +4,7 @@ # CHECK: .debug_addr contents: # CHECK-NOT: {{.}} -# ERR: address table at offset 0x0 contains data of size 7 which is not a multiple of addr size 4 +# ERR: address table at offset 0x0 contains data of size 0x7 which is not a multiple of addr size 4 # ERR-NOT: {{.}} # data size is not multiple of address_size diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s index c2afea30e5a0..4eeeaa7e6980 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_unsupported_version.s @@ -3,6 +3,7 @@ # RUN: FileCheck %s -input-file %t.err -check-prefix=ERR # ERR: address table at offset 0x0 has unsupported version 6 +# ERR: address table at offset 0x20 has unsupported version 4 # ERR-NOT: {{.}} # CHECK: .debug_addr contents @@ -40,3 +41,13 @@ .byte 0 # segment_selector_size .long 0x00000002 .long 0x00000003 + + .section .debug_addr,"",@progbits +.Ldebug_addr2: + .long 12 # unit_length = .short + .byte + .byte + .long + .long + .short 4 # version + .byte 4 # address_size + .byte 0 # segment_selector_size + .long 0x00000000 + .long 0x00000001 + diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s deleted file mode 100644 index 788e102f4f02..000000000000 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_version_mismatch.s +++ /dev/null @@ -1,42 +0,0 @@ -# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ -# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s -# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR - -# ERR: address table at offset 0x0 has version 4 which is different from the version suggested by the DWARF unit header: 5 -# ERR-NOT: {{.}} - -# CHECK: .debug_addr contents -# CHECK-NEXT: length = 0x0000000c, version = 0x0005, addr_size = 0x04, seg_size = 0x00 -# CHECK-NEXT: Addrs: [ -# CHECK-NEXT: 0x00000000 -# CHECK-NEXT: 0x00000001 -# CHECK-NEXT: ] -# CHECK-NOT: {{.}} - - .section .debug_abbrev,"",@progbits - .byte 1 # Abbreviation Code - .section .debug_info,"",@progbits -.Lcu_begin0: - .long 8 # Length of Unit - .short 5 # DWARF version number - .byte 1 # DWARF unit type - .byte 4 # Address Size (in bytes) - .long .debug_abbrev # Offset Into Abbrev. Section - - .section .debug_addr,"",@progbits -.Ldebug_addr0: - .long 12 # unit_length = .short + .byte + .byte + .long + .long - .short 4 # version - .byte 4 # address_size - .byte 0 # segment_selector_size - .long 0x00000000 - .long 0x00000001 - - .section .debug_addr,"",@progbits -.Ldebug_addr1: - .long 12 # unit_length = .short + .byte + .byte + .long + .long - .short 5 # version - .byte 4 # address_size - .byte 0 # segment_selector_size - .long 0x00000000 - .long 0x00000001 -- GitLab From 07e50c7b9161e32c43e095aed586614bf8b02c71 Mon Sep 17 00:00:00 2001 From: Igor Kudrin Date: Mon, 8 Jul 2019 21:55:36 +0700 Subject: [PATCH 120/142] [DebugInfo] Add support for DWARF64 into DWARFDebugAddr. Differential Revision: https://reviews.llvm.org/D74198 --- .../llvm/DebugInfo/DWARF/DWARFDebugAddr.h | 2 +- llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp | 39 ++++++++++++------ .../llvm-dwarfdump/X86/debug_addr_dwarf64.s | 40 +++++++++++-------- .../X86/debug_addr_reserved_length.s | 8 ++++ ...addr_too_small_for_extended_length_field.s | 13 ++++++ 5 files changed, 72 insertions(+), 30 deletions(-) create mode 100644 llvm/test/tools/llvm-dwarfdump/X86/debug_addr_reserved_length.s create mode 100644 llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_extended_length_field.s diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h index fd9c5dc55c02..32844ffd570f 100644 --- a/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h +++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFDebugAddr.h @@ -31,7 +31,7 @@ class DWARFDebugAddrTable { uint64_t Offset; /// The total length of the entries for this table, not including the length /// field itself. - uint32_t Length = 0; + uint64_t Length = 0; /// The DWARF version number. uint16_t Version; /// The size in bytes of an address on the target architecture. For diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp index d2344e7e4f5d..273d316e0912 100644 --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugAddr.cpp @@ -50,34 +50,48 @@ Error DWARFDebugAddrTable::extractV5(const DWARFDataExtractor &Data, "section is not large enough to contain an " "address table length at offset 0x%" PRIx64, Offset); - // TODO: Add support for DWARF64. Format = dwarf::DwarfFormat::DWARF32; Length = Data.getU32(OffsetPtr); if (Length == dwarf::DW_LENGTH_DWARF64) { + // Check that we can read the extended unit length field. + if (!Data.isValidOffsetForDataOfSize(*OffsetPtr, 8)) { + invalidateLength(); + return createStringError( + errc::invalid_argument, + "section is not large enough to contain an extended length field " + "of the address table at offset 0x%" PRIx64, + Offset); + } + Format = dwarf::DwarfFormat::DWARF64; + Length = Data.getU64(OffsetPtr); + } else if (Length >= dwarf::DW_LENGTH_lo_reserved) { + uint64_t DiagnosticLength = Length; invalidateLength(); return createStringError( errc::not_supported, - "DWARF64 is not supported in .debug_addr at offset 0x%" PRIx64, Offset); + "address table at offset 0x%" PRIx64 + " has unsupported reserved unit length of value 0x%" PRIx64, + Offset, DiagnosticLength); } if (!Data.isValidOffsetForDataOfSize(*OffsetPtr, Length)) { - uint32_t DiagnosticLength = Length; + uint64_t DiagnosticLength = Length; invalidateLength(); return createStringError( errc::invalid_argument, "section is not large enough to contain an address table " - "at offset 0x%" PRIx64 " with a unit_length value of 0x%" PRIx32, + "at offset 0x%" PRIx64 " with a unit_length value of 0x%" PRIx64, Offset, DiagnosticLength); } uint64_t EndOffset = *OffsetPtr + Length; // Ensure that we can read the remaining header fields. if (Length < 4) { - uint32_t DiagnosticLength = Length; + uint64_t DiagnosticLength = Length; invalidateLength(); return createStringError( errc::invalid_argument, "address table at offset 0x%" PRIx64 - " has a unit_length value of 0x%" PRIx32 + " has a unit_length value of 0x%" PRIx64 ", which is too small to contain a complete header", Offset, DiagnosticLength); } @@ -142,12 +156,14 @@ Error DWARFDebugAddrTable::extract(const DWARFDataExtractor &Data, void DWARFDebugAddrTable::dump(raw_ostream &OS, DIDumpOptions DumpOpts) const { if (DumpOpts.Verbose) - OS << format("0x%8.8" PRIx32 ": ", Offset); - if (Length) - OS << format("Address table header: length = 0x%8.8" PRIx32 + OS << format("0x%8.8" PRIx64 ": ", Offset); + if (Length) { + int LengthFieldWidth = (Format == dwarf::DwarfFormat::DWARF64) ? 16 : 8; + OS << format("Address table header: length = 0x%0*" PRIx64 ", version = 0x%4.4" PRIx16 ", addr_size = 0x%2.2" PRIx8 ", seg_size = 0x%2.2" PRIx8 "\n", - Length, Version, AddrSize, SegSize); + LengthFieldWidth, Length, Version, AddrSize, SegSize); + } if (Addrs.size() > 0) { const char *AddrFmt = @@ -171,7 +187,6 @@ Expected DWARFDebugAddrTable::getAddrEntry(uint32_t Index) const { Optional DWARFDebugAddrTable::getFullLength() const { if (Length == 0) return None; - // TODO: DWARF64 support. - return Length + sizeof(uint32_t); + return Length + dwarf::getUnitLengthFieldByteSize(Format); } diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf64.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf64.s index bed41952df05..6c97ae81909d 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf64.s +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_dwarf64.s @@ -1,19 +1,25 @@ -# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ -# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s -# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR +# RUN: llvm-mc %s -filetype obj -triple x86_64-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - | \ +# RUN: FileCheck %s -# CHECK: .debug_addr contents: -# CHECK-NOT: {{.}} -# ERR: DWARF64 is not supported in .debug_addr at offset 0x0 -# ERR-NOT: {{.}} +# CHECK: .debug_addr contents: +# CHECK-NEXT: Address table header: +# CHECK-SAME: length = 0x000000000000000c, +# CHECK-SAME: version = 0x0005, +# CHECK-SAME: addr_size = 0x04, +# CHECK-SAME: seg_size = 0x00 +# CHECK-NEXT: Addrs: [ +# CHECK-NEXT: 0x00000000 +# CHECK-NEXT: 0x00001000 +# CHECK-NEXT: ] -# DWARF64 table - .section .debug_addr,"",@progbits -.Ldebug_addr0: - .long 0xffffffff # unit_length DWARF64 mark - .quad 12 # unit_length - .short 5 # version - .byte 3 # address_size - .byte 0 # segment_selector_size - .long 0x00000000 - .long 0x00000001 + .section .debug_addr,"",@progbits + .long 0xffffffff # DWARF64 mark + .quad .LAddr0end-.LAddr0version # Length +.LAddr0version: + .short 5 # Version + .byte 4 # Address size + .byte 0 # Segment selector size + .long 0x00000000 + .long 0x00001000 +.LAddr0end: diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_reserved_length.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_reserved_length.s new file mode 100644 index 000000000000..58857808422f --- /dev/null +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_reserved_length.s @@ -0,0 +1,8 @@ +# RUN: llvm-mc %s -filetype obj -triple x86_64-pc-linux -o - | \ +# RUN: llvm-dwarfdump --debug-addr - 2>&1 | \ +# RUN: FileCheck %s --implicit-check-not=error + +# CHECK: error: address table at offset 0x0 has unsupported reserved unit length of value 0xfffffff0 + +.section .debug_addr,"",@progbits +.long 0xfffffff0 diff --git a/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_extended_length_field.s b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_extended_length_field.s new file mode 100644 index 000000000000..8c2cc11de854 --- /dev/null +++ b/llvm/test/tools/llvm-dwarfdump/X86/debug_addr_too_small_for_extended_length_field.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc %s -filetype obj -triple i386-pc-linux -o - | \ +# RUN: llvm-dwarfdump -debug-addr - 2> %t.err | FileCheck %s +# RUN: FileCheck %s -input-file %t.err -check-prefix=ERR + +# CHECK: .debug_addr contents: +# CHECK-NOT: {{.}} +# ERR: section is not large enough to contain an extended length field of the address table at offset 0x0 +# ERR-NOT: {{.}} + +# too small section to contain an extended length field of a DWARF64 address table. + .section .debug_addr,"",@progbits + .long 0xffffffff # DWARF64 mark + .space 7 # a DWARF64 unit length field takes 8 bytes. -- GitLab From 3988b7046a5c998deacde3b89187d6e2eb76154d Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 11 Feb 2020 23:13:28 -0800 Subject: [PATCH 121/142] [X86] Correct the predicate on some patterns for 128 and 256 EVEX versions of VCVTPS2PH. These should require AVX512VL not AVX512F. The legacy VEX patterns will match first unless AVX512VL is enabled so this doesn't cause a functional issue. --- llvm/lib/Target/X86/X86InstrAVX512.td | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index f07f5687cf37..53a9294c9fef 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -8664,14 +8664,18 @@ let Predicates = [HasAVX512] in { WriteCvtPS2PHZ, WriteCvtPS2PHZSt>, avx512_cvtps2ph_sae, EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; - let Predicates = [HasVLX] in { - defm VCVTPS2PHZ256 : avx512_cvtps2ph, - EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>; - defm VCVTPS2PHZ128 : avx512_cvtps2ph, - EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>; - } + + def : Pat<(store (v16i16 (X86any_cvtps2ph VR512:$src1, timm:$src2)), addr:$dst), + (VCVTPS2PHZmr addr:$dst, VR512:$src1, timm:$src2)>; +} + +let Predicates = [HasVLX] in { + defm VCVTPS2PHZ256 : avx512_cvtps2ph, + EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>; + defm VCVTPS2PHZ128 : avx512_cvtps2ph, + EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>; def : Pat<(store (f64 (extractelt (bc_v2f64 (v8i16 (X86any_cvtps2ph VR128X:$src1, timm:$src2))), @@ -8683,8 +8687,6 @@ let Predicates = [HasAVX512] in { (VCVTPS2PHZ128mr addr:$dst, VR128X:$src1, timm:$src2)>; def : Pat<(store (v8i16 (X86any_cvtps2ph VR256X:$src1, timm:$src2)), addr:$dst), (VCVTPS2PHZ256mr addr:$dst, VR256X:$src1, timm:$src2)>; - def : Pat<(store (v16i16 (X86any_cvtps2ph VR512:$src1, timm:$src2)), addr:$dst), - (VCVTPS2PHZmr addr:$dst, VR512:$src1, timm:$src2)>; } // Unordered/Ordered scalar fp compare with Sae and set EFLAGS -- GitLab From 746395a446f7de0657bde6942a31bd14f4ce9adf Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 11 Feb 2020 23:16:32 -0800 Subject: [PATCH 122/142] [X86] Remove unnecessary hasSideEffects = 0, mayLoad = 1 from an instruction with a pattern. NFC --- llvm/lib/Target/X86/X86InstrSSE.td | 1 - 1 file changed, 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 54cb78d72ddc..a8c285cfe5f5 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -7339,7 +7339,6 @@ multiclass f16c_ph2ps, T8PD, VEX, Sched<[sched]>; - let hasSideEffects = 0, mayLoad = 1 in def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), "vcvtph2ps\t{$src, $dst|$dst, $src}", [(set RC:$dst, (X86any_cvtph2ps (loadv8i16 addr:$src)))]>, -- GitLab From 33b9f3abd78ffe31e2f468f64d36dbdf75b25d6e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 11 Feb 2020 23:27:26 -0800 Subject: [PATCH 123/142] [X86] Add test case for SoftPromoteHalf of STRICT_FP_EXTEND/STRICT_FP_ROUND. Tests that should have been with 0daf9b8e41327b1511b2bbc272184ff4fdb8de79 --- llvm/test/CodeGen/X86/half-constrained.ll | 379 ++++++++++++++++++++++ 1 file changed, 379 insertions(+) create mode 100644 llvm/test/CodeGen/X86/half-constrained.ll diff --git a/llvm/test/CodeGen/X86/half-constrained.ll b/llvm/test/CodeGen/X86/half-constrained.ll new file mode 100644 index 000000000000..2082e1df67bf --- /dev/null +++ b/llvm/test/CodeGen/X86/half-constrained.ll @@ -0,0 +1,379 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s --check-prefix=X32-NOF16C +; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s --check-prefix=X32-F16C +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s --check-prefix=X64-NOF16C +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=f16c | FileCheck %s --check-prefix=X64-F16C + +@a = global half 0xH0000, align 2 +@b = global half 0xH0000, align 2 +@c = global half 0xH0000, align 2 + +define float @half_to_float() strictfp { +; X32-NOF16C-LABEL: half_to_float: +; X32-NOF16C: ## %bb.0: +; X32-NOF16C-NEXT: subl $12, %esp +; X32-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X32-NOF16C-NEXT: movzwl _a, %eax +; X32-NOF16C-NEXT: movl %eax, (%esp) +; X32-NOF16C-NEXT: calll ___extendhfsf2 +; X32-NOF16C-NEXT: addl $12, %esp +; X32-NOF16C-NEXT: retl +; +; X32-F16C-LABEL: half_to_float: +; X32-F16C: ## %bb.0: +; X32-F16C-NEXT: subl $12, %esp +; X32-F16C-NEXT: .cfi_def_cfa_offset 16 +; X32-F16C-NEXT: movzwl _a, %eax +; X32-F16C-NEXT: movl %eax, (%esp) +; X32-F16C-NEXT: calll ___extendhfsf2 +; X32-F16C-NEXT: addl $12, %esp +; X32-F16C-NEXT: retl +; +; X64-NOF16C-LABEL: half_to_float: +; X64-NOF16C: ## %bb.0: +; X64-NOF16C-NEXT: pushq %rax +; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi +; X64-NOF16C-NEXT: callq ___extendhfsf2 +; X64-NOF16C-NEXT: popq %rax +; X64-NOF16C-NEXT: retq +; +; X64-F16C-LABEL: half_to_float: +; X64-F16C: ## %bb.0: +; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax +; X64-F16C-NEXT: vmovd %eax, %xmm0 +; X64-F16C-NEXT: vcvtph2ps %xmm0, %xmm0 +; X64-F16C-NEXT: retq + %1 = load half, half* @a, align 2 + %2 = tail call float @llvm.experimental.constrained.fpext.f32.f16(half %1, metadata !"fpexcept.strict") #0 + ret float %2 +} + +define double @half_to_double() strictfp { +; X32-NOF16C-LABEL: half_to_double: +; X32-NOF16C: ## %bb.0: +; X32-NOF16C-NEXT: subl $12, %esp +; X32-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X32-NOF16C-NEXT: movzwl _a, %eax +; X32-NOF16C-NEXT: movl %eax, (%esp) +; X32-NOF16C-NEXT: calll ___extendhfsf2 +; X32-NOF16C-NEXT: addl $12, %esp +; X32-NOF16C-NEXT: retl +; +; X32-F16C-LABEL: half_to_double: +; X32-F16C: ## %bb.0: +; X32-F16C-NEXT: subl $12, %esp +; X32-F16C-NEXT: .cfi_def_cfa_offset 16 +; X32-F16C-NEXT: movzwl _a, %eax +; X32-F16C-NEXT: movl %eax, (%esp) +; X32-F16C-NEXT: calll ___extendhfsf2 +; X32-F16C-NEXT: addl $12, %esp +; X32-F16C-NEXT: retl +; +; X64-NOF16C-LABEL: half_to_double: +; X64-NOF16C: ## %bb.0: +; X64-NOF16C-NEXT: pushq %rax +; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi +; X64-NOF16C-NEXT: callq ___extendhfsf2 +; X64-NOF16C-NEXT: cvtss2sd %xmm0, %xmm0 +; X64-NOF16C-NEXT: popq %rax +; X64-NOF16C-NEXT: retq +; +; X64-F16C-LABEL: half_to_double: +; X64-F16C: ## %bb.0: +; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax +; X64-F16C-NEXT: vmovd %eax, %xmm0 +; X64-F16C-NEXT: vcvtph2ps %xmm0, %xmm0 +; X64-F16C-NEXT: vcvtss2sd %xmm0, %xmm0, %xmm0 +; X64-F16C-NEXT: retq + %1 = load half, half* @a, align 2 + %2 = tail call double @llvm.experimental.constrained.fpext.f64.f16(half %1, metadata !"fpexcept.strict") #0 + ret double %2 +} + +define x86_fp80 @half_to_fp80() strictfp { +; X32-NOF16C-LABEL: half_to_fp80: +; X32-NOF16C: ## %bb.0: +; X32-NOF16C-NEXT: subl $12, %esp +; X32-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X32-NOF16C-NEXT: movzwl _a, %eax +; X32-NOF16C-NEXT: movl %eax, (%esp) +; X32-NOF16C-NEXT: calll ___extendhfsf2 +; X32-NOF16C-NEXT: addl $12, %esp +; X32-NOF16C-NEXT: retl +; +; X32-F16C-LABEL: half_to_fp80: +; X32-F16C: ## %bb.0: +; X32-F16C-NEXT: subl $12, %esp +; X32-F16C-NEXT: .cfi_def_cfa_offset 16 +; X32-F16C-NEXT: movzwl _a, %eax +; X32-F16C-NEXT: movl %eax, (%esp) +; X32-F16C-NEXT: calll ___extendhfsf2 +; X32-F16C-NEXT: addl $12, %esp +; X32-F16C-NEXT: retl +; +; X64-NOF16C-LABEL: half_to_fp80: +; X64-NOF16C: ## %bb.0: +; X64-NOF16C-NEXT: pushq %rax +; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi +; X64-NOF16C-NEXT: callq ___extendhfsf2 +; X64-NOF16C-NEXT: movss %xmm0, {{[0-9]+}}(%rsp) +; X64-NOF16C-NEXT: flds {{[0-9]+}}(%rsp) +; X64-NOF16C-NEXT: wait +; X64-NOF16C-NEXT: popq %rax +; X64-NOF16C-NEXT: retq +; +; X64-F16C-LABEL: half_to_fp80: +; X64-F16C: ## %bb.0: +; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax +; X64-F16C-NEXT: vmovd %eax, %xmm0 +; X64-F16C-NEXT: vcvtph2ps %xmm0, %xmm0 +; X64-F16C-NEXT: vmovss %xmm0, -{{[0-9]+}}(%rsp) +; X64-F16C-NEXT: flds -{{[0-9]+}}(%rsp) +; X64-F16C-NEXT: wait +; X64-F16C-NEXT: retq + %1 = load half, half* @a, align 2 + %2 = tail call x86_fp80 @llvm.experimental.constrained.fpext.f80.f16(half %1, metadata !"fpexcept.strict") #0 + ret x86_fp80 %2 +} + +define void @float_to_half(float %0) strictfp { +; X32-NOF16C-LABEL: float_to_half: +; X32-NOF16C: ## %bb.0: +; X32-NOF16C-NEXT: subl $12, %esp +; X32-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X32-NOF16C-NEXT: flds {{[0-9]+}}(%esp) +; X32-NOF16C-NEXT: fstps (%esp) +; X32-NOF16C-NEXT: wait +; X32-NOF16C-NEXT: calll ___truncsfhf2 +; X32-NOF16C-NEXT: movw %ax, _a +; X32-NOF16C-NEXT: addl $12, %esp +; X32-NOF16C-NEXT: retl +; +; X32-F16C-LABEL: float_to_half: +; X32-F16C: ## %bb.0: +; X32-F16C-NEXT: subl $12, %esp +; X32-F16C-NEXT: .cfi_def_cfa_offset 16 +; X32-F16C-NEXT: flds {{[0-9]+}}(%esp) +; X32-F16C-NEXT: fstps (%esp) +; X32-F16C-NEXT: wait +; X32-F16C-NEXT: calll ___truncsfhf2 +; X32-F16C-NEXT: movw %ax, _a +; X32-F16C-NEXT: addl $12, %esp +; X32-F16C-NEXT: retl +; +; X64-NOF16C-LABEL: float_to_half: +; X64-NOF16C: ## %bb.0: +; X64-NOF16C-NEXT: pushq %rax +; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X64-NOF16C-NEXT: callq ___truncsfhf2 +; X64-NOF16C-NEXT: movw %ax, {{.*}}(%rip) +; X64-NOF16C-NEXT: popq %rax +; X64-NOF16C-NEXT: retq +; +; X64-F16C-LABEL: float_to_half: +; X64-F16C: ## %bb.0: +; X64-F16C-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X64-F16C-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; X64-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; X64-F16C-NEXT: vpextrw $0, %xmm0, {{.*}}(%rip) +; X64-F16C-NEXT: retq + %2 = tail call half @llvm.experimental.constrained.fptrunc.f16.f32(float %0, metadata !"round.tonearest", metadata !"fpexcept.strict") #0 + store half %2, half* @a, align 2 + ret void +} + +define void @double_to_half(double %0) strictfp { +; X32-NOF16C-LABEL: double_to_half: +; X32-NOF16C: ## %bb.0: +; X32-NOF16C-NEXT: subl $12, %esp +; X32-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X32-NOF16C-NEXT: fldl {{[0-9]+}}(%esp) +; X32-NOF16C-NEXT: fstpl (%esp) +; X32-NOF16C-NEXT: wait +; X32-NOF16C-NEXT: calll ___truncdfhf2 +; X32-NOF16C-NEXT: movw %ax, _a +; X32-NOF16C-NEXT: addl $12, %esp +; X32-NOF16C-NEXT: retl +; +; X32-F16C-LABEL: double_to_half: +; X32-F16C: ## %bb.0: +; X32-F16C-NEXT: subl $12, %esp +; X32-F16C-NEXT: .cfi_def_cfa_offset 16 +; X32-F16C-NEXT: fldl {{[0-9]+}}(%esp) +; X32-F16C-NEXT: fstpl (%esp) +; X32-F16C-NEXT: wait +; X32-F16C-NEXT: calll ___truncdfhf2 +; X32-F16C-NEXT: movw %ax, _a +; X32-F16C-NEXT: addl $12, %esp +; X32-F16C-NEXT: retl +; +; X64-NOF16C-LABEL: double_to_half: +; X64-NOF16C: ## %bb.0: +; X64-NOF16C-NEXT: pushq %rax +; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X64-NOF16C-NEXT: callq ___truncdfhf2 +; X64-NOF16C-NEXT: movw %ax, {{.*}}(%rip) +; X64-NOF16C-NEXT: popq %rax +; X64-NOF16C-NEXT: retq +; +; X64-F16C-LABEL: double_to_half: +; X64-F16C: ## %bb.0: +; X64-F16C-NEXT: pushq %rax +; X64-F16C-NEXT: .cfi_def_cfa_offset 16 +; X64-F16C-NEXT: callq ___truncdfhf2 +; X64-F16C-NEXT: movw %ax, {{.*}}(%rip) +; X64-F16C-NEXT: popq %rax +; X64-F16C-NEXT: retq + %2 = tail call half @llvm.experimental.constrained.fptrunc.f16.f64(double %0, metadata !"round.tonearest", metadata !"fpexcept.strict") #0 + store half %2, half* @a, align 2 + ret void +} + +define void @fp80_to_half(x86_fp80 %0) strictfp { +; X32-NOF16C-LABEL: fp80_to_half: +; X32-NOF16C: ## %bb.0: +; X32-NOF16C-NEXT: subl $28, %esp +; X32-NOF16C-NEXT: .cfi_def_cfa_offset 32 +; X32-NOF16C-NEXT: fldt {{[0-9]+}}(%esp) +; X32-NOF16C-NEXT: fstpt (%esp) +; X32-NOF16C-NEXT: wait +; X32-NOF16C-NEXT: calll ___truncxfhf2 +; X32-NOF16C-NEXT: movw %ax, _a +; X32-NOF16C-NEXT: addl $28, %esp +; X32-NOF16C-NEXT: retl +; +; X32-F16C-LABEL: fp80_to_half: +; X32-F16C: ## %bb.0: +; X32-F16C-NEXT: subl $28, %esp +; X32-F16C-NEXT: .cfi_def_cfa_offset 32 +; X32-F16C-NEXT: fldt {{[0-9]+}}(%esp) +; X32-F16C-NEXT: fstpt (%esp) +; X32-F16C-NEXT: wait +; X32-F16C-NEXT: calll ___truncxfhf2 +; X32-F16C-NEXT: movw %ax, _a +; X32-F16C-NEXT: addl $28, %esp +; X32-F16C-NEXT: retl +; +; X64-NOF16C-LABEL: fp80_to_half: +; X64-NOF16C: ## %bb.0: +; X64-NOF16C-NEXT: subq $24, %rsp +; X64-NOF16C-NEXT: .cfi_def_cfa_offset 32 +; X64-NOF16C-NEXT: fldt {{[0-9]+}}(%rsp) +; X64-NOF16C-NEXT: fstpt (%rsp) +; X64-NOF16C-NEXT: wait +; X64-NOF16C-NEXT: callq ___truncxfhf2 +; X64-NOF16C-NEXT: movw %ax, {{.*}}(%rip) +; X64-NOF16C-NEXT: addq $24, %rsp +; X64-NOF16C-NEXT: retq +; +; X64-F16C-LABEL: fp80_to_half: +; X64-F16C: ## %bb.0: +; X64-F16C-NEXT: subq $24, %rsp +; X64-F16C-NEXT: .cfi_def_cfa_offset 32 +; X64-F16C-NEXT: fldt {{[0-9]+}}(%rsp) +; X64-F16C-NEXT: fstpt (%rsp) +; X64-F16C-NEXT: wait +; X64-F16C-NEXT: callq ___truncxfhf2 +; X64-F16C-NEXT: movw %ax, {{.*}}(%rip) +; X64-F16C-NEXT: addq $24, %rsp +; X64-F16C-NEXT: retq + %2 = tail call half @llvm.experimental.constrained.fptrunc.f16.f80(x86_fp80 %0, metadata !"round.tonearest", metadata !"fpexcept.strict") #0 + store half %2, half* @a, align 2 + ret void +} + +define void @add() strictfp { +; X32-NOF16C-LABEL: add: +; X32-NOF16C: ## %bb.0: +; X32-NOF16C-NEXT: subl $12, %esp +; X32-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X32-NOF16C-NEXT: movzwl _a, %eax +; X32-NOF16C-NEXT: movl %eax, (%esp) +; X32-NOF16C-NEXT: calll ___extendhfsf2 +; X32-NOF16C-NEXT: fstps {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill +; X32-NOF16C-NEXT: wait +; X32-NOF16C-NEXT: movzwl _b, %eax +; X32-NOF16C-NEXT: movl %eax, (%esp) +; X32-NOF16C-NEXT: calll ___extendhfsf2 +; X32-NOF16C-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Reload +; X32-NOF16C-NEXT: faddp %st, %st(1) +; X32-NOF16C-NEXT: fstps (%esp) +; X32-NOF16C-NEXT: wait +; X32-NOF16C-NEXT: calll ___truncsfhf2 +; X32-NOF16C-NEXT: movw %ax, _c +; X32-NOF16C-NEXT: addl $12, %esp +; X32-NOF16C-NEXT: retl +; +; X32-F16C-LABEL: add: +; X32-F16C: ## %bb.0: +; X32-F16C-NEXT: subl $12, %esp +; X32-F16C-NEXT: .cfi_def_cfa_offset 16 +; X32-F16C-NEXT: movzwl _a, %eax +; X32-F16C-NEXT: movl %eax, (%esp) +; X32-F16C-NEXT: calll ___extendhfsf2 +; X32-F16C-NEXT: fstps {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill +; X32-F16C-NEXT: wait +; X32-F16C-NEXT: movzwl _b, %eax +; X32-F16C-NEXT: movl %eax, (%esp) +; X32-F16C-NEXT: calll ___extendhfsf2 +; X32-F16C-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Reload +; X32-F16C-NEXT: faddp %st, %st(1) +; X32-F16C-NEXT: fstps (%esp) +; X32-F16C-NEXT: wait +; X32-F16C-NEXT: calll ___truncsfhf2 +; X32-F16C-NEXT: movw %ax, _c +; X32-F16C-NEXT: addl $12, %esp +; X32-F16C-NEXT: retl +; +; X64-NOF16C-LABEL: add: +; X64-NOF16C: ## %bb.0: +; X64-NOF16C-NEXT: pushq %rax +; X64-NOF16C-NEXT: .cfi_def_cfa_offset 16 +; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi +; X64-NOF16C-NEXT: callq ___extendhfsf2 +; X64-NOF16C-NEXT: movss %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill +; X64-NOF16C-NEXT: movzwl {{.*}}(%rip), %edi +; X64-NOF16C-NEXT: callq ___extendhfsf2 +; X64-NOF16C-NEXT: addss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 4-byte Folded Reload +; X64-NOF16C-NEXT: callq ___truncsfhf2 +; X64-NOF16C-NEXT: movw %ax, {{.*}}(%rip) +; X64-NOF16C-NEXT: popq %rax +; X64-NOF16C-NEXT: retq +; +; X64-F16C-LABEL: add: +; X64-F16C: ## %bb.0: +; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax +; X64-F16C-NEXT: vmovd %eax, %xmm0 +; X64-F16C-NEXT: vcvtph2ps %xmm0, %xmm0 +; X64-F16C-NEXT: movzwl {{.*}}(%rip), %eax +; X64-F16C-NEXT: vmovd %eax, %xmm1 +; X64-F16C-NEXT: vcvtph2ps %xmm1, %xmm1 +; X64-F16C-NEXT: vaddss %xmm1, %xmm0, %xmm0 +; X64-F16C-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; X64-F16C-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; X64-F16C-NEXT: vcvtps2ph $4, %xmm0, %xmm0 +; X64-F16C-NEXT: vpextrw $0, %xmm0, {{.*}}(%rip) +; X64-F16C-NEXT: retq + %1 = load half, half* @a, align 2 + %2 = tail call float @llvm.experimental.constrained.fpext.f32.f16(half %1, metadata !"fpexcept.strict") #0 + %3 = load half, half* @b, align 2 + %4 = tail call float @llvm.experimental.constrained.fpext.f32.f16(half %3, metadata !"fpexcept.strict") #0 + %5 = tail call float @llvm.experimental.constrained.fadd.f32(float %2, float %4, metadata !"round.tonearest", metadata !"fpexcept.strict") #0 + %6 = tail call half @llvm.experimental.constrained.fptrunc.f16.f32(float %5, metadata !"round.tonearest", metadata !"fpexcept.strict") #0 + store half %6, half* @c, align 2 + ret void +} + +declare float @llvm.experimental.constrained.fpext.f32.f16(half, metadata) +declare double @llvm.experimental.constrained.fpext.f64.f16(half, metadata) +declare x86_fp80 @llvm.experimental.constrained.fpext.f80.f16(half, metadata) +declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) +declare half @llvm.experimental.constrained.fptrunc.f16.f32(float, metadata, metadata) +declare half @llvm.experimental.constrained.fptrunc.f16.f64(double, metadata, metadata) +declare half @llvm.experimental.constrained.fptrunc.f16.f80(x86_fp80, metadata, metadata) + +attributes #0 = { strictfp } + -- GitLab From 477c09043e654bc154fce6e6b013f8f91fb96f05 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Wed, 12 Feb 2020 07:57:00 +0100 Subject: [PATCH 124/142] [lldb][NFC] Remove eCustomCompletion mode It's not used by anyone. Also if something implements its own completion it could just not call the method instead of having a parameter that makes the function a no-op. --- lldb/source/Commands/CommandCompletions.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/lldb/source/Commands/CommandCompletions.cpp b/lldb/source/Commands/CommandCompletions.cpp index 2ced56f90178..0e35e0d1123f 100644 --- a/lldb/source/Commands/CommandCompletions.cpp +++ b/lldb/source/Commands/CommandCompletions.cpp @@ -29,7 +29,6 @@ using namespace lldb_private; CommandCompletions::CommonCompletionElement CommandCompletions::g_common_completions[] = { - {eCustomCompletion, nullptr}, {eSourceFileCompletion, CommandCompletions::SourceFiles}, {eDiskFileCompletion, CommandCompletions::DiskFiles}, {eDiskDirectoryCompletion, CommandCompletions::DiskDirectories}, @@ -47,9 +46,6 @@ bool CommandCompletions::InvokeCommonCompletionCallbacks( CompletionRequest &request, SearchFilter *searcher) { bool handled = false; - if (completion_mask & eCustomCompletion) - return false; - for (int i = 0;; i++) { if (g_common_completions[i].type == eNoCompletion) break; -- GitLab From 42a16dacda41be13ccd57b55fef196ca8664b11d Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Wed, 12 Feb 2020 09:01:30 +0100 Subject: [PATCH 125/142] [VE] Bit operator isel Summary: Isel and tests for bswap,brev,ctpop,ctlz,ctty,rotl,rotr Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D74304 --- llvm/lib/Target/VE/VEISelLowering.cpp | 19 ++++- llvm/lib/Target/VE/VEInstrInfo.td | 58 +++++++++++++++ llvm/test/CodeGen/VE/bitreverse.ll | 100 ++++++++++++++++++++++++++ llvm/test/CodeGen/VE/bswap.ll | 71 ++++++++++++++++++ llvm/test/CodeGen/VE/ctlz.ll | 54 ++++++++++++++ llvm/test/CodeGen/VE/ctpop.ll | 54 ++++++++++++++ llvm/test/CodeGen/VE/cttz.ll | 63 ++++++++++++++++ llvm/test/CodeGen/VE/rotl.ll | 37 ++++++++++ llvm/test/CodeGen/VE/rotr.ll | 36 ++++++++++ 9 files changed, 490 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/VE/bitreverse.ll create mode 100644 llvm/test/CodeGen/VE/bswap.ll create mode 100644 llvm/test/CodeGen/VE/ctlz.ll create mode 100644 llvm/test/CodeGen/VE/ctpop.ll create mode 100644 llvm/test/CodeGen/VE/cttz.ll create mode 100644 llvm/test/CodeGen/VE/rotl.ll create mode 100644 llvm/test/CodeGen/VE/rotr.ll diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index 92d0fc2419d4..e0411dae1727 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -556,13 +556,28 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM, setOperationAction(ISD::VAEND, MVT::Other, Expand); /// } VAARG handling - // VE has no REM or DIVREM operations. - for (MVT IntVT : MVT::integer_valuetypes()) { + /// Int Ops { + for (MVT IntVT : {MVT::i32, MVT::i64}) { + // VE has no REM or DIVREM operations. setOperationAction(ISD::UREM, IntVT, Expand); setOperationAction(ISD::SREM, IntVT, Expand); setOperationAction(ISD::SDIVREM, IntVT, Expand); setOperationAction(ISD::UDIVREM, IntVT, Expand); + + setOperationAction(ISD::CTTZ, IntVT, Expand); + setOperationAction(ISD::ROTL, IntVT, Expand); + setOperationAction(ISD::ROTR, IntVT, Expand); + + // Use isel patterns for i32 and i64 + setOperationAction(ISD::BSWAP, IntVT, Legal); + setOperationAction(ISD::CTLZ, IntVT, Legal); + setOperationAction(ISD::CTPOP, IntVT, Legal); + + // Use isel patterns for i64, Promote i32 + LegalizeAction Act = (IntVT == MVT::i32) ? Promote : Legal; + setOperationAction(ISD::BITREVERSE, IntVT, Act); } + /// } Int Ops /// Conversion { // VE doesn't have instructions for fp<->uint, so expand them by llvm diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td index a64fa5f54547..f788b3232f7e 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -533,6 +533,41 @@ multiclass RRCMOVmopc, } } +// Multiclass for RR type instructions with only 2 operands +// Used by pcnt, brv +let hasSideEffects = 0 in +multiclass RRI2mopc, RegisterClass RC, ValueType Ty, + Operand immOp2, SDPatternOperator OpNode=null_frag> { + def r : RR< + opc, (outs RC:$sx), (ins RC:$sz), + !strconcat(opcStr, " $sx, $sz"), + [(set Ty:$sx, (OpNode Ty:$sz))]> { + let cy = 1; + let cz = 1; + } + def i : RR< + opc, (outs RC:$sx), (ins RC:$sz), + !strconcat(opcStr, " $sx, $sz"), + [(set Ty:$sx, (OpNode Ty:$sz))]> { + let cy = 0; + let cz = 1; + } + def m0 : RR< + opc, (outs RC:$sx), (ins immOp2:$sz), + !strconcat(opcStr, " $sx, (${sz})0")> { + let cy = 1; + let cz = 0; + let sz{6} = 1; + } + def m1 : RR< + opc, (outs RC:$sx), (ins immOp2:$sz), + !strconcat(opcStr, " $sx, (${sz})1")> { + let cy = 1; + let cz = 0; + } +} + + // Branch multiclass let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in multiclass BCRm opc, @@ -760,6 +795,16 @@ let cx = 0 in { } } +// Bits operations + +let cx = 0 in { + defm PCNT : RRI2m<"pcnt", 0x38, I64, i64, uimm6Op64, ctpop>; + defm BRV : RRI2m<"brv", 0x39, I64, i64, uimm6Op64, bitreverse>; + defm LDZ : RRI2m<"ldz", 0x67, I64, i64, uimm6Op64, ctlz>; + defm BSWP : RRIm<"bswp", 0x2B, I64, i64, simm7Op64, uimm6Op64>; +} + + // 5.3.2.4 Shift Instructions @@ -1426,6 +1471,19 @@ def : Pat<(f32 (bitconvert i32:$op)), (EXTRACT_SUBREG (SLLri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $op, sub_i32), 32), sub_f32)>; +// Bits operations pattern matchings. +def : Pat<(i32 (ctpop i32:$src)), + (EXTRACT_SUBREG (PCNTr (ANDrm0 (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), $src, sub_i32), 32)), sub_i32)>; +def : Pat<(i32 (ctlz i32:$src)), + (EXTRACT_SUBREG (LDZr (SLLri (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), $src, sub_i32), 32)), sub_i32)>; +def : Pat<(i64 (bswap i64:$src)), + (BSWPri $src, 0)>; +def : Pat<(i32 (bswap i32:$src)), + (EXTRACT_SUBREG (BSWPri (INSERT_SUBREG + (i64 (IMPLICIT_DEF)), $src, sub_i32), 1), sub_i32)>; + // Several special pattern matches to optimize code def : Pat<(i32 (and i32:$lhs, 0xff)), diff --git a/llvm/test/CodeGen/VE/bitreverse.ll b/llvm/test/CodeGen/VE/bitreverse.ll new file mode 100644 index 000000000000..fce969af657e --- /dev/null +++ b/llvm/test/CodeGen/VE/bitreverse.ll @@ -0,0 +1,100 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @func1(i64 %p) { +; CHECK-LABEL: func1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: brv %s0, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i64 @llvm.bitreverse.i64(i64 %p) + ret i64 %r +} + +declare i64 @llvm.bitreverse.i64(i64) + +define i32 @func2(i32 %p) { +; CHECK-LABEL: func2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: brv %s0, %s0 +; CHECK-NEXT: srl %s0, %s0, 32 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i32 @llvm.bitreverse.i32(i32 %p) + ret i32 %r +} + +declare i32 @llvm.bitreverse.i32(i32) + +define signext i16 @func3(i16 signext %p) { +; CHECK-LABEL: func3: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: brv %s0, %s0 +; CHECK-NEXT: sra.l %s0, %s0, 48 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i16 @llvm.bitreverse.i16(i16 %p) + ret i16 %r +} + +declare i16 @llvm.bitreverse.i16(i16) + +define signext i8 @func4(i8 signext %p) { +; CHECK-LABEL: func4: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: brv %s0, %s0 +; CHECK-NEXT: sra.l %s0, %s0, 56 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i8 @llvm.bitreverse.i8(i8 %p) + ret i8 %r +} + +declare i8 @llvm.bitreverse.i8(i8) + +define i64 @func5(i64 %p) { +; CHECK-LABEL: func5: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: brv %s0, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i64 @llvm.bitreverse.i64(i64 %p) + ret i64 %r +} + +define i32 @func6(i32 %p) { +; CHECK-LABEL: func6: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: brv %s0, %s0 +; CHECK-NEXT: srl %s0, %s0, 32 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i32 @llvm.bitreverse.i32(i32 %p) + ret i32 %r +} + +define zeroext i16 @func7(i16 zeroext %p) { +; CHECK-LABEL: func7: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: brv %s0, %s0 +; CHECK-NEXT: srl %s0, %s0, 48 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i16 @llvm.bitreverse.i16(i16 %p) + ret i16 %r +} + +define zeroext i8 @func8(i8 zeroext %p) { +; CHECK-LABEL: func8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: brv %s0, %s0 +; CHECK-NEXT: srl %s0, %s0, 56 +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i8 @llvm.bitreverse.i8(i8 %p) + ret i8 %r +} + diff --git a/llvm/test/CodeGen/VE/bswap.ll b/llvm/test/CodeGen/VE/bswap.ll new file mode 100644 index 000000000000..274085462856 --- /dev/null +++ b/llvm/test/CodeGen/VE/bswap.ll @@ -0,0 +1,71 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @func1(i64 %p) { +; CHECK-LABEL: func1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: bswp %s0, %s0, 0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i64 @llvm.bswap.i64(i64 %p) + ret i64 %r +} + +declare i64 @llvm.bswap.i64(i64) + +define i32 @func2(i32 %p) { +; CHECK-LABEL: func2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: bswp %s0, %s0, 1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i32 @llvm.bswap.i32(i32 %p) + ret i32 %r +} + +declare i32 @llvm.bswap.i32(i32) + +define signext i16 @func3(i16 signext %p) { +; CHECK-LABEL: func3: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: bswp %s0, %s0, 1 +; CHECK-NEXT: sra.w.sx %s0, %s0, 16 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i16 @llvm.bswap.i16(i16 %p) + ret i16 %r +} + +declare i16 @llvm.bswap.i16(i16) + +define i64 @func4(i64 %p) { +; CHECK-LABEL: func4: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: bswp %s0, %s0, 0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i64 @llvm.bswap.i64(i64 %p) + ret i64 %r +} + +define i32 @func5(i32 %p) { +; CHECK-LABEL: func5: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: bswp %s0, %s0, 1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i32 @llvm.bswap.i32(i32 %p) + ret i32 %r +} + +define zeroext i16 @func6(i16 zeroext %p) { +; CHECK-LABEL: func6: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: bswp %s0, %s0, 1 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: srl %s0, %s0, 16 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i16 @llvm.bswap.i16(i16 %p) + ret i16 %r +} diff --git a/llvm/test/CodeGen/VE/ctlz.ll b/llvm/test/CodeGen/VE/ctlz.ll new file mode 100644 index 000000000000..0d0b2c3f6b0a --- /dev/null +++ b/llvm/test/CodeGen/VE/ctlz.ll @@ -0,0 +1,54 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @func1(i64 %p) { +; CHECK-LABEL: func1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: ldz %s0, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i64 @llvm.ctlz.i64(i64 %p, i1 true) + ret i64 %r +} + +declare i64 @llvm.ctlz.i64(i64, i1) + +define i32 @func2(i32 %p) { +; CHECK-LABEL: func2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: sll %s0, %s0, 32 +; CHECK-NEXT: ldz %s0, %s0 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i32 @llvm.ctlz.i32(i32 %p, i1 true) + ret i32 %r +} + +declare i32 @llvm.ctlz.i32(i32, i1) + +define i16 @func3(i16 %p) { +; CHECK-LABEL: func3: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: and %s0, %s0, (48)0 +; CHECK-NEXT: sll %s0, %s0, 32 +; CHECK-NEXT: ldz %s0, %s0 +; CHECK-NEXT: lea %s0, -16(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i16 @llvm.ctlz.i16(i16 %p, i1 true) + ret i16 %r +} + +declare i16 @llvm.ctlz.i16(i16, i1) + +define i8 @func4(i8 %p) { +; CHECK-LABEL: func4: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: and %s0, %s0, (56)0 +; CHECK-NEXT: sll %s0, %s0, 32 +; CHECK-NEXT: ldz %s0, %s0 +; CHECK-NEXT: lea %s0, -24(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i8 @llvm.ctlz.i8(i8 %p, i1 true) + ret i8 %r +} + +declare i8 @llvm.ctlz.i8(i8, i1) diff --git a/llvm/test/CodeGen/VE/ctpop.ll b/llvm/test/CodeGen/VE/ctpop.ll new file mode 100644 index 000000000000..3d25909ab25c --- /dev/null +++ b/llvm/test/CodeGen/VE/ctpop.ll @@ -0,0 +1,54 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @func1(i64 %p) { +; CHECK-LABEL: func1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: pcnt %s0, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i64 @llvm.ctpop.i64(i64 %p) + ret i64 %r +} + +declare i64 @llvm.ctpop.i64(i64 %p) + +define i32 @func2(i32 %p) { +; CHECK-LABEL: func2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: pcnt %s0, %s0 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i32 @llvm.ctpop.i32(i32 %p) + ret i32 %r +} + +declare i32 @llvm.ctpop.i32(i32 %p) + +define i16 @func3(i16 %p) { +; CHECK-LABEL: func3: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: and %s0, %s0, (48)0 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: pcnt %s0, %s0 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i16 @llvm.ctpop.i16(i16 %p) + ret i16 %r +} + +declare i16 @llvm.ctpop.i16(i16 %p) + +define i8 @func4(i8 %p) { +; CHECK-LABEL: func4: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: and %s0, %s0, (56)0 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: pcnt %s0, %s0 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i8 @llvm.ctpop.i8(i8 %p) + ret i8 %r +} + +declare i8 @llvm.ctpop.i8(i8) diff --git a/llvm/test/CodeGen/VE/cttz.ll b/llvm/test/CodeGen/VE/cttz.ll new file mode 100644 index 000000000000..0b0399523ab7 --- /dev/null +++ b/llvm/test/CodeGen/VE/cttz.ll @@ -0,0 +1,63 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @func1(i64 %p) { +; CHECK-LABEL: func1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s1, -1(%s0) +; CHECK-NEXT: xor %s0, -1, %s0 +; CHECK-NEXT: and %s0, %s0, %s1 +; CHECK-NEXT: pcnt %s0, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i64 @llvm.cttz.i64(i64 %p, i1 true) + ret i64 %r +} + +declare i64 @llvm.cttz.i64(i64, i1) + +define i32 @func2(i32 %p) { +; CHECK-LABEL: func2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s1, -1(%s0) +; CHECK-NEXT: xor %s0, -1, %s0 +; CHECK-NEXT: and %s0, %s0, %s1 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: pcnt %s0, %s0 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i32 @llvm.cttz.i32(i32 %p, i1 true) + ret i32 %r +} + +declare i32 @llvm.cttz.i32(i32, i1) + +define i16 @func3(i16 %p) { +; CHECK-LABEL: func3: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s1, -1(%s0) +; CHECK-NEXT: xor %s0, -1, %s0 +; CHECK-NEXT: and %s0, %s0, %s1 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: pcnt %s0, %s0 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i16 @llvm.cttz.i16(i16 %p, i1 true) + ret i16 %r +} + +declare i16 @llvm.cttz.i16(i16, i1) + +define i8 @func4(i8 %p) { +; CHECK-LABEL: func4: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s1, -1(%s0) +; CHECK-NEXT: xor %s0, -1, %s0 +; CHECK-NEXT: and %s0, %s0, %s1 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: pcnt %s0, %s0 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %r = tail call i8 @llvm.cttz.i8(i8 %p, i1 true) + ret i8 %r +} + +declare i8 @llvm.cttz.i8(i8, i1) diff --git a/llvm/test/CodeGen/VE/rotl.ll b/llvm/test/CodeGen/VE/rotl.ll new file mode 100644 index 000000000000..e7c498f1d34d --- /dev/null +++ b/llvm/test/CodeGen/VE/rotl.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @func1(i64 %a, i32 %b) { +; CHECK-LABEL: func1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: sll %s2, %s0, %s1 +; CHECK-NEXT: lea %s3, 64 +; CHECK-NEXT: subs.w.sx %s1, %s3, %s1 +; CHECK-NEXT: srl %s0, %s0, %s1 +; CHECK-NEXT: or %s0, %s0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %b64 = zext i32 %b to i64 + %a.sl = shl i64 %a, %b64 + %b.inv = sub nsw i32 64, %b + %b.inv64 = zext i32 %b.inv to i64 + %a.sr = lshr i64 %a, %b.inv64 + %r = or i64 %a.sr, %a.sl + ret i64 %r +} + +define i32 @func2(i32 %a, i32 %b) { +; CHECK-LABEL: func2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: sla.w.sx %s2, %s0, %s1 +; CHECK-NEXT: subs.w.sx %s1, 32, %s1 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: srl %s0, %s0, %s1 +; CHECK-NEXT: or %s0, %s0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %a.sl = shl i32 %a, %b + %b.inv = sub nsw i32 32, %b + %a.sr = lshr i32 %a, %b.inv + %r = or i32 %a.sr, %a.sl + ret i32 %r +} + diff --git a/llvm/test/CodeGen/VE/rotr.ll b/llvm/test/CodeGen/VE/rotr.ll new file mode 100644 index 000000000000..40734a3d5178 --- /dev/null +++ b/llvm/test/CodeGen/VE/rotr.ll @@ -0,0 +1,36 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i64 @func1(i64 %a, i32 %b) { +; CHECK-LABEL: func1: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: srl %s2, %s0, %s1 +; CHECK-NEXT: lea %s3, 64 +; CHECK-NEXT: subs.w.sx %s1, %s3, %s1 +; CHECK-NEXT: sll %s0, %s0, %s1 +; CHECK-NEXT: or %s0, %s0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %b64 = zext i32 %b to i64 + %a.lr = lshr i64 %a, %b64 + %b.inv = sub nsw i32 64, %b + %b.inv64 = zext i32 %b.inv to i64 + %a.sl = shl i64 %a, %b.inv64 + %r = or i64 %a.sl, %a.lr + ret i64 %r +} + +define i32 @func2(i32 %a, i32 %b) { +; CHECK-LABEL: func2: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: # kill: def $sw0 killed $sw0 def $sx0 +; CHECK-NEXT: and %s2, %s0, (32)0 +; CHECK-NEXT: srl %s2, %s2, %s1 +; CHECK-NEXT: subs.w.sx %s1, 32, %s1 +; CHECK-NEXT: sla.w.sx %s0, %s0, %s1 +; CHECK-NEXT: or %s0, %s0, %s2 +; CHECK-NEXT: or %s11, 0, %s9 + %a.lr = lshr i32 %a, %b + %b.inv = sub nsw i32 32, %b + %a.sl = shl i32 %a, %b.inv + %r = or i32 %a.sl, %a.lr + ret i32 %r +} -- GitLab From 7e5d8a34e341a06a1b8ce221a36146163a00aaa3 Mon Sep 17 00:00:00 2001 From: Alexander Belyaev Date: Wed, 12 Feb 2020 09:04:15 +0100 Subject: [PATCH 126/142] [MLIR] Support memrefs with complex element types. Differential Revision: https://reviews.llvm.org/D74307 --- mlir/lib/IR/StandardTypes.cpp | 6 ++++-- mlir/test/IR/parser.mlir | 10 ++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/mlir/lib/IR/StandardTypes.cpp b/mlir/lib/IR/StandardTypes.cpp index bd12cff65f7e..c4269af9030e 100644 --- a/mlir/lib/IR/StandardTypes.cpp +++ b/mlir/lib/IR/StandardTypes.cpp @@ -333,7 +333,8 @@ MemRefType MemRefType::getImpl(ArrayRef shape, Type elementType, auto *context = elementType.getContext(); // Check that memref is formed from allowed types. - if (!elementType.isIntOrFloat() && !elementType.isa()) + if (!elementType.isIntOrFloat() && !elementType.isa() && + !elementType.isa()) return emitOptionalError(location, "invalid memref element type"), MemRefType(); @@ -411,7 +412,8 @@ LogicalResult UnrankedMemRefType::verifyConstructionInvariants( Optional loc, MLIRContext *context, Type elementType, unsigned memorySpace) { // Check that memref is formed from allowed types. - if (!elementType.isIntOrFloat() && !elementType.isa()) + if (!elementType.isIntOrFloat() && !elementType.isa() && + !elementType.isa()) return emitOptionalError(*loc, "invalid memref element type"); return success(); } diff --git a/mlir/test/IR/parser.mlir b/mlir/test/IR/parser.mlir index b2c93ce15291..71e82b0fe090 100644 --- a/mlir/test/IR/parser.mlir +++ b/mlir/test/IR/parser.mlir @@ -133,6 +133,16 @@ func @memrefs_compose_with_id(memref<2x2xi8, affine_map<(d0, d1) -> (d0, d1)>, // CHECK: func @complex_types(complex) -> complex func @complex_types(complex) -> complex + +// CHECK: func @memref_with_complex_elems(memref<1x?xcomplex>) +func @memref_with_complex_elems(memref<1x?xcomplex>) + +// CHECK: func @memref_with_vector_elems(memref<1x?xvector<10xf32>>) +func @memref_with_vector_elems(memref<1x?xvector<10xf32>>) + +// CHECK: func @unranked_memref_with_complex_elems(memref<*xcomplex>) +func @unranked_memref_with_complex_elems(memref<*xcomplex>) + // CHECK: func @functions((memref<1x?x4x?x?xi32, #map0>, memref<8xi8>) -> (), () -> ()) func @functions((memref<1x?x4x?x?xi32, #map0, 0>, memref<8xi8, #map1, 0>) -> (), ()->()) -- GitLab From 572fc8974277e5def25029219daec20d08f85030 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Wed, 12 Feb 2020 08:56:03 +0100 Subject: [PATCH 127/142] [lldb][NFC] Move all completer subclasses into source file They are all implementation details so let's keep them out of the interface. Also makes this code more readable by keeping these small classes not spread over header and source file. --- .../lldb/Interpreter/CommandCompletions.h | 88 ----- lldb/source/Commands/CommandCompletions.cpp | 362 ++++++++++-------- 2 files changed, 202 insertions(+), 248 deletions(-) diff --git a/lldb/include/lldb/Interpreter/CommandCompletions.h b/lldb/include/lldb/Interpreter/CommandCompletions.h index 39061d9db8bc..c4eb1ae878f4 100644 --- a/lldb/include/lldb/Interpreter/CommandCompletions.h +++ b/lldb/include/lldb/Interpreter/CommandCompletions.h @@ -94,94 +94,6 @@ public: static void VariablePath(CommandInterpreter &interpreter, CompletionRequest &request, SearchFilter *searcher); - // The Completer class is a convenient base class for building searchers that - // go along with the SearchFilter passed to the standard Completer functions. - class Completer : public Searcher { - public: - Completer(CommandInterpreter &interpreter, CompletionRequest &request); - - ~Completer() override; - - CallbackReturn SearchCallback(SearchFilter &filter, SymbolContext &context, - Address *addr) override = 0; - - lldb::SearchDepth GetDepth() override = 0; - - virtual void DoCompletion(SearchFilter *filter) = 0; - - protected: - CommandInterpreter &m_interpreter; - CompletionRequest &m_request; - - private: - DISALLOW_COPY_AND_ASSIGN(Completer); - }; - - // SourceFileCompleter implements the source file completer - class SourceFileCompleter : public Completer { - public: - SourceFileCompleter(CommandInterpreter &interpreter, - CompletionRequest &request); - - lldb::SearchDepth GetDepth() override; - - Searcher::CallbackReturn SearchCallback(SearchFilter &filter, - SymbolContext &context, - Address *addr) override; - - void DoCompletion(SearchFilter *filter) override; - - private: - FileSpecList m_matching_files; - const char *m_file_name; - const char *m_dir_name; - - DISALLOW_COPY_AND_ASSIGN(SourceFileCompleter); - }; - - // ModuleCompleter implements the module completer - class ModuleCompleter : public Completer { - public: - ModuleCompleter(CommandInterpreter &interpreter, - CompletionRequest &request); - - lldb::SearchDepth GetDepth() override; - - Searcher::CallbackReturn SearchCallback(SearchFilter &filter, - SymbolContext &context, - Address *addr) override; - - void DoCompletion(SearchFilter *filter) override; - - private: - const char *m_file_name; - const char *m_dir_name; - - DISALLOW_COPY_AND_ASSIGN(ModuleCompleter); - }; - - // SymbolCompleter implements the symbol completer - class SymbolCompleter : public Completer { - public: - SymbolCompleter(CommandInterpreter &interpreter, - CompletionRequest &request); - - lldb::SearchDepth GetDepth() override; - - Searcher::CallbackReturn SearchCallback(SearchFilter &filter, - SymbolContext &context, - Address *addr) override; - - void DoCompletion(SearchFilter *filter) override; - - private: - RegularExpression m_regex; - typedef std::set collection; - collection m_match_set; - - DISALLOW_COPY_AND_ASSIGN(SymbolCompleter); - }; - private: static CommonCompletionElement g_common_completions[]; }; diff --git a/lldb/source/Commands/CommandCompletions.cpp b/lldb/source/Commands/CommandCompletions.cpp index 0e35e0d1123f..31c8e6ab17cc 100644 --- a/lldb/source/Commands/CommandCompletions.cpp +++ b/lldb/source/Commands/CommandCompletions.cpp @@ -59,6 +59,208 @@ bool CommandCompletions::InvokeCommonCompletionCallbacks( return handled; } +namespace { +// The Completer class is a convenient base class for building searchers that +// go along with the SearchFilter passed to the standard Completer functions. +class Completer : public Searcher { +public: + Completer(CommandInterpreter &interpreter, CompletionRequest &request) + : m_interpreter(interpreter), m_request(request) {} + + ~Completer() override = default; + + CallbackReturn SearchCallback(SearchFilter &filter, SymbolContext &context, + Address *addr) override = 0; + + lldb::SearchDepth GetDepth() override = 0; + + virtual void DoCompletion(SearchFilter *filter) = 0; + +protected: + CommandInterpreter &m_interpreter; + CompletionRequest &m_request; + +private: + DISALLOW_COPY_AND_ASSIGN(Completer); +}; +} // namespace + +// SourceFileCompleter implements the source file completer +namespace { +class SourceFileCompleter : public Completer { +public: + SourceFileCompleter(CommandInterpreter &interpreter, + CompletionRequest &request) + : Completer(interpreter, request), m_matching_files() { + FileSpec partial_spec(m_request.GetCursorArgumentPrefix()); + m_file_name = partial_spec.GetFilename().GetCString(); + m_dir_name = partial_spec.GetDirectory().GetCString(); + } + + lldb::SearchDepth GetDepth() override { return lldb::eSearchDepthCompUnit; } + + Searcher::CallbackReturn SearchCallback(SearchFilter &filter, + SymbolContext &context, + Address *addr) override { + if (context.comp_unit != nullptr) { + const char *cur_file_name = + context.comp_unit->GetPrimaryFile().GetFilename().GetCString(); + const char *cur_dir_name = + context.comp_unit->GetPrimaryFile().GetDirectory().GetCString(); + + bool match = false; + if (m_file_name && cur_file_name && + strstr(cur_file_name, m_file_name) == cur_file_name) + match = true; + + if (match && m_dir_name && cur_dir_name && + strstr(cur_dir_name, m_dir_name) != cur_dir_name) + match = false; + + if (match) { + m_matching_files.AppendIfUnique(context.comp_unit->GetPrimaryFile()); + } + } + return Searcher::eCallbackReturnContinue; + } + + void DoCompletion(SearchFilter *filter) override { + filter->Search(*this); + // Now convert the filelist to completions: + for (size_t i = 0; i < m_matching_files.GetSize(); i++) { + m_request.AddCompletion( + m_matching_files.GetFileSpecAtIndex(i).GetFilename().GetCString()); + } + } + +private: + FileSpecList m_matching_files; + const char *m_file_name; + const char *m_dir_name; + + DISALLOW_COPY_AND_ASSIGN(SourceFileCompleter); +}; +} // namespace + +static bool regex_chars(const char comp) { + return llvm::StringRef("[](){}+.*|^$\\?").contains(comp); +} + +namespace { +class SymbolCompleter : public Completer { + +public: + SymbolCompleter(CommandInterpreter &interpreter, CompletionRequest &request) + : Completer(interpreter, request) { + std::string regex_str; + if (!m_request.GetCursorArgumentPrefix().empty()) { + regex_str.append("^"); + regex_str.append(std::string(m_request.GetCursorArgumentPrefix())); + } else { + // Match anything since the completion string is empty + regex_str.append("."); + } + std::string::iterator pos = + find_if(regex_str.begin() + 1, regex_str.end(), regex_chars); + while (pos < regex_str.end()) { + pos = regex_str.insert(pos, '\\'); + pos = find_if(pos + 2, regex_str.end(), regex_chars); + } + m_regex = RegularExpression(regex_str); + } + + lldb::SearchDepth GetDepth() override { return lldb::eSearchDepthModule; } + + Searcher::CallbackReturn SearchCallback(SearchFilter &filter, + SymbolContext &context, + Address *addr) override { + if (context.module_sp) { + SymbolContextList sc_list; + const bool include_symbols = true; + const bool include_inlines = true; + context.module_sp->FindFunctions(m_regex, include_symbols, + include_inlines, sc_list); + + SymbolContext sc; + // Now add the functions & symbols to the list - only add if unique: + for (uint32_t i = 0; i < sc_list.GetSize(); i++) { + if (sc_list.GetContextAtIndex(i, sc)) { + ConstString func_name = sc.GetFunctionName(Mangled::ePreferDemangled); + // Ensure that the function name matches the regex. This is more than + // a sanity check. It is possible that the demangled function name + // does not start with the prefix, for example when it's in an + // anonymous namespace. + if (!func_name.IsEmpty() && m_regex.Execute(func_name.GetStringRef())) + m_match_set.insert(func_name); + } + } + } + return Searcher::eCallbackReturnContinue; + } + + void DoCompletion(SearchFilter *filter) override { + filter->Search(*this); + collection::iterator pos = m_match_set.begin(), end = m_match_set.end(); + for (pos = m_match_set.begin(); pos != end; pos++) + m_request.AddCompletion((*pos).GetCString()); + } + +private: + RegularExpression m_regex; + typedef std::set collection; + collection m_match_set; + + DISALLOW_COPY_AND_ASSIGN(SymbolCompleter); +}; +} // namespace + +namespace { +class ModuleCompleter : public Completer { +public: + ModuleCompleter(CommandInterpreter &interpreter, CompletionRequest &request) + : Completer(interpreter, request) { + FileSpec partial_spec(m_request.GetCursorArgumentPrefix()); + m_file_name = partial_spec.GetFilename().GetCString(); + m_dir_name = partial_spec.GetDirectory().GetCString(); + } + + lldb::SearchDepth GetDepth() override { return lldb::eSearchDepthModule; } + + Searcher::CallbackReturn SearchCallback(SearchFilter &filter, + SymbolContext &context, + Address *addr) override { + if (context.module_sp) { + const char *cur_file_name = + context.module_sp->GetFileSpec().GetFilename().GetCString(); + const char *cur_dir_name = + context.module_sp->GetFileSpec().GetDirectory().GetCString(); + + bool match = false; + if (m_file_name && cur_file_name && + strstr(cur_file_name, m_file_name) == cur_file_name) + match = true; + + if (match && m_dir_name && cur_dir_name && + strstr(cur_dir_name, m_dir_name) != cur_dir_name) + match = false; + + if (match) { + m_request.AddCompletion(cur_file_name); + } + } + return Searcher::eCallbackReturnContinue; + } + + void DoCompletion(SearchFilter *filter) override { filter->Search(*this); } + +private: + const char *m_file_name; + const char *m_dir_name; + + DISALLOW_COPY_AND_ASSIGN(ModuleCompleter); +}; +} // namespace + void CommandCompletions::SourceFiles(CommandInterpreter &interpreter, CompletionRequest &request, SearchFilter *searcher) { @@ -317,163 +519,3 @@ void CommandCompletions::VariablePath(CommandInterpreter &interpreter, SearchFilter *searcher) { Variable::AutoComplete(interpreter.GetExecutionContext(), request); } - -CommandCompletions::Completer::Completer(CommandInterpreter &interpreter, - CompletionRequest &request) - : m_interpreter(interpreter), m_request(request) {} - -CommandCompletions::Completer::~Completer() = default; - -// SourceFileCompleter - -CommandCompletions::SourceFileCompleter::SourceFileCompleter( - CommandInterpreter &interpreter, CompletionRequest &request) - : CommandCompletions::Completer(interpreter, request), m_matching_files() { - FileSpec partial_spec(m_request.GetCursorArgumentPrefix()); - m_file_name = partial_spec.GetFilename().GetCString(); - m_dir_name = partial_spec.GetDirectory().GetCString(); -} - -lldb::SearchDepth CommandCompletions::SourceFileCompleter::GetDepth() { - return lldb::eSearchDepthCompUnit; -} - -Searcher::CallbackReturn -CommandCompletions::SourceFileCompleter::SearchCallback(SearchFilter &filter, - SymbolContext &context, - Address *addr) { - if (context.comp_unit != nullptr) { - const char *cur_file_name = - context.comp_unit->GetPrimaryFile().GetFilename().GetCString(); - const char *cur_dir_name = - context.comp_unit->GetPrimaryFile().GetDirectory().GetCString(); - - bool match = false; - if (m_file_name && cur_file_name && - strstr(cur_file_name, m_file_name) == cur_file_name) - match = true; - - if (match && m_dir_name && cur_dir_name && - strstr(cur_dir_name, m_dir_name) != cur_dir_name) - match = false; - - if (match) { - m_matching_files.AppendIfUnique(context.comp_unit->GetPrimaryFile()); - } - } - return Searcher::eCallbackReturnContinue; -} - -void CommandCompletions::SourceFileCompleter::DoCompletion( - SearchFilter *filter) { - filter->Search(*this); - // Now convert the filelist to completions: - for (size_t i = 0; i < m_matching_files.GetSize(); i++) { - m_request.AddCompletion( - m_matching_files.GetFileSpecAtIndex(i).GetFilename().GetCString()); - } -} - -// SymbolCompleter - -static bool regex_chars(const char comp) { - return llvm::StringRef("[](){}+.*|^$\\?").contains(comp); -} - -CommandCompletions::SymbolCompleter::SymbolCompleter( - CommandInterpreter &interpreter, CompletionRequest &request) - : CommandCompletions::Completer(interpreter, request) { - std::string regex_str; - if (!m_request.GetCursorArgumentPrefix().empty()) { - regex_str.append("^"); - regex_str.append(std::string(m_request.GetCursorArgumentPrefix())); - } else { - // Match anything since the completion string is empty - regex_str.append("."); - } - std::string::iterator pos = - find_if(regex_str.begin() + 1, regex_str.end(), regex_chars); - while (pos < regex_str.end()) { - pos = regex_str.insert(pos, '\\'); - pos = find_if(pos + 2, regex_str.end(), regex_chars); - } - m_regex = RegularExpression(regex_str); -} - -lldb::SearchDepth CommandCompletions::SymbolCompleter::GetDepth() { - return lldb::eSearchDepthModule; -} - -Searcher::CallbackReturn CommandCompletions::SymbolCompleter::SearchCallback( - SearchFilter &filter, SymbolContext &context, Address *addr) { - if (context.module_sp) { - SymbolContextList sc_list; - const bool include_symbols = true; - const bool include_inlines = true; - context.module_sp->FindFunctions(m_regex, include_symbols, include_inlines, - sc_list); - - SymbolContext sc; - // Now add the functions & symbols to the list - only add if unique: - for (uint32_t i = 0; i < sc_list.GetSize(); i++) { - if (sc_list.GetContextAtIndex(i, sc)) { - ConstString func_name = sc.GetFunctionName(Mangled::ePreferDemangled); - // Ensure that the function name matches the regex. This is more than a - // sanity check. It is possible that the demangled function name does - // not start with the prefix, for example when it's in an anonymous - // namespace. - if (!func_name.IsEmpty() && m_regex.Execute(func_name.GetStringRef())) - m_match_set.insert(func_name); - } - } - } - return Searcher::eCallbackReturnContinue; -} - -void CommandCompletions::SymbolCompleter::DoCompletion(SearchFilter *filter) { - filter->Search(*this); - collection::iterator pos = m_match_set.begin(), end = m_match_set.end(); - for (pos = m_match_set.begin(); pos != end; pos++) - m_request.AddCompletion((*pos).GetCString()); -} - -// ModuleCompleter -CommandCompletions::ModuleCompleter::ModuleCompleter( - CommandInterpreter &interpreter, CompletionRequest &request) - : CommandCompletions::Completer(interpreter, request) { - FileSpec partial_spec(m_request.GetCursorArgumentPrefix()); - m_file_name = partial_spec.GetFilename().GetCString(); - m_dir_name = partial_spec.GetDirectory().GetCString(); -} - -lldb::SearchDepth CommandCompletions::ModuleCompleter::GetDepth() { - return lldb::eSearchDepthModule; -} - -Searcher::CallbackReturn CommandCompletions::ModuleCompleter::SearchCallback( - SearchFilter &filter, SymbolContext &context, Address *addr) { - if (context.module_sp) { - const char *cur_file_name = - context.module_sp->GetFileSpec().GetFilename().GetCString(); - const char *cur_dir_name = - context.module_sp->GetFileSpec().GetDirectory().GetCString(); - - bool match = false; - if (m_file_name && cur_file_name && - strstr(cur_file_name, m_file_name) == cur_file_name) - match = true; - - if (match && m_dir_name && cur_dir_name && - strstr(cur_dir_name, m_dir_name) != cur_dir_name) - match = false; - - if (match) { - m_request.AddCompletion(cur_file_name); - } - } - return Searcher::eCallbackReturnContinue; -} - -void CommandCompletions::ModuleCompleter::DoCompletion(SearchFilter *filter) { - filter->Search(*this); -} -- GitLab From 07a5b849f7bcd4b99080298e93d05651aaaf4dcb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Fri, 7 Feb 2020 22:08:36 +0100 Subject: [PATCH 128/142] SelectionDAG: Fix bug in ClusterNeighboringLoads Summary: The method attempts to find loads that can be legally clustered by looking for loads consuming the same chain glue token. However, the old code looks at _all_ users of values produced by the chain node -- including uses of the loaded/returned value of volatile loads or atomics. This could lead to circular dependencies which then failed during scheduling. With this change, we filter out users by getResNo, i.e. by which SDValue value they use, to ensure that we only look at users of the chain glue token. This appears to be a rather old bug, which is perhaps surprising. However, the test case is actually quite fragile (i.e., it is hidden by fairly small changes), and the test _must_ use volatile loads for the bug to manifest. Reviewers: arsenm, bogner, craig.topper, foad Subscribers: MatzeB, jvesely, wdng, hiraditya, javed.absar, jfb, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74253 --- .../SelectionDAG/ScheduleDAGSDNodes.cpp | 7 +++-- .../AMDGPU/bug-sdag-scheduler-cycle.ll | 27 +++++++++++++++++++ 2 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index a297db178835..7bded0005a51 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -198,10 +198,10 @@ static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) { /// outputs to ensure they are scheduled together and in order. This /// optimization may benefit some targets by improving cache locality. void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) { - SDNode *Chain = nullptr; + SDValue Chain; unsigned NumOps = Node->getNumOperands(); if (Node->getOperand(NumOps-1).getValueType() == MVT::Other) - Chain = Node->getOperand(NumOps-1).getNode(); + Chain = Node->getOperand(NumOps-1); if (!Chain) return; @@ -234,6 +234,9 @@ void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) { unsigned UseCount = 0; for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end(); I != E && UseCount < 100; ++I, ++UseCount) { + if (I.getUse().getResNo() != Chain.getResNo()) + continue; + SDNode *User = *I; if (User == Node || !Visited.insert(User).second) continue; diff --git a/llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll b/llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll new file mode 100644 index 000000000000..50ba7e19f46e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/bug-sdag-scheduler-cycle.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx1010 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK + +; This used to cause a circular chain dependency during +; SelectionDAG instruction scheduling. + +; CHECK-LABEL: {{^}}_amdgpu_gs_main: +; CHECK: ds_read_b32 +; CHECK: ds_read_b32 +; CHECK: ds_read_b32 +; CHECK: ds_read_b32 +define amdgpu_gs float @_amdgpu_gs_main(i8 addrspace(3)* %arg0, i8 addrspace(3)* %arg1, i8 addrspace(3)* %arg2) #0 { + %tmp0 = bitcast i8 addrspace(3)* %arg0 to i32 addrspace(3)* addrspace(3)* + %tmp = load volatile i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* %tmp0, align 4 + + %tmp3 = load volatile i32, i32 addrspace(3)* %tmp, align 4 + + %tmp4a = bitcast i8 addrspace(3)* %arg1 to i32 addrspace(3)* + %tmp4 = load volatile i32, i32 addrspace(3)* %tmp4a, align 4 + + %tmp7a = getelementptr i32, i32 addrspace(3)* %tmp, i32 8 + %tmp8 = load volatile i32, i32 addrspace(3)* %tmp7a, align 4 + + %tmp9 = add i32 %tmp3, %tmp8 + %tmp10 = add i32 %tmp9, %tmp4 + %tmp14 = bitcast i32 %tmp10 to float + ret float %tmp14 +} -- GitLab From ab2f610f3855b388c46b78be452a49ee491a3951 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nicolai=20H=C3=A4hnle?= Date: Tue, 11 Feb 2020 14:40:00 +0100 Subject: [PATCH 129/142] AMDGPU: llvm.amdgcn.writelane is a source of divergence Summary: Consider: %r = call i32 @llvm.amdgcn.writelane(i32 0, i32 1, i32 2) This produces a value that is 0 on lane 1, and 2 everywhere else; i.e., it is divergent. Reported-by: Marek Olsak Reviewers: arsenm, foad, mareko Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74400 --- llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td | 1 + .../test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td index a7eb081d1a25..103b2bb8a6cc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td @@ -247,6 +247,7 @@ def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; +def : SourceOfDivergence; def : SourceOfDivergence; def : SourceOfDivergence; diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll index 923ce600a8bf..e9c753f027ab 100644 --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll @@ -42,12 +42,20 @@ define amdgpu_kernel void @mov_dpp8(i32 addrspace(1)* %out, i32 %in) #0 { ret void } +; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.writelane(i32 0, i32 1, i32 2) +define amdgpu_kernel void @writelane(i32 addrspace(1)* %out) #0 { + %tmp0 = call i32 @llvm.amdgcn.writelane(i32 0, i32 1, i32 2) + store i32 %tmp0, i32 addrspace(1)* %out + ret void +} + declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #1 declare i32 @llvm.amdgcn.permlane16(i32, i32, i32, i32, i1, i1) #1 declare i32 @llvm.amdgcn.permlanex16(i32, i32, i32, i32, i1, i1) #1 declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #1 declare i32 @llvm.amdgcn.mov.dpp8.i32(i32, i32) #1 declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #1 +declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #1 attributes #0 = { nounwind convergent } attributes #1 = { nounwind readnone convergent } -- GitLab From 6646f315c06c178a23508d4319aa8b322687f5f7 Mon Sep 17 00:00:00 2001 From: Georgii Rymar Date: Tue, 11 Feb 2020 14:13:16 +0300 Subject: [PATCH 130/142] [yaml2obj][test] - Simplify the test: yaml2obj/ELF/call-graph-profile-section.yaml Now with the new functionality that allows creating "defines", it is possible to reduce this test (I tried to find another ones, but seems others were already fixed previously). Differential revision: https://reviews.llvm.org/D74392 --- .../ELF/call-graph-profile-section.yaml | 97 ++++--------------- 1 file changed, 17 insertions(+), 80 deletions(-) diff --git a/llvm/test/tools/yaml2obj/ELF/call-graph-profile-section.yaml b/llvm/test/tools/yaml2obj/ELF/call-graph-profile-section.yaml index 4555bdc656d7..a4ca37bd2aab 100644 --- a/llvm/test/tools/yaml2obj/ELF/call-graph-profile-section.yaml +++ b/llvm/test/tools/yaml2obj/ELF/call-graph-profile-section.yaml @@ -2,14 +2,14 @@ ## Test that the content of SHT_LLVM_CALL_GRAPH_PROFILE sections ## for 32/64-bit little/big endian targets is correct. -# RUN: yaml2obj --docnum=1 %s -o %t.le64 -# RUN: llvm-readobj --elf-cg-profile --sections --section-data %t.le64 | FileCheck %s --check-prefixes=BASIC,BASIC-LE -# RUN: yaml2obj --docnum=2 %s -o %t.be64 -# RUN: llvm-readobj --elf-cg-profile --sections --section-data %t.be64 | FileCheck %s --check-prefixes=BASIC,BASIC-BE -# RUN: yaml2obj --docnum=3 %s -o %t.le32 -# RUN: llvm-readobj --elf-cg-profile --sections --section-data %t.le32 | FileCheck %s --check-prefixes=BASIC,BASIC-LE -# RUN: yaml2obj --docnum=4 %s -o %t.be32 -# RUN: llvm-readobj --elf-cg-profile --sections --section-data %t.be32 | FileCheck %s --check-prefixes=BASIC,BASIC-BE +# RUN: yaml2obj --docnum=1 -D BITS=64 -D ENCODE=LSB %s -o %t.le64 +# RUN: llvm-readobj --elf-cg-profile --sections --section-data %t.le64 | FileCheck %s --check-prefixes=BASIC,BASIC-LE +# RUN: yaml2obj --docnum=1 -D BITS=64 -D ENCODE=MSB %s -o %t.be64 +# RUN: llvm-readobj --elf-cg-profile --sections --section-data %t.be64 | FileCheck %s --check-prefixes=BASIC,BASIC-BE +# RUN: yaml2obj --docnum=1 -D BITS=32 -D ENCODE=LSB %s -o %t.le32 +# RUN: llvm-readobj --elf-cg-profile --sections --section-data %t.le32 | FileCheck %s --check-prefixes=BASIC,BASIC-LE +# RUN: yaml2obj --docnum=1 -D BITS=32 -D ENCODE=MSB %s -o %t.be32 +# RUN: llvm-readobj --elf-cg-profile --sections --section-data %t.be32 | FileCheck %s --check-prefixes=BASIC,BASIC-BE # BASIC: Name: .llvm.call-graph-profile # BASIC-NEXT: Type: SHT_LLVM_CALL_GRAPH_PROFILE @@ -48,13 +48,10 @@ # BASIC-NEXT: } # BASIC-NEXT: ] -## TODO: we should really improve yaml2obj somehow to be able to collapse -## the following four YAML descriptions into a single one. - --- !ELF FileHeader: - Class: ELFCLASS64 - Data: ELFDATA2LSB + Class: ELFCLASS[[BITS]] + Data: ELFDATA2[[ENCODE]] Type: ET_DYN Machine: EM_X86_64 Sections: @@ -71,69 +68,9 @@ Symbols: - Name: foo - Name: bar ---- !ELF -FileHeader: - Class: ELFCLASS64 - Data: ELFDATA2MSB - Type: ET_DYN - Machine: EM_X86_64 -Sections: - - Name: .llvm.call-graph-profile - Type: SHT_LLVM_CALL_GRAPH_PROFILE - Entries: - - From: 1 - To: 2 - Weight: 89 - - From: 2 - To: 1 - Weight: 98 -Symbols: - - Name: foo - - Name: bar - ---- !ELF -FileHeader: - Class: ELFCLASS32 - Data: ELFDATA2LSB - Type: ET_DYN - Machine: EM_386 -Sections: - - Name: .llvm.call-graph-profile - Type: SHT_LLVM_CALL_GRAPH_PROFILE - Entries: - - From: 1 - To: 2 - Weight: 89 - - From: 2 - To: 1 - Weight: 98 -Symbols: - - Name: foo - - Name: bar - ---- !ELF -FileHeader: - Class: ELFCLASS32 - Data: ELFDATA2MSB - Type: ET_DYN - Machine: EM_386 -Sections: - - Name: .llvm.call-graph-profile - Type: SHT_LLVM_CALL_GRAPH_PROFILE - Entries: - - From: 1 - To: 2 - Weight: 89 - - From: 2 - To: 1 - Weight: 98 -Symbols: - - Name: foo - - Name: bar - ## Check we can set arbitrary sh_link and sh_entsize values. ## Check we can specify neither "Content" nor "Entries" tags. -# RUN: yaml2obj --docnum=5 %s -o %t.link +# RUN: yaml2obj --docnum=2 %s -o %t.link # RUN: llvm-readelf --sections %t.link | FileCheck %s --check-prefix=LINK # LINK: [Nr] Name Type Address Off Size ES Flg Lk @@ -157,7 +94,7 @@ Sections: EntSize: 0xFF ## Check we can't specify both "Content" and "Entries" tags. -# RUN: not yaml2obj --docnum=6 %s 2>&1 | FileCheck %s --check-prefix=BOTH +# RUN: not yaml2obj --docnum=3 %s 2>&1 | FileCheck %s --check-prefix=BOTH # BOTH: error: "Entries" and "Content" can't be used together --- !ELF @@ -173,7 +110,7 @@ Sections: Entries: [] ## Check we can refer to symbols by name. -# RUN: yaml2obj --docnum=7 %s -o %t.sym +# RUN: yaml2obj --docnum=4 %s -o %t.sym # RUN: llvm-readobj --elf-cg-profile %t.sym | FileCheck %s --check-prefix=SYMBOL-NAMES # SYMBOL-NAMES: CGProfile [ @@ -213,7 +150,7 @@ Symbols: - Name: 'foo [1]' ## Check we can describe SHT_LLVM_CALL_GRAPH_PROFILE sections using the "Content" tag. -# RUN: yaml2obj --docnum=8 %s -o %t.content +# RUN: yaml2obj --docnum=5 %s -o %t.content # RUN: llvm-readobj --sections --section-data %t.content | FileCheck %s --check-prefix=CONTENT # CONTENT: Name: .llvm.call-graph-profile @@ -233,8 +170,8 @@ Sections: Content: "11223344" ## Check we can't reference unknown symbols by name. -# RUN: not yaml2obj --docnum=9 %s 2>&1 | FileCheck %s --check-prefix=UNKNOWN-NAME -# RUN: not yaml2obj --docnum=10 %s 2>&1 | FileCheck %s --check-prefix=UNKNOWN-NAME +# RUN: not yaml2obj --docnum=6 %s 2>&1 | FileCheck %s --check-prefix=UNKNOWN-NAME +# RUN: not yaml2obj --docnum=7 %s 2>&1 | FileCheck %s --check-prefix=UNKNOWN-NAME # UNKNOWN-NAME: error: unknown symbol referenced: 'bar' by YAML section '.llvm.call-graph-profile' --- !ELF @@ -272,7 +209,7 @@ Symbols: - Name: foo ## Check we can specify arbitrary symbol indexes for an SHT_LLVM_CALL_GRAPH_PROFILE section entry. -# RUN: yaml2obj --docnum=11 %s -o %t.unk +# RUN: yaml2obj --docnum=8 %s -o %t.unk # RUN: llvm-readobj --sections --section-data %t.unk | FileCheck %s --check-prefix=UNKNOWN-INDEX # UNKNOWN-INDEX: Name: .llvm.call-graph-profile -- GitLab From 4617fb0b7fd444dca9bf7612dd632ef3feb61d48 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Wed, 12 Feb 2020 09:10:19 +0100 Subject: [PATCH 131/142] [lldb] Move implementation of GetDisplayName to TypeSystem class CompilerType doesn't implement logic. --- lldb/include/lldb/Symbol/TypeSystem.h | 2 ++ lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h | 4 ++++ lldb/source/Symbol/CompilerType.cpp | 6 +++++- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/lldb/include/lldb/Symbol/TypeSystem.h b/lldb/include/lldb/Symbol/TypeSystem.h index 811b99028f63..188b276b7c48 100644 --- a/lldb/include/lldb/Symbol/TypeSystem.h +++ b/lldb/include/lldb/Symbol/TypeSystem.h @@ -199,6 +199,8 @@ public: virtual ConstString GetTypeName(lldb::opaque_compiler_type_t type) = 0; + virtual ConstString GetDisplayTypeName(lldb::opaque_compiler_type_t type) = 0; + virtual uint32_t GetTypeInfo(lldb::opaque_compiler_type_t type, CompilerType *pointee_or_element_compiler_type) = 0; diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h index db03595e970b..049975a3547b 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h @@ -586,6 +586,10 @@ public: ConstString GetTypeName(lldb::opaque_compiler_type_t type) override; + ConstString GetDisplayTypeName(lldb::opaque_compiler_type_t type) override { + return GetTypeName(type); + } + uint32_t GetTypeInfo(lldb::opaque_compiler_type_t type, CompilerType *pointee_or_element_compiler_type) override; diff --git a/lldb/source/Symbol/CompilerType.cpp b/lldb/source/Symbol/CompilerType.cpp index a0f38981e2db..ba69b6b9f0c2 100644 --- a/lldb/source/Symbol/CompilerType.cpp +++ b/lldb/source/Symbol/CompilerType.cpp @@ -288,7 +288,11 @@ ConstString CompilerType::GetTypeName() const { return ConstString(""); } -ConstString CompilerType::GetDisplayTypeName() const { return GetTypeName(); } +ConstString CompilerType::GetDisplayTypeName() const { + if (IsValid()) + return m_type_system->GetDisplayTypeName(m_type); + return ConstString(""); +} uint32_t CompilerType::GetTypeInfo( CompilerType *pointee_or_element_compiler_type) const { -- GitLab From 9d0956ebd47144a8e8ada237aeb4d2e5118422b6 Mon Sep 17 00:00:00 2001 From: Ehud Katz Date: Wed, 12 Feb 2020 10:42:55 +0200 Subject: [PATCH 132/142] [APFloat] Fix FP remainder operation Reimplement IEEEFloat::remainder() function. Fix PR3359. Differential Revision: https://reviews.llvm.org/D69776 --- llvm/include/llvm/ADT/APFloat.h | 1 + llvm/lib/Support/APFloat.cpp | 148 ++++++++-- llvm/unittests/ADT/APFloatTest.cpp | 438 +++++++++++++++++++++++++++++ 3 files changed, 566 insertions(+), 21 deletions(-) diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h index 0b744267a9ad..ce8fd6536b4b 100644 --- a/llvm/include/llvm/ADT/APFloat.h +++ b/llvm/include/llvm/ADT/APFloat.h @@ -511,6 +511,7 @@ private: opStatus divideSpecials(const IEEEFloat &); opStatus multiplySpecials(const IEEEFloat &); opStatus modSpecials(const IEEEFloat &); + opStatus remainderSpecials(const IEEEFloat&); /// @} diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp index 03f0bb1f705e..54f8f8e4bfdb 100644 --- a/llvm/lib/Support/APFloat.cpp +++ b/llvm/lib/Support/APFloat.cpp @@ -1686,6 +1686,44 @@ IEEEFloat::opStatus IEEEFloat::modSpecials(const IEEEFloat &rhs) { } } +IEEEFloat::opStatus IEEEFloat::remainderSpecials(const IEEEFloat &rhs) { + switch (PackCategoriesIntoKey(category, rhs.category)) { + default: + llvm_unreachable(nullptr); + + case PackCategoriesIntoKey(fcZero, fcNaN): + case PackCategoriesIntoKey(fcNormal, fcNaN): + case PackCategoriesIntoKey(fcInfinity, fcNaN): + assign(rhs); + LLVM_FALLTHROUGH; + case PackCategoriesIntoKey(fcNaN, fcZero): + case PackCategoriesIntoKey(fcNaN, fcNormal): + case PackCategoriesIntoKey(fcNaN, fcInfinity): + case PackCategoriesIntoKey(fcNaN, fcNaN): + if (isSignaling()) { + makeQuiet(); + return opInvalidOp; + } + return rhs.isSignaling() ? opInvalidOp : opOK; + + case PackCategoriesIntoKey(fcZero, fcInfinity): + case PackCategoriesIntoKey(fcZero, fcNormal): + case PackCategoriesIntoKey(fcNormal, fcInfinity): + return opOK; + + case PackCategoriesIntoKey(fcNormal, fcZero): + case PackCategoriesIntoKey(fcInfinity, fcZero): + case PackCategoriesIntoKey(fcInfinity, fcNormal): + case PackCategoriesIntoKey(fcInfinity, fcInfinity): + case PackCategoriesIntoKey(fcZero, fcZero): + makeNaN(); + return opInvalidOp; + + case PackCategoriesIntoKey(fcNormal, fcNormal): + return opDivByZero; // fake status, indicating this is not a special case + } +} + /* Change sign. */ void IEEEFloat::changeSign() { /* Look mummy, this one's easy. */ @@ -1770,40 +1808,108 @@ IEEEFloat::opStatus IEEEFloat::divide(const IEEEFloat &rhs, return fs; } -/* Normalized remainder. This is not currently correct in all cases. */ +/* Normalized remainder. */ IEEEFloat::opStatus IEEEFloat::remainder(const IEEEFloat &rhs) { opStatus fs; - IEEEFloat V = *this; unsigned int origSign = sign; - fs = V.divide(rhs, rmNearestTiesToEven); - if (fs == opDivByZero) + // First handle the special cases. + fs = remainderSpecials(rhs); + if (fs != opDivByZero) return fs; - int parts = partCount(); - integerPart *x = new integerPart[parts]; - bool ignored; - fs = V.convertToInteger(makeMutableArrayRef(x, parts), - parts * integerPartWidth, true, rmNearestTiesToEven, - &ignored); - if (fs == opInvalidOp) { - delete[] x; - return fs; + fs = opOK; + + // Make sure the current value is less than twice the denom. If the addition + // did not succeed (an overflow has happened), which means that the finite + // value we currently posses must be less than twice the denom (as we are + // using the same semantics). + IEEEFloat P2 = rhs; + if (P2.add(rhs, rmNearestTiesToEven) == opOK) { + fs = mod(P2); + assert(fs == opOK); } - fs = V.convertFromZeroExtendedInteger(x, parts * integerPartWidth, true, - rmNearestTiesToEven); - assert(fs==opOK); // should always work + // Lets work with absolute numbers. + IEEEFloat P = rhs; + P.sign = false; + sign = false; - fs = V.multiply(rhs, rmNearestTiesToEven); - assert(fs==opOK || fs==opInexact); // should not overflow or underflow + // + // To calculate the remainder we use the following scheme. + // + // The remainder is defained as follows: + // + // remainder = numer - rquot * denom = x - r * p + // + // Where r is the result of: x/p, rounded toward the nearest integral value + // (with halfway cases rounded toward the even number). + // + // Currently, (after x mod 2p): + // r is the number of 2p's present inside x, which is inherently, an even + // number of p's. + // + // We may split the remaining calculation into 4 options: + // - if x < 0.5p then we round to the nearest number with is 0, and are done. + // - if x == 0.5p then we round to the nearest even number which is 0, and we + // are done as well. + // - if 0.5p < x < p then we round to nearest number which is 1, and we have + // to subtract 1p at least once. + // - if x >= p then we must subtract p at least once, as x must be a + // remainder. + // + // By now, we were done, or we added 1 to r, which in turn, now an odd number. + // + // We can now split the remaining calculation to the following 3 options: + // - if x < 0.5p then we round to the nearest number with is 0, and are done. + // - if x == 0.5p then we round to the nearest even number. As r is odd, we + // must round up to the next even number. so we must subtract p once more. + // - if x > 0.5p (and inherently x < p) then we must round r up to the next + // integral, and subtract p once more. + // + + // Extend the semantics to prevent an overflow/underflow or inexact result. + bool losesInfo; + fltSemantics extendedSemantics = *semantics; + extendedSemantics.maxExponent++; + extendedSemantics.minExponent--; + extendedSemantics.precision += 2; - fs = subtract(V, rmNearestTiesToEven); - assert(fs==opOK || fs==opInexact); // likewise + IEEEFloat VEx = *this; + fs = VEx.convert(extendedSemantics, rmNearestTiesToEven, &losesInfo); + assert(fs == opOK && !losesInfo); + IEEEFloat PEx = P; + fs = PEx.convert(extendedSemantics, rmNearestTiesToEven, &losesInfo); + assert(fs == opOK && !losesInfo); + + // It is simpler to work with 2x instead of 0.5p, and we do not need to lose + // any fraction. + fs = VEx.add(VEx, rmNearestTiesToEven); + assert(fs == opOK); + + if (VEx.compare(PEx) == cmpGreaterThan) { + fs = subtract(P, rmNearestTiesToEven); + assert(fs == opOK); + + // Make VEx = this.add(this), but because we have different semantics, we do + // not want to `convert` again, so we just subtract PEx twice (which equals + // to the desired value). + fs = VEx.subtract(PEx, rmNearestTiesToEven); + assert(fs == opOK); + fs = VEx.subtract(PEx, rmNearestTiesToEven); + assert(fs == opOK); + + cmpResult result = VEx.compare(PEx); + if (result == cmpGreaterThan || result == cmpEqual) { + fs = subtract(P, rmNearestTiesToEven); + assert(fs == opOK); + } + } if (isZero()) sign = origSign; // IEEE754 requires this - delete[] x; + else + sign ^= origSign; return fs; } diff --git a/llvm/unittests/ADT/APFloatTest.cpp b/llvm/unittests/ADT/APFloatTest.cpp index e571e04614ae..6822161729b2 100644 --- a/llvm/unittests/ADT/APFloatTest.cpp +++ b/llvm/unittests/ADT/APFloatTest.cpp @@ -3410,6 +3410,444 @@ TEST(APFloatTest, mod) { } } +TEST(APFloatTest, remainder) { + // Test Special Cases against each other and normal values. + + APFloat PInf = APFloat::getInf(APFloat::IEEEsingle(), false); + APFloat MInf = APFloat::getInf(APFloat::IEEEsingle(), true); + APFloat PZero = APFloat::getZero(APFloat::IEEEsingle(), false); + APFloat MZero = APFloat::getZero(APFloat::IEEEsingle(), true); + APFloat QNaN = APFloat::getNaN(APFloat::IEEEsingle(), false); + APFloat SNaN = APFloat(APFloat::IEEEsingle(), "snan123"); + APFloat PNormalValue = APFloat(APFloat::IEEEsingle(), "0x1p+0"); + APFloat MNormalValue = APFloat(APFloat::IEEEsingle(), "-0x1p+0"); + APFloat PLargestValue = APFloat::getLargest(APFloat::IEEEsingle(), false); + APFloat MLargestValue = APFloat::getLargest(APFloat::IEEEsingle(), true); + APFloat PSmallestValue = APFloat::getSmallest(APFloat::IEEEsingle(), false); + APFloat MSmallestValue = APFloat::getSmallest(APFloat::IEEEsingle(), true); + APFloat PSmallestNormalized = + APFloat::getSmallestNormalized(APFloat::IEEEsingle(), false); + APFloat MSmallestNormalized = + APFloat::getSmallestNormalized(APFloat::IEEEsingle(), true); + + APFloat PVal1(APFloat::IEEEsingle(), "0x1.fffffep+126"); + APFloat MVal1(APFloat::IEEEsingle(), "-0x1.fffffep+126"); + APFloat PVal2(APFloat::IEEEsingle(), "0x1.fffffep-126"); + APFloat MVal2(APFloat::IEEEsingle(), "-0x1.fffffep-126"); + APFloat PVal3(APFloat::IEEEsingle(), "0x1p-125"); + APFloat MVal3(APFloat::IEEEsingle(), "-0x1p-125"); + APFloat PVal4(APFloat::IEEEsingle(), "0x1p+127"); + APFloat MVal4(APFloat::IEEEsingle(), "-0x1p+127"); + APFloat PVal5(APFloat::IEEEsingle(), "1.5"); + APFloat MVal5(APFloat::IEEEsingle(), "-1.5"); + APFloat PVal6(APFloat::IEEEsingle(), "1"); + APFloat MVal6(APFloat::IEEEsingle(), "-1"); + + struct { + APFloat x; + APFloat y; + const char *result; + int status; + int category; + } SpecialCaseTests[] = { + { PInf, PInf, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, MInf, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { PInf, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, PNormalValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, MNormalValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, PLargestValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, MLargestValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, PSmallestValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, MSmallestValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, PSmallestNormalized, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PInf, MSmallestNormalized, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, PInf, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, MInf, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { MInf, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, PNormalValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, MNormalValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, PLargestValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, MLargestValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, PSmallestValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, MSmallestValue, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, PSmallestNormalized, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MInf, MSmallestNormalized, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PZero, PInf, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, MInf, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PZero, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PZero, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { PZero, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { PZero, PNormalValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, MNormalValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, PLargestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, MLargestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, PSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, MSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, PSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PZero, MSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, PInf, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, MInf, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MZero, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MZero, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { MZero, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { MZero, PNormalValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, MNormalValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, PLargestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, MLargestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, PSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, MSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, PSmallestNormalized, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MZero, MSmallestNormalized, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { QNaN, PInf, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, MInf, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, PZero, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, MZero, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, SNaN, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { QNaN, PNormalValue, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, MNormalValue, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, PLargestValue, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, MLargestValue, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, PSmallestValue, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, MSmallestValue, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, PSmallestNormalized, "nan", APFloat::opOK, APFloat::fcNaN }, + { QNaN, MSmallestNormalized, "nan", APFloat::opOK, APFloat::fcNaN }, + { SNaN, PInf, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, MInf, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, PZero, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, MZero, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, QNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, PNormalValue, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, MNormalValue, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, PLargestValue, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, MLargestValue, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, PSmallestValue, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, MSmallestValue, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, PSmallestNormalized, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { SNaN, MSmallestNormalized, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { PNormalValue, PInf, "0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { PNormalValue, MInf, "0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { PNormalValue, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PNormalValue, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PNormalValue, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { PNormalValue, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { PNormalValue, PNormalValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PNormalValue, MNormalValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PNormalValue, PLargestValue, "0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { PNormalValue, MLargestValue, "0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { PNormalValue, PSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PNormalValue, MSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PNormalValue, PSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PNormalValue, MSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MNormalValue, PInf, "-0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { MNormalValue, MInf, "-0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { MNormalValue, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MNormalValue, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MNormalValue, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { MNormalValue, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { MNormalValue, PNormalValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MNormalValue, MNormalValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MNormalValue, PLargestValue, "-0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { MNormalValue, MLargestValue, "-0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { MNormalValue, PSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MNormalValue, MSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MNormalValue, PSmallestNormalized, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MNormalValue, MSmallestNormalized, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PLargestValue, PInf, "0x1.fffffep+127", APFloat::opOK, APFloat::fcNormal }, + { PLargestValue, MInf, "0x1.fffffep+127", APFloat::opOK, APFloat::fcNormal }, + { PLargestValue, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PLargestValue, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PLargestValue, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { PLargestValue, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { PLargestValue, PNormalValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PLargestValue, MNormalValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PLargestValue, PLargestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PLargestValue, MLargestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PLargestValue, PSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PLargestValue, MSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PLargestValue, PSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PLargestValue, MSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MLargestValue, PInf, "-0x1.fffffep+127", APFloat::opOK, APFloat::fcNormal }, + { MLargestValue, MInf, "-0x1.fffffep+127", APFloat::opOK, APFloat::fcNormal }, + { MLargestValue, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MLargestValue, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MLargestValue, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { MLargestValue, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { MLargestValue, PNormalValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MLargestValue, MNormalValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MLargestValue, PLargestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MLargestValue, MLargestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MLargestValue, PSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MLargestValue, MSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MLargestValue, PSmallestNormalized, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MLargestValue, MSmallestNormalized, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PSmallestValue, PInf, "0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { PSmallestValue, MInf, "0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { PSmallestValue, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PSmallestValue, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PSmallestValue, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { PSmallestValue, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { PSmallestValue, PNormalValue, "0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { PSmallestValue, MNormalValue, "0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { PSmallestValue, PLargestValue, "0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { PSmallestValue, MLargestValue, "0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { PSmallestValue, PSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PSmallestValue, MSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PSmallestValue, PSmallestNormalized, "0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { PSmallestValue, MSmallestNormalized, "0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { MSmallestValue, PInf, "-0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { MSmallestValue, MInf, "-0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { MSmallestValue, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MSmallestValue, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MSmallestValue, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { MSmallestValue, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { MSmallestValue, PNormalValue, "-0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { MSmallestValue, MNormalValue, "-0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { MSmallestValue, PLargestValue, "-0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { MSmallestValue, MLargestValue, "-0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { MSmallestValue, PSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MSmallestValue, MSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MSmallestValue, PSmallestNormalized, "-0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { MSmallestValue, MSmallestNormalized, "-0x1p-149", APFloat::opOK, APFloat::fcNormal }, + { PSmallestNormalized, PInf, "0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { PSmallestNormalized, MInf, "0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { PSmallestNormalized, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PSmallestNormalized, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { PSmallestNormalized, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { PSmallestNormalized, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { PSmallestNormalized, PNormalValue, "0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { PSmallestNormalized, MNormalValue, "0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { PSmallestNormalized, PLargestValue, "0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { PSmallestNormalized, MLargestValue, "0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { PSmallestNormalized, PSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PSmallestNormalized, MSmallestValue, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PSmallestNormalized, PSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PSmallestNormalized, MSmallestNormalized, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MSmallestNormalized, PInf, "-0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { MSmallestNormalized, MInf, "-0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { MSmallestNormalized, PZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MSmallestNormalized, MZero, "nan", APFloat::opInvalidOp, APFloat::fcNaN }, + { MSmallestNormalized, QNaN, "nan", APFloat::opOK, APFloat::fcNaN }, + { MSmallestNormalized, SNaN, "nan123", APFloat::opInvalidOp, APFloat::fcNaN }, + { MSmallestNormalized, PNormalValue, "-0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { MSmallestNormalized, MNormalValue, "-0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { MSmallestNormalized, PLargestValue, "-0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { MSmallestNormalized, MLargestValue, "-0x1p-126", APFloat::opOK, APFloat::fcNormal }, + { MSmallestNormalized, PSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MSmallestNormalized, MSmallestValue, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MSmallestNormalized, PSmallestNormalized, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MSmallestNormalized, MSmallestNormalized, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + + { PVal1, PVal1, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, MVal1, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, PVal2, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, MVal2, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, PVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, MVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, PVal4, "-0x1p+103", APFloat::opOK, APFloat::fcNormal }, + { PVal1, MVal4, "-0x1p+103", APFloat::opOK, APFloat::fcNormal }, + { PVal1, PVal5, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, MVal5, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, PVal6, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal1, MVal6, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, PVal1, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, MVal1, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, PVal2, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, MVal2, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, PVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, MVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, PVal4, "0x1p+103", APFloat::opOK, APFloat::fcNormal }, + { MVal1, MVal4, "0x1p+103", APFloat::opOK, APFloat::fcNormal }, + { MVal1, PVal5, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, MVal5, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, PVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal1, MVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal2, PVal1, "0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, MVal1, "0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, PVal2, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal2, MVal2, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal2, PVal3, "-0x0.000002p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, MVal3, "-0x0.000002p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, PVal4, "0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, MVal4, "0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, PVal5, "0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, MVal5, "0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, PVal6, "0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { PVal2, MVal6, "0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, PVal1, "-0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, MVal1, "-0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, PVal2, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal2, MVal2, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal2, PVal3, "0x0.000002p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, MVal3, "0x0.000002p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, PVal4, "-0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, MVal4, "-0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, PVal5, "-0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, MVal5, "-0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, PVal6, "-0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { MVal2, MVal6, "-0x1.fffffep-126", APFloat::opOK, APFloat::fcNormal }, + { PVal3, PVal1, "0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { PVal3, MVal1, "0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { PVal3, PVal2, "0x0.000002p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal3, MVal2, "0x0.000002p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal3, PVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal3, MVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal3, PVal4, "0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { PVal3, MVal4, "0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { PVal3, PVal5, "0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { PVal3, MVal5, "0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { PVal3, PVal6, "0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { PVal3, MVal6, "0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { MVal3, PVal1, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { MVal3, MVal1, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { MVal3, PVal2, "-0x0.000002p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal3, MVal2, "-0x0.000002p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal3, PVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal3, MVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal3, PVal4, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { MVal3, MVal4, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { MVal3, PVal5, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { MVal3, MVal5, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { MVal3, PVal6, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { MVal3, MVal6, "-0x1p-125", APFloat::opOK, APFloat::fcNormal }, + { PVal4, PVal1, "0x1p+103", APFloat::opOK, APFloat::fcNormal }, + { PVal4, MVal1, "0x1p+103", APFloat::opOK, APFloat::fcNormal }, + { PVal4, PVal2, "0x0.002p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal4, MVal2, "0x0.002p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal4, PVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal4, MVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal4, PVal4, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal4, MVal4, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal4, PVal5, "0.5", APFloat::opOK, APFloat::fcNormal }, + { PVal4, MVal5, "0.5", APFloat::opOK, APFloat::fcNormal }, + { PVal4, PVal6, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal4, MVal6, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal4, PVal1, "-0x1p+103", APFloat::opOK, APFloat::fcNormal }, + { MVal4, MVal1, "-0x1p+103", APFloat::opOK, APFloat::fcNormal }, + { MVal4, PVal2, "-0x0.002p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal4, MVal2, "-0x0.002p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal4, PVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal4, MVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal4, PVal4, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal4, MVal4, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal4, PVal5, "-0.5", APFloat::opOK, APFloat::fcNormal }, + { MVal4, MVal5, "-0.5", APFloat::opOK, APFloat::fcNormal }, + { MVal4, PVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal4, MVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal5, PVal1, "1.5", APFloat::opOK, APFloat::fcNormal }, + { PVal5, MVal1, "1.5", APFloat::opOK, APFloat::fcNormal }, + { PVal5, PVal2, "0x0.00006p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal5, MVal2, "0x0.00006p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal5, PVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal5, MVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal5, PVal4, "1.5", APFloat::opOK, APFloat::fcNormal }, + { PVal5, MVal4, "1.5", APFloat::opOK, APFloat::fcNormal }, + { PVal5, PVal5, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal5, MVal5, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal5, PVal6, "-0.5", APFloat::opOK, APFloat::fcNormal }, + { PVal5, MVal6, "-0.5", APFloat::opOK, APFloat::fcNormal }, + { MVal5, PVal1, "-1.5", APFloat::opOK, APFloat::fcNormal }, + { MVal5, MVal1, "-1.5", APFloat::opOK, APFloat::fcNormal }, + { MVal5, PVal2, "-0x0.00006p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal5, MVal2, "-0x0.00006p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal5, PVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal5, MVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal5, PVal4, "-1.5", APFloat::opOK, APFloat::fcNormal }, + { MVal5, MVal4, "-1.5", APFloat::opOK, APFloat::fcNormal }, + { MVal5, PVal5, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal5, MVal5, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal5, PVal6, "0.5", APFloat::opOK, APFloat::fcNormal }, + { MVal5, MVal6, "0.5", APFloat::opOK, APFloat::fcNormal }, + { PVal6, PVal1, "0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { PVal6, MVal1, "0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { PVal6, PVal2, "0x0.00004p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal6, MVal2, "0x0.00004p-126", APFloat::opOK, APFloat::fcNormal }, + { PVal6, PVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal6, MVal3, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal6, PVal4, "0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { PVal6, MVal4, "0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { PVal6, PVal5, "-0.5", APFloat::opOK, APFloat::fcNormal }, + { PVal6, MVal5, "-0.5", APFloat::opOK, APFloat::fcNormal }, + { PVal6, PVal6, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { PVal6, MVal6, "0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal6, PVal1, "-0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { MVal6, MVal1, "-0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { MVal6, PVal2, "-0x0.00004p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal6, MVal2, "-0x0.00004p-126", APFloat::opOK, APFloat::fcNormal }, + { MVal6, PVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal6, MVal3, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal6, PVal4, "-0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { MVal6, MVal4, "-0x1p+0", APFloat::opOK, APFloat::fcNormal }, + { MVal6, PVal5, "0.5", APFloat::opOK, APFloat::fcNormal }, + { MVal6, MVal5, "0.5", APFloat::opOK, APFloat::fcNormal }, + { MVal6, PVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + { MVal6, MVal6, "-0x0p+0", APFloat::opOK, APFloat::fcZero }, + }; + + for (size_t i = 0; i < array_lengthof(SpecialCaseTests); ++i) { + APFloat x(SpecialCaseTests[i].x); + APFloat y(SpecialCaseTests[i].y); + APFloat::opStatus status = x.remainder(y); + + APFloat result(x.getSemantics(), SpecialCaseTests[i].result); + + EXPECT_TRUE(result.bitwiseIsEqual(x)); + EXPECT_EQ(SpecialCaseTests[i].status, (int)status); + EXPECT_EQ(SpecialCaseTests[i].category, (int)x.getCategory()); + } + + { + APFloat f1(APFloat::IEEEdouble(), "0x1.3333333333333p-2"); // 0.3 + APFloat f2(APFloat::IEEEdouble(), "0x1.47ae147ae147bp-7"); // 0.01 + APFloat expected(APFloat::IEEEdouble(), "-0x1.4p-56"); + EXPECT_EQ(APFloat::opOK, f1.remainder(f2)); + EXPECT_TRUE(f1.bitwiseIsEqual(expected)); + } + { + APFloat f1(APFloat::IEEEdouble(), "0x1p64"); // 1.8446744073709552e19 + APFloat f2(APFloat::IEEEdouble(), "1.5"); + APFloat expected(APFloat::IEEEdouble(), "-0.5"); + EXPECT_EQ(APFloat::opOK, f1.remainder(f2)); + EXPECT_TRUE(f1.bitwiseIsEqual(expected)); + } + { + APFloat f1(APFloat::IEEEdouble(), "0x1p1000"); + APFloat f2(APFloat::IEEEdouble(), "0x1p-1000"); + APFloat expected(APFloat::IEEEdouble(), "0.0"); + EXPECT_EQ(APFloat::opOK, f1.remainder(f2)); + EXPECT_TRUE(f1.bitwiseIsEqual(expected)); + } + { + APFloat f1 = APFloat::getInf(APFloat::IEEEdouble(), false); + APFloat f2(APFloat::IEEEdouble(), "1.0"); + EXPECT_EQ(f1.remainder(f2), APFloat::opInvalidOp); + EXPECT_TRUE(f1.isNaN()); + } + { + APFloat f1(APFloat::IEEEdouble(), "-4.0"); + APFloat f2(APFloat::IEEEdouble(), "-2.0"); + APFloat expected(APFloat::IEEEdouble(), "-0.0"); + EXPECT_EQ(APFloat::opOK, f1.remainder(f2)); + EXPECT_TRUE(f1.bitwiseIsEqual(expected)); + } + { + APFloat f1(APFloat::IEEEdouble(), "-4.0"); + APFloat f2(APFloat::IEEEdouble(), "2.0"); + APFloat expected(APFloat::IEEEdouble(), "-0.0"); + EXPECT_EQ(APFloat::opOK, f1.remainder(f2)); + EXPECT_TRUE(f1.bitwiseIsEqual(expected)); + } +} + TEST(APFloatTest, PPCDoubleDoubleAddSpecial) { using DataType = std::tuple; -- GitLab From a9a305716bbfa657ce0f7ae9cd50df82720a6db0 Mon Sep 17 00:00:00 2001 From: Marius Brehler Date: Wed, 12 Feb 2020 09:41:40 +0100 Subject: [PATCH 133/142] [mlir] Revise naming of MLIROptMain and MLIRMlirOptLib * Rename CMake target MLIROptMain to MLIROptLib: The target provides the main library * Rename CMake target MLIRMlirOptLib to MLIRMlirOptMain: The target provides the main() entry function At the moment, the Bazel configuration of TenorFlow maps the target MlirOptLib to "lib/Support/MlirOptMain.cpp" and MlirOptMain to "tools/mlir-opt/mlir-opt.cpp". This is the other way around in the CMake configuration. As discussed in the context of the pull request https://github.com/tensorflow/tensorflow/pull/36301, it seems useful to revise the naming in the MLIR repo. Differential Revision: https://reviews.llvm.org/D73778 --- mlir/lib/Support/CMakeLists.txt | 4 ++-- mlir/tools/mlir-opt/CMakeLists.txt | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/mlir/lib/Support/CMakeLists.txt b/mlir/lib/Support/CMakeLists.txt index 84fecd05fbfd..b8c0b17a68f8 100644 --- a/mlir/lib/Support/CMakeLists.txt +++ b/mlir/lib/Support/CMakeLists.txt @@ -17,13 +17,13 @@ add_llvm_library(MLIRSupport ) target_link_libraries(MLIRSupport LLVMSupport ${LLVM_PTHREAD_LIB}) -add_llvm_library(MLIROptMain +add_llvm_library(MLIROptLib MlirOptMain.cpp ADDITIONAL_HEADER_DIRS ${MLIR_MAIN_INCLUDE_DIR}/mlir/Support ) -target_link_libraries(MLIROptMain +target_link_libraries(MLIROptLib MLIRPass MLIRParser LLVMSupport diff --git a/mlir/tools/mlir-opt/CMakeLists.txt b/mlir/tools/mlir-opt/CMakeLists.txt index de18159f18f0..2277c4110d3d 100644 --- a/mlir/tools/mlir-opt/CMakeLists.txt +++ b/mlir/tools/mlir-opt/CMakeLists.txt @@ -5,16 +5,16 @@ set(LLVM_OPTIONAL_SOURCES set(LIB_LIBS MLIRAnalysis MLIRLLVMIR - MLIROptMain + MLIROptLib MLIRParser MLIRPass MLIRTransforms MLIRSupport ) -add_llvm_library(MLIRMlirOptLib +add_llvm_library(MLIRMlirOptMain mlir-opt.cpp ) -target_link_libraries(MLIRMlirOptLib +target_link_libraries(MLIRMlirOptMain ${LIB_LIBS} ) @@ -43,7 +43,7 @@ set(FULL_LINK_LIBS MLIRLoopOps MLIRNVVMIR MLIROpenMP - MLIROptMain + MLIROptLib MLIRParser MLIRPass MLIRQuantizerFxpMathConfig @@ -71,7 +71,7 @@ set(FULL_LINK_LIBS ) set(LIBS MLIRIR - MLIROptMain + MLIROptLib LLVMSupport LLVMCore LLVMAsmParser -- GitLab From 440460f1e70193f5805e2fdbc6d91ab5d5d0bbab Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Wed, 12 Feb 2020 09:22:59 +0100 Subject: [PATCH 134/142] [lldb][NFC] Move common_completions mapping out of CommandCompletions header. --- .../lldb/Interpreter/CommandCompletions.h | 15 ------ lldb/source/Commands/CommandCompletions.cpp | 46 ++++++++++++------- 2 files changed, 29 insertions(+), 32 deletions(-) diff --git a/lldb/include/lldb/Interpreter/CommandCompletions.h b/lldb/include/lldb/Interpreter/CommandCompletions.h index c4eb1ae878f4..a678a1173c36 100644 --- a/lldb/include/lldb/Interpreter/CommandCompletions.h +++ b/lldb/include/lldb/Interpreter/CommandCompletions.h @@ -23,13 +23,6 @@ namespace lldb_private { class TildeExpressionResolver; class CommandCompletions { public: - // This is the command completion callback that is used to complete the - // argument of the option it is bound to (in the OptionDefinition table - // below). Return the total number of matches. - typedef void (*CompletionCallback)(CommandInterpreter &interpreter, - CompletionRequest &request, - // A search filter to limit the search... - lldb_private::SearchFilter *searcher); enum CommonCompletionTypes { eNoCompletion = 0u, eSourceFileCompletion = (1u << 0), @@ -47,11 +40,6 @@ public: eCustomCompletion = (1u << 9) }; - struct CommonCompletionElement { - uint32_t type; - CompletionCallback callback; - }; - static bool InvokeCommonCompletionCallbacks( CommandInterpreter &interpreter, uint32_t completion_mask, lldb_private::CompletionRequest &request, SearchFilter *searcher); @@ -93,9 +81,6 @@ public: static void VariablePath(CommandInterpreter &interpreter, CompletionRequest &request, SearchFilter *searcher); - -private: - static CommonCompletionElement g_common_completions[]; }; } // namespace lldb_private diff --git a/lldb/source/Commands/CommandCompletions.cpp b/lldb/source/Commands/CommandCompletions.cpp index 31c8e6ab17cc..bc3a2ec4bd9e 100644 --- a/lldb/source/Commands/CommandCompletions.cpp +++ b/lldb/source/Commands/CommandCompletions.cpp @@ -27,18 +27,17 @@ using namespace lldb_private; -CommandCompletions::CommonCompletionElement - CommandCompletions::g_common_completions[] = { - {eSourceFileCompletion, CommandCompletions::SourceFiles}, - {eDiskFileCompletion, CommandCompletions::DiskFiles}, - {eDiskDirectoryCompletion, CommandCompletions::DiskDirectories}, - {eSymbolCompletion, CommandCompletions::Symbols}, - {eModuleCompletion, CommandCompletions::Modules}, - {eSettingsNameCompletion, CommandCompletions::SettingsNames}, - {ePlatformPluginCompletion, CommandCompletions::PlatformPluginNames}, - {eArchitectureCompletion, CommandCompletions::ArchitectureNames}, - {eVariablePathCompletion, CommandCompletions::VariablePath}, - {eNoCompletion, nullptr} // This one has to be last in the list. +// This is the command completion callback that is used to complete the +// argument of the option it is bound to (in the OptionDefinition table +// below). +typedef void (*CompletionCallback)(CommandInterpreter &interpreter, + CompletionRequest &request, + // A search filter to limit the search... + lldb_private::SearchFilter *searcher); + +struct CommonCompletionElement { + uint32_t type; + CompletionCallback callback; }; bool CommandCompletions::InvokeCommonCompletionCallbacks( @@ -46,14 +45,27 @@ bool CommandCompletions::InvokeCommonCompletionCallbacks( CompletionRequest &request, SearchFilter *searcher) { bool handled = false; + const CommonCompletionElement common_completions[] = { + {eSourceFileCompletion, CommandCompletions::SourceFiles}, + {eDiskFileCompletion, CommandCompletions::DiskFiles}, + {eDiskDirectoryCompletion, CommandCompletions::DiskDirectories}, + {eSymbolCompletion, CommandCompletions::Symbols}, + {eModuleCompletion, CommandCompletions::Modules}, + {eSettingsNameCompletion, CommandCompletions::SettingsNames}, + {ePlatformPluginCompletion, CommandCompletions::PlatformPluginNames}, + {eArchitectureCompletion, CommandCompletions::ArchitectureNames}, + {eVariablePathCompletion, CommandCompletions::VariablePath}, + {eNoCompletion, nullptr} // This one has to be last in the list. + }; + for (int i = 0;; i++) { - if (g_common_completions[i].type == eNoCompletion) + if (common_completions[i].type == eNoCompletion) break; - else if ((g_common_completions[i].type & completion_mask) == - g_common_completions[i].type && - g_common_completions[i].callback != nullptr) { + else if ((common_completions[i].type & completion_mask) == + common_completions[i].type && + common_completions[i].callback != nullptr) { handled = true; - g_common_completions[i].callback(interpreter, request, searcher); + common_completions[i].callback(interpreter, request, searcher); } } return handled; -- GitLab From 30ce956aec94ab3785025346a890f4a8cbbe1c58 Mon Sep 17 00:00:00 2001 From: Raphael Isemann Date: Wed, 12 Feb 2020 09:35:19 +0100 Subject: [PATCH 135/142] [lldb][NFC] Remove GetConstTypeName and GetConstQualifiedTypeName from CompilerType Beside these two functions just being wrappers around GetTypeName they are also just a leftover from migrating the CompilerType interface to ConstString. --- lldb/include/lldb/DataFormatters/FormatClasses.h | 2 +- lldb/include/lldb/Symbol/CompilerType.h | 4 ---- lldb/source/Core/ValueObject.cpp | 4 ++-- lldb/source/Core/ValueObjectChild.cpp | 4 ++-- lldb/source/Core/ValueObjectConstResult.cpp | 2 +- lldb/source/Core/ValueObjectMemory.cpp | 2 +- lldb/source/Core/ValueObjectRegister.cpp | 2 +- lldb/source/DataFormatters/FormatManager.cpp | 2 +- .../ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp | 2 +- .../LanguageRuntime/ObjC/ObjCLanguageRuntime.cpp | 2 +- lldb/source/Symbol/CompilerType.cpp | 13 ------------- lldb/source/Symbol/Type.cpp | 4 ++-- 12 files changed, 13 insertions(+), 30 deletions(-) diff --git a/lldb/include/lldb/DataFormatters/FormatClasses.h b/lldb/include/lldb/DataFormatters/FormatClasses.h index 344a2d70ac53..41b9539803aa 100644 --- a/lldb/include/lldb/DataFormatters/FormatClasses.h +++ b/lldb/include/lldb/DataFormatters/FormatClasses.h @@ -126,7 +126,7 @@ public: TypeNameSpecifierImpl(CompilerType type) : m_is_regex(false), m_type() { if (type.IsValid()) { - m_type.m_type_name.assign(type.GetConstTypeName().GetCString()); + m_type.m_type_name.assign(type.GetTypeName().GetCString()); m_type.m_compiler_type = type; } } diff --git a/lldb/include/lldb/Symbol/CompilerType.h b/lldb/include/lldb/Symbol/CompilerType.h index 3885283e8ecf..8399166b4dd4 100644 --- a/lldb/include/lldb/Symbol/CompilerType.h +++ b/lldb/include/lldb/Symbol/CompilerType.h @@ -149,10 +149,6 @@ public: TypeSystem *GetTypeSystem() const { return m_type_system; } - ConstString GetConstQualifiedTypeName() const; - - ConstString GetConstTypeName() const; - ConstString GetTypeName() const; ConstString GetDisplayTypeName() const; diff --git a/lldb/source/Core/ValueObject.cpp b/lldb/source/Core/ValueObject.cpp index 80e41c91e68b..71ceef7798d3 100644 --- a/lldb/source/Core/ValueObject.cpp +++ b/lldb/source/Core/ValueObject.cpp @@ -1650,13 +1650,13 @@ bool ValueObject::GetDeclaration(Declaration &decl) { } ConstString ValueObject::GetTypeName() { - return GetCompilerType().GetConstTypeName(); + return GetCompilerType().GetTypeName(); } ConstString ValueObject::GetDisplayTypeName() { return GetTypeName(); } ConstString ValueObject::GetQualifiedTypeName() { - return GetCompilerType().GetConstQualifiedTypeName(); + return GetCompilerType().GetTypeName(); } LanguageType ValueObject::GetObjectRuntimeLanguage() { diff --git a/lldb/source/Core/ValueObjectChild.cpp b/lldb/source/Core/ValueObjectChild.cpp index 778bcecf05d3..6205ed32c615 100644 --- a/lldb/source/Core/ValueObjectChild.cpp +++ b/lldb/source/Core/ValueObjectChild.cpp @@ -70,14 +70,14 @@ static void AdjustForBitfieldness(ConstString &name, ConstString ValueObjectChild::GetTypeName() { if (m_type_name.IsEmpty()) { - m_type_name = GetCompilerType().GetConstTypeName(); + m_type_name = GetCompilerType().GetTypeName(); AdjustForBitfieldness(m_type_name, m_bitfield_bit_size); } return m_type_name; } ConstString ValueObjectChild::GetQualifiedTypeName() { - ConstString qualified_name = GetCompilerType().GetConstTypeName(); + ConstString qualified_name = GetCompilerType().GetTypeName(); AdjustForBitfieldness(qualified_name, m_bitfield_bit_size); return qualified_name; } diff --git a/lldb/source/Core/ValueObjectConstResult.cpp b/lldb/source/Core/ValueObjectConstResult.cpp index 80d7783ea267..8d84f8e62ccc 100644 --- a/lldb/source/Core/ValueObjectConstResult.cpp +++ b/lldb/source/Core/ValueObjectConstResult.cpp @@ -228,7 +228,7 @@ size_t ValueObjectConstResult::CalculateNumChildren(uint32_t max) { ConstString ValueObjectConstResult::GetTypeName() { if (m_type_name.IsEmpty()) - m_type_name = GetCompilerType().GetConstTypeName(); + m_type_name = GetCompilerType().GetTypeName(); return m_type_name; } diff --git a/lldb/source/Core/ValueObjectMemory.cpp b/lldb/source/Core/ValueObjectMemory.cpp index b1fd51386682..91b2c6084928 100644 --- a/lldb/source/Core/ValueObjectMemory.cpp +++ b/lldb/source/Core/ValueObjectMemory.cpp @@ -117,7 +117,7 @@ CompilerType ValueObjectMemory::GetCompilerTypeImpl() { ConstString ValueObjectMemory::GetTypeName() { if (m_type_sp) return m_type_sp->GetName(); - return m_compiler_type.GetConstTypeName(); + return m_compiler_type.GetTypeName(); } ConstString ValueObjectMemory::GetDisplayTypeName() { diff --git a/lldb/source/Core/ValueObjectRegister.cpp b/lldb/source/Core/ValueObjectRegister.cpp index bd1e2359afae..ec87c38fb367 100644 --- a/lldb/source/Core/ValueObjectRegister.cpp +++ b/lldb/source/Core/ValueObjectRegister.cpp @@ -219,7 +219,7 @@ CompilerType ValueObjectRegister::GetCompilerTypeImpl() { ConstString ValueObjectRegister::GetTypeName() { if (m_type_name.IsEmpty()) - m_type_name = GetCompilerType().GetConstTypeName(); + m_type_name = GetCompilerType().GetTypeName(); return m_type_name; } diff --git a/lldb/source/DataFormatters/FormatManager.cpp b/lldb/source/DataFormatters/FormatManager.cpp index 0230c84e992e..23ad6c67f887 100644 --- a/lldb/source/DataFormatters/FormatManager.cpp +++ b/lldb/source/DataFormatters/FormatManager.cpp @@ -179,7 +179,7 @@ void FormatManager::GetPossibleMatches( bool did_strip_ptr, bool did_strip_ref, bool did_strip_typedef, bool root_level) { compiler_type = compiler_type.GetTypeForFormatters(); - ConstString type_name(compiler_type.GetConstTypeName()); + ConstString type_name(compiler_type.GetTypeName()); if (valobj.GetBitfieldBitSize() > 0) { StreamString sstring; sstring.Printf("%s:%d", type_name.AsCString(), valobj.GetBitfieldBitSize()); diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp index bae489128fd1..0f89550984ac 100644 --- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp +++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp @@ -895,7 +895,7 @@ size_t AppleObjCRuntimeV2::GetByteOffsetForIvar(CompilerType &parent_ast_type, const char *ivar_name) { uint32_t ivar_offset = LLDB_INVALID_IVAR_OFFSET; - ConstString class_name = parent_ast_type.GetConstTypeName(); + ConstString class_name = parent_ast_type.GetTypeName(); if (!class_name.IsEmpty() && ivar_name && ivar_name[0]) { // Make the objective C V2 mangled name for the ivar offset from the class // name and ivar name diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.cpp index a9e48e2cabfe..459e02e55745 100644 --- a/lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.cpp +++ b/lldb/source/Plugins/LanguageRuntime/ObjC/ObjCLanguageRuntime.cpp @@ -397,7 +397,7 @@ ObjCLanguageRuntime::GetRuntimeType(CompilerType base_type) { if (!class_type) return llvm::None; - ConstString class_name(class_type.GetConstTypeName()); + ConstString class_name(class_type.GetTypeName()); if (!class_name) return llvm::None; diff --git a/lldb/source/Symbol/CompilerType.cpp b/lldb/source/Symbol/CompilerType.cpp index ba69b6b9f0c2..1507f2c3121b 100644 --- a/lldb/source/Symbol/CompilerType.cpp +++ b/lldb/source/Symbol/CompilerType.cpp @@ -268,19 +268,6 @@ size_t CompilerType::GetPointerByteSize() const { return 0; } -ConstString CompilerType::GetConstQualifiedTypeName() const { - return GetConstTypeName(); -} - -ConstString CompilerType::GetConstTypeName() const { - if (IsValid()) { - ConstString type_name(GetTypeName()); - if (type_name) - return type_name; - } - return ConstString(""); -} - ConstString CompilerType::GetTypeName() const { if (IsValid()) { return m_type_system->GetTypeName(m_type); diff --git a/lldb/source/Symbol/Type.cpp b/lldb/source/Symbol/Type.cpp index b6d86801d230..09c0e1638793 100644 --- a/lldb/source/Symbol/Type.cpp +++ b/lldb/source/Symbol/Type.cpp @@ -303,7 +303,7 @@ void Type::Dump(Stream *s, bool show_context) { ConstString Type::GetName() { if (!m_name) - m_name = GetForwardCompilerType().GetConstTypeName(); + m_name = GetForwardCompilerType().GetTypeName(); return m_name; } @@ -657,7 +657,7 @@ CompilerType Type::GetForwardCompilerType() { } ConstString Type::GetQualifiedName() { - return GetForwardCompilerType().GetConstTypeName(); + return GetForwardCompilerType().GetTypeName(); } bool Type::GetTypeScopeAndBasename(const llvm::StringRef& name, -- GitLab From 24856002e066347b2f65226d398c92a7472105c5 Mon Sep 17 00:00:00 2001 From: Clement Courbet Date: Wed, 12 Feb 2020 09:05:27 +0100 Subject: [PATCH 136/142] [CodeGenPrepare] Add more store splitting tests for PR44877. --- .../CodeGenPrepare/PowerPC/lit.local.cfg | 2 + .../PowerPC/split-store-alignment.ll | 75 +++++++++++++++++++ .../X86/split-store-alignment.ll | 51 +++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 llvm/test/Transforms/CodeGenPrepare/PowerPC/lit.local.cfg create mode 100644 llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll create mode 100644 llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll diff --git a/llvm/test/Transforms/CodeGenPrepare/PowerPC/lit.local.cfg b/llvm/test/Transforms/CodeGenPrepare/PowerPC/lit.local.cfg new file mode 100644 index 000000000000..091332439b18 --- /dev/null +++ b/llvm/test/Transforms/CodeGenPrepare/PowerPC/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'PowerPC' in config.root.targets: + config.unsupported = True diff --git a/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll b/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll new file mode 100644 index 000000000000..53cf743ef02d --- /dev/null +++ b/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll @@ -0,0 +1,75 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -codegenprepare -mtriple=powerpc64-unknown-linux-gnu -data-layout="E-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefixes=ALL,BE %s +; RUN: opt -S -codegenprepare -mtriple=powerpc64le-unknown-linux-gnu -data-layout="e-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefixes=ALL,LE %s + +define void @split_store_align2(float %x, i64* %p) { +; BE-LABEL: @split_store_align2( +; BE-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; BE-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; BE-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; BE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; BE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; BE-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; BE-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], i32 1 +; BE-NEXT: store i32 [[B]], i32* [[TMP2]], align 2 +; BE-NEXT: [[TMP3:%.*]] = bitcast i64* [[P]] to i32* +; BE-NEXT: store i32 0, i32* [[TMP3]], align 1 +; BE-NEXT: ret void +; +; LE-LABEL: @split_store_align2( +; LE-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; LE-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; LE-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; LE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; LE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; LE-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; LE-NEXT: store i32 [[B]], i32* [[TMP1]], align 2 +; LE-NEXT: [[TMP2:%.*]] = bitcast i64* [[P]] to i32* +; LE-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1 +; LE-NEXT: store i32 0, i32* [[TMP3]], align 1 +; LE-NEXT: ret void +; + %b = bitcast float %x to i32 + %z = zext i32 0 to i64 + %s = shl nuw nsw i64 %z, 32 + %z2 = zext i32 %b to i64 + %o = or i64 %s, %z2 + store i64 %o, i64* %p, align 2 + ret void +} + +define void @split_store_align8(float %x, i64* %p) { +; BE-LABEL: @split_store_align8( +; BE-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; BE-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; BE-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; BE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; BE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; BE-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; BE-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], i32 1 +; BE-NEXT: store i32 [[B]], i32* [[TMP2]], align 8 +; BE-NEXT: [[TMP3:%.*]] = bitcast i64* [[P]] to i32* +; BE-NEXT: store i32 0, i32* [[TMP3]], align 4 +; BE-NEXT: ret void +; +; LE-LABEL: @split_store_align8( +; LE-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; LE-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; LE-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; LE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; LE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; LE-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; LE-NEXT: store i32 [[B]], i32* [[TMP1]], align 8 +; LE-NEXT: [[TMP2:%.*]] = bitcast i64* [[P]] to i32* +; LE-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1 +; LE-NEXT: store i32 0, i32* [[TMP3]], align 4 +; LE-NEXT: ret void +; + %b = bitcast float %x to i32 + %z = zext i32 0 to i64 + %s = shl nuw nsw i64 %z, 32 + %z2 = zext i32 %b to i64 + %o = or i64 %s, %z2 + store i64 %o, i64* %p, align 8 + ret void +} diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll b/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll new file mode 100644 index 000000000000..7e0f5125f087 --- /dev/null +++ b/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll @@ -0,0 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -codegenprepare -mtriple=x86_64-unknown-unknown -force-split-store -S < %s | FileCheck %s + +target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32" +target triple = "i686-w64-windows-gnu" + +define void @split_store_align2(float %x, i64* %p) { +; CHECK-LABEL: @split_store_align2( +; CHECK-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; CHECK-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; CHECK-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; CHECK-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; CHECK-NEXT: store i32 [[B]], i32* [[TMP1]], align 2 +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[P]] to i32* +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1 +; CHECK-NEXT: store i32 0, i32* [[TMP3]], align 1 +; CHECK-NEXT: ret void +; + %b = bitcast float %x to i32 + %z = zext i32 0 to i64 + %s = shl nuw nsw i64 %z, 32 + %z2 = zext i32 %b to i64 + %o = or i64 %s, %z2 + store i64 %o, i64* %p, align 2 + ret void +} + +define void @split_store_align8(float %x, i64* %p) { +; CHECK-LABEL: @split_store_align8( +; CHECK-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; CHECK-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; CHECK-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; CHECK-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; CHECK-NEXT: store i32 [[B]], i32* [[TMP1]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[P]] to i32* +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1 +; CHECK-NEXT: store i32 0, i32* [[TMP3]], align 4 +; CHECK-NEXT: ret void +; + %b = bitcast float %x to i32 + %z = zext i32 0 to i64 + %s = shl nuw nsw i64 %z, 32 + %z2 = zext i32 %b to i64 + %o = or i64 %s, %z2 + store i64 %o, i64* %p, align 8 + ret void +} -- GitLab From c64770506b89a2376fe13080bc3b72789e6c752d Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Wed, 12 Feb 2020 09:03:40 +0000 Subject: [PATCH 137/142] Remove static registration for dialects, and the "alwayslink" hack for passes In the previous state, we were relying on forcing the linker to include all libraries in the final binary and the global initializer to self-register every piece of the system. This change help moving away from this model, and allow users to compose pieces more freely. The current change is only "fixing" the dialect registration and avoiding relying on "whole link" for the passes. The translation is still relying on the global registry, and some refactoring is needed to make this all more convenient. Differential Revision: https://reviews.llvm.org/D74461 --- mlir/examples/toy/Ch5/CMakeLists.txt | 7 +- mlir/examples/toy/Ch5/toyc.cpp | 2 + mlir/examples/toy/Ch6/CMakeLists.txt | 9 +- mlir/examples/toy/Ch6/toyc.cpp | 2 + mlir/examples/toy/Ch7/CMakeLists.txt | 11 +- mlir/examples/toy/Ch7/toyc.cpp | 2 + mlir/include/mlir/Analysis/Passes.h | 3 - mlir/include/mlir/InitAllDialects.h | 59 +++++++++ mlir/include/mlir/InitAllPasses.h | 124 ++++++++++++++++++ .../mlir/Quantizer/Transforms/Passes.h | 3 + mlir/include/mlir/Transforms/Passes.h | 19 +-- mlir/lib/Dialect/AffineOps/CMakeLists.txt | 3 +- .../Dialect/AffineOps/DialectRegistration.cpp | 13 -- mlir/lib/Dialect/CMakeLists.txt | 31 +++++ mlir/lib/Dialect/FxpMathOps/CMakeLists.txt | 1 - .../FxpMathOps/IR/DialectRegistration.cpp | 15 --- mlir/lib/Dialect/GPU/CMakeLists.txt | 1 - .../Dialect/GPU/IR/DialectRegistration.cpp | 12 -- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 2 - mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 1 - mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp | 1 - mlir/lib/Dialect/Linalg/IR/CMakeLists.txt | 1 - .../Dialect/Linalg/IR/LinalgRegistration.cpp | 16 --- .../Dialect/LoopOps/DialectRegistration.cpp | 13 -- mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp | 2 - mlir/lib/Dialect/QuantOps/CMakeLists.txt | 1 - .../QuantOps/IR/DialectRegistration.cpp | 15 --- mlir/lib/Dialect/SDBM/CMakeLists.txt | 1 - mlir/lib/Dialect/SDBM/SDBMDialect.cpp | 11 -- mlir/lib/Dialect/SPIRV/CMakeLists.txt | 1 - .../lib/Dialect/SPIRV/DialectRegistration.cpp | 12 -- .../StandardOps/DialectRegistration.cpp | 13 -- mlir/lib/Dialect/VectorOps/CMakeLists.txt | 1 - .../Dialect/VectorOps/DialectRegistration.cpp | 13 -- .../Transforms/InferQuantizedTypesPass.cpp | 5 + mlir/lib/Support/JitRunner.cpp | 2 + mlir/lib/Transforms/OpStats.cpp | 5 + mlir/test/Dialect/SPIRV/TestAvailability.cpp | 9 +- mlir/test/EDSC/builder-api-test.cpp | 11 +- mlir/test/SDBM/sdbm-api-test.cpp | 3 + mlir/test/lib/IR/TestFunc.cpp | 14 +- mlir/test/lib/IR/TestMatchers.cpp | 7 +- mlir/test/lib/IR/TestSymbolUses.cpp | 12 +- mlir/test/lib/Pass/TestPassManager.cpp | 77 +++++------ mlir/test/lib/TestDialect/TestPatterns.cpp | 35 ++--- .../lib/Transforms/TestAllReduceLowering.cpp | 10 +- mlir/test/lib/Transforms/TestCallGraph.cpp | 9 +- mlir/test/lib/Transforms/TestConstantFold.cpp | 8 +- .../lib/Transforms/TestGpuMemoryPromotion.cpp | 10 +- mlir/test/lib/Transforms/TestInlining.cpp | 7 +- .../lib/Transforms/TestLinalgTransforms.cpp | 10 +- mlir/test/lib/Transforms/TestLiveness.cpp | 10 +- mlir/test/lib/Transforms/TestLoopFusion.cpp | 12 +- mlir/test/lib/Transforms/TestLoopMapping.cpp | 11 +- .../Transforms/TestLoopParametricTiling.cpp | 15 +-- .../lib/Transforms/TestMemRefBoundCheck.cpp | 9 +- .../Transforms/TestMemRefDependenceCheck.cpp | 10 +- .../TestMemRefStrideCalculation.cpp | 8 +- mlir/test/lib/Transforms/TestOpaqueLoc.cpp | 8 +- .../Transforms/TestParallelismDetection.cpp | 11 +- .../TestVectorToLoopsConversion.cpp | 10 +- .../lib/Transforms/TestVectorTransforms.cpp | 18 ++- .../lib/Transforms/TestVectorizationUtils.cpp | 13 +- mlir/tools/mlir-cpu-runner/CMakeLists.txt | 7 +- mlir/tools/mlir-opt/CMakeLists.txt | 13 +- mlir/tools/mlir-opt/mlir-opt.cpp | 68 ++++++++++ mlir/tools/mlir-translate/CMakeLists.txt | 9 +- mlir/tools/mlir-translate/mlir-translate.cpp | 2 + .../QuantOps/QuantizationUtilsTest.cpp | 4 + .../Dialect/SPIRV/DeserializationTest.cpp | 4 + mlir/unittests/SDBM/SDBMTest.cpp | 3 + 71 files changed, 555 insertions(+), 345 deletions(-) create mode 100644 mlir/include/mlir/InitAllDialects.h create mode 100644 mlir/include/mlir/InitAllPasses.h delete mode 100644 mlir/lib/Dialect/AffineOps/DialectRegistration.cpp delete mode 100644 mlir/lib/Dialect/FxpMathOps/IR/DialectRegistration.cpp delete mode 100644 mlir/lib/Dialect/GPU/IR/DialectRegistration.cpp delete mode 100644 mlir/lib/Dialect/Linalg/IR/LinalgRegistration.cpp delete mode 100644 mlir/lib/Dialect/LoopOps/DialectRegistration.cpp delete mode 100644 mlir/lib/Dialect/QuantOps/IR/DialectRegistration.cpp delete mode 100644 mlir/lib/Dialect/SDBM/SDBMDialect.cpp delete mode 100644 mlir/lib/Dialect/SPIRV/DialectRegistration.cpp delete mode 100644 mlir/lib/Dialect/StandardOps/DialectRegistration.cpp delete mode 100644 mlir/lib/Dialect/VectorOps/DialectRegistration.cpp diff --git a/mlir/examples/toy/Ch5/CMakeLists.txt b/mlir/examples/toy/Ch5/CMakeLists.txt index de868daa9b7a..df71c35a7a77 100644 --- a/mlir/examples/toy/Ch5/CMakeLists.txt +++ b/mlir/examples/toy/Ch5/CMakeLists.txt @@ -27,15 +27,10 @@ include_directories(${CMAKE_CURRENT_BINARY_DIR}) include_directories(${CMAKE_CURRENT_BINARY_DIR}/include/) target_link_libraries(toyc-ch5 PRIVATE - MLIRAffineOps + MLIRAllDialects MLIRAnalysis MLIRIR MLIRParser MLIRPass - MLIRStandardOps MLIRTransforms) -whole_archive_link(toyc-ch5 - MLIRAffineOps - MLIRStandardOps - ) diff --git a/mlir/examples/toy/Ch5/toyc.cpp b/mlir/examples/toy/Ch5/toyc.cpp index d3a83a971587..c9a52c606b21 100644 --- a/mlir/examples/toy/Ch5/toyc.cpp +++ b/mlir/examples/toy/Ch5/toyc.cpp @@ -18,6 +18,7 @@ #include "mlir/Analysis/Verifier.h" #include "mlir/IR/MLIRContext.h" #include "mlir/IR/Module.h" +#include "mlir/InitAllDialects.h" #include "mlir/Parser.h" #include "mlir/Pass/Pass.h" #include "mlir/Pass/PassManager.h" @@ -171,6 +172,7 @@ int dumpAST() { } int main(int argc, char **argv) { + mlir::registerAllDialects(); mlir::registerPassManagerCLOptions(); cl::ParseCommandLineOptions(argc, argv, "toy compiler\n"); diff --git a/mlir/examples/toy/Ch6/CMakeLists.txt b/mlir/examples/toy/Ch6/CMakeLists.txt index a539d591b90c..1497cc349868 100644 --- a/mlir/examples/toy/Ch6/CMakeLists.txt +++ b/mlir/examples/toy/Ch6/CMakeLists.txt @@ -29,7 +29,7 @@ include_directories(${CMAKE_CURRENT_BINARY_DIR}) include_directories(${CMAKE_CURRENT_BINARY_DIR}/include/) target_link_libraries(toyc-ch6 PRIVATE - MLIRAffineOps + MLIRAllDialects MLIRAffineToStandard MLIRAnalysis MLIRExecutionEngine @@ -38,15 +38,8 @@ target_link_libraries(toyc-ch6 MLIRLoopToStandard MLIRParser MLIRPass - MLIRStandardOps MLIRStandardToLLVM MLIRTargetLLVMIR MLIRTransforms ) -whole_archive_link(toyc-ch6 - MLIRAffineToStandard - MLIRAffineOps - MLIRLLVMIR - MLIRStandardOps - ) diff --git a/mlir/examples/toy/Ch6/toyc.cpp b/mlir/examples/toy/Ch6/toyc.cpp index f33f7390344a..3c54f731ff42 100644 --- a/mlir/examples/toy/Ch6/toyc.cpp +++ b/mlir/examples/toy/Ch6/toyc.cpp @@ -20,6 +20,7 @@ #include "mlir/ExecutionEngine/OptUtils.h" #include "mlir/IR/MLIRContext.h" #include "mlir/IR/Module.h" +#include "mlir/InitAllDialects.h" #include "mlir/Parser.h" #include "mlir/Pass/Pass.h" #include "mlir/Pass/PassManager.h" @@ -238,6 +239,7 @@ int runJit(mlir::ModuleOp module) { } int main(int argc, char **argv) { + mlir::registerAllDialects(); mlir::registerPassManagerCLOptions(); cl::ParseCommandLineOptions(argc, argv, "toy compiler\n"); diff --git a/mlir/examples/toy/Ch7/CMakeLists.txt b/mlir/examples/toy/Ch7/CMakeLists.txt index 66d543987752..ece8c873786e 100644 --- a/mlir/examples/toy/Ch7/CMakeLists.txt +++ b/mlir/examples/toy/Ch7/CMakeLists.txt @@ -29,24 +29,15 @@ include_directories(${CMAKE_CURRENT_BINARY_DIR}) include_directories(${CMAKE_CURRENT_BINARY_DIR}/include/) target_link_libraries(toyc-ch7 PRIVATE - MLIRAffineOps + MLIRAllDialects MLIRAffineToStandard MLIRAnalysis MLIRExecutionEngine MLIRIR - MLIRLLVMIR MLIRLoopToStandard MLIRParser MLIRPass - MLIRStandardOps MLIRStandardToLLVM MLIRTargetLLVMIR MLIRTransforms ) - -whole_archive_link(toyc-ch7 - MLIRAffineToStandard - MLIRAffineOps - MLIRLLVMIR - MLIRStandardOps - ) diff --git a/mlir/examples/toy/Ch7/toyc.cpp b/mlir/examples/toy/Ch7/toyc.cpp index 199fff96d3b3..1f5f988caca3 100644 --- a/mlir/examples/toy/Ch7/toyc.cpp +++ b/mlir/examples/toy/Ch7/toyc.cpp @@ -20,6 +20,7 @@ #include "mlir/ExecutionEngine/OptUtils.h" #include "mlir/IR/MLIRContext.h" #include "mlir/IR/Module.h" +#include "mlir/InitAllDialects.h" #include "mlir/Parser.h" #include "mlir/Pass/Pass.h" #include "mlir/Pass/PassManager.h" @@ -239,6 +240,7 @@ int runJit(mlir::ModuleOp module) { } int main(int argc, char **argv) { + mlir::registerAllDialects(); mlir::registerPassManagerCLOptions(); cl::ParseCommandLineOptions(argc, argv, "toy compiler\n"); diff --git a/mlir/include/mlir/Analysis/Passes.h b/mlir/include/mlir/Analysis/Passes.h index db53f60b4954..296b3b9838c5 100644 --- a/mlir/include/mlir/Analysis/Passes.h +++ b/mlir/include/mlir/Analysis/Passes.h @@ -28,9 +28,6 @@ std::unique_ptr> createTestMemRefBoundCheckPass(); /// Creates a pass to check memref access dependences in a Function. std::unique_ptr> createTestMemRefDependenceCheckPass(); -/// Creates a pass to test parallelism detection; emits note for parallel loops. -std::unique_ptr> createParallelismDetectionTestPass(); - } // end namespace mlir #endif // MLIR_ANALYSIS_PASSES_H diff --git a/mlir/include/mlir/InitAllDialects.h b/mlir/include/mlir/InitAllDialects.h new file mode 100644 index 000000000000..eeac773cff94 --- /dev/null +++ b/mlir/include/mlir/InitAllDialects.h @@ -0,0 +1,59 @@ +//===- InitAllDialects.h - MLIR Dialects Registration -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines a helper to trigger the registration of all dialects and +// passes to the system. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_INITALLDIALECTS_H_ +#define MLIR_INITALLDIALECTS_H_ + +#include "mlir/Dialect/AffineOps/AffineOps.h" +#include "mlir/Dialect/FxpMathOps/FxpMathOps.h" +#include "mlir/Dialect/GPU/GPUDialect.h" +#include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/Dialect/LLVMIR/NVVMDialect.h" +#include "mlir/Dialect/LLVMIR/ROCDLDialect.h" +#include "mlir/Dialect/Linalg/IR/LinalgOps.h" +#include "mlir/Dialect/LoopOps/LoopOps.h" +#include "mlir/Dialect/OpenMP/OpenMPDialect.h" +#include "mlir/Dialect/QuantOps/QuantOps.h" +#include "mlir/Dialect/SDBM/SDBMDialect.h" +#include "mlir/Dialect/SPIRV/SPIRVDialect.h" +#include "mlir/Dialect/StandardOps/Ops.h" +#include "mlir/Dialect/VectorOps/VectorOps.h" +#include "mlir/IR/Dialect.h" + +namespace mlir { + +// This function should be called before creating any MLIRContext if one expect +// all the possible dialects to be made available to the context automatically. +inline void registerAllDialects() { + static bool init_once = []() { + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + return true; + }(); + (void)init_once; +} +} // namespace mlir + +#endif // MLIR_INITALLDIALECTS_H_ diff --git a/mlir/include/mlir/InitAllPasses.h b/mlir/include/mlir/InitAllPasses.h new file mode 100644 index 000000000000..e48af6f5ff9e --- /dev/null +++ b/mlir/include/mlir/InitAllPasses.h @@ -0,0 +1,124 @@ +//===- LinkAllPassesAndDialects.h - MLIR Registration -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines a helper to trigger the registration of all dialects and +// passes to the system. +// +//===----------------------------------------------------------------------===// + +#ifndef MLIR_INITALLPASSES_H_ +#define MLIR_INITALLPASSES_H_ + +#include "mlir/Analysis/Passes.h" +#include "mlir/Conversion/GPUToCUDA/GPUToCUDAPass.h" +#include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h" +#include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h" +#include "mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h" +#include "mlir/Conversion/LinalgToLLVM/LinalgToLLVM.h" +#include "mlir/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h" +#include "mlir/Conversion/LoopsToGPU/LoopsToGPUPass.h" +#include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h" +#include "mlir/Dialect/FxpMathOps/Passes.h" +#include "mlir/Dialect/GPU/Passes.h" +#include "mlir/Dialect/Linalg/Passes.h" +#include "mlir/Dialect/QuantOps/Passes.h" +#include "mlir/Dialect/SPIRV/Passes.h" +#include "mlir/Quantizer/Transforms/Passes.h" +#include "mlir/Transforms/LocationSnapshot.h" +#include "mlir/Transforms/Passes.h" + +#include + +namespace mlir { + +// This function may be called to register the MLIR passes with the +// global registry. +// If you're building a compiler, you likely don't need this: you would build a +// pipeline programmatically without the need to register with the global +// registry, since it would already be calling the creation routine of the +// individual passes. +// The global registry is interesting to interact with the command-line tools. +inline void registerAllPasses() { + // At the moment we still rely on global initializers for registering passes, + // but we may not do it in the future. + // We must reference the passes in such a way that compilers will not + // delete it all as dead code, even with whole program optimization, + // yet is effectively a NO-OP. As the compiler isn't smart enough + // to know that getenv() never returns -1, this will do the job. + if (std::getenv("bar") != (char *)-1) + return; + + // Init general passes + createCanonicalizerPass(); + createCSEPass(); + createVectorizePass({}); + createLoopUnrollPass(); + createLoopUnrollAndJamPass(); + createSimplifyAffineStructuresPass(); + createLoopFusionPass(); + createLoopInvariantCodeMotionPass(); + createAffineLoopInvariantCodeMotionPass(); + createPipelineDataTransferPass(); + createLowerAffinePass(); + createLoopTilingPass(0); + createLoopCoalescingPass(); + createAffineDataCopyGenerationPass(0, 0); + createMemRefDataFlowOptPass(); + createStripDebugInfoPass(); + createPrintOpStatsPass(); + createInlinerPass(); + createSymbolDCEPass(); + createLocationSnapshotPass({}); + + // GPUtoRODCLPass + createLowerGpuOpsToROCDLOpsPass(); + + // FxpOpsDialect passes + fxpmath::createLowerUniformRealMathPass(); + fxpmath::createLowerUniformCastsPass(); + + // GPU + createGpuKernelOutliningPass(); + createSimpleLoopsToGPUPass(0, 0); + createLoopToGPUPass({}, {}); + + // CUDA + createConvertGpuLaunchFuncToCudaCallsPass(); + createConvertGPUKernelToCubinPass( + [](const std::string &, Location, StringRef) { return nullptr; }); + createLowerGpuOpsToNVVMOpsPass(); + + // Linalg + createLinalgFusionPass(); + createLinalgTilingPass(); + createLinalgTilingToParallelLoopsPass(); + createLinalgPromotionPass(0); + createConvertLinalgToLoopsPass(); + createConvertLinalgToParallelLoopsPass(); + createConvertLinalgToAffineLoopsPass(); + createConvertLinalgToLLVMPass(); + + // QuantOps + quant::createConvertSimulatedQuantPass(); + quant::createConvertConstPass(); + quantizer::createAddDefaultStatsPass(); + quantizer::createRemoveInstrumentationPass(); + quantizer::registerInferQuantizedTypesPass(); + + // SPIR-V + spirv::createDecorateSPIRVCompositeTypeLayoutPass(); + spirv::createLowerABIAttributesPass(); + createConvertGPUToSPIRVPass(); + createConvertStandardToSPIRVPass(); + createLegalizeStdOpsForSPIRVLoweringPass(); + createLinalgToSPIRVPass(); +} + +} // namespace mlir + +#endif // MLIR_INITALLPASSES_H_ diff --git a/mlir/include/mlir/Quantizer/Transforms/Passes.h b/mlir/include/mlir/Quantizer/Transforms/Passes.h index a8a53b95fae8..3cd0475d2f8e 100644 --- a/mlir/include/mlir/Quantizer/Transforms/Passes.h +++ b/mlir/include/mlir/Quantizer/Transforms/Passes.h @@ -28,6 +28,9 @@ std::unique_ptr> createInferQuantizedTypesPass(SolverContext &solverContext, const TargetConfiguration &config); +/// Registers the InferQuantizedTypes pass with the global registry. +void registerInferQuantizedTypesPass(); + /// Creates a pass which removes any instrumentation and hint ops which have /// no effect on final runtime. std::unique_ptr> createRemoveInstrumentationPass(); diff --git a/mlir/include/mlir/Transforms/Passes.h b/mlir/include/mlir/Transforms/Passes.h index 133b716e4c59..8b7495ec0e58 100644 --- a/mlir/include/mlir/Transforms/Passes.h +++ b/mlir/include/mlir/Transforms/Passes.h @@ -37,10 +37,6 @@ std::unique_ptr createCSEPass(); std::unique_ptr> createVectorizePass(ArrayRef virtualVectorSize); -/// Creates a pass to allow independent testing of vectorizer functionality with -/// FileCheck. -std::unique_ptr> createVectorizerTestPass(); - /// Creates a loop unrolling pass with the provided parameters. /// 'getUnrollFactor' is a function callback for clients to supply a function /// that computes an unroll factor - the callback takes precedence over unroll @@ -91,12 +87,6 @@ std::unique_ptr> createLowerAffinePass(); std::unique_ptr> createLoopTilingPass(uint64_t cacheSizeBytes); -/// Creates a pass that performs parametric tiling so that the outermost loops -/// have the given fixed number of iterations. Assumes outermost loop nests -/// are permutable. -std::unique_ptr> -createSimpleParametricTilingPass(ArrayRef outerLoopSizes); - /// Creates a pass that transforms perfectly nested loops with independent /// bounds into a single loop. std::unique_ptr> createLoopCoalescingPass(); @@ -116,11 +106,12 @@ std::unique_ptr> createMemRefDataFlowOptPass(); /// Creates a pass to strip debug information from a function. std::unique_ptr createStripDebugInfoPass(); -/// Creates a pass which tests loop fusion utilities. -std::unique_ptr> createTestLoopFusionPass(); +/// Creates a pass which prints the list of ops and the number of occurences in +/// the module. +std::unique_ptr> createPrintOpStatsPass(); -/// Creates a pass which inlines calls and callable operations as defined by the -/// CallGraph. +/// Creates a pass which inlines calls and callable operations as defined by +/// the CallGraph. std::unique_ptr createInlinerPass(); /// Creates a pass which delete symbol operations that are unreachable. This diff --git a/mlir/lib/Dialect/AffineOps/CMakeLists.txt b/mlir/lib/Dialect/AffineOps/CMakeLists.txt index 9648f27f1067..3d07cde5d6e6 100644 --- a/mlir/lib/Dialect/AffineOps/CMakeLists.txt +++ b/mlir/lib/Dialect/AffineOps/CMakeLists.txt @@ -1,9 +1,8 @@ add_llvm_library(MLIRAffineOps AffineOps.cpp AffineValueMap.cpp - DialectRegistration.cpp EDSC/Builders.cpp - + ADDITIONAL_HEADER_DIRS ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/AffineOps ) diff --git a/mlir/lib/Dialect/AffineOps/DialectRegistration.cpp b/mlir/lib/Dialect/AffineOps/DialectRegistration.cpp deleted file mode 100644 index b9535b5f0d2a..000000000000 --- a/mlir/lib/Dialect/AffineOps/DialectRegistration.cpp +++ /dev/null @@ -1,13 +0,0 @@ -//===- DialectRegistration.cpp - Register Affine Op dialect ---------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/AffineOps/AffineOps.h" -using namespace mlir; - -// Static initialization for Affine op dialect registration. -static DialectRegistration StandardOps; diff --git a/mlir/lib/Dialect/CMakeLists.txt b/mlir/lib/Dialect/CMakeLists.txt index f1d30d86d321..0542830c1660 100644 --- a/mlir/lib/Dialect/CMakeLists.txt +++ b/mlir/lib/Dialect/CMakeLists.txt @@ -12,6 +12,11 @@ add_subdirectory(SPIRV) add_subdirectory(StandardOps) add_subdirectory(VectorOps) + +set(LLVM_OPTIONAL_SOURCES + Traits.cpp +) + add_llvm_library(MLIRDialect Traits.cpp @@ -19,3 +24,29 @@ add_llvm_library(MLIRDialect ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect ) target_link_libraries(MLIRDialect MLIRIR) + +# Create a dummy MLIRAllDialects library for the purpose +# of having an easy tracking of all dialects when linking +# them in tools. +# Empty libraries aren't possible with CMake, create a dummy file. +file(WRITE ${CMAKE_CURRENT_BINARY_DIR}/all_dialects.c "typedef int make_iso_compilers_happy;\n") +add_llvm_library(MLIRAllDialects + ${CMAKE_CURRENT_BINARY_DIR}/all_dialects.c +) +target_link_libraries(MLIRAllDialects + MLIRAffineOps + MLIRFxpMathOps + MLIRGPU + MLIRLLVMIR + MLIRNVVMIR + MLIRROCDLIR + MLIRLinalgOps + MLIRLoopOps + MLIROpenMP + MLIRQuantOps + MLIRSDBM + MLIRShape + MLIRSPIRV + MLIRStandardOps + MLIRVectorOps +) diff --git a/mlir/lib/Dialect/FxpMathOps/CMakeLists.txt b/mlir/lib/Dialect/FxpMathOps/CMakeLists.txt index 61806e0d8089..ba9a3001154e 100644 --- a/mlir/lib/Dialect/FxpMathOps/CMakeLists.txt +++ b/mlir/lib/Dialect/FxpMathOps/CMakeLists.txt @@ -1,6 +1,5 @@ add_llvm_library(MLIRFxpMathOps IR/FxpMathOps.cpp - IR/DialectRegistration.cpp Transforms/LowerUniformRealMath.cpp ADDITIONAL_HEADER_DIRS diff --git a/mlir/lib/Dialect/FxpMathOps/IR/DialectRegistration.cpp b/mlir/lib/Dialect/FxpMathOps/IR/DialectRegistration.cpp deleted file mode 100644 index d732ff944b6d..000000000000 --- a/mlir/lib/Dialect/FxpMathOps/IR/DialectRegistration.cpp +++ /dev/null @@ -1,15 +0,0 @@ -//===- DialectRegistration.cpp - Register FxpMathOps dialect --------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/FxpMathOps/FxpMathOps.h" - -using namespace mlir; -using namespace mlir::fxpmath; - -// Static initialization for the fxpmath ops dialect registration. -static mlir::DialectRegistration FxpMathOps; diff --git a/mlir/lib/Dialect/GPU/CMakeLists.txt b/mlir/lib/Dialect/GPU/CMakeLists.txt index 063aa1ea5ce6..17342f85f9d2 100644 --- a/mlir/lib/Dialect/GPU/CMakeLists.txt +++ b/mlir/lib/Dialect/GPU/CMakeLists.txt @@ -1,6 +1,5 @@ add_llvm_library(MLIRGPU IR/GPUDialect.cpp - IR/DialectRegistration.cpp Transforms/AllReduceLowering.cpp Transforms/KernelOutlining.cpp Transforms/MemoryPromotion.cpp diff --git a/mlir/lib/Dialect/GPU/IR/DialectRegistration.cpp b/mlir/lib/Dialect/GPU/IR/DialectRegistration.cpp deleted file mode 100644 index 2a1b68779dcd..000000000000 --- a/mlir/lib/Dialect/GPU/IR/DialectRegistration.cpp +++ /dev/null @@ -1,12 +0,0 @@ -//===- DialectRegistration.cpp - MLIR GPU dialect registration ------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/GPU/GPUDialect.h" - -// Static initialization for GPU dialect registration. -static mlir::DialectRegistration kernelDialect; diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp index 8e2e3c5ff065..a63a593dfc1e 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp @@ -1658,8 +1658,6 @@ LogicalResult LLVMDialect::verifyRegionArgAttribute(Operation *op, return success(); } -static DialectRegistration llvmDialect; - //===----------------------------------------------------------------------===// // LLVMType. //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp index b7b32df12ca6..210507a61fc3 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp @@ -159,4 +159,3 @@ namespace NVVM { } // namespace NVVM } // namespace mlir -static DialectRegistration nvvmDialect; diff --git a/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp index 28ee28f71e86..83d3ffb1d761 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp @@ -52,4 +52,3 @@ namespace ROCDL { } // namespace ROCDL } // namespace mlir -static DialectRegistration rocdlDialect; diff --git a/mlir/lib/Dialect/Linalg/IR/CMakeLists.txt b/mlir/lib/Dialect/Linalg/IR/CMakeLists.txt index df71c831a7f7..40ce1724235a 100644 --- a/mlir/lib/Dialect/Linalg/IR/CMakeLists.txt +++ b/mlir/lib/Dialect/Linalg/IR/CMakeLists.txt @@ -7,7 +7,6 @@ set(LIBS add_llvm_library(MLIRLinalgOps LinalgOps.cpp LinalgTypes.cpp - LinalgRegistration.cpp ADDITIONAL_HEADER_DIRS ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/Linalg diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgRegistration.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgRegistration.cpp deleted file mode 100644 index f9c2c9b4b637..000000000000 --- a/mlir/lib/Dialect/Linalg/IR/LinalgRegistration.cpp +++ /dev/null @@ -1,16 +0,0 @@ -//===- LinalgRegistration.cpp - Register the linalg dialect statically ----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/Linalg/IR/LinalgOps.h" -#include "mlir/Dialect/Linalg/IR/LinalgTypes.h" - -using namespace mlir; -using namespace mlir::linalg; - -// Static initialization for LinalgOps dialect registration. -static DialectRegistration LinalgOps; diff --git a/mlir/lib/Dialect/LoopOps/DialectRegistration.cpp b/mlir/lib/Dialect/LoopOps/DialectRegistration.cpp deleted file mode 100644 index c0ca419d506c..000000000000 --- a/mlir/lib/Dialect/LoopOps/DialectRegistration.cpp +++ /dev/null @@ -1,13 +0,0 @@ -//===- DialectRegistration.cpp - Register loop dialect --------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/LoopOps/LoopOps.h" -using namespace mlir; - -// Static initialization for loop dialect registration. -static DialectRegistration LoopOps; diff --git a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp index 445323b42e46..edb1a4eb5eb4 100644 --- a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp +++ b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp @@ -30,5 +30,3 @@ namespace omp { #include "mlir/Dialect/OpenMP/OpenMPOps.cpp.inc" } // namespace omp } // namespace mlir - -static DialectRegistration ompDialect; diff --git a/mlir/lib/Dialect/QuantOps/CMakeLists.txt b/mlir/lib/Dialect/QuantOps/CMakeLists.txt index bfbcbdbd3a6e..483056675ef4 100644 --- a/mlir/lib/Dialect/QuantOps/CMakeLists.txt +++ b/mlir/lib/Dialect/QuantOps/CMakeLists.txt @@ -1,5 +1,4 @@ add_llvm_library(MLIRQuantOps - IR/DialectRegistration.cpp IR/QuantOps.cpp IR/QuantTypes.cpp IR/TypeDetail.h diff --git a/mlir/lib/Dialect/QuantOps/IR/DialectRegistration.cpp b/mlir/lib/Dialect/QuantOps/IR/DialectRegistration.cpp deleted file mode 100644 index 8321e88b0b6c..000000000000 --- a/mlir/lib/Dialect/QuantOps/IR/DialectRegistration.cpp +++ /dev/null @@ -1,15 +0,0 @@ -//===- DialectRegistration.cpp - Register Quantization dialect ------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/QuantOps/QuantOps.h" - -using namespace mlir; -using namespace mlir::quant; - -// Static initialization for Quantization dialect registration. -static mlir::DialectRegistration QuantizationOps; diff --git a/mlir/lib/Dialect/SDBM/CMakeLists.txt b/mlir/lib/Dialect/SDBM/CMakeLists.txt index e36308e0edaf..36be9466c573 100644 --- a/mlir/lib/Dialect/SDBM/CMakeLists.txt +++ b/mlir/lib/Dialect/SDBM/CMakeLists.txt @@ -1,7 +1,6 @@ add_llvm_library(MLIRSDBM SDBM.cpp SDBMExpr.cpp - SDBMDialect.cpp ADDITIONAL_HEADER_DIRS ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/SDBM diff --git a/mlir/lib/Dialect/SDBM/SDBMDialect.cpp b/mlir/lib/Dialect/SDBM/SDBMDialect.cpp deleted file mode 100644 index 9b18a126958b..000000000000 --- a/mlir/lib/Dialect/SDBM/SDBMDialect.cpp +++ /dev/null @@ -1,11 +0,0 @@ -//===- SDBMDialect.cpp - Dialect for striped difference-bound matrices ----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/SDBM/SDBMDialect.h" - -static mlir::DialectRegistration SDBMDialect; diff --git a/mlir/lib/Dialect/SPIRV/CMakeLists.txt b/mlir/lib/Dialect/SPIRV/CMakeLists.txt index da7fd1ae7541..d0ff25ef68f0 100644 --- a/mlir/lib/Dialect/SPIRV/CMakeLists.txt +++ b/mlir/lib/Dialect/SPIRV/CMakeLists.txt @@ -3,7 +3,6 @@ mlir_tablegen(SPIRVCanonicalization.inc -gen-rewriters) add_public_tablegen_target(MLIRSPIRVCanonicalizationIncGen) add_llvm_library(MLIRSPIRV - DialectRegistration.cpp LayoutUtils.cpp SPIRVDialect.cpp SPIRVOps.cpp diff --git a/mlir/lib/Dialect/SPIRV/DialectRegistration.cpp b/mlir/lib/Dialect/SPIRV/DialectRegistration.cpp deleted file mode 100644 index 2af7593487c0..000000000000 --- a/mlir/lib/Dialect/SPIRV/DialectRegistration.cpp +++ /dev/null @@ -1,12 +0,0 @@ -//===- DialectRegistration.cpp - MLIR SPIR-V dialect registration ---------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/SPIRV/SPIRVDialect.h" - -// Static initialization for SPIR-V dialect registration. -static mlir::DialectRegistration spirvDialect; diff --git a/mlir/lib/Dialect/StandardOps/DialectRegistration.cpp b/mlir/lib/Dialect/StandardOps/DialectRegistration.cpp deleted file mode 100644 index 54d35f0bf8a7..000000000000 --- a/mlir/lib/Dialect/StandardOps/DialectRegistration.cpp +++ /dev/null @@ -1,13 +0,0 @@ -//===- DialectRegistration.cpp - Register standard Op dialect -------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/StandardOps/Ops.h" -using namespace mlir; - -// Static initialization for standard op dialect registration. -static DialectRegistration StandardOps; diff --git a/mlir/lib/Dialect/VectorOps/CMakeLists.txt b/mlir/lib/Dialect/VectorOps/CMakeLists.txt index 2a9071036331..27cb10f53c20 100644 --- a/mlir/lib/Dialect/VectorOps/CMakeLists.txt +++ b/mlir/lib/Dialect/VectorOps/CMakeLists.txt @@ -1,5 +1,4 @@ add_llvm_library(MLIRVectorOps - DialectRegistration.cpp VectorOps.cpp VectorTransforms.cpp VectorUtils.cpp diff --git a/mlir/lib/Dialect/VectorOps/DialectRegistration.cpp b/mlir/lib/Dialect/VectorOps/DialectRegistration.cpp deleted file mode 100644 index 848504f8c52e..000000000000 --- a/mlir/lib/Dialect/VectorOps/DialectRegistration.cpp +++ /dev/null @@ -1,13 +0,0 @@ -//===- DialectRegistration.cpp - Register super vectorization dialect -----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "mlir/Dialect/VectorOps/VectorOps.h" -using namespace mlir; - -// Static initialization for VectorOps dialect registration. -static DialectRegistration VectorOps; diff --git a/mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp b/mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp index dac67fb7ffae..48c2ca2c075e 100644 --- a/mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp +++ b/mlir/lib/Quantizer/Transforms/InferQuantizedTypesPass.cpp @@ -282,6 +282,11 @@ mlir::quantizer::createInferQuantizedTypesPass( SolverContext &solverContext, const TargetConfiguration &config) { return std::make_unique(solverContext, config); } +void mlir::quantizer::registerInferQuantizedTypesPass() { + // Do nothing, this will be enough to force link this file and the static + // registration will kick-in. This is temporary while we're refactoring pass + // registration to move away from static constructors. +} static PassRegistration pass("quantizer-infer-quantized-types", diff --git a/mlir/lib/Support/JitRunner.cpp b/mlir/lib/Support/JitRunner.cpp index ab7f0bb9ca03..dd8f0832afb5 100644 --- a/mlir/lib/Support/JitRunner.cpp +++ b/mlir/lib/Support/JitRunner.cpp @@ -22,6 +22,7 @@ #include "mlir/IR/MLIRContext.h" #include "mlir/IR/Module.h" #include "mlir/IR/StandardTypes.h" +#include "mlir/InitAllDialects.h" #include "mlir/Parser.h" #include "mlir/Support/FileUtilities.h" @@ -209,6 +210,7 @@ static Error compileAndExecuteSingleFloatReturnFunction( int mlir::JitRunnerMain( int argc, char **argv, function_ref mlirTransformer) { + registerAllDialects(); llvm::InitLLVM y(argc, argv); initializeLLVM(); diff --git a/mlir/lib/Transforms/OpStats.cpp b/mlir/lib/Transforms/OpStats.cpp index dd684d373562..0377b719f6d2 100644 --- a/mlir/lib/Transforms/OpStats.cpp +++ b/mlir/lib/Transforms/OpStats.cpp @@ -10,6 +10,7 @@ #include "mlir/IR/Operation.h" #include "mlir/IR/OperationSupport.h" #include "mlir/Pass/Pass.h" +#include "mlir/Transforms/Passes.h" #include "llvm/ADT/DenseMap.h" #include "llvm/Support/Format.h" #include "llvm/Support/raw_ostream.h" @@ -80,5 +81,9 @@ void PrintOpStatsPass::printSummary() { } } +std::unique_ptr> mlir::createPrintOpStatsPass() { + return std::make_unique(); +} + static PassRegistration pass("print-op-stats", "Print statistics of operations"); diff --git a/mlir/test/Dialect/SPIRV/TestAvailability.cpp b/mlir/test/Dialect/SPIRV/TestAvailability.cpp index 373397bdc2cd..0055085c1661 100644 --- a/mlir/test/Dialect/SPIRV/TestAvailability.cpp +++ b/mlir/test/Dialect/SPIRV/TestAvailability.cpp @@ -213,6 +213,9 @@ ConvertToSubgroupBallot::matchAndRewrite(Operation *op, return matchSuccess(); } -static PassRegistration - convertToTargetEnvPass("test-spirv-target-env", - "Test SPIR-V target environment"); +namespace mlir { +void registerConvertToTargetEnvPass() { + PassRegistration convertToTargetEnvPass( + "test-spirv-target-env", "Test SPIR-V target environment"); +} +} // namespace mlir diff --git a/mlir/test/EDSC/builder-api-test.cpp b/mlir/test/EDSC/builder-api-test.cpp index 92f05680e432..2cf808642905 100644 --- a/mlir/test/EDSC/builder-api-test.cpp +++ b/mlir/test/EDSC/builder-api-test.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -// RUN: mlir-edsc-builder-api-test | FileCheck %s +// RUN: mlir-edsc-builder-api-test | FileCheck %s -dump-input-on-failure #include "mlir/Dialect/AffineOps/EDSC/Intrinsics.h" #include "mlir/Dialect/Linalg/EDSC/Intrinsics.h" @@ -37,6 +37,15 @@ using namespace mlir::edsc; using namespace mlir::edsc::intrinsics; static MLIRContext &globalContext() { + static bool init_once = []() { + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + registerDialect(); + return true; + }(); + (void)init_once; static thread_local MLIRContext context; return context; } diff --git a/mlir/test/SDBM/sdbm-api-test.cpp b/mlir/test/SDBM/sdbm-api-test.cpp index 4606df9a85e1..0b58e2948145 100644 --- a/mlir/test/SDBM/sdbm-api-test.cpp +++ b/mlir/test/SDBM/sdbm-api-test.cpp @@ -19,6 +19,9 @@ using namespace mlir; +// Load the SDBM dialect +static DialectRegistration SDBMRegistration; + static MLIRContext *ctx() { static thread_local MLIRContext context; return &context; diff --git a/mlir/test/lib/IR/TestFunc.cpp b/mlir/test/lib/IR/TestFunc.cpp index 7003600984f9..0e885c555e38 100644 --- a/mlir/test/lib/IR/TestFunc.cpp +++ b/mlir/test/lib/IR/TestFunc.cpp @@ -51,8 +51,12 @@ struct TestFuncSetType : public ModulePass { }; } // end anonymous namespace -static PassRegistration pass("test-func-erase-arg", - "Test erasing func args."); - -static PassRegistration pass2("test-func-set-type", - "Test FuncOp::setType."); +namespace mlir { +void registerTestFunc() { + PassRegistration pass("test-func-erase-arg", + "Test erasing func args."); + + PassRegistration pass2("test-func-set-type", + "Test FuncOp::setType."); +} +} // namespace mlir diff --git a/mlir/test/lib/IR/TestMatchers.cpp b/mlir/test/lib/IR/TestMatchers.cpp index 5620df3d6ed8..c6c144ef1fd0 100644 --- a/mlir/test/lib/IR/TestMatchers.cpp +++ b/mlir/test/lib/IR/TestMatchers.cpp @@ -146,5 +146,8 @@ void TestMatchers::runOnFunction() { test2(f); } -static PassRegistration pass("test-matchers", - "Test C++ pattern matchers."); +namespace mlir { +void registerTestMatchers() { + PassRegistration("test-matchers", "Test C++ pattern matchers."); +} +} // namespace mlir diff --git a/mlir/test/lib/IR/TestSymbolUses.cpp b/mlir/test/lib/IR/TestSymbolUses.cpp index 7757da5c968a..6082cdcbe72b 100644 --- a/mlir/test/lib/IR/TestSymbolUses.cpp +++ b/mlir/test/lib/IR/TestSymbolUses.cpp @@ -103,8 +103,12 @@ struct SymbolReplacementPass : public ModulePass { }; } // end anonymous namespace -static PassRegistration pass("test-symbol-uses", - "Test detection of symbol uses"); +namespace mlir { +void registerSymbolTestPasses() { + PassRegistration("test-symbol-uses", + "Test detection of symbol uses"); -static PassRegistration - rauwPass("test-symbol-rauw", "Test replacement of symbol uses"); + PassRegistration("test-symbol-rauw", + "Test replacement of symbol uses"); +} +} // namespace mlir diff --git a/mlir/test/lib/Pass/TestPassManager.cpp b/mlir/test/lib/Pass/TestPassManager.cpp index 4097fd0675e9..95bef9b878e2 100644 --- a/mlir/test/lib/Pass/TestPassManager.cpp +++ b/mlir/test/lib/Pass/TestPassManager.cpp @@ -88,40 +88,43 @@ static void testNestedPipelineTextual(OpPassManager &pm) { (void)parsePassPipeline("test-pm-nested-pipeline", pm); } -static PassRegistration - reg("test-options-pass", "Test options parsing capabilities"); - -static PassRegistration - unusedMP("test-module-pass", "Test a module pass in the pass manager"); -static PassRegistration - unusedFP("test-function-pass", "Test a function pass in the pass manager"); - -static PassRegistration - unusedCrashP("test-pass-crash", - "Test a pass in the pass manager that always crashes"); - -static PassRegistration unusedStatP("test-stats-pass", - "Test pass statistics"); - -static PassPipelineRegistration<> - unused("test-pm-nested-pipeline", - "Test a nested pipeline in the pass manager", testNestedPipeline); -static PassPipelineRegistration<> - unusedTextual("test-textual-pm-nested-pipeline", - "Test a nested pipeline in the pass manager", - testNestedPipelineTextual); -static PassPipelineRegistration<> - unusedDump("test-dump-pipeline", - "Dumps the pipeline build so far for debugging purposes", - [](OpPassManager &pm) { - pm.printAsTextualPipeline(llvm::errs()); - llvm::errs() << "\n"; - }); - -static PassPipelineRegistration - registerOptionsPassPipeline( - "test-options-pass-pipeline", - "Parses options using pass pipeline registration", - [](OpPassManager &pm, const TestOptionsPass::Options &options) { - pm.addPass(std::make_unique(options)); - }); +namespace mlir { +void registerPassManagerTestPass() { + PassRegistration("test-options-pass", + "Test options parsing capabilities"); + + PassRegistration("test-module-pass", + "Test a module pass in the pass manager"); + + PassRegistration( + "test-function-pass", "Test a function pass in the pass manager"); + + PassRegistration( + "test-pass-crash", "Test a pass in the pass manager that always crashes"); + + PassRegistration unusedStatP("test-stats-pass", + "Test pass statistics"); + + PassPipelineRegistration<>("test-pm-nested-pipeline", + "Test a nested pipeline in the pass manager", + testNestedPipeline); + PassPipelineRegistration<>("test-textual-pm-nested-pipeline", + "Test a nested pipeline in the pass manager", + testNestedPipelineTextual); + PassPipelineRegistration<>( + "test-dump-pipeline", + "Dumps the pipeline build so far for debugging purposes", + [](OpPassManager &pm) { + pm.printAsTextualPipeline(llvm::errs()); + llvm::errs() << "\n"; + }); + + PassPipelineRegistration + registerOptionsPassPipeline( + "test-options-pass-pipeline", + "Parses options using pass pipeline registration", + [](OpPassManager &pm, const TestOptionsPass::Options &options) { + pm.addPass(std::make_unique(options)); + }); +} +} // namespace mlir diff --git a/mlir/test/lib/TestDialect/TestPatterns.cpp b/mlir/test/lib/TestDialect/TestPatterns.cpp index 30330052d5e5..d975d6719170 100644 --- a/mlir/test/lib/TestDialect/TestPatterns.cpp +++ b/mlir/test/lib/TestDialect/TestPatterns.cpp @@ -50,9 +50,6 @@ struct TestPatternDriver : public FunctionPass { }; } // end anonymous namespace -static mlir::PassRegistration - pass("test-patterns", "Run test dialect patterns"); - //===----------------------------------------------------------------------===// // ReturnType Driver. //===----------------------------------------------------------------------===// @@ -107,9 +104,6 @@ struct TestReturnTypeDriver : public FunctionPass { }; } // end anonymous namespace -static mlir::PassRegistration - rt_pass("test-return-type", "Run return type functions"); - //===----------------------------------------------------------------------===// // Legalization Driver. //===----------------------------------------------------------------------===// @@ -440,13 +434,6 @@ static llvm::cl::opt clEnumValN(TestLegalizePatternDriver::ConversionMode::Partial, "partial", "Perform a partial conversion"))); -static mlir::PassRegistration - legalizer_pass("test-legalize-patterns", - "Run test dialect legalization patterns", [] { - return std::make_unique( - legalizerConversionMode); - }); - //===----------------------------------------------------------------------===// // ConversionPatternRewriter::getRemappedValue testing. This method is used // to get the remapped value of a original value that was replaced using @@ -505,6 +492,22 @@ struct TestRemappedValue : public mlir::FunctionPass { }; } // end anonymous namespace -static PassRegistration remapped_value_pass( - "test-remapped-value", - "Test public remapped value mechanism in ConversionPatternRewriter"); +namespace mlir { +void registerPatternsTestPass() { + mlir::PassRegistration("test-return-type", + "Run return type functions"); + + mlir::PassRegistration("test-patterns", + "Run test dialect patterns"); + + mlir::PassRegistration( + "test-legalize-patterns", "Run test dialect legalization patterns", [] { + return std::make_unique( + legalizerConversionMode); + }); + + PassRegistration( + "test-remapped-value", + "Test public remapped value mechanism in ConversionPatternRewriter"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestAllReduceLowering.cpp b/mlir/test/lib/Transforms/TestAllReduceLowering.cpp index fef08050d2f5..508f70887350 100644 --- a/mlir/test/lib/Transforms/TestAllReduceLowering.cpp +++ b/mlir/test/lib/Transforms/TestAllReduceLowering.cpp @@ -27,6 +27,10 @@ struct TestAllReduceLoweringPass }; } // namespace -static PassRegistration - pass("test-all-reduce-lowering", - "Lowers gpu.all-reduce ops within the GPU dialect."); +namespace mlir { +void registerTestAllReduceLoweringPass() { + PassRegistration pass( + "test-all-reduce-lowering", + "Lowers gpu.all-reduce ops within the GPU dialect."); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestCallGraph.cpp b/mlir/test/lib/Transforms/TestCallGraph.cpp index 13115c9cc578..89c25da9e8ed 100644 --- a/mlir/test/lib/Transforms/TestCallGraph.cpp +++ b/mlir/test/lib/Transforms/TestCallGraph.cpp @@ -25,6 +25,9 @@ struct TestCallGraphPass : public ModulePass { }; } // end anonymous namespace -static PassRegistration - pass("test-print-callgraph", - "Print the contents of a constructed callgraph."); +namespace mlir { +void registerTestCallGraphPass() { + PassRegistration pass( + "test-print-callgraph", "Print the contents of a constructed callgraph."); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestConstantFold.cpp b/mlir/test/lib/Transforms/TestConstantFold.cpp index 4c19f7932da0..269f5f613c18 100644 --- a/mlir/test/lib/Transforms/TestConstantFold.cpp +++ b/mlir/test/lib/Transforms/TestConstantFold.cpp @@ -64,5 +64,9 @@ void TestConstantFold::runOnFunction() { } } -static PassRegistration - pass("test-constant-fold", "Test operation constant folding"); +namespace mlir { +void registerTestConstantFold() { + PassRegistration("test-constant-fold", + "Test operation constant folding"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestGpuMemoryPromotion.cpp b/mlir/test/lib/Transforms/TestGpuMemoryPromotion.cpp index 24ea0d95cf41..72304244d8fc 100644 --- a/mlir/test/lib/Transforms/TestGpuMemoryPromotion.cpp +++ b/mlir/test/lib/Transforms/TestGpuMemoryPromotion.cpp @@ -35,6 +35,10 @@ class TestGpuMemoryPromotionPass }; } // end namespace -static PassRegistration registration( - "test-gpu-memory-promotion", - "Promotes the annotated arguments of gpu.func to workgroup memory."); +namespace mlir { +void registerTestGpuMemoryPromotionPass() { + PassRegistration( + "test-gpu-memory-promotion", + "Promotes the annotated arguments of gpu.func to workgroup memory."); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestInlining.cpp b/mlir/test/lib/Transforms/TestInlining.cpp index 3d64b55c46ac..513594f655cc 100644 --- a/mlir/test/lib/Transforms/TestInlining.cpp +++ b/mlir/test/lib/Transforms/TestInlining.cpp @@ -60,5 +60,8 @@ struct Inliner : public FunctionPass { }; } // end anonymous namespace -static PassRegistration pass("test-inline", - "Test inlining region calls"); +namespace mlir { +void registerInliner() { + PassRegistration("test-inline", "Test inlining region calls"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestLinalgTransforms.cpp b/mlir/test/lib/Transforms/TestLinalgTransforms.cpp index 94e4a887a4e3..645ce887135d 100644 --- a/mlir/test/lib/Transforms/TestLinalgTransforms.cpp +++ b/mlir/test/lib/Transforms/TestLinalgTransforms.cpp @@ -47,6 +47,10 @@ void TestLinalgTransforms::runOnFunction() { }); } -static PassRegistration - pass("test-linalg-transform-patterns", - "Test Linalg transformation patterns by applying them greedily."); +namespace mlir { +void registerTestLinalgTransforms() { + PassRegistration( + "test-linalg-transform-patterns", + "Test Linalg transformation patterns by applying them greedily."); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestLiveness.cpp b/mlir/test/lib/Transforms/TestLiveness.cpp index 64276157ced9..9b98ebd49a9c 100644 --- a/mlir/test/lib/Transforms/TestLiveness.cpp +++ b/mlir/test/lib/Transforms/TestLiveness.cpp @@ -28,6 +28,10 @@ struct TestLivenessPass : public FunctionPass { } // end anonymous namespace -static PassRegistration - pass("test-print-liveness", - "Print the contents of a constructed liveness information."); +namespace mlir { +void registerTestLivenessPass() { + PassRegistration( + "test-print-liveness", + "Print the contents of a constructed liveness information."); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestLoopFusion.cpp b/mlir/test/lib/Transforms/TestLoopFusion.cpp index 93e6fd450160..9ffa347173f6 100644 --- a/mlir/test/lib/Transforms/TestLoopFusion.cpp +++ b/mlir/test/lib/Transforms/TestLoopFusion.cpp @@ -54,10 +54,6 @@ struct TestLoopFusion : public FunctionPass { } // end anonymous namespace -std::unique_ptr> mlir::createTestLoopFusionPass() { - return std::make_unique(); -} - // Gathers all AffineForOps in 'block' at 'currLoopDepth' in 'depthToLoops'. static void gatherLoops(Block *block, unsigned currLoopDepth, @@ -218,5 +214,9 @@ void TestLoopFusion::runOnFunction() { iterateLoops(depthToLoops, testSliceComputation); } -static PassRegistration - pass("test-loop-fusion", "Tests loop fusion utility functions."); +namespace mlir { +void registerTestLoopFusion() { + PassRegistration("test-loop-fusion", + "Tests loop fusion utility functions."); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestLoopMapping.cpp b/mlir/test/lib/Transforms/TestLoopMapping.cpp index f20a0ba19c33..ee96d630ae0e 100644 --- a/mlir/test/lib/Transforms/TestLoopMapping.cpp +++ b/mlir/test/lib/Transforms/TestLoopMapping.cpp @@ -50,7 +50,10 @@ public: }; } // end namespace -static PassRegistration - reg("test-mapping-to-processing-elements", - "test mapping a single loop on a virtual processor grid", - [] { return std::make_unique(); }); +namespace mlir { +void registerTestLoopMappingPass() { + PassRegistration( + "test-mapping-to-processing-elements", + "test mapping a single loop on a virtual processor grid"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestLoopParametricTiling.cpp b/mlir/test/lib/Transforms/TestLoopParametricTiling.cpp index 0ef602a746f3..f82ea3aed284 100644 --- a/mlir/test/lib/Transforms/TestLoopParametricTiling.cpp +++ b/mlir/test/lib/Transforms/TestLoopParametricTiling.cpp @@ -48,12 +48,11 @@ public: }; } // end namespace -std::unique_ptr> -mlir::createSimpleParametricTilingPass(ArrayRef outerLoopSizes) { - return std::make_unique(outerLoopSizes); +namespace mlir { +void registerSimpleParametricTilingPass() { + PassRegistration( + "test-extract-fixed-outer-loops", + "test application of parametric tiling to the outer loops so that the " + "ranges of outer loops become static"); } - -static PassRegistration - reg("test-extract-fixed-outer-loops", - "test application of parametric tiling to the outer loops so that the " - "ranges of outer loops become static"); +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp b/mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp index bd53956ee1f4..224d9c34e73d 100644 --- a/mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp +++ b/mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp @@ -48,6 +48,9 @@ void TestMemRefBoundCheck::runOnFunction() { }); } -static PassRegistration - memRefBoundCheck("test-memref-bound-check", - "Check memref access bounds in a Function"); +namespace mlir { +void registerMemRefBoundCheck() { + PassRegistration( + "test-memref-bound-check", "Check memref access bounds in a Function"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestMemRefDependenceCheck.cpp b/mlir/test/lib/Transforms/TestMemRefDependenceCheck.cpp index f9c45c5cb338..289c9a75f5b1 100644 --- a/mlir/test/lib/Transforms/TestMemRefDependenceCheck.cpp +++ b/mlir/test/lib/Transforms/TestMemRefDependenceCheck.cpp @@ -116,6 +116,10 @@ void TestMemRefDependenceCheck::runOnFunction() { checkDependences(loadsAndStores); } -static PassRegistration - pass("test-memref-dependence-check", - "Checks dependences between all pairs of memref accesses."); +namespace mlir { +void registerTestMemRefDependenceCheck() { + PassRegistration pass( + "test-memref-dependence-check", + "Checks dependences between all pairs of memref accesses."); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp b/mlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp index 3c80741c1d7d..52af86e39682 100644 --- a/mlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp +++ b/mlir/test/lib/Transforms/TestMemRefStrideCalculation.cpp @@ -50,5 +50,9 @@ void TestMemRefStrideCalculation::runOnFunction() { llvm::outs().flush(); } -static PassRegistration - pass("test-memref-stride-calculation", "Test operation constant folding"); +namespace mlir { +void registerTestMemRefStrideCalculation() { + PassRegistration pass( + "test-memref-stride-calculation", "Test operation constant folding"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestOpaqueLoc.cpp b/mlir/test/lib/Transforms/TestOpaqueLoc.cpp index 1b21b0013d97..5f2dab20ea09 100644 --- a/mlir/test/lib/Transforms/TestOpaqueLoc.cpp +++ b/mlir/test/lib/Transforms/TestOpaqueLoc.cpp @@ -80,5 +80,9 @@ struct TestOpaqueLoc : public ModulePass { } // end anonymous namespace -static PassRegistration - pass("test-opaque-loc", "Changes all leaf locations to opaque locations"); +namespace mlir { +void registerTestOpaqueLoc() { + PassRegistration pass( + "test-opaque-loc", "Changes all leaf locations to opaque locations"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestParallelismDetection.cpp b/mlir/test/lib/Transforms/TestParallelismDetection.cpp index eca8dda4aaa7..7c16a259723f 100644 --- a/mlir/test/lib/Transforms/TestParallelismDetection.cpp +++ b/mlir/test/lib/Transforms/TestParallelismDetection.cpp @@ -27,9 +27,6 @@ struct TestParallelismDetection } // end anonymous namespace -std::unique_ptr> mlir::createParallelismDetectionTestPass() { - return std::make_unique(); -} // Walks the function and emits a note for all 'affine.for' ops detected as // parallel. @@ -44,5 +41,9 @@ void TestParallelismDetection::runOnFunction() { }); } -static PassRegistration - pass("test-detect-parallel", "Test parallelism detection "); +namespace mlir { +void registerTestParallelismDetection() { + PassRegistration pass( + "test-detect-parallel", "Test parallelism detection "); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestVectorToLoopsConversion.cpp b/mlir/test/lib/Transforms/TestVectorToLoopsConversion.cpp index 2d4329db3aa2..88d08ce63119 100644 --- a/mlir/test/lib/Transforms/TestVectorToLoopsConversion.cpp +++ b/mlir/test/lib/Transforms/TestVectorToLoopsConversion.cpp @@ -29,6 +29,10 @@ struct TestVectorToLoopsPass } // end anonymous namespace -static PassRegistration - pass("test-convert-vector-to-loops", - "Converts vector transfer ops to loops over scalars and vector casts"); +namespace mlir { +void registerTestVectorToLoopsPass() { + PassRegistration pass( + "test-convert-vector-to-loops", + "Converts vector transfer ops to loops over scalars and vector casts"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestVectorTransforms.cpp b/mlir/test/lib/Transforms/TestVectorTransforms.cpp index 09561cfb1861..d0ac7189a4d9 100644 --- a/mlir/test/lib/Transforms/TestVectorTransforms.cpp +++ b/mlir/test/lib/Transforms/TestVectorTransforms.cpp @@ -44,10 +44,14 @@ struct TestVectorSlicesConversion } // end anonymous namespace -static PassRegistration - pass("test-vector-to-vector-conversion", - "Test conversion patterns between ops in the vector dialect"); - -static PassRegistration slices_pass( - "test-vector-slices-conversion", - "Test conversion patterns that lower slices ops in the vector dialect"); +namespace mlir { +void registerTestVectorConversions() { + PassRegistration pass( + "test-vector-to-vector-conversion", + "Test conversion patterns between ops in the vector dialect"); + + PassRegistration slices_pass( + "test-vector-slices-conversion", + "Test conversion patterns that lower slices ops in the vector dialect"); +} +} // namespace mlir diff --git a/mlir/test/lib/Transforms/TestVectorizationUtils.cpp b/mlir/test/lib/Transforms/TestVectorizationUtils.cpp index 05705ae5f72a..50086e5c333a 100644 --- a/mlir/test/lib/Transforms/TestVectorizationUtils.cpp +++ b/mlir/test/lib/Transforms/TestVectorizationUtils.cpp @@ -281,12 +281,9 @@ void VectorizerTestPass::runOnFunction() { } } -std::unique_ptr> mlir::createVectorizerTestPass() { - return std::make_unique(); +namespace mlir { +void registerVectorizerTestPass() { + PassRegistration pass( + "affine-vectorizer-test", "Tests vectorizer standalone functionality."); } - -static PassRegistration - pass("affine-vectorizer-test", - "Tests vectorizer standalone functionality."); - -#undef DEBUG_TYPE +} // namespace mlir diff --git a/mlir/tools/mlir-cpu-runner/CMakeLists.txt b/mlir/tools/mlir-cpu-runner/CMakeLists.txt index 21da9052d05c..b0676ef7de71 100644 --- a/mlir/tools/mlir-cpu-runner/CMakeLists.txt +++ b/mlir/tools/mlir-cpu-runner/CMakeLists.txt @@ -2,13 +2,8 @@ add_llvm_tool(mlir-cpu-runner mlir-cpu-runner.cpp ) llvm_update_compile_flags(mlir-cpu-runner) -whole_archive_link(mlir-cpu-runner - MLIRAffineOps - MLIRLLVMIR - MLIRTargetLLVMIR - MLIRTranslation -) target_link_libraries(mlir-cpu-runner PRIVATE + MLIRAllDialects MLIRAnalysis MLIREDSC MLIRExecutionEngine diff --git a/mlir/tools/mlir-opt/CMakeLists.txt b/mlir/tools/mlir-opt/CMakeLists.txt index 2277c4110d3d..b7e1b4442e21 100644 --- a/mlir/tools/mlir-opt/CMakeLists.txt +++ b/mlir/tools/mlir-opt/CMakeLists.txt @@ -18,7 +18,7 @@ target_link_libraries(MLIRMlirOptMain ${LIB_LIBS} ) -set(FULL_LINK_LIBS +set(LIBS MLIRLoopAnalysis MLIRAnalysis MLIRAffineOps @@ -68,8 +68,6 @@ set(FULL_LINK_LIBS MLIRVectorOps MLIRVectorToLLVM MLIRVectorToLoops -) -set(LIBS MLIRIR MLIROptLib LLVMSupport @@ -82,19 +80,12 @@ if(MLIR_CUDA_CONVERSIONS_ENABLED) LLVMNVPTXCodeGen LLVMNVPTXDesc LLVMNVPTXInfo - MLIRTargetNVVMIR - ) - # Order matters here, so insert at front. - list(INSERT FULL_LINK_LIBS 0 MLIRGPUtoCUDATransforms + MLIRTargetNVVMIR ) endif() add_llvm_tool(mlir-opt mlir-opt.cpp ) llvm_update_compile_flags(mlir-opt) -# It is necessary to use whole_archive_link to ensure that all static -# initializers are called. However, whole_archive_link libraries cannot -# also be target_link_libraries. -whole_archive_link(mlir-opt ${FULL_LINK_LIBS}) target_link_libraries(mlir-opt PRIVATE ${LIBS}) diff --git a/mlir/tools/mlir-opt/mlir-opt.cpp b/mlir/tools/mlir-opt/mlir-opt.cpp index f637a2feea95..bf6b57c2b624 100644 --- a/mlir/tools/mlir-opt/mlir-opt.cpp +++ b/mlir/tools/mlir-opt/mlir-opt.cpp @@ -11,6 +11,8 @@ //===----------------------------------------------------------------------===// #include "mlir/Analysis/Passes.h" +#include "mlir/InitAllDialects.h" +#include "mlir/InitAllPasses.h" #include "mlir/Pass/Pass.h" #include "mlir/Pass/PassManager.h" #include "mlir/Support/FileUtilities.h" @@ -23,6 +25,34 @@ using namespace llvm; using namespace mlir; +namespace mlir { +// Defined in the test directory, no public header. +void registerConvertToTargetEnvPass(); +void registerInliner(); +void registerMemRefBoundCheck(); +void registerPassManagerTestPass(); +void registerPatternsTestPass(); +void registerSimpleParametricTilingPass(); +void registerSymbolTestPasses(); +void registerTestAllReduceLoweringPass(); +void registerTestCallGraphPass(); +void registerTestConstantFold(); +void registerTestFunc(); +void registerTestGpuMemoryPromotionPass(); +void registerTestLinalgTransforms(); +void registerTestLivenessPass(); +void registerTestLoopFusion(); +void registerTestLoopMappingPass(); +void registerTestMatchers(); +void registerTestMemRefDependenceCheck(); +void registerTestMemRefStrideCalculation(); +void registerTestOpaqueLoc(); +void registerTestParallelismDetection(); +void registerTestVectorConversions(); +void registerTestVectorToLoopsPass(); +void registerVectorizerTestPass(); +} // namespace mlir + static cl::opt inputFilename(cl::Positional, cl::desc(""), cl::init("-")); @@ -47,7 +77,45 @@ static cl::opt cl::desc("Run the verifier after each transformation pass"), cl::init(true)); +void registerTestPasses() { + registerConvertToTargetEnvPass(); + registerInliner(); + registerMemRefBoundCheck(); + registerPassManagerTestPass(); + registerPatternsTestPass(); + registerSimpleParametricTilingPass(); + registerSymbolTestPasses(); + registerTestAllReduceLoweringPass(); + registerTestCallGraphPass(); + registerTestConstantFold(); + registerTestFunc(); + registerTestGpuMemoryPromotionPass(); + registerTestLinalgTransforms(); + registerTestLivenessPass(); + registerTestLoopFusion(); + registerTestLoopMappingPass(); + registerTestMatchers(); + registerTestMemRefDependenceCheck(); + registerTestMemRefStrideCalculation(); + registerTestOpaqueLoc(); + registerTestParallelismDetection(); + registerTestVectorConversions(); + registerTestVectorToLoopsPass(); + registerVectorizerTestPass(); + + // The following passes are using global initializers, just link them in. + if (std::getenv("bar") != (char *)-1) + return; + + // TODO: move these to the test folder. + createTestMemRefBoundCheckPass(); + createTestMemRefDependenceCheckPass(); +} + int main(int argc, char **argv) { + registerAllDialects(); + registerAllPasses(); + registerTestPasses(); InitLLVM y(argc, argv); // Register any pass manager command line options. diff --git a/mlir/tools/mlir-translate/CMakeLists.txt b/mlir/tools/mlir-translate/CMakeLists.txt index 9d585579060d..4b95a953e867 100644 --- a/mlir/tools/mlir-translate/CMakeLists.txt +++ b/mlir/tools/mlir-translate/CMakeLists.txt @@ -1,4 +1,5 @@ set(LIBS + MLIRAllDialects MLIRParser MLIRPass MLIRSPIRV @@ -9,9 +10,15 @@ set(LIBS MLIRTranslation MLIRSupport ) +set(FULL_LIBS + MLIRSPIRVSerialization + MLIRTargetLLVMIR + MLIRTargetNVVMIR + MLIRTargetROCDLIR +) add_llvm_tool(mlir-translate mlir-translate.cpp ) llvm_update_compile_flags(mlir-translate) -whole_archive_link(mlir-translate ${LIBS}) +whole_archive_link(mlir-translate ${FULL_LIBS}) target_link_libraries(mlir-translate PRIVATE MLIRIR MLIRTranslateClParser ${LIBS} LLVMSupport) diff --git a/mlir/tools/mlir-translate/mlir-translate.cpp b/mlir/tools/mlir-translate/mlir-translate.cpp index 5181436d7c8d..cd1b226deff7 100644 --- a/mlir/tools/mlir-translate/mlir-translate.cpp +++ b/mlir/tools/mlir-translate/mlir-translate.cpp @@ -13,6 +13,7 @@ #include "mlir/IR/Diagnostics.h" #include "mlir/IR/MLIRContext.h" +#include "mlir/InitAllDialects.h" #include "mlir/Support/FileUtilities.h" #include "mlir/Support/LogicalResult.h" #include "mlir/Support/ToolUtilities.h" @@ -45,6 +46,7 @@ static llvm::cl::opt verifyDiagnostics( llvm::cl::init(false)); int main(int argc, char **argv) { + registerAllDialects(); llvm::InitLLVM y(argc, argv); // Add flags for all the registered translations. diff --git a/mlir/unittests/Dialect/QuantOps/QuantizationUtilsTest.cpp b/mlir/unittests/Dialect/QuantOps/QuantizationUtilsTest.cpp index 46dc57fb4da3..e6188ea0de7e 100644 --- a/mlir/unittests/Dialect/QuantOps/QuantizationUtilsTest.cpp +++ b/mlir/unittests/Dialect/QuantOps/QuantizationUtilsTest.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "mlir/Dialect/QuantOps/QuantOps.h" #include "mlir/Dialect/QuantOps/QuantizeUtils.h" #include "mlir/Dialect/QuantOps/UniformSupport.h" #include "mlir/IR/Attributes.h" @@ -16,6 +17,9 @@ using namespace mlir; using namespace mlir::quant; +// Load the quant dialect +static DialectRegistration QuantOpsRegistration; + namespace { // Test UniformQuantizedValueConverter converts all APFloat to a magic number 5. diff --git a/mlir/unittests/Dialect/SPIRV/DeserializationTest.cpp b/mlir/unittests/Dialect/SPIRV/DeserializationTest.cpp index bcc3d1cb29ae..bee6a2d434b3 100644 --- a/mlir/unittests/Dialect/SPIRV/DeserializationTest.cpp +++ b/mlir/unittests/Dialect/SPIRV/DeserializationTest.cpp @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "mlir/Dialect/SPIRV/SPIRVBinaryUtils.h" +#include "mlir/Dialect/SPIRV/SPIRVDialect.h" #include "mlir/Dialect/SPIRV/SPIRVOps.h" #include "mlir/Dialect/SPIRV/Serialization.h" #include "mlir/IR/Diagnostics.h" @@ -23,6 +24,9 @@ using namespace mlir; +// Load the SPIRV dialect +static DialectRegistration SPIRVRegistration; + using ::testing::StrEq; //===----------------------------------------------------------------------===// diff --git a/mlir/unittests/SDBM/SDBMTest.cpp b/mlir/unittests/SDBM/SDBMTest.cpp index eadb3597f1dd..e599094ee592 100644 --- a/mlir/unittests/SDBM/SDBMTest.cpp +++ b/mlir/unittests/SDBM/SDBMTest.cpp @@ -17,6 +17,9 @@ using namespace mlir; +// Load the SDBM dialect +static DialectRegistration SDBMRegistration; + static MLIRContext *ctx() { static thread_local MLIRContext context; return &context; -- GitLab From 9f6ff07f8a396dfc736c4cb6f9fba9a203531329 Mon Sep 17 00:00:00 2001 From: Djordje Todorovic Date: Mon, 10 Feb 2020 11:06:44 +0100 Subject: [PATCH 138/142] [DebugInfo] Enable the debug entry values feature by default This patch enables the debug entry values feature. - Remove the (CC1) experimental -femit-debug-entry-values option - Enable it for x86, arm and aarch64 targets - Resolve the test failures - Leave the llc experimental option for targets that do not support the CallSiteInfo yet Differential Revision: https://reviews.llvm.org/D73534 --- clang/include/clang/Basic/CodeGenOptions.def | 1 - clang/include/clang/Driver/CC1Options.td | 2 - clang/lib/CodeGen/BackendUtil.cpp | 1 - clang/lib/CodeGen/CGDebugInfo.cpp | 3 +- clang/lib/Frontend/CompilerInvocation.cpp | 10 --- clang/test/CodeGen/debug-info-extern-call.c | 2 +- .../dbg-info-all-calls-described.cpp | 12 +-- .../Python/lldbsuite/test/decorators.py | 2 +- .../basic_entry_values_x86_64/Makefile | 2 +- llvm/include/llvm/CodeGen/CommandFlags.inc | 2 +- llvm/include/llvm/Target/TargetMachine.h | 3 + llvm/include/llvm/Target/TargetOptions.h | 15 +++- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 15 +++- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 9 ++ llvm/lib/CodeGen/LiveDebugValues.cpp | 4 +- llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 4 +- llvm/lib/CodeGen/MachineFunction.cpp | 3 +- .../SelectionDAG/ScheduleDAGSDNodes.cpp | 2 +- llvm/lib/CodeGen/TargetOptionsImpl.cpp | 8 ++ .../Target/AArch64/AArch64ISelLowering.cpp | 2 +- .../Target/AArch64/AArch64TargetMachine.cpp | 3 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 3 + llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 3 + llvm/test/CodeGen/ARM/smml.ll | 2 +- .../MIR/Hexagon/bundled-call-site-info.mir | 2 + .../CodeGen/MIR/X86/call-site-info-error1.mir | 2 +- .../CodeGen/MIR/X86/call-site-info-error2.mir | 2 +- .../CodeGen/MIR/X86/call-site-info-error3.mir | 2 +- .../CodeGen/MIR/X86/call-site-info-error4.mir | 4 +- .../test/CodeGen/X86/call-site-info-output.ll | 4 +- .../AArch64/call-site-info-output.ll | 2 +- .../DebugInfo/ARM/call-site-info-output.ll | 2 +- .../ARM/entry-value-multi-byte-expr.ll | 2 +- .../AArch64/dbgcall-site-interpret-movzxi.mir | 2 +- .../AArch64/dbgcall-site-interpretation.mir | 2 +- .../MIR/AArch64/dbgcall-site-orr-moves.mir | 2 +- .../MIR/ARM/dbgcall-site-interpretation.mir | 2 +- .../MIR/ARM/dbgcall-site-propagated-value.mir | 4 +- .../MIR/ARM/if-coverter-call-site-info.mir | 5 +- ...dbgcall-site-instr-before-bundled-call.mir | 4 +- ...live-debug-values-bundled-entry-values.mir | 2 + .../DebugInfo/MIR/SystemZ/call-site-lzer.mir | 2 + .../DebugInfo/MIR/X86/DW_OP_entry_value.mir | 2 +- .../MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir | 10 ++- .../MIR/X86/dbg-call-site-spilled-arg.mir | 4 +- .../MIR/X86/dbgcall-site-copy-super-sub.mir | 2 +- .../MIR/X86/dbgcall-site-interpretation.mir | 2 +- .../X86/dbgcall-site-lea-interpretation.mir | 2 +- .../MIR/X86/dbgcall-site-partial-describe.mir | 2 +- .../MIR/X86/dbgcall-site-reference.mir | 2 +- .../MIR/X86/dbgcall-site-reg-shuffle.mir | 2 +- .../MIR/X86/dbgcall-site-two-fwd-reg-defs.mir | 2 +- .../DebugInfo/MIR/X86/dbginfo-entryvals.mir | 2 +- .../MIR/X86/debug-call-site-param.mir | 4 +- .../MIR/X86/entry-value-of-modified-param.mir | 2 +- .../MIR/X86/entry-values-diamond-bbs.mir | 2 +- .../kill-entry-value-after-diamond-bbs.mir | 2 +- .../X86/multiple-param-dbg-value-entry.mir | 2 +- .../X86/propagate-entry-value-cross-bbs.mir | 2 +- .../MIR/X86/unreachable-block-call-site.mir | 2 +- .../Sparc/entry-value-complex-reg-expr.ll | 2 + llvm/test/DebugInfo/X86/dbg-value-range.ll | 2 +- .../X86/dbg-value-regmask-clobber.ll | 6 +- .../DebugInfo/X86/dbgcall-site-64-bit-imms.ll | 2 +- .../X86/dbgcall-site-zero-valued-imms.ll | 2 +- llvm/test/DebugInfo/X86/loclists-dwp.ll | 6 +- .../DebugInfo/X86/no-entry-values-with-O0.ll | 88 +++++++++++++++++++ .../test/tools/llvm-dwarfdump/X86/locstats.ll | 2 +- .../X86/stats-dbg-callsite-info.ll | 5 +- .../X86/valid-call-site-GNU-extensions.ll | 2 +- llvm/test/tools/llvm-locstats/locstats.ll | 6 +- 73 files changed, 234 insertions(+), 101 deletions(-) create mode 100644 llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index 48c0df49e32d..fa450724ddd4 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -63,7 +63,6 @@ CODEGENOPT(ExperimentalNewPassManager, 1, 0) ///< Enables the new, experimental CODEGENOPT(DebugPassManager, 1, 0) ///< Prints debug information for the new ///< pass manager. CODEGENOPT(DisableRedZone , 1, 0) ///< Set when -mno-red-zone is enabled. -CODEGENOPT(EnableDebugEntryValues, 1, 0) ///< Emit call site parameter dbg info CODEGENOPT(IndirectTlsSegRefs, 1, 0) ///< Set when -mno-tls-direct-seg-refs ///< is specified. CODEGENOPT(DisableTailCalls , 1, 0) ///< Do not emit tail calls. diff --git a/clang/include/clang/Driver/CC1Options.td b/clang/include/clang/Driver/CC1Options.td index 733a1080be52..8dcf28e34810 100644 --- a/clang/include/clang/Driver/CC1Options.td +++ b/clang/include/clang/Driver/CC1Options.td @@ -390,8 +390,6 @@ def flto_visibility_public_std: def flto_unit: Flag<["-"], "flto-unit">, HelpText<"Emit IR to support LTO unit features (CFI, whole program vtable opt)">; def fno_lto_unit: Flag<["-"], "fno-lto-unit">; -def femit_debug_entry_values : Flag<["-"], "femit-debug-entry-values">, - HelpText<"Enables debug info about call site parameter's entry values">; def fdebug_pass_manager : Flag<["-"], "fdebug-pass-manager">, HelpText<"Prints debug information for the new pass manager">; def fno_debug_pass_manager : Flag<["-"], "fno-debug-pass-manager">, diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 48e26459e94f..033a2898c5a8 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -481,7 +481,6 @@ static void initTargetOptions(llvm::TargetOptions &Options, Options.DebuggerTuning = CodeGenOpts.getDebuggerTuning(); Options.EmitStackSizeSection = CodeGenOpts.StackSizeSection; Options.EmitAddrsig = CodeGenOpts.Addrsig; - Options.EnableDebugEntryValues = CodeGenOpts.EnableDebugEntryValues; Options.ForceDwarfFrameSection = CodeGenOpts.ForceDwarfFrameSection; Options.MCOptions.SplitDwarfFile = CodeGenOpts.SplitDwarfFile; diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index e171082942f6..f706ffb92a0e 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -4861,8 +4861,7 @@ llvm::DINode::DIFlags CGDebugInfo::getCallSiteRelatedAttrs() const { (CGM.getCodeGenOpts().getDebuggerTuning() == llvm::DebuggerKind::LLDB || CGM.getCodeGenOpts().getDebuggerTuning() == llvm::DebuggerKind::GDB); - if (!SupportsDWARFv4Ext && CGM.getCodeGenOpts().DwarfVersion < 5 && - !CGM.getCodeGenOpts().EnableDebugEntryValues) + if (!SupportsDWARFv4Ext && CGM.getCodeGenOpts().DwarfVersion < 5) return llvm::DINode::FlagZero; return llvm::DINode::FlagAllCallsDescribed; diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index ae39066edd4c..dca80562b445 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -792,16 +792,6 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK, Opts.DisableLLVMPasses = Args.hasArg(OPT_disable_llvm_passes); Opts.DisableLifetimeMarkers = Args.hasArg(OPT_disable_lifetimemarkers); - - const llvm::Triple::ArchType DebugEntryValueArchs[] = { - llvm::Triple::x86, llvm::Triple::x86_64, llvm::Triple::aarch64, - llvm::Triple::arm, llvm::Triple::armeb}; - - llvm::Triple T(TargetOpts.Triple); - if (Opts.OptimizationLevel > 0 && Opts.hasReducedDebugInfo() && - llvm::is_contained(DebugEntryValueArchs, T.getArch())) - Opts.EnableDebugEntryValues = Args.hasArg(OPT_femit_debug_entry_values); - Opts.DisableO0ImplyOptNone = Args.hasArg(OPT_disable_O0_optnone); Opts.DisableRedZone = Args.hasArg(OPT_disable_red_zone); Opts.IndirectTlsSegRefs = Args.hasArg(OPT_mno_tls_direct_seg_refs); diff --git a/clang/test/CodeGen/debug-info-extern-call.c b/clang/test/CodeGen/debug-info-extern-call.c index da3764f7359e..072e578b5898 100644 --- a/clang/test/CodeGen/debug-info-extern-call.c +++ b/clang/test/CodeGen/debug-info-extern-call.c @@ -1,7 +1,7 @@ // When entry values are emitted, expect a subprogram for extern decls so that // the dwarf generator can describe call site parameters at extern call sites. // -// RUN: %clang -Xclang -femit-debug-entry-values -g -O2 -target x86_64-none-linux-gnu -S -emit-llvm %s -o - \ +// RUN: %clang -g -O2 -target x86_64-none-linux-gnu -S -emit-llvm %s -o - \ // RUN: | FileCheck %s -check-prefix=DECLS-FOR-EXTERN // Similarly, when the debugger tuning is gdb, expect a subprogram for extern diff --git a/clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp b/clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp index 667c2469b55e..540ef02c908a 100644 --- a/clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp +++ b/clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp @@ -15,22 +15,22 @@ // RUN: | FileCheck %s -check-prefix=HAS-ATTR \ // RUN: -implicit-check-not=DISubprogram -implicit-check-not=DIFlagAllCallsDescribed -// Supported: DWARF4 + GDB tuning by using '-femit-debug-entry-values' -// RUN: %clang_cc1 -femit-debug-entry-values -emit-llvm -triple x86_64-linux-gnu \ +// Supported: DWARF4 + GDB tuning, -O1 +// RUN: %clang_cc1 -emit-llvm -triple x86_64-linux-gnu \ // RUN: %s -o - -O1 -disable-llvm-passes -debugger-tuning=gdb \ // RUN: -debug-info-kind=standalone -dwarf-version=4 \ // RUN: | FileCheck %s -check-prefix=HAS-ATTR \ // RUN: -implicit-check-not=DIFlagAllCallsDescribed -// Supported: DWARF4 + LLDB tuning by using '-femit-debug-entry-values' -// RUN: %clang_cc1 -femit-debug-entry-values -emit-llvm -triple x86_64-linux-gnu \ +// Supported: DWARF4 + LLDB tuning, -O1 +// RUN: %clang_cc1 -emit-llvm -triple x86_64-linux-gnu \ // RUN: %s -o - -O1 -disable-llvm-passes -debugger-tuning=lldb \ // RUN: -debug-info-kind=standalone -dwarf-version=4 \ // RUN: | FileCheck %s -check-prefix=HAS-ATTR \ // RUN: -implicit-check-not=DIFlagAllCallsDescribed -// Unsupported: -O0 + '-femit-debug-entry-values' -// RUN: %clang_cc1 -femit-debug-entry-values -emit-llvm -triple x86_64-linux-gnu \ +// Unsupported: -O0 +// RUN: %clang_cc1 -emit-llvm -triple x86_64-linux-gnu \ // RUN: %s -o - -O0 -disable-llvm-passes -debugger-tuning=gdb \ // RUN: -debug-info-kind=standalone -dwarf-version=4 \ // RUN: | FileCheck %s -check-prefix=NO-ATTR diff --git a/lldb/packages/Python/lldbsuite/test/decorators.py b/lldb/packages/Python/lldbsuite/test/decorators.py index ec17cb7c2569..39cda3a81954 100644 --- a/lldb/packages/Python/lldbsuite/test/decorators.py +++ b/lldb/packages/Python/lldbsuite/test/decorators.py @@ -694,7 +694,7 @@ def skipUnlessHasCallSiteInfo(func): f = tempfile.NamedTemporaryFile() cmd = "echo 'int main() {}' | " \ - "%s -g -glldb -O1 -Xclang -femit-debug-entry-values -S -emit-llvm -x c -o %s -" % (compiler_path, f.name) + "%s -g -glldb -O1 -S -emit-llvm -x c -o %s -" % (compiler_path, f.name) if os.popen(cmd).close() is not None: return "Compiler can't compile with call site info enabled" diff --git a/lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile b/lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile index db8fa57abb91..ab505a684126 100644 --- a/lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile +++ b/lldb/test/API/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile @@ -1,3 +1,3 @@ CXX_SOURCES := main.cpp -CXXFLAGS_EXTRAS := -O2 -glldb -Xclang -femit-debug-entry-values +CXXFLAGS_EXTRAS := -O2 -glldb include Makefile.rules diff --git a/llvm/include/llvm/CodeGen/CommandFlags.inc b/llvm/include/llvm/CodeGen/CommandFlags.inc index e12293461759..8b676655d2d3 100644 --- a/llvm/include/llvm/CodeGen/CommandFlags.inc +++ b/llvm/include/llvm/CodeGen/CommandFlags.inc @@ -277,7 +277,7 @@ static cl::opt static cl::opt EnableDebugEntryValues("debug-entry-values", - cl::desc("Emit debug info about parameter's entry values"), + cl::desc("Enable debug info for the debug entry values"), cl::init(false)); static cl::opt diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index 176ae39b17a7..3c2e2fe1a37f 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -237,6 +237,9 @@ public: void setSupportsDefaultOutlining(bool Enable) { Options.SupportsDefaultOutlining = Enable; } + void setSupportsDebugEntryValues(bool Enable) { + Options.SupportsDebugEntryValues = Enable; + } bool shouldPrintMachineCode() const { return Options.PrintMachineCode; } diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h index 84c6ee2a6387..535909cc77c3 100644 --- a/llvm/include/llvm/Target/TargetOptions.h +++ b/llvm/include/llvm/Target/TargetOptions.h @@ -119,7 +119,8 @@ namespace llvm { ExplicitEmulatedTLS(false), EnableIPRA(false), EmitStackSizeSection(false), EnableMachineOutliner(false), SupportsDefaultOutlining(false), EmitAddrsig(false), - EnableDebugEntryValues(false), ForceDwarfFrameSection(false) {} + SupportsDebugEntryValues(false), EnableDebugEntryValues(false), + ForceDwarfFrameSection(false) {} /// PrintMachineCode - This flag is enabled when the -print-machineinstrs /// option is specified on the command line, and should enable debugging @@ -256,8 +257,18 @@ namespace llvm { /// Emit address-significance table. unsigned EmitAddrsig : 1; - /// Emit debug info about parameter's entry values. + /// Set if the target supports the debug entry values by default. + unsigned SupportsDebugEntryValues : 1; + /// When set to true, the EnableDebugEntryValues option forces production + /// of debug entry values even if the target does not officially support + /// it. Useful for testing purposes only. This flag should never be checked + /// directly, always use \ref ShouldEmitDebugEntryValues instead. unsigned EnableDebugEntryValues : 1; + /// NOTE: There are targets that still do not support the call site info + /// production (the info about the arguments passed to the call, necessary + /// for the debug entry values), so we keep using the experimental option + /// (-debug-entry-values) to test them as well. + bool ShouldEmitDebugEntryValues() const; /// Emit DWARF debug frame section. unsigned ForceDwarfFrameSection : 1; diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index c1e7d9fe0211..cbfbf62a4866 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -95,6 +95,10 @@ static cl::opt UseDwarfRangesBaseAddressSpecifier( "use-dwarf-ranges-base-address-specifier", cl::Hidden, cl::desc("Use base address specifiers in debug_ranges"), cl::init(false)); +static cl::opt EmitDwarfDebugEntryValues( + "emit-debug-entry-values", cl::Hidden, + cl::desc("Emit the debug entry values"), cl::init(false)); + static cl::opt GenerateARangeSection("generate-arange-section", cl::Hidden, cl::desc("Generate dwarf aranges"), @@ -419,6 +423,12 @@ DwarfDebug::DwarfDebug(AsmPrinter *A, Module *M) // a monolithic string offsets table without any header. UseSegmentedStringOffsetsTable = DwarfVersion >= 5; + // Emit call-site-param debug info for GDB and LLDB, if the target supports + // the debug entry values feature. It can also be enabled explicitly. + EmitDebugEntryValues = (Asm->TM.Options.ShouldEmitDebugEntryValues() && + (tuneForGDB() || tuneForLLDB())) || + EmitDwarfDebugEntryValues; + Asm->OutStreamer->getContext().setDwarfVersion(DwarfVersion); } @@ -840,9 +850,8 @@ void DwarfDebug::constructCallSiteEntryDIEs(const DISubprogram &SP, DIE &CallSiteDIE = CU.constructCallSiteEntryDIE(ScopeDIE, CalleeDIE, IsTail, PCAddr, CallReg); - // GDB and LLDB support call site parameter debug info. - if (Asm->TM.Options.EnableDebugEntryValues && - (tuneForGDB() || tuneForLLDB())) { + // Optionally emit call-site-param debug info. + if (emitDebugEntryValues()) { ParamSet Params; // Try to interpret values of call site parameters. collectCallSiteParameters(&MI, Params); diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h index a44960589d89..882fc739d792 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h @@ -386,6 +386,11 @@ class DwarfDebug : public DebugHandlerBase { /// a monolithic sequence of string offsets. bool UseSegmentedStringOffsetsTable; + /// Enable production of call site parameters needed to print the debug entry + /// values. Useful for testing purposes when a debugger does not support the + /// feature yet. + bool EmitDebugEntryValues; + /// Separated Dwarf Variables /// In general these will all be for bits that are left in the /// original object file, rather than things that are meant @@ -708,6 +713,10 @@ public: return UseSegmentedStringOffsetsTable; } + bool emitDebugEntryValues() const { + return EmitDebugEntryValues; + } + bool shareAcrossDWOCUs() const; /// Returns the Dwarf Version. diff --git a/llvm/lib/CodeGen/LiveDebugValues.cpp b/llvm/lib/CodeGen/LiveDebugValues.cpp index 6acaf4099c3e..a07fd4028123 100644 --- a/llvm/lib/CodeGen/LiveDebugValues.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues.cpp @@ -960,7 +960,7 @@ void LiveDebugValues::transferRegisterDef( if (auto *TPC = getAnalysisIfAvailable()) { auto &TM = TPC->getTM(); - if (TM.Options.EnableDebugEntryValues) + if (TM.Options.ShouldEmitDebugEntryValues()) emitEntryValues(MI, OpenRanges, VarLocIDs, Transfers, KillSet); } } @@ -1460,7 +1460,7 @@ void LiveDebugValues::recordEntryValue(const MachineInstr &MI, VarLocMap &VarLocIDs) { if (auto *TPC = getAnalysisIfAvailable()) { auto &TM = TPC->getTM(); - if (!TM.Options.EnableDebugEntryValues) + if (!TM.Options.ShouldEmitDebugEntryValues()) return; } diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 10157c746b46..69d14cf68eca 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -381,11 +381,11 @@ bool MIRParserImpl::initializeCallSiteInfo( CSInfo.emplace_back(Reg, ArgRegPair.ArgNo); } - if (TM.Options.EnableDebugEntryValues) + if (TM.Options.ShouldEmitDebugEntryValues()) MF.addCallArgsForwardingRegs(&*CallI, std::move(CSInfo)); } - if (YamlMF.CallSitesInfo.size() && !TM.Options.EnableDebugEntryValues) + if (YamlMF.CallSitesInfo.size() && !TM.Options.ShouldEmitDebugEntryValues()) return error(Twine("Call site info provided but not used")); return false; } diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index 06b5ab5b7f4c..2eb8d9460e05 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -865,8 +865,7 @@ MachineFunction::CallSiteInfoMap::iterator MachineFunction::getCallSiteInfo(const MachineInstr *MI) { assert(MI->isCandidateForCallSiteEntry() && "Call site info refers only to call (MI) candidates"); - - if (!Target.Options.EnableDebugEntryValues) + if (!Target.Options.ShouldEmitDebugEntryValues()) return CallSitesInfo.end(); return CallSitesInfo.find(MI); } diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 7bded0005a51..ea0bcd1fd888 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -867,7 +867,7 @@ EmitSchedule(MachineBasicBlock::iterator &InsertPos) { } if (MI->isCandidateForCallSiteEntry() && - DAG->getTarget().Options.EnableDebugEntryValues) + DAG->getTarget().Options.SupportsDebugEntryValues) MF.addCallArgsForwardingRegs(MI, DAG->getSDCallSiteInfo(Node)); return MI; diff --git a/llvm/lib/CodeGen/TargetOptionsImpl.cpp b/llvm/lib/CodeGen/TargetOptionsImpl.cpp index d794a261ecb2..3db0f2f2829a 100644 --- a/llvm/lib/CodeGen/TargetOptionsImpl.cpp +++ b/llvm/lib/CodeGen/TargetOptionsImpl.cpp @@ -45,3 +45,11 @@ bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const { bool TargetOptions::HonorSignDependentRoundingFPMath() const { return !UnsafeFPMath && HonorSignDependentRoundingFPMathOption; } + +/// NOTE: There are targets that still do not support the call site info +/// production (the info about the arguments passed to the call, necessary +/// for the debug entry values), so we keep using the experimental option +/// (-debug-entry-values) to test them as well. +bool TargetOptions::ShouldEmitDebugEntryValues() const { + return SupportsDebugEntryValues || EnableDebugEntryValues; +} diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index e01762e2ca9b..57dc51d068fd 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4169,7 +4169,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, RegsToPass.emplace_back(VA.getLocReg(), Arg); RegsUsed.insert(VA.getLocReg()); const TargetOptions &Options = DAG.getTarget().Options; - if (Options.EnableDebugEntryValues) + if (Options.SupportsDebugEntryValues) CSInfo.emplace_back(VA.getLocReg(), i); } } else { diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index bc7b4384662a..d50bd090aeee 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -309,6 +309,9 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT, // AArch64 supports default outlining behaviour. setSupportsDefaultOutlining(true); + + // AArch64 supports the debug entry values. + setSupportsDebugEntryValues(true); } AArch64TargetMachine::~AArch64TargetMachine() = default; diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index bd82c8f64400..f6ee9c07bd40 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2223,7 +2223,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, isThisReturn = true; } const TargetOptions &Options = DAG.getTarget().Options; - if (Options.EnableDebugEntryValues) + if (Options.SupportsDebugEntryValues) CSInfo.emplace_back(VA.getLocReg(), i); RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); } else if (isByVal) { diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 84876eda33a6..63aa65267ef2 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -243,6 +243,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT, this->Options.NoTrapAfterNoreturn = true; } + // ARM supports the debug entry values. + setSupportsDebugEntryValues(true); + initAsmInfo(); } diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8cd177aa302f..60b06546f544 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -4020,7 +4020,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } else if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); const TargetOptions &Options = DAG.getTarget().Options; - if (Options.EnableDebugEntryValues) + if (Options.SupportsDebugEntryValues) CSInfo.emplace_back(VA.getLocReg(), I); if (isVarArg && IsWin64) { // Win64 ABI requires argument XMM reg to be copied to the corresponding diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp index 22b4e2805a5e..0cfa7bb04771 100644 --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -232,6 +232,9 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT, setMachineOutliner(true); + // x86 supports the debug entry values. + setSupportsDebugEntryValues(true); + initAsmInfo(); } diff --git a/llvm/test/CodeGen/ARM/smml.ll b/llvm/test/CodeGen/ARM/smml.ll index 712aaa4392f6..9ddb1a28301d 100644 --- a/llvm/test/CodeGen/ARM/smml.ll +++ b/llvm/test/CodeGen/ARM/smml.ll @@ -10,7 +10,7 @@ ; Next test would previously trigger an assertion responsible for verification of ; call site info state. -; RUN: llc -stop-after=if-converter -debug-entry-values -mtriple=thumbv6t2-eabi %s -o -| FileCheck %s -check-prefix=CHECK-CALLSITE +; RUN: llc -stop-after=if-converter -mtriple=thumbv6t2-eabi %s -o -| FileCheck %s -check-prefix=CHECK-CALLSITE ; CHECK-CALLSITE: name: test_used_flags ; CHECK-CALLSITE: callSites: diff --git a/llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir b/llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir index 5ffa0293a2e1..96a9411af311 100644 --- a/llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir +++ b/llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir @@ -1,3 +1,5 @@ +# We do not support the call site info for the target now, so we use the experimental option (-debug-entry-values). + # RUN: llc -debug-entry-values -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s # Verify that it is possible to read and write MIR where a callSites entry diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir b/llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir index 096a80f77dbb..c28e1d7084ff 100644 --- a/llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir +++ b/llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=x86_64-- -run-pass none -debug-entry-values %s -o - 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64-- -run-pass none %s -o - 2>&1 | FileCheck %s # CHECK: baa call instruction block out of range. Unable to reference bb:1 --- | define dso_local i32 @baa(i32 %a) local_unnamed_addr { diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir b/llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir index bd5b2451a8d7..ca26a738f6e5 100644 --- a/llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir +++ b/llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=x86_64-- -run-pass none -debug-entry-values %s -o - 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64-- -run-pass none %s -o - 2>&1 | FileCheck %s # CHECK: baa call instruction offset out of range. Unable to reference instruction at bb: 0 at offset:1 --- | define dso_local i32 @baa(i32 %a) local_unnamed_addr { diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir b/llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir index ded9fd2bb1bc..3271a8b3a80c 100644 --- a/llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir +++ b/llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=x86_64-- -run-pass none -debug-entry-values %s -o - 2>&1 | FileCheck %s +# RUN: not llc -mtriple=x86_64-- -run-pass none %s -o - 2>&1 | FileCheck %s # CHECK: baa call site info should reference call instruction. Instruction at bb:0 at offset:0 is not a call instruction --- | define dso_local i32 @baa(i32 %a) local_unnamed_addr { diff --git a/llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir b/llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir index 2472aa707e16..8f71d2b21da3 100644 --- a/llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir +++ b/llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir @@ -1,5 +1,5 @@ -# RUN: not llc -mtriple=x86_64-- -run-pass none %s -o - 2>&1 | FileCheck %s -# CHECK: Call site info provided but not used +# RUN: llc -mtriple=x86_64-- -run-pass none %s -o - 2>&1 | FileCheck %s +# CHECK-NOT: Call site info provided but not used --- | define dso_local i32 @baa(i32 %a) local_unnamed_addr { entry: diff --git a/llvm/test/CodeGen/X86/call-site-info-output.ll b/llvm/test/CodeGen/X86/call-site-info-output.ll index 4b1e236aadfe..8586d34762db 100644 --- a/llvm/test/CodeGen/X86/call-site-info-output.ll +++ b/llvm/test/CodeGen/X86/call-site-info-output.ll @@ -1,6 +1,6 @@ ; Test call site info MIR printer and parser.Parser assertions and machine ; verifier will check the rest; -; RUN: llc -debug-entry-values %s -stop-before=finalize-isel -o %t.mir +; RUN: llc %s -stop-before=finalize-isel -o %t.mir ; RUN: cat %t.mir | FileCheck %s ; CHECK: name: fn2 ; CHECK: callSites: @@ -10,7 +10,7 @@ ; CHECK-NEXT: arg: 0, reg: '$edi' ; CHECK-NEXT: arg: 1, reg: '$esi' ; CHECK-NEXT: arg: 2, reg: '$edx' -; RUN: llc -debug-entry-values %t.mir -run-pass=finalize-isel -o -| FileCheck %s --check-prefix=PARSER +; RUN: llc %t.mir -run-pass=finalize-isel -o -| FileCheck %s --check-prefix=PARSER ; Verify that we are able to parse output mir and that we are getting the same result. ; PARSER: name: fn2 ; PARSER: callSites: diff --git a/llvm/test/DebugInfo/AArch64/call-site-info-output.ll b/llvm/test/DebugInfo/AArch64/call-site-info-output.ll index d52d6962f3c4..6817aabd602b 100644 --- a/llvm/test/DebugInfo/AArch64/call-site-info-output.ll +++ b/llvm/test/DebugInfo/AArch64/call-site-info-output.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple aarch64-linux-gnu -debug-entry-values %s -o - -stop-before=finalize-isel | FileCheck %s +; RUN: llc -mtriple aarch64-linux-gnu %s -o - -stop-before=finalize-isel | FileCheck %s ; Verify that Selection DAG knows how to recognize simple function parameter forwarding registers. ; Produced from: ; extern int fn1(int,int,int); diff --git a/llvm/test/DebugInfo/ARM/call-site-info-output.ll b/llvm/test/DebugInfo/ARM/call-site-info-output.ll index 9255a7d57dde..e1cd900aefb1 100644 --- a/llvm/test/DebugInfo/ARM/call-site-info-output.ll +++ b/llvm/test/DebugInfo/ARM/call-site-info-output.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple arm-linux-gnu -debug-entry-values %s -o - -stop-before=finalize-isel | FileCheck %s +; RUN: llc -mtriple arm-linux-gnu %s -o - -stop-before=finalize-isel | FileCheck %s ; Verify that Selection DAG knows how to recognize simple function parameter forwarding registers. ; Produced from: ; extern int fn1(int,int,int); diff --git a/llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll b/llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll index 71cf41782720..4c5a38161c70 100644 --- a/llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll +++ b/llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll @@ -1,4 +1,4 @@ -; RUN: llc -debug-entry-values -filetype=asm -o - %s | FileCheck %s +; RUN: llc -filetype=asm -o - %s | FileCheck %s ; Verify that the size operands of the DW_OP_GNU_entry_value operations are ; correct for the multi-byte DW_OP_regx expressions. diff --git a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir index dc7561ca6400..8fdfe37d7db5 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple aarch64-linux-gnu -debug-entry-values -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s +# RUN: llc -mtriple aarch64-linux-gnu -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s # # Based on the following C reproducer: # diff --git a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir index 0371ccef603e..559a11d3d536 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple aarch64-linux-gnu -debug-entry-values -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s +# RUN: llc -mtriple aarch64-linux-gnu -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s # Following code is used for producing this test case. Note that # some of argument loading instruction are modified in order to # cover certain cases. diff --git a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir index 9d4feaccf9e7..72540049612f 100644 --- a/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir +++ b/llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -start-after=livedebugvalues -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s +# RUN: llc -start-after=livedebugvalues -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s # Based on the following C reproducer: # diff --git a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir index ce8dc97f0e72..507250d0e5a1 100644 --- a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=arm-linux-gnueabi -debug-entry-values -filetype=obj -start-after=machineverifier %s -o -| llvm-dwarfdump -| FileCheck %s +# RUN: llc -mtriple=arm-linux-gnueabi -filetype=obj -start-after=machineverifier %s -o -| llvm-dwarfdump -| FileCheck %s # Following code is used for producing this test case. Note that # some of argument loading instruction are modified in order to # cover certain cases. diff --git a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir index 9001c8ba8eea..13012a7dc106 100644 --- a/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir +++ b/llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -o - %s | FileCheck %s +# RUN: llc -run-pass=livedebugvalues -o - %s | FileCheck %s # Based on the following C reproducer: # @@ -20,7 +20,7 @@ # # Generated using: # -# clang -Os -fno-inline -Xclang -femit-debug-entry-values -g --target=armeb. +# clang -Os -fno-inline -g --target=armeb. --- | target datalayout = "E-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" diff --git a/llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir b/llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir index aa7b54c1e5bb..b2b9580cdc7b 100644 --- a/llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir +++ b/llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=arm-linux-gnu -debug-entry-values -run-pass if-converter %s -o -| FileCheck %s +# RUN: llc -mtriple=arm-linux-gnu -run-pass if-converter %s -o -| FileCheck %s # Vefify that the call site info will be updated after the optimization. # This test case would previously trigger an assertion when @@ -19,8 +19,7 @@ # # With slight change of MIR - substitution of BL instruction with BL_pred # in order to trigger optimization. -# clang -target arm-linux-gnu -g -O2 -Xclang -femit-debug-entry-values -# %s -stop-before=if-convert +# clang -target arm-linux-gnu -g -O2 %s -stop-before=if-convert # # CHECK: callSites: # CHECK-NEXT: - { bb: {{.*}}, offset: {{.*}}, fwdArgRegs: diff --git a/llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir b/llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir index 8ae628af2c09..a86cd7f7a440 100644 --- a/llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir +++ b/llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir @@ -1,4 +1,6 @@ -# RUN: llc -mtriple hexagon -debug-entry-values -start-after=machineverifier -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s +# We do not support the call site info for the target now, so we use the experimental option (-debug-entry-values). + +# RUN: llc -debug-entry-values -mtriple hexagon -start-after=machineverifier -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s # Based on the following C reproducer: # diff --git a/llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir b/llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir index ff0a539dd15d..956db574c59d 100644 --- a/llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir +++ b/llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir @@ -1,3 +1,5 @@ +# We do not support the call site info for the target now, so we use the experimental option (-debug-entry-values). + # RUN: llc -debug-entry-values -run-pass=livedebugvalues -o - %s | FileCheck %s # Verify that the entry values for the input parameters are inserted after the diff --git a/llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir b/llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir index 8a4e8b5632c2..4f06b1a639e5 100644 --- a/llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir +++ b/llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir @@ -1,3 +1,5 @@ +# We do not support the call site info for the target now, so we use the experimental option (-debug-entry-values). + # RUN: llc -debug-entry-values -start-after=livedebugvalues -o - %s | FileCheck %s # This test would previously trigger an assertion when trying to describe the diff --git a/llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir b/llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir index e6fe5d2de878..f7f74b628d16 100644 --- a/llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir +++ b/llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -start-before=livedebugvalues -mtriple=x86_64-apple-darwin -o %t %s -filetype=obj +# RUN: llc -start-before=livedebugvalues -mtriple=x86_64-apple-darwin -o %t %s -filetype=obj # RUN: llvm-dwarfdump %t | FileCheck %s # # int global; diff --git a/llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir b/llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir index 1c5922ce76f0..0718878e0faa 100644 --- a/llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir +++ b/llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir @@ -1,14 +1,18 @@ # Test the call site encoding in DWARF5 vs GNU extensions. # -# RUN: llc -dwarf-version 4 -debugger-tune=gdb -debug-entry-values -filetype=obj \ +# RUN: llc -dwarf-version 4 -debugger-tune=gdb -filetype=obj \ # RUN: -mtriple=x86_64-unknown-unknown -start-after=machineverifier -o - %s \ # RUN: | llvm-dwarfdump - | FileCheck %s -check-prefixes=CHECK-GNU # -# RUN: llc -dwarf-version 5 -debugger-tune=lldb -debug-entry-values -filetype=obj \ +# RUN: llc -dwarf-version 5 -debugger-tune=lldb -filetype=obj \ # RUN: -mtriple=x86_64-unknown-unknown -start-after=machineverifier -o - %s \ # RUN: | llvm-dwarfdump - | FileCheck %s -check-prefixes=CHECK-DWARF5 # -# RUN: llc -dwarf-version 5 -debug-entry-values -filetype=obj \ +# RUN: llc -dwarf-version 5 -filetype=obj \ +# RUN: -mtriple=x86_64-unknown-unknown -start-after=machineverifier -o - %s \ +# RUN: | llvm-dwarfdump - | FileCheck %s -check-prefixes=CHECK-DWARF5 +# +# RUN: llc -dwarf-version 5 -filetype=obj -debugger-tune=sce -emit-debug-entry-values \ # RUN: -mtriple=x86_64-unknown-unknown -start-after=machineverifier -o - %s \ # RUN: | llvm-dwarfdump - | FileCheck %s -check-prefixes=CHECK-DWARF5 # diff --git a/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir b/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir index c32a1155d038..0d161fe26c06 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir @@ -1,9 +1,9 @@ # Check that llvm can describe a call site parameter which resides in a spill slot. # -# RUN: llc -debug-entry-values -start-after=machineverifier -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s +# RUN: llc -start-after=machineverifier -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s # # Command: -# $ ~/src/builds/llvm-project-master-RA/bin/clang -g -Xclang -femit-debug-entry-values -O2 -c -o spill.o spill.cc -mllvm -stop-before=machineverifier -o spill.mir +# $ ~/src/builds/llvm-project-master-RA/bin/clang -g -O2 -c -o spill.o spill.cc -mllvm -stop-before=machineverifier -o spill.mir # # Source: ## extern void callee(int); diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir index a2d51a203512..271a9c101e77 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -start-after=livedebugvalues -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s +# RUN: llc -start-after=livedebugvalues -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s # Based on the following reproducer: # diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir index dc3a425e5690..5204bae67aed 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s +# RUN: llc -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s # # CHECK: DW_TAG_GNU_call_site # CHECK-NEXT: DW_AT_abstract_origin {{.*}} "foo" diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir index 1bb70f6d4530..4530ab6eae99 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s +# RUN: llc -start-after=machineverifier -filetype=obj %s -o -| llvm-dwarfdump -| FileCheck %s # CHECK: DW_TAG_GNU_call_site # CHECK-NEXT: DW_AT_abstract_origin {{.*}} "foo") # CHECK-NEXT: DW_AT_low_pc {{.*}} diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir index 377409518432..580eefb9234f 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -start-before=livedebugvalues -filetype=obj -o - %s \ +# RUN: llc -start-before=livedebugvalues -filetype=obj -o - %s \ # RUN: | llvm-dwarfdump - | FileCheck %s --implicit-check-not=DW_TAG_GNU_call_site_parameter --- | diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir index 235787573f51..73927772ca08 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -start-before=livedebugvalues -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s +# RUN: llc -start-before=livedebugvalues -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s # Based on the following C++ code: # struct A { A(A &) {} }; diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir index 5b934f6dc533..c9bed340bbcd 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -start-before=livedebugvalues -filetype=obj -o - %s \ +# RUN: llc -start-before=livedebugvalues -filetype=obj -o - %s \ # RUN: | llvm-dwarfdump - | FileCheck %s --implicit-check-not=DW_TAG_GNU_call_site_parameter --- | diff --git a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir index 4e1b8fdb5bef..77b26c398ba7 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir @@ -1,4 +1,4 @@ -# RUN: llc -O1 -debug-entry-values -start-after=livedebugvalues -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s +# RUN: llc -O1 -start-after=livedebugvalues -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s # Based on the following C reproducer: # diff --git a/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir b/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir index 5d203029936e..6c6b4ddb46d7 100644 --- a/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir +++ b/llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s +# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s # #extern void fn2(int); # diff --git a/llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir b/llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir index caee15c2a9e6..dfbca43e571f 100644 --- a/llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir +++ b/llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir @@ -2,8 +2,8 @@ # When the debugger tuning is set to gdb, use GNU opcodes. # For lldb, use the standard DWARF5 opcodes. -# RUN: llc -debug-entry-values -debugger-tune=gdb -filetype=obj -mtriple=x86_64-unknown-unknown -start-after=machineverifier -o - %s | llvm-dwarfdump - | FileCheck %s -check-prefixes=CHECK-GNU -# RUN: llc -debug-entry-values -debugger-tune=lldb -filetype=obj -mtriple=x86_64-unknown-unknown -start-after=machineverifier -o - %s | llvm-dwarfdump - | FileCheck %s -check-prefixes=CHECK-DWARF5 +# RUN: llc -debugger-tune=gdb -filetype=obj -mtriple=x86_64-unknown-unknown -start-after=machineverifier -o - %s | llvm-dwarfdump - | FileCheck %s -check-prefixes=CHECK-GNU +# RUN: llc -debugger-tune=lldb -filetype=obj -mtriple=x86_64-unknown-unknown -start-after=machineverifier -o - %s | llvm-dwarfdump - | FileCheck %s -check-prefixes=CHECK-DWARF5 # # extern void foo(int *a, int b, int c, int d, int e, int f); # extern int getVal(); diff --git a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir index adc43d96a961..b37f6557ae68 100644 --- a/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir +++ b/llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s +# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s # #extern void fn1 (int, int, int); # diff --git a/llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir b/llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir index 2396daada876..f2f02e809522 100644 --- a/llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir +++ b/llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s +# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s # # The test case was artificially adjusted, in order to make proper diamond basic # block structure relevant to the debug entry values propagation. diff --git a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir index 0109dc47ef36..7152080923c3 100644 --- a/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir +++ b/llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s +# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s # # The test case was artificially adjusted, in order to make proper diamond basic # block structure relevant to the debug entry values clobbering. diff --git a/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir b/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir index fd154ed6a731..be3fc00a1b78 100644 --- a/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir +++ b/llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s| FileCheck %s +# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s| FileCheck %s # #int global; #int foo(int p, int q, int r) { diff --git a/llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir b/llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir index 86b1cddaa462..e24f90ff2706 100644 --- a/llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir +++ b/llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir @@ -1,4 +1,4 @@ -# RUN: llc -debug-entry-values -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s +# RUN: llc -run-pass=livedebugvalues -march=x86-64 -o - %s | FileCheck %s # #extern void fn1 (int, int, int); #__attribute__((noinline)) diff --git a/llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir b/llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir index d282d796f6d7..66d799162e04 100644 --- a/llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir +++ b/llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=x86_64-pc-linux -debug-entry-values -run-pass=unreachable-mbb-elimination -o - %s | FileCheck %s +# RUN: llc -mtriple=x86_64-pc-linux -run-pass=unreachable-mbb-elimination -o - %s | FileCheck %s # Verify that the call site information for the call residing in the eliminated # block is removed. This test case would previously trigger an assertion when diff --git a/llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll b/llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll index 0af5619b75d7..cfe8a3d0da04 100644 --- a/llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll +++ b/llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll @@ -1,3 +1,5 @@ +; We do not support the call site info for the target now, so we use the experimental option (-debug-entry-values). + ; RUN: llc -debug-entry-values -filetype=asm -o - %s | FileCheck %s ; Verify that the entry value covers both of the DW_OP_regx pieces. Previously diff --git a/llvm/test/DebugInfo/X86/dbg-value-range.ll b/llvm/test/DebugInfo/X86/dbg-value-range.ll index e0cfe5f15ee9..9159d2aac780 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-range.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-range.ll @@ -56,6 +56,6 @@ declare void @llvm.dbg.value(metadata, metadata, metadata) nounwind readnone ;CHECK-NEXT: .quad [[CLOBBER_OFF]] ;CHECK-NEXT: .short 1 ## Loc expr size ;CHECK-NEXT: .byte 85 ## DW_OP_reg -;CHECK-NEXT: .quad 0 +;CHECK: .quad 0 ;CHECK-NEXT: .quad 0 !24 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll b/llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll index 440498a9d8dd..425a6cb38c41 100644 --- a/llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll +++ b/llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll @@ -9,8 +9,7 @@ ; ASM: movl $1, x(%rip) ; ASM: callq clobber ; ASM-NEXT: [[argc_range_end:.Ltmp[0-9]+]]: -; Previously LiveDebugValues would claim argc was still in ecx after the call. -; ASM-NOT: #DEBUG_VALUE: main:argc +; ASM: #DEBUG_VALUE: main:argc <- [DW_OP_LLVM_entry_value 1] $ecx ; argc is the first debug location. ; ASM: .Ldebug_loc1: @@ -23,7 +22,8 @@ ; DWARF: .debug_info contents: ; DWARF: DW_TAG_formal_parameter ; DWARF-NEXT: DW_AT_location ({{0x.*}} -; DWARF-NEXT: [0x0000000000000000, 0x0000000000000013): DW_OP_reg2 RCX) +; DWARF-NEXT: [0x0000000000000000, 0x0000000000000013): DW_OP_reg2 RCX +; DWARF-NEXT: [0x0000000000000013, 0x0000000000000043): DW_OP_GNU_entry_value(DW_OP_reg2 RCX), DW_OP_stack_value ; DWARF-NEXT: DW_AT_name ("argc") ; ModuleID = 't.cpp' diff --git a/llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll b/llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll index b698f1cdbfe8..c25d614f9d55 100644 --- a/llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll +++ b/llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll @@ -1,4 +1,4 @@ -; RUN: llc -O1 -debug-entry-values -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s +; RUN: llc -O1 -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s ; Verify that the 64-bit call site immediates are not truncated. ; diff --git a/llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll b/llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll index 9fe67f82a2b4..1900a6ae0023 100644 --- a/llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll +++ b/llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -debug-entry-values -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s +; RUN: llc -O3 -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/DebugInfo/X86/loclists-dwp.ll b/llvm/test/DebugInfo/X86/loclists-dwp.ll index 91f838876338..a972c8094c5f 100644 --- a/llvm/test/DebugInfo/X86/loclists-dwp.ll +++ b/llvm/test/DebugInfo/X86/loclists-dwp.ll @@ -19,10 +19,12 @@ ; void b(int i) { asm("" : : : "rdi"); } ; CHECK: DW_AT_location [DW_FORM_sec_offset] (0x00000000 -; CHECK-NEXT: DW_LLE_startx_length (0x0000000000000000, 0x0000000000000006): DW_OP_reg5 RDI) +; CHECK-NEXT: DW_LLE_startx_length (0x0000000000000000, 0x0000000000000006): DW_OP_reg5 RDI +; CHECK-NEXT: DW_LLE_startx_length (0x0000000000000001, 0x0000000000000002): DW_OP_GNU_entry_value(DW_OP_reg5 RDI), DW_OP_stack_value) ; CHECK: DW_AT_location [DW_FORM_sec_offset] (0x00000000 -; CHECK-NEXT: DW_LLE_startx_length (0x0000000000000000, 0x0000000000000000): DW_OP_reg5 RDI) +; CHECK-NEXT: DW_LLE_startx_length (0x0000000000000000, 0x0000000000000000): DW_OP_reg5 RDI +; CHECK-NEXT: DW_LLE_startx_length (0x0000000000000001, 0x0000000000000001): DW_OP_GNU_entry_value(DW_OP_reg5 RDI), DW_OP_stack_value) target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll b/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll new file mode 100644 index 000000000000..8ba22b7b6e51 --- /dev/null +++ b/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll @@ -0,0 +1,88 @@ +; RUN: llc -O0 -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \ +; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s +; RUN: llc -O0 -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \ +; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s + +; The call-site-params are created iff corresponding DISubprogram contains +; the AllCallsDescribed DIFlag. +; CHECK-NOT: DW_TAG_call_site_param + +; Genarated with: +; clang -gdwarf-5 -O0 test.c -S -emit-llvm +; +; ModuleID = 'test.c' +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; Function Attrs: noinline nounwind optnone uwtable +define dso_local void @fn1(i32 %x, i32 %y) !dbg !7 { +entry: + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + %u = alloca i32, align 4 + %a = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !11, metadata !DIExpression()), !dbg !12 + store i32 %y, i32* %y.addr, align 4 + call void @llvm.dbg.declare(metadata i32* %y.addr, metadata !13, metadata !DIExpression()), !dbg !14 + call void @llvm.dbg.declare(metadata i32* %u, metadata !15, metadata !DIExpression()), !dbg !16 + %0 = load i32, i32* %x.addr, align 4, !dbg !16 + %1 = load i32, i32* %y.addr, align 4, !dbg !16 + %add = add nsw i32 %0, %1, !dbg !16 + store i32 %add, i32* %u, align 4, !dbg !16 + %2 = load i32, i32* %x.addr, align 4, !dbg !17 + %cmp = icmp sgt i32 %2, 1, !dbg !17 + br i1 %cmp, label %if.then, label %if.else, !dbg !16 + +if.then: ; preds = %entry + %3 = load i32, i32* %u, align 4, !dbg !17 + %add1 = add nsw i32 %3, 1, !dbg !17 + store i32 %add1, i32* %u, align 4, !dbg !17 + br label %if.end, !dbg !17 + +if.else: ; preds = %entry + %4 = load i32, i32* %u, align 4, !dbg !17 + %add2 = add nsw i32 %4, 2, !dbg !17 + store i32 %add2, i32* %u, align 4, !dbg !17 + br label %if.end + +if.end: ; preds = %if.else, %if.then + call void @llvm.dbg.declare(metadata i32* %a, metadata !19, metadata !DIExpression()), !dbg !16 + store i32 7, i32* %a, align 4, !dbg !16 + %5 = load i32, i32* %a, align 4, !dbg !16 + call void @fn2(i32 %5), !dbg !16 + %6 = load i32, i32* %u, align 4, !dbg !16 + %dec = add nsw i32 %6, -1, !dbg !16 + store i32 %dec, i32* %u, align 4, !dbg !16 + ret void, !dbg !16 +} + +; Function Attrs: nounwind readnone speculatable willreturn +declare void @llvm.dbg.declare(metadata, metadata, metadata) + +declare dso_local void @fn2(i32) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 11.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.c", directory: "/") +!2 = !{} +!3 = !{i32 7, !"Dwarf Version", i32 5} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{!"clang version 11.0.0"} +!7 = distinct !DISubprogram(name: "fn1", scope: !1, file: !1, line: 5, type: !8, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2) +!8 = !DISubroutineType(types: !9) +!9 = !{null, !10, !10} +!10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!11 = !DILocalVariable(name: "x", arg: 1, scope: !7, file: !1, line: 5, type: !10) +!12 = !DILocation(line: 5, column: 10, scope: !7) +!13 = !DILocalVariable(name: "y", arg: 2, scope: !7, file: !1, line: 5, type: !10) +!14 = !DILocation(line: 5, column: 17, scope: !7) +!15 = !DILocalVariable(name: "u", scope: !7, file: !1, line: 6, type: !10) +!16 = !DILocation(line: 6, column: 7, scope: !7) +!17 = !DILocation(line: 7, column: 7, scope: !18) +!18 = distinct !DILexicalBlock(scope: !7, file: !1, line: 7, column: 7) +!19 = !DILocalVariable(name: "a", scope: !7, file: !1, line: 11, type: !10) diff --git a/llvm/test/tools/llvm-dwarfdump/X86/locstats.ll b/llvm/test/tools/llvm-dwarfdump/X86/locstats.ll index 7521806c624f..ca9140f5fabd 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/locstats.ll +++ b/llvm/test/tools/llvm-dwarfdump/X86/locstats.ll @@ -1,4 +1,4 @@ -; RUN: llc -debug-entry-values %s -o - -filetype=obj \ +; RUN: llc %s -o - -filetype=obj \ ; RUN: | llvm-dwarfdump -statistics - | FileCheck %s ; ; CHECK: "entry value scope bytes covered":5 diff --git a/llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll b/llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll index c304e9d768a5..8601dc3595f7 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll +++ b/llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll @@ -1,9 +1,6 @@ -; RUN: llc -debug-entry-values %s -o - -filetype=obj \ +; RUN: llc %s -o - -filetype=obj \ ; RUN: | llvm-dwarfdump -statistics - | FileCheck %s ; -; The LLVM IR file was generated on this source code by using -; option '-femit-debug-entry-values'. -; ; extern void foo(int *a, int b, int c, int d, int e, int f); ; extern int getVal(); ; diff --git a/llvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll b/llvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll index 935f3a2d1d35..acb875bd0f13 100644 --- a/llvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll +++ b/llvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll @@ -1,4 +1,4 @@ -; RUN: llc -debug-entry-values %s -o - -filetype=obj \ +; RUN: llc %s -o - -filetype=obj \ ; RUN: | llvm-dwarfdump -verify - | FileCheck %s ; ; CHECK: No errors. diff --git a/llvm/test/tools/llvm-locstats/locstats.ll b/llvm/test/tools/llvm-locstats/locstats.ll index f16635d2e8e4..fd28679f3ec1 100644 --- a/llvm/test/tools/llvm-locstats/locstats.ll +++ b/llvm/test/tools/llvm-locstats/locstats.ll @@ -9,9 +9,9 @@ ; LOCSTATS: [10%,20%) 0 0% ; LOCSTATS: [20%,30%) 1 11% ; LOCSTATS: [30%,40%) 0 0% -; LOCSTATS: [40%,50%) 1 11% -; LOCSTATS: [50%,60%) 1 11% -; LOCSTATS: [60%,70%) 1 11% +; LOCSTATS: [40%,50%) 0 0% +; LOCSTATS: [50%,60%) 0 0% +; LOCSTATS: [60%,70%) 3 33% ; LOCSTATS: [70%,80%) 0 0% ; LOCSTATS: [80%,90%) 2 22% ; LOCSTATS: [90%,100%) 1 11% -- GitLab From 3bd33ccfdf2f5183062e775e99725930bb4e5403 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Wed, 12 Feb 2020 12:27:38 +0300 Subject: [PATCH 139/142] [NFC?][SCEV][LoopVectorize] Add datalayout to the X86/float-induction-x86.ll test Summary: Currently, `SCEVExpander::isHighCostExpansionHelper()` has the following logic: ``` if (auto *UDivExpr = dyn_cast(S)) { // If the divisor is a power of two and the SCEV type fits in a native // integer (and the LHS not expensive), consider the division cheap // irrespective of whether it occurs in the user code since it can be // lowered into a right shift. if (auto *SC = dyn_cast(UDivExpr->getRHS())) if (SC->getAPInt().isPowerOf2()) { if (isHighCostExpansionHelper(UDivExpr->getLHS(), L, At, BudgetRemaining, TTI, Processed)) return true; const DataLayout &DL = L->getHeader()->getParent()->getParent()->getDataLayout(); unsigned Width = cast(UDivExpr->getType())->getBitWidth(); return DL.isIllegalInteger(Width); } ``` Since this test does not have a datalayout specified, `SCEVExpander::isHighCostExpansionHelper()` says that `[[TMP2:%.*]] = lshr exact i64 [[TMP1]], 5` is high-cost, and didn't perform it. But future patches will change that logic to solely rely on cost-model, without any such datalayout checks, so i think it is best to show that that change is ephemeral, and can already happen without costmodel changes. Reviewers: reames, fhahn, sanjoy, craig.topper, RKSimon Reviewed By: RKSimon Subscribers: javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73717 --- .../LoopVectorize/X86/float-induction-x86.ll | 262 +++++++++++++++--- 1 file changed, 222 insertions(+), 40 deletions(-) diff --git a/llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll b/llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll index 7266d8e0bb42..bfa9c727950f 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -O3 -simplifycfg -keep-loops=false -mcpu=core-avx2 -mtriple=x86_64-unknown-linux-gnu -S | FileCheck --check-prefix AUTO_VEC %s +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + ; This test checks auto-vectorization with FP induction variable. ; The FP operation is not "fast" and requires "fast-math" function attribute. @@ -26,29 +28,119 @@ define void @fp_iv_loop1(float* noalias nocapture %A, i32 %N) #0 { ; AUTO_VEC-NEXT: [[CAST_CRD:%.*]] = sitofp i64 [[N_VEC]] to float ; AUTO_VEC-NEXT: [[TMP0:%.*]] = fmul fast float [[CAST_CRD]], 5.000000e-01 ; AUTO_VEC-NEXT: [[IND_END:%.*]] = fadd fast float [[TMP0]], 1.000000e+00 +; AUTO_VEC-NEXT: [[TMP1:%.*]] = add nsw i64 [[N_VEC]], -32 +; AUTO_VEC-NEXT: [[TMP2:%.*]] = lshr exact i64 [[TMP1]], 5 +; AUTO_VEC-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1 +; AUTO_VEC-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP3]], 3 +; AUTO_VEC-NEXT: [[TMP4:%.*]] = icmp ult i64 [[TMP1]], 96 +; AUTO_VEC-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK_UNR_LCSSA:%.*]], label [[VECTOR_PH_NEW:%.*]] +; AUTO_VEC: vector.ph.new: +; AUTO_VEC-NEXT: [[UNROLL_ITER:%.*]] = sub nsw i64 [[TMP3]], [[XTRAITER]] ; AUTO_VEC-NEXT: br label [[VECTOR_BODY:%.*]] ; AUTO_VEC: vector.body: -; AUTO_VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; AUTO_VEC-NEXT: [[VEC_IND:%.*]] = phi <8 x float> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH_NEW]] ], [ [[INDEX_NEXT_3:%.*]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[VEC_IND:%.*]] = phi <8 x float> [ , [[VECTOR_PH_NEW]] ], [ [[VEC_IND_NEXT_3:%.*]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[NITER:%.*]] = phi i64 [ [[UNROLL_ITER]], [[VECTOR_PH_NEW]] ], [ [[NITER_NSUB_3:%.*]], [[VECTOR_BODY]] ] ; AUTO_VEC-NEXT: [[STEP_ADD:%.*]] = fadd fast <8 x float> [[VEC_IND]], ; AUTO_VEC-NEXT: [[STEP_ADD5:%.*]] = fadd fast <8 x float> [[VEC_IND]], ; AUTO_VEC-NEXT: [[STEP_ADD6:%.*]] = fadd fast <8 x float> [[VEC_IND]], -; AUTO_VEC-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[INDEX]] -; AUTO_VEC-NEXT: [[TMP2:%.*]] = bitcast float* [[TMP1]] to <8 x float>* -; AUTO_VEC-NEXT: store <8 x float> [[VEC_IND]], <8 x float>* [[TMP2]], align 4 -; AUTO_VEC-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 8 -; AUTO_VEC-NEXT: [[TMP4:%.*]] = bitcast float* [[TMP3]] to <8 x float>* -; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD]], <8 x float>* [[TMP4]], align 4 -; AUTO_VEC-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 16 +; AUTO_VEC-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[INDEX]] ; AUTO_VEC-NEXT: [[TMP6:%.*]] = bitcast float* [[TMP5]] to <8 x float>* -; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD5]], <8 x float>* [[TMP6]], align 4 -; AUTO_VEC-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 24 +; AUTO_VEC-NEXT: store <8 x float> [[VEC_IND]], <8 x float>* [[TMP6]], align 4 +; AUTO_VEC-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 8 ; AUTO_VEC-NEXT: [[TMP8:%.*]] = bitcast float* [[TMP7]] to <8 x float>* -; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD6]], <8 x float>* [[TMP8]], align 4 -; AUTO_VEC-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 32 -; AUTO_VEC-NEXT: [[VEC_IND_NEXT]] = fadd fast <8 x float> [[VEC_IND]], -; AUTO_VEC-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; AUTO_VEC-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0 +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD]], <8 x float>* [[TMP8]], align 4 +; AUTO_VEC-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 16 +; AUTO_VEC-NEXT: [[TMP10:%.*]] = bitcast float* [[TMP9]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD5]], <8 x float>* [[TMP10]], align 4 +; AUTO_VEC-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 24 +; AUTO_VEC-NEXT: [[TMP12:%.*]] = bitcast float* [[TMP11]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD6]], <8 x float>* [[TMP12]], align 4 +; AUTO_VEC-NEXT: [[INDEX_NEXT:%.*]] = or i64 [[INDEX]], 32 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD_1:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD5_1:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD6_1:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDEX_NEXT]] +; AUTO_VEC-NEXT: [[TMP14:%.*]] = bitcast float* [[TMP13]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[VEC_IND_NEXT]], <8 x float>* [[TMP14]], align 4 +; AUTO_VEC-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 8 +; AUTO_VEC-NEXT: [[TMP16:%.*]] = bitcast float* [[TMP15]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD_1]], <8 x float>* [[TMP16]], align 4 +; AUTO_VEC-NEXT: [[TMP17:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 16 +; AUTO_VEC-NEXT: [[TMP18:%.*]] = bitcast float* [[TMP17]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD5_1]], <8 x float>* [[TMP18]], align 4 +; AUTO_VEC-NEXT: [[TMP19:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 24 +; AUTO_VEC-NEXT: [[TMP20:%.*]] = bitcast float* [[TMP19]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD6_1]], <8 x float>* [[TMP20]], align 4 +; AUTO_VEC-NEXT: [[INDEX_NEXT_1:%.*]] = or i64 [[INDEX]], 64 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT_1:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD_2:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD5_2:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD6_2:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[TMP21:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDEX_NEXT_1]] +; AUTO_VEC-NEXT: [[TMP22:%.*]] = bitcast float* [[TMP21]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[VEC_IND_NEXT_1]], <8 x float>* [[TMP22]], align 4 +; AUTO_VEC-NEXT: [[TMP23:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 8 +; AUTO_VEC-NEXT: [[TMP24:%.*]] = bitcast float* [[TMP23]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD_2]], <8 x float>* [[TMP24]], align 4 +; AUTO_VEC-NEXT: [[TMP25:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 16 +; AUTO_VEC-NEXT: [[TMP26:%.*]] = bitcast float* [[TMP25]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD5_2]], <8 x float>* [[TMP26]], align 4 +; AUTO_VEC-NEXT: [[TMP27:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 24 +; AUTO_VEC-NEXT: [[TMP28:%.*]] = bitcast float* [[TMP27]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD6_2]], <8 x float>* [[TMP28]], align 4 +; AUTO_VEC-NEXT: [[INDEX_NEXT_2:%.*]] = or i64 [[INDEX]], 96 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT_2:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD_3:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD5_3:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD6_3:%.*]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[TMP29:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDEX_NEXT_2]] +; AUTO_VEC-NEXT: [[TMP30:%.*]] = bitcast float* [[TMP29]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[VEC_IND_NEXT_2]], <8 x float>* [[TMP30]], align 4 +; AUTO_VEC-NEXT: [[TMP31:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 8 +; AUTO_VEC-NEXT: [[TMP32:%.*]] = bitcast float* [[TMP31]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD_3]], <8 x float>* [[TMP32]], align 4 +; AUTO_VEC-NEXT: [[TMP33:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 16 +; AUTO_VEC-NEXT: [[TMP34:%.*]] = bitcast float* [[TMP33]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD5_3]], <8 x float>* [[TMP34]], align 4 +; AUTO_VEC-NEXT: [[TMP35:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 24 +; AUTO_VEC-NEXT: [[TMP36:%.*]] = bitcast float* [[TMP35]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD6_3]], <8 x float>* [[TMP36]], align 4 +; AUTO_VEC-NEXT: [[INDEX_NEXT_3]] = add i64 [[INDEX]], 128 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT_3]] = fadd fast <8 x float> [[VEC_IND]], +; AUTO_VEC-NEXT: [[NITER_NSUB_3]] = add i64 [[NITER]], -4 +; AUTO_VEC-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NSUB_3]], 0 +; AUTO_VEC-NEXT: br i1 [[NITER_NCMP_3]], label [[MIDDLE_BLOCK_UNR_LCSSA]], label [[VECTOR_BODY]], !llvm.loop !0 +; AUTO_VEC: middle.block.unr-lcssa: +; AUTO_VEC-NEXT: [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT_3]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[VEC_IND_UNR:%.*]] = phi <8 x float> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT_3]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[LCMP_MOD:%.*]] = icmp eq i64 [[XTRAITER]], 0 +; AUTO_VEC-NEXT: br i1 [[LCMP_MOD]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY_EPIL:%.*]] +; AUTO_VEC: vector.body.epil: +; AUTO_VEC-NEXT: [[INDEX_EPIL:%.*]] = phi i64 [ [[INDEX_NEXT_EPIL:%.*]], [[VECTOR_BODY_EPIL]] ], [ [[INDEX_UNR]], [[MIDDLE_BLOCK_UNR_LCSSA]] ] +; AUTO_VEC-NEXT: [[VEC_IND_EPIL:%.*]] = phi <8 x float> [ [[VEC_IND_NEXT_EPIL:%.*]], [[VECTOR_BODY_EPIL]] ], [ [[VEC_IND_UNR]], [[MIDDLE_BLOCK_UNR_LCSSA]] ] +; AUTO_VEC-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ [[EPIL_ITER_SUB:%.*]], [[VECTOR_BODY_EPIL]] ], [ [[XTRAITER]], [[MIDDLE_BLOCK_UNR_LCSSA]] ] +; AUTO_VEC-NEXT: [[STEP_ADD_EPIL:%.*]] = fadd fast <8 x float> [[VEC_IND_EPIL]], +; AUTO_VEC-NEXT: [[STEP_ADD5_EPIL:%.*]] = fadd fast <8 x float> [[VEC_IND_EPIL]], +; AUTO_VEC-NEXT: [[STEP_ADD6_EPIL:%.*]] = fadd fast <8 x float> [[VEC_IND_EPIL]], +; AUTO_VEC-NEXT: [[TMP37:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDEX_EPIL]] +; AUTO_VEC-NEXT: [[TMP38:%.*]] = bitcast float* [[TMP37]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[VEC_IND_EPIL]], <8 x float>* [[TMP38]], align 4 +; AUTO_VEC-NEXT: [[TMP39:%.*]] = getelementptr inbounds float, float* [[TMP37]], i64 8 +; AUTO_VEC-NEXT: [[TMP40:%.*]] = bitcast float* [[TMP39]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD_EPIL]], <8 x float>* [[TMP40]], align 4 +; AUTO_VEC-NEXT: [[TMP41:%.*]] = getelementptr inbounds float, float* [[TMP37]], i64 16 +; AUTO_VEC-NEXT: [[TMP42:%.*]] = bitcast float* [[TMP41]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD5_EPIL]], <8 x float>* [[TMP42]], align 4 +; AUTO_VEC-NEXT: [[TMP43:%.*]] = getelementptr inbounds float, float* [[TMP37]], i64 24 +; AUTO_VEC-NEXT: [[TMP44:%.*]] = bitcast float* [[TMP43]] to <8 x float>* +; AUTO_VEC-NEXT: store <8 x float> [[STEP_ADD6_EPIL]], <8 x float>* [[TMP44]], align 4 +; AUTO_VEC-NEXT: [[INDEX_NEXT_EPIL]] = add i64 [[INDEX_EPIL]], 32 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT_EPIL]] = fadd fast <8 x float> [[VEC_IND_EPIL]], +; AUTO_VEC-NEXT: [[EPIL_ITER_SUB]] = add i64 [[EPIL_ITER]], -1 +; AUTO_VEC-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp eq i64 [[EPIL_ITER_SUB]], 0 +; AUTO_VEC-NEXT: br i1 [[EPIL_ITER_CMP]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY_EPIL]], !llvm.loop !2 ; AUTO_VEC: middle.block: ; AUTO_VEC-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[ZEXT]] ; AUTO_VEC-NEXT: br i1 [[CMP_N]], label [[FOR_END]], label [[FOR_BODY]] @@ -59,8 +151,8 @@ define void @fp_iv_loop1(float* noalias nocapture %A, i32 %N) #0 { ; AUTO_VEC-NEXT: store float [[X_06]], float* [[ARRAYIDX]], align 4 ; AUTO_VEC-NEXT: [[CONV1]] = fadd float [[X_06]], 5.000000e-01 ; AUTO_VEC-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -; AUTO_VEC-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[ZEXT]] -; AUTO_VEC-NEXT: br i1 [[TMP10]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop !2 +; AUTO_VEC-NEXT: [[TMP45:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[ZEXT]] +; AUTO_VEC-NEXT: br i1 [[TMP45]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop !4 ; AUTO_VEC: for.end: ; AUTO_VEC-NEXT: ret void ; @@ -167,7 +259,7 @@ define void @fp_iv_loop2(float* noalias nocapture %A, i32 %N) #1 { ; AUTO_VEC-NEXT: [[INDVARS_IV_NEXT_EPIL]] = add nuw nsw i64 [[INDVARS_IV_EPIL]], 1 ; AUTO_VEC-NEXT: [[EPIL_ITER_SUB]] = add i64 [[EPIL_ITER]], -1 ; AUTO_VEC-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp eq i64 [[EPIL_ITER_SUB]], 0 -; AUTO_VEC-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_END]], label [[FOR_BODY_EPIL]], !llvm.loop !4 +; AUTO_VEC-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_END]], label [[FOR_BODY_EPIL]], !llvm.loop !6 ; AUTO_VEC: for.end: ; AUTO_VEC-NEXT: ret void ; @@ -207,34 +299,124 @@ define double @external_use_with_fast_math(double* %a, i64 %n) { ; AUTO_VEC-NEXT: [[N_VEC:%.*]] = and i64 [[SMAX]], 9223372036854775792 ; AUTO_VEC-NEXT: [[CAST_CRD:%.*]] = sitofp i64 [[N_VEC]] to double ; AUTO_VEC-NEXT: [[TMP1:%.*]] = fmul fast double [[CAST_CRD]], 3.000000e+00 +; AUTO_VEC-NEXT: [[TMP2:%.*]] = add nsw i64 [[N_VEC]], -16 +; AUTO_VEC-NEXT: [[TMP3:%.*]] = lshr exact i64 [[TMP2]], 4 +; AUTO_VEC-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1 +; AUTO_VEC-NEXT: [[XTRAITER:%.*]] = and i64 [[TMP4]], 3 +; AUTO_VEC-NEXT: [[TMP5:%.*]] = icmp ult i64 [[TMP2]], 48 +; AUTO_VEC-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK_UNR_LCSSA:%.*]], label [[VECTOR_PH_NEW:%.*]] +; AUTO_VEC: vector.ph.new: +; AUTO_VEC-NEXT: [[UNROLL_ITER:%.*]] = sub nsw i64 [[TMP4]], [[XTRAITER]] ; AUTO_VEC-NEXT: br label [[VECTOR_BODY:%.*]] ; AUTO_VEC: vector.body: -; AUTO_VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; AUTO_VEC-NEXT: [[VEC_IND:%.*]] = phi <4 x double> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH_NEW]] ], [ [[INDEX_NEXT_3:%.*]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[VEC_IND:%.*]] = phi <4 x double> [ , [[VECTOR_PH_NEW]] ], [ [[VEC_IND_NEXT_3:%.*]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[NITER:%.*]] = phi i64 [ [[UNROLL_ITER]], [[VECTOR_PH_NEW]] ], [ [[NITER_NSUB_3:%.*]], [[VECTOR_BODY]] ] ; AUTO_VEC-NEXT: [[STEP_ADD:%.*]] = fadd fast <4 x double> [[VEC_IND]], ; AUTO_VEC-NEXT: [[STEP_ADD5:%.*]] = fadd fast <4 x double> [[VEC_IND]], ; AUTO_VEC-NEXT: [[STEP_ADD6:%.*]] = fadd fast <4 x double> [[VEC_IND]], -; AUTO_VEC-NEXT: [[TMP2:%.*]] = getelementptr double, double* [[A:%.*]], i64 [[INDEX]] -; AUTO_VEC-NEXT: [[TMP3:%.*]] = bitcast double* [[TMP2]] to <4 x double>* -; AUTO_VEC-NEXT: store <4 x double> [[VEC_IND]], <4 x double>* [[TMP3]], align 8 -; AUTO_VEC-NEXT: [[TMP4:%.*]] = getelementptr double, double* [[TMP2]], i64 4 -; AUTO_VEC-NEXT: [[TMP5:%.*]] = bitcast double* [[TMP4]] to <4 x double>* -; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD]], <4 x double>* [[TMP5]], align 8 -; AUTO_VEC-NEXT: [[TMP6:%.*]] = getelementptr double, double* [[TMP2]], i64 8 +; AUTO_VEC-NEXT: [[TMP6:%.*]] = getelementptr double, double* [[A:%.*]], i64 [[INDEX]] ; AUTO_VEC-NEXT: [[TMP7:%.*]] = bitcast double* [[TMP6]] to <4 x double>* -; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD5]], <4 x double>* [[TMP7]], align 8 -; AUTO_VEC-NEXT: [[TMP8:%.*]] = getelementptr double, double* [[TMP2]], i64 12 +; AUTO_VEC-NEXT: store <4 x double> [[VEC_IND]], <4 x double>* [[TMP7]], align 8 +; AUTO_VEC-NEXT: [[TMP8:%.*]] = getelementptr double, double* [[TMP6]], i64 4 ; AUTO_VEC-NEXT: [[TMP9:%.*]] = bitcast double* [[TMP8]] to <4 x double>* -; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD6]], <4 x double>* [[TMP9]], align 8 -; AUTO_VEC-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 16 -; AUTO_VEC-NEXT: [[VEC_IND_NEXT]] = fadd fast <4 x double> [[VEC_IND]], -; AUTO_VEC-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; AUTO_VEC-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !6 +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD]], <4 x double>* [[TMP9]], align 8 +; AUTO_VEC-NEXT: [[TMP10:%.*]] = getelementptr double, double* [[TMP6]], i64 8 +; AUTO_VEC-NEXT: [[TMP11:%.*]] = bitcast double* [[TMP10]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD5]], <4 x double>* [[TMP11]], align 8 +; AUTO_VEC-NEXT: [[TMP12:%.*]] = getelementptr double, double* [[TMP6]], i64 12 +; AUTO_VEC-NEXT: [[TMP13:%.*]] = bitcast double* [[TMP12]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD6]], <4 x double>* [[TMP13]], align 8 +; AUTO_VEC-NEXT: [[INDEX_NEXT:%.*]] = or i64 [[INDEX]], 16 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD_1:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD5_1:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD6_1:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[TMP14:%.*]] = getelementptr double, double* [[A]], i64 [[INDEX_NEXT]] +; AUTO_VEC-NEXT: [[TMP15:%.*]] = bitcast double* [[TMP14]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[VEC_IND_NEXT]], <4 x double>* [[TMP15]], align 8 +; AUTO_VEC-NEXT: [[TMP16:%.*]] = getelementptr double, double* [[TMP14]], i64 4 +; AUTO_VEC-NEXT: [[TMP17:%.*]] = bitcast double* [[TMP16]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD_1]], <4 x double>* [[TMP17]], align 8 +; AUTO_VEC-NEXT: [[TMP18:%.*]] = getelementptr double, double* [[TMP14]], i64 8 +; AUTO_VEC-NEXT: [[TMP19:%.*]] = bitcast double* [[TMP18]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD5_1]], <4 x double>* [[TMP19]], align 8 +; AUTO_VEC-NEXT: [[TMP20:%.*]] = getelementptr double, double* [[TMP14]], i64 12 +; AUTO_VEC-NEXT: [[TMP21:%.*]] = bitcast double* [[TMP20]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD6_1]], <4 x double>* [[TMP21]], align 8 +; AUTO_VEC-NEXT: [[INDEX_NEXT_1:%.*]] = or i64 [[INDEX]], 32 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT_1:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD_2:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD5_2:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD6_2:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[TMP22:%.*]] = getelementptr double, double* [[A]], i64 [[INDEX_NEXT_1]] +; AUTO_VEC-NEXT: [[TMP23:%.*]] = bitcast double* [[TMP22]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[VEC_IND_NEXT_1]], <4 x double>* [[TMP23]], align 8 +; AUTO_VEC-NEXT: [[TMP24:%.*]] = getelementptr double, double* [[TMP22]], i64 4 +; AUTO_VEC-NEXT: [[TMP25:%.*]] = bitcast double* [[TMP24]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD_2]], <4 x double>* [[TMP25]], align 8 +; AUTO_VEC-NEXT: [[TMP26:%.*]] = getelementptr double, double* [[TMP22]], i64 8 +; AUTO_VEC-NEXT: [[TMP27:%.*]] = bitcast double* [[TMP26]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD5_2]], <4 x double>* [[TMP27]], align 8 +; AUTO_VEC-NEXT: [[TMP28:%.*]] = getelementptr double, double* [[TMP22]], i64 12 +; AUTO_VEC-NEXT: [[TMP29:%.*]] = bitcast double* [[TMP28]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD6_2]], <4 x double>* [[TMP29]], align 8 +; AUTO_VEC-NEXT: [[INDEX_NEXT_2:%.*]] = or i64 [[INDEX]], 48 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT_2:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD_3:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD5_3:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[STEP_ADD6_3:%.*]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[TMP30:%.*]] = getelementptr double, double* [[A]], i64 [[INDEX_NEXT_2]] +; AUTO_VEC-NEXT: [[TMP31:%.*]] = bitcast double* [[TMP30]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[VEC_IND_NEXT_2]], <4 x double>* [[TMP31]], align 8 +; AUTO_VEC-NEXT: [[TMP32:%.*]] = getelementptr double, double* [[TMP30]], i64 4 +; AUTO_VEC-NEXT: [[TMP33:%.*]] = bitcast double* [[TMP32]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD_3]], <4 x double>* [[TMP33]], align 8 +; AUTO_VEC-NEXT: [[TMP34:%.*]] = getelementptr double, double* [[TMP30]], i64 8 +; AUTO_VEC-NEXT: [[TMP35:%.*]] = bitcast double* [[TMP34]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD5_3]], <4 x double>* [[TMP35]], align 8 +; AUTO_VEC-NEXT: [[TMP36:%.*]] = getelementptr double, double* [[TMP30]], i64 12 +; AUTO_VEC-NEXT: [[TMP37:%.*]] = bitcast double* [[TMP36]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD6_3]], <4 x double>* [[TMP37]], align 8 +; AUTO_VEC-NEXT: [[INDEX_NEXT_3]] = add i64 [[INDEX]], 64 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT_3]] = fadd fast <4 x double> [[VEC_IND]], +; AUTO_VEC-NEXT: [[NITER_NSUB_3]] = add i64 [[NITER]], -4 +; AUTO_VEC-NEXT: [[NITER_NCMP_3:%.*]] = icmp eq i64 [[NITER_NSUB_3]], 0 +; AUTO_VEC-NEXT: br i1 [[NITER_NCMP_3]], label [[MIDDLE_BLOCK_UNR_LCSSA]], label [[VECTOR_BODY]], !llvm.loop !7 +; AUTO_VEC: middle.block.unr-lcssa: +; AUTO_VEC-NEXT: [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT_3]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[VEC_IND_UNR:%.*]] = phi <4 x double> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT_3]], [[VECTOR_BODY]] ] +; AUTO_VEC-NEXT: [[LCMP_MOD:%.*]] = icmp eq i64 [[XTRAITER]], 0 +; AUTO_VEC-NEXT: br i1 [[LCMP_MOD]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY_EPIL:%.*]] +; AUTO_VEC: vector.body.epil: +; AUTO_VEC-NEXT: [[INDEX_EPIL:%.*]] = phi i64 [ [[INDEX_NEXT_EPIL:%.*]], [[VECTOR_BODY_EPIL]] ], [ [[INDEX_UNR]], [[MIDDLE_BLOCK_UNR_LCSSA]] ] +; AUTO_VEC-NEXT: [[VEC_IND_EPIL:%.*]] = phi <4 x double> [ [[VEC_IND_NEXT_EPIL:%.*]], [[VECTOR_BODY_EPIL]] ], [ [[VEC_IND_UNR]], [[MIDDLE_BLOCK_UNR_LCSSA]] ] +; AUTO_VEC-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ [[EPIL_ITER_SUB:%.*]], [[VECTOR_BODY_EPIL]] ], [ [[XTRAITER]], [[MIDDLE_BLOCK_UNR_LCSSA]] ] +; AUTO_VEC-NEXT: [[STEP_ADD_EPIL:%.*]] = fadd fast <4 x double> [[VEC_IND_EPIL]], +; AUTO_VEC-NEXT: [[STEP_ADD5_EPIL:%.*]] = fadd fast <4 x double> [[VEC_IND_EPIL]], +; AUTO_VEC-NEXT: [[STEP_ADD6_EPIL:%.*]] = fadd fast <4 x double> [[VEC_IND_EPIL]], +; AUTO_VEC-NEXT: [[TMP38:%.*]] = getelementptr double, double* [[A]], i64 [[INDEX_EPIL]] +; AUTO_VEC-NEXT: [[TMP39:%.*]] = bitcast double* [[TMP38]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[VEC_IND_EPIL]], <4 x double>* [[TMP39]], align 8 +; AUTO_VEC-NEXT: [[TMP40:%.*]] = getelementptr double, double* [[TMP38]], i64 4 +; AUTO_VEC-NEXT: [[TMP41:%.*]] = bitcast double* [[TMP40]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD_EPIL]], <4 x double>* [[TMP41]], align 8 +; AUTO_VEC-NEXT: [[TMP42:%.*]] = getelementptr double, double* [[TMP38]], i64 8 +; AUTO_VEC-NEXT: [[TMP43:%.*]] = bitcast double* [[TMP42]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD5_EPIL]], <4 x double>* [[TMP43]], align 8 +; AUTO_VEC-NEXT: [[TMP44:%.*]] = getelementptr double, double* [[TMP38]], i64 12 +; AUTO_VEC-NEXT: [[TMP45:%.*]] = bitcast double* [[TMP44]] to <4 x double>* +; AUTO_VEC-NEXT: store <4 x double> [[STEP_ADD6_EPIL]], <4 x double>* [[TMP45]], align 8 +; AUTO_VEC-NEXT: [[INDEX_NEXT_EPIL]] = add i64 [[INDEX_EPIL]], 16 +; AUTO_VEC-NEXT: [[VEC_IND_NEXT_EPIL]] = fadd fast <4 x double> [[VEC_IND_EPIL]], +; AUTO_VEC-NEXT: [[EPIL_ITER_SUB]] = add i64 [[EPIL_ITER]], -1 +; AUTO_VEC-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp eq i64 [[EPIL_ITER_SUB]], 0 +; AUTO_VEC-NEXT: br i1 [[EPIL_ITER_CMP]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY_EPIL]], !llvm.loop !8 ; AUTO_VEC: middle.block: ; AUTO_VEC-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]] -; AUTO_VEC-NEXT: [[TMP11:%.*]] = add nsw i64 [[N_VEC]], -1 -; AUTO_VEC-NEXT: [[CAST_CMO:%.*]] = sitofp i64 [[TMP11]] to double -; AUTO_VEC-NEXT: [[TMP12:%.*]] = fmul fast double [[CAST_CMO]], 3.000000e+00 +; AUTO_VEC-NEXT: [[TMP46:%.*]] = add nsw i64 [[N_VEC]], -1 +; AUTO_VEC-NEXT: [[CAST_CMO:%.*]] = sitofp i64 [[TMP46]] to double +; AUTO_VEC-NEXT: [[TMP47:%.*]] = fmul fast double [[CAST_CMO]], 3.000000e+00 ; AUTO_VEC-NEXT: br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[FOR_BODY]] ; AUTO_VEC: for.body: ; AUTO_VEC-NEXT: [[I:%.*]] = phi i64 [ [[I_NEXT:%.*]], [[FOR_BODY]] ], [ 0, [[ENTRY:%.*]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ] @@ -244,9 +426,9 @@ define double @external_use_with_fast_math(double* %a, i64 %n) { ; AUTO_VEC-NEXT: [[I_NEXT]] = add nuw nsw i64 [[I]], 1 ; AUTO_VEC-NEXT: [[J_NEXT]] = fadd fast double [[J]], 3.000000e+00 ; AUTO_VEC-NEXT: [[COND:%.*]] = icmp slt i64 [[I_NEXT]], [[N]] -; AUTO_VEC-NEXT: br i1 [[COND]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop !7 +; AUTO_VEC-NEXT: br i1 [[COND]], label [[FOR_BODY]], label [[FOR_END]], !llvm.loop !9 ; AUTO_VEC: for.end: -; AUTO_VEC-NEXT: [[J_LCSSA:%.*]] = phi double [ [[TMP12]], [[MIDDLE_BLOCK]] ], [ [[J]], [[FOR_BODY]] ] +; AUTO_VEC-NEXT: [[J_LCSSA:%.*]] = phi double [ [[TMP47]], [[MIDDLE_BLOCK]] ], [ [[J]], [[FOR_BODY]] ] ; AUTO_VEC-NEXT: ret double [[J_LCSSA]] ; entry: -- GitLab From 15488ff24b4ae205f979be7248b38655acd82f9c Mon Sep 17 00:00:00 2001 From: Clement Courbet Date: Mon, 10 Feb 2020 11:27:53 +0100 Subject: [PATCH 140/142] [CodeGen] Fix the computation of the alignment of split stores. Summary: Right now the alignment of the lower half of a store is computed as align/2, which fails for unaligned stores (align = 1), and is overly pessimitic for, e.g. a 8 byte store aligned to 4 bytes. Fixes PR44851 Fixes PR44877 Reviewers: gchatelet, spatel, lebedev.ri Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74311 --- llvm/lib/CodeGen/CodeGenPrepare.cpp | 13 ++++-- .../PowerPC/split-store-alignment.ll | 44 +++++++++++++++++-- .../X86/split-store-alignment.ll | 25 ++++++++++- 3 files changed, 74 insertions(+), 8 deletions(-) diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index efcf7ba39009..ce758d698c96 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -6864,12 +6864,19 @@ static bool splitMergedValStore(StoreInst &SI, const DataLayout &DL, Value *Addr = Builder.CreateBitCast( SI.getOperand(1), SplitStoreType->getPointerTo(SI.getPointerAddressSpace())); - if ((IsLE && Upper) || (!IsLE && !Upper)) + const bool IsOffsetStore = (IsLE && Upper) || (!IsLE && !Upper); + if (IsOffsetStore) Addr = Builder.CreateGEP( SplitStoreType, Addr, ConstantInt::get(Type::getInt32Ty(SI.getContext()), 1)); - Builder.CreateAlignedStore(V, Addr, - Upper ? SI.getAlign() / 2 : SI.getAlign()); + MaybeAlign Alignment = SI.getAlign(); + if (IsOffsetStore && Alignment) { + // When splitting the store in half, naturally one half will retain the + // alignment of the original wider store, regardless of whether it was + // over-aligned or not, while the other will require adjustment. + Alignment = commonAlignment(Alignment, HalfValBitSize / 8); + } + Builder.CreateAlignedStore(V, Addr, Alignment); }; CreateSplitStore(LValue, false); diff --git a/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll b/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll index 53cf743ef02d..5bc7d3a3b3b4 100644 --- a/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll +++ b/llvm/test/Transforms/CodeGenPrepare/PowerPC/split-store-alignment.ll @@ -2,6 +2,42 @@ ; RUN: opt -S -codegenprepare -mtriple=powerpc64-unknown-linux-gnu -data-layout="E-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefixes=ALL,BE %s ; RUN: opt -S -codegenprepare -mtriple=powerpc64le-unknown-linux-gnu -data-layout="e-m:e-i64:64-n32:64" -force-split-store < %s | FileCheck --check-prefixes=ALL,LE %s +define void @split_store_align1(float %x, i64* %p) { +; BE-LABEL: @split_store_align1( +; BE-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; BE-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; BE-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; BE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; BE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; BE-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; BE-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], i32 1 +; BE-NEXT: store i32 [[B]], i32* [[TMP2]], align 1 +; BE-NEXT: [[TMP3:%.*]] = bitcast i64* [[P]] to i32* +; BE-NEXT: store i32 0, i32* [[TMP3]], align 1 +; BE-NEXT: ret void +; +; LE-LABEL: @split_store_align1( +; LE-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; LE-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; LE-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; LE-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; LE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; LE-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; LE-NEXT: store i32 [[B]], i32* [[TMP1]], align 1 +; LE-NEXT: [[TMP2:%.*]] = bitcast i64* [[P]] to i32* +; LE-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1 +; LE-NEXT: store i32 0, i32* [[TMP3]], align 1 +; LE-NEXT: ret void +; + %b = bitcast float %x to i32 + %z = zext i32 0 to i64 + %s = shl nuw nsw i64 %z, 32 + %z2 = zext i32 %b to i64 + %o = or i64 %s, %z2 + store i64 %o, i64* %p, align 1 + ret void +} + define void @split_store_align2(float %x, i64* %p) { ; BE-LABEL: @split_store_align2( ; BE-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 @@ -13,7 +49,7 @@ define void @split_store_align2(float %x, i64* %p) { ; BE-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], i32 1 ; BE-NEXT: store i32 [[B]], i32* [[TMP2]], align 2 ; BE-NEXT: [[TMP3:%.*]] = bitcast i64* [[P]] to i32* -; BE-NEXT: store i32 0, i32* [[TMP3]], align 1 +; BE-NEXT: store i32 0, i32* [[TMP3]], align 2 ; BE-NEXT: ret void ; ; LE-LABEL: @split_store_align2( @@ -26,7 +62,7 @@ define void @split_store_align2(float %x, i64* %p) { ; LE-NEXT: store i32 [[B]], i32* [[TMP1]], align 2 ; LE-NEXT: [[TMP2:%.*]] = bitcast i64* [[P]] to i32* ; LE-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1 -; LE-NEXT: store i32 0, i32* [[TMP3]], align 1 +; LE-NEXT: store i32 0, i32* [[TMP3]], align 2 ; LE-NEXT: ret void ; %b = bitcast float %x to i32 @@ -47,9 +83,9 @@ define void @split_store_align8(float %x, i64* %p) { ; BE-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] ; BE-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* ; BE-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], i32 1 -; BE-NEXT: store i32 [[B]], i32* [[TMP2]], align 8 +; BE-NEXT: store i32 [[B]], i32* [[TMP2]], align 4 ; BE-NEXT: [[TMP3:%.*]] = bitcast i64* [[P]] to i32* -; BE-NEXT: store i32 0, i32* [[TMP3]], align 4 +; BE-NEXT: store i32 0, i32* [[TMP3]], align 8 ; BE-NEXT: ret void ; ; LE-LABEL: @split_store_align8( diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll b/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll index 7e0f5125f087..7eb8cb8ebfe1 100644 --- a/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll +++ b/llvm/test/Transforms/CodeGenPrepare/X86/split-store-alignment.ll @@ -4,6 +4,29 @@ target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i686-w64-windows-gnu" +define void @split_store_align1(float %x, i64* %p) { +; CHECK-LABEL: @split_store_align1( +; CHECK-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 +; CHECK-NEXT: [[Z:%.*]] = zext i32 0 to i64 +; CHECK-NEXT: [[S:%.*]] = shl nuw nsw i64 [[Z]], 32 +; CHECK-NEXT: [[Z2:%.*]] = zext i32 [[B]] to i64 +; CHECK-NEXT: [[O:%.*]] = or i64 [[S]], [[Z2]] +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[P:%.*]] to i32* +; CHECK-NEXT: store i32 [[B]], i32* [[TMP1]], align 1 +; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[P]] to i32* +; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1 +; CHECK-NEXT: store i32 0, i32* [[TMP3]], align 1 +; CHECK-NEXT: ret void +; + %b = bitcast float %x to i32 + %z = zext i32 0 to i64 + %s = shl nuw nsw i64 %z, 32 + %z2 = zext i32 %b to i64 + %o = or i64 %s, %z2 + store i64 %o, i64* %p, align 1 + ret void +} + define void @split_store_align2(float %x, i64* %p) { ; CHECK-LABEL: @split_store_align2( ; CHECK-NEXT: [[B:%.*]] = bitcast float [[X:%.*]] to i32 @@ -15,7 +38,7 @@ define void @split_store_align2(float %x, i64* %p) { ; CHECK-NEXT: store i32 [[B]], i32* [[TMP1]], align 2 ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[P]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, i32* [[TMP2]], i32 1 -; CHECK-NEXT: store i32 0, i32* [[TMP3]], align 1 +; CHECK-NEXT: store i32 0, i32* [[TMP3]], align 2 ; CHECK-NEXT: ret void ; %b = bitcast float %x to i32 -- GitLab From fa74b31a3e9cd844c7ce2087978568e3f5ec8519 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 12 Feb 2020 09:41:19 +0000 Subject: [PATCH 141/142] Revert "[SCCP] Remove forcedconstant, go to overdefined instead" This causes a crash for the reproducer below enum { a }; enum b { c, d }; e; static _Bool g(struct f *h, enum b i) { i &&j(); return a; } static k(char h, enum b i) { _Bool l = g(e, i); l; } m(h) { k(h, c); g(h, d); } This reverts commit aadb635e04854220064b77cc10d0e6772f5492fd. --- llvm/lib/Transforms/Scalar/SCCP.cpp | 248 ++++++++++++++++-- .../test/Transforms/IPConstantProp/PR16052.ll | 9 +- .../test/Transforms/IPConstantProp/PR26044.ll | 6 +- .../Transforms/SCCP/2006-12-19-UndefBug.ll | 12 +- llvm/test/Transforms/SCCP/apint-bigint2.ll | 24 +- llvm/test/Transforms/SCCP/apint-ipsccp3.ll | 40 +-- llvm/test/Transforms/SCCP/apint-select.ll | 30 +-- .../Transforms/SCCP/ip-constant-ranges.ll | 10 +- llvm/test/Transforms/SCCP/ipsccp-basic.ll | 34 +-- llvm/test/Transforms/SCCP/logical-nuke.ll | 28 +- .../Transforms/SCCP/switch-multiple-undef.ll | 26 +- llvm/test/Transforms/SCCP/ub-shift.ll | 53 ++-- llvm/test/Transforms/SCCP/undef-resolve.ll | 156 +++-------- 13 files changed, 346 insertions(+), 330 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/SCCP.cpp b/llvm/lib/Transforms/Scalar/SCCP.cpp index 3e6697e91b9e..34f18ec7c121 100644 --- a/llvm/lib/Transforms/Scalar/SCCP.cpp +++ b/llvm/lib/Transforms/Scalar/SCCP.cpp @@ -85,13 +85,19 @@ class LatticeVal { /// constant - This LLVM Value has a specific constant value. constant, + /// forcedconstant - This LLVM Value was thought to be undef until + /// ResolvedUndefsIn. This is treated just like 'constant', but if merged + /// with another (different) constant, it goes to overdefined, instead of + /// asserting. + forcedconstant, + /// overdefined - This instruction is not known to be constant, and we know /// it has a value. overdefined }; /// Val: This stores the current lattice value along with the Constant* for - /// the constant if this is a 'constant' value. + /// the constant if this is a 'constant' or 'forcedconstant' value. PointerIntPair Val; LatticeValueTy getLatticeValue() const { @@ -103,7 +109,9 @@ public: bool isUnknown() const { return getLatticeValue() == unknown; } - bool isConstant() const { return getLatticeValue() == constant; } + bool isConstant() const { + return getLatticeValue() == constant || getLatticeValue() == forcedconstant; + } bool isOverdefined() const { return getLatticeValue() == overdefined; } @@ -123,15 +131,26 @@ public: /// markConstant - Return true if this is a change in status. bool markConstant(Constant *V) { - if (getLatticeValue() == constant) { // Constant + if (getLatticeValue() == constant) { // Constant but not forcedconstant. assert(getConstant() == V && "Marking constant with different value"); return false; } - assert(isUnknown()); - Val.setInt(constant); - assert(V && "Marking constant with NULL"); - Val.setPointer(V); + if (isUnknown()) { + Val.setInt(constant); + assert(V && "Marking constant with NULL"); + Val.setPointer(V); + } else { + assert(getLatticeValue() == forcedconstant && + "Cannot move from overdefined to constant!"); + // Stay at forcedconstant if the constant is the same. + if (V == getConstant()) return false; + + // Otherwise, we go to overdefined. Assumptions made based on the + // forced value are possibly wrong. Assuming this is another constant + // could expose a contradiction. + Val.setInt(overdefined); + } return true; } @@ -151,6 +170,12 @@ public: return nullptr; } + void markForcedConstant(Constant *V) { + assert(isUnknown() && "Can't force a defined value!"); + Val.setInt(forcedconstant); + Val.setPointer(V); + } + ValueLatticeElement toValueLattice() const { if (isOverdefined()) return ValueLatticeElement::getOverdefined(); @@ -396,7 +421,7 @@ public: } private: - // pushToWorkList - Helper for markConstant/markOverdefined + // pushToWorkList - Helper for markConstant/markForcedConstant/markOverdefined void pushToWorkList(LatticeVal &IV, Value *V) { if (IV.isOverdefined()) return OverdefinedInstWorkList.push_back(V); @@ -418,6 +443,14 @@ private: return markConstant(ValueState[V], V, C); } + void markForcedConstant(Value *V, Constant *C) { + assert(!V->getType()->isStructTy() && "structs should use mergeInValue"); + LatticeVal &IV = ValueState[V]; + IV.markForcedConstant(C); + LLVM_DEBUG(dbgs() << "markForcedConstant: " << *C << ": " << *V << '\n'); + pushToWorkList(IV, V); + } + // markOverdefined - Make a value be marked as "overdefined". If the // value is not already overdefined, add it to the overdefined instruction // work list so that the users of the instruction are updated later. @@ -999,10 +1032,8 @@ void SCCPSolver::visitBinaryOperator(Instruction &I) { } // If something is undef, wait for it to resolve. - if (!V1State.isOverdefined() && !V2State.isOverdefined()) { - + if (!V1State.isOverdefined() && !V2State.isOverdefined()) return; - } // Otherwise, one of our operands is overdefined. Try to produce something // better than overdefined with some tricks. @@ -1418,8 +1449,10 @@ void SCCPSolver::Solve() { /// constraints on the condition of the branch, as that would impact other users /// of the value. /// -/// This scan also checks for values that use undefs. It conservatively marks -/// them as overdefined. +/// This scan also checks for values that use undefs, whose results are actually +/// defined. For example, 'zext i8 undef to i32' should produce all zeros +/// conservatively, as "(zext i8 X -> i32) & 0xFF00" must always return zero, +/// even if X isn't defined. bool SCCPSolver::ResolvedUndefsIn(Function &F) { for (BasicBlock &BB : F) { if (!BBExecutable.count(&BB)) @@ -1442,6 +1475,7 @@ bool SCCPSolver::ResolvedUndefsIn(Function &F) { // tracked as precisely as their operands. if (isa(I) || isa(I)) continue; + // Send the results of everything else to overdefined. We could be // more precise than this but it isn't worth bothering. for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { @@ -1461,13 +1495,195 @@ bool SCCPSolver::ResolvedUndefsIn(Function &F) { // 2. It could be constant-foldable. // Because of the way we solve return values, tracked calls must // never be marked overdefined in ResolvedUndefsIn. - if (CallSite CS = CallSite(&I)) + if (CallSite CS = CallSite(&I)) { if (Function *F = CS.getCalledFunction()) if (TrackedRetVals.count(F)) continue; - markOverdefined(&I); - return true; + // If the call is constant-foldable, we mark it overdefined because + // we do not know what return values are valid. + markOverdefined(&I); + return true; + } + + // extractvalue is safe; check here because the argument is a struct. + if (isa(I)) + continue; + + // Compute the operand LatticeVals, for convenience below. + // Anything taking a struct is conservatively assumed to require + // overdefined markings. + if (I.getOperand(0)->getType()->isStructTy()) { + markOverdefined(&I); + return true; + } + LatticeVal Op0LV = getValueState(I.getOperand(0)); + LatticeVal Op1LV; + if (I.getNumOperands() == 2) { + if (I.getOperand(1)->getType()->isStructTy()) { + markOverdefined(&I); + return true; + } + + Op1LV = getValueState(I.getOperand(1)); + } + // If this is an instructions whose result is defined even if the input is + // not fully defined, propagate the information. + Type *ITy = I.getType(); + switch (I.getOpcode()) { + case Instruction::Add: + case Instruction::Sub: + case Instruction::Trunc: + case Instruction::FPTrunc: + case Instruction::BitCast: + break; // Any undef -> undef + case Instruction::FSub: + case Instruction::FAdd: + case Instruction::FMul: + case Instruction::FDiv: + case Instruction::FRem: + // Floating-point binary operation: be conservative. + if (Op0LV.isUnknown() && Op1LV.isUnknown()) + markForcedConstant(&I, Constant::getNullValue(ITy)); + else + markOverdefined(&I); + return true; + case Instruction::FNeg: + break; // fneg undef -> undef + case Instruction::ZExt: + case Instruction::SExt: + case Instruction::FPToUI: + case Instruction::FPToSI: + case Instruction::FPExt: + case Instruction::PtrToInt: + case Instruction::IntToPtr: + case Instruction::SIToFP: + case Instruction::UIToFP: + // undef -> 0; some outputs are impossible + markForcedConstant(&I, Constant::getNullValue(ITy)); + return true; + case Instruction::Mul: + case Instruction::And: + // Both operands undef -> undef + if (Op0LV.isUnknown() && Op1LV.isUnknown()) + break; + // undef * X -> 0. X could be zero. + // undef & X -> 0. X could be zero. + markForcedConstant(&I, Constant::getNullValue(ITy)); + return true; + case Instruction::Or: + // Both operands undef -> undef + if (Op0LV.isUnknown() && Op1LV.isUnknown()) + break; + // undef | X -> -1. X could be -1. + markForcedConstant(&I, Constant::getAllOnesValue(ITy)); + return true; + case Instruction::Xor: + // undef ^ undef -> 0; strictly speaking, this is not strictly + // necessary, but we try to be nice to people who expect this + // behavior in simple cases + if (Op0LV.isUnknown() && Op1LV.isUnknown()) { + markForcedConstant(&I, Constant::getNullValue(ITy)); + return true; + } + // undef ^ X -> undef + break; + case Instruction::SDiv: + case Instruction::UDiv: + case Instruction::SRem: + case Instruction::URem: + // X / undef -> undef. No change. + // X % undef -> undef. No change. + if (Op1LV.isUnknown()) break; + + // X / 0 -> undef. No change. + // X % 0 -> undef. No change. + if (Op1LV.isConstant() && Op1LV.getConstant()->isZeroValue()) + break; + + // undef / X -> 0. X could be maxint. + // undef % X -> 0. X could be 1. + markForcedConstant(&I, Constant::getNullValue(ITy)); + return true; + case Instruction::AShr: + // X >>a undef -> undef. + if (Op1LV.isUnknown()) break; + + // Shifting by the bitwidth or more is undefined. + if (Op1LV.isConstant()) { + if (auto *ShiftAmt = Op1LV.getConstantInt()) + if (ShiftAmt->getLimitedValue() >= + ShiftAmt->getType()->getScalarSizeInBits()) + break; + } + + // undef >>a X -> 0 + markForcedConstant(&I, Constant::getNullValue(ITy)); + return true; + case Instruction::LShr: + case Instruction::Shl: + // X << undef -> undef. + // X >> undef -> undef. + if (Op1LV.isUnknown()) break; + + // Shifting by the bitwidth or more is undefined. + if (Op1LV.isConstant()) { + if (auto *ShiftAmt = Op1LV.getConstantInt()) + if (ShiftAmt->getLimitedValue() >= + ShiftAmt->getType()->getScalarSizeInBits()) + break; + } + + // undef << X -> 0 + // undef >> X -> 0 + markForcedConstant(&I, Constant::getNullValue(ITy)); + return true; + case Instruction::Select: + Op1LV = getValueState(I.getOperand(1)); + // undef ? X : Y -> X or Y. There could be commonality between X/Y. + if (Op0LV.isUnknown()) { + if (!Op1LV.isConstant()) // Pick the constant one if there is any. + Op1LV = getValueState(I.getOperand(2)); + } else if (Op1LV.isUnknown()) { + // c ? undef : undef -> undef. No change. + Op1LV = getValueState(I.getOperand(2)); + if (Op1LV.isUnknown()) + break; + // Otherwise, c ? undef : x -> x. + } else { + // Leave Op1LV as Operand(1)'s LatticeValue. + } + + if (Op1LV.isConstant()) + markForcedConstant(&I, Op1LV.getConstant()); + else + markOverdefined(&I); + return true; + case Instruction::Load: + // A load here means one of two things: a load of undef from a global, + // a load from an unknown pointer. Either way, having it return undef + // is okay. + break; + case Instruction::ICmp: + // X == undef -> undef. Other comparisons get more complicated. + Op0LV = getValueState(I.getOperand(0)); + Op1LV = getValueState(I.getOperand(1)); + + if ((Op0LV.isUnknown() || Op1LV.isUnknown()) && + cast(&I)->isEquality()) + break; + markOverdefined(&I); + return true; + case Instruction::Call: + case Instruction::Invoke: + case Instruction::CallBr: + llvm_unreachable("Call-like instructions should have be handled early"); + default: + // If we don't know what should happen here, conservatively mark it + // overdefined. + markOverdefined(&I); + return true; + } } // Check to see if we have a branch or switch on an undefined value. If so diff --git a/llvm/test/Transforms/IPConstantProp/PR16052.ll b/llvm/test/Transforms/IPConstantProp/PR16052.ll index a16067fe278a..451693f1c90c 100644 --- a/llvm/test/Transforms/IPConstantProp/PR16052.ll +++ b/llvm/test/Transforms/IPConstantProp/PR16052.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes ; RUN: opt < %s -S -ipsccp | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" @@ -7,9 +7,7 @@ target triple = "x86_64-unknown-linux-gnu" define i64 @fn2() { ; CHECK-LABEL: define {{[^@]+}}@fn2() ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CONV:%.*]] = sext i32 undef to i64 -; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 8, [[CONV]] -; CHECK-NEXT: [[CALL2:%.*]] = call i64 @fn1(i64 [[DIV]]) +; CHECK-NEXT: [[CALL2:%.*]] = call i64 @fn1(i64 undef) ; CHECK-NEXT: ret i64 [[CALL2]] ; entry: @@ -23,8 +21,7 @@ define internal i64 @fn1(i64 %p1) { ; CHECK-LABEL: define {{[^@]+}}@fn1 ; CHECK-SAME: (i64 [[P1:%.*]]) ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i64 [[P1]], 0 -; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 [[P1]], i64 [[P1]] +; CHECK-NEXT: [[COND:%.*]] = select i1 undef, i64 undef, i64 undef ; CHECK-NEXT: ret i64 [[COND]] ; entry: diff --git a/llvm/test/Transforms/IPConstantProp/PR26044.ll b/llvm/test/Transforms/IPConstantProp/PR26044.ll index 8b4f2590b9f8..eeb5b87e0a28 100644 --- a/llvm/test/Transforms/IPConstantProp/PR26044.ll +++ b/llvm/test/Transforms/IPConstantProp/PR26044.ll @@ -11,8 +11,7 @@ define void @fn2(i32* %P) { ; CHECK: for.cond1: ; CHECK-NEXT: br i1 false, label [[IF_END]], label [[IF_END]] ; CHECK: if.end: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* null, align 4 -; CHECK-NEXT: [[CALL:%.*]] = call i32 @fn1(i32 [[TMP0]]) +; CHECK-NEXT: [[CALL:%.*]] = call i32 @fn1(i32 undef) ; CHECK-NEXT: store i32 [[CALL]], i32* [[P]] ; CHECK-NEXT: br label [[FOR_COND1:%.*]] ; @@ -34,8 +33,7 @@ define internal i32 @fn1(i32 %p1) { ; CHECK-LABEL: define {{[^@]+}}@fn1 ; CHECK-SAME: (i32 [[P1:%.*]]) ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[P1]], 0 -; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 [[P1]], i32 [[P1]] +; CHECK-NEXT: [[COND:%.*]] = select i1 undef, i32 undef, i32 undef ; CHECK-NEXT: ret i32 [[COND]] ; entry: diff --git a/llvm/test/Transforms/SCCP/2006-12-19-UndefBug.ll b/llvm/test/Transforms/SCCP/2006-12-19-UndefBug.ll index 4bd096e0a656..ede1a32c5f7a 100644 --- a/llvm/test/Transforms/SCCP/2006-12-19-UndefBug.ll +++ b/llvm/test/Transforms/SCCP/2006-12-19-UndefBug.ll @@ -1,12 +1,8 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -sccp -S | FileCheck %s +; RUN: opt < %s -sccp -S | \ +; RUN: grep "ret i1 false" define i1 @foo() { -; CHECK-LABEL: @foo( -; CHECK-NEXT: [[X:%.*]] = and i1 false, undef -; CHECK-NEXT: ret i1 [[X]] -; - %X = and i1 false, undef ; [#uses=1] - ret i1 %X + %X = and i1 false, undef ; [#uses=1] + ret i1 %X } diff --git a/llvm/test/Transforms/SCCP/apint-bigint2.ll b/llvm/test/Transforms/SCCP/apint-bigint2.ll index 7d75240a0d8e..5277d9fa5c6e 100644 --- a/llvm/test/Transforms/SCCP/apint-bigint2.ll +++ b/llvm/test/Transforms/SCCP/apint-bigint2.ll @@ -18,13 +18,7 @@ define i101 @array() { } ; CHECK-LABEL: @large_aggregate -; CHECK-NEXT: %B = load i101, i101* undef -; CHECK-NEXT: %D = and i101 %B, 1 -; CHECK-NEXT: %DD = or i101 %D, 1 -; CHECK-NEXT: %G = getelementptr i101, i101* getelementptr inbounds ([6 x i101], [6 x i101]* @Y, i32 0, i32 5), i101 %DD -; CHECK-NEXT: %L3 = load i101, i101* %G -; CHECK-NEXT: ret i101 %L3 -; +; CHECK-NEXT: ret i101 undef define i101 @large_aggregate() { %B = load i101, i101* undef %D = and i101 %B, 1 @@ -35,22 +29,6 @@ define i101 @large_aggregate() { ret i101 %L3 } -; CHECK-LABEL: define i101 @large_aggregate_2() { -; CHECK-NEXT: %D = and i101 undef, 1 -; CHECK-NEXT: %DD = or i101 %D, 1 -; CHECK-NEXT: %G = getelementptr i101, i101* getelementptr inbounds ([6 x i101], [6 x i101]* @Y, i32 0, i32 5), i101 %DD -; CHECK-NEXT: %L3 = load i101, i101* %G -; CHECK-NEXT: ret i101 %L3 -; -define i101 @large_aggregate_2() { - %D = and i101 undef, 1 - %DD = or i101 %D, 1 - %F = getelementptr [6 x i101], [6 x i101]* @Y, i32 0, i32 5 - %G = getelementptr i101, i101* %F, i101 %DD - %L3 = load i101, i101* %G - ret i101 %L3 -} - ; CHECK-LABEL: @index_too_large ; CHECK-NEXT: store i101* getelementptr (i101, i101* getelementptr ([6 x i101], [6 x i101]* @Y, i32 0, i32 -1), i101 9224497936761618431), i101** undef ; CHECK-NEXT: ret void diff --git a/llvm/test/Transforms/SCCP/apint-ipsccp3.ll b/llvm/test/Transforms/SCCP/apint-ipsccp3.ll index 4ba1f8db30ba..c99ae5820b2d 100644 --- a/llvm/test/Transforms/SCCP/apint-ipsccp3.ll +++ b/llvm/test/Transforms/SCCP/apint-ipsccp3.ll @@ -1,39 +1,23 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -ipsccp -S | FileCheck %s +; RUN: opt < %s -ipsccp -S | not grep global @G = internal global i66 undef + define void @foo() { -; CHECK-LABEL: @foo( -; CHECK-NEXT: [[X:%.*]] = load i66, i66* @G -; CHECK-NEXT: store i66 [[X]], i66* @G -; CHECK-NEXT: ret void -; - %X = load i66, i66* @G - store i66 %X, i66* @G - ret void + %X = load i66, i66* @G + store i66 %X, i66* @G + ret void } define i66 @bar() { -; CHECK-LABEL: @bar( -; CHECK-NEXT: [[V:%.*]] = load i66, i66* @G -; CHECK-NEXT: [[C:%.*]] = icmp eq i66 [[V]], 17 -; CHECK-NEXT: br i1 [[C]], label [[T:%.*]], label [[F:%.*]] -; CHECK: T: -; CHECK-NEXT: store i66 17, i66* @G -; CHECK-NEXT: ret i66 17 -; CHECK: F: -; CHECK-NEXT: store i66 123, i66* @G -; CHECK-NEXT: ret i66 0 -; - %V = load i66, i66* @G - %C = icmp eq i66 %V, 17 - br i1 %C, label %T, label %F + %V = load i66, i66* @G + %C = icmp eq i66 %V, 17 + br i1 %C, label %T, label %F T: - store i66 17, i66* @G - ret i66 %V + store i66 17, i66* @G + ret i66 %V F: - store i66 123, i66* @G - ret i66 0 + store i66 123, i66* @G + ret i66 0 } diff --git a/llvm/test/Transforms/SCCP/apint-select.ll b/llvm/test/Transforms/SCCP/apint-select.ll index d797c7a4d43c..893331ea9867 100644 --- a/llvm/test/Transforms/SCCP/apint-select.ll +++ b/llvm/test/Transforms/SCCP/apint-select.ll @@ -1,29 +1,21 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -sccp -S | FileCheck %s +; RUN: opt < %s -sccp -S | not grep select @A = constant i32 10 define i712 @test1() { -; CHECK-LABEL: @test1( -; CHECK-NEXT: [[BB:%.*]] = and i64 ptrtoint (i32* @A to i64), undef -; CHECK-NEXT: [[C:%.*]] = icmp sge i64 [[BB]], 0 -; CHECK-NEXT: [[X:%.*]] = select i1 [[C]], i712 0, i712 1 -; CHECK-NEXT: ret i712 [[X]] -; - %P = getelementptr i32, i32* @A, i32 0 - %B = ptrtoint i32* %P to i64 - %BB = and i64 %B, undef - %C = icmp sge i64 %BB, 0 - %X = select i1 %C, i712 0, i712 1 - ret i712 %X + %P = getelementptr i32, i32* @A, i32 0 + %B = ptrtoint i32* %P to i64 + %BB = and i64 %B, undef + %C = icmp sge i64 %BB, 0 + %X = select i1 %C, i712 0, i712 1 + ret i712 %X } define i712 @test2(i1 %C) { -; CHECK-LABEL: @test2( -; CHECK-NEXT: ret i712 0 -; - %X = select i1 %C, i712 0, i712 undef - ret i712 %X + %X = select i1 %C, i712 0, i712 undef + ret i712 %X } + + diff --git a/llvm/test/Transforms/SCCP/ip-constant-ranges.ll b/llvm/test/Transforms/SCCP/ip-constant-ranges.ll index 08de8dba4046..426e3279661f 100644 --- a/llvm/test/Transforms/SCCP/ip-constant-ranges.ll +++ b/llvm/test/Transforms/SCCP/ip-constant-ranges.ll @@ -141,12 +141,10 @@ define double @test_struct({ double, double } %test) { ; Constant range for %x is [47, 302) ; CHECK-LABEL: @f5 ; CHECK-NEXT: entry: -; CHECK-NEXT: %cmp = icmp sgt i32 %x, undef -; CHECK-NEXT: %cmp2 = icmp ne i32 undef, %x -; CHECK-NEXT: %res1 = select i1 %cmp, i32 1, i32 2 -; CHECK-NEXT: %res2 = select i1 %cmp2, i32 3, i32 4 -; CHECK-NEXT: %res = add i32 %res1, %res2 -; CHECK-NEXT: ret i32 %res +; CHECK-NEXT: %cmp = icmp sgt i32 %x, undef +; CHECK-NEXT: %res1 = select i1 %cmp, i32 1, i32 2 +; CHECK-NEXT: %res = add i32 %res1, 3 +; CHECK-NEXT: ret i32 %res define internal i32 @f5(i32 %x) { entry: %cmp = icmp sgt i32 %x, undef diff --git a/llvm/test/Transforms/SCCP/ipsccp-basic.ll b/llvm/test/Transforms/SCCP/ipsccp-basic.ll index 795a73f1d907..b1660b545652 100644 --- a/llvm/test/Transforms/SCCP/ipsccp-basic.ll +++ b/llvm/test/Transforms/SCCP/ipsccp-basic.ll @@ -56,9 +56,7 @@ define void @test3a() { ret void } ; CHECK-LABEL: define void @test3a( -; CHECK-NEXT: %X = load i32, i32* @G -; CHECK-NEXT: store i32 %X, i32* @G -; CHECK-NEXT: ret void +; CHECK-NEXT: ret void define i32 @test3b() { @@ -73,17 +71,9 @@ F: ret i32 0 } ; CHECK-LABEL: define i32 @test3b( -; CHECK-NEXT: %V = load i32, i32* @G -; CHECK-NEXT: %C = icmp eq i32 %V, 17 -; CHECK-NEXT: br i1 %C, label %T, label %F - -; CHECK-LABEL: T: -; CHECK-NEXT: store i32 17, i32* @G -; CHECK-NEXT: ret i32 17 +; CHECK-NOT: store +; CHECK: ret i32 0 -; CHECK-LABEL: F: -; CHECK-NEXT: store i32 123, i32* @G -; CHECK-NEXT: ret i32 0 ;;======================== test4 @@ -236,11 +226,8 @@ define i32 @test10a() nounwind { entry: %call = call i32 @test10b(i32 undef) ret i32 %call - ; CHECK-LABEL: define i32 @test10a( -; CHECK-NEXT: entry: -; CHECK-NEXT: %call = call i32 @test10b(i32 undef) -; CHECK-NEXT: ret i32 %call +; CHECK: ret i32 0 } define internal i32 @test10b(i32 %x) nounwind { @@ -248,9 +235,7 @@ entry: %r = and i32 %x, 1 ret i32 %r ; CHECK-LABEL: define internal i32 @test10b( -; CHECK-NEXT: entry: -; CHECK-NEXT: %r = and i32 undef, 1 -; CHECK-NEXT: ret i32 %r +; CHECK: ret i32 undef } ;;======================== test11 @@ -259,8 +244,7 @@ define i64 @test11a() { %xor = xor i64 undef, undef ret i64 %xor ; CHECK-LABEL: define i64 @test11a -; CHECK-NEXT: %xor = xor i64 undef, undef -; CHECK-NEXT: ret i64 %xor +; CHECK: ret i64 0 } define i64 @test11b() { @@ -268,9 +252,9 @@ define i64 @test11b() { %call2 = call i64 @llvm.ctpop.i64(i64 %call1) ret i64 %call2 ; CHECK-LABEL: define i64 @test11b -; CHECK-NEXT: [[call1:%.*]] = call i64 @test11a() -; CHECK-NEXT: [[call2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[call1]]) -; CHECK-NEXT: ret i64 [[call2]] +; CHECK: %[[call1:.*]] = call i64 @test11a() +; CHECK-NOT: call i64 @llvm.ctpop.i64 +; CHECK-NEXT: ret i64 0 } declare i64 @llvm.ctpop.i64(i64) diff --git a/llvm/test/Transforms/SCCP/logical-nuke.ll b/llvm/test/Transforms/SCCP/logical-nuke.ll index 5152e126e8fa..6ca16de4489b 100644 --- a/llvm/test/Transforms/SCCP/logical-nuke.ll +++ b/llvm/test/Transforms/SCCP/logical-nuke.ll @@ -1,47 +1,39 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -sccp -S | FileCheck %s ; Test that SCCP has basic knowledge of when and/or/mul nuke overdefined values. +; CHECK-LABEL: test +; CHECK: ret i32 0 define i32 @test(i32 %X) { -; CHECK-LABEL: @test( -; CHECK-NEXT: ret i32 0 -; %Y = and i32 %X, 0 ret i32 %Y } +; CHECK-LABEL: test2 +; CHECK: ret i32 -1 define i32 @test2(i32 %X) { -; CHECK-LABEL: @test2( -; CHECK-NEXT: ret i32 -1 -; %Y = or i32 -1, %X ret i32 %Y } +; CHECK-LABEL: test3 +; CHECK: ret i32 0 define i32 @test3(i32 %X) { -; CHECK-LABEL: @test3( -; CHECK-NEXT: [[Y:%.*]] = and i32 undef, [[X:%.*]] -; CHECK-NEXT: ret i32 [[Y]] -; %Y = and i32 undef, %X ret i32 %Y } +; CHECK-LABEL: test4 +; CHECK: ret i32 -1 define i32 @test4(i32 %X) { -; CHECK-LABEL: @test4( -; CHECK-NEXT: [[Y:%.*]] = or i32 [[X:%.*]], undef -; CHECK-NEXT: ret i32 [[Y]] -; %Y = or i32 %X, undef ret i32 %Y } ; X * 0 = 0 even if X is overdefined. +; CHECK-LABEL: test5 +; CHECK: ret i32 0 define i32 @test5(i32 %foo) { -; CHECK-LABEL: @test5( -; CHECK-NEXT: ret i32 0 -; %patatino = mul i32 %foo, 0 ret i32 %patatino } diff --git a/llvm/test/Transforms/SCCP/switch-multiple-undef.ll b/llvm/test/Transforms/SCCP/switch-multiple-undef.ll index df99e4eee7d2..027c9c0c9ba7 100644 --- a/llvm/test/Transforms/SCCP/switch-multiple-undef.ll +++ b/llvm/test/Transforms/SCCP/switch-multiple-undef.ll @@ -1,4 +1,3 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -ipsccp < %s | FileCheck %s declare void @foo() @@ -6,25 +5,9 @@ declare void @goo() declare void @patatino() define void @test1(i32 %t) { -; CHECK-LABEL: @test1( -; CHECK-NEXT: [[CHOICE:%.*]] = icmp eq i32 undef, -1 -; CHECK-NEXT: switch i1 [[CHOICE]], label [[FIRST:%.*]] [ -; CHECK-NEXT: i1 false, label [[SECOND:%.*]] -; CHECK-NEXT: i1 true, label [[THIRD:%.*]] -; CHECK-NEXT: ] -; CHECK: first: -; CHECK-NEXT: call void @foo() -; CHECK-NEXT: ret void -; CHECK: second: -; CHECK-NEXT: call void @goo() -; CHECK-NEXT: ret void -; CHECK: third: -; CHECK-NEXT: call void @patatino() -; CHECK-NEXT: ret void -; %choice = icmp eq i32 undef, -1 switch i1 %choice, label %first [i1 0, label %second - i1 1, label %third] + i1 1, label %third] first: call void @foo() ret void @@ -35,3 +18,10 @@ third: call void @patatino() ret void } + +; CHECK: define void @test1(i32 %t) { +; CHECK-NEXT: br label %second +; CHECK: second: +; CHECK-NEXT: call void @goo() +; CHECK-NEXT: ret void +; CHECK-NEXT: } diff --git a/llvm/test/Transforms/SCCP/ub-shift.ll b/llvm/test/Transforms/SCCP/ub-shift.ll index 6e15d6b2bccd..3fb2d97457d9 100644 --- a/llvm/test/Transforms/SCCP/ub-shift.ll +++ b/llvm/test/Transforms/SCCP/ub-shift.ll @@ -1,89 +1,68 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -sccp -S | FileCheck %s +; CHECK-LABEL: shift_undef_64 define void @shift_undef_64(i64* %p) { -; CHECK-LABEL: @shift_undef_64( -; CHECK-NEXT: [[R1:%.*]] = lshr i64 -1, 4294967296 -; CHECK-NEXT: store i64 [[R1]], i64* [[P:%.*]] -; CHECK-NEXT: [[R2:%.*]] = ashr i64 -1, 4294967297 -; CHECK-NEXT: store i64 [[R2]], i64* [[P]] -; CHECK-NEXT: [[R3:%.*]] = shl i64 -1, 4294967298 -; CHECK-NEXT: store i64 [[R3]], i64* [[P]] -; CHECK-NEXT: ret void -; %r1 = lshr i64 -1, 4294967296 ; 2^32 + ; CHECK: store i64 undef store i64 %r1, i64* %p %r2 = ashr i64 -1, 4294967297 ; 2^32 + 1 + ; CHECK: store i64 undef store i64 %r2, i64* %p %r3 = shl i64 -1, 4294967298 ; 2^32 + 2 + ; CHECK: store i64 undef store i64 %r3, i64* %p ret void } +; CHECK-LABEL: shift_undef_65 define void @shift_undef_65(i65* %p) { -; CHECK-LABEL: @shift_undef_65( -; CHECK-NEXT: [[R1:%.*]] = lshr i65 2, -18446744073709551615 -; CHECK-NEXT: store i65 [[R1]], i65* [[P:%.*]] -; CHECK-NEXT: [[R2:%.*]] = ashr i65 4, -18446744073709551615 -; CHECK-NEXT: store i65 [[R2]], i65* [[P]] -; CHECK-NEXT: [[R3:%.*]] = shl i65 1, -18446744073709551615 -; CHECK-NEXT: store i65 [[R3]], i65* [[P]] -; CHECK-NEXT: ret void -; %r1 = lshr i65 2, 18446744073709551617 + ; CHECK: store i65 undef store i65 %r1, i65* %p %r2 = ashr i65 4, 18446744073709551617 + ; CHECK: store i65 undef store i65 %r2, i65* %p %r3 = shl i65 1, 18446744073709551617 + ; CHECK: store i65 undef store i65 %r3, i65* %p ret void } +; CHECK-LABEL: shift_undef_256 define void @shift_undef_256(i256* %p) { -; CHECK-LABEL: @shift_undef_256( -; CHECK-NEXT: [[R1:%.*]] = lshr i256 2, 18446744073709551617 -; CHECK-NEXT: store i256 [[R1]], i256* [[P:%.*]] -; CHECK-NEXT: [[R2:%.*]] = ashr i256 4, 18446744073709551618 -; CHECK-NEXT: store i256 [[R2]], i256* [[P]] -; CHECK-NEXT: [[R3:%.*]] = shl i256 1, 18446744073709551619 -; CHECK-NEXT: store i256 [[R3]], i256* [[P]] -; CHECK-NEXT: ret void -; %r1 = lshr i256 2, 18446744073709551617 + ; CHECK: store i256 undef store i256 %r1, i256* %p %r2 = ashr i256 4, 18446744073709551618 + ; CHECK: store i256 undef store i256 %r2, i256* %p %r3 = shl i256 1, 18446744073709551619 + ; CHECK: store i256 undef store i256 %r3, i256* %p ret void } +; CHECK-LABEL: shift_undef_511 define void @shift_undef_511(i511* %p) { -; CHECK-LABEL: @shift_undef_511( -; CHECK-NEXT: [[R1:%.*]] = lshr i511 -1, 1208925819614629174706276 -; CHECK-NEXT: store i511 [[R1]], i511* [[P:%.*]] -; CHECK-NEXT: [[R2:%.*]] = ashr i511 -2, 1208925819614629174706200 -; CHECK-NEXT: store i511 [[R2]], i511* [[P]] -; CHECK-NEXT: [[R3:%.*]] = shl i511 -3, 1208925819614629174706180 -; CHECK-NEXT: store i511 [[R3]], i511* [[P]] -; CHECK-NEXT: ret void -; %r1 = lshr i511 -1, 1208925819614629174706276 ; 2^80 + 100 + ; CHECK: store i511 undef store i511 %r1, i511* %p %r2 = ashr i511 -2, 1208925819614629174706200 + ; CHECK: store i511 undef store i511 %r2, i511* %p %r3 = shl i511 -3, 1208925819614629174706180 + ; CHECK: store i511 undef store i511 %r3, i511* %p ret void diff --git a/llvm/test/Transforms/SCCP/undef-resolve.ll b/llvm/test/Transforms/SCCP/undef-resolve.ll index e2a4268596f4..7fdcd556dae6 100644 --- a/llvm/test/Transforms/SCCP/undef-resolve.ll +++ b/llvm/test/Transforms/SCCP/undef-resolve.ll @@ -1,15 +1,12 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -sccp -S < %s | FileCheck %s ; PR6940 define double @test1() { -; CHECK-LABEL: @test1( -; CHECK-NEXT: [[T:%.*]] = sitofp i32 undef to double -; CHECK-NEXT: ret double [[T]] -; %t = sitofp i32 undef to double ret double %t +; CHECK-LABEL: @test1( +; CHECK: ret double 0.0 } @@ -17,72 +14,6 @@ define double @test1() { ; Check that lots of stuff doesn't get turned into undef. define i32 @test2() nounwind readnone ssp { ; CHECK-LABEL: @test2( -; CHECK-NEXT: init: -; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER:%.*]] -; CHECK: control.outer.loopexit.us-lcssa: -; CHECK-NEXT: br label [[CONTROL_OUTER_LOOPEXIT:%.*]] -; CHECK: control.outer.loopexit: -; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER_BACKEDGE:%.*]] -; CHECK: control.outer.outer: -; CHECK-NEXT: [[SWITCHCOND_0_PH_PH:%.*]] = phi i32 [ 2, [[INIT:%.*]] ], [ 3, [[CONTROL_OUTER_OUTER_BACKEDGE]] ] -; CHECK-NEXT: [[I_0_PH_PH:%.*]] = phi i32 [ undef, [[INIT]] ], [ [[I_0_PH_PH_BE:%.*]], [[CONTROL_OUTER_OUTER_BACKEDGE]] ] -; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[I_0_PH_PH]], 0 -; CHECK-NEXT: br i1 [[TMP4]], label [[CONTROL_OUTER_OUTER_SPLIT_US:%.*]], label [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE:%.*]] -; CHECK: control.outer.outer.control.outer.outer.split_crit_edge: -; CHECK-NEXT: br label [[CONTROL_OUTER:%.*]] -; CHECK: control.outer.outer.split.us: -; CHECK-NEXT: br label [[CONTROL_OUTER_US:%.*]] -; CHECK: control.outer.us: -; CHECK-NEXT: [[A_0_PH_US:%.*]] = phi i32 [ [[SWITCHCOND_0_US:%.*]], [[BB3_US:%.*]] ], [ 4, [[CONTROL_OUTER_OUTER_SPLIT_US]] ] -; CHECK-NEXT: [[SWITCHCOND_0_PH_US:%.*]] = phi i32 [ [[A_0_PH_US]], [[BB3_US]] ], [ [[SWITCHCOND_0_PH_PH]], [[CONTROL_OUTER_OUTER_SPLIT_US]] ] -; CHECK-NEXT: br label [[CONTROL_US:%.*]] -; CHECK: bb3.us: -; CHECK-NEXT: br label [[CONTROL_OUTER_US]] -; CHECK: bb0.us: -; CHECK-NEXT: br label [[CONTROL_US]] -; CHECK: control.us: -; CHECK-NEXT: [[SWITCHCOND_0_US]] = phi i32 [ [[A_0_PH_US]], [[BB0_US:%.*]] ], [ [[SWITCHCOND_0_PH_US]], [[CONTROL_OUTER_US]] ] -; CHECK-NEXT: switch i32 [[SWITCHCOND_0_US]], label [[CONTROL_OUTER_LOOPEXIT_US_LCSSA_US:%.*]] [ -; CHECK-NEXT: i32 0, label [[BB0_US]] -; CHECK-NEXT: i32 1, label [[BB1_US_LCSSA_US:%.*]] -; CHECK-NEXT: i32 3, label [[BB3_US]] -; CHECK-NEXT: i32 4, label [[BB4_US_LCSSA_US:%.*]] -; CHECK-NEXT: ] -; CHECK: control.outer.loopexit.us-lcssa.us: -; CHECK-NEXT: br label [[CONTROL_OUTER_LOOPEXIT]] -; CHECK: bb1.us-lcssa.us: -; CHECK-NEXT: br label [[BB1:%.*]] -; CHECK: bb4.us-lcssa.us: -; CHECK-NEXT: br label [[BB4:%.*]] -; CHECK: control.outer: -; CHECK-NEXT: [[A_0_PH:%.*]] = phi i32 [ [[NEXTID17:%.*]], [[BB3:%.*]] ], [ 4, [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE]] ] -; CHECK-NEXT: [[SWITCHCOND_0_PH:%.*]] = phi i32 [ 0, [[BB3]] ], [ [[SWITCHCOND_0_PH_PH]], [[CONTROL_OUTER_OUTER_CONTROL_OUTER_OUTER_SPLIT_CRIT_EDGE]] ] -; CHECK-NEXT: br label [[CONTROL:%.*]] -; CHECK: control: -; CHECK-NEXT: [[SWITCHCOND_0:%.*]] = phi i32 [ [[A_0_PH]], [[BB0:%.*]] ], [ [[SWITCHCOND_0_PH]], [[CONTROL_OUTER]] ] -; CHECK-NEXT: switch i32 [[SWITCHCOND_0]], label [[CONTROL_OUTER_LOOPEXIT_US_LCSSA:%.*]] [ -; CHECK-NEXT: i32 0, label [[BB0]] -; CHECK-NEXT: i32 1, label [[BB1_US_LCSSA:%.*]] -; CHECK-NEXT: i32 3, label [[BB3]] -; CHECK-NEXT: i32 4, label [[BB4_US_LCSSA:%.*]] -; CHECK-NEXT: ] -; CHECK: bb4.us-lcssa: -; CHECK-NEXT: br label [[BB4]] -; CHECK: bb4: -; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER_BACKEDGE]] -; CHECK: control.outer.outer.backedge: -; CHECK-NEXT: [[I_0_PH_PH_BE]] = phi i32 [ 1, [[BB4]] ], [ 0, [[CONTROL_OUTER_LOOPEXIT]] ] -; CHECK-NEXT: br label [[CONTROL_OUTER_OUTER]] -; CHECK: bb3: -; CHECK-NEXT: [[NEXTID17]] = add i32 [[SWITCHCOND_0]], -2 -; CHECK-NEXT: br label [[CONTROL_OUTER]] -; CHECK: bb0: -; CHECK-NEXT: br label [[CONTROL]] -; CHECK: bb1.us-lcssa: -; CHECK-NEXT: br label [[BB1]] -; CHECK: bb1: -; CHECK-NEXT: ret i32 0 -; init: br label %control.outer.outer @@ -115,13 +46,16 @@ bb3.us: ; preds = %control.us bb0.us: ; preds = %control.us br label %control.us +; CHECK: control.us: ; preds = %bb0.us, %control.outer.us +; CHECK-NEXT: %switchCond.0.us = phi i32 +; CHECK-NEXT: switch i32 %switchCond.0.us control.us: ; preds = %bb0.us, %control.outer.us %switchCond.0.us = phi i32 [ %A.0.ph.us, %bb0.us ], [ %switchCond.0.ph.us, %control.outer.us ] ; [#uses=2] switch i32 %switchCond.0.us, label %control.outer.loopexit.us-lcssa.us [ - i32 0, label %bb0.us - i32 1, label %bb1.us-lcssa.us - i32 3, label %bb3.us - i32 4, label %bb4.us-lcssa.us + i32 0, label %bb0.us + i32 1, label %bb1.us-lcssa.us + i32 3, label %bb3.us + i32 4, label %bb4.us-lcssa.us ] control.outer.loopexit.us-lcssa.us: ; preds = %control.us @@ -141,10 +75,10 @@ control.outer: ; preds = %bb3, %control.outer control: ; preds = %bb0, %control.outer %switchCond.0 = phi i32 [ %A.0.ph, %bb0 ], [ %switchCond.0.ph, %control.outer ] ; [#uses=2] switch i32 %switchCond.0, label %control.outer.loopexit.us-lcssa [ - i32 0, label %bb0 - i32 1, label %bb1.us-lcssa - i32 3, label %bb3 - i32 4, label %bb4.us-lcssa + i32 0, label %bb0 + i32 1, label %bb1.us-lcssa + i32 3, label %bb3 + i32 4, label %bb4.us-lcssa ] bb4.us-lcssa: ; preds = %control @@ -174,105 +108,83 @@ bb1: ; preds = %bb1.us-lcssa, %bb1. ; Make sure SCCP honors the xor "idiom" ; rdar://9956541 define i32 @test3() { -; CHECK-LABEL: @test3( -; CHECK-NEXT: [[T:%.*]] = xor i32 undef, undef -; CHECK-NEXT: ret i32 [[T]] -; %t = xor i32 undef, undef ret i32 %t +; CHECK-LABEL: @test3( +; CHECK: ret i32 0 } ; Be conservative with FP ops define double @test4(double %x) { -; CHECK-LABEL: @test4( -; CHECK-NEXT: [[T:%.*]] = fadd double [[X:%.*]], undef -; CHECK-NEXT: ret double [[T]] -; %t = fadd double %x, undef ret double %t +; CHECK-LABEL: @test4( +; CHECK: fadd double %x, undef } ; Make sure casts produce a possible value define i32 @test5() { -; CHECK-LABEL: @test5( -; CHECK-NEXT: [[T:%.*]] = sext i8 undef to i32 -; CHECK-NEXT: ret i32 [[T]] -; %t = sext i8 undef to i32 ret i32 %t +; CHECK-LABEL: @test5( +; CHECK: ret i32 0 } ; Make sure ashr produces a possible value define i32 @test6() { -; CHECK-LABEL: @test6( -; CHECK-NEXT: [[T:%.*]] = ashr i32 undef, 31 -; CHECK-NEXT: ret i32 [[T]] -; %t = ashr i32 undef, 31 ret i32 %t +; CHECK-LABEL: @test6( +; CHECK: ret i32 0 } ; Make sure lshr produces a possible value define i32 @test7() { -; CHECK-LABEL: @test7( -; CHECK-NEXT: [[T:%.*]] = lshr i32 undef, 31 -; CHECK-NEXT: ret i32 [[T]] -; %t = lshr i32 undef, 31 ret i32 %t +; CHECK-LABEL: @test7( +; CHECK: ret i32 0 } ; icmp eq with undef simplifies to undef define i1 @test8() { -; CHECK-LABEL: @test8( -; CHECK-NEXT: [[T:%.*]] = icmp eq i32 undef, -1 -; CHECK-NEXT: ret i1 [[T]] -; %t = icmp eq i32 undef, -1 ret i1 %t +; CHECK-LABEL: @test8( +; CHECK: ret i1 undef } ; Make sure we don't conclude that relational comparisons simplify to undef define i1 @test9() { -; CHECK-LABEL: @test9( -; CHECK-NEXT: [[T:%.*]] = icmp ugt i32 undef, -1 -; CHECK-NEXT: ret i1 [[T]] -; %t = icmp ugt i32 undef, -1 ret i1 %t +; CHECK-LABEL: @test9( +; CHECK: icmp ugt } ; Make sure we handle extractvalue -define i64 @test10() { -; CHECK-LABEL: @test10( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[E:%.*]] = extractvalue { i64, i64 } undef, 1 -; CHECK-NEXT: ret i64 [[E]] -; +define i64 @test10() { entry: %e = extractvalue { i64, i64 } undef, 1 ret i64 %e +; CHECK-LABEL: @test10( +; CHECK: ret i64 undef } @GV = external global i32 define i32 @test11(i1 %tobool) { -; CHECK-LABEL: @test11( -; CHECK-NEXT: entry: -; CHECK-NEXT: [[SHR4:%.*]] = ashr i32 undef, zext (i1 icmp eq (i32* bitcast (i32 (i1)* @test11 to i32*), i32* @GV) to i32) -; CHECK-NEXT: ret i32 [[SHR4]] -; entry: %shr4 = ashr i32 undef, zext (i1 icmp eq (i32* bitcast (i32 (i1)* @test11 to i32*), i32* @GV) to i32) ret i32 %shr4 +; CHECK-LABEL: @test11( +; CHECK: ret i32 0 } ; Test unary ops define double @test12(double %x) { -; CHECK-LABEL: @test12( -; CHECK-NEXT: [[T:%.*]] = fneg double undef -; CHECK-NEXT: ret double [[T]] -; %t = fneg double undef ret double %t +; CHECK-LABEL: @test12( +; CHECK: double undef } -- GitLab From 55e2678fcd4d7eca3f9a602a919da499c1103041 Mon Sep 17 00:00:00 2001 From: jasonliu Date: Tue, 11 Feb 2020 09:52:56 +0000 Subject: [PATCH 142/142] [clang] Add -fignore-exceptions Summary: This is trying to implement the functionality proposed in: http://lists.llvm.org/pipermail/cfe-dev/2017-April/053417.html An exception can throw, but no cleanup is going to happen. A module compiled with exceptions on, can catch the exception throws from module compiled with -fignore-exceptions. The use cases for enabling this option are: 1. Performance analysis of EH instrumentation overhead 2. The ability to QA non EH functionality when EH functionality is not available. 3. User of EH enabled headers knows the calls won't throw in their program and wants the performance gain from ignoring EH construct. The implementation tried to accomplish that by removing any landing pad code that might get generated. Reviewed by: aaron.ballman Differential Revision: https://reviews.llvm.org/D72644 --- clang/include/clang/Basic/LangOptions.def | 1 + clang/include/clang/Driver/Options.td | 2 ++ clang/lib/CodeGen/CGException.cpp | 12 ++++++----- clang/lib/Driver/ToolChains/Clang.cpp | 5 +++++ clang/lib/Frontend/CompilerInvocation.cpp | 1 + clang/test/CodeGen/ignore-exceptions.cpp | 25 +++++++++++++++++++++++ 6 files changed, 41 insertions(+), 5 deletions(-) create mode 100644 clang/test/CodeGen/ignore-exceptions.cpp diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def index 4c7f7dde1f7d..3cc7c384ac10 100644 --- a/clang/include/clang/Basic/LangOptions.def +++ b/clang/include/clang/Basic/LangOptions.def @@ -132,6 +132,7 @@ LANGOPT(DWARFExceptions , 1, 0, "dwarf exception handling") LANGOPT(SjLjExceptions , 1, 0, "setjmp-longjump exception handling") LANGOPT(SEHExceptions , 1, 0, "SEH .xdata exception handling") LANGOPT(WasmExceptions , 1, 0, "WebAssembly exception handling") +LANGOPT(IgnoreExceptions , 1, 0, "ignore exceptions") LANGOPT(ExternCNoUnwind , 1, 0, "Assume extern C functions don't unwind") LANGOPT(TraditionalCPP , 1, 0, "traditional CPP emulation") LANGOPT(RTTI , 1, 1, "run-time type information") diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 5987e735c77a..b0e9d9590fde 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -932,6 +932,8 @@ def fseh_exceptions : Flag<["-"], "fseh-exceptions">, Group, Flags<[CC1Option]>, HelpText<"Use SEH style exceptions">; def fwasm_exceptions : Flag<["-"], "fwasm-exceptions">, Group, Flags<[CC1Option]>, HelpText<"Use WebAssembly style exceptions">; +def fignore_exceptions : Flag<["-"], "fignore-exceptions">, Group, Flags<[CC1Option]>, + HelpText<"Enable support for ignoring exception handling constructs">; def fexcess_precision_EQ : Joined<["-"], "fexcess-precision=">, Group; def : Flag<["-"], "fexpensive-optimizations">, Group; diff --git a/clang/lib/CodeGen/CGException.cpp b/clang/lib/CodeGen/CGException.cpp index fffd9897270e..a542c3d85a84 100644 --- a/clang/lib/CodeGen/CGException.cpp +++ b/clang/lib/CodeGen/CGException.cpp @@ -703,12 +703,12 @@ llvm::BasicBlock *CodeGenFunction::getInvokeDestImpl() { assert(EHStack.requiresLandingPad()); assert(!EHStack.empty()); - // If exceptions are disabled and SEH is not in use, then there is no invoke - // destination. SEH "works" even if exceptions are off. In practice, this - // means that C++ destructors and other EH cleanups don't run, which is + // If exceptions are disabled/ignored and SEH is not in use, then there is no + // invoke destination. SEH "works" even if exceptions are off. In practice, + // this means that C++ destructors and other EH cleanups don't run, which is // consistent with MSVC's behavior. const LangOptions &LO = CGM.getLangOpts(); - if (!LO.Exceptions) { + if (!LO.Exceptions || LO.IgnoreExceptions) { if (!LO.Borland && !LO.MicrosoftExt) return nullptr; if (!currentFunctionUsesSEHTry()) @@ -751,7 +751,9 @@ llvm::BasicBlock *CodeGenFunction::getInvokeDestImpl() { llvm::BasicBlock *CodeGenFunction::EmitLandingPad() { assert(EHStack.requiresLandingPad()); - + assert(!CGM.getLangOpts().IgnoreExceptions && + "LandingPad should not be emitted when -fignore-exceptions are in " + "effect."); EHScope &innermostEHScope = *EHStack.find(EHStack.getInnermostEHScope()); switch (innermostEHScope.getKind()) { case EHScope::Terminate: diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 7901f8a48f5f..4424d8e6f72c 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -463,6 +463,11 @@ static void addExceptionArgs(const ArgList &Args, types::ID InputType, } } + // OPT_fignore_exceptions means exception could still be thrown, + // but no clean up or catch would happen in current module. + // So we do not set EH to false. + Args.AddLastArg(CmdArgs, options::OPT_fignore_exceptions); + if (EH) CmdArgs.push_back("-fexceptions"); } diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index dca80562b445..2a7ec58b2141 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -2773,6 +2773,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK, if (Args.hasArg(OPT_fno_threadsafe_statics)) Opts.ThreadsafeStatics = 0; Opts.Exceptions = Args.hasArg(OPT_fexceptions); + Opts.IgnoreExceptions = Args.hasArg(OPT_fignore_exceptions); Opts.ObjCExceptions = Args.hasArg(OPT_fobjc_exceptions); Opts.CXXExceptions = Args.hasArg(OPT_fcxx_exceptions); diff --git a/clang/test/CodeGen/ignore-exceptions.cpp b/clang/test/CodeGen/ignore-exceptions.cpp new file mode 100644 index 000000000000..c2770005cb73 --- /dev/null +++ b/clang/test/CodeGen/ignore-exceptions.cpp @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 %s -triple powerpc64-linux -fexceptions -fcxx-exceptions -fignore-exceptions -emit-llvm -o - | FileCheck %s + +struct A { + ~A(){} +}; + +void f(void) { +// CHECK-NOT: personality i8* bitcast (i32 (...)* @__gcc_personality_v0 to i8*) + A a; + try { + throw 1; + } catch(...) { + } +// CHECK: %a = alloca %struct.A, align 1 +// CHECK: %exception = call i8* @__cxa_allocate_exception(i64 4) #1 +// CHECK: %0 = bitcast i8* %exception to i32* +// CHECK: store i32 1, i32* %0, align 16 +// CHECK: call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #2 +// CHECK: unreachable + +// CHECK-NOT: invoke +// CHECK-NOT: landingpad +// CHECK-NOT: __cxa_begin_catch +// CHECK-NOT: __cxa_end_catch +} -- GitLab