diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index ab871a25d073f5c2554dbae159038c2580ba74d3..11cc699ffe1eb741b8e818b7f8a8a4653ecf450b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -10898,7 +10898,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { auto isFMulNegTwo = [](SDValue FMul) { if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) return false; - auto *C = isConstOrConstSplatFP(FMul.getOperand(1)); + auto *C = isConstOrConstSplatFP(FMul.getOperand(1), true); return C && C->isExactlyValue(-2.0); }; diff --git a/llvm/test/CodeGen/AArch64/fadd-combines.ll b/llvm/test/CodeGen/AArch64/fadd-combines.ll index c2e4430029ad387f4668faf9980a5f39c15626c3..7332101a481e610c037cf34bc77cfd237cd4900d 100644 --- a/llvm/test/CodeGen/AArch64/fadd-combines.ll +++ b/llvm/test/CodeGen/AArch64/fadd-combines.ll @@ -76,9 +76,8 @@ define <4 x float> @fmulnegtwo_vec_commute(<4 x float> %a, <4 x float> %b) { define <4 x float> @fmulnegtwo_vec_undefs(<4 x float> %a, <4 x float> %b) { ; CHECK-LABEL: fmulnegtwo_vec_undefs: ; CHECK: // %bb.0: -; CHECK-NEXT: movi v2.4s, #192, lsl #24 -; CHECK-NEXT: fmul v1.4s, v1.4s, v2.4s -; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s +; CHECK-NEXT: fadd v1.4s, v1.4s, v1.4s +; CHECK-NEXT: fsub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %mul = fmul <4 x float> %b, %add = fadd <4 x float> %a, %mul @@ -88,9 +87,8 @@ define <4 x float> @fmulnegtwo_vec_undefs(<4 x float> %a, <4 x float> %b) { define <4 x float> @fmulnegtwo_vec_commute_undefs(<4 x float> %a, <4 x float> %b) { ; CHECK-LABEL: fmulnegtwo_vec_commute_undefs: ; CHECK: // %bb.0: -; CHECK-NEXT: movi v2.4s, #192, lsl #24 -; CHECK-NEXT: fmul v1.4s, v1.4s, v2.4s -; CHECK-NEXT: fadd v0.4s, v1.4s, v0.4s +; CHECK-NEXT: fadd v1.4s, v1.4s, v1.4s +; CHECK-NEXT: fsub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %mul = fmul <4 x float> %b, %add = fadd <4 x float> %mul, %a