diff --git a/bolt/lib/Core/BinaryFunction.cpp b/bolt/lib/Core/BinaryFunction.cpp index ef3fba37817daa541f28528f62555dd2df8676f9..c12217d549479bc0452367a46862f456aec777de 100644 --- a/bolt/lib/Core/BinaryFunction.cpp +++ b/bolt/lib/Core/BinaryFunction.cpp @@ -2577,6 +2577,7 @@ private: case MCCFIInstruction::OpAdjustCfaOffset: case MCCFIInstruction::OpWindowSave: case MCCFIInstruction::OpNegateRAState: + case MCCFIInstruction::OpNegateRAStateWithPC: case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: llvm_unreachable("unsupported CFI opcode"); @@ -2715,6 +2716,7 @@ struct CFISnapshotDiff : public CFISnapshot { case MCCFIInstruction::OpAdjustCfaOffset: case MCCFIInstruction::OpWindowSave: case MCCFIInstruction::OpNegateRAState: + case MCCFIInstruction::OpNegateRAStateWithPC: case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: llvm_unreachable("unsupported CFI opcode"); @@ -2864,6 +2866,7 @@ BinaryFunction::unwindCFIState(int32_t FromState, int32_t ToState, case MCCFIInstruction::OpAdjustCfaOffset: case MCCFIInstruction::OpWindowSave: case MCCFIInstruction::OpNegateRAState: + case MCCFIInstruction::OpNegateRAStateWithPC: case MCCFIInstruction::OpLLVMDefAspaceCfa: case MCCFIInstruction::OpLabel: llvm_unreachable("unsupported CFI opcode"); diff --git a/clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp b/clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp index 2a0cc403b726e8d4050ff63dfab3a00e15839fb5..3132067f3d5ece6c094ea6fe90593f4641128b44 100644 --- a/clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp +++ b/clang-tools-extra/clang-tidy/modernize/UseDesignatedInitializersCheck.cpp @@ -80,9 +80,13 @@ unsigned getNumberOfDesignated(const InitListExpr *SyntacticInitList) { }); } -AST_MATCHER(CXXRecordDecl, isAggregate) { return Node.isAggregate(); } +AST_MATCHER(CXXRecordDecl, isAggregate) { + return Node.hasDefinition() && Node.isAggregate(); +} -AST_MATCHER(CXXRecordDecl, isPOD) { return Node.isPOD(); } +AST_MATCHER(CXXRecordDecl, isPOD) { + return Node.hasDefinition() && Node.isPOD(); +} AST_MATCHER(InitListExpr, isFullyDesignated) { if (const InitListExpr *SyntacticForm = diff --git a/clang-tools-extra/clangd/ModulesBuilder.cpp b/clang-tools-extra/clangd/ModulesBuilder.cpp index 1eeff468ef1236f71acf4b770e29bf05d0d8d366..97f67ddf5495a2d2fb63bea3e2ffb12bcb7efc00 100644 --- a/clang-tools-extra/clangd/ModulesBuilder.cpp +++ b/clang-tools-extra/clangd/ModulesBuilder.cpp @@ -12,6 +12,7 @@ #include "clang/Frontend/FrontendAction.h" #include "clang/Frontend/FrontendActions.h" #include "clang/Serialization/ASTReader.h" +#include "clang/Serialization/InMemoryModuleCache.h" namespace clang { namespace clangd { @@ -127,50 +128,68 @@ struct ModuleFile { std::string ModuleFilePath; }; -bool IsModuleFileUpToDate( - PathRef ModuleFilePath, - const PrerequisiteModules &RequisiteModules) { -IntrusiveRefCntPtr Diags = - CompilerInstance::createDiagnostics(new DiagnosticOptions()); - +bool IsModuleFileUpToDate(PathRef ModuleFilePath, + const PrerequisiteModules &RequisiteModules, + llvm::IntrusiveRefCntPtr VFS) { auto HSOpts = std::make_shared(); RequisiteModules.adjustHeaderSearchOptions(*HSOpts); HSOpts->ForceCheckCXX20ModulesInputFiles = true; HSOpts->ValidateASTInputFilesContent = true; + clang::clangd::IgnoreDiagnostics IgnoreDiags; + IntrusiveRefCntPtr Diags = + CompilerInstance::createDiagnostics(new DiagnosticOptions, &IgnoreDiags, + /*ShouldOwnClient=*/false); + + LangOptions LangOpts; + LangOpts.SkipODRCheckInGMF = true; + + FileManager FileMgr(FileSystemOptions(), VFS); + + SourceManager SourceMgr(*Diags, FileMgr); + + HeaderSearch HeaderInfo(HSOpts, SourceMgr, *Diags, LangOpts, + /*Target=*/nullptr); + + TrivialModuleLoader ModuleLoader; + Preprocessor PP(std::make_shared(), *Diags, LangOpts, + SourceMgr, HeaderInfo, ModuleLoader); + + IntrusiveRefCntPtr ModuleCache = new InMemoryModuleCache; PCHContainerOperations PCHOperations; - std::unique_ptr Unit = ASTUnit::LoadFromASTFile( - ModuleFilePath.str(), PCHOperations.getRawReader(), ASTUnit::LoadASTOnly, - Diags, FileSystemOptions(), std::move(HSOpts)); + ASTReader Reader(PP, *ModuleCache, /*ASTContext=*/nullptr, + PCHOperations.getRawReader(), {}); - if (!Unit) - return false; + // We don't need any listener here. By default it will use a validator + // listener. + Reader.setListener(nullptr); - auto Reader = Unit->getASTReader(); - if (!Reader) + if (Reader.ReadAST(ModuleFilePath, serialization::MK_MainFile, + SourceLocation(), + ASTReader::ARR_None) != ASTReader::Success) return false; bool UpToDate = true; - Reader->getModuleManager().visit([&](serialization::ModuleFile &MF) -> bool { - Reader->visitInputFiles( + Reader.getModuleManager().visit([&](serialization::ModuleFile &MF) -> bool { + Reader.visitInputFiles( MF, /*IncludeSystem=*/false, /*Complain=*/false, [&](const serialization::InputFile &IF, bool isSystem) { if (!IF.getFile() || IF.isOutOfDate()) UpToDate = false; }); - return !UpToDate; }); - return UpToDate; } bool IsModuleFilesUpToDate( llvm::SmallVector ModuleFilePaths, - const PrerequisiteModules &RequisiteModules) { - return llvm::all_of(ModuleFilePaths, [&RequisiteModules](auto ModuleFilePath) { - return IsModuleFileUpToDate(ModuleFilePath, RequisiteModules); - }); + const PrerequisiteModules &RequisiteModules, + llvm::IntrusiveRefCntPtr VFS) { + return llvm::all_of( + ModuleFilePaths, [&RequisiteModules, VFS](auto ModuleFilePath) { + return IsModuleFileUpToDate(ModuleFilePath, RequisiteModules, VFS); + }); } // StandalonePrerequisiteModules - stands for PrerequisiteModules for which all @@ -347,7 +366,7 @@ bool StandalonePrerequisiteModules::canReuse( SmallVector BMIPaths; for (auto &MF : RequiredModules) BMIPaths.push_back(MF.ModuleFilePath); - return IsModuleFilesUpToDate(BMIPaths, *this); + return IsModuleFilesUpToDate(BMIPaths, *this, VFS); } } // namespace clangd diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 54118e5f92f417348c3e8b158036b0915fade943..ccebf74e8a67e7361f84ce5885cdffa6982c5d14 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -216,6 +216,10 @@ Changes in existing checks a false positive when only an implicit conversion happened inside an initializer list. +- Improved :doc:`modernize-use-designated-initializers + ` check to fix a + crash when a class is declared but not defined. + - Improved :doc:`modernize-use-nullptr ` check to also recognize ``NULL``/``__null`` (but not ``0``) when used with a templated type. diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers.cpp b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers.cpp index 9b769ad0be23cab8e399bea24797f95b45973a46..048665b2e54ac5aa27674c77bc54fb23c0437a2b 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-designated-initializers.cpp @@ -201,3 +201,11 @@ DECLARE_S93; // CHECK-MESSAGES-MACROS: :[[@LINE-1]]:1: warning: use designated initializer list to initialize 'S9' [modernize-use-designated-initializers] // CHECK-MESSAGES-MACROS: :[[@LINE-4]]:28: note: expanded from macro 'DECLARE_S93' // CHECK-MESSAGES-MACROS: :[[@LINE-71]]:1: note: aggregate type is defined here + +// Issue #113652. +struct S14; + +struct S15{ + S15(S14& d):d{d}{} + S14& d; +}; diff --git a/clang/Maintainers.rst b/clang/Maintainers.rst index 54690452681a608449367e569562ea8caab423d8..35c218d8e0e8fa434f2b68d7e1215eb59f4b2c05 100644 --- a/clang/Maintainers.rst +++ b/clang/Maintainers.rst @@ -33,6 +33,12 @@ AST matchers | aaron\@aaronballman.com (email), aaron.ballman (Phabricator), AaronBallman (GitHub), AaronBallman (Discourse), aaronballman (Discord), AaronBallman (IRC) +AST Visitors +~~~~~~~~~~~~ +| Sirraide +| aeternalmail\@gmail.com (email), Sirraide (GitHub), Ætérnal (Discord), Sirraide (Discourse) + + Clang LLVM IR generation ~~~~~~~~~~~~~~~~~~~~~~~~ | John McCall @@ -57,6 +63,12 @@ Analysis & CFG | sgatev\@google.com (email), sgatev (Phabricator), sgatev (GitHub) +Sema +~~~~ +| Sirraide +| aeternalmail\@gmail.com (email), Sirraide (GitHub), Ætérnal (Discord), Sirraide (Discourse) + + Experimental new constant interpreter ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | Timm Bäder @@ -71,6 +83,9 @@ Modules & serialization | Michael Spencer | bigcheesegs\@gmail.com (email), Bigcheese (Phabricator), Bigcheese (GitHub) +| Vassil Vassilev +| Vassil.Vassilev\@cern.ch (email), v.g.vassilev (Phabricator), vgvassilev (GitHub) + Templates ~~~~~~~~~ @@ -78,6 +93,12 @@ Templates | ekeane\@nvidia.com (email), ErichKeane (Phabricator), erichkeane (GitHub) +Lambdas +~~~~~~~ +| Corentin Jabot +| corentin.jabot\@gmail.com (email), cor3ntin (Phabricator), cor3ntin (GitHub) + + Debug information ~~~~~~~~~~~~~~~~~ | Adrian Prantl @@ -172,6 +193,12 @@ Attributes | ekeane\@nvidia.com (email), ErichKeane (Phabricator), erichkeane (GitHub) +Plugins +~~~~~~~ +| Vassil Vassilev +| Vassil.Vassilev\@cern.ch (email), v.g.vassilev (Phabricator), vgvassilev (GitHub) + + Inline assembly ~~~~~~~~~~~~~~~ | Eric Christopher @@ -225,6 +252,12 @@ C++ conformance | Hubert Tong | hubert.reinterpretcast\@gmail.com (email), hubert.reinterpretcast (Phabricator), hubert-reinterpretcast (GitHub) +| Shafik Yaghmour +| shafik.yaghmour\@intel.com (email), shafik (GitHub), shafik.yaghmour (Discord), shafik (Discourse) + +| Vlad Serebrennikov +| serebrennikov.vladislav\@gmail.com (email), Endilll (GitHub), Endill (Discord), Endill (Discourse) + C++ Defect Reports ~~~~~~~~~~~~~~~~~~ diff --git a/clang/docs/ClangFormat.rst b/clang/docs/ClangFormat.rst index dbd9c91ae508e5d8175c5e1734e4fcdb34c80090..7afad5b15b2d547f724d5cc31f580ed90b4c1146 100644 --- a/clang/docs/ClangFormat.rst +++ b/clang/docs/ClangFormat.rst @@ -363,8 +363,3 @@ those as well). These commands use the file paths shown in the diff output so they will only work from the root of the repository. - -Current State of Clang Format for LLVM -====================================== - -The following table :doc:`ClangFormattedStatus` shows the current status of clang-formatting for the entire LLVM source tree. diff --git a/clang/docs/ClangFormattedStatus.rst b/clang/docs/ClangFormattedStatus.rst deleted file mode 100644 index 2475a5d4b2775b2ac180f162a877d604b93c401d..0000000000000000000000000000000000000000 --- a/clang/docs/ClangFormattedStatus.rst +++ /dev/null @@ -1,8536 +0,0 @@ -.. raw:: html - - - -.. role:: none -.. role:: part -.. role:: good -.. role:: total - -====================== -Clang Formatted Status -====================== - -:doc:`ClangFormattedStatus` describes the state of LLVM source -tree in terms of conformance to :doc:`ClangFormat` as of: March 06, 2022 17:32:26 (`830ba4cebe79 `_). - - -.. list-table:: LLVM Clang-Format Status - :widths: 50 25 25 25 25 - :header-rows: 1 - - * - Directory - - Total Files - - Formatted Files - - Unformatted Files - - % Complete - * - bolt/include/bolt/Core - - `15` - - `10` - - `5` - - :part:`66%` - * - bolt/include/bolt/Passes - - `47` - - `47` - - `0` - - :good:`100%` - * - bolt/include/bolt/Profile - - `8` - - `8` - - `0` - - :good:`100%` - * - bolt/include/bolt/Rewrite - - `5` - - `4` - - `1` - - :part:`80%` - * - bolt/include/bolt/RuntimeLibs - - `3` - - `3` - - `0` - - :good:`100%` - * - bolt/include/bolt/Utils - - `4` - - `4` - - `0` - - :good:`100%` - * - bolt/lib/Core - - `14` - - `5` - - `9` - - :part:`35%` - * - bolt/lib/Passes - - `45` - - `21` - - `24` - - :part:`46%` - * - bolt/lib/Profile - - `7` - - `3` - - `4` - - :part:`42%` - * - bolt/lib/Rewrite - - `6` - - `0` - - `6` - - :none:`0%` - * - bolt/lib/RuntimeLibs - - `3` - - `3` - - `0` - - :good:`100%` - * - bolt/lib/Target/AArch64 - - `1` - - `0` - - `1` - - :none:`0%` - * - bolt/lib/Target/X86 - - `1` - - `0` - - `1` - - :none:`0%` - * - bolt/lib/Utils - - `2` - - `1` - - `1` - - :part:`50%` - * - bolt/runtime - - `3` - - `0` - - `3` - - :none:`0%` - * - bolt/tools/driver - - `1` - - `0` - - `1` - - :none:`0%` - * - bolt/tools/heatmap - - `1` - - `1` - - `0` - - :good:`100%` - * - bolt/tools/llvm-bolt-fuzzer - - `1` - - `1` - - `0` - - :good:`100%` - * - bolt/tools/merge-fdata - - `1` - - `0` - - `1` - - :none:`0%` - * - bolt/unittests/Core - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/bindings/python/tests/cindex/INPUTS - - `5` - - `3` - - `2` - - :part:`60%` - * - clang/docs/analyzer/checkers - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/examples/AnnotateFunctions - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/examples/Attribute - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/examples/CallSuperAttribute - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/examples/PluginsOrder - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/examples/PrintFunctionNames - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/include/clang/Analysis - - `16` - - `4` - - `12` - - :part:`25%` - * - clang/include/clang/Analysis/Analyses - - `15` - - `3` - - `12` - - :part:`20%` - * - clang/include/clang/Analysis/DomainSpecific - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/include/clang/Analysis/FlowSensitive - - `16` - - `15` - - `1` - - :part:`93%` - * - clang/include/clang/Analysis/Support - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/include/clang/APINotes - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/include/clang/ARCMigrate - - `3` - - `0` - - `3` - - :none:`0%` - * - clang/include/clang/AST - - `114` - - `20` - - `94` - - :part:`17%` - * - clang/include/clang/ASTMatchers - - `5` - - `1` - - `4` - - :part:`20%` - * - clang/include/clang/ASTMatchers/Dynamic - - `4` - - `1` - - `3` - - :part:`25%` - * - clang/include/clang/Basic - - `82` - - `32` - - `50` - - :part:`39%` - * - clang/include/clang/CodeGen - - `9` - - `0` - - `9` - - :none:`0%` - * - clang/include/clang/CrossTU - - `2` - - `1` - - `1` - - :part:`50%` - * - clang/include/clang/DirectoryWatcher - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/include/clang/Driver - - `17` - - `4` - - `13` - - :part:`23%` - * - clang/include/clang/Edit - - `5` - - `1` - - `4` - - :part:`20%` - * - clang/include/clang/Format - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/include/clang/Frontend - - `28` - - `7` - - `21` - - :part:`25%` - * - clang/include/clang/FrontendTool - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/include/clang/Index - - `7` - - `2` - - `5` - - :part:`28%` - * - clang/include/clang/IndexSerialization - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/include/clang/Interpreter - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/include/clang/Lex - - `29` - - `6` - - `23` - - :part:`20%` - * - clang/include/clang/Parse - - `5` - - `2` - - `3` - - :part:`40%` - * - clang/include/clang/Rewrite/Core - - `6` - - `0` - - `6` - - :none:`0%` - * - clang/include/clang/Rewrite/Frontend - - `4` - - `0` - - `4` - - :none:`0%` - * - clang/include/clang/Sema - - `32` - - `3` - - `29` - - :part:`9%` - * - clang/include/clang/Serialization - - `14` - - `3` - - `11` - - :part:`21%` - * - clang/include/clang/StaticAnalyzer/Checkers - - `4` - - `1` - - `3` - - :part:`25%` - * - clang/include/clang/StaticAnalyzer/Core - - `5` - - `1` - - `4` - - :part:`20%` - * - clang/include/clang/StaticAnalyzer/Core/BugReporter - - `4` - - `1` - - `3` - - :part:`25%` - * - clang/include/clang/StaticAnalyzer/Core/PathSensitive - - `37` - - `10` - - `27` - - :part:`27%` - * - clang/include/clang/StaticAnalyzer/Frontend - - `5` - - `2` - - `3` - - :part:`40%` - * - clang/include/clang/Testing - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/include/clang/Tooling - - `17` - - `10` - - `7` - - :part:`58%` - * - clang/include/clang/Tooling/ASTDiff - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/include/clang/Tooling/Core - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/include/clang/Tooling/DependencyScanning - - `5` - - `5` - - `0` - - :good:`100%` - * - clang/include/clang/Tooling/Inclusions - - `3` - - `3` - - `0` - - :good:`100%` - * - clang/include/clang/Tooling/Refactoring - - `15` - - `12` - - `3` - - :part:`80%` - * - clang/include/clang/Tooling/Refactoring/Extract - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/include/clang/Tooling/Refactoring/Rename - - `6` - - `5` - - `1` - - :part:`83%` - * - clang/include/clang/Tooling/Syntax - - `5` - - `5` - - `0` - - :good:`100%` - * - clang/include/clang/Tooling/Syntax/Pseudo - - `5` - - `5` - - `0` - - :good:`100%` - * - clang/include/clang/Tooling/Transformer - - `8` - - `6` - - `2` - - :part:`75%` - * - clang/include/clang-c - - `10` - - `3` - - `7` - - :part:`30%` - * - clang/INPUTS - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/lib/Analysis - - `28` - - `3` - - `25` - - :part:`10%` - * - clang/lib/Analysis/FlowSensitive - - `7` - - `7` - - `0` - - :good:`100%` - * - clang/lib/Analysis/plugins/CheckerDependencyHandling - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/lib/Analysis/plugins/CheckerOptionHandling - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/lib/Analysis/plugins/SampleAnalyzer - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/lib/APINotes - - `3` - - `3` - - `0` - - :good:`100%` - * - clang/lib/ARCMigrate - - `22` - - `0` - - `22` - - :none:`0%` - * - clang/lib/AST - - `81` - - `2` - - `79` - - :part:`2%` - * - clang/lib/AST/ByteCode - - `44` - - `18` - - `26` - - :part:`40%` - * - clang/lib/ASTMatchers - - `3` - - `1` - - `2` - - :part:`33%` - * - clang/lib/ASTMatchers/Dynamic - - `6` - - `1` - - `5` - - :part:`16%` - * - clang/lib/Basic - - `39` - - `13` - - `26` - - :part:`33%` - * - clang/lib/Basic/Targets - - `50` - - `25` - - `25` - - :part:`50%` - * - clang/lib/CodeGen - - `87` - - `9` - - `78` - - :part:`10%` - * - clang/lib/CrossTU - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/lib/DirectoryWatcher - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/lib/DirectoryWatcher/default - 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- `7` - - `2` - - `5` - - :part:`28%` - * - clang/lib/Index - - `11` - - `2` - - `9` - - :part:`18%` - * - clang/lib/IndexSerialization - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/lib/Interpreter - - `5` - - `5` - - `0` - - :good:`100%` - * - clang/lib/Lex - - `24` - - `1` - - `23` - - :part:`4%` - * - clang/lib/Parse - - `15` - - `1` - - `14` - - :part:`6%` - * - clang/lib/Rewrite - - `5` - - `0` - - `5` - - :none:`0%` - * - clang/lib/Sema - - `55` - - `4` - - `51` - - :part:`7%` - * - clang/lib/Serialization - - `17` - - `2` - - `15` - - :part:`11%` - * - clang/lib/StaticAnalyzer/Checkers - - `122` - - `19` - - `103` - - :part:`15%` - * - clang/lib/StaticAnalyzer/Checkers/cert - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/lib/StaticAnalyzer/Checkers/MPI-Checker - - `6` - - `0` - - `6` - - :none:`0%` - * - clang/lib/StaticAnalyzer/Checkers/RetainCountChecker - - `4` - - `0` - - `4` - - :none:`0%` - * - clang/lib/StaticAnalyzer/Checkers/UninitializedObject - - `3` - - `1` - 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* - clang/lib/Tooling/Syntax - - `7` - - `6` - - `1` - - :part:`85%` - * - clang/lib/Tooling/Syntax/Pseudo - - `8` - - `8` - - `0` - - :good:`100%` - * - clang/lib/Tooling/Transformer - - `7` - - `4` - - `3` - - :part:`57%` - * - clang/tools/amdgpu-arch - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/apinotes-test - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/arcmt-test - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/c-index-test - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-check - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-diff - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-extdef-mapping - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-format - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/tools/clang-format/fuzzer - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/tools/clang-fuzzer - - `6` - - `4` - - `2` - - :part:`66%` - * - clang/tools/clang-fuzzer/fuzzer-initialize - - `2` - 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* - clang/unittests/Driver - - `5` - - `1` - - `4` - - :part:`20%` - * - clang/unittests/Format - - `24` - - `24` - - `0` - - :good:`100%` - * - clang/unittests/Frontend - - `11` - - `7` - - `4` - - :part:`63%` - * - clang/unittests/Index - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/unittests/Interpreter - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/unittests/Interpreter/ExceptionTests - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/unittests/Introspection - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/unittests/Lex - - `8` - - `4` - - `4` - - :part:`50%` - * - clang/unittests/libclang - - `2` - - `0` - - `2` - - :none:`0%` - * - clang/unittests/libclang/CrashTests - - `1` - - `1` - - `0` - - :good:`100%` - * - clang/unittests/Rename - - `6` - - `0` - - `6` - - :none:`0%` - * - clang/unittests/Rewrite - - `2` - - `1` - - `1` - - :part:`50%` - * - clang/unittests/Sema - - `3` - - `2` - - `1` - - :part:`66%` - * - clang/unittests/Serialization - - `2` - - `2` - - `0` - - :good:`100%` - * - clang/unittests/StaticAnalyzer - - `16` - - `7` - - `9` - - :part:`43%` - * - clang/unittests/Tooling - - `30` - - `10` - - `20` - - :part:`33%` - * - clang/unittests/Tooling/RecursiveASTVisitorTests - - `30` - - `12` - - `18` - - :part:`40%` - * - clang/unittests/Tooling/Syntax - - `7` - - `3` - - `4` - - :part:`42%` - * - clang/unittests/Tooling/Syntax/Pseudo - - `4` - - `4` - - `0` - - :good:`100%` - * - clang/utils/perf-training/cxx - - `1` - - `0` - - `1` - - :none:`0%` - * - clang/utils/TableGen - - `22` - - `3` - - `19` - - :part:`13%` - * - clang-tools-extra/clang-apply-replacements/include/clang-apply-replacements/Tooling - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-apply-replacements/lib/Tooling - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-apply-replacements/tool - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clang-change-namespace - - `2` - - `0` - - `2` - - :none:`0%` - * - clang-tools-extra/clang-change-namespace/tool - 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clang-tools-extra/clangd/unittests/decision_forest_model - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/unittests/remote - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/unittests/support - - `11` - - `11` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/unittests/tweaks - - `20` - - `19` - - `1` - - :part:`95%` - * - clang-tools-extra/clangd/unittests/xpc - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/xpc - - `3` - - `3` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/xpc/framework - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/clangd/xpc/test-client - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/modularize - - `9` - - `1` - - `8` - - :part:`11%` - * - clang-tools-extra/pp-trace - - `3` - - `1` - - `2` - - :part:`33%` - * - clang-tools-extra/tool-template - - `1` - - `1` - - `0` - - :good:`100%` - * - clang-tools-extra/unittests/clang-apply-replacements - - `1` - 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llvm/tools/bugpoint - - `12` - - `1` - - `11` - - :part:`8%` - * - llvm/tools/bugpoint-passes - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/dsymutil - - `18` - - `16` - - `2` - - :part:`88%` - * - llvm/tools/gold - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llc - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/lli - - `4` - - `3` - - `1` - - :part:`75%` - * - llvm/tools/lli/ChildTarget - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-ar - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-as - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-as-fuzzer - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-bcanalyzer - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-c-test - - `2` - - `0` - - `2` - - :none:`0%` - * - llvm/tools/llvm-cat - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-cfi-verify - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-cfi-verify/lib - - `4` - - `1` - - `3` - - :part:`25%` - * - llvm/tools/llvm-config - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-cov - - `23` - - `12` - - `11` - - :part:`52%` - * - llvm/tools/llvm-cvtres - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-cxxdump - - `4` - - `1` - - `3` - - :part:`25%` - * - llvm/tools/llvm-cxxfilt - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-cxxmap - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-debuginfod-find - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-diff - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-diff/lib - - `6` - - `0` - - `6` - - :none:`0%` - * - llvm/tools/llvm-dis - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-dis-fuzzer - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-dlang-demangle-fuzzer - - `2` - - `2` - - `0` - - :good:`100%` - * - llvm/tools/llvm-dwarfdump - - `4` - - `3` - - `1` - - :part:`75%` - * - llvm/tools/llvm-dwarfdump/fuzzer - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-dwp - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-exegesis - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-exegesis/lib - - `44` - - `33` - - `11` - - :part:`75%` - * - llvm/tools/llvm-exegesis/lib/AArch64 - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-exegesis/lib/Mips - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-exegesis/lib/PowerPC - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-exegesis/lib/X86 - - `3` - - `2` - - `1` - - :part:`66%` - * - llvm/tools/llvm-extract - - `1` - - `0` - - `1` - - :none:`0%` - * - llvm/tools/llvm-gsymutil - - `1` - - `1` - - `0` - - :good:`100%` - * - llvm/tools/llvm-ifs - - `3` - - `2` - - `1` - - :part:`66%` - * - llvm/tools/llvm-isel-fuzzer - - `2` - - `1` - - `1` - - :part:`50%` - * - llvm/tools/llvm-itanium-demangle-fuzzer - - `2` - - `1` - - `1` - - :part:`50%` - * - llvm/tools/llvm-jitlink - - `4` - - `2` - - `2` - - :part:`50%` - * - llvm/tools/llvm-jitlink/llvm-jitlink-executor - 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mlir/lib/Pass - - `8` - - `6` - - `2` - - :part:`75%` - * - mlir/lib/Reducer - - `4` - - `4` - - `0` - - :good:`100%` - * - mlir/lib/Rewrite - - `4` - - `3` - - `1` - - :part:`75%` - * - mlir/lib/Support - - `8` - - `8` - - `0` - - :good:`100%` - * - mlir/lib/TableGen - - `18` - - `18` - - `0` - - :good:`100%` - * - mlir/lib/Target/Cpp - - `2` - - `2` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR - - `7` - - `6` - - `1` - - :part:`85%` - * - mlir/lib/Target/LLVMIR/Dialect/AMX - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/ArmNeon - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/ArmSVE - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/LLVMIR - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/NVVM - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/OpenACC - - `1` - - `0` - - `1` - - :none:`0%` - * - mlir/lib/Target/LLVMIR/Dialect/OpenMP - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/ROCDL - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/LLVMIR/Dialect/X86Vector - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Target/SPIRV - - `2` - - `2` - - `0` - - :good:`100%` - * - mlir/lib/Target/SPIRV/Deserialization - - `4` - - `3` - - `1` - - :part:`75%` - * - mlir/lib/Target/SPIRV/Serialization - - `4` - - `3` - - `1` - - :part:`75%` - * - mlir/lib/Tools/mlir-lsp-server - - `5` - - `4` - - `1` - - :part:`80%` - * - mlir/lib/Tools/mlir-lsp-server/lsp - - `6` - - `4` - - `2` - - :part:`66%` - * - mlir/lib/Tools/mlir-reduce - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/lib/Tools/PDLL/AST - - `6` - - `5` - - `1` - - :part:`83%` - * - mlir/lib/Tools/PDLL/CodeGen - - `2` - - `1` - - `1` - - :part:`50%` - * - mlir/lib/Tools/PDLL/ODS - - `3` - - `3` - - `0` - - :good:`100%` - * - mlir/lib/Tools/PDLL/Parser - - `3` - - `1` - - `2` - - :part:`33%` - * - mlir/lib/Transforms - - `13` - - `11` - - `2` - - :part:`84%` - * - mlir/lib/Transforms/Utils - - `6` - - `6` - - `0` - - :good:`100%` - * - mlir/lib/Translation - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-cpu-runner - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-linalg-ods-gen - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-lsp-server - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-opt - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-pdll - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-reduce - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-shlib - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-spirv-cpu-runner - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-tblgen - - `29` - - `28` - - `1` - - :part:`96%` - * - mlir/tools/mlir-translate - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/tools/mlir-vulkan-runner - - `4` - - `4` - - `0` - - :good:`100%` - * - mlir/unittests/Analysis/Presburger - - `8` - - `8` - - `0` - - :good:`100%` - * - mlir/unittests/Conversion/PDLToPDLInterp - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/Affine/Analysis - - `3` - - `3` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/Quant - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/SparseTensor - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/SPIRV - - `2` - - `2` - - `0` - - :good:`100%` - * - mlir/unittests/Dialect/Utils - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/ExecutionEngine - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Interfaces - - `3` - - `3` - - `0` - - :good:`100%` - * - mlir/unittests/IR - - `7` - - `7` - - `0` - - :good:`100%` - * - mlir/unittests/Pass - - `3` - - `3` - - `0` - - :good:`100%` - * - mlir/unittests/Rewrite - - `1` - - `1` - - `0` - - :good:`100%` - * - mlir/unittests/Support - - `5` - - `4` - - `1` - - :part:`80%` - * - mlir/unittests/TableGen - - `5` - - `3` - - `2` - - :part:`60%` - * - mlir/unittests/Transforms - - `2` - - `2` - - `0` - - :good:`100%` - * - openmp/libompd/src - - `9` - - `9` - - `0` - - :good:`100%` - * - openmp/libomptarget/DeviceRTL/include - - `8` - - `8` - - `0` - - :good:`100%` - * - openmp/libomptarget/DeviceRTL/src - - `12` - - `9` - - `3` - - :part:`75%` - * - openmp/libomptarget/include - - `9` - - `8` - - `1` - - :part:`88%` - * - openmp/libomptarget/plugins/amdgpu/dynamic_hsa - - `3` - - `2` - - `1` - - :part:`66%` - * - openmp/libomptarget/plugins/amdgpu/impl - - `13` - - `10` - - `3` - - :part:`76%` - * - openmp/libomptarget/plugins/amdgpu/src - - `2` - - `1` - - `1` - - :part:`50%` - * - openmp/libomptarget/plugins/common/elf_common - - `2` - - `2` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/common/MemoryManager - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/cuda/dynamic_cuda - - `2` - - `2` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/cuda/src - - `1` - - `0` - - `1` - - :none:`0%` - * - openmp/libomptarget/plugins/generic-elf-64bit/src - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/remote/include - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/remote/lib - - `1` - - `0` - - `1` - - :none:`0%` - * - openmp/libomptarget/plugins/remote/server - - `3` - - `3` - - `0` - - :good:`100%` - * - openmp/libomptarget/plugins/remote/src - - `3` - - `2` - - `1` - - :part:`66%` - * - openmp/libomptarget/plugins/ve/src - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/libomptarget/src - - `7` - - `6` - - `1` - - :part:`85%` - * - openmp/libomptarget/tools/deviceinfo - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/runtime/doc/doxygen - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/runtime/src - - `75` - - `65` - - `10` - - :part:`86%` - * - openmp/runtime/src/thirdparty/ittnotify - - `6` - - `5` - - `1` - - :part:`83%` - * - openmp/runtime/src/thirdparty/ittnotify/legacy - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/archer - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/archer/tests/ompt - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/multiplex - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/multiplex/tests - - `1` - - `1` - - `0` - - :good:`100%` - * - openmp/tools/multiplex/tests/custom_data_storage - - `2` - - `1` - - `1` - - :part:`50%` - * - openmp/tools/multiplex/tests/print - - `2` - - `2` - - `0` - - :good:`100%` - * - polly/include/polly - - `25` - - `25` - - `0` - - :good:`100%` - * - polly/include/polly/CodeGen - - `14` - - `14` - - `0` - - :good:`100%` - * - polly/include/polly/Support - - `12` - - `12` - - `0` - - :good:`100%` - * - polly/lib/Analysis - - `9` - - `9` - - `0` - - :good:`100%` - * - polly/lib/CodeGen - - `15` - - `15` - - `0` - - :good:`100%` - * - polly/lib/Exchange - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/lib/External/isl - - `68` - - `1` - - `67` - - :part:`1%` - * - polly/lib/External/isl/imath - - `6` - - `1` - - `5` - - :part:`16%` - * - polly/lib/External/isl/imath_wrap - - `4` - - `0` - - `4` - - :none:`0%` - * - polly/lib/External/isl/include/isl - - `59` - - `9` - - `50` - - :part:`15%` - * - polly/lib/External/isl/interface - - `8` - - `1` - - `7` - - :part:`12%` - * - polly/lib/External/pet/include - - `1` - - `0` - - `1` - - :none:`0%` - * - polly/lib/External/ppcg - - `17` - - `0` - - `17` - - :none:`0%` - * - polly/lib/Plugin - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/lib/Support - - `11` - - `11` - - `0` - - :good:`100%` - * - polly/lib/Transform - - `15` - - `15` - - `0` - - :good:`100%` - * - polly/tools/GPURuntime - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/DeLICM - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/Flatten - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/Isl - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/ScheduleOptimizer - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/ScopPassManager - - `1` - - `1` - - `0` - - :good:`100%` - * - polly/unittests/Support - - `1` - - `1` - - `0` - - :good:`100%` - * - pstl/include/pstl/internal - - `23` - - `16` - - `7` - - :part:`69%` - * - pstl/include/pstl/internal/omp - - `11` - - `8` - - `3` - - :part:`72%` - * - third-party/benchmark/cmake - - `5` - - `1` - - `4` - - :part:`20%` - * - third-party/benchmark/include/benchmark - - `1` - - `0` - - `1` - - :none:`0%` - * - third-party/benchmark/src - - `21` - - `21` - - `0` - - :good:`100%` - * - utils/bazel/llvm-project-overlay/clang/include/clang/Config - - `1` - - `1` - - `0` - - :good:`100%` - * - utils/bazel/llvm-project-overlay/llvm/include/llvm/Config - - `2` - - `1` - - `1` - - :part:`50%` - * - Total - - :total:`16432` - - :total:`8857` - - :total:`7575` - - :total:`53%` diff --git a/clang/docs/ClangLinkerWrapper.rst b/clang/docs/ClangLinkerWrapper.rst index 99352863b4773a38d33ce168a297fe1f2f4199b9..e69cdba434c93cdd4f94e592f50c0a21aa7e685f 100644 --- a/clang/docs/ClangLinkerWrapper.rst +++ b/clang/docs/ClangLinkerWrapper.rst @@ -30,14 +30,11 @@ only for the linker wrapper will be forwarded to the wrapped linker job. USAGE: clang-linker-wrapper [options] -- OPTIONS: - --bitcode-library=--= - Extra bitcode library to link --cuda-path= Set the system CUDA path --device-debug Use debugging --device-linker= or = Arguments to pass to the device linker invocation --dry-run Print program arguments without running - --embed-bitcode Embed linked bitcode in the module --help-hidden Display all available options --help Display available options (--help-hidden for more) --host-triple= Triple to use for the host compilation diff --git a/clang/docs/RealtimeSanitizer.rst b/clang/docs/RealtimeSanitizer.rst index 41b8bbb33baf1442f9b6b52a85c769bb44ab1c2b..e5f5abfcd9b47e6dba9699524e72712d74cf6570 100644 --- a/clang/docs/RealtimeSanitizer.rst +++ b/clang/docs/RealtimeSanitizer.rst @@ -11,11 +11,16 @@ RealtimeSanitizer (a.k.a. RTSan) is a real-time safety testing tool for C and C+ projects. RTSan can be used to detect real-time violations, i.e. calls to methods that are not safe for use in functions with deterministic run time requirements. RTSan considers any function marked with the ``[[clang::nonblocking]]`` attribute -to be a real-time function. If RTSan detects a call to ``malloc``, ``free``, -``pthread_mutex_lock``, or anything else that could have a non-deterministic -execution time in a function marked ``[[clang::nonblocking]]`` +to be a real-time function. At run-time, if RTSan detects a call to ``malloc``, +``free``, ``pthread_mutex_lock``, or anything else that could have a +non-deterministic execution time in a function marked ``[[clang::nonblocking]]`` RTSan raises an error. +RTSan performs its analysis at run-time but shares the ``[[clang::nonblocking]]`` +attribute with the :doc:`FunctionEffectAnalysis` system, which operates at +compile-time to detect potential real-time safety violations. For comprehensive +detection of real-time safety issues, it is recommended to use both systems together. + The runtime slowdown introduced by RealtimeSanitizer is negligible. How to build diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index a39ffc8366dda41fd501bfcbd4133443ca9ac642..145786bcc59b45d71f9e0da535234327e738a2cd 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -140,7 +140,7 @@ C++ Specific Potentially Breaking Changes unsigned operator""_udl_name(unsigned long long); - Clang will now produce an error diagnostic when [[clang::lifetimebound]] is - applied on a parameter of a function that returns void. This was previously + applied on a parameter of a function that returns void. This was previously ignored and had no effect. (#GH107556) .. code-block:: c++ @@ -469,7 +469,8 @@ Bug Fixes in This Version - Fixed a crash using ``__array_rank`` on 64-bit targets. (#GH113044). - The warning emitted for an unsupported register variable type now points to the unsupported type instead of the ``register`` keyword (#GH109776). -- Fixed a crash when emit ctor for global variant with flexible array init (#GH113187). +- Fixed a crash when emit ctor for global variant with flexible array init (#GH113187). +- Fixed a crash when GNU statement expression contains invalid statement (#GH113468). Bug Fixes to Compiler Builtins ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -573,6 +574,8 @@ Bug Fixes to C++ Support (#GH95854). - Fixed an assertion failure when evaluating an invalid expression in an array initializer. (#GH112140) - Fixed an assertion failure in range calculations for conditional throw expressions. (#GH111854) +- Clang now correctly ignores previous partial specializations of member templates explicitly specialized for + an implicitly instantiated class template specialization. (#GH51051) Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -658,6 +661,7 @@ X86 Support - Supported intrinsics for ``MOVRS AND AVX10.2``. * Supported intrinsics of ``_mm(256|512)_(mask(z))_loadrs_epi(8|16|32|64)``. +- Support ISA of ``AMX-FP8``. Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ @@ -742,6 +746,8 @@ AST Matchers - Fixed a crash when traverse lambda expr with invalid captures. (#GH106444) +- Fixed ``isInstantiated`` and ``isInTemplateInstantiation`` to also match for variable templates. (#GH110666) + - Ensure ``hasName`` matches template specializations across inline namespaces, making `matchesNodeFullSlow` and `matchesNodeFullFast` consistent. diff --git a/clang/docs/index.rst b/clang/docs/index.rst index 1096432813fac523d26d9bdbbb8fd1a5ebebebbc..66a4540a0bcacf44eb839ee7e770fb240cd6c2c5 100644 --- a/clang/docs/index.rst +++ b/clang/docs/index.rst @@ -93,7 +93,6 @@ Using Clang Tools ClangCheck ClangFormat ClangFormatStyleOptions - ClangFormattedStatus ClangLinkerWrapper ClangNVLinkWrapper ClangOffloadBundler diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt deleted file mode 100644 index 67ff085144f4dec4e685299c8d9c1a95452688f4..0000000000000000000000000000000000000000 --- a/clang/docs/tools/clang-formatted-files.txt +++ /dev/null @@ -1,8827 +0,0 @@ -bolt/include/bolt/Core/BinaryData.h -bolt/include/bolt/Core/BinaryEmitter.h -bolt/include/bolt/Core/BinaryLoop.h -bolt/include/bolt/Core/BinarySection.h -bolt/include/bolt/Core/DebugData.h -bolt/include/bolt/Core/Exceptions.h -bolt/include/bolt/Core/JumpTable.h -bolt/include/bolt/Core/MCPlus.h -bolt/include/bolt/Core/MCPlusBuilder.h -bolt/include/bolt/Core/ParallelUtilities.h -bolt/include/bolt/Passes/ADRRelaxationPass.h -bolt/include/bolt/Passes/Aligner.h -bolt/include/bolt/Passes/AllocCombiner.h -bolt/include/bolt/Passes/AsmDump.h -bolt/include/bolt/Passes/BinaryFunctionCallGraph.h -bolt/include/bolt/Passes/BinaryPasses.h -bolt/include/bolt/Passes/CacheMetrics.h -bolt/include/bolt/Passes/CallGraph.h -bolt/include/bolt/Passes/CallGraphWalker.h -bolt/include/bolt/Passes/DataflowAnalysis.h -bolt/include/bolt/Passes/DataflowInfoManager.h -bolt/include/bolt/Passes/DominatorAnalysis.h -bolt/include/bolt/Passes/FrameAnalysis.h -bolt/include/bolt/Passes/FrameOptimizer.h -bolt/include/bolt/Passes/HFSort.h -bolt/include/bolt/Passes/IdenticalCodeFolding.h -bolt/include/bolt/Passes/IndirectCallPromotion.h -bolt/include/bolt/Passes/Inliner.h -bolt/include/bolt/Passes/Instrumentation.h -bolt/include/bolt/Passes/InstrumentationSummary.h -bolt/include/bolt/Passes/JTFootprintReduction.h -bolt/include/bolt/Passes/LivenessAnalysis.h -bolt/include/bolt/Passes/LongJmp.h -bolt/include/bolt/Passes/LoopInversionPass.h -bolt/include/bolt/Passes/MCF.h -bolt/include/bolt/Passes/PatchEntries.h -bolt/include/bolt/Passes/PLTCall.h -bolt/include/bolt/Passes/ReachingDefOrUse.h -bolt/include/bolt/Passes/ReachingInsns.h -bolt/include/bolt/Passes/RegAnalysis.h -bolt/include/bolt/Passes/RegReAssign.h -bolt/include/bolt/Passes/ReorderAlgorithm.h -bolt/include/bolt/Passes/ReorderData.h -bolt/include/bolt/Passes/ReorderFunctions.h -bolt/include/bolt/Passes/ReorderUtils.h -bolt/include/bolt/Passes/RetpolineInsertion.h -bolt/include/bolt/Passes/ShrinkWrapping.h -bolt/include/bolt/Passes/SplitFunctions.h -bolt/include/bolt/Passes/StackAllocationAnalysis.h -bolt/include/bolt/Passes/StackAvailableExpressions.h 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-bolt/include/bolt/RuntimeLibs/RuntimeLibrary.h -bolt/include/bolt/Utils/CommandLineOpts.h -bolt/include/bolt/Utils/NameResolver.h -bolt/include/bolt/Utils/NameShortener.h -bolt/include/bolt/Utils/Utils.h -bolt/lib/Core/BinaryBasicBlock.cpp -bolt/lib/Core/BinarySection.cpp -bolt/lib/Core/DebugData.cpp -bolt/lib/Core/JumpTable.cpp -bolt/lib/Core/MCPlusBuilder.cpp -bolt/lib/Passes/ADRRelaxationPass.cpp -bolt/lib/Passes/AllocCombiner.cpp -bolt/lib/Passes/AsmDump.cpp -bolt/lib/Passes/BinaryFunctionCallGraph.cpp -bolt/lib/Passes/CacheMetrics.cpp -bolt/lib/Passes/CallGraphWalker.cpp -bolt/lib/Passes/DataflowAnalysis.cpp -bolt/lib/Passes/DataflowInfoManager.cpp -bolt/lib/Passes/HFSort.cpp -bolt/lib/Passes/IndirectCallPromotion.cpp -bolt/lib/Passes/Instrumentation.cpp -bolt/lib/Passes/JTFootprintReduction.cpp -bolt/lib/Passes/LivenessAnalysis.cpp -bolt/lib/Passes/LoopInversionPass.cpp -bolt/lib/Passes/PettisAndHansen.cpp -bolt/lib/Passes/StackAllocationAnalysis.cpp -bolt/lib/Passes/StackPointerTracking.cpp -bolt/lib/Passes/StackReachingUses.cpp -bolt/lib/Passes/TailDuplication.cpp -bolt/lib/Passes/ThreeWayBranch.cpp -bolt/lib/Passes/ValidateInternalCalls.cpp -bolt/lib/Profile/BoltAddressTranslation.cpp -bolt/lib/Profile/Heatmap.cpp -bolt/lib/Profile/ProfileReaderBase.cpp -bolt/lib/RuntimeLibs/HugifyRuntimeLibrary.cpp -bolt/lib/RuntimeLibs/InstrumentationRuntimeLibrary.cpp -bolt/lib/RuntimeLibs/RuntimeLibrary.cpp -bolt/lib/Utils/Utils.cpp -bolt/tools/heatmap/heatmap.cpp -bolt/tools/llvm-bolt-fuzzer/llvm-bolt-fuzzer.cpp -bolt/unittests/Core/MCPlusBuilder.cpp -clang/bindings/python/tests/cindex/INPUTS/header1.h -clang/bindings/python/tests/cindex/INPUTS/header2.h -clang/bindings/python/tests/cindex/INPUTS/header3.h -clang/examples/Attribute/Attribute.cpp -clang/examples/CallSuperAttribute/CallSuperAttrInfo.cpp -clang/examples/PluginsOrder/PluginsOrder.cpp -clang/include/clang/Analysis/BodyFarm.h -clang/include/clang/Analysis/IssueHash.h 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-clang/include/clang/Analysis/FlowSensitive/NoopLattice.h -clang/include/clang/Analysis/FlowSensitive/Solver.h -clang/include/clang/Analysis/FlowSensitive/StorageLocation.h -clang/include/clang/Analysis/FlowSensitive/Transfer.h -clang/include/clang/Analysis/FlowSensitive/TypeErasedDataflowAnalysis.h -clang/include/clang/Analysis/FlowSensitive/Value.h -clang/include/clang/Analysis/FlowSensitive/WatchedLiteralsSolver.h -clang/include/clang/APINotes/APINotesYAMLCompiler.h -clang/include/clang/APINotes/Types.h -clang/include/clang/AST/AST.h -clang/include/clang/AST/ASTContextAllocate.h -clang/include/clang/AST/ASTDumper.h -clang/include/clang/AST/ASTFwd.h -clang/include/clang/AST/ASTImporterLookupTable.h -clang/include/clang/AST/ASTImporterSharedState.h -clang/include/clang/AST/AttrVisitor.h -clang/include/clang/AST/Availability.h -clang/include/clang/AST/ComputeDependence.h -clang/include/clang/AST/CurrentSourceLocExprScope.h -clang/include/clang/AST/DataCollection.h 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-polly/include/polly/Support/LinkGPURuntime.h -polly/include/polly/Support/SCEVAffinator.h -polly/include/polly/Support/SCEVValidator.h -polly/include/polly/Support/ScopHelper.h -polly/include/polly/Support/ScopLocation.h -polly/include/polly/Support/VirtualInstruction.h -polly/lib/Analysis/DependenceInfo.cpp -polly/lib/Analysis/PolyhedralInfo.cpp -polly/lib/Analysis/PruneUnprofitable.cpp -polly/lib/Analysis/ScopBuilder.cpp -polly/lib/Analysis/ScopDetection.cpp -polly/lib/Analysis/ScopDetectionDiagnostic.cpp -polly/lib/Analysis/ScopGraphPrinter.cpp -polly/lib/Analysis/ScopInfo.cpp -polly/lib/Analysis/ScopPass.cpp -polly/lib/CodeGen/BlockGenerators.cpp -polly/lib/CodeGen/CodegenCleanup.cpp -polly/lib/CodeGen/CodeGeneration.cpp -polly/lib/CodeGen/IRBuilder.cpp -polly/lib/CodeGen/IslAst.cpp -polly/lib/CodeGen/IslExprBuilder.cpp -polly/lib/CodeGen/IslNodeBuilder.cpp -polly/lib/CodeGen/LoopGenerators.cpp -polly/lib/CodeGen/LoopGeneratorsGOMP.cpp -polly/lib/CodeGen/LoopGeneratorsKMP.cpp -polly/lib/CodeGen/ManagedMemoryRewrite.cpp -polly/lib/CodeGen/PerfMonitor.cpp -polly/lib/CodeGen/PPCGCodeGeneration.cpp -polly/lib/CodeGen/RuntimeDebugBuilder.cpp -polly/lib/CodeGen/Utils.cpp -polly/lib/Exchange/JSONExporter.cpp -polly/lib/External/isl/isl_local_private.h -polly/lib/External/isl/imath/iprime.h -polly/lib/External/isl/include/isl/id_type.h -polly/lib/External/isl/include/isl/isl-noexceptions.h -polly/lib/External/isl/include/isl/map_type.h -polly/lib/External/isl/include/isl/printer_type.h -polly/lib/External/isl/include/isl/set_type.h -polly/lib/External/isl/include/isl/union_map_type.h -polly/lib/External/isl/include/isl/union_set_type.h -polly/lib/External/isl/include/isl/val_type.h -polly/lib/External/isl/include/isl/version.h -polly/lib/External/isl/interface/extract_interface.h -polly/lib/Plugin/Polly.cpp -polly/lib/Support/DumpFunctionPass.cpp -polly/lib/Support/DumpModulePass.cpp -polly/lib/Support/GICHelper.cpp -polly/lib/Support/ISLTools.cpp -polly/lib/Support/Mainpage.h -polly/lib/Support/RegisterPasses.cpp -polly/lib/Support/SCEVAffinator.cpp -polly/lib/Support/SCEVValidator.cpp -polly/lib/Support/ScopHelper.cpp -polly/lib/Support/ScopLocation.cpp -polly/lib/Support/VirtualInstruction.cpp -polly/lib/Transform/Canonicalization.cpp -polly/lib/Transform/CodePreparation.cpp -polly/lib/Transform/DeadCodeElimination.cpp -polly/lib/Transform/DeLICM.cpp -polly/lib/Transform/FlattenAlgo.cpp -polly/lib/Transform/FlattenSchedule.cpp -polly/lib/Transform/ForwardOpTree.cpp -polly/lib/Transform/ManualOptimizer.cpp -polly/lib/Transform/MatmulOptimizer.cpp -polly/lib/Transform/MaximalStaticExpansion.cpp -polly/lib/Transform/ScheduleOptimizer.cpp -polly/lib/Transform/ScheduleTreeTransform.cpp -polly/lib/Transform/ScopInliner.cpp -polly/lib/Transform/Simplify.cpp -polly/lib/Transform/ZoneAlgo.cpp -polly/tools/GPURuntime/GPUJIT.h -polly/unittests/DeLICM/DeLICMTest.cpp -polly/unittests/Flatten/FlattenTest.cpp -polly/unittests/Isl/IslTest.cpp -polly/unittests/ScheduleOptimizer/ScheduleTreeTransformTest.cpp -polly/unittests/ScopPassManager/PassManagerTest.cpp -polly/unittests/Support/ISLTools.cpp -pstl/include/pstl/internal/algorithm_fwd.h -pstl/include/pstl/internal/execution_defs.h -pstl/include/pstl/internal/execution_impl.h -pstl/include/pstl/internal/glue_algorithm_defs.h -pstl/include/pstl/internal/glue_algorithm_impl.h -pstl/include/pstl/internal/glue_execution_defs.h -pstl/include/pstl/internal/glue_memory_defs.h -pstl/include/pstl/internal/glue_memory_impl.h -pstl/include/pstl/internal/glue_numeric_defs.h -pstl/include/pstl/internal/glue_numeric_impl.h -pstl/include/pstl/internal/numeric_fwd.h -pstl/include/pstl/internal/parallel_backend.h -pstl/include/pstl/internal/parallel_backend_omp.h -pstl/include/pstl/internal/parallel_backend_serial.h -pstl/include/pstl/internal/parallel_backend_utils.h -pstl/include/pstl/internal/parallel_impl.h -pstl/include/pstl/internal/omp/parallel_for.h -pstl/include/pstl/internal/omp/parallel_for_each.h -pstl/include/pstl/internal/omp/parallel_invoke.h -pstl/include/pstl/internal/omp/parallel_reduce.h -pstl/include/pstl/internal/omp/parallel_scan.h -pstl/include/pstl/internal/omp/parallel_stable_partial_sort.h -pstl/include/pstl/internal/omp/parallel_transform_scan.h -pstl/include/pstl/internal/omp/util.h -third-party/benchmark/cmake/thread_safety_attributes.cpp -third-party/benchmark/src/arraysize.h -third-party/benchmark/src/benchmark_api_internal.h -third-party/benchmark/src/benchmark_register.h -third-party/benchmark/src/benchmark_runner.h -third-party/benchmark/src/check.h -third-party/benchmark/src/colorprint.h -third-party/benchmark/src/commandlineflags.h -third-party/benchmark/src/complexity.h -third-party/benchmark/src/counter.h -third-party/benchmark/src/cycleclock.h -third-party/benchmark/src/internal_macros.h -third-party/benchmark/src/log.h -third-party/benchmark/src/mutex.h -third-party/benchmark/src/perf_counters.h -third-party/benchmark/src/re.h -third-party/benchmark/src/sleep.h -third-party/benchmark/src/statistics.h -third-party/benchmark/src/string_util.h -third-party/benchmark/src/thread_manager.h -third-party/benchmark/src/thread_timer.h -third-party/benchmark/src/timers.h -utils/bazel/llvm-project-overlay/clang/include/clang/Config/config.h -utils/bazel/llvm-project-overlay/llvm/include/llvm/Config/config.h diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h index d514c8f930375657b7af1de9de2bba9a9df3c485..93b697ee60795d8dc38fcc9f407c046a2810cadd 100644 --- a/clang/include/clang/AST/ASTContext.h +++ b/clang/include/clang/AST/ASTContext.h @@ -260,7 +260,7 @@ class ASTContext : public RefCountedBase { mutable llvm::ContextualFoldingSet DependentTemplateSpecializationTypes; - llvm::FoldingSet PackExpansionTypes; + mutable llvm::FoldingSet PackExpansionTypes; mutable llvm::FoldingSet ObjCObjectTypes; mutable llvm::FoldingSet ObjCObjectPointerTypes; mutable llvm::FoldingSet @@ -1803,13 +1803,7 @@ public: ElaboratedTypeKeyword Keyword, NestedNameSpecifier *NNS, const IdentifierInfo *Name, ArrayRef Args) const; - TemplateArgument getInjectedTemplateArg(NamedDecl *ParamDecl); - - /// Get a template argument list with one argument per template parameter - /// in a template parameter list, such as for the injected class name of - /// a class template. - void getInjectedTemplateArgs(const TemplateParameterList *Params, - SmallVectorImpl &Args); + TemplateArgument getInjectedTemplateArg(NamedDecl *ParamDecl) const; /// Form a pack expansion type with the given pattern. /// \param NumExpansions The number of expansions for the pack, if known. @@ -1820,7 +1814,7 @@ public: /// if this is the canonical type of another pack expansion type. QualType getPackExpansionType(QualType Pattern, std::optional NumExpansions, - bool ExpectPackInType = true); + bool ExpectPackInType = true) const; QualType getObjCInterfaceType(const ObjCInterfaceDecl *Decl, ObjCInterfaceDecl *PrevDecl = nullptr) const; diff --git a/clang/include/clang/AST/DeclTemplate.h b/clang/include/clang/AST/DeclTemplate.h index 0f0c0bf6e4ef4f5c2adbc88c4cca201ef7c0efd5..a572e3380f165501c178da42e521ed7ddfaaecd9 100644 --- a/clang/include/clang/AST/DeclTemplate.h +++ b/clang/include/clang/AST/DeclTemplate.h @@ -71,6 +71,9 @@ NamedDecl *getAsNamedDecl(TemplateParameter P); class TemplateParameterList final : private llvm::TrailingObjects { + /// The template argument list of the template parameter list. + TemplateArgument *InjectedArgs = nullptr; + /// The location of the 'template' keyword. SourceLocation TemplateLoc; @@ -196,6 +199,9 @@ public: bool hasAssociatedConstraints() const; + /// Get the template argument list of the template parameter list. + ArrayRef getInjectedTemplateArgs(const ASTContext &Context); + SourceLocation getTemplateLoc() const { return TemplateLoc; } SourceLocation getLAngleLoc() const { return LAngleLoc; } SourceLocation getRAngleLoc() const { return RAngleLoc; } @@ -793,15 +799,6 @@ protected: /// The first value in the array is the number of specializations/partial /// specializations that follow. GlobalDeclID *LazySpecializations = nullptr; - - /// The set of "injected" template arguments used within this - /// template. - /// - /// This pointer refers to the template arguments (there are as - /// many template arguments as template parameters) for the - /// template, and is allocated lazily, since most templates do not - /// require the use of this information. - TemplateArgument *InjectedArgs = nullptr; }; /// Pointer to the common data shared by all declarations of this @@ -927,7 +924,10 @@ public: /// Although the C++ standard has no notion of the "injected" template /// arguments for a template, the notion is convenient when /// we need to perform substitutions inside the definition of a template. - ArrayRef getInjectedTemplateArgs(); + ArrayRef + getInjectedTemplateArgs(const ASTContext &Context) const { + return getTemplateParameters()->getInjectedTemplateArgs(Context); + } using redecl_range = redeclarable_base::redecl_range; using redecl_iterator = redeclarable_base::redecl_iterator; @@ -2087,10 +2087,6 @@ class ClassTemplatePartialSpecializationDecl /// The list of template parameters TemplateParameterList *TemplateParams = nullptr; - /// The set of "injected" template arguments used within this - /// partial specialization. - TemplateArgument *InjectedArgs = nullptr; - /// The class template partial specialization from which this /// class template partial specialization was instantiated. /// @@ -2136,9 +2132,11 @@ public: return TemplateParams; } - /// Retrieve the template arguments list of the template parameter list - /// of this template. - ArrayRef getInjectedTemplateArgs(); + /// Get the template argument list of the template parameter list. + ArrayRef + getInjectedTemplateArgs(const ASTContext &Context) const { + return getTemplateParameters()->getInjectedTemplateArgs(Context); + } /// \brief All associated constraints of this partial specialization, /// including the requires clause and any constraints derived from @@ -2864,10 +2862,6 @@ class VarTemplatePartialSpecializationDecl /// The list of template parameters TemplateParameterList *TemplateParams = nullptr; - /// The set of "injected" template arguments used within this - /// partial specialization. - TemplateArgument *InjectedArgs = nullptr; - /// The variable template partial specialization from which this /// variable template partial specialization was instantiated. /// @@ -2914,9 +2908,11 @@ public: return TemplateParams; } - /// Retrieve the template arguments list of the template parameter list - /// of this template. - ArrayRef getInjectedTemplateArgs(); + /// Get the template argument list of the template parameter list. + ArrayRef + getInjectedTemplateArgs(const ASTContext &Context) const { + return getTemplateParameters()->getInjectedTemplateArgs(Context); + } /// \brief All associated constraints of this partial specialization, /// including the requires clause and any constraints derived from diff --git a/clang/include/clang/ASTMatchers/ASTMatchers.h b/clang/include/clang/ASTMatchers/ASTMatchers.h index 54e484d41fb1c3eb6b5cb88001a47a6a4cf3cce6..c77140842d7a6e14ad2615149aa9e32c8236dc5a 100644 --- a/clang/include/clang/ASTMatchers/ASTMatchers.h +++ b/clang/include/clang/ASTMatchers/ASTMatchers.h @@ -6750,7 +6750,8 @@ AST_POLYMORPHIC_MATCHER(isTemplateInstantiation, /// matches 'A(int) {...};' and 'A(unsigned) {...}'. AST_MATCHER_FUNCTION(internal::Matcher, isInstantiated) { auto IsInstantiation = decl(anyOf(cxxRecordDecl(isTemplateInstantiation()), - functionDecl(isTemplateInstantiation()))); + functionDecl(isTemplateInstantiation()), + varDecl(isTemplateInstantiation()))); return decl(anyOf(IsInstantiation, hasAncestor(IsInstantiation))); } @@ -6769,9 +6770,9 @@ AST_MATCHER_FUNCTION(internal::Matcher, isInstantiated) { /// will NOT match j += 42; as it's shared between the template definition and /// instantiation. AST_MATCHER_FUNCTION(internal::Matcher, isInTemplateInstantiation) { - return stmt( - hasAncestor(decl(anyOf(cxxRecordDecl(isTemplateInstantiation()), - functionDecl(isTemplateInstantiation()))))); + return stmt(hasAncestor(decl(anyOf(cxxRecordDecl(isTemplateInstantiation()), + functionDecl(isTemplateInstantiation()), + varDecl(isTemplateInstantiation()))))); } /// Matches explicit template specializations of function, class, or diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index 7a130c434e73cedf97338a028292d1b90fc3fa0c..fbbfc4acdf391ef815e32c4be871ce086e2cabfa 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -3702,20 +3702,32 @@ user-declared functions. For example: .. code-block:: c++ + #include + #include + + using namespace std::literals; + // Returns m[key] if key is present, or default_value if not. template const U &get_or_default(const std::map &m [[clang::lifetimebound]], const T &key, /* note, not lifetimebound */ - const U &default_value [[clang::lifetimebound]]); + const U &default_value [[clang::lifetimebound]]) { + if (auto iter = m.find(key); iter != m.end()) return iter->second; + else return default_value; + } - std::map m; - // warning: temporary "bar"s that might be bound to local reference 'val' - // will be destroyed at the end of the full-expression - const std::string &val = get_or_default(m, "foo"s, "bar"s); + int main() { + std::map m; + // warning: temporary bound to local reference 'val1' will be destroyed + // at the end of the full-expression + const std::string &val1 = get_or_default(m, "foo"s, "bar"s); - // No warning in this case. - std::string def_val = "bar"s; - const std::string &val = get_or_default(m, "foo"s, def_val); + // No warning in this case. + std::string def_val = "bar"s; + const std::string &val2 = get_or_default(m, "foo"s, def_val); + + return 0; + } The attribute can be applied to the implicit ``this`` parameter of a member function by writing the attribute after the function type: diff --git a/clang/include/clang/Basic/BuiltinsBase.td b/clang/include/clang/Basic/BuiltinsBase.td index 58dee22fc0a450ddea7039b4b70387a9875b3e99..cff182f3f282cb5c2d34502aa24f5d3a8e64cb9b 100644 --- a/clang/include/clang/Basic/BuiltinsBase.td +++ b/clang/include/clang/Basic/BuiltinsBase.td @@ -60,6 +60,10 @@ def ConstIgnoringExceptions : Attribute<"g">; // This function requires a specific header or an explicit declaration. def RequireDeclaration : Attribute<"h">; +// FIXME: Why is this not simply the min_vector_width attribute? +// Vector has to be at least N bits wide. +class RequiredVectorWidth : IndexedAttribute<"V", N>; + class PrintfFormat : IndexedAttribute<"p", I>; class VPrintfFormat : IndexedAttribute<"P", I>; class ScanfFormat : IndexedAttribute<"s", I>; diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def index 4486eb73a11fa6a3b2ae4a67ce4f94a2d442992e..c93ea27f164e34d000846e8677faea0390089b57 100644 --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -26,17 +26,6 @@ # define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANG, FEATURE) BUILTIN(ID, TYPE, ATTRS) #endif -// Undefined Values -// -TARGET_BUILTIN(__builtin_ia32_undef128, "V2d", "ncV:128:", "") -TARGET_BUILTIN(__builtin_ia32_undef256, "V4d", "ncV:256:", "") -TARGET_BUILTIN(__builtin_ia32_undef512, "V8d", "ncV:512:", "") - -// FLAGS -// -TARGET_BUILTIN(__builtin_ia32_readeflags_u32, "Ui", "n", "") -TARGET_BUILTIN(__builtin_ia32_writeeflags_u32, "vUi", "n", "") - // MMX // // All MMX instructions will be generated via builtins. Any MMX vector @@ -46,113 +35,8 @@ TARGET_BUILTIN(__builtin_ia32_writeeflags_u32, "vUi", "n", "") // argument and our prior approach of using a #define to the current built-in // doesn't work in the presence of re-declaration of _mm_prefetch for windows. TARGET_BUILTIN(_mm_prefetch, "vcC*i", "nc", "mmx") -TARGET_BUILTIN(__builtin_ia32_emms, "v", "n", "mmx") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v4hi, "sV4sIi", "ncV:64:", "sse") -TARGET_BUILTIN(__builtin_ia32_vec_set_v4hi, "V4sV4ssIi", "ncV:64:", "sse") // SSE intrinsics. -TARGET_BUILTIN(__builtin_ia32_comieq, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comilt, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comile, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comigt, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comige, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_comineq, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomieq, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomilt, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomile, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomigt, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomige, "iV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_ucomineq, "iV4fV4f", "ncV:128:", "sse") - -TARGET_BUILTIN(__builtin_ia32_comisdeq, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdlt, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdle, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdgt, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdge, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_comisdneq, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdeq, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdlt, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdle, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdgt, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdge, "iV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_ucomisdneq, "iV2dV2d", "ncV:128:", "sse2") - -TARGET_BUILTIN(__builtin_ia32_cmpeqps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpltps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpleps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpunordps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpneqps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpnltps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpnleps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpordps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpeqss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpltss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpless, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpunordss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpneqss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpnltss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpnless, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpordss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_minps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_maxps, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_minss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_maxss, "V4fV4fV4f", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "sse") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "sse") - -TARGET_BUILTIN(__builtin_ia32_cmpeqpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpltpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmplepd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpunordpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpneqpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpnltpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpnlepd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpordpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpeqsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpltsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmplesd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpunordsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpneqsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpnltsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpnlesd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpordsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_minpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_maxpd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_minsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_maxsd, "V2dV2dV2d", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_pmulhw128, "V8sV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_pavgb128, "V16cV16cV16c", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_pavgw128, "V8sV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_packsswb128, "V16cV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_packssdw128, "V8sV4iV4i", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_packuswb128, "V16cV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_pmulhuw128, "V8sV8sV8s", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v2di, "OiV2OiIi", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v4si, "iV4iIi", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v4sf, "fV4fIi", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_ext_v8hi, "sV8sIi", "ncV:128:", "sse2") -TARGET_BUILTIN(__builtin_ia32_vec_set_v8hi, "V8sV8ssIi", "ncV:128:", "sse2") - -TARGET_BUILTIN(__builtin_ia32_addsubps, "V4fV4fV4f", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_addsubpd, "V2dV2dV2d", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_haddps, "V4fV4fV4f", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_haddpd, "V2dV2dV2d", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_hsubps, "V4fV4fV4f", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_hsubpd, "V2dV2dV2d", "ncV:128:", "sse3") -TARGET_BUILTIN(__builtin_ia32_phaddw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phaddd128, "V4iV4iV4i", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phaddsw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phsubw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phsubd128, "V4iV4iV4i", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_phsubsw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_pmaddubsw128, "V8sV16cV16c", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_pmulhrsw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_pshufb128, "V16cV16cV16c", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_psignb128, "V16cV16cV16c", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_psignw128, "V8sV8sV8s", "ncV:128:", "ssse3") -TARGET_BUILTIN(__builtin_ia32_psignd128, "V4iV4iV4i", "ncV:128:", "ssse3") TARGET_BUILTIN(__builtin_ia32_ldmxcsr, "vUi", "n", "sse") TARGET_HEADER_BUILTIN(_mm_setcsr, "vUi", "nh",XMMINTRIN_H, ALL_LANGUAGES, "sse") @@ -316,16 +200,6 @@ TARGET_BUILTIN(__builtin_ia32_pclmulqdq256, "V4OiV4OiV4OiIc", "ncV:256:", "vpclm TARGET_BUILTIN(__builtin_ia32_pclmulqdq512, "V8OiV8OiV8OiIc", "ncV:512:", "avx512f,evex512,vpclmulqdq") // AVX -TARGET_BUILTIN(__builtin_ia32_addsubpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_addsubps256, "V8fV8fV8f", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_haddpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_hsubps256, "V8fV8fV8f", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_hsubpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_haddps256, "V8fV8fV8f", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_maxpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_maxps256, "V8fV8fV8f", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_minpd256, "V4dV4dV4d", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_minps256, "V8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vpermilvarpd, "V2dV2dV2Oi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vpermilvarps, "V4fV4fV4i", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_vpermilvarpd256, "V4dV4dV4Oi", "ncV:256:", "avx") diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td new file mode 100644 index 0000000000000000000000000000000000000000..cf8d2771310e3ce1480d094106ef38d7fdae35a1 --- /dev/null +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -0,0 +1,137 @@ +//===--- BuiltinsX86.td - X86 Builtin function database ---------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines the X86-specific builtin function database. +// +//===----------------------------------------------------------------------===// + +include "clang/Basic/BuiltinsBase.td" + +class X86Builtin : TargetBuiltin { + let Spellings = ["__builtin_ia32_" # NAME]; + let Prototype = prototype; +} + +// Undefined Values +def undef128 : X86Builtin<"_Vector<2, double>()"> { + let Attributes = [Const, NoThrow, RequiredVectorWidth<128>]; +} + +def undef256 : X86Builtin<"_Vector<4, double>()"> { + let Attributes = [Const, NoThrow, RequiredVectorWidth<256>]; +} + +def undef512 : X86Builtin<"_Vector<8, double>()"> { + let Attributes = [Const, NoThrow, RequiredVectorWidth<512>]; +} + +// FLAGS +def readeflags_u32 : X86Builtin<"unsigned int()"> { + let Attributes = [NoThrow]; +} + +def writeeflags_u32 : X86Builtin<"void(unsigned int)"> { + let Attributes = [NoThrow]; +} + +// MMX +// +// All MMX instructions will be generated via builtins. Any MMX vector +// types (<1 x i64>, <2 x i32>, etc.) that aren't used by these builtins will be +// expanded by the back-end. + +def emms : X86Builtin<"void()"> { + let Attributes = [NoThrow]; + let Features = "mmx"; +} + +let Attributes = [NoThrow, Const, RequiredVectorWidth<64>], Features = "sse" in { + def vec_ext_v4hi : X86Builtin<"short(_Vector<4, short>, _Constant int)">; + def vec_set_v4hi : X86Builtin<"_Vector<4, short>(_Vector<4, short>, short, _Constant int)">; +} + +// SSE intrinsics +let Attributes = [Const, NoThrow, RequiredVectorWidth<128>] in { + foreach Cmp = ["eq", "lt", "le", "gt", "ge", "neq"] in { + let Features = "sse" in { + def comi#Cmp : X86Builtin<"int(_Vector<4, float>, _Vector<4, float>)">; + def ucomi#Cmp : X86Builtin<"int(_Vector<4, float>, _Vector<4, float>)">; + } + let Features = "sse2" in { + def comisd#Cmp : X86Builtin<"int(_Vector<2, double>, _Vector<2, double>)">; + def ucomisd#Cmp : X86Builtin<"int(_Vector<2, double>, _Vector<2, double>)">; + } + } + + foreach Cmp = ["cmpeq", "cmplt", "cmple", "cmpunord", "cmpneq", "cmpnlt", + "cmpnle", "cmpord", "min", "max"] in { + let Features = "sse" in { + def Cmp#ps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">; + def Cmp#ss : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">; + } + let Features = "sse2" in { + def Cmp#pd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">; + def Cmp#sd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">; + } + } + + let Features = "sse" in { + def cmpps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Constant char)">; + def cmpss : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Constant char)">; + } + + let Features = "sse2" in { + def cmppd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>, _Constant char)">; + def cmpsd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>, _Constant char)">; + } + + let Features = "sse2" in { + def pmulhw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def pavgb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; + def pavgw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def packsswb128 : X86Builtin<"_Vector<16, char>(_Vector<8, short>, _Vector<8, short>)">; + def packssdw128 : X86Builtin<"_Vector<8, short>(_Vector<4, int>, _Vector<4, int>)">; + def packuswb128 : X86Builtin<"_Vector<16, char>(_Vector<8, short>, _Vector<8, short>)">; + def pmulhuw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def vec_ext_v2di : X86Builtin<"long long int(_Vector<2, long long int>, _Constant int)">; + def vec_ext_v4si : X86Builtin<"int(_Vector<4, int>, _Constant int)">; + def vec_ext_v4sf : X86Builtin<"float(_Vector<4, float>, _Constant int)">; + def vec_ext_v8hi : X86Builtin<"short(_Vector<8, short>, _Constant int)">; + def vec_set_v8hi : X86Builtin<"_Vector<8, short>(_Vector<8, short>, short, _Constant int)">; + } + + let Features = "sse3" in { + foreach Op = ["addsub", "hadd", "hsub"] in { + def Op#ps : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>)">; + def Op#pd : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>)">; + } + } + + let Features = "ssse3" in { + foreach Op = ["phadd", "phsub"] in { + def Op#w128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def Op#sw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def Op#d128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">; + } + + def pmaddubsw128 : X86Builtin<"_Vector<8, short>(_Vector<16, char>, _Vector<16, char>)">; + def pmulhrsw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def pshufb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; + def psignb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; + def psignw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def psignd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">; + } +} + +// AVX +let Attributes = [Const, NoThrow, RequiredVectorWidth<256>], Features = "avx" in { + foreach Op = ["addsub", "hadd", "hsub", "max", "min"] in { + def Op#pd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>)">; + def Op#ps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>)">; + } +} diff --git a/clang/include/clang/Basic/BuiltinsX86_64.def b/clang/include/clang/Basic/BuiltinsX86_64.def index e1e613560167ac5fae543f18e2a753a523dd1300..68904ae8abcd1510917951b71d217bab4967c38e 100644 --- a/clang/include/clang/Basic/BuiltinsX86_64.def +++ b/clang/include/clang/Basic/BuiltinsX86_64.def @@ -155,6 +155,12 @@ TARGET_BUILTIN(__builtin_ia32_cmpccxadd64, "SLLiv*SLLiSLLiIi", "n", "cmpccxadd") // AMX_FP16 FP16 TARGET_BUILTIN(__builtin_ia32_tdpfp16ps, "vIUcIUcIUc", "n", "amx-fp16") +// AMX FP8 +TARGET_BUILTIN(__builtin_ia32_tdpbf8ps, "vIUcUIcUIc", "n", "amx-fp8") +TARGET_BUILTIN(__builtin_ia32_tdpbhf8ps, "vIUcUIcUIc", "n", "amx-fp8") +TARGET_BUILTIN(__builtin_ia32_tdphbf8ps, "vIUcUIcUIc", "n", "amx-fp8") +TARGET_BUILTIN(__builtin_ia32_tdphf8ps, "vIUcUIcUIc", "n", "amx-fp8") + // RAO-INT TARGET_BUILTIN(__builtin_ia32_aadd64, "vv*SOi", "n", "raoint") TARGET_BUILTIN(__builtin_ia32_aand64, "vv*SOi", "n", "raoint") diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt index 6ce32598043f2edeceabfb670c6bad51f85922f5..aa9e1cfcbaf6556ef22d446a89b014b09ecf1bd4 100644 --- a/clang/include/clang/Basic/CMakeLists.txt +++ b/clang/include/clang/Basic/CMakeLists.txt @@ -60,6 +60,10 @@ clang_tablegen(BuiltinsRISCV.inc -gen-clang-builtins SOURCE BuiltinsRISCV.td TARGET ClangBuiltinsRISCV) +clang_tablegen(BuiltinsX86.inc -gen-clang-builtins + SOURCE BuiltinsX86.td + TARGET ClangBuiltinsX86) + # ARM NEON and MVE clang_tablegen(arm_neon.inc -gen-arm-neon-sema SOURCE arm_neon.td diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h index 7e7ce5004b29404eb12c66b23ef757ae80da4d36..f0c24643933e87b98c3e95dc19b701b847631f1a 100644 --- a/clang/include/clang/Basic/TargetBuiltins.h +++ b/clang/include/clang/Basic/TargetBuiltins.h @@ -125,6 +125,8 @@ namespace clang { LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1, #define BUILTIN(ID, TYPE, ATTRS) BI##ID, #include "clang/Basic/BuiltinsX86.def" +#define BUILTIN(ID, TYPE, ATTRS) BI##ID, +#include "clang/Basic/BuiltinsX86.inc" FirstX86_64Builtin, LastX86CommonBuiltin = FirstX86_64Builtin - 1, #define BUILTIN(ID, TYPE, ATTRS) BI##ID, diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 272f52992d67a27d2bce4714457ce83b13462b44..4d8d21301baade1e0c473068bbe73f3071e51244 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4678,7 +4678,8 @@ def malign_loops_EQ : Joined<["-"], "malign-loops=">, Group; def malign_branch_boundary_EQ : Joined<["-"], "malign-branch-boundary=">, Group, @@ -6306,6 +6307,8 @@ def mamx_fp16 : Flag<["-"], "mamx-fp16">, Group; def mno_amx_fp16 : Flag<["-"], "mno-amx-fp16">, Group; def mamx_int8 : Flag<["-"], "mamx-int8">, Group; def mno_amx_int8 : Flag<["-"], "mno-amx-int8">, Group; +def mamx_fp8 : Flag<["-"], "mamx-fp8">, Group; +def mno_amx_fp8 : Flag<["-"], "mno-amx-fp8">, Group; def mamx_tile : Flag<["-"], "mamx-tile">, Group; def mno_amx_tile : Flag<["-"], "mno-amx-tile">, Group; def mcmpccxadd : Flag<["-"], "mcmpccxadd">, Group; @@ -7370,6 +7373,7 @@ def mabi_EQ_ieeelongdouble : Flag<["-"], "mabi=ieeelongdouble">, HelpText<"Use IEEE 754 quadruple-precision for long double">, MarshallingInfoFlag>; def mabi_EQ_vec_extabi : Flag<["-"], "mabi=vec-extabi">, + Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>, HelpText<"Enable the extended Altivec ABI on AIX. Use volatile and nonvolatile vector registers">, MarshallingInfoFlag>; def mfloat_abi : Separate<["-"], "mfloat-abi">, diff --git a/clang/include/clang/Index/USRGeneration.h b/clang/include/clang/Index/USRGeneration.h index f89fc5cf49302c71e9cd2828c4f8bb15a6efd11c..61d267f3545a701431e1ee2f608a0061312c5fe9 100644 --- a/clang/include/clang/Index/USRGeneration.h +++ b/clang/include/clang/Index/USRGeneration.h @@ -15,6 +15,7 @@ namespace clang { class ASTContext; class Decl; +class LangOptions; class MacroDefinitionRecord; class Module; class SourceLocation; @@ -30,6 +31,8 @@ static inline StringRef getUSRSpacePrefix() { /// Generate a USR for a Decl, including the USR prefix. /// \returns true if the results should be ignored, false otherwise. bool generateUSRForDecl(const Decl *D, SmallVectorImpl &Buf); +bool generateUSRForDecl(const Decl *D, SmallVectorImpl &Buf, + const LangOptions &LangOpts); /// Generate a USR fragment for an Objective-C class. void generateUSRForObjCClass(StringRef Cls, raw_ostream &OS, @@ -75,7 +78,10 @@ bool generateUSRForMacro(StringRef MacroName, SourceLocation Loc, /// Generates a USR for a type. /// /// \return true on error, false on success. -bool generateUSRForType(QualType T, ASTContext &Ctx, SmallVectorImpl &Buf); +bool generateUSRForType(QualType T, ASTContext &Ctx, + SmallVectorImpl &Buf); +bool generateUSRForType(QualType T, ASTContext &Ctx, SmallVectorImpl &Buf, + const LangOptions &LangOpts); /// Generate a USR for a module, including the USR prefix. /// \returns true on error, false on success. diff --git a/clang/include/clang/Sema/SemaObjC.h b/clang/include/clang/Sema/SemaObjC.h index 1332eb4f4d4233babcc1310b4b3329842a20d63b..791a7f45b832f791848ec14a60fdec89d79136ec 100644 --- a/clang/include/clang/Sema/SemaObjC.h +++ b/clang/include/clang/Sema/SemaObjC.h @@ -351,6 +351,10 @@ public: ParsedAttributesView ArgAttrs; }; + ParmVarDecl *ActOnMethodParmDeclaration(Scope *S, ObjCArgInfo &ArgInfo, + int ParamIndex, + bool MethodDefinition); + Decl *ActOnMethodDeclaration( Scope *S, SourceLocation BeginLoc, // location of the + or -. @@ -359,7 +363,7 @@ public: ArrayRef SelectorLocs, Selector Sel, // optional arguments. The number of types/arguments is obtained // from the Sel.getNumArgs(). - ObjCArgInfo *ArgInfo, DeclaratorChunk::ParamInfo *CParamInfo, + ParmVarDecl **ArgInfo, DeclaratorChunk::ParamInfo *CParamInfo, unsigned CNumArgs, // c-style args const ParsedAttributesView &AttrList, tok::ObjCKeywordKind MethodImplKind, bool isVariadic, bool MethodDefinition); diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index a3664695f0961e84da7826e675aac8b334c49182..2463e24e4bcaf9efd1fb3b5310662bb412b54979 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -5694,7 +5694,7 @@ ASTContext::getDependentTemplateSpecializationType( return QualType(T, 0); } -TemplateArgument ASTContext::getInjectedTemplateArg(NamedDecl *Param) { +TemplateArgument ASTContext::getInjectedTemplateArg(NamedDecl *Param) const { TemplateArgument Arg; if (const auto *TTP = dyn_cast(Param)) { QualType ArgType = getTypeDeclType(TTP); @@ -5738,23 +5738,15 @@ TemplateArgument ASTContext::getInjectedTemplateArg(NamedDecl *Param) { } if (Param->isTemplateParameterPack()) - Arg = TemplateArgument::CreatePackCopy(*this, Arg); + Arg = + TemplateArgument::CreatePackCopy(const_cast(*this), Arg); return Arg; } -void -ASTContext::getInjectedTemplateArgs(const TemplateParameterList *Params, - SmallVectorImpl &Args) { - Args.reserve(Args.size() + Params->size()); - - for (NamedDecl *Param : *Params) - Args.push_back(getInjectedTemplateArg(Param)); -} - QualType ASTContext::getPackExpansionType(QualType Pattern, std::optional NumExpansions, - bool ExpectPackInType) { + bool ExpectPackInType) const { assert((!ExpectPackInType || Pattern->containsUnexpandedParameterPack()) && "Pack expansions must expand one or more parameter packs"); diff --git a/clang/lib/AST/DeclTemplate.cpp b/clang/lib/AST/DeclTemplate.cpp index 4a506b7be4564298a58c13ee6f92a5f8f09172d7..755ec72f00bf77177715ed1486c7254e74db880d 100644 --- a/clang/lib/AST/DeclTemplate.cpp +++ b/clang/lib/AST/DeclTemplate.cpp @@ -51,7 +51,7 @@ DefaultTemplateArgumentContainsUnexpandedPack(const TemplateParam &P) { P.getDefaultArgument().getArgument().containsUnexpandedParameterPack(); } -TemplateParameterList::TemplateParameterList(const ASTContext& C, +TemplateParameterList::TemplateParameterList(const ASTContext &C, SourceLocation TemplateLoc, SourceLocation LAngleLoc, ArrayRef Params, @@ -244,6 +244,17 @@ bool TemplateParameterList::hasAssociatedConstraints() const { return HasRequiresClause || HasConstrainedParameters; } +ArrayRef +TemplateParameterList::getInjectedTemplateArgs(const ASTContext &Context) { + if (!InjectedArgs) { + InjectedArgs = new (Context) TemplateArgument[size()]; + llvm::transform(*this, InjectedArgs, [&](NamedDecl *ND) { + return Context.getInjectedTemplateArg(ND); + }); + } + return {InjectedArgs, NumParams}; +} + bool TemplateParameterList::shouldIncludeTypeForArgument( const PrintingPolicy &Policy, const TemplateParameterList *TPL, unsigned Idx) { @@ -396,22 +407,6 @@ void RedeclarableTemplateDecl::addSpecializationImpl( SETraits::getDecl(Entry)); } -ArrayRef RedeclarableTemplateDecl::getInjectedTemplateArgs() { - TemplateParameterList *Params = getTemplateParameters(); - auto *CommonPtr = getCommonPtr(); - if (!CommonPtr->InjectedArgs) { - auto &Context = getASTContext(); - SmallVector TemplateArgs; - Context.getInjectedTemplateArgs(Params, TemplateArgs); - CommonPtr->InjectedArgs = - new (Context) TemplateArgument[TemplateArgs.size()]; - std::copy(TemplateArgs.begin(), TemplateArgs.end(), - CommonPtr->InjectedArgs); - } - - return llvm::ArrayRef(CommonPtr->InjectedArgs, Params->size()); -} - //===----------------------------------------------------------------------===// // FunctionTemplateDecl Implementation //===----------------------------------------------------------------------===// @@ -631,13 +626,10 @@ ClassTemplateDecl::getInjectedClassNameSpecialization() { // expansion (14.5.3) whose pattern is the name of the template parameter // pack. ASTContext &Context = getASTContext(); - TemplateParameterList *Params = getTemplateParameters(); - SmallVector TemplateArgs; - Context.getInjectedTemplateArgs(Params, TemplateArgs); TemplateName Name = Context.getQualifiedTemplateName( /*NNS=*/nullptr, /*TemplateKeyword=*/false, TemplateName(this)); - CommonPtr->InjectedClassNameType = - Context.getTemplateSpecializationType(Name, TemplateArgs); + CommonPtr->InjectedClassNameType = Context.getTemplateSpecializationType( + Name, getTemplateParameters()->getInjectedTemplateArgs(Context)); return CommonPtr->InjectedClassNameType; } @@ -1184,20 +1176,6 @@ SourceRange ClassTemplatePartialSpecializationDecl::getSourceRange() const { return Range; } -ArrayRef -ClassTemplatePartialSpecializationDecl::getInjectedTemplateArgs() { - TemplateParameterList *Params = getTemplateParameters(); - auto *First = cast(getFirstDecl()); - if (!First->InjectedArgs) { - auto &Context = getASTContext(); - SmallVector TemplateArgs; - Context.getInjectedTemplateArgs(Params, TemplateArgs); - First->InjectedArgs = new (Context) TemplateArgument[TemplateArgs.size()]; - std::copy(TemplateArgs.begin(), TemplateArgs.end(), First->InjectedArgs); - } - return llvm::ArrayRef(First->InjectedArgs, Params->size()); -} - //===----------------------------------------------------------------------===// // FriendTemplateDecl Implementation //===----------------------------------------------------------------------===// @@ -1548,20 +1526,6 @@ SourceRange VarTemplatePartialSpecializationDecl::getSourceRange() const { return Range; } -ArrayRef -VarTemplatePartialSpecializationDecl::getInjectedTemplateArgs() { - TemplateParameterList *Params = getTemplateParameters(); - auto *First = cast(getFirstDecl()); - if (!First->InjectedArgs) { - auto &Context = getASTContext(); - SmallVector TemplateArgs; - Context.getInjectedTemplateArgs(Params, TemplateArgs); - First->InjectedArgs = new (Context) TemplateArgument[TemplateArgs.size()]; - std::copy(TemplateArgs.begin(), TemplateArgs.end(), First->InjectedArgs); - } - return llvm::ArrayRef(First->InjectedArgs, Params->size()); -} - static TemplateParameterList * createMakeIntegerSeqParameterList(const ASTContext &C, DeclContext *DC) { // typename T diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp index b3e46508cf596dea0c2ecba5f4f77e1ab3032bb2..14bc260d0245fb90e6d981ebe2b7a2c94ef54a1a 100644 --- a/clang/lib/AST/ItaniumMangle.cpp +++ b/clang/lib/AST/ItaniumMangle.cpp @@ -468,6 +468,7 @@ public: void mangleLambdaSig(const CXXRecordDecl *Lambda); void mangleModuleNamePrefix(StringRef Name, bool IsPartition = false); void mangleVendorQualifier(StringRef Name); + void mangleVendorType(StringRef Name); private: @@ -2891,6 +2892,10 @@ void CXXNameMangler::mangleVendorQualifier(StringRef name) { Out << 'U' << name.size() << name; } +void CXXNameMangler::mangleVendorType(StringRef name) { + Out << 'u' << name.size() << name; +} + void CXXNameMangler::mangleRefQualifier(RefQualifierKind RefQualifier) { // ::= R # lvalue reference // ::= O # rvalue-reference @@ -3413,8 +3418,7 @@ void CXXNameMangler::mangleType(const BuiltinType *T) { if (T->getKind() == BuiltinType::SveBFloat16 && \ isCompatibleWith(LangOptions::ClangABI::Ver17)) { \ /* Prior to Clang 18.0 we used this incorrect mangled name */ \ - type_name = "__SVBFloat16_t"; \ - Out << "u" << type_name.size() << type_name; \ + mangleVendorType("__SVBFloat16_t"); \ } else { \ type_name = MangledName; \ Out << (type_name == Name ? "u" : "") << type_name.size() << type_name; \ @@ -3436,35 +3440,30 @@ void CXXNameMangler::mangleType(const BuiltinType *T) { Out << (type_name == Name ? "u" : "") << type_name.size() << type_name; \ break; #include "clang/Basic/AArch64SVEACLETypes.def" -#define PPC_VECTOR_TYPE(Name, Id, Size) \ - case BuiltinType::Id: \ - type_name = #Name; \ - Out << 'u' << type_name.size() << type_name; \ +#define PPC_VECTOR_TYPE(Name, Id, Size) \ + case BuiltinType::Id: \ + mangleVendorType(#Name); \ break; #include "clang/Basic/PPCTypes.def" // TODO: Check the mangling scheme for RISC-V V. #define RVV_TYPE(Name, Id, SingletonId) \ case BuiltinType::Id: \ - type_name = Name; \ - Out << 'u' << type_name.size() << type_name; \ + mangleVendorType(Name); \ break; #include "clang/Basic/RISCVVTypes.def" #define WASM_REF_TYPE(InternalName, MangledName, Id, SingletonId, AS) \ case BuiltinType::Id: \ - type_name = MangledName; \ - Out << 'u' << type_name.size() << type_name; \ + mangleVendorType(MangledName); \ break; #include "clang/Basic/WebAssemblyReferenceTypes.def" #define AMDGPU_TYPE(Name, Id, SingletonId, Width, Align) \ case BuiltinType::Id: \ - type_name = Name; \ - Out << 'u' << type_name.size() << type_name; \ + mangleVendorType(Name); \ break; #include "clang/Basic/AMDGPUTypes.def" #define HLSL_INTANGIBLE_TYPE(Name, Id, SingletonId) \ case BuiltinType::Id: \ - type_name = #Name; \ - Out << 'u' << type_name.size() << type_name; \ + mangleVendorType(#Name); \ break; #include "clang/Basic/HLSLIntangibleTypes.def" } @@ -4035,8 +4034,9 @@ void CXXNameMangler::mangleAArch64FixedSveVectorType(const VectorType *T) { if (T->getVectorKind() == VectorKind::SveFixedLengthPredicate) VecSizeInBits *= 8; - Out << "9__SVE_VLSI" << 'u' << TypeName.size() << TypeName << "Lj" - << VecSizeInBits << "EE"; + Out << "9__SVE_VLSI"; + mangleVendorType(TypeName); + Out << "Lj" << VecSizeInBits << "EE"; } void CXXNameMangler::mangleAArch64FixedSveVectorType( @@ -4136,8 +4136,9 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const VectorType *T) { } TypeNameOS << "_t"; - Out << "9__RVV_VLSI" << 'u' << TypeNameStr.size() << TypeNameStr << "Lj" - << VecSizeInBits << "EE"; + Out << "9__RVV_VLSI"; + mangleVendorType(TypeNameStr); + Out << "Lj" << VecSizeInBits << "EE"; } void CXXNameMangler::mangleRISCVFixedRVVVectorType( @@ -4236,8 +4237,7 @@ void CXXNameMangler::mangleType(const ConstantMatrixType *T) { // Mangle matrix types as a vendor extended type: // umatrix_typeIE - StringRef VendorQualifier = "matrix_type"; - Out << "u" << VendorQualifier.size() << VendorQualifier; + mangleVendorType("matrix_type"); Out << "I"; auto &ASTCtx = getASTContext(); @@ -4255,8 +4255,7 @@ void CXXNameMangler::mangleType(const ConstantMatrixType *T) { void CXXNameMangler::mangleType(const DependentSizedMatrixType *T) { // Mangle matrix types as a vendor extended type: // umatrix_typeIE - StringRef VendorQualifier = "matrix_type"; - Out << "u" << VendorQualifier.size() << VendorQualifier; + mangleVendorType("matrix_type"); Out << "I"; mangleTemplateArgExpr(T->getRowExpr()); @@ -4302,7 +4301,7 @@ void CXXNameMangler::mangleType(const ObjCObjectType *T) { StringRef name = I->getName(); QualOS << name.size() << name; } - Out << 'U' << QualStr.size() << QualStr; + mangleVendorQualifier(QualStr); } mangleType(T->getBaseType()); @@ -4436,8 +4435,6 @@ void CXXNameMangler::mangleType(const UnaryTransformType *T) { // If this is dependent, we need to record that. If not, we simply // mangle it as the underlying type since they are equivalent. if (T->isDependentType()) { - Out << "u"; - StringRef BuiltinName; switch (T->getUTTKind()) { #define TRANSFORM_TYPE_TRAIT_DEF(Enum, Trait) \ @@ -4446,7 +4443,7 @@ void CXXNameMangler::mangleType(const UnaryTransformType *T) { break; #include "clang/Basic/TransformTypeTraits.def" } - Out << BuiltinName.size() << BuiltinName; + mangleVendorType(BuiltinName); } Out << "I"; @@ -5311,9 +5308,8 @@ recurse: // ::= u * E # vendor extension const TypeTraitExpr *TTE = cast(E); NotPrimaryExpr(); - Out << 'u'; llvm::StringRef Spelling = getTraitSpelling(TTE->getTrait()); - Out << Spelling.size() << Spelling; + mangleVendorType(Spelling); for (TypeSourceInfo *TSI : TTE->getArgs()) { mangleType(TSI->getType()); } diff --git a/clang/lib/Analysis/UnsafeBufferUsage.cpp b/clang/lib/Analysis/UnsafeBufferUsage.cpp index fad2f52e89ef149ad67aad2efe46f9e2b0631adf..2c68409b846bc88e9606518a9d63167776396667 100644 --- a/clang/lib/Analysis/UnsafeBufferUsage.cpp +++ b/clang/lib/Analysis/UnsafeBufferUsage.cpp @@ -171,6 +171,12 @@ public: return VisitorBase::TraverseCXXTypeidExpr(Node); } + bool TraverseCXXDefaultInitExpr(CXXDefaultInitExpr *Node) { + if (!TraverseStmt(Node->getExpr())) + return false; + return VisitorBase::TraverseCXXDefaultInitExpr(Node); + } + bool TraverseStmt(Stmt *Node, DataRecursionQueue *Queue = nullptr) { if (!Node) return true; @@ -1972,14 +1978,18 @@ public: }; /// Scan the function and return a list of gadgets found with provided kits. -static std::tuple -findGadgets(const Decl *D, const UnsafeBufferUsageHandler &Handler, - bool EmitSuggestions) { +static void findGadgets(const Stmt *S, ASTContext &Ctx, + const UnsafeBufferUsageHandler &Handler, + bool EmitSuggestions, FixableGadgetList &FixableGadgets, + WarningGadgetList &WarningGadgets, + DeclUseTracker &Tracker) { struct GadgetFinderCallback : MatchFinder::MatchCallback { - FixableGadgetList FixableGadgets; - WarningGadgetList WarningGadgets; - DeclUseTracker Tracker; + GadgetFinderCallback(FixableGadgetList &FixableGadgets, + WarningGadgetList &WarningGadgets, + DeclUseTracker &Tracker) + : FixableGadgets(FixableGadgets), WarningGadgets(WarningGadgets), + Tracker(Tracker) {} void run(const MatchFinder::MatchResult &Result) override { // In debug mode, assert that we've found exactly one gadget. @@ -2020,10 +2030,14 @@ findGadgets(const Decl *D, const UnsafeBufferUsageHandler &Handler, assert(numFound >= 1 && "Gadgets not found in match result!"); assert(numFound <= 1 && "Conflicting bind tags in gadgets!"); } + + FixableGadgetList &FixableGadgets; + WarningGadgetList &WarningGadgets; + DeclUseTracker &Tracker; }; MatchFinder M; - GadgetFinderCallback CB; + GadgetFinderCallback CB{FixableGadgets, WarningGadgets, Tracker}; // clang-format off M.addMatcher( @@ -2068,9 +2082,7 @@ findGadgets(const Decl *D, const UnsafeBufferUsageHandler &Handler, // clang-format on } - M.match(*D->getBody(), D->getASTContext()); - return {std::move(CB.FixableGadgets), std::move(CB.WarningGadgets), - std::move(CB.Tracker)}; + M.match(*S, Ctx); } // Compares AST nodes by source locations. @@ -3614,39 +3626,9 @@ public: } }; -void clang::checkUnsafeBufferUsage(const Decl *D, - UnsafeBufferUsageHandler &Handler, - bool EmitSuggestions) { -#ifndef NDEBUG - Handler.clearDebugNotes(); -#endif - - assert(D && D->getBody()); - // We do not want to visit a Lambda expression defined inside a method - // independently. Instead, it should be visited along with the outer method. - // FIXME: do we want to do the same thing for `BlockDecl`s? - if (const auto *fd = dyn_cast(D)) { - if (fd->getParent()->isLambda() && fd->getParent()->isLocalClass()) - return; - } - - // Do not emit fixit suggestions for functions declared in an - // extern "C" block. - if (const auto *FD = dyn_cast(D)) { - for (FunctionDecl *FReDecl : FD->redecls()) { - if (FReDecl->isExternC()) { - EmitSuggestions = false; - break; - } - } - } - - WarningGadgetSets UnsafeOps; - FixableGadgetSets FixablesForAllVars; - - auto [FixableGadgets, WarningGadgets, Tracker] = - findGadgets(D, Handler, EmitSuggestions); - +void applyGadgets(const Decl *D, FixableGadgetList FixableGadgets, + WarningGadgetList WarningGadgets, DeclUseTracker Tracker, + UnsafeBufferUsageHandler &Handler, bool EmitSuggestions) { if (!EmitSuggestions) { // Our job is very easy without suggestions. Just warn about // every problematic operation and consider it done. No need to deal @@ -3690,8 +3672,10 @@ void clang::checkUnsafeBufferUsage(const Decl *D, if (WarningGadgets.empty()) return; - UnsafeOps = groupWarningGadgetsByVar(std::move(WarningGadgets)); - FixablesForAllVars = groupFixablesByVar(std::move(FixableGadgets)); + WarningGadgetSets UnsafeOps = + groupWarningGadgetsByVar(std::move(WarningGadgets)); + FixableGadgetSets FixablesForAllVars = + groupFixablesByVar(std::move(FixableGadgets)); std::map FixItsForVariableGroup; @@ -3912,3 +3896,56 @@ void clang::checkUnsafeBufferUsage(const Decl *D, } } } + +void clang::checkUnsafeBufferUsage(const Decl *D, + UnsafeBufferUsageHandler &Handler, + bool EmitSuggestions) { +#ifndef NDEBUG + Handler.clearDebugNotes(); +#endif + + assert(D); + + SmallVector Stmts; + + if (const auto *FD = dyn_cast(D)) { + // We do not want to visit a Lambda expression defined inside a method + // independently. Instead, it should be visited along with the outer method. + // FIXME: do we want to do the same thing for `BlockDecl`s? + if (const auto *MD = dyn_cast(D)) { + if (MD->getParent()->isLambda() && MD->getParent()->isLocalClass()) + return; + } + + for (FunctionDecl *FReDecl : FD->redecls()) { + if (FReDecl->isExternC()) { + // Do not emit fixit suggestions for functions declared in an + // extern "C" block. + EmitSuggestions = false; + break; + } + } + + Stmts.push_back(FD->getBody()); + + if (const auto *ID = dyn_cast(D)) { + for (const CXXCtorInitializer *CI : ID->inits()) { + Stmts.push_back(CI->getInit()); + } + } + } else if (isa(D) || isa(D)) { + Stmts.push_back(D->getBody()); + } + + assert(!Stmts.empty()); + + FixableGadgetList FixableGadgets; + WarningGadgetList WarningGadgets; + DeclUseTracker Tracker; + for (Stmt *S : Stmts) { + findGadgets(S, D->getASTContext(), Handler, EmitSuggestions, FixableGadgets, + WarningGadgets, Tracker); + } + applyGadgets(D, std::move(FixableGadgets), std::move(WarningGadgets), + std::move(Tracker), Handler, EmitSuggestions); +} diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index a0f94d5d3154807f757a4985e33f5273c3696fe5..e35ee2b7b9c385396d3676eb960d76962ee5cc81 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -765,8 +765,6 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const { .Case("i8mm", HasMatMul) .Case("bf16", HasBFloat16) .Case("sve", FPU & SveMode) - .Case("sve-bf16", FPU & SveMode && HasBFloat16) - .Case("sve-i8mm", FPU & SveMode && HasMatMul) .Case("sve-b16b16", HasSVEB16B16) .Case("f32mm", FPU & SveMode && HasMatmulFP32) .Case("f64mm", FPU & SveMode && HasMatmulFP64) @@ -1716,7 +1714,7 @@ void DarwinAArch64TargetInfo::getOSDefines(const LangOptions &Opts, if (Triple.isArm64e()) Builder.defineMacro("__arm64e__", "1"); - getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); + DarwinTargetInfo::getOSDefines(Opts, Triple, Builder); } TargetInfo::BuiltinVaListKind diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 700c2f9a5dbd18d1624c8269bca2643fec33e32e..4988682a22f01943ce1c226c98b55a565d83be86 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -32,6 +32,14 @@ static constexpr Builtin::Info BuiltinInfoX86[] = { {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, #include "clang/Basic/BuiltinsX86.def" +#define BUILTIN(ID, TYPE, ATTRS) \ + {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, +#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ + {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, +#define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ + {#ID, TYPE, ATTRS, FEATURE, HeaderDesc::HEADER, LANGS}, +#include "clang/Basic/BuiltinsX86.inc" + #define BUILTIN(ID, TYPE, ATTRS) \ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES}, #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ @@ -420,6 +428,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector &Features, HasAMXTILE = true; } else if (Feature == "+amx-complex") { HasAMXCOMPLEX = true; + } else if (Feature == "+amx-fp8") { + HasAMXFP8 = true; } else if (Feature == "+cmpccxadd") { HasCMPCCXADD = true; } else if (Feature == "+raoint") { @@ -939,6 +949,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__AMX_FP16__"); if (HasAMXCOMPLEX) Builder.defineMacro("__AMX_COMPLEX__"); + if (HasAMXFP8) + Builder.defineMacro("__AMX_FP8__"); if (HasCMPCCXADD) Builder.defineMacro("__CMPCCXADD__"); if (HasRAOINT) @@ -1069,6 +1081,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("amx-fp16", true) .Case("amx-int8", true) .Case("amx-tile", true) + .Case("amx-fp8", true) .Case("avx", true) .Case("avx10.1-256", true) .Case("avx10.1-512", true) @@ -1187,6 +1200,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("amx-fp16", HasAMXFP16) .Case("amx-int8", HasAMXINT8) .Case("amx-tile", HasAMXTILE) + .Case("amx-fp8", HasAMXFP8) .Case("avx", SSELevel >= AVX) .Case("avx10.1-256", HasAVX10_1) .Case("avx10.1-512", HasAVX10_1_512) diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h index e8aad3ec5a74b102c90dfeb9abf0099dfcae28f9..a1b2a0cec209ab152f0fae08a5642f42b965bf4a 100644 --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -157,6 +157,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasAMXINT8 = false; bool HasAMXBF16 = false; bool HasAMXCOMPLEX = false; + bool HasAMXFP8 = false; bool HasSERIALIZE = false; bool HasTSXLDTRK = false; bool HasUSERMSR = false; diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 51cbce7b93fecff35ecdc0cd3ff02883735cfc88..50a9eb0000fb53a26b59decd7e9409f9b7f9fedc 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -1014,9 +1014,10 @@ void EmitAssemblyHelper::RunOptimizationPipeline( if (IsThinLTOPostLink) PB.registerPipelineStartEPCallback( [](ModulePassManager &MPM, OptimizationLevel Level) { - MPM.addPass(LowerTypeTestsPass(/*ExportSummary=*/nullptr, - /*ImportSummary=*/nullptr, - /*DropTypeTests=*/true)); + MPM.addPass(LowerTypeTestsPass( + /*ExportSummary=*/nullptr, + /*ImportSummary=*/nullptr, + /*DropTypeTests=*/lowertypetests::DropTestKind::Assume)); }); // Register callbacks to schedule sanitizer passes at the appropriate part diff --git a/clang/lib/CodeGen/CGBlocks.cpp b/clang/lib/CodeGen/CGBlocks.cpp index 41bb8d19d161ebbbfcf7b47fd7305e4941810179..bfa9b0a2f836bc8331adba14333d1cf1f334bfec 100644 --- a/clang/lib/CodeGen/CGBlocks.cpp +++ b/clang/lib/CodeGen/CGBlocks.cpp @@ -2590,10 +2590,6 @@ const BlockByrefInfo &CodeGenFunction::getBlockByrefInfo(const VarDecl *D) { if (it != BlockByrefInfos.end()) return it->second; - llvm::StructType *byrefType = - llvm::StructType::create(getLLVMContext(), - "struct.__block_byref_" + D->getNameAsString()); - QualType Ty = D->getType(); CharUnits size; @@ -2658,7 +2654,9 @@ const BlockByrefInfo &CodeGenFunction::getBlockByrefInfo(const VarDecl *D) { } types.push_back(varTy); - byrefType->setBody(types, packed); + llvm::StructType *byrefType = llvm::StructType::create( + getLLVMContext(), types, "struct.__block_byref_" + D->getNameAsString(), + packed); BlockByrefInfo info; info.Type = byrefType; diff --git a/clang/lib/CodeGen/CGHLSLRuntime.cpp b/clang/lib/CodeGen/CGHLSLRuntime.cpp index 06558ce796f2e4947828e04db52165e043917f9d..7ba0d615018181898786006eb504183afb9375d8 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.cpp +++ b/clang/lib/CodeGen/CGHLSLRuntime.cpp @@ -306,6 +306,16 @@ void CGHLSLRuntime::annotateHLSLResource(const VarDecl *D, GlobalVariable *GV) { continue; llvm::hlsl::ResourceClass RC = AttrResType->getAttrs().ResourceClass; + if (RC == llvm::hlsl::ResourceClass::UAV || + RC == llvm::hlsl::ResourceClass::SRV) + // UAVs and SRVs have already been converted to use LLVM target types, + // we can disable generating of these resource annotations. This will + // enable progress on structured buffers with user defined types this + // resource annotations code does not handle and it crashes. + // This whole function is going to be removed as soon as cbuffers are + // converted to target types (llvm/llvm-project #114126). + return; + bool IsROV = AttrResType->getAttrs().IsROV; llvm::hlsl::ResourceKind RK = HLSLResAttr->getResourceKind(); llvm::hlsl::ElementType ET = calculateElementType(CGM.getContext(), Ty); diff --git a/clang/lib/CodeGen/CGObjCGNU.cpp b/clang/lib/CodeGen/CGObjCGNU.cpp index 7a07284f8a8aa56af38ae650e68a0e8b82bfe472..d6f5f2a43cf51b20d3d765b7c571c9505d44a046 100644 --- a/clang/lib/CodeGen/CGObjCGNU.cpp +++ b/clang/lib/CodeGen/CGObjCGNU.cpp @@ -1509,8 +1509,8 @@ class CGObjCGNUstep2 : public CGObjCGNUstep { GetSectionBounds(StringRef Section) { if (CGM.getTriple().isOSBinFormatCOFF()) { if (emptyStruct == nullptr) { - emptyStruct = llvm::StructType::create(VMContext, ".objc_section_sentinel"); - emptyStruct->setBody({}, /*isPacked*/true); + emptyStruct = llvm::StructType::create( + VMContext, {}, ".objc_section_sentinel", /*isPacked=*/true); } auto ZeroInit = llvm::Constant::getNullValue(emptyStruct); auto Sym = [&](StringRef Prefix, StringRef SecSuffix) { diff --git a/clang/lib/CodeGen/CGObjCMac.cpp b/clang/lib/CodeGen/CGObjCMac.cpp index 1c16d273a5535713e0c1604d825464442e83285b..47ea636c756438afe7c40fb4ef5931d5b38ffbbf 100644 --- a/clang/lib/CodeGen/CGObjCMac.cpp +++ b/clang/lib/CodeGen/CGObjCMac.cpp @@ -5835,15 +5835,7 @@ ObjCTypesHelper::ObjCTypesHelper(CodeGen::CodeGenModule &cgm) // struct _objc_protocol_extension * ProtocolExtensionPtrTy = llvm::PointerType::getUnqual(ProtocolExtensionTy); - // Handle recursive construction of Protocol and ProtocolList types - - ProtocolTy = - llvm::StructType::create(VMContext, "struct._objc_protocol"); - - ProtocolListTy = - llvm::StructType::create(VMContext, "struct._objc_protocol_list"); - ProtocolListTy->setBody(llvm::PointerType::getUnqual(ProtocolListTy), LongTy, - llvm::ArrayType::get(ProtocolTy, 0)); + // Handle construction of Protocol and ProtocolList types // struct _objc_protocol { // struct _objc_protocol_extension *isa; @@ -5852,9 +5844,16 @@ ObjCTypesHelper::ObjCTypesHelper(CodeGen::CodeGenModule &cgm) // struct _objc_method_description_list *instance_methods; // struct _objc_method_description_list *class_methods; // } - ProtocolTy->setBody(ProtocolExtensionPtrTy, Int8PtrTy, - llvm::PointerType::getUnqual(ProtocolListTy), - MethodDescriptionListPtrTy, MethodDescriptionListPtrTy); + ProtocolTy = llvm::StructType::create( + {ProtocolExtensionPtrTy, Int8PtrTy, + llvm::PointerType::getUnqual(VMContext), MethodDescriptionListPtrTy, + MethodDescriptionListPtrTy}, + "struct._objc_protocol"); + + ProtocolListTy = + llvm::StructType::create({llvm::PointerType::getUnqual(VMContext), LongTy, + llvm::ArrayType::get(ProtocolTy, 0)}, + "struct._objc_protocol_list"); // struct _objc_protocol_list * ProtocolListPtrTy = llvm::PointerType::getUnqual(ProtocolListTy); @@ -5886,8 +5885,6 @@ ObjCTypesHelper::ObjCTypesHelper(CodeGen::CodeGenModule &cgm) "struct._objc_class_extension", IntTy, Int8PtrTy, PropertyListPtrTy); ClassExtensionPtrTy = llvm::PointerType::getUnqual(ClassExtensionTy); - ClassTy = llvm::StructType::create(VMContext, "struct._objc_class"); - // struct _objc_class { // Class isa; // Class super_class; @@ -5902,10 +5899,12 @@ ObjCTypesHelper::ObjCTypesHelper(CodeGen::CodeGenModule &cgm) // char *ivar_layout; // struct _objc_class_ext *ext; // }; - ClassTy->setBody(llvm::PointerType::getUnqual(ClassTy), - llvm::PointerType::getUnqual(ClassTy), Int8PtrTy, LongTy, - LongTy, LongTy, IvarListPtrTy, MethodListPtrTy, CachePtrTy, - ProtocolListPtrTy, Int8PtrTy, ClassExtensionPtrTy); + ClassTy = llvm::StructType::create( + {llvm::PointerType::getUnqual(VMContext), + llvm::PointerType::getUnqual(VMContext), Int8PtrTy, LongTy, LongTy, + LongTy, IvarListPtrTy, MethodListPtrTy, CachePtrTy, ProtocolListPtrTy, + Int8PtrTy, ClassExtensionPtrTy}, + "struct._objc_class"); ClassPtrTy = llvm::PointerType::getUnqual(ClassTy); @@ -5988,13 +5987,9 @@ ObjCNonFragileABITypesHelper::ObjCNonFragileABITypesHelper(CodeGen::CodeGenModul // const struct _prop_list_t * class_properties; // } - // Holder for struct _protocol_list_t * - ProtocolListnfABITy = - llvm::StructType::create(VMContext, "struct._objc_protocol_list"); - ProtocolnfABITy = llvm::StructType::create( "struct._protocol_t", ObjectPtrTy, Int8PtrTy, - llvm::PointerType::getUnqual(ProtocolListnfABITy), MethodListnfABIPtrTy, + llvm::PointerType::getUnqual(VMContext), MethodListnfABIPtrTy, MethodListnfABIPtrTy, MethodListnfABIPtrTy, MethodListnfABIPtrTy, PropertyListPtrTy, IntTy, IntTy, Int8PtrPtrTy, Int8PtrTy, PropertyListPtrTy); @@ -6006,8 +6001,9 @@ ObjCNonFragileABITypesHelper::ObjCNonFragileABITypesHelper(CodeGen::CodeGenModul // long protocol_count; // Note, this is 32/64 bit // struct _protocol_t *[protocol_count]; // } - ProtocolListnfABITy->setBody(LongTy, - llvm::ArrayType::get(ProtocolnfABIPtrTy, 0)); + ProtocolListnfABITy = llvm::StructType::create( + {LongTy, llvm::ArrayType::get(ProtocolnfABIPtrTy, 0)}, + "struct._objc_protocol_list"); // struct _objc_protocol_list* ProtocolListnfABIPtrTy = llvm::PointerType::getUnqual(ProtocolListnfABITy); @@ -6067,11 +6063,12 @@ ObjCNonFragileABITypesHelper::ObjCNonFragileABITypesHelper(CodeGen::CodeGenModul // struct class_ro_t *ro; // } - ClassnfABITy = llvm::StructType::create(VMContext, "struct._class_t"); - ClassnfABITy->setBody(llvm::PointerType::getUnqual(ClassnfABITy), - llvm::PointerType::getUnqual(ClassnfABITy), CachePtrTy, - llvm::PointerType::getUnqual(ImpnfABITy), - llvm::PointerType::getUnqual(ClassRonfABITy)); + ClassnfABITy = llvm::StructType::create( + {llvm::PointerType::getUnqual(VMContext), + llvm::PointerType::getUnqual(VMContext), CachePtrTy, + llvm::PointerType::getUnqual(ImpnfABITy), + llvm::PointerType::getUnqual(ClassRonfABITy)}, + "struct._class_t"); // LLVM for struct _class_t * ClassnfABIPtrTy = llvm::PointerType::getUnqual(ClassnfABITy); diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 2bcca5e85bdfeb916720b3488fa3709005283ad2..ba376f9ecfacde7359471de304c207dae8772a27 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -7146,8 +7146,8 @@ void CodeGenModule::EmitTopLevelDecl(Decl *D) { // For C++ standard modules we are done - we will call the module // initializer for imported modules, and that will likewise call those for // any imports it has. - if (CXX20ModuleInits && Import->getImportedOwningModule() && - !Import->getImportedOwningModule()->isModuleMapModule()) + if (CXX20ModuleInits && Import->getImportedModule() && + Import->getImportedModule()->isNamedModule()) break; // For clang C++ module map modules the initializers for sub-modules are diff --git a/clang/lib/CodeGen/MicrosoftCXXABI.cpp b/clang/lib/CodeGen/MicrosoftCXXABI.cpp index 0b0b45ffead92fb824799984b6949999eb0a000d..3802dc8bcafc49b687b146868c887ba1def423a6 100644 --- a/clang/lib/CodeGen/MicrosoftCXXABI.cpp +++ b/clang/lib/CodeGen/MicrosoftCXXABI.cpp @@ -529,31 +529,29 @@ public: if (ClassHierarchyDescriptorType) return ClassHierarchyDescriptorType; // Forward-declare RTTIClassHierarchyDescriptor to break a cycle. - ClassHierarchyDescriptorType = llvm::StructType::create( - CGM.getLLVMContext(), "rtti.ClassHierarchyDescriptor"); llvm::Type *FieldTypes[] = {CGM.IntTy, CGM.IntTy, CGM.IntTy, getImageRelativeType(CGM.UnqualPtrTy)}; - ClassHierarchyDescriptorType->setBody(FieldTypes); + ClassHierarchyDescriptorType = + llvm::StructType::create(FieldTypes, "rtti.ClassHierarchyDescriptor"); return ClassHierarchyDescriptorType; } llvm::StructType *getCompleteObjectLocatorType() { if (CompleteObjectLocatorType) return CompleteObjectLocatorType; - CompleteObjectLocatorType = llvm::StructType::create( - CGM.getLLVMContext(), "rtti.CompleteObjectLocator"); llvm::Type *FieldTypes[] = { CGM.IntTy, CGM.IntTy, CGM.IntTy, getImageRelativeType(CGM.Int8PtrTy), getImageRelativeType(CGM.UnqualPtrTy), - getImageRelativeType(CompleteObjectLocatorType), + getImageRelativeType(CGM.VoidTy), }; llvm::ArrayRef FieldTypesRef(FieldTypes); if (!isImageRelative()) FieldTypesRef = FieldTypesRef.drop_back(); - CompleteObjectLocatorType->setBody(FieldTypesRef); + CompleteObjectLocatorType = + llvm::StructType::create(FieldTypesRef, "rtti.CompleteObjectLocator"); return CompleteObjectLocatorType; } diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 34de0043ca012aa5435f0a0b83741c5510b01799..bdf3da0c96adcae7f40614669b1f77eb02b60bff 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -109,7 +109,8 @@ ToolChain::ToolChain(const Driver &D, const llvm::Triple &T, llvm::Expected> ToolChain::executeToolChainProgram(StringRef Executable) const { llvm::SmallString<64> OutputFile; - llvm::sys::fs::createTemporaryFile("toolchain-program", "txt", OutputFile); + llvm::sys::fs::createTemporaryFile("toolchain-program", "txt", OutputFile, + llvm::sys::fs::OF_Text); llvm::FileRemover OutputRemover(OutputFile.c_str()); std::optional Redirects[] = { {""}, @@ -128,7 +129,8 @@ ToolChain::executeToolChainProgram(StringRef Executable) const { *Str + "'"); SecondsToWait = std::max(SecondsToWait, 0); // infinite } - if (llvm::sys::ExecuteAndWait(Executable, {}, {}, Redirects, SecondsToWait, + if (llvm::sys::ExecuteAndWait(Executable, {Executable}, {}, Redirects, + SecondsToWait, /*MemoryLimit=*/0, &ErrorMessage)) return llvm::createStringError(std::error_code(), Executable + ": " + ErrorMessage); diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp index 1e2ac4e501bafd1a09e5813ea7ba29036df8005c..f083e40df13144965b163cfb5f002df409bea118 100644 --- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp +++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp @@ -135,21 +135,15 @@ getAArch64ArchFeaturesFromMarch(const Driver &D, StringRef March, return true; } -static bool getAArch64ArchFeaturesFromMcpu( - const Driver &D, StringRef Mcpu, const ArgList &Args, - llvm::AArch64::ExtensionSet &Extensions, std::vector &Features) { +static bool +getAArch64ArchFeaturesFromMcpu(const Driver &D, StringRef Mcpu, + const ArgList &Args, + llvm::AArch64::ExtensionSet &Extensions) { StringRef CPU; std::string McpuLowerCase = Mcpu.lower(); if (!DecodeAArch64Mcpu(D, McpuLowerCase, CPU, Extensions)) return false; - if (Mcpu == "native") { - llvm::StringMap HostFeatures = llvm::sys::getHostCPUFeatures(); - for (auto &[Feature, Enabled] : HostFeatures) { - Features.push_back(Args.MakeArgString((Enabled ? "+" : "-") + Feature)); - } - } - return true; } @@ -216,11 +210,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D, success = getAArch64ArchFeaturesFromMarch(D, A->getValue(), Args, Extensions); else if ((A = Args.getLastArg(options::OPT_mcpu_EQ))) - success = getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions, - Features); + success = + getAArch64ArchFeaturesFromMcpu(D, A->getValue(), Args, Extensions); else if (isCPUDeterminedByTriple(Triple)) success = getAArch64ArchFeaturesFromMcpu( - D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions, Features); + D, getAArch64TargetCPU(Args, Triple, A), Args, Extensions); else // Default to 'A' profile if the architecture is not specified. success = getAArch64ArchFeaturesFromMarch(D, "armv8-a", Args, Extensions); diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index a9d2b7a4dc48f9f7154a3cdb4f5caa1e9e7fedb5..f9d2fdffe3b2fc0aab6041e6ca1e58bf7ab458bc 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -203,6 +203,32 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args, } } +void Flang::AddPPCTargetArgs(const ArgList &Args, + ArgStringList &CmdArgs) const { + const Driver &D = getToolChain().getDriver(); + bool VecExtabi = false; + + if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) { + StringRef V = A->getValue(); + if (V == "vec-extabi") + VecExtabi = true; + else if (V == "vec-default") + VecExtabi = false; + else + D.Diag(diag::err_drv_unsupported_option_argument) + << A->getSpelling() << V; + } + + const llvm::Triple &T = getToolChain().getTriple(); + if (VecExtabi) { + if (!T.isOSAIX()) { + D.Diag(diag::err_drv_unsupported_opt_for_target) + << "-mabi=vec-extabi" << T.str(); + } + CmdArgs.push_back("-mabi=vec-extabi"); + } +} + void Flang::AddRISCVTargetArgs(const ArgList &Args, ArgStringList &CmdArgs) const { const llvm::Triple &Triple = getToolChain().getTriple(); @@ -383,6 +409,11 @@ void Flang::addTargetOptions(const ArgList &Args, getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); AddX86_64TargetArgs(Args, CmdArgs); break; + case llvm::Triple::ppc: + case llvm::Triple::ppc64: + case llvm::Triple::ppc64le: + AddPPCTargetArgs(Args, CmdArgs); + break; } if (Arg *A = Args.getLastArg(options::OPT_fveclib)) { diff --git a/clang/lib/Driver/ToolChains/Flang.h b/clang/lib/Driver/ToolChains/Flang.h index 9f5e26b8608324def4e7cf3a47e2c7d4136a6c4a..4d7d0b8cd9ea55c8d2ff720264d7bdeab0bca1b4 100644 --- a/clang/lib/Driver/ToolChains/Flang.h +++ b/clang/lib/Driver/ToolChains/Flang.h @@ -84,6 +84,13 @@ private: void AddX86_64TargetArgs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const; + /// Add specific options for PPC target. + /// + /// \param [in] Args The list of input driver arguments + /// \param [out] CmdArgs The list of output command arguments + void AddPPCTargetArgs(const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const; + /// Extract offload options from the driver arguments and add them to /// the command arguments. /// \param [in] C The current compilation for the driver invocation diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt index ee3ed71d139f20636842491cf30657e67a68ba48..86ebbaf73c4cc12d56208cb3a10297cf031f9b43 100644 --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -149,6 +149,7 @@ set(x86_files amxcomplexintrin.h amxfp16intrin.h amxintrin.h + amxfp8intrin.h avx10_2_512bf16intrin.h avx10_2_512convertintrin.h avx10_2_512minmaxintrin.h diff --git a/clang/lib/Headers/amxfp8intrin.h b/clang/lib/Headers/amxfp8intrin.h new file mode 100644 index 0000000000000000000000000000000000000000..0f5ddc87e5a7525af63b0a226c78107e9c194c96 --- /dev/null +++ b/clang/lib/Headers/amxfp8intrin.h @@ -0,0 +1,95 @@ +/*===------------- amxfp8intrin.h - AMX intrinsics -*- C++ -*----------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===------------------------------------------------------------------------=== + */ + +#ifndef __IMMINTRIN_H +#error "Never use directly; include instead." +#endif /* __IMMINTRIN_H */ + +#ifndef __AMXFP8INTRIN_H +#define __AMXFP8INTRIN_H +#ifdef __x86_64__ + +/// Peform the dot product of a BF8 value \a a by a BF8 value \a b accumulating +/// into a Single Precision (FP32) source/dest \a dst. +/// +/// \headerfile +/// +/// \code +/// void _tile_dpbf8ps (__tile dst, __tile a, __tile b) +/// \endcode +/// +/// This intrinsic corresponds to the \c TDPBF8PS instruction. +/// +/// \param dst +/// The destination tile. Max size is 1024 Bytes. +/// \param a +/// The 1st source tile. Max size is 1024 Bytes. +/// \param b +/// The 2nd source tile. Max size is 1024 Bytes. +#define _tile_dpbf8ps(dst, a, b) __builtin_ia32_tdpbf8ps((dst), (a), (b)) + +/// Perform the dot product of a BF8 value \a a by an HF8 value \a b +/// accumulating into a Single Precision (FP32) source/dest \a dst. +/// +/// \headerfile +/// +/// \code +/// void _tile_dpbhf8ps (__tile dst, __tile a, __tile b) +/// \endcode +/// +/// This intrinsic corresponds to the \c TDPBHF8PS instruction. +/// +/// \param dst +/// The destination tile. Max size is 1024 Bytes. +/// \param a +/// The 1st source tile. Max size is 1024 Bytes. +/// \param b +/// The 2nd source tile. Max size is 1024 Bytes. +#define _tile_dpbhf8ps(dst, a, b) __builtin_ia32_tdpbhf8ps((dst), (a), (b)) + +/// Perform the dot product of an HF8 value \a a by a BF8 value \a b +/// accumulating into a Single Precision (FP32) source/dest \a dst. +/// +/// \headerfile +/// +/// \code +/// void _tile_dphbf8ps (__tile dst, __tile a, __tile b) +/// \endcode +/// +/// This intrinsic corresponds to the \c TDPHBF8PS instruction. +/// +/// \param dst +/// The destination tile. Max size is 1024 Bytes. +/// \param a +/// The 1st source tile. Max size is 1024 Bytes. +/// \param b +/// The 2nd source tile. Max size is 1024 Bytes. +#define _tile_dphbf8ps(dst, a, b) __builtin_ia32_tdphbf8ps((dst), (a), (b)) + +/// Perform the dot product of an HF8 value \a a by an HF8 value \a b +/// accumulating into a Single Precision (FP32) source/dest \a dst. +/// +/// \headerfile +/// +/// \code +/// void _tile_dphf8ps (__tile dst, __tile a, __tile b) +/// \endcode +/// +/// This intrinsic corresponds to the \c TDPHF8PS instruction. +/// +/// \param dst +/// The destination tile. Max size is 1024 Bytes. +/// \param a +/// The 1st source tile. Max size is 1024 Bytes. +/// \param b +/// The 2nd source tile. Max size is 1024 Bytes. +#define _tile_dphf8ps(dst, a, b) __builtin_ia32_tdphf8ps((dst), (a), (b)) + +#endif /* __x86_64__ */ +#endif /* __AMXFP8INTRIN_H */ diff --git a/clang/lib/Headers/emmintrin.h b/clang/lib/Headers/emmintrin.h index d6494762169b25b5f6d9c8fce2044680ca98e709..4f00b7f1a8d9d4e3ca8ef15a5e47cd66531a09da 100644 --- a/clang/lib/Headers/emmintrin.h +++ b/clang/lib/Headers/emmintrin.h @@ -2110,8 +2110,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_add_epi16(__m128i __a, /// A 128-bit vector of [4 x i32]. /// \returns A 128-bit vector of [4 x i32] containing the sums of both /// parameters. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_add_epi32(__m128i __a, - __m128i __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_add_epi32(__m128i __a, __m128i __b) { return (__m128i)((__v4su)__a + (__v4su)__b); } @@ -2147,8 +2147,8 @@ static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_add_si64(__m64 __a, __m64 __b) { /// A 128-bit vector of [2 x i64]. /// \returns A 128-bit vector of [2 x i64] containing the sums of both /// parameters. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_add_epi64(__m128i __a, - __m128i __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_add_epi64(__m128i __a, __m128i __b) { return (__m128i)((__v2du)__a + (__v2du)__b); } @@ -2539,8 +2539,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_sub_epi16(__m128i __a, /// A 128-bit integer vector containing the subtrahends. /// \returns A 128-bit integer vector containing the differences of the values /// in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_sub_epi32(__m128i __a, - __m128i __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_sub_epi32(__m128i __a, __m128i __b) { return (__m128i)((__v4su)__a - (__v4su)__b); } @@ -2573,8 +2573,8 @@ static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sub_si64(__m64 __a, __m64 __b) { /// A 128-bit integer vector containing the subtrahends. /// \returns A 128-bit integer vector containing the differences of the values /// in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_sub_epi64(__m128i __a, - __m128i __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_sub_epi64(__m128i __a, __m128i __b) { return (__m128i)((__v2du)__a - (__v2du)__b); } @@ -3512,8 +3512,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_undefined_si128(void) { /// destination vector of [2 x i64]. /// \returns An initialized 128-bit vector of [2 x i64] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi64x(long long __q1, - long long __q0) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set_epi64x(long long __q1, long long __q0) { return __extension__(__m128i)(__v2di){__q0, __q1}; } @@ -3533,9 +3533,9 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi64x(long long __q1, /// destination vector of [2 x i64]. /// \returns An initialized 128-bit vector of [2 x i64] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi64(__m64 __q1, - __m64 __q0) { - return _mm_set_epi64x((long long)__q1, (long long)__q0); +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set_epi64(__m64 __q1, __m64 __q0) { + return _mm_set_epi64x((long long)__q1[0], (long long)__q0[0]); } /// Initializes the 32-bit values in a 128-bit vector of [4 x i32] with @@ -3560,8 +3560,10 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi64(__m64 __q1, /// vector. /// \returns An initialized 128-bit vector of [4 x i32] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi32(int __i3, int __i2, - int __i1, int __i0) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set_epi32(int __i3, + int __i2, + int __i1, + int __i0) { return __extension__(__m128i)(__v4si){__i0, __i1, __i2, __i3}; } @@ -3599,7 +3601,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set_epi32(int __i3, int __i2, /// vector. /// \returns An initialized 128-bit vector of [8 x i16] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set_epi16(short __w7, short __w6, short __w5, short __w4, short __w3, short __w2, short __w1, short __w0) { return __extension__(__m128i)(__v8hi){__w0, __w1, __w2, __w3, @@ -3648,7 +3650,7 @@ _mm_set_epi16(short __w7, short __w6, short __w5, short __w4, short __w3, /// Initializes bits [7:0] of the destination vector. /// \returns An initialized 128-bit vector of [16 x i8] containing the values /// provided in the operands. -static __inline__ __m128i __DEFAULT_FN_ATTRS +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set_epi8(char __b15, char __b14, char __b13, char __b12, char __b11, char __b10, char __b9, char __b8, char __b7, char __b6, char __b5, char __b4, char __b3, char __b2, char __b1, char __b0) { @@ -3670,7 +3672,8 @@ _mm_set_epi8(char __b15, char __b14, char __b13, char __b12, char __b11, /// vector. /// \returns An initialized 128-bit integer vector of [2 x i64] with both /// elements containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi64x(long long __q) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set1_epi64x(long long __q) { return _mm_set_epi64x(__q, __q); } @@ -3687,7 +3690,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi64x(long long __q) { /// vector. /// \returns An initialized 128-bit vector of [2 x i64] with all elements /// containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi64(__m64 __q) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set1_epi64(__m64 __q) { return _mm_set_epi64(__q, __q); } @@ -3704,7 +3708,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi64(__m64 __q) { /// vector. /// \returns An initialized 128-bit vector of [4 x i32] with all elements /// containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi32(int __i) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set1_epi32(int __i) { return _mm_set_epi32(__i, __i, __i, __i); } @@ -3721,7 +3725,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi32(int __i) { /// vector. /// \returns An initialized 128-bit vector of [8 x i16] with all elements /// containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi16(short __w) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_set1_epi16(short __w) { return _mm_set_epi16(__w, __w, __w, __w, __w, __w, __w, __w); } @@ -3738,7 +3743,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi16(short __w) { /// vector. /// \returns An initialized 128-bit vector of [16 x i8] with all elements /// containing the value provided in the operand. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi8(char __b) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_set1_epi8(char __b) { return _mm_set_epi8(__b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b, __b); } @@ -3757,8 +3762,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_set1_epi8(char __b) { /// A 64-bit integral value used to initialize the upper 64 bits of the /// result. /// \returns An initialized 128-bit integer vector. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_setr_epi64(__m64 __q0, - __m64 __q1) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_setr_epi64(__m64 __q0, __m64 __q1) { return _mm_set_epi64(__q1, __q0); } @@ -3779,9 +3784,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_setr_epi64(__m64 __q0, /// \param __i3 /// A 32-bit integral value used to initialize bits [127:96] of the result. /// \returns An initialized 128-bit integer vector. -static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_setr_epi32(int __i0, int __i1, - int __i2, - int __i3) { +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_setr_epi32(int __i0, int __i1, int __i2, int __i3) { return _mm_set_epi32(__i3, __i2, __i1, __i0); } @@ -3810,7 +3814,7 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS _mm_setr_epi32(int __i0, int __i1, /// \param __w7 /// A 16-bit integral value used to initialize bits [127:112] of the result. /// \returns An initialized 128-bit integer vector. -static __inline__ __m128i __DEFAULT_FN_ATTRS +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_setr_epi16(short __w0, short __w1, short __w2, short __w3, short __w4, short __w5, short __w6, short __w7) { return _mm_set_epi16(__w7, __w6, __w5, __w4, __w3, __w2, __w1, __w0); @@ -3857,7 +3861,7 @@ _mm_setr_epi16(short __w0, short __w1, short __w2, short __w3, short __w4, /// \param __b15 /// An 8-bit integral value used to initialize bits [127:120] of the result. /// \returns An initialized 128-bit integer vector. -static __inline__ __m128i __DEFAULT_FN_ATTRS +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR _mm_setr_epi8(char __b0, char __b1, char __b2, char __b3, char __b4, char __b5, char __b6, char __b7, char __b8, char __b9, char __b10, char __b11, char __b12, char __b13, char __b14, char __b15) { diff --git a/clang/lib/Headers/hlsl/hlsl_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_intrinsics.h index 8ade4b27f360fbcec54cd192d6f4d1e970d0e45b..d9f3a17ea23d8e7be8f244c6f79afa17541b5ce5 100644 --- a/clang/lib/Headers/hlsl/hlsl_intrinsics.h +++ b/clang/lib/Headers/hlsl/hlsl_intrinsics.h @@ -723,66 +723,88 @@ float4 cosh(float4); #ifdef __HLSL_ENABLE_16_BIT _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int16_t countbits(int16_t); +const inline uint countbits(int16_t x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int16_t2 countbits(int16_t2); +const inline uint2 countbits(int16_t2 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int16_t3 countbits(int16_t3); +const inline uint3 countbits(int16_t3 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int16_t4 countbits(int16_t4); +const inline uint4 countbits(int16_t4 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint16_t countbits(uint16_t); +const inline uint countbits(uint16_t x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint16_t2 countbits(uint16_t2); +const inline uint2 countbits(uint16_t2 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint16_t3 countbits(uint16_t3); +const inline uint3 countbits(uint16_t3 x) { + return __builtin_elementwise_popcount(x); +} _HLSL_AVAILABILITY(shadermodel, 6.2) -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint16_t4 countbits(uint16_t4); +const inline uint4 countbits(uint16_t4 x) { + return __builtin_elementwise_popcount(x); +} #endif -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int countbits(int); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int2 countbits(int2); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int3 countbits(int3); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int4 countbits(int4); - -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint countbits(uint); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint2 countbits(uint2); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint3 countbits(uint3); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint4 countbits(uint4); - -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int64_t countbits(int64_t); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int64_t2 countbits(int64_t2); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int64_t3 countbits(int64_t3); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -int64_t4 countbits(int64_t4); - -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint64_t countbits(uint64_t); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint64_t2 countbits(uint64_t2); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint64_t3 countbits(uint64_t3); -_HLSL_BUILTIN_ALIAS(__builtin_elementwise_popcount) -uint64_t4 countbits(uint64_t4); +const inline uint countbits(int x) { return __builtin_elementwise_popcount(x); } +const inline uint2 countbits(int2 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint3 countbits(int3 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint4 countbits(int4 x) { + return __builtin_elementwise_popcount(x); +} + +const inline uint countbits(uint x) { + return __builtin_elementwise_popcount(x); +} +const inline uint2 countbits(uint2 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint3 countbits(uint3 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint4 countbits(uint4 x) { + return __builtin_elementwise_popcount(x); +} + +const inline uint countbits(int64_t x) { + return __builtin_elementwise_popcount(x); +} +const inline uint2 countbits(int64_t2 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint3 countbits(int64_t3 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint4 countbits(int64_t4 x) { + return __builtin_elementwise_popcount(x); +} + +const inline uint countbits(uint64_t x) { + return __builtin_elementwise_popcount(x); +} +const inline uint2 countbits(uint64_t2 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint3 countbits(uint64_t3 x) { + return __builtin_elementwise_popcount(x); +} +const inline uint4 countbits(uint64_t4 x) { + return __builtin_elementwise_popcount(x); +} //===----------------------------------------------------------------------===// // degrees builtins diff --git a/clang/lib/Headers/immintrin.h b/clang/lib/Headers/immintrin.h index 65ad72bc479f49a2f83cbecc6ad3eccd28f3b7c9..6184e9c84796957a4a8faa1c600e3733561d7229 100644 --- a/clang/lib/Headers/immintrin.h +++ b/clang/lib/Headers/immintrin.h @@ -648,6 +648,10 @@ _storebe_i64(void * __P, long long __D) { #include #endif +#if !defined(__SCE__) || __has_feature(modules) || defined(__AMX_FP8__) +#include +#endif + #if !defined(__SCE__) || __has_feature(modules) || \ defined(__AVX512VP2INTERSECT__) #include diff --git a/clang/lib/Index/USRGeneration.cpp b/clang/lib/Index/USRGeneration.cpp index 35d0aefaf69a680b3ecee3701ea81f9339a16df8..493123459a5a4dbc505660605c50e4bdccff2fec 100644 --- a/clang/lib/Index/USRGeneration.cpp +++ b/clang/lib/Index/USRGeneration.cpp @@ -62,20 +62,17 @@ namespace { class USRGenerator : public ConstDeclVisitor { SmallVectorImpl &Buf; llvm::raw_svector_ostream Out; - bool IgnoreResults; ASTContext *Context; - bool generatedLoc; + const LangOptions &LangOpts; + bool IgnoreResults = false; + bool generatedLoc = false; llvm::DenseMap TypeSubstitutions; public: - explicit USRGenerator(ASTContext *Ctx, SmallVectorImpl &Buf) - : Buf(Buf), - Out(Buf), - IgnoreResults(false), - Context(Ctx), - generatedLoc(false) - { + USRGenerator(ASTContext *Ctx, SmallVectorImpl &Buf, + const LangOptions &LangOpts) + : Buf(Buf), Out(Buf), Context(Ctx), LangOpts(LangOpts) { // Add the USR space prefix. Out << getUSRSpacePrefix(); } @@ -246,14 +243,13 @@ void USRGenerator::VisitFunctionDecl(const FunctionDecl *D) { } else Out << "@F@"; - PrintingPolicy Policy(Context->getLangOpts()); + PrintingPolicy Policy(LangOpts); // Forward references can have different template argument names. Suppress the // template argument names in constructors to make their USR more stable. Policy.SuppressTemplateArgsInCXXConstructors = true; D->getDeclName().print(Out, Policy); - ASTContext &Ctx = *Context; - if ((!Ctx.getLangOpts().CPlusPlus || D->isExternC()) && + if ((!LangOpts.CPlusPlus || D->isExternC()) && !D->hasAttr()) return; @@ -657,9 +653,10 @@ bool USRGenerator::GenLoc(const Decl *D, bool IncludeOffset) { return IgnoreResults; } -static void printQualifier(llvm::raw_ostream &Out, ASTContext &Ctx, NestedNameSpecifier *NNS) { +static void printQualifier(llvm::raw_ostream &Out, const LangOptions &LangOpts, + NestedNameSpecifier *NNS) { // FIXME: Encode the qualifier, don't just print it. - PrintingPolicy PO(Ctx.getLangOpts()); + PrintingPolicy PO(LangOpts); PO.SuppressTagKeyword = true; PO.SuppressUnwrittenScope = true; PO.ConstantArraySizeAsWritten = false; @@ -948,7 +945,7 @@ void USRGenerator::VisitType(QualType T) { } if (const DependentNameType *DNT = T->getAs()) { Out << '^'; - printQualifier(Out, Ctx, DNT->getQualifier()); + printQualifier(Out, LangOpts, DNT->getQualifier()); Out << ':' << DNT->getIdentifier()->getName(); return; } @@ -1090,7 +1087,7 @@ void USRGenerator::VisitUnresolvedUsingValueDecl(const UnresolvedUsingValueDecl return; VisitDeclContext(D->getDeclContext()); Out << "@UUV@"; - printQualifier(Out, D->getASTContext(), D->getQualifier()); + printQualifier(Out, LangOpts, D->getQualifier()); EmitDeclName(D); } @@ -1099,7 +1096,7 @@ void USRGenerator::VisitUnresolvedUsingTypenameDecl(const UnresolvedUsingTypenam return; VisitDeclContext(D->getDeclContext()); Out << "@UUT@"; - printQualifier(Out, D->getASTContext(), D->getQualifier()); + printQualifier(Out, LangOpts, D->getQualifier()); Out << D->getName(); // Simple name. } @@ -1190,6 +1187,13 @@ bool clang::index::generateUSRForDecl(const Decl *D, SmallVectorImpl &Buf) { if (!D) return true; + return generateUSRForDecl(D, Buf, D->getASTContext().getLangOpts()); +} + +bool clang::index::generateUSRForDecl(const Decl *D, SmallVectorImpl &Buf, + const LangOptions &LangOpts) { + if (!D) + return true; // We don't ignore decls with invalid source locations. Implicit decls, like // C++'s operator new function, can have invalid locations but it is fine to // create USRs that can identify them. @@ -1203,7 +1207,7 @@ bool clang::index::generateUSRForDecl(const Decl *D, return false; } } - USRGenerator UG(&D->getASTContext(), Buf); + USRGenerator UG(&D->getASTContext(), Buf, LangOpts); UG.Visit(D); return UG.ignoreResults(); } @@ -1240,11 +1244,17 @@ bool clang::index::generateUSRForMacro(StringRef MacroName, SourceLocation Loc, bool clang::index::generateUSRForType(QualType T, ASTContext &Ctx, SmallVectorImpl &Buf) { + return generateUSRForType(T, Ctx, Buf, Ctx.getLangOpts()); +} + +bool clang::index::generateUSRForType(QualType T, ASTContext &Ctx, + SmallVectorImpl &Buf, + const LangOptions &LangOpts) { if (T.isNull()) return true; T = T.getCanonicalType(); - USRGenerator UG(&Ctx, Buf); + USRGenerator UG(&Ctx, Buf, LangOpts); UG.VisitType(T); return UG.ignoreResults(); } diff --git a/clang/lib/Parse/ParseObjc.cpp b/clang/lib/Parse/ParseObjc.cpp index 28ccd3061f8433a2b4fbd399abf205bb7b79d0db..e69fa152481982d9f5a5d43c7adc05fd64c26d34 100644 --- a/clang/lib/Parse/ParseObjc.cpp +++ b/clang/lib/Parse/ParseObjc.cpp @@ -1454,7 +1454,7 @@ Decl *Parser::ParseObjCMethodDecl(SourceLocation mLoc, SmallVector KeyIdents; SmallVector KeyLocs; - SmallVector ArgInfos; + SmallVector ObjCParamInfo; ParseScope PrototypeScope(this, Scope::FunctionPrototypeScope | Scope::FunctionDeclarationScope | Scope::DeclScope); @@ -1495,7 +1495,9 @@ Decl *Parser::ParseObjCMethodDecl(SourceLocation mLoc, ArgInfo.NameLoc = Tok.getLocation(); ConsumeToken(); // Eat the identifier. - ArgInfos.push_back(ArgInfo); + ParmVarDecl *Param = Actions.ObjC().ActOnMethodParmDeclaration( + getCurScope(), ArgInfo, ObjCParamInfo.size(), MethodDefinition); + ObjCParamInfo.push_back(Param); KeyIdents.push_back(SelIdent); KeyLocs.push_back(selLoc); @@ -1567,8 +1569,8 @@ Decl *Parser::ParseObjCMethodDecl(SourceLocation mLoc, &KeyIdents[0]); Decl *Result = Actions.ObjC().ActOnMethodDeclaration( getCurScope(), mLoc, Tok.getLocation(), mType, DSRet, ReturnType, KeyLocs, - Sel, &ArgInfos[0], CParamInfo.data(), CParamInfo.size(), methodAttrs, - MethodImplKind, isVariadic, MethodDefinition); + Sel, ObjCParamInfo.data(), CParamInfo.data(), CParamInfo.size(), + methodAttrs, MethodImplKind, isVariadic, MethodDefinition); PD.complete(Result); return Result; diff --git a/clang/lib/Parse/ParseStmt.cpp b/clang/lib/Parse/ParseStmt.cpp index 7d727efb228731c6cd43968146ff62580b7bca6a..6470e55e521add7a4a0586a48ad2675e76c3482e 100644 --- a/clang/lib/Parse/ParseStmt.cpp +++ b/clang/lib/Parse/ParseStmt.cpp @@ -1243,6 +1243,7 @@ StmtResult Parser::ParseCompoundStatementBody(bool isStmtExpr) { ParsedStmtContext::Compound | (isStmtExpr ? ParsedStmtContext::InStmtExpr : ParsedStmtContext()); + bool LastIsError = false; while (!tryParseMisplacedModuleImport() && Tok.isNot(tok::r_brace) && Tok.isNot(tok::eof)) { if (Tok.is(tok::annot_pragma_unused)) { @@ -1299,7 +1300,15 @@ StmtResult Parser::ParseCompoundStatementBody(bool isStmtExpr) { if (R.isUsable()) Stmts.push_back(R.get()); + LastIsError = R.isInvalid(); } + // StmtExpr needs to do copy initialization for last statement. + // If last statement is invalid, the last statement in `Stmts` will be + // incorrect. Then the whole compound statement should also be marked as + // invalid to prevent subsequent errors. + if (isStmtExpr && LastIsError && !Stmts.empty()) + return StmtError(); + // Warn the user that using option `-ffp-eval-method=source` on a // 32-bit target and feature `sse` disabled, or using // `pragma clang fp eval_method=source` and feature `sse` disabled, is not diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 3308b898a5b68f44007bf5012c4450da83945d45..dae271c1ff5001470c63003aeeb773e74a641872 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -8900,7 +8900,12 @@ void Sema::CheckMemaccessArguments(const CallExpr *Call, << Call->getCallee()->getSourceRange()); else if (const auto *RT = PointeeTy->getAs()) { - bool IsTriviallyCopyableCXXRecord = + // FIXME: Do not consider incomplete types even though they may be + // completed later. GCC does not diagnose such code, but we may want to + // consider diagnosing it in the future, perhaps under a different, but + // related, diagnostic group. + bool MayBeTriviallyCopyableCXXRecord = + RT->isIncompleteType() || RT->desugar().isTriviallyCopyableType(Context); if ((BId == Builtin::BImemset || BId == Builtin::BIbzero) && @@ -8910,7 +8915,7 @@ void Sema::CheckMemaccessArguments(const CallExpr *Call, << ArgIdx << FnName << PointeeTy << 0); SearchNonTrivialToInitializeField::diag(PointeeTy, Dest, *this); } else if ((BId == Builtin::BImemset || BId == Builtin::BIbzero) && - !IsTriviallyCopyableCXXRecord && ArgIdx == 0) { + !MayBeTriviallyCopyableCXXRecord && ArgIdx == 0) { // FIXME: Limiting this warning to dest argument until we decide // whether it's valid for source argument too. DiagRuntimeBehavior(Dest->getExprLoc(), Dest, @@ -8923,7 +8928,7 @@ void Sema::CheckMemaccessArguments(const CallExpr *Call, << ArgIdx << FnName << PointeeTy << 1); SearchNonTrivialToCopyField::diag(PointeeTy, Dest, *this); } else if ((BId == Builtin::BImemcpy || BId == Builtin::BImemmove) && - !IsTriviallyCopyableCXXRecord && ArgIdx == 0) { + !MayBeTriviallyCopyableCXXRecord && ArgIdx == 0) { // FIXME: Limiting this warning to dest argument until we decide // whether it's valid for source argument too. DiagRuntimeBehavior(Dest->getExprLoc(), Dest, diff --git a/clang/lib/Sema/SemaDeclObjC.cpp b/clang/lib/Sema/SemaDeclObjC.cpp index 78acfeddb786391a1f405edba3b94635bbfe51e6..3b19c9b21c257f3dd343eb43a29c7363359a4b79 100644 --- a/clang/lib/Sema/SemaDeclObjC.cpp +++ b/clang/lib/Sema/SemaDeclObjC.cpp @@ -4720,13 +4720,67 @@ static void checkObjCDirectMethodClashes(Sema &S, ObjCInterfaceDecl *IDecl, diagClash(IMD); } +ParmVarDecl *SemaObjC::ActOnMethodParmDeclaration(Scope *S, + ObjCArgInfo &ArgInfo, + int ParamIndex, + bool MethodDefinition) { + ASTContext &Context = getASTContext(); + QualType ArgType; + TypeSourceInfo *DI; + + if (!ArgInfo.Type) { + ArgType = Context.getObjCIdType(); + DI = nullptr; + } else { + ArgType = SemaRef.GetTypeFromParser(ArgInfo.Type, &DI); + } + LookupResult R(SemaRef, ArgInfo.Name, ArgInfo.NameLoc, + Sema::LookupOrdinaryName, + SemaRef.forRedeclarationInCurContext()); + SemaRef.LookupName(R, S); + if (R.isSingleResult()) { + NamedDecl *PrevDecl = R.getFoundDecl(); + if (S->isDeclScope(PrevDecl)) { + Diag(ArgInfo.NameLoc, + (MethodDefinition ? diag::warn_method_param_redefinition + : diag::warn_method_param_declaration)) + << ArgInfo.Name; + Diag(PrevDecl->getLocation(), diag::note_previous_declaration); + } + } + SourceLocation StartLoc = + DI ? DI->getTypeLoc().getBeginLoc() : ArgInfo.NameLoc; + + // Temporarily put parameter variables in the translation unit. This is what + // ActOnParamDeclarator does in the case of C arguments to the Objective-C + // method too. + ParmVarDecl *Param = SemaRef.CheckParameter( + Context.getTranslationUnitDecl(), StartLoc, ArgInfo.NameLoc, ArgInfo.Name, + ArgType, DI, SC_None); + Param->setObjCMethodScopeInfo(ParamIndex); + Param->setObjCDeclQualifier( + CvtQTToAstBitMask(ArgInfo.DeclSpec.getObjCDeclQualifier())); + + // Apply the attributes to the parameter. + SemaRef.ProcessDeclAttributeList(SemaRef.TUScope, Param, ArgInfo.ArgAttrs); + SemaRef.AddPragmaAttributes(SemaRef.TUScope, Param); + if (Param->hasAttr()) { + Diag(Param->getLocation(), diag::err_block_on_nonlocal); + Param->setInvalidDecl(); + } + + S->AddDecl(Param); + SemaRef.IdResolver.AddDecl(Param); + return Param; +} + Decl *SemaObjC::ActOnMethodDeclaration( Scope *S, SourceLocation MethodLoc, SourceLocation EndLoc, tok::TokenKind MethodType, ObjCDeclSpec &ReturnQT, ParsedType ReturnType, ArrayRef SelectorLocs, Selector Sel, // optional arguments. The number of types/arguments is obtained // from the Sel.getNumArgs(). - ObjCArgInfo *ArgInfo, DeclaratorChunk::ParamInfo *CParamInfo, + ParmVarDecl **ArgInfo, DeclaratorChunk::ParamInfo *CParamInfo, unsigned CNumArgs, // c-style args const ParsedAttributesView &AttrList, tok::ObjCKeywordKind MethodDeclKind, bool isVariadic, bool MethodDefinition) { @@ -4768,60 +4822,10 @@ Decl *SemaObjC::ActOnMethodDeclaration( HasRelatedResultType); SmallVector Params; - - for (unsigned i = 0, e = Sel.getNumArgs(); i != e; ++i) { - QualType ArgType; - TypeSourceInfo *DI; - - if (!ArgInfo[i].Type) { - ArgType = Context.getObjCIdType(); - DI = nullptr; - } else { - ArgType = SemaRef.GetTypeFromParser(ArgInfo[i].Type, &DI); - } - - LookupResult R(SemaRef, ArgInfo[i].Name, ArgInfo[i].NameLoc, - Sema::LookupOrdinaryName, - SemaRef.forRedeclarationInCurContext()); - SemaRef.LookupName(R, S); - if (R.isSingleResult()) { - NamedDecl *PrevDecl = R.getFoundDecl(); - if (S->isDeclScope(PrevDecl)) { - Diag(ArgInfo[i].NameLoc, - (MethodDefinition ? diag::warn_method_param_redefinition - : diag::warn_method_param_declaration)) - << ArgInfo[i].Name; - Diag(PrevDecl->getLocation(), - diag::note_previous_declaration); - } - } - - SourceLocation StartLoc = DI - ? DI->getTypeLoc().getBeginLoc() - : ArgInfo[i].NameLoc; - - ParmVarDecl *Param = - SemaRef.CheckParameter(ObjCMethod, StartLoc, ArgInfo[i].NameLoc, - ArgInfo[i].Name, ArgType, DI, SC_None); - - Param->setObjCMethodScopeInfo(i); - - Param->setObjCDeclQualifier( - CvtQTToAstBitMask(ArgInfo[i].DeclSpec.getObjCDeclQualifier())); - - // Apply the attributes to the parameter. - SemaRef.ProcessDeclAttributeList(SemaRef.TUScope, Param, - ArgInfo[i].ArgAttrs); - SemaRef.AddPragmaAttributes(SemaRef.TUScope, Param); + for (unsigned I = 0; I < Sel.getNumArgs(); ++I) { + ParmVarDecl *Param = ArgInfo[I]; + Param->setDeclContext(ObjCMethod); SemaRef.ProcessAPINotes(Param); - - if (Param->hasAttr()) { - Diag(Param->getLocation(), diag::err_block_on_nonlocal); - Param->setInvalidDecl(); - } - S->AddDecl(Param); - SemaRef.IdResolver.AddDecl(Param); - Params.push_back(Param); } diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index fcf05798d9c709c1f9062053dab4a1a17236d0bb..4503e60cff8c2f0a9672fba7fabb3f0293cdd3f1 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -4381,8 +4381,20 @@ Sema::CheckVarTemplateId(VarTemplateDecl *Template, SourceLocation TemplateLoc, SmallVector PartialSpecs; Template->getPartialSpecializations(PartialSpecs); - for (unsigned I = 0, N = PartialSpecs.size(); I != N; ++I) { - VarTemplatePartialSpecializationDecl *Partial = PartialSpecs[I]; + for (VarTemplatePartialSpecializationDecl *Partial : PartialSpecs) { + // C++ [temp.spec.partial.member]p2: + // If the primary member template is explicitly specialized for a given + // (implicit) specialization of the enclosing class template, the partial + // specializations of the member template are ignored for this + // specialization of the enclosing class template. If a partial + // specialization of the member template is explicitly specialized for a + // given (implicit) specialization of the enclosing class template, the + // primary member template and its other partial specializations are still + // considered for this specialization of the enclosing class template. + if (Template->getMostRecentDecl()->isMemberSpecialization() && + !Partial->getMostRecentDecl()->isMemberSpecialization()) + continue; + TemplateDeductionInfo Info(FailedCandidates.getLocation()); if (TemplateDeductionResult Result = diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp index db1d7fa237131a8441189a8091011f26f6d2ce5b..b45f30fed49a647542dd94cbc0256ec036604a69 100644 --- a/clang/lib/Sema/SemaTemplateDeduction.cpp +++ b/clang/lib/Sema/SemaTemplateDeduction.cpp @@ -6163,7 +6163,7 @@ struct TemplateArgumentListAreEqual { std::enable_if_t, bool> = true> bool operator()(T1 *Spec, T2 *Primary) { ArrayRef Args1 = Spec->getTemplateArgs().asArray(), - Args2 = Primary->getInjectedTemplateArgs(); + Args2 = Primary->getInjectedTemplateArgs(Ctx); for (unsigned I = 0, E = Args1.size(); I < E; ++I) { // We use profile, instead of structural comparison of the arguments, @@ -6342,7 +6342,7 @@ bool Sema::isMoreSpecializedThanPrimary( VarTemplateDecl *Primary = Spec->getSpecializedTemplate(); TemplateName Name(Primary); QualType PrimaryT = Context.getTemplateSpecializationType( - Name, Primary->getInjectedTemplateArgs()); + Name, Primary->getInjectedTemplateArgs(Context)); QualType PartialT = Context.getTemplateSpecializationType( Name, Spec->getTemplateArgs().asArray()); @@ -6372,18 +6372,14 @@ bool Sema::isTemplateTemplateParameterAtLeastAsSpecializedAs( // - Each function template has a single function parameter whose type is // a specialization of X with template arguments corresponding to the // template parameters from the respective function template - SmallVector AArgs; - Context.getInjectedTemplateArgs(A, AArgs); + SmallVector AArgs(A->getInjectedTemplateArgs(Context)); // Check P's arguments against A's parameter list. This will fill in default // template arguments as needed. AArgs are already correct by construction. // We can't just use CheckTemplateIdType because that will expand alias // templates. - SmallVector PArgs; + SmallVector PArgs(P->getInjectedTemplateArgs(Context)); { - SFINAETrap Trap(*this); - - Context.getInjectedTemplateArgs(P, PArgs); TemplateArgumentListInfo PArgList(P->getLAngleLoc(), P->getRAngleLoc()); for (unsigned I = 0, N = P->size(); I != N; ++I) { @@ -6399,6 +6395,7 @@ bool Sema::isTemplateTemplateParameterAtLeastAsSpecializedAs( } PArgs.clear(); + SFINAETrap Trap(*this); // C++1z [temp.arg.template]p3: // If the rewrite produces an invalid type, then P is not at least as // specialized as A. diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index 6a55861fe5af3b1b729d64c0d3612887e5d8e318..b63063813f1b566e40a22b4324038968521b1513 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -200,7 +200,7 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(FTD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(FTD, FTD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(FTD, FTD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (FTD->isMemberSpecialization()) @@ -219,7 +219,7 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(VTD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(VTD, VTD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(VTD, VTD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (VTD->isMemberSpecialization()) @@ -237,7 +237,8 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(VTPSD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(VTPSD, VTPSD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(VTPSD, + VTPSD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (VTPSD->isMemberSpecialization()) @@ -254,7 +255,7 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(CTD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(CTD, CTD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(CTD, CTD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (CTD->isMemberSpecialization()) @@ -274,7 +275,8 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(CTPSD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(CTPSD, CTPSD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(CTPSD, + CTPSD->getInjectedTemplateArgs(S.Context), /*Final=*/false); if (CTPSD->isMemberSpecialization()) @@ -290,7 +292,7 @@ struct TemplateInstantiationArgumentCollecter if (Innermost) AddInnermostTemplateArguments(TATD); else if (ForConstraintInstantiation) - AddOuterTemplateArguments(TATD, TATD->getInjectedTemplateArgs(), + AddOuterTemplateArguments(TATD, TATD->getInjectedTemplateArgs(S.Context), /*Final=*/false); return UseNextDecl(TATD); @@ -3976,11 +3978,24 @@ bool Sema::usesPartialOrExplicitSpecialization( return true; SmallVector PartialSpecs; - ClassTemplateSpec->getSpecializedTemplate() - ->getPartialSpecializations(PartialSpecs); - for (unsigned I = 0, N = PartialSpecs.size(); I != N; ++I) { + ClassTemplateDecl *CTD = ClassTemplateSpec->getSpecializedTemplate(); + CTD->getPartialSpecializations(PartialSpecs); + for (ClassTemplatePartialSpecializationDecl *CTPSD : PartialSpecs) { + // C++ [temp.spec.partial.member]p2: + // If the primary member template is explicitly specialized for a given + // (implicit) specialization of the enclosing class template, the partial + // specializations of the member template are ignored for this + // specialization of the enclosing class template. If a partial + // specialization of the member template is explicitly specialized for a + // given (implicit) specialization of the enclosing class template, the + // primary member template and its other partial specializations are still + // considered for this specialization of the enclosing class template. + if (CTD->getMostRecentDecl()->isMemberSpecialization() && + !CTPSD->getMostRecentDecl()->isMemberSpecialization()) + continue; + TemplateDeductionInfo Info(Loc); - if (DeduceTemplateArguments(PartialSpecs[I], + if (DeduceTemplateArguments(CTPSD, ClassTemplateSpec->getTemplateArgs().asArray(), Info) == TemplateDeductionResult::Success) return true; @@ -4023,8 +4038,21 @@ getPatternForClassTemplateSpecialization( SmallVector PartialSpecs; Template->getPartialSpecializations(PartialSpecs); TemplateSpecCandidateSet FailedCandidates(PointOfInstantiation); - for (unsigned I = 0, N = PartialSpecs.size(); I != N; ++I) { - ClassTemplatePartialSpecializationDecl *Partial = PartialSpecs[I]; + for (ClassTemplatePartialSpecializationDecl *Partial : PartialSpecs) { + // C++ [temp.spec.partial.member]p2: + // If the primary member template is explicitly specialized for a given + // (implicit) specialization of the enclosing class template, the + // partial specializations of the member template are ignored for this + // specialization of the enclosing class template. If a partial + // specialization of the member template is explicitly specialized for a + // given (implicit) specialization of the enclosing class template, the + // primary member template and its other partial specializations are + // still considered for this specialization of the enclosing class + // template. + if (Template->getMostRecentDecl()->isMemberSpecialization() && + !Partial->getMostRecentDecl()->isMemberSpecialization()) + continue; + TemplateDeductionInfo Info(FailedCandidates.getLocation()); if (TemplateDeductionResult Result = S.DeduceTemplateArguments( Partial, ClassTemplateSpec->getTemplateArgs().asArray(), Info); diff --git a/clang/lib/Sema/SemaX86.cpp b/clang/lib/Sema/SemaX86.cpp index 6a4d78f0ca90841cbcd3e5f899c96cd34db461c6..0e43b030e70d41fd563c8591beead164ed4fecee 100644 --- a/clang/lib/Sema/SemaX86.cpp +++ b/clang/lib/Sema/SemaX86.cpp @@ -640,6 +640,10 @@ bool SemaX86::CheckBuiltinTileArguments(unsigned BuiltinID, CallExpr *TheCall) { case X86::BI__builtin_ia32_tdpfp16ps: case X86::BI__builtin_ia32_tcmmimfp16ps: case X86::BI__builtin_ia32_tcmmrlfp16ps: + case X86::BI__builtin_ia32_tdpbf8ps: + case X86::BI__builtin_ia32_tdpbhf8ps: + case X86::BI__builtin_ia32_tdphbf8ps: + case X86::BI__builtin_ia32_tdphf8ps: return CheckBuiltinTileRangeAndDuplicate(TheCall, {0, 1, 2}); } } diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp index 5cdf047738abcb2cfa9fc542a3b5bdadbccf0ac4..76a4599cc8d788383da32ce09fd760a238cb3087 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedLocalVarsChecker.cpp @@ -48,6 +48,65 @@ bool isRefcountedStringsHack(const VarDecl *V) { return false; } +struct GuardianVisitor : public RecursiveASTVisitor { + using Base = RecursiveASTVisitor; + + const VarDecl *Guardian{nullptr}; + +public: + explicit GuardianVisitor(const VarDecl *Guardian) : Guardian(Guardian) { + assert(Guardian); + } + + bool VisitBinaryOperator(const BinaryOperator *BO) { + if (BO->isAssignmentOp()) { + if (auto *VarRef = dyn_cast(BO->getLHS())) { + if (VarRef->getDecl() == Guardian) + return false; + } + } + return true; + } + + bool VisitCXXConstructExpr(const CXXConstructExpr *CE) { + if (auto *Ctor = CE->getConstructor()) { + if (Ctor->isMoveConstructor() && CE->getNumArgs() == 1) { + auto *Arg = CE->getArg(0)->IgnoreParenCasts(); + if (auto *VarRef = dyn_cast(Arg)) { + if (VarRef->getDecl() == Guardian) + return false; + } + } + } + return true; + } + + bool VisitCXXMemberCallExpr(const CXXMemberCallExpr *MCE) { + auto MethodName = safeGetName(MCE->getMethodDecl()); + if (MethodName == "swap" || MethodName == "leakRef" || + MethodName == "releaseNonNull") { + auto *ThisArg = MCE->getImplicitObjectArgument()->IgnoreParenCasts(); + if (auto *VarRef = dyn_cast(ThisArg)) { + if (VarRef->getDecl() == Guardian) + return false; + } + } + return true; + } + + bool VisitCXXOperatorCallExpr(const CXXOperatorCallExpr *OCE) { + if (OCE->isAssignmentOp()) { + assert(OCE->getNumArgs() == 2); + auto *ThisArg = OCE->getArg(0)->IgnoreParenCasts(); + if (auto *VarRef = dyn_cast(ThisArg)) { + if (VarRef->getDecl() == Guardian) + return false; + } + } + return true; + } +}; + bool isGuardedScopeEmbeddedInGuardianScope(const VarDecl *Guarded, const VarDecl *MaybeGuardian) { assert(Guarded); @@ -81,7 +140,7 @@ bool isGuardedScopeEmbeddedInGuardianScope(const VarDecl *Guarded, // We need to skip the first CompoundStmt to avoid situation when guardian is // defined in the same scope as guarded variable. - bool HaveSkippedFirstCompoundStmt = false; + const CompoundStmt *FirstCompondStmt = nullptr; for (DynTypedNodeList guardedVarAncestors = ctx.getParents(*Guarded); !guardedVarAncestors.empty(); guardedVarAncestors = ctx.getParents( @@ -90,12 +149,15 @@ bool isGuardedScopeEmbeddedInGuardianScope(const VarDecl *Guarded, ) { for (auto &guardedVarAncestor : guardedVarAncestors) { if (auto *CStmtAncestor = guardedVarAncestor.get()) { - if (!HaveSkippedFirstCompoundStmt) { - HaveSkippedFirstCompoundStmt = true; + if (!FirstCompondStmt) { + FirstCompondStmt = CStmtAncestor; continue; } - if (CStmtAncestor == guardiansClosestCompStmtAncestor) - return true; + if (CStmtAncestor == guardiansClosestCompStmtAncestor) { + GuardianVisitor guardianVisitor(MaybeGuardian); + auto *GuardedScope = const_cast(FirstCompondStmt); + return guardianVisitor.TraverseCompoundStmt(GuardedScope); + } } } } diff --git a/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc b/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc index 0d351d688a3296c61dd31d20dc5288d4db6127b7..4d466013eeac3f395dc9d7b897db650c5677d8dc 100644 --- a/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc +++ b/clang/lib/Tooling/Inclusions/Stdlib/StdSpecialSymbolMap.inc @@ -367,6 +367,11 @@ SYMBOL(any_cast, std::, ) SYMBOL(div, std::, ) SYMBOL(abort, std::, ) +SYMBOL(binary_search, std::ranges::, ) +SYMBOL(equal_range, std::ranges::, ) +SYMBOL(lower_bound, std::ranges::, ) +SYMBOL(upper_bound, std::ranges::, ) + // These are C symbols that are not under std namespace. SYMBOL(localtime_r, None, ) SYMBOL(localtime_r, None, ) diff --git a/clang/test/Analysis/Checkers/WebKit/mock-types.h b/clang/test/Analysis/Checkers/WebKit/mock-types.h index 8d8a90f0afae0e140f042984405f0a138aecf9c6..82c79c97a83de606fdaef31b7dfc75039a4bea4b 100644 --- a/clang/test/Analysis/Checkers/WebKit/mock-types.h +++ b/clang/test/Analysis/Checkers/WebKit/mock-types.h @@ -49,7 +49,23 @@ template , typename RefDerefTra Ref() : t{} {}; Ref(T &t) : t(&RefDerefTraits::ref(t)) { } Ref(const Ref& o) : t(RefDerefTraits::refIfNotNull(PtrTraits::unwrap(o.t))) { } + Ref(Ref&& o) : t(o.leakRef()) { } ~Ref() { RefDerefTraits::derefIfNotNull(PtrTraits::exchange(t, nullptr)); } + Ref& operator=(T &t) { + Ref o(t); + swap(o); + return *this; + } + Ref& operator=(Ref &&o) { + Ref m(o); + swap(m); + return *this; + } + void swap(Ref& o) { + typename PtrTraits::StorageType tmp = t; + t = o.t; + o.t = tmp; + } T &get() { return *PtrTraits::unwrap(t); } T *ptr() { return PtrTraits::unwrap(t); } T *operator->() { return PtrTraits::unwrap(t); } @@ -74,11 +90,27 @@ template struct RefPtr { if (t) t->deref(); } + Ref releaseNonNull() { + Ref tmp(*t); + if (t) + t->deref(); + t = nullptr; + return tmp; + } + void swap(RefPtr& o) { + T* tmp = t; + t = o.t; + o.t = tmp; + } T *get() { return t; } T *operator->() { return t; } const T *operator->() const { return t; } T &operator*() { return *t; } - RefPtr &operator=(T *) { return *this; } + RefPtr &operator=(T *t) { + RefPtr o(t); + swap(o); + return *this; + } operator bool() const { return t; } }; diff --git a/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp b/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp index 1c0df42cdda663c312d1ebf48132dc87da08cdba..d7fb689557a6fcfd22c975ef803dbee70c2df63b 100644 --- a/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp +++ b/clang/test/Analysis/Checkers/WebKit/uncounted-local-vars.cpp @@ -83,6 +83,83 @@ void foo7(RefCountable* obj) { bar.obj->method(); } +void foo8(RefCountable* obj) { + RefPtr foo; + { + RefCountable *bar = foo.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + foo = nullptr; + bar->method(); + } + RefPtr baz; + { + RefCountable *bar = baz.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + baz = obj; + bar->method(); + } + foo = nullptr; + { + RefCountable *bar = foo.get(); + // No warning. It's okay to mutate RefPtr in an outer scope. + bar->method(); + } + foo = obj; + { + RefCountable *bar = foo.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + foo.releaseNonNull(); + bar->method(); + } + { + RefCountable *bar = foo.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + foo = obj ? obj : nullptr; + bar->method(); + } + { + RefCountable *bar = foo->trivial() ? foo.get() : nullptr; + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + foo = nullptr; + bar->method(); + } +} + +void foo9(RefCountable& o) { + Ref guardian(o); + { + RefCountable &bar = guardian.get(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + guardian = o; // We don't detect that we're setting it to the same value. + bar.method(); + } + { + RefCountable *bar = guardian.ptr(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + Ref other(*bar); // We don't detect other has the same value as guardian. + guardian.swap(other); + bar->method(); + } + { + RefCountable *bar = guardian.ptr(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + Ref other(static_cast&&>(guardian)); + bar->method(); + } + { + RefCountable *bar = guardian.ptr(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + guardian.leakRef(); + bar->method(); + } + { + RefCountable *bar = guardian.ptr(); + // expected-warning@-1{{Local variable 'bar' is uncounted and unsafe [alpha.webkit.UncountedLocalVarsChecker]}} + guardian = o.trivial() ? o : *bar; + bar->method(); + } +} + } // namespace guardian_scopes namespace auto_keyword { diff --git a/clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp b/clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7969b7efe597f98a41fa2c821eff16500a5b619a --- /dev/null +++ b/clang/test/CXX/temp/temp.decls/temp.spec.partial/temp.spec.partial.member/p2.cpp @@ -0,0 +1,85 @@ +// RUN: %clang_cc1 -std=c++20 -fsyntax-only -verify %s +// expected-no-diagnostics + +template +struct A { + template + struct B { + static constexpr int y = 0; + }; + + template + struct B { + static constexpr int y = 1; + }; + + template + static constexpr int x = 0; + + template + static constexpr int x = 1; +}; + +template +template +struct A::B { + static constexpr int y = 2; +}; + +template +template +constexpr int A::x = 2; + +static_assert(A::B::y == 0); +static_assert(A::B::y == 1); +static_assert(A::B::y == 2); +static_assert(A::x == 0); +static_assert(A::x == 1); +static_assert(A::x == 2); + +template<> +template +struct A::B { + static constexpr int y = 3; +}; + +template<> +template +struct A::B { + static constexpr int y = 4; +}; + +template<> +template +struct A::B { + static constexpr int y = 5; +}; + +template<> +template +constexpr int A::x = 3; + +template<> +template +constexpr int A::x = 4; + +template<> +template +constexpr int A::x = 5; + +static_assert(A::B::y == 3); +static_assert(A::B::y == 3); +static_assert(A::B::y == 3); +static_assert(A::B::y == 4); +static_assert(A::x == 3); +static_assert(A::x == 3); +static_assert(A::x == 3); +static_assert(A::x == 4); +static_assert(A::B::y == 0); +static_assert(A::B::y == 1); +static_assert(A::B::y == 2); +static_assert(A::B::y == 5); +static_assert(A::x == 0); +static_assert(A::x == 1); +static_assert(A::x == 2); +static_assert(A::x == 5); diff --git a/clang/test/CodeGen/X86/amx_fp8.c b/clang/test/CodeGen/X86/amx_fp8.c new file mode 100644 index 0000000000000000000000000000000000000000..9c79514f891299ad3037a5d452c560213f2151db --- /dev/null +++ b/clang/test/CodeGen/X86/amx_fp8.c @@ -0,0 +1,27 @@ +// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-fp8 \ +// RUN: -emit-llvm -o - -Werror -pedantic | FileCheck %s +#include + +void test_amx(void *data) { + //CHECK-LABEL: @test_amx + //CHECK: call void @llvm.x86.tdpbf8ps(i8 1, i8 2, i8 3) + _tile_dpbf8ps(1, 2, 3); +} + +void test_amx2(void *data) { + //CHECK-LABEL: @test_amx2 + //CHECK: call void @llvm.x86.tdpbhf8ps(i8 1, i8 2, i8 3) + _tile_dpbhf8ps(1, 2, 3); +} + +void test_amx3(void *data) { + //CHECK-LABEL: @test_amx3 + //CHECK: call void @llvm.x86.tdphbf8ps(i8 1, i8 2, i8 3) + _tile_dphbf8ps(1, 2, 3); +} + +void test_amx4(void *data) { + //CHECK-LABEL: @test_amx4 + //CHECK: call void @llvm.x86.tdphf8ps(i8 1, i8 2, i8 3) + _tile_dphf8ps(1, 2, 3); +} diff --git a/clang/test/CodeGen/X86/amx_fp8_errors.c b/clang/test/CodeGen/X86/amx_fp8_errors.c new file mode 100644 index 0000000000000000000000000000000000000000..77cbd34905b8ba9f307a33d65af3d6a5b1caf11d --- /dev/null +++ b/clang/test/CodeGen/X86/amx_fp8_errors.c @@ -0,0 +1,10 @@ +// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-tile -target-feature +amx-fp8 -verify + +#include + +void test_amx(void *data) { + _tile_dpbf8ps(4, 3, 3); // expected-error {{tile arguments must refer to different tiles}} + _tile_dpbhf8ps(4, 3, 3); // expected-error {{tile arguments must refer to different tiles}} + _tile_dphbf8ps(4, 3, 3); // expected-error {{tile arguments must refer to different tiles}} + _tile_dphf8ps(4, 3, 3); // expected-error {{tile arguments must refer to different tiles}} +} diff --git a/clang/test/CodeGen/X86/amx_fp8_inline_asm.c b/clang/test/CodeGen/X86/amx_fp8_inline_asm.c new file mode 100644 index 0000000000000000000000000000000000000000..49331bd9d368abb3f59f78bd06f0feceab272cb5 --- /dev/null +++ b/clang/test/CodeGen/X86/amx_fp8_inline_asm.c @@ -0,0 +1,32 @@ +// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-fp8 -emit-llvm -o - -Wall -Werror -pedantic | FileCheck %s + +void f_tilemul(short a) +{ + //CHECK: call void asm sideeffect "tileloadd 0(%rsi,%r13,4), %tmm0 \0A\09tileloadd 0(%rdx,%r14,4), %tmm6 \0A\09tdpbf8ps %tmm6, %tmm0, %tmm7 \0A\09tilestored %tmm7, 0(%r12,%r15,4) \0A\09", "~{memory},~{tmm0},~{tmm6},~{tmm7},~{dirflag},~{fpsr},~{flags}"() + __asm__ volatile ("tileloadd 0(%%rsi,%%r13,4), %%tmm0 \n\t" + "tileloadd 0(%%rdx,%%r14,4), %%tmm6 \n\t" + "tdpbf8ps %%tmm6, %%tmm0, %%tmm7 \n\t" + "tilestored %%tmm7, 0(%%r12,%%r15,4) \n\t" + ::: "memory", "tmm0", "tmm6", "tmm7"); + + //CHECK: call void asm sideeffect "tileloadd 0(%rsi,%r13,4), %tmm0 \0A\09tileloadd 0(%rdx,%r14,4), %tmm6 \0A\09tdpbhf8ps %tmm6, %tmm0, %tmm7 \0A\09tilestored %tmm7, 0(%r12,%r15,4) \0A\09", "~{memory},~{tmm0},~{tmm6},~{tmm7},~{dirflag},~{fpsr},~{flags}"() + __asm__ volatile ("tileloadd 0(%%rsi,%%r13,4), %%tmm0 \n\t" + "tileloadd 0(%%rdx,%%r14,4), %%tmm6 \n\t" + "tdpbhf8ps %%tmm6, %%tmm0, %%tmm7 \n\t" + "tilestored %%tmm7, 0(%%r12,%%r15,4) \n\t" + ::: "memory", "tmm0", "tmm6", "tmm7"); + + //CHECK: call void asm sideeffect "tileloadd 0(%rsi,%r13,4), %tmm0 \0A\09tileloadd 0(%rdx,%r14,4), %tmm6 \0A\09tdphbf8ps %tmm6, %tmm0, %tmm7 \0A\09tilestored %tmm7, 0(%r12,%r15,4) \0A\09", "~{memory},~{tmm0},~{tmm6},~{tmm7},~{dirflag},~{fpsr},~{flags}"() + __asm__ volatile ("tileloadd 0(%%rsi,%%r13,4), %%tmm0 \n\t" + "tileloadd 0(%%rdx,%%r14,4), %%tmm6 \n\t" + "tdphbf8ps %%tmm6, %%tmm0, %%tmm7 \n\t" + "tilestored %%tmm7, 0(%%r12,%%r15,4) \n\t" + ::: "memory", "tmm0", "tmm6", "tmm7"); + + //CHECK: call void asm sideeffect "tileloadd 0(%rsi,%r13,4), %tmm0 \0A\09tileloadd 0(%rdx,%r14,4), %tmm6 \0A\09tdphf8ps %tmm6, %tmm0, %tmm7 \0A\09tilestored %tmm7, 0(%r12,%r15,4) \0A\09", "~{memory},~{tmm0},~{tmm6},~{tmm7},~{dirflag},~{fpsr},~{flags}"() + __asm__ volatile ("tileloadd 0(%%rsi,%%r13,4), %%tmm0 \n\t" + "tileloadd 0(%%rdx,%%r14,4), %%tmm6 \n\t" + "tdphf8ps %%tmm6, %%tmm0, %%tmm7 \n\t" + "tilestored %%tmm7, 0(%%r12,%%r15,4) \n\t" + ::: "memory", "tmm0", "tmm6", "tmm7"); +} diff --git a/clang/test/CodeGen/X86/avx-builtins.c b/clang/test/CodeGen/X86/avx-builtins.c index 9d6c1897f540d3841e3f38cfc2e796f612d1e98a..4e56204c8ad40fa1cdcde3a5eb04707939fbfdf6 100644 --- a/clang/test/CodeGen/X86/avx-builtins.c +++ b/clang/test/CodeGen/X86/avx-builtins.c @@ -11,6 +11,7 @@ #include +#include "builtin_test_helpers.h" // NOTE: This should match the tests in llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll @@ -1740,18 +1741,21 @@ __m256d test_mm256_setzero_pd(void) { // CHECK: store <4 x double> zeroinitializer return _mm256_setzero_pd(); } +TEST_CONSTEXPR(match_m256d(_mm256_setzero_pd(), +0.0, +0.0, +0.0, +0.0)); __m256 test_mm256_setzero_ps(void) { // CHECK-LABEL: test_mm256_setzero_ps // CHECK: store <8 x float> zeroinitializer return _mm256_setzero_ps(); } +TEST_CONSTEXPR(match_m256(_mm256_setzero_ps(), +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f)); __m256i test_mm256_setzero_si256(void) { // CHECK-LABEL: test_mm256_setzero_si256 // CHECK: store <4 x i64> zeroinitializer return _mm256_setzero_si256(); } +TEST_CONSTEXPR(match_m256i(_mm256_setzero_si256(), 0, 0, 0, 0)); __m256d test_mm256_shuffle_pd(__m256d A, __m256d B) { // CHECK-LABEL: test_mm256_shuffle_pd @@ -2097,19 +2101,3 @@ float test_mm256_cvtss_f32(__m256 __a) // CHECK: extractelement <8 x float> %{{.*}}, i32 0 return _mm256_cvtss_f32(__a); } - -// Test constexpr handling. -#if defined(__cplusplus) && (__cplusplus >= 201103L) - -void test_constexpr() { - constexpr __m256d v_mm256_setzero_pd = _mm256_setzero_pd(); - static_assert(v_mm256_setzero_pd[0] == +0.0 && v_mm256_setzero_pd[1] == +0.0 && v_mm256_setzero_pd[2] == +0.0 && v_mm256_setzero_pd[3] == +0.0); - - constexpr __m256 v_mm256_setzero_ps = _mm256_setzero_ps(); - static_assert(v_mm256_setzero_ps[0] == +0.0f && v_mm256_setzero_ps[1] == +0.0f && v_mm256_setzero_ps[2] == +0.0f && v_mm256_setzero_ps[3] == +0.0f && v_mm256_setzero_ps[4] == +0.0f && v_mm256_setzero_ps[5] == +0.0f && v_mm256_setzero_ps[6] == +0.0f && v_mm256_setzero_ps[7] == +0.0f); - - constexpr __m256i v_mm256_setzero_si256 = _mm256_setzero_si256(); - static_assert(v_mm256_setzero_si256[0] == 0x0000000000000000ULL && v_mm256_setzero_si256[1] == 0x0000000000000000ULL && v_mm256_setzero_si256[2] == 0x0000000000000000ULL && v_mm256_setzero_si256[3] == 0x0000000000000000ULL); -} - -#endif diff --git a/clang/test/CodeGen/X86/avx512f-builtins.c b/clang/test/CodeGen/X86/avx512f-builtins.c index 0b4f778a0637ab715adb37b89ac9e4c3d70e7f05..372790a8cd668be0aedb25ed9999bd56bc61e0b5 100644 --- a/clang/test/CodeGen/X86/avx512f-builtins.c +++ b/clang/test/CodeGen/X86/avx512f-builtins.c @@ -4,6 +4,7 @@ // RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -fms-extensions -fms-compatibility -ffreestanding %s -triple=x86_64-windows-msvc -target-feature +avx512f -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s #include +#include "builtin_test_helpers.h" __m512d test_mm512_sqrt_pd(__m512d a) { @@ -10615,13 +10616,13 @@ __m128 test_mm_maskz_cvtsd_ss(__mmask8 __U, __m128 __A, __m128d __B) { return _mm_maskz_cvtsd_ss(__U, __A, __B); } - __m512i test_mm512_setzero_epi32(void) { // CHECK-LABEL: test_mm512_setzero_epi32 // CHECK: zeroinitializer return _mm512_setzero_epi32(); } +TEST_CONSTEXPR(match_m512i(_mm512_setzero_epi32(), 0, 0, 0, 0, 0, 0, 0, 0)); __m512 test_mm512_setzero(void) { @@ -10629,6 +10630,7 @@ __m512 test_mm512_setzero(void) // CHECK: zeroinitializer return _mm512_setzero(); } +TEST_CONSTEXPR(match_m512(_mm512_setzero(), +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f)); __m512i test_mm512_setzero_si512(void) { @@ -10636,6 +10638,7 @@ __m512i test_mm512_setzero_si512(void) // CHECK: zeroinitializer return _mm512_setzero_si512(); } +TEST_CONSTEXPR(match_m512i(_mm512_setzero_si512(), 0, 0, 0, 0, 0, 0, 0, 0)); __m512 test_mm512_setzero_ps(void) { @@ -10643,6 +10646,7 @@ __m512 test_mm512_setzero_ps(void) // CHECK: zeroinitializer return _mm512_setzero_ps(); } +TEST_CONSTEXPR(match_m512(_mm512_setzero_ps(), +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f, +0.0f)); __m512d test_mm512_setzero_pd(void) { @@ -10650,6 +10654,7 @@ __m512d test_mm512_setzero_pd(void) // CHECK: zeroinitializer return _mm512_setzero_pd(); } +TEST_CONSTEXPR(match_m512d(_mm512_setzero_pd(), 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0)); __mmask16 test_mm512_int2mask(int __a) { @@ -10880,25 +10885,3 @@ void test_mm512_mask_i32loscatter_epi64(void *__addr, __mmask8 __mask, __m512i _ // CHECK: @llvm.x86.avx512.mask.scatter.dpq.512 _mm512_mask_i32loscatter_epi64(__addr, __mask, __index, __v1, 2); } - -// Test constexpr handling. -#if defined(__cplusplus) && (__cplusplus >= 201103L) - -void test_constexpr() { - constexpr __m512 v_mm512_setzero = _mm512_setzero(); - static_assert(v_mm512_setzero[0] == +0.0f && v_mm512_setzero[1] == +0.0f && v_mm512_setzero[2] == +0.0f && v_mm512_setzero[3] == +0.0f && v_mm512_setzero[4] == +0.0f && v_mm512_setzero[5] == +0.0f && v_mm512_setzero[6] == +0.0f && v_mm512_setzero[7] == +0.0f && v_mm512_setzero[8] == +0.0f && v_mm512_setzero[9] == +0.0f && v_mm512_setzero[10] == +0.0f && v_mm512_setzero[11] == +0.0f && v_mm512_setzero[12] == +0.0f && v_mm512_setzero[13] == +0.0f && v_mm512_setzero[14] == +0.0f && v_mm512_setzero[15] == +0.0f); - - constexpr __m512 v_mm512_setzero_ps = _mm512_setzero_ps(); - static_assert(v_mm512_setzero_ps[0] == +0.0f && v_mm512_setzero_ps[1] == +0.0f && v_mm512_setzero_ps[2] == +0.0f && v_mm512_setzero_ps[3] == +0.0f && v_mm512_setzero_ps[4] == +0.0f && v_mm512_setzero_ps[5] == +0.0f && v_mm512_setzero_ps[6] == +0.0f && v_mm512_setzero_ps[7] == +0.0f && v_mm512_setzero_ps[8] == +0.0f && v_mm512_setzero_ps[9] == +0.0f && v_mm512_setzero_ps[10] == +0.0f && v_mm512_setzero_ps[11] == +0.0f && v_mm512_setzero_ps[12] == +0.0f && v_mm512_setzero_ps[13] == +0.0f && v_mm512_setzero_ps[14] == +0.0f && v_mm512_setzero_ps[15] == +0.0f); - - constexpr __m512d v_mm512_setzero_pd = _mm512_setzero_pd(); - static_assert(v_mm512_setzero_pd[0] == +0.0 && v_mm512_setzero_pd[1] == +0.0 && v_mm512_setzero_pd[2] == +0.0 && v_mm512_setzero_pd[3] == +0.0 && v_mm512_setzero_pd[4] == +0.0 && v_mm512_setzero_pd[5] == +0.0 && v_mm512_setzero_pd[6] == +0.0 && v_mm512_setzero_pd[7] == +0.0); - - constexpr __m512i v_mm512_setzero_si512 = _mm512_setzero_si512(); - static_assert(v_mm512_setzero_si512[0] == 0x0000000000000000ULL && v_mm512_setzero_si512[1] == 0x0000000000000000ULL && v_mm512_setzero_si512[2] == 0x0000000000000000ULL && v_mm512_setzero_si512[3] == 0x0000000000000000ULL && v_mm512_setzero_si512[4] == 0x0000000000000000ULL && v_mm512_setzero_si512[5] == 0x0000000000000000ULL && v_mm512_setzero_si512[6] == 0x0000000000000000ULL && v_mm512_setzero_si512[7] == 0x0000000000000000ULL); - - constexpr __m512i v_mm512_setzero_epi32 = _mm512_setzero_epi32(); - static_assert(v_mm512_setzero_epi32[0] == 0x0000000000000000ULL && v_mm512_setzero_epi32[1] == 0x0000000000000000ULL && v_mm512_setzero_epi32[2] == 0x0000000000000000ULL && v_mm512_setzero_epi32[3] == 0x0000000000000000ULL && v_mm512_setzero_epi32[4] == 0x0000000000000000ULL && v_mm512_setzero_epi32[5] == 0x0000000000000000ULL && v_mm512_setzero_epi32[6] == 0x0000000000000000ULL && v_mm512_setzero_epi32[7] == 0x0000000000000000ULL); -} - -#endif diff --git a/clang/test/CodeGen/X86/builtin_test_helpers.h b/clang/test/CodeGen/X86/builtin_test_helpers.h index 043b6ecbc69f18fc1d82ae6302927f4c55fea718..01800db33afbb9b95a717c8f00a97cdaf5807ba6 100644 --- a/clang/test/CodeGen/X86/builtin_test_helpers.h +++ b/clang/test/CodeGen/X86/builtin_test_helpers.h @@ -4,16 +4,59 @@ #if defined(__cplusplus) && (__cplusplus >= 201103L) -constexpr bool match_m128(__m128 v, float x, float y, float z, float w) { - return v[0] == x && v[1] == y && v[2] == z && v[3] == w; +constexpr bool match_m128(__m128 v, float a, float b, float c, float d) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d; } -constexpr bool match_m128d(__m128d v, double x, double y) { - return v[0] == x && v[1] == y; +constexpr bool match_m128d(__m128d v, double a, double b) { + return v[0] == a && v[1] == b; } -constexpr bool match_m128i(__m128i v, unsigned long long x, unsigned long long y) { - return v[0] == x && v[1] == y; +constexpr bool match_m128i(__m128i v, unsigned long long a, unsigned long long b) { + return v[0] == a && v[1] == b; +} + +constexpr bool match_v2di(__m128i v, long long a, long long b) { + return v[0] == a && v[1] == b; +} + +constexpr bool match_v4si(__m128i _v, int a, int b, int c, int d) { + __v4si v = (__v4si)_v; + return v[0] == a && v[1] == b && v[2] == c && v[3] == d; +} + +constexpr bool match_v8hi(__m128i _v, short a, short b, short c, short d, short e, short f, short g, short h) { + __v8hi v = (__v8hi)_v; + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h; +} + +constexpr bool match_v16qi(__m128i _v, char a, char b, char c, char d, char e, char f, char g, char h, char i, char j, char k, char l, char m, char n, char o, char p) { + __v16qi v = (__v16qi)_v; + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h && v[8] == i && v[9] == j && v[10] == k && v[11] == l && v[12] == m && v[13] == n && v[14] == o && v[15] == p; +} + +constexpr bool match_m256(__m256 v, float a, float b, float c, float d, float e, float f, float g, float h) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h; +} + +constexpr bool match_m256d(__m256d v, double a, double b, double c, double d) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d; +} + +constexpr bool match_m256i(__m256i v, unsigned long long a, unsigned long long b, unsigned long long c, unsigned long long d) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d; +} + +constexpr bool match_m512(__m512 v, float a, float b, float c, float d, float e, float f, float g, float h, float i, float j, float k, float l, float m, float n, float o, float p) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h && v[8] == i && v[9] == j && v[10] == k && v[11] == l && v[12] == m && v[13] == n && v[14] == o && v[15] == p; +} + +constexpr bool match_m512d(__m512d v, double a, double b, double c, double d, double e, double f, double g, double h) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h; +} + +constexpr bool match_m512i(__m512i v, unsigned long long a, unsigned long long b, unsigned long long c, unsigned long long d, unsigned long long e, unsigned long long f, unsigned long long g, unsigned long long h) { + return v[0] == a && v[1] == b && v[2] == c && v[3] == d && v[4] == e && v[5] == f && v[6] == g && v[7] == h; } #define TEST_CONSTEXPR(...) static_assert(__VA_ARGS__) @@ -22,4 +65,4 @@ constexpr bool match_m128i(__m128i v, unsigned long long x, unsigned long long y #define TEST_CONSTEXPR(...) -#endif \ No newline at end of file +#endif diff --git a/clang/test/CodeGen/X86/sse2-builtins.c b/clang/test/CodeGen/X86/sse2-builtins.c index 4287d3d4b5ec4eb283cabd6a3fa7d633d35b7b2a..c4493a49120543a47c1ca572698d97fb649c79e7 100644 --- a/clang/test/CodeGen/X86/sse2-builtins.c +++ b/clang/test/CodeGen/X86/sse2-builtins.c @@ -32,12 +32,14 @@ __m128i test_mm_add_epi32(__m128i A, __m128i B) { // CHECK: add <4 x i32> return _mm_add_epi32(A, B); } +TEST_CONSTEXPR(match_v4si(_mm_add_epi32((__m128i)(__v4si){+1, -2, +3, -4}, (__m128i)(__v4si){-10, +8, +6, -4}), -9, +6, +9, -8)); __m128i test_mm_add_epi64(__m128i A, __m128i B) { // CHECK-LABEL: test_mm_add_epi64 // CHECK: add <2 x i64> return _mm_add_epi64(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_add_epi64((__m128i)(__v2di){+5, -3}, (__m128i)(__v2di){-9, +8}), -4, +5)); __m128d test_mm_add_pd(__m128d A, __m128d B) { // CHECK-LABEL: test_mm_add_pd @@ -1011,6 +1013,7 @@ __m128i test_mm_set_epi8(char A, char B, char C, char D, // CHECK: insertelement <16 x i8> %{{.*}}, i8 %{{.*}}, i32 15 return _mm_set_epi8(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P); } +TEST_CONSTEXPR(match_v16qi(_mm_set_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)); __m128i test_mm_set_epi16(short A, short B, short C, short D, short E, short F, short G, short H) { @@ -1025,6 +1028,7 @@ __m128i test_mm_set_epi16(short A, short B, short C, short D, // CHECK: insertelement <8 x i16> %{{.*}}, i16 %{{.*}}, i32 7 return _mm_set_epi16(A, B, C, D, E, F, G, H); } +TEST_CONSTEXPR(match_v8hi(_mm_set_epi16(0, -1, -2, -3, -4, -5, -6, -7), -7, -6, -5, -4, -3, -2, -1, 0)); __m128i test_mm_set_epi32(int A, int B, int C, int D) { // CHECK-LABEL: test_mm_set_epi32 @@ -1034,6 +1038,7 @@ __m128i test_mm_set_epi32(int A, int B, int C, int D) { // CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i32 3 return _mm_set_epi32(A, B, C, D); } +TEST_CONSTEXPR(match_v4si(_mm_set_epi32(1, -3, 5, -7), -7, 5, -3, 1)); __m128i test_mm_set_epi64(__m64 A, __m64 B) { // CHECK-LABEL: test_mm_set_epi64 @@ -1041,6 +1046,7 @@ __m128i test_mm_set_epi64(__m64 A, __m64 B) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_set_epi64(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_set_epi64((__m64){-1}, (__m64){42}), 42, -1)); __m128i test_mm_set_epi64x(long long A, long long B) { // CHECK-LABEL: test_mm_set_epi64x @@ -1048,6 +1054,7 @@ __m128i test_mm_set_epi64x(long long A, long long B) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_set_epi64x(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_set_epi64x(100, -1000), -1000, 100)); __m128d test_mm_set_pd(double A, double B) { // CHECK-LABEL: test_mm_set_pd @@ -1093,6 +1100,7 @@ __m128i test_mm_set1_epi8(char A) { // CHECK: insertelement <16 x i8> %{{.*}}, i8 %{{.*}}, i32 15 return _mm_set1_epi8(A); } +TEST_CONSTEXPR(match_v16qi(_mm_set1_epi8(99), 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99)); __m128i test_mm_set1_epi16(short A) { // CHECK-LABEL: test_mm_set1_epi16 @@ -1106,6 +1114,7 @@ __m128i test_mm_set1_epi16(short A) { // CHECK: insertelement <8 x i16> %{{.*}}, i16 %{{.*}}, i32 7 return _mm_set1_epi16(A); } +TEST_CONSTEXPR(match_v8hi(_mm_set1_epi16(-128), -128, -128, -128, -128, -128, -128, -128, -128)); __m128i test_mm_set1_epi32(int A) { // CHECK-LABEL: test_mm_set1_epi32 @@ -1115,6 +1124,7 @@ __m128i test_mm_set1_epi32(int A) { // CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i32 3 return _mm_set1_epi32(A); } +TEST_CONSTEXPR(match_v4si(_mm_set1_epi32(55), 55, 55, 55, 55)); __m128i test_mm_set1_epi64(__m64 A) { // CHECK-LABEL: test_mm_set1_epi64 @@ -1122,6 +1132,7 @@ __m128i test_mm_set1_epi64(__m64 A) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_set1_epi64(A); } +TEST_CONSTEXPR(match_v2di(_mm_set1_epi64((__m64){-65535}), -65535, -65535)); __m128i test_mm_set1_epi64x(long long A) { // CHECK-LABEL: test_mm_set1_epi64x @@ -1129,6 +1140,7 @@ __m128i test_mm_set1_epi64x(long long A) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_set1_epi64x(A); } +TEST_CONSTEXPR(match_v2di(_mm_set1_epi64x(65536), 65536, 65536)); __m128d test_mm_set1_pd(double A) { // CHECK-LABEL: test_mm_set1_pd @@ -1161,6 +1173,7 @@ __m128i test_mm_setr_epi8(char A, char B, char C, char D, // CHECK: insertelement <16 x i8> %{{.*}}, i8 %{{.*}}, i32 15 return _mm_setr_epi8(A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P); } +TEST_CONSTEXPR(match_v16qi(_mm_setr_epi8(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15), 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)); __m128i test_mm_setr_epi16(short A, short B, short C, short D, short E, short F, short G, short H) { @@ -1175,6 +1188,7 @@ __m128i test_mm_setr_epi16(short A, short B, short C, short D, // CHECK: insertelement <8 x i16> %{{.*}}, i16 %{{.*}}, i32 7 return _mm_setr_epi16(A, B, C, D, E, F, G, H); } +TEST_CONSTEXPR(match_v8hi(_mm_setr_epi16(0, -1, -2, -3, -4, -5, -6, -7), 0, -1, -2, -3, -4, -5, -6, -7)); __m128i test_mm_setr_epi32(int A, int B, int C, int D) { // CHECK-LABEL: test_mm_setr_epi32 @@ -1184,6 +1198,7 @@ __m128i test_mm_setr_epi32(int A, int B, int C, int D) { // CHECK: insertelement <4 x i32> %{{.*}}, i32 %{{.*}}, i32 3 return _mm_setr_epi32(A, B, C, D); } +TEST_CONSTEXPR(match_v4si(_mm_setr_epi32(1, -3, 5, -7), 1, -3, 5, -7)); __m128i test_mm_setr_epi64(__m64 A, __m64 B) { // CHECK-LABEL: test_mm_setr_epi64 @@ -1191,6 +1206,7 @@ __m128i test_mm_setr_epi64(__m64 A, __m64 B) { // CHECK: insertelement <2 x i64> %{{.*}}, i64 %{{.*}}, i32 1 return _mm_setr_epi64(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_setr_epi64((__m64){-1}, (__m64){42}), -1, 42)); __m128d test_mm_setr_pd(double A, double B) { // CHECK-LABEL: test_mm_setr_pd @@ -1634,12 +1650,14 @@ __m128i test_mm_sub_epi32(__m128i A, __m128i B) { // CHECK: sub <4 x i32> return _mm_sub_epi32(A, B); } +TEST_CONSTEXPR(match_v4si(_mm_sub_epi32((__m128i)(__v4si){+1, -2, +3, -4}, (__m128i)(__v4si){-10, +8, +6, -4}), +11, -10, -3, 0)); __m128i test_mm_sub_epi64(__m128i A, __m128i B) { // CHECK-LABEL: test_mm_sub_epi64 // CHECK: sub <2 x i64> return _mm_sub_epi64(A, B); } +TEST_CONSTEXPR(match_v2di(_mm_sub_epi64((__m128i)(__v2di){+5, -3}, (__m128i)(__v2di){-9, +8}), +14, -11)); __m128d test_mm_sub_pd(__m128d A, __m128d B) { // CHECK-LABEL: test_mm_sub_pd diff --git a/clang/test/CodeGen/aarch64-cpu-supports-target.c b/clang/test/CodeGen/aarch64-cpu-supports-target.c index 5186cab92a921d782cb25940dc74d9becd1d4de4..e3a75e9a1fc7d397b2f486b9c991f366f9904f13 100644 --- a/clang/test/CodeGen/aarch64-cpu-supports-target.c +++ b/clang/test/CodeGen/aarch64-cpu-supports-target.c @@ -9,9 +9,9 @@ int check_all_feature() { return 3; else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts+dgh")) return 4; - else if (__builtin_cpu_supports("i8mm+bf16+ebf16+rpres+sve+sve-bf16")) + else if (__builtin_cpu_supports("i8mm+bf16+ebf16+rpres+sve")) return 5; - else if (__builtin_cpu_supports("sve-ebf16+sve-i8mm+f32mm+f64mm")) + else if (__builtin_cpu_supports("sve+ebf16+i8mm+f32mm+f64mm")) return 6; else if (__builtin_cpu_supports("sve2+sve2-aes+sve2-pmull128")) return 7; diff --git a/clang/test/CodeGen/aarch64-fmv-dependencies.c b/clang/test/CodeGen/aarch64-fmv-dependencies.c index 6d230007f91ff9570ab945e7861c0fe390f8852d..db6be423b99f788e8f31ded67c881a33af563a43 100644 --- a/clang/test/CodeGen/aarch64-fmv-dependencies.c +++ b/clang/test/CodeGen/aarch64-fmv-dependencies.c @@ -135,15 +135,6 @@ __attribute__((target_version("ssbs"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msve() #[[sve:[0-9]+]] { __attribute__((target_version("sve"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Msve-bf16() #[[sve_bf16_ebf16:[0-9]+]] { -__attribute__((target_version("sve-bf16"))) int fmv(void) { return 0; } - -// CHECK: define dso_local i32 @fmv._Msve-ebf16() #[[sve_bf16_ebf16:[0-9]+]] { -__attribute__((target_version("sve-ebf16"))) int fmv(void) { return 0; } - -// CHECK: define dso_local i32 @fmv._Msve-i8mm() #[[sve_i8mm:[0-9]+]] { -__attribute__((target_version("sve-i8mm"))) int fmv(void) { return 0; } - // CHECK: define dso_local i32 @fmv._Msve2() #[[sve2:[0-9]+]] { __attribute__((target_version("sve2"))) int fmv(void) { return 0; } @@ -209,8 +200,6 @@ int caller() { // CHECK: attributes #[[sme2]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a" // CHECK: attributes #[[ssbs]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a" // CHECK: attributes #[[sve]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" -// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" -// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a" // CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a" // CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a" // CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a" diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c index dc0cc429abffd1899d1f8dfd253d3d741e119551..cd09e05b25e4cd8371fc45d64b38c8b4bfcf9f6b 100644 --- a/clang/test/CodeGen/attr-target-version.c +++ b/clang/test/CodeGen/attr-target-version.c @@ -27,11 +27,11 @@ int foo() { inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; } inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; } inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; } -inline int __attribute__((target_version("dit+sve-ebf16"))) fmv_inline(void) { return 8; } +inline int __attribute__((target_version("dit+ebf16"))) fmv_inline(void) { return 8; } inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; } inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; } inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; } -inline int __attribute__((target_version("sve+sve-bf16"))) fmv_inline(void) { return 4; } +inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; } inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; } inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; } inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; } @@ -680,7 +680,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMsve-ebf16 +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMebf16 // CHECK-SAME: () #[[ATTR28:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 8 @@ -708,7 +708,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // // CHECK: Function Attrs: noinline nounwind optnone -// CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsveMsve-bf16 +// CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve // CHECK-SAME: () #[[ATTR32:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 4 @@ -837,20 +837,20 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3 // CHECK: resolver_else12: // CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 4295098368 -// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 4295098368 +// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1207959552 +// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1207959552 // CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] // CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] // CHECK: resolver_return13: -// CHECK-NEXT: ret ptr @fmv_inline._MditMsve-ebf16 +// CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve // CHECK: resolver_else14: // CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 -// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 3221225472 -// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 3221225472 +// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 268566528 +// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 268566528 // CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] // CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] // CHECK: resolver_return15: -// CHECK-NEXT: ret ptr @fmv_inline._MsveMsve-bf16 +// CHECK-NEXT: ret ptr @fmv_inline._MditMebf16 // CHECK: resolver_else16: // CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 // CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971520 diff --git a/clang/test/CodeGen/pgo-cold-function-coverage.c b/clang/test/CodeGen/pgo-cold-function-coverage.c index fd1e1e7e14cda567ac5663eb7f08b06d65eed7b7..3003cdc3e15e02c6d6eebac3c6a50066a51914ca 100644 --- a/clang/test/CodeGen/pgo-cold-function-coverage.c +++ b/clang/test/CodeGen/pgo-cold-function-coverage.c @@ -1,7 +1,7 @@ // Test -fprofile-generate-cold-function-coverage // RUN: rm -rf %t && split-file %s %t -// RUN: %clang -O2 -fprofile-generate-cold-function-coverage=/xxx/yyy/ -fprofile-sample-accurate -fprofile-sample-use=%t/pgo-cold-func.prof -S -emit-llvm -o - %t/pgo-cold-func.c | FileCheck %s +// RUN: %clang --target=x86_64 -O2 -fprofile-generate-cold-function-coverage=/xxx/yyy/ -fprofile-sample-accurate -fprofile-sample-use=%t/pgo-cold-func.prof -S -emit-llvm -o - %t/pgo-cold-func.c | FileCheck %s // CHECK: @__llvm_profile_filename = {{.*}} c"/xxx/yyy/default_%m.profraw\00" diff --git a/clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl b/clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl deleted file mode 100644 index e1e047485e4df01b13680cd9b50242f614882e45..0000000000000000000000000000000000000000 --- a/clang/test/CodeGenHLSL/builtins/RWBuffer-annotations.hlsl +++ /dev/null @@ -1,24 +0,0 @@ -// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s - -RWBuffer Buffer1; -RWBuffer > BufferArray[4]; - -RWBuffer Buffer2 : register(u3); -RWBuffer > BufferArray2[4] : register(u4); - -RWBuffer Buffer3 : register(u3, space1); -RWBuffer > BufferArray3[4] : register(u4, space1); - - - -[numthreads(1,1,1)] -void main() { -} - -// CHECK: !hlsl.uavs = !{![[Single:[0-9]+]], ![[Array:[0-9]+]], ![[SingleAllocated:[0-9]+]], ![[ArrayAllocated:[0-9]+]], ![[SingleSpace:[0-9]+]], ![[ArraySpace:[0-9]+]]} -// CHECK-DAG: ![[Single]] = !{ptr @Buffer1, i32 10, i32 9, i1 false, i32 -1, i32 0} -// CHECK-DAG: ![[Array]] = !{ptr @BufferArray, i32 10, i32 9, i1 false, i32 -1, i32 0} -// CHECK-DAG: ![[SingleAllocated]] = !{ptr @Buffer2, i32 10, i32 9, i1 false, i32 3, i32 0} -// CHECK-DAG: ![[ArrayAllocated]] = !{ptr @BufferArray2, i32 10, i32 9, i1 false, i32 4, i32 0} -// CHECK-DAG: ![[SingleSpace]] = !{ptr @Buffer3, i32 10, i32 9, i1 false, i32 3, i32 1} -// CHECK-DAG: ![[ArraySpace]] = !{ptr @BufferArray3, i32 10, i32 9, i1 false, i32 4, i32 1} diff --git a/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl b/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl index fa81b53fd9bddcb1215fb4e971c77326f69bd8be..16120a44a9e4d2a28b38d9cbb80a61ce3a4b4195 100644 --- a/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl +++ b/clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl @@ -54,17 +54,3 @@ void main(int GI : SV_GroupIndex) { BufF16x2[GI] = 0; BufF32x3[GI] = 0; } - -// CHECK: !{{[0-9]+}} = !{ptr @BufI16, i32 10, i32 2, -// CHECK: !{{[0-9]+}} = !{ptr @BufU16, i32 10, i32 3, -// CHECK: !{{[0-9]+}} = !{ptr @BufI32, i32 10, i32 4, -// CHECK: !{{[0-9]+}} = !{ptr @BufU32, i32 10, i32 5, -// CHECK: !{{[0-9]+}} = !{ptr @BufI64, i32 10, i32 6, -// CHECK: !{{[0-9]+}} = !{ptr @BufU64, i32 10, i32 7, -// CHECK: !{{[0-9]+}} = !{ptr @BufF16, i32 10, i32 8, -// CHECK: !{{[0-9]+}} = !{ptr @BufF32, i32 10, i32 9, -// CHECK: !{{[0-9]+}} = !{ptr @BufF64, i32 10, i32 10, -// CHECK: !{{[0-9]+}} = !{ptr @BufI16x4, i32 10, i32 2, -// CHECK: !{{[0-9]+}} = !{ptr @BufU32x3, i32 10, i32 5, -// CHECK: !{{[0-9]+}} = !{ptr @BufF16x2, i32 10, i32 8, -// CHECK: !{{[0-9]+}} = !{ptr @BufF32x3, i32 10, i32 9, diff --git a/clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl b/clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl index 727f416cde57fd6aa2d9e37be865770ad642982a..71b5b7a75fa431bd67796f482e0b2a07aa616841 100644 --- a/clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl +++ b/clang/test/CodeGenHLSL/builtins/RWStructuredBuffer-elementtype.hlsl @@ -54,17 +54,3 @@ void main(int GI : SV_GroupIndex) { BufF16x2[GI] = 0; BufF32x3[GI] = 0; } - -// CHECK: !{{[0-9]+}} = !{ptr @BufI16, i32 10, i32 2, -// CHECK: !{{[0-9]+}} = !{ptr @BufU16, i32 10, i32 3, -// CHECK: !{{[0-9]+}} = !{ptr @BufI32, i32 10, i32 4, -// CHECK: !{{[0-9]+}} = !{ptr @BufU32, i32 10, i32 5, -// CHECK: !{{[0-9]+}} = !{ptr @BufI64, i32 10, i32 6, -// CHECK: !{{[0-9]+}} = !{ptr @BufU64, i32 10, i32 7, -// CHECK: !{{[0-9]+}} = !{ptr @BufF16, i32 10, i32 8, -// CHECK: !{{[0-9]+}} = !{ptr @BufF32, i32 10, i32 9, -// CHECK: !{{[0-9]+}} = !{ptr @BufF64, i32 10, i32 10, -// CHECK: !{{[0-9]+}} = !{ptr @BufI16x4, i32 10, i32 2, -// CHECK: !{{[0-9]+}} = !{ptr @BufU32x3, i32 10, i32 5, -// CHECK: !{{[0-9]+}} = !{ptr @BufF16x2, i32 10, i32 8, -// CHECK: !{{[0-9]+}} = !{ptr @BufF32x3, i32 10, i32 9, diff --git a/clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl b/clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl deleted file mode 100644 index 5155f12902597979aa5eed62e4b5dc5a1ea30762..0000000000000000000000000000000000000000 --- a/clang/test/CodeGenHLSL/builtins/RasterizerOrderedBuffer-annotations.hlsl +++ /dev/null @@ -1,20 +0,0 @@ -// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-pixel -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s - -RasterizerOrderedBuffer Buffer1; -RasterizerOrderedBuffer > BufferArray[4]; - -RasterizerOrderedBuffer Buffer2 : register(u3); -RasterizerOrderedBuffer > BufferArray2[4] : register(u4); - -RasterizerOrderedBuffer Buffer3 : register(u3, space1); -RasterizerOrderedBuffer > BufferArray3[4] : register(u4, space1); - -void main() {} - -// CHECK: !hlsl.uavs = !{![[Single:[0-9]+]], ![[Array:[0-9]+]], ![[SingleAllocated:[0-9]+]], ![[ArrayAllocated:[0-9]+]], ![[SingleSpace:[0-9]+]], ![[ArraySpace:[0-9]+]]} -// CHECK-DAG: ![[Single]] = !{ptr @Buffer1, i32 10, i32 9, i1 true, i32 -1, i32 0} -// CHECK-DAG: ![[Array]] = !{ptr @BufferArray, i32 10, i32 9, i1 true, i32 -1, i32 0} -// CHECK-DAG: ![[SingleAllocated]] = !{ptr @Buffer2, i32 10, i32 9, i1 true, i32 3, i32 0} -// CHECK-DAG: ![[ArrayAllocated]] = !{ptr @BufferArray2, i32 10, i32 9, i1 true, i32 4, i32 0} -// CHECK-DAG: ![[SingleSpace]] = !{ptr @Buffer3, i32 10, i32 9, i1 true, i32 3, i32 1} -// CHECK-DAG: ![[ArraySpace]] = !{ptr @BufferArray3, i32 10, i32 9, i1 true, i32 4, i32 1} diff --git a/clang/test/CodeGenHLSL/builtins/StructuredBuffer-annotations.hlsl b/clang/test/CodeGenHLSL/builtins/StructuredBuffer-annotations.hlsl deleted file mode 100644 index a88ea774f33201595148ab0f79b20cb20b14432f..0000000000000000000000000000000000000000 --- a/clang/test/CodeGenHLSL/builtins/StructuredBuffer-annotations.hlsl +++ /dev/null @@ -1,22 +0,0 @@ -// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-compute -x hlsl -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s - -StructuredBuffer Buffer1; -StructuredBuffer > BufferArray[4]; - -StructuredBuffer Buffer2 : register(t3); -StructuredBuffer > BufferArray2[4] : register(t4); - -StructuredBuffer Buffer3 : register(t3, space1); -StructuredBuffer > BufferArray3[4] : register(t4, space1); - -[numthreads(1,1,1)] -void main() { -} - -// CHECK: !hlsl.srvs = !{![[Single:[0-9]+]], ![[Array:[0-9]+]], ![[SingleAllocated:[0-9]+]], ![[ArrayAllocated:[0-9]+]], ![[SingleSpace:[0-9]+]], ![[ArraySpace:[0-9]+]]} -// CHECK-DAG: ![[Single]] = !{ptr @Buffer1, i32 10, i32 9, i1 false, i32 -1, i32 0} -// CHECK-DAG: ![[Array]] = !{ptr @BufferArray, i32 10, i32 9, i1 false, i32 -1, i32 0} -// CHECK-DAG: ![[SingleAllocated]] = !{ptr @Buffer2, i32 10, i32 9, i1 false, i32 3, i32 0} -// CHECK-DAG: ![[ArrayAllocated]] = !{ptr @BufferArray2, i32 10, i32 9, i1 false, i32 4, i32 0} -// CHECK-DAG: ![[SingleSpace]] = !{ptr @Buffer3, i32 10, i32 9, i1 false, i32 3, i32 1} -// CHECK-DAG: ![[ArraySpace]] = !{ptr @BufferArray3, i32 10, i32 9, i1 false, i32 4, i32 1} diff --git a/clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl b/clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl index 4c30119498ff1a2616f81c8c6816235bf9e8d23d..205e13b4de3946d239aef00894aa0e8b0ae2b3e1 100644 --- a/clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl +++ b/clang/test/CodeGenHLSL/builtins/StructuredBuffer-elementtype.hlsl @@ -54,17 +54,3 @@ void main(int GI : SV_GroupIndex) { half2 v12 = BufF16x2[GI]; float3 v13 = BufF32x3[GI]; } - -// CHECK: !{{[0-9]+}} = !{ptr @BufI16, i32 10, i32 2, -// CHECK: !{{[0-9]+}} = !{ptr @BufU16, i32 10, i32 3, -// CHECK: !{{[0-9]+}} = !{ptr @BufI32, i32 10, i32 4, -// CHECK: !{{[0-9]+}} = !{ptr @BufU32, i32 10, i32 5, -// CHECK: !{{[0-9]+}} = !{ptr @BufI64, i32 10, i32 6, -// CHECK: !{{[0-9]+}} = !{ptr @BufU64, i32 10, i32 7, -// CHECK: !{{[0-9]+}} = !{ptr @BufF16, i32 10, i32 8, -// CHECK: !{{[0-9]+}} = !{ptr @BufF32, i32 10, i32 9, -// CHECK: !{{[0-9]+}} = !{ptr @BufF64, i32 10, i32 10, -// CHECK: !{{[0-9]+}} = !{ptr @BufI16x4, i32 10, i32 2, -// CHECK: !{{[0-9]+}} = !{ptr @BufU32x3, i32 10, i32 5, -// CHECK: !{{[0-9]+}} = !{ptr @BufF16x2, i32 10, i32 8, -// CHECK: !{{[0-9]+}} = !{ptr @BufF32x3, i32 10, i32 9, diff --git a/clang/test/CodeGenHLSL/builtins/countbits.hlsl b/clang/test/CodeGenHLSL/builtins/countbits.hlsl index 8dfe977bfae6269fa41e067849594a6a2d174c24..218d8dcd10f8d707a946388d577efc5ec218e47a 100644 --- a/clang/test/CodeGenHLSL/builtins/countbits.hlsl +++ b/clang/test/CodeGenHLSL/builtins/countbits.hlsl @@ -4,26 +4,37 @@ #ifdef __HLSL_ENABLE_16_BIT // CHECK-LABEL: test_countbits_ushort -// CHECK: call i16 @llvm.ctpop.i16 -uint16_t test_countbits_ushort(uint16_t p0) +// CHECK: [[A:%.*]] = call i16 @llvm.ctpop.i16 +// CHECK-NEXT: zext i16 [[A]] to i32 +uint test_countbits_ushort(uint16_t p0) +{ + return countbits(p0); +} +// CHECK-LABEL: test_countbits_short +// CHECK: [[A:%.*]] = call i16 @llvm.ctpop.i16 +// CHECK-NEXT: sext i16 [[A]] to i32 +uint test_countbits_short(int16_t p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_ushort2 -// CHECK: call <2 x i16> @llvm.ctpop.v2i16 -uint16_t2 test_countbits_ushort2(uint16_t2 p0) +// CHECK: [[A:%.*]] = call <2 x i16> @llvm.ctpop.v2i16 +// CHECK-NEXT: zext <2 x i16> [[A]] to <2 x i32> +uint2 test_countbits_ushort2(uint16_t2 p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_ushort3 -// CHECK: call <3 x i16> @llvm.ctpop.v3i16 -uint16_t3 test_countbits_ushort3(uint16_t3 p0) +// CHECK: [[A:%.*]] = call <3 x i16> @llvm.ctpop.v3i16 +// CHECK-NEXT: zext <3 x i16> [[A]] to <3 x i32> +uint3 test_countbits_ushort3(uint16_t3 p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_ushort4 -// CHECK: call <4 x i16> @llvm.ctpop.v4i16 -uint16_t4 test_countbits_ushort4(uint16_t4 p0) +// CHECK: [[A:%.*]] = call <4 x i16> @llvm.ctpop.v4i16 +// CHECK-NEXT: zext <4 x i16> [[A]] to <4 x i32> +uint4 test_countbits_ushort4(uint16_t4 p0) { return countbits(p0); } @@ -31,7 +42,13 @@ uint16_t4 test_countbits_ushort4(uint16_t4 p0) // CHECK-LABEL: test_countbits_uint // CHECK: call i32 @llvm.ctpop.i32 -int test_countbits_uint(uint p0) +uint test_countbits_uint(uint p0) +{ + return countbits(p0); +} +// CHECK-LABEL: test_countbits_int +// CHECK: call i32 @llvm.ctpop.i32 +uint test_countbits_int(int p0) { return countbits(p0); } @@ -55,26 +72,37 @@ uint4 test_countbits_uint4(uint4 p0) } // CHECK-LABEL: test_countbits_long -// CHECK: call i64 @llvm.ctpop.i64 -uint64_t test_countbits_long(uint64_t p0) +// CHECK: [[A:%.*]] = call i64 @llvm.ctpop.i64 +// CHECK-NEXT: trunc i64 [[A]] to i32 +uint test_countbits_long(uint64_t p0) +{ + return countbits(p0); +} +// CHECK-LABEL: test_countbits_slong +// CHECK: [[A:%.*]] = call i64 @llvm.ctpop.i64 +// CHECK-NEXT: trunc i64 [[A]] to i32 +uint test_countbits_slong(int64_t p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_long2 -// CHECK: call <2 x i64> @llvm.ctpop.v2i64 -uint64_t2 test_countbits_long2(uint64_t2 p0) +// CHECK: [[A:%.*]] = call <2 x i64> @llvm.ctpop.v2i64 +// CHECK-NEXT: trunc <2 x i64> [[A]] to <2 x i32> +uint2 test_countbits_long2(uint64_t2 p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_long3 -// CHECK: call <3 x i64> @llvm.ctpop.v3i64 -uint64_t3 test_countbits_long3(uint64_t3 p0) +// CHECK: [[A:%.*]] = call <3 x i64> @llvm.ctpop.v3i64 +// CHECK-NEXT: trunc <3 x i64> [[A]] to <3 x i32> +uint3 test_countbits_long3(uint64_t3 p0) { return countbits(p0); } // CHECK-LABEL: test_countbits_long4 -// CHECK: call <4 x i64> @llvm.ctpop.v4i64 -uint64_t4 test_countbits_long4(uint64_t4 p0) +// CHECK: [[A:%.*]] = call <4 x i64> @llvm.ctpop.v4i64 +// CHECK-NEXT: trunc <4 x i64> [[A]] to <4 x i32> +uint4 test_countbits_long4(uint64_t4 p0) { return countbits(p0); } diff --git a/clang/test/CodeGenHLSL/cbuf.hlsl b/clang/test/CodeGenHLSL/cbuf.hlsl index 78d9768b22fc8750df22be664084433ab89c02d6..3f9d4514967dd2a7f987602b1aea85652e97eb04 100644 --- a/clang/test/CodeGenHLSL/cbuf.hlsl +++ b/clang/test/CodeGenHLSL/cbuf.hlsl @@ -23,6 +23,4 @@ float foo() { } // CHECK: !hlsl.cbufs = !{![[CBMD:[0-9]+]]} -// CHECK: !hlsl.srvs = !{![[TBMD:[0-9]+]]} // CHECK: ![[CBMD]] = !{ptr @[[CB]], i32 13, i32 0, i1 false, i32 0, i32 2} -// CHECK: ![[TBMD]] = !{ptr @[[TB]], i32 15, i32 0, i1 false, i32 2, i32 1} diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a57 b/clang/test/Driver/Inputs/cpunative/cortex-a57 deleted file mode 100644 index e1903012ab79ccda38c861ce11b9f32c1a8892aa..0000000000000000000000000000000000000000 --- a/clang/test/Driver/Inputs/cpunative/cortex-a57 +++ /dev/null @@ -1,8 +0,0 @@ -processor : 0 -BogoMIPS : 200.00 -Features : fp asimd evtstrm crc32 cpuid -CPU implementer : 0x41 -CPU architecture: 8 -CPU variant : 0x1 -CPU part : 0xd07 -CPU revision : 1 diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a72 b/clang/test/Driver/Inputs/cpunative/cortex-a72 deleted file mode 100644 index 7aed4a6fa732369477adbbbb0f0c1271df6651ba..0000000000000000000000000000000000000000 --- a/clang/test/Driver/Inputs/cpunative/cortex-a72 +++ /dev/null @@ -1,8 +0,0 @@ -processor : 0 -BogoMIPS : 250.00 -Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid asimdrdm -CPU implementer : 0x41 -CPU architecture: 8 -CPU variant : 0x0 -CPU part : 0xd08 -CPU revision : 2 diff --git a/clang/test/Driver/Inputs/cpunative/cortex-a76 b/clang/test/Driver/Inputs/cpunative/cortex-a76 deleted file mode 100644 index 21822cfcec60b0e6e7316f69875c9d6d88d28242..0000000000000000000000000000000000000000 --- a/clang/test/Driver/Inputs/cpunative/cortex-a76 +++ /dev/null @@ -1,8 +0,0 @@ -processor : 0 -BogoMIPS : 500.00 -Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics cpuid asimdrdm ssbs jscvt fcma -CPU implementer : 0x41 -CPU architecture: 8 -CPU variant : 0x1 -CPU part : 0xd0b -CPU revision : 2 diff --git a/clang/test/Driver/Inputs/cpunative/neoverse-n1 b/clang/test/Driver/Inputs/cpunative/neoverse-n1 deleted file mode 100644 index 571e8840b09f08a82665ab1e1997fc7afde117cf..0000000000000000000000000000000000000000 --- a/clang/test/Driver/Inputs/cpunative/neoverse-n1 +++ /dev/null @@ -1,8 +0,0 @@ -processor : 0 -BogoMIPS : 50.00 -Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs -CPU implementer : 0x41 -CPU architecture: 8 -CPU variant : 0x3 -CPU part : 0xd0c -CPU revision : 1 diff --git a/clang/test/Driver/Inputs/cpunative/neoverse-v2 b/clang/test/Driver/Inputs/cpunative/neoverse-v2 deleted file mode 100644 index c3c8433415d7a08c60057c01a91bafceba4923e7..0000000000000000000000000000000000000000 --- a/clang/test/Driver/Inputs/cpunative/neoverse-v2 +++ /dev/null @@ -1,8 +0,0 @@ -processor : 0 -BogoMIPS : 2000.00 -Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp sve2 sveaes svepmull svebitperm svesha3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti -CPU implementer : 0x41 -CPU architecture: 8 -CPU variant : 0x0 -CPU part : 0xd4f -CPU revision : 0 diff --git a/clang/test/Driver/XRay/xray-shared.cpp b/clang/test/Driver/XRay/xray-shared.cpp index 215854e1fc7cefecca5ed5bcccc38bde03bed46c..e331fefed1e0c9f40401158fea2fbeabef56d3c6 100644 --- a/clang/test/Driver/XRay/xray-shared.cpp +++ b/clang/test/Driver/XRay/xray-shared.cpp @@ -1,6 +1,5 @@ // RUN: %clang -### --target=x86_64-unknown-linux-gnu -fPIC -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s // RUN: %clang -### --target=x86_64-unknown-linux-gnu -fpic -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s // RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fno-PIC -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR-PIC // RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fno-pic -fxray-instrument -fxray-shared -c %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR-PIC diff --git a/clang/test/Driver/aarch64-mcpu-native.c b/clang/test/Driver/aarch64-mcpu-native.c deleted file mode 100644 index f1d0ba76ad79c49afe834644308562478d6dce53..0000000000000000000000000000000000000000 --- a/clang/test/Driver/aarch64-mcpu-native.c +++ /dev/null @@ -1,138 +0,0 @@ -// REQUIRES: aarch64-registered-target -// RUN: export LLVM_CPUINFO=%S/Inputs/cpunative/neoverse-v2 -// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --check-prefix=CHECK-FEAT-NV2 --implicit-check-not=FEAT_ %s - -// CHECK-FEAT-NV2: Extensions enabled for the given AArch64 target -// CHECK-FEAT-NV2-EMPTY: -// CHECK-FEAT-NV2: Architecture Feature(s) Description -// CHECK-FEAT-NV2: FEAT_AES, FEAT_PMULL Enable AES support -// CHECK-FEAT-NV2: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension -// CHECK-FEAT-NV2: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-FEAT-NV2: FEAT_BF16 Enable BFloat16 Extension -// CHECK-FEAT-NV2: FEAT_BTI Enable Branch Target Identification -// CHECK-FEAT-NV2: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets -// CHECK-FEAT-NV2: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions -// CHECK-FEAT-NV2: FEAT_CSV2_2 Enable architectural speculation restriction -// CHECK-FEAT-NV2: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions -// CHECK-FEAT-NV2: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence -// CHECK-FEAT-NV2: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence -// CHECK-FEAT-NV2: FEAT_DotProd Enable dot product support -// CHECK-FEAT-NV2: FEAT_ETE Enable Embedded Trace Extension -// CHECK-FEAT-NV2: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support -// CHECK-FEAT-NV2: FEAT_FHM Enable FP16 FML instructions -// CHECK-FEAT-NV2: FEAT_FP Enable Armv8.0-A Floating Point Extensions -// CHECK-FEAT-NV2: FEAT_FP16 Enable half-precision floating-point data processing -// CHECK-FEAT-NV2: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int -// CHECK-FEAT-NV2: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions -// CHECK-FEAT-NV2: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons -// CHECK-FEAT-NV2: FEAT_I8MM Enable Matrix Multiply Int8 Extension -// CHECK-FEAT-NV2: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions -// CHECK-FEAT-NV2: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension -// CHECK-FEAT-NV2: FEAT_LRCPC Enable support for RCPC extension -// CHECK-FEAT-NV2: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets -// CHECK-FEAT-NV2: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions -// CHECK-FEAT-NV2: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules -// CHECK-FEAT-NV2: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension -// CHECK-FEAT-NV2: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension -// CHECK-FEAT-NV2: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement -// CHECK-FEAT-NV2: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension -// CHECK-FEAT-NV2: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants -// CHECK-FEAT-NV2: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension -// CHECK-FEAT-NV2: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension -// CHECK-FEAT-NV2: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions -// CHECK-FEAT-NV2: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions -// CHECK-FEAT-NV2: FEAT_RNG Enable Random Number generation instructions -// CHECK-FEAT-NV2: FEAT_SB Enable Armv8.5-A Speculation Barrier -// CHECK-FEAT-NV2: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension -// CHECK-FEAT-NV2: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support -// CHECK-FEAT-NV2: FEAT_SPE Enable Statistical Profiling extension -// CHECK-FEAT-NV2: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions -// CHECK-FEAT-NV2: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit -// CHECK-FEAT-NV2: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions -// CHECK-FEAT-NV2: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions -// CHECK-FEAT-NV2: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions -// CHECK-FEAT-NV2: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions -// CHECK-FEAT-NV2: FEAT_TRBE Enable Trace Buffer Extension -// CHECK-FEAT-NV2: FEAT_TRF Enable Armv8.4-A Trace extension -// CHECK-FEAT-NV2: FEAT_UAO Enable Armv8.2-A UAO PState -// CHECK-FEAT-NV2: FEAT_VHE Enable Armv8.1-A Virtual Host extension - -// RUN: export LLVM_CPUINFO=%S/Inputs/cpunative/neoverse-n1 -// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --check-prefix=CHECK-FEAT-NN1 --implicit-check-not=FEAT_ %s - -// CHECK-FEAT-NN1: Extensions enabled for the given AArch64 target -// CHECK-FEAT-NN1-EMPTY: -// CHECK-FEAT-NN1: Architecture Feature(s) Description -// CHECK-FEAT-NN1: FEAT_AES, FEAT_PMULL Enable AES support -// CHECK-FEAT-NN1: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-FEAT-NN1: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions -// CHECK-FEAT-NN1: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence -// CHECK-FEAT-NN1: FEAT_DotProd Enable dot product support -// CHECK-FEAT-NN1: FEAT_FP Enable Armv8.0-A Floating Point Extensions -// CHECK-FEAT-NN1: FEAT_FP16 Enable half-precision floating-point data processing -// CHECK-FEAT-NN1: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension -// CHECK-FEAT-NN1: FEAT_LRCPC Enable support for RCPC extension -// CHECK-FEAT-NN1: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions -// CHECK-FEAT-NN1: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension -// CHECK-FEAT-NN1: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants -// CHECK-FEAT-NN1: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension -// CHECK-FEAT-NN1: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions -// CHECK-FEAT-NN1: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions -// CHECK-FEAT-NN1: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support -// CHECK-FEAT-NN1: FEAT_SPE Enable Statistical Profiling extension -// CHECK-FEAT-NN1: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit -// CHECK-FEAT-NN1: FEAT_UAO Enable Armv8.2-A UAO PState -// CHECK-FEAT-NN1: FEAT_VHE Enable Armv8.1-A Virtual Host extension - - -// RUN: export LLVM_CPUINFO=%S/Inputs/cpunative/cortex-a57 -// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --check-prefix=CHECK-FEAT-CA57 --implicit-check-not=FEAT_ %s - -// CHECK-FEAT-CA57: Extensions enabled for the given AArch64 target -// CHECK-FEAT-CA57-EMPTY: -// CHECK-FEAT-CA57: Architecture Feature(s) Description -// CHECK-FEAT-CA57: FEAT_AES, FEAT_PMULL Enable AES support -// CHECK-FEAT-CA57: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-FEAT-CA57: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions -// CHECK-FEAT-CA57: FEAT_FP Enable Armv8.0-A Floating Point Extensions -// CHECK-FEAT-CA57: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension -// CHECK-FEAT-CA57: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support - -// RUN: export LLVM_CPUINFO=%S/Inputs/cpunative/cortex-a72 -// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --check-prefix=CHECK-FEAT-CA72 --implicit-check-not=FEAT_ %s - -// CHECK-FEAT-CA72: Extensions enabled for the given AArch64 target -// CHECK-EMPTY: -// CHECK-FEAT-CA72: Architecture Feature(s) Description -// CHECK-FEAT-CA72: FEAT_AES, FEAT_PMULL Enable AES support -// CHECK-FEAT-CA72: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-FEAT-CA72: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions -// CHECK-FEAT-CA72: FEAT_FP Enable Armv8.0-A Floating Point Extensions -// CHECK-FEAT-CA72: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension -// CHECK-FEAT-CA72: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support - -// RUN: export LLVM_CPUINFO=%S/Inputs/cpunative/cortex-a76 -// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=native | FileCheck --strict-whitespace --check-prefix=CHECK-FEAT-CA76 --implicit-check-not=FEAT_ %s - -// CHECK-FEAT-CA76: Extensions enabled for the given AArch64 target -// CHECK-FEAT-CA76-EMPTY: -// CHECK-FEAT-CA76: Architecture Feature(s) Description -// CHECK-FEAT-CA76: FEAT_AES, FEAT_PMULL Enable AES support -// CHECK-FEAT-CA76: FEAT_AdvSIMD Enable Advanced SIMD instructions -// CHECK-FEAT-CA76: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions -// CHECK-FEAT-CA76: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence -// CHECK-FEAT-CA76: FEAT_DotProd Enable dot product support -// CHECK-FEAT-CA76: FEAT_FP Enable Armv8.0-A Floating Point Extensions -// CHECK-FEAT-CA76: FEAT_FP16 Enable half-precision floating-point data processing -// CHECK-FEAT-CA76: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension -// CHECK-FEAT-CA76: FEAT_LRCPC Enable support for RCPC extension -// CHECK-FEAT-CA76: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions -// CHECK-FEAT-CA76: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension -// CHECK-FEAT-CA76: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants -// CHECK-FEAT-CA76: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension -// CHECK-FEAT-CA76: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions -// CHECK-FEAT-CA76: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions -// CHECK-FEAT-CA76: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support -// CHECK-FEAT-CA76: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit -// CHECK-FEAT-CA76: FEAT_UAO Enable Armv8.2-A UAO PState -// CHECK-FEAT-CA76: FEAT_VHE Enable Armv8.1-A Virtual Host extension diff --git a/clang/test/Driver/nvlink-wrapper.c b/clang/test/Driver/nvlink-wrapper.c index 2b0993caee4248200f8296a4327d99d94d40286d..79f4a6641732f79eb21f5f3d3eea403a5f9bf8c1 100644 --- a/clang/test/Driver/nvlink-wrapper.c +++ b/clang/test/Driver/nvlink-wrapper.c @@ -21,12 +21,13 @@ int bar() { } #else extern int y; -int __attribute__((visibility("hidden"))) x = 999; +extern int x; int baz() { return y + x; } #endif // Create various inputs to test basic linking and LTO capabilities. Creating a // CUDA binary requires access to the `ptxas` executable, so we just use x64. +// RUN: %clang -cc1 %s -triple nvptx64-nvidia-cuda -emit-llvm-bc -o %t.o // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -DX -o %t-x.o // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -DY -o %t-y.o // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -DZ -o %t-z.o @@ -36,6 +37,7 @@ int baz() { return y + x; } // RUN: llvm-ar rcs %t-y.a %t-y.o // RUN: llvm-ar rcs %t-z.a %t-z.o // RUN: llvm-ar rcs %t-w.a %t-w.o +// RUN: llvm-ar rcs %t-u.a %t-u.o // // Check that we forward any unrecognized argument to 'nvlink'. @@ -49,11 +51,16 @@ int baz() { return y + x; } // `libx.a` and `liby.a` because extern weak symbols do not extract and `libz.a` // is not used at all. // -// RUN: clang-nvlink-wrapper --dry-run %t-x.a %t-u.o %t-y.a %t-z.a %t-w.a \ +// RUN: clang-nvlink-wrapper --dry-run %t-x.a %t-u.a %t-y.a %t-z.a %t-w.a %t.o \ // RUN: -arch sm_52 -o a.out 2>&1 | FileCheck %s --check-prefix=LINK // LINK: nvlink{{.*}} -arch sm_52 -o a.out [[INPUT:.+]].cubin {{.*}}-x-{{.*}}.cubin{{.*}}-y-{{.*}}.cubin -// RUN: %clang -cc1 %s -triple nvptx64-nvidia-cuda -emit-llvm-bc -o %t.o +// +// Same as above but we use '--undefined' to forcibly extract 'libz.a' +// +// RUN: clang-nvlink-wrapper --dry-run %t-x.a %t-u.a %t-y.a %t-z.a %t-w.a %t.o \ +// RUN: -u z -arch sm_52 -o a.out 2>&1 | FileCheck %s --check-prefix=LINK +// UNDEFINED: nvlink{{.*}} -arch sm_52 -o a.out [[INPUT:.+]].cubin {{.*}}-x-{{.*}}.cubin{{.*}}-y-{{.*}}.cubin{{.*}}-z-{{.*}}.cubin // // Check that the LTO interface works and properly preserves symbols used in a diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index 2b4d19422874cfb38f09d906aba3974703f3d3b7..67e09d0e69ebc3ebb035cba0c3429b1e0400990f 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -147,6 +147,7 @@ // RVA23U64: "-target-feature" "+zvbb" // RVA23U64: "-target-feature" "+zvfhmin" // RVA23U64: "-target-feature" "+zvkt" +// RVA23U64: "-target-feature" "+supm" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 \ // RUN: | FileCheck -check-prefix=RVA23S64 %s @@ -186,6 +187,7 @@ // RVA23S64: "-target-feature" "+zvbb" // RVA23S64: "-target-feature" "+zvfhmin" // RVA23S64: "-target-feature" "+zvkt" +// RVA23S64: "-target-feature" "+sha" // RVA23S64: "-target-feature" "+shcounterenw" // RVA23S64: "-target-feature" "+shgatpa" // RVA23S64: "-target-feature" "+shtvala" @@ -201,6 +203,7 @@ // RVA23S64: "-target-feature" "+sstvala" // RVA23S64: "-target-feature" "+sstvecd" // RVA23S64: "-target-feature" "+ssu64xl" +// RVA23S64: "-target-feature" "+supm" // RVA23S64: "-target-feature" "+svade" // RVA23S64: "-target-feature" "+svbare" // RVA23S64: "-target-feature" "+svinval" diff --git a/clang/test/Modules/static-initializer.cppm b/clang/test/Modules/static-initializer.cppm new file mode 100644 index 0000000000000000000000000000000000000000..10d4854ee67fa6241e7ee8008dcf229334b0572d --- /dev/null +++ b/clang/test/Modules/static-initializer.cppm @@ -0,0 +1,18 @@ +// RUN: rm -rf %t +// RUN: mkdir -p %t +// RUN: split-file %s %t +// +// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++20 %t/a.cppm -emit-module-interface -o %t/a.pcm +// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++20 %t/a.cpp -fmodule-file=a=%t/a.pcm -emit-llvm -o - | FileCheck %t/a.cpp + +//--- a.cppm +export module a; +int func(); +static int a = func(); + +//--- a.cpp +import a; + +// CHECK-NOT: internal global +// CHECK-NOT: __cxx_global_var_init + diff --git a/clang/test/Sema/attr-target-clones-aarch64.c b/clang/test/Sema/attr-target-clones-aarch64.c index a723c5965c5bcdeda6a6445b902de71f0da015c0..e101fefd2b67c4b062d162b081caa1765bc4fcc2 100644 --- a/clang/test/Sema/attr-target-clones-aarch64.c +++ b/clang/test/Sema/attr-target-clones-aarch64.c @@ -7,7 +7,7 @@ void __attribute__((target_clones("default+sha3"))) warn1(void); // expected-error@+2 {{'target_clones' and 'target_version' attributes are not compatible}} // expected-note@+1 {{conflicting attribute is here}} -void __attribute__((target_version("sve-bf16"), target_clones("sme+memtag"))) not_compat(void); +void __attribute__((target_version("sve"), target_clones("sme+memtag"))) not_compat(void); int redecl(void); int __attribute__((target_clones("frintts", "simd+fp", "default"))) redecl(void) { return 1; } @@ -78,4 +78,4 @@ int useage(void) { // expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}} int __attribute__((target_clones("sve2-sha3+ssbs", "sm4"))) mv_after_use(void) { return 1; } // expected-error@+1 {{'main' cannot be a multiversioned function}} -int __attribute__((target_clones("sve-i8mm"))) main() { return 1; } +int __attribute__((target_clones("i8mm"))) main() { return 1; } diff --git a/clang/test/SemaCXX/attr-target-version.cpp b/clang/test/SemaCXX/attr-target-version.cpp index 2c85f9735a87b1683185fa5eea4ba29e374c274a..c0a645713b218715b481183a3e9bfbfea75a5ee3 100644 --- a/clang/test/SemaCXX/attr-target-version.cpp +++ b/clang/test/SemaCXX/attr-target-version.cpp @@ -49,7 +49,7 @@ double __attribute__((target_version("rcpc"))) diff_type1(void); auto __attribute__((target_version("rcpc2"))) diff_type2(void) -> int { return 1; } //expected-error@+1 {{multiversioned function declaration has a different return type}} -auto __attribute__((target_version("sve-bf16"))) diff_type2(void) -> long { return (long)1; } +auto __attribute__((target_version("bf16"))) diff_type2(void) -> long { return (long)1; } int __attribute__((target_version("fp16fml"))) diff_type3(void) noexcept(false) { return 1; } //expected-error@+2 {{exception specification in declaration does not match previous declaration}} @@ -75,7 +75,7 @@ auto __attribute__((target_version("dpb2"))) ret3(void) -> int { return 1; } class Cls { __attribute__((target_version("rng"))) Cls(); // expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support constructors}} - __attribute__((target_version("sve-i8mm"))) ~Cls(); + __attribute__((target_version("i8mm"))) ~Cls(); // expected-error@-1 {{attribute 'target_version' multiversioned functions do not yet support destructors}} Cls &__attribute__((target_version("f32mm"))) operator=(const Cls &) = default; diff --git a/clang/test/SemaCXX/constexpr-string.cpp b/clang/test/SemaCXX/constexpr-string.cpp index 5448365489a514d102cdf69720503f052b183887..c456740ef7551f70c930ce64f5782ac351232896 100644 --- a/clang/test/SemaCXX/constexpr-string.cpp +++ b/clang/test/SemaCXX/constexpr-string.cpp @@ -670,8 +670,6 @@ namespace MemcpyEtc { constexpr bool test_address_of_incomplete_struct_type() { // expected-error {{never produces a constant}} struct Incomplete; extern Incomplete x, y; - // expected-warning@+2 {{first argument in call to '__builtin_memcpy' is a pointer to non-trivially copyable type 'Incomplete'}} - // expected-note@+1 {{explicitly cast the pointer to silence this warning}} __builtin_memcpy(&x, &x, 4); // expected-note@-1 2{{cannot constant evaluate 'memcpy' between objects of incomplete type 'Incomplete'}} return true; diff --git a/clang/test/SemaCXX/gh113468.cpp b/clang/test/SemaCXX/gh113468.cpp new file mode 100644 index 0000000000000000000000000000000000000000..94551986b0efaab908eb564af5cd08a3255b1a3f --- /dev/null +++ b/clang/test/SemaCXX/gh113468.cpp @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -std=c++20 -fsyntax-only -verify %s + +constexpr int expr() { + if (({ + int f; + f = 0; + if (f) + break; // expected-error {{'break' statement not in loop or switch statement}} + })) + return 2; + return 1; +} diff --git a/clang/test/SemaCXX/warn-memaccess.cpp b/clang/test/SemaCXX/warn-memaccess.cpp index b4b7f6a6905b23e92e50eeb888fcd67bbc271b39..070b44891a91aa4e4aca48c851cfb68f8e96eb08 100644 --- a/clang/test/SemaCXX/warn-memaccess.cpp +++ b/clang/test/SemaCXX/warn-memaccess.cpp @@ -7,12 +7,17 @@ extern "C" void *memcpy(void *s1, const void *s2, unsigned n); class TriviallyCopyable {}; class NonTriviallyCopyable { NonTriviallyCopyable(const NonTriviallyCopyable&);}; +struct Incomplete; void test_bzero(TriviallyCopyable* tc, - NonTriviallyCopyable *ntc) { + NonTriviallyCopyable *ntc, + Incomplete* i) { // OK bzero(tc, sizeof(*tc)); + // OK + bzero(i, 10); + // expected-warning@+2{{first argument in call to 'bzero' is a pointer to non-trivially copyable type 'NonTriviallyCopyable'}} // expected-note@+1{{explicitly cast the pointer to silence this warning}} bzero(ntc, sizeof(*ntc)); @@ -22,10 +27,14 @@ void test_bzero(TriviallyCopyable* tc, } void test_memset(TriviallyCopyable* tc, - NonTriviallyCopyable *ntc) { + NonTriviallyCopyable *ntc, + Incomplete* i) { // OK memset(tc, 0, sizeof(*tc)); + // OK + memset(i, 0, 10); + // expected-warning@+2{{first argument in call to 'memset' is a pointer to non-trivially copyable type 'NonTriviallyCopyable'}} // expected-note@+1{{explicitly cast the pointer to silence this warning}} memset(ntc, 0, sizeof(*ntc)); @@ -36,10 +45,14 @@ void test_memset(TriviallyCopyable* tc, void test_memcpy(TriviallyCopyable* tc0, TriviallyCopyable* tc1, - NonTriviallyCopyable *ntc0, NonTriviallyCopyable *ntc1) { + NonTriviallyCopyable *ntc0, NonTriviallyCopyable *ntc1, + Incomplete *i0, Incomplete *i1) { // OK memcpy(tc0, tc1, sizeof(*tc0)); + // OK + memcpy(i0, i1, 10); + // expected-warning@+2{{first argument in call to 'memcpy' is a pointer to non-trivially copyable type 'NonTriviallyCopyable'}} // expected-note@+1{{explicitly cast the pointer to silence this warning}} memcpy(ntc0, ntc1, sizeof(*ntc0)); @@ -52,10 +65,14 @@ void test_memcpy(TriviallyCopyable* tc0, TriviallyCopyable* tc1, } void test_memmove(TriviallyCopyable* tc0, TriviallyCopyable* tc1, - NonTriviallyCopyable *ntc0, NonTriviallyCopyable *ntc1) { + NonTriviallyCopyable *ntc0, NonTriviallyCopyable *ntc1, + Incomplete *i0, Incomplete *i1) { // OK memmove(tc0, tc1, sizeof(*tc0)); + // OK + memmove(i0, i1, 10); + // expected-warning@+2{{first argument in call to 'memmove' is a pointer to non-trivially copyable type 'NonTriviallyCopyable'}} // expected-note@+1{{explicitly cast the pointer to silence this warning}} memmove(ntc0, ntc1, sizeof(*ntc0)); diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp index bfc34b55c1f66785d627c41a0de888d09cee505c..724d444638b57e7a3e02ea7c844aa05945bcd2c4 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-function-attr.cpp @@ -111,6 +111,37 @@ int testFoldExpression(Vs&&... v) { return (... + v); // expected-warning{{function introduces unsafe buffer manipulation}} } +struct HoldsUnsafeMembers { + HoldsUnsafeMembers() + : FromCtor(3), // expected-warning{{function introduces unsafe buffer manipulation}} + FromCtor2{3} // expected-warning{{function introduces unsafe buffer manipulation}} + {} + + [[clang::unsafe_buffer_usage]] + HoldsUnsafeMembers(int i) + : FromCtor(i), // expected-warning{{function introduces unsafe buffer manipulation}} + FromCtor2{i} // expected-warning{{function introduces unsafe buffer manipulation}} + {} + + HoldsUnsafeMembers(float f) + : HoldsUnsafeMembers(0) {} // expected-warning{{function introduces unsafe buffer manipulation}} + + UnsafeMembers FromCtor; + UnsafeMembers FromCtor2; + UnsafeMembers FromField{3}; // expected-warning 2{{function introduces unsafe buffer manipulation}} +}; + +struct SubclassUnsafeMembers : public UnsafeMembers { + SubclassUnsafeMembers() + : UnsafeMembers(3) // expected-warning{{function introduces unsafe buffer manipulation}} + {} + + [[clang::unsafe_buffer_usage]] + SubclassUnsafeMembers(int i) + : UnsafeMembers(i) // expected-warning{{function introduces unsafe buffer manipulation}} + {} +}; + // https://github.com/llvm/llvm-project/issues/80482 void testClassMembers() { UnsafeMembers(3); // expected-warning{{function introduces unsafe buffer manipulation}} @@ -122,4 +153,95 @@ void testClassMembers() { UnsafeMembers()(); // expected-warning{{function introduces unsafe buffer manipulation}} testFoldExpression(UnsafeMembers(), UnsafeMembers()); + + HoldsUnsafeMembers(); + HoldsUnsafeMembers(3); // expected-warning{{function introduces unsafe buffer manipulation}} + + SubclassUnsafeMembers(); + SubclassUnsafeMembers(3); // expected-warning{{function introduces unsafe buffer manipulation}} +} + +// Not an aggregate, so its constructor is not implicit code and will be +// visited/checked for warnings. +struct NotCalledHoldsUnsafeMembers { + NotCalledHoldsUnsafeMembers() + : FromCtor(3), // expected-warning{{function introduces unsafe buffer manipulation}} + FromCtor2{3} // expected-warning{{function introduces unsafe buffer manipulation}} + {} + + UnsafeMembers FromCtor; + UnsafeMembers FromCtor2; + UnsafeMembers FromField{3}; // expected-warning{{function introduces unsafe buffer manipulation}} +}; + +// An aggregate, so its constructor is implicit code. Since it's not called, it +// is never generated. +struct AggregateUnused { + UnsafeMembers f1; + // While this field would trigger the warning during initialization, since + // it's unused, there's no code generated that does the initialization, so + // no warning. + UnsafeMembers f2{3}; +}; + +struct AggregateExplicitlyInitializedSafe { + UnsafeMembers f1; + // The warning is not fired as the field is always explicltly initialized + // elsewhere. This initializer is never used. + UnsafeMembers f2{3}; +}; + +void testAggregateExplicitlyInitializedSafe() { + AggregateExplicitlyInitializedSafe A{ + .f2 = UnsafeMembers(), // A safe constructor. + }; } + +struct AggregateExplicitlyInitializedUnsafe { + UnsafeMembers f1; + // The warning is not fired as the field is always explicltly initialized + // elsewhere. This initializer is never used. + UnsafeMembers f2{3}; +}; + +void testAggregateExplicitlyInitializedUnsafe() { + AggregateExplicitlyInitializedUnsafe A{ + .f2 = UnsafeMembers(3), // expected-warning{{function introduces unsafe buffer manipulation}} + }; +} + +struct AggregateViaAggregateInit { + UnsafeMembers f1; + // FIXME: A construction of this class does initialize the field through + // this initializer, so it should warn. Ideally it should also point to + // where the site of the construction is in testAggregateViaAggregateInit(). + UnsafeMembers f2{3}; +}; + +void testAggregateViaAggregateInit() { + AggregateViaAggregateInit A{}; +}; + +struct AggregateViaValueInit { + UnsafeMembers f1; + // FIXME: A construction of this class does initialize the field through + // this initializer, so it should warn. Ideally it should also point to + // where the site of the construction is in testAggregateViaValueInit(). + UnsafeMembers f2{3}; +}; + +void testAggregateViaValueInit() { + auto A = AggregateViaValueInit(); +}; + +struct AggregateViaDefaultInit { + UnsafeMembers f1; + // FIXME: A construction of this class does initialize the field through + // this initializer, so it should warn. Ideally it should also point to + // where the site of the construction is in testAggregateViaValueInit(). + UnsafeMembers f2{3}; +}; + +void testAggregateViaDefaultInit() { + AggregateViaDefaultInit A; +}; diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp index e97511593bbd8151fde8c986c4cf3718a071abb8..c138fe088b3ba9724ae5e0f4e1c3e64a0271c69d 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-in-container-span-construct.cpp @@ -157,3 +157,23 @@ namespace test_flag { } } //namespace test_flag + +struct HoldsStdSpanAndInitializedInCtor { + char* Ptr; + unsigned Size; + std::span Span{Ptr, Size}; // no-warning (this code is unreachable) + + HoldsStdSpanAndInitializedInCtor(char* P, unsigned S) + : Span(P, S) // expected-warning{{the two-parameter std::span construction is unsafe as it can introduce mismatch between buffer size and the bound information}} + {} +}; + +struct HoldsStdSpanAndNotInitializedInCtor { + char* Ptr; + unsigned Size; + std::span Span{Ptr, Size}; // expected-warning{{the two-parameter std::span construction is unsafe as it can introduce mismatch between buffer size and the bound information}} + + HoldsStdSpanAndNotInitializedInCtor(char* P, unsigned S) + : Ptr(P), Size(S) + {} +}; diff --git a/clang/test/SemaHLSL/BuiltIns/countbits-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/countbits-errors.hlsl index 8d5f0abb2860f8ea3707b9fa99601cd7b280169b..5704165e1a45053fd7fda1ff175363bc488ec392 100644 --- a/clang/test/SemaHLSL/BuiltIns/countbits-errors.hlsl +++ b/clang/test/SemaHLSL/BuiltIns/countbits-errors.hlsl @@ -1,6 +1,4 @@ -// RUN: %clang_cc1 -finclude-default-header -// -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -// -disable-llvm-passes -verify -verify-ignore-unexpected +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only -disable-llvm-passes -verify -verify-ignore-unexpected double test_int_builtin(double p0) { @@ -9,13 +7,11 @@ double test_int_builtin(double p0) { } double2 test_int_builtin_2(double2 p0) { - return __builtin_elementwise_popcount(p0); - // expected-error@-1 {{1st argument must be a vector of integers - // (was 'double2' (aka 'vector'))}} + return countbits(p0); + // expected-error@-1 {{call to 'countbits' is ambiguous}} } double test_int_builtin_3(float p0) { - return __builtin_elementwise_popcount(p0); - // expected-error@-1 {{1st argument must be a vector of integers - // (was 'float')}} + return countbits(p0); + // expected-error@-1 {{call to 'countbits' is ambiguous}} } diff --git a/clang/tools/clang-format/git-clang-format.bat b/clang/tools/clang-format/git-clang-format.bat index 19c82d8a04132b63c016d1e58da81f4fd264228c..a40276e63c5848bde0144a0677e4279151af362c 100644 --- a/clang/tools/clang-format/git-clang-format.bat +++ b/clang/tools/clang-format/git-clang-format.bat @@ -1 +1 @@ -py -3 "%~pn0" %* +py -3 "%~dpn0" %* diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index 1653904d1afe384146f3c0a9eec195243218ebc5..a5aa649026d8e19091437f10e5a5c8f1b215db21 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -140,9 +140,6 @@ static std::list> TempFiles; /// Codegen flags for LTO backend. static codegen::RegisterCodeGenFlags CodeGenFlags; -/// Global flag to indicate that the LTO pipeline threw an error. -static std::atomic LTOError; - using OffloadingImage = OffloadBinary::OffloadingImage; namespace llvm { @@ -219,33 +216,6 @@ void printCommands(ArrayRef CmdArgs) { exit(EXIT_FAILURE); } -/// Create an extra user-specified \p OffloadFile. -/// TODO: We should find a way to wrap these as libraries instead. -Expected getInputBitcodeLibrary(StringRef Input) { - auto [Device, Path] = StringRef(Input).split('='); - auto [String, Arch] = Device.rsplit('-'); - auto [Kind, Triple] = String.split('-'); - - llvm::ErrorOr> ImageOrError = - llvm::MemoryBuffer::getFileOrSTDIN(Path); - if (std::error_code EC = ImageOrError.getError()) - return createFileError(Path, EC); - - OffloadingImage Image{}; - Image.TheImageKind = IMG_Bitcode; - Image.TheOffloadKind = getOffloadKind(Kind); - Image.StringData["triple"] = Triple; - Image.StringData["arch"] = Arch; - Image.Image = std::move(*ImageOrError); - - std::unique_ptr Binary = - MemoryBuffer::getMemBufferCopy(OffloadBinary::write(Image)); - auto NewBinaryOrErr = OffloadBinary::create(*Binary); - if (!NewBinaryOrErr) - return NewBinaryOrErr.takeError(); - return OffloadFile(std::move(*NewBinaryOrErr), std::move(Binary)); -} - std::string getMainExecutable(const char *Name) { void *Ptr = (void *)(intptr_t)&getMainExecutable; auto COWPath = sys::fs::getMainExecutable(Name, Ptr); @@ -293,12 +263,10 @@ Expected findProgram(StringRef Name, ArrayRef Paths) { return *Path; } -/// We will defer LTO to the target's linker if we are not doing JIT and it is -/// supported by the toolchain. bool linkerSupportsLTO(const ArgList &Args) { llvm::Triple Triple(Args.getLastArgValue(OPT_triple_EQ)); return Triple.isNVPTX() || Triple.isAMDGPU() || - Args.getLastArgValue(OPT_linker_path_EQ).ends_with("ld.lld"); + Args.getLastArgValue(OPT_linker_path_EQ).ends_with("lld"); } /// Returns the hashed value for a constant string. @@ -528,13 +496,11 @@ Expected clang(ArrayRef InputFiles, const ArgList &Args) { }; // Forward all of the `--offload-opt` and similar options to the device. - if (linkerSupportsLTO(Args)) { - CmdArgs.push_back("-flto"); - for (auto &Arg : Args.filtered(OPT_offload_opt_eq_minus, OPT_mllvm)) - CmdArgs.append( - {"-Xlinker", - Args.MakeArgString("--plugin-opt=" + StringRef(Arg->getValue()))}); - } + CmdArgs.push_back("-flto"); + for (auto &Arg : Args.filtered(OPT_offload_opt_eq_minus, OPT_mllvm)) + CmdArgs.append( + {"-Xlinker", + Args.MakeArgString("--plugin-opt=" + StringRef(Arg->getValue()))}); if (!Triple.isNVPTX()) CmdArgs.push_back("-Wl,--no-undefined"); @@ -607,17 +573,6 @@ Expected clang(ArrayRef InputFiles, const ArgList &Args) { for (StringRef Arg : Args.getAllArgValues(OPT_compiler_arg_EQ)) CmdArgs.push_back(Args.MakeArgString(Arg)); - for (StringRef Arg : Args.getAllArgValues(OPT_builtin_bitcode_EQ)) { - if (llvm::Triple(Arg.split('=').first) == Triple) - CmdArgs.append({"-Xclang", "-mlink-builtin-bitcode", "-Xclang", - Args.MakeArgString(Arg.split('=').second)}); - } - - // The OpenMPOpt pass can introduce new calls and is expensive, we do - // not want this when running CodeGen through clang. - if (Args.hasArg(OPT_clang_backend) || Args.hasArg(OPT_builtin_bitcode_EQ)) - CmdArgs.append({"-mllvm", "-openmp-opt-disable"}); - if (Error Err = executeCommands(*ClangPath, CmdArgs)) return std::move(Err); @@ -697,357 +652,6 @@ Expected linkDevice(ArrayRef InputFiles, } } -void diagnosticHandler(const DiagnosticInfo &DI) { - std::string ErrStorage; - raw_string_ostream OS(ErrStorage); - DiagnosticPrinterRawOStream DP(OS); - DI.print(DP); - - switch (DI.getSeverity()) { - case DS_Error: - WithColor::error(errs(), LinkerExecutable) << ErrStorage << "\n"; - LTOError = true; - break; - case DS_Warning: - WithColor::warning(errs(), LinkerExecutable) << ErrStorage << "\n"; - break; - case DS_Note: - WithColor::note(errs(), LinkerExecutable) << ErrStorage << "\n"; - break; - case DS_Remark: - WithColor::remark(errs()) << ErrStorage << "\n"; - break; - } -} - -// Get the list of target features from the input file and unify them such that -// if there are multiple +xxx or -xxx features we only keep the last one. -std::vector getTargetFeatures(ArrayRef InputFiles) { - SmallVector Features; - for (const OffloadFile &File : InputFiles) { - for (auto Arg : llvm::split(File.getBinary()->getString("feature"), ",")) - Features.emplace_back(Arg); - } - - // Only add a feature if it hasn't been seen before starting from the end. - std::vector UnifiedFeatures; - DenseSet UsedFeatures; - for (StringRef Feature : llvm::reverse(Features)) { - if (UsedFeatures.insert(Feature.drop_front()).second) - UnifiedFeatures.push_back(Feature.str()); - } - - return UnifiedFeatures; -} - -template > -std::unique_ptr createLTO( - const ArgList &Args, const std::vector &Features, - ModuleHook Hook = [](size_t, const Module &) { return true; }) { - const llvm::Triple Triple(Args.getLastArgValue(OPT_triple_EQ)); - // We need to remove AMD's target-id from the processor if present. - StringRef TargetID = Args.getLastArgValue(OPT_arch_EQ); - StringRef Arch = clang::getProcessorFromTargetID(Triple, TargetID); - lto::Config Conf; - lto::ThinBackend Backend; - // TODO: Handle index-only thin-LTO - Backend = - lto::createInProcessThinBackend(llvm::heavyweight_hardware_concurrency()); - - Conf.CPU = Arch.str(); - Conf.Options = codegen::InitTargetOptionsFromCodeGenFlags(Triple); - - Conf.RemarksFilename = RemarksFilename; - Conf.RemarksPasses = RemarksPasses; - Conf.RemarksWithHotness = RemarksWithHotness; - Conf.RemarksHotnessThreshold = RemarksHotnessThreshold; - Conf.RemarksFormat = RemarksFormat; - - StringRef OptLevel = Args.getLastArgValue(OPT_opt_level, "O2"); - Conf.MAttrs = Features; - std::optional CGOptLevelOrNone = - CodeGenOpt::parseLevel(OptLevel[1]); - assert(CGOptLevelOrNone && "Invalid optimization level"); - Conf.CGOptLevel = *CGOptLevelOrNone; - Conf.OptLevel = OptLevel[1] - '0'; - Conf.DefaultTriple = Triple.getTriple(); - - // TODO: Should we complain about combining --opt-level and -passes, as opt - // does? That might be too limiting in clang-linker-wrapper, so for now we - // just warn in the help entry for -passes that the default corresponding - // to --opt-level=O? should be included there. The problem is that - // --opt-level produces effects in clang-linker-wrapper beyond what -passes - // appears to be able to achieve, so rejecting the combination of --opt-level - // and -passes would apparently make it impossible to combine those effects - // with a custom pass pipeline. - Conf.OptPipeline = PassPipeline; - Conf.PassPlugins = PassPlugins; - - LTOError = false; - Conf.DiagHandler = diagnosticHandler; - - Conf.PTO.LoopVectorization = Conf.OptLevel > 1; - Conf.PTO.SLPVectorization = Conf.OptLevel > 1; - - if (SaveTemps) { - std::string TempName = (sys::path::filename(ExecutableName) + "." + - Triple.getTriple() + "." + TargetID) - .str(); - Conf.PostInternalizeModuleHook = [=](size_t Task, const Module &M) { - std::string File = - !Task ? TempName + ".postlink.bc" - : TempName + "." + std::to_string(Task) + ".postlink.bc"; - error_code EC; - raw_fd_ostream LinkedBitcode(File, EC, sys::fs::OF_None); - if (EC) - reportError(errorCodeToError(EC)); - WriteBitcodeToFile(M, LinkedBitcode); - return true; - }; - Conf.PreCodeGenModuleHook = [=](size_t Task, const Module &M) { - std::string File = - !Task ? TempName + ".postopt.bc" - : TempName + "." + std::to_string(Task) + ".postopt.bc"; - error_code EC; - raw_fd_ostream LinkedBitcode(File, EC, sys::fs::OF_None); - if (EC) - reportError(errorCodeToError(EC)); - WriteBitcodeToFile(M, LinkedBitcode); - return true; - }; - } - Conf.PostOptModuleHook = Hook; - Conf.CGFileType = (Triple.isNVPTX() || SaveTemps) - ? CodeGenFileType::AssemblyFile - : CodeGenFileType::ObjectFile; - - // TODO: Handle remark files - Conf.HasWholeProgramVisibility = Args.hasArg(OPT_whole_program); - - return std::make_unique(std::move(Conf), Backend); -} - -// Returns true if \p S is valid as a C language identifier and will be given -// `__start_` and `__stop_` symbols. -bool isValidCIdentifier(StringRef S) { - return !S.empty() && (isAlpha(S[0]) || S[0] == '_') && - llvm::all_of(llvm::drop_begin(S), - [](char C) { return C == '_' || isAlnum(C); }); -} - -Error linkBitcodeFiles(SmallVectorImpl &InputFiles, - SmallVectorImpl &OutputFiles, - const ArgList &Args) { - llvm::TimeTraceScope TimeScope("Link bitcode files"); - const llvm::Triple Triple(Args.getLastArgValue(OPT_triple_EQ)); - StringRef Arch = Args.getLastArgValue(OPT_arch_EQ); - - SmallVector BitcodeInputFiles; - DenseSet StrongResolutions; - DenseSet UsedInRegularObj; - DenseSet UsedInSharedLib; - BumpPtrAllocator Alloc; - StringSaver Saver(Alloc); - - // Search for bitcode files in the input and create an LTO input file. If - // it is not a bitcode file, scan its symbol table for symbols we need to - // save. - for (OffloadFile &File : InputFiles) { - MemoryBufferRef Buffer = MemoryBufferRef(File.getBinary()->getImage(), ""); - - file_magic Type = identify_magic(Buffer.getBuffer()); - switch (Type) { - case file_magic::bitcode: { - Expected IRSymtabOrErr = readIRSymtab(Buffer); - if (!IRSymtabOrErr) - return IRSymtabOrErr.takeError(); - - // Check for any strong resolutions we need to preserve. - for (unsigned I = 0; I != IRSymtabOrErr->Mods.size(); ++I) { - for (const auto &Sym : IRSymtabOrErr->TheReader.module_symbols(I)) { - if (!Sym.isFormatSpecific() && Sym.isGlobal() && !Sym.isWeak() && - !Sym.isUndefined()) - StrongResolutions.insert(Saver.save(Sym.Name)); - } - } - BitcodeInputFiles.emplace_back(std::move(File)); - continue; - } - case file_magic::elf_relocatable: - case file_magic::elf_shared_object: { - Expected> ObjFile = - ObjectFile::createObjectFile(Buffer); - if (!ObjFile) - continue; - - for (SymbolRef Sym : (*ObjFile)->symbols()) { - Expected Name = Sym.getName(); - if (!Name) - return Name.takeError(); - - // Record if we've seen these symbols in any object or shared - // libraries. - if ((*ObjFile)->isRelocatableObject()) - UsedInRegularObj.insert(Saver.save(*Name)); - else - UsedInSharedLib.insert(Saver.save(*Name)); - } - continue; - } - default: - continue; - } - } - - if (BitcodeInputFiles.empty()) - return Error::success(); - - // Remove all the bitcode files that we moved from the original input. - llvm::erase_if(InputFiles, [](OffloadFile &F) { return !F.getBinary(); }); - - // LTO Module hook to output bitcode without running the backend. - SmallVector BitcodeOutput; - auto OutputBitcode = [&](size_t, const Module &M) { - auto TempFileOrErr = createOutputFile(sys::path::filename(ExecutableName) + - "-jit-" + Triple.getTriple(), - "bc"); - if (!TempFileOrErr) - reportError(TempFileOrErr.takeError()); - - std::error_code EC; - raw_fd_ostream LinkedBitcode(*TempFileOrErr, EC, sys::fs::OF_None); - if (EC) - reportError(errorCodeToError(EC)); - WriteBitcodeToFile(M, LinkedBitcode); - BitcodeOutput.push_back(*TempFileOrErr); - return false; - }; - - // We assume visibility of the whole program if every input file was - // bitcode. - auto Features = getTargetFeatures(BitcodeInputFiles); - auto LTOBackend = Args.hasArg(OPT_embed_bitcode) || - Args.hasArg(OPT_builtin_bitcode_EQ) || - Args.hasArg(OPT_clang_backend) - ? createLTO(Args, Features, OutputBitcode) - : createLTO(Args, Features); - - // We need to resolve the symbols so the LTO backend knows which symbols - // need to be kept or can be internalized. This is a simplified symbol - // resolution scheme to approximate the full resolution a linker would do. - uint64_t Idx = 0; - DenseSet PrevailingSymbols; - for (auto &BitcodeInput : BitcodeInputFiles) { - // Get a semi-unique buffer identifier for Thin-LTO. - StringRef Identifier = Saver.save( - std::to_string(Idx++) + "." + - BitcodeInput.getBinary()->getMemoryBufferRef().getBufferIdentifier()); - MemoryBufferRef Buffer = - MemoryBufferRef(BitcodeInput.getBinary()->getImage(), Identifier); - Expected> BitcodeFileOrErr = - llvm::lto::InputFile::create(Buffer); - if (!BitcodeFileOrErr) - return BitcodeFileOrErr.takeError(); - - // Save the input file and the buffer associated with its memory. - const auto Symbols = (*BitcodeFileOrErr)->symbols(); - SmallVector Resolutions(Symbols.size()); - size_t Idx = 0; - for (auto &Sym : Symbols) { - lto::SymbolResolution &Res = Resolutions[Idx++]; - - // We will use this as the prevailing symbol definition in LTO unless - // it is undefined or another definition has already been used. - Res.Prevailing = - !Sym.isUndefined() && - !(Sym.isWeak() && StrongResolutions.contains(Sym.getName())) && - PrevailingSymbols.insert(Saver.save(Sym.getName())).second; - - // We need LTO to preseve the following global symbols: - // 1) Symbols used in regular objects. - // 2) Sections that will be given a __start/__stop symbol. - // 3) Prevailing symbols that are needed visible to external - // libraries. - Res.VisibleToRegularObj = - UsedInRegularObj.contains(Sym.getName()) || - isValidCIdentifier(Sym.getSectionName()) || - (Res.Prevailing && - (Sym.getVisibility() != GlobalValue::HiddenVisibility && - !Sym.canBeOmittedFromSymbolTable())); - - // Identify symbols that must be exported dynamically and can be - // referenced by other files. - Res.ExportDynamic = - Sym.getVisibility() != GlobalValue::HiddenVisibility && - (UsedInSharedLib.contains(Sym.getName()) || - !Sym.canBeOmittedFromSymbolTable()); - - // The final definition will reside in this linkage unit if the symbol - // is defined and local to the module. This only checks for bitcode - // files, full assertion will require complete symbol resolution. - Res.FinalDefinitionInLinkageUnit = - Sym.getVisibility() != GlobalValue::DefaultVisibility && - (!Sym.isUndefined() && !Sym.isCommon()); - - // We do not support linker redefined symbols (e.g. --wrap) for device - // image linking, so the symbols will not be changed after LTO. - Res.LinkerRedefined = false; - } - - // Add the bitcode file with its resolved symbols to the LTO job. - if (Error Err = LTOBackend->add(std::move(*BitcodeFileOrErr), Resolutions)) - return Err; - } - - // Run the LTO job to compile the bitcode. - size_t MaxTasks = LTOBackend->getMaxTasks(); - SmallVector Files(MaxTasks); - auto AddStream = - [&](size_t Task, - const Twine &ModuleName) -> std::unique_ptr { - int FD = -1; - auto &TempFile = Files[Task]; - StringRef Extension = (Triple.isNVPTX() || SaveTemps) ? "s" : "o"; - std::string TaskStr = Task ? "." + std::to_string(Task) : ""; - auto TempFileOrErr = - createOutputFile(sys::path::filename(ExecutableName) + "." + - Triple.getTriple() + "." + Arch + TaskStr, - Extension); - if (!TempFileOrErr) - reportError(TempFileOrErr.takeError()); - TempFile = *TempFileOrErr; - if (std::error_code EC = sys::fs::openFileForWrite(TempFile, FD)) - reportError(errorCodeToError(EC)); - return std::make_unique( - std::make_unique(FD, true)); - }; - - if (Error Err = LTOBackend->run(AddStream)) - return Err; - - if (LTOError) - return createStringError("Errors encountered inside the LTO pipeline."); - - // If we are embedding bitcode we only need the intermediate output. - bool SingleOutput = Files.size() == 1; - if (Args.hasArg(OPT_embed_bitcode)) { - if (BitcodeOutput.size() != 1 || !SingleOutput) - return createStringError("Cannot embed bitcode with multiple files."); - OutputFiles.push_back(Args.MakeArgString(BitcodeOutput.front())); - return Error::success(); - } - - // Append the new inputs to the device linker input. If the user requested - // an internalizing link we need to pass the bitcode to clang. - for (StringRef File : - Args.hasArg(OPT_clang_backend) || Args.hasArg(OPT_builtin_bitcode_EQ) - ? BitcodeOutput - : Files) - OutputFiles.push_back(File); - - return Error::success(); -} - Expected writeOffloadFile(const OffloadFile &File) { const OffloadBinary &Binary = *File.getBinary(); @@ -1378,15 +982,8 @@ Expected> linkAndWrapDeviceFiles( if (File.getBinary()->getOffloadKind() != OFK_None) ActiveOffloadKinds.insert(File.getBinary()->getOffloadKind()); - // First link and remove all the input files containing bitcode if - // the target linker does not support it natively. + // Write any remaining device inputs to an output file. SmallVector InputFiles; - if (!linkerSupportsLTO(LinkerArgs)) - if (Error Err = linkBitcodeFiles(Input, InputFiles, LinkerArgs)) - return Err; - - // Write any remaining device inputs to an output file for the - // linker. for (const OffloadFile &File : Input) { auto FileNameOrErr = writeOffloadFile(File); if (!FileNameOrErr) @@ -1394,12 +991,9 @@ Expected> linkAndWrapDeviceFiles( InputFiles.emplace_back(*FileNameOrErr); } + // Link the remaining device files using the device linker. auto OutputOrErr = - !Args.hasArg(OPT_embed_bitcode) || linkerSupportsLTO(LinkerArgs) - ? linkDevice(InputFiles, LinkerArgs, - Args.hasArg(OPT_link_with_clang)) - : InputFiles.front(); - + linkDevice(InputFiles, LinkerArgs, Args.hasArg(OPT_link_with_clang)); if (!OutputOrErr) return OutputOrErr.takeError(); @@ -1782,13 +1376,6 @@ getDeviceInput(const ArgList &Args) { } } - for (StringRef Library : Args.getAllArgValues(OPT_bitcode_library_EQ)) { - auto FileOrErr = getInputBitcodeLibrary(Library); - if (!FileOrErr) - return FileOrErr.takeError(); - InputFiles[*FileOrErr].push_back(std::move(*FileOrErr)); - } - SmallVector> InputsForTarget; for (auto &[ID, Input] : InputFiles) InputsForTarget.emplace_back(std::move(Input)); diff --git a/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td b/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td index 377c37a9da734ea119cf27ded3177b0e20169b58..dfb1205f6fe28495cbd9cf58d1cacb988c883036 100644 --- a/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td +++ b/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td @@ -22,22 +22,12 @@ def host_triple_EQ : Joined<["--"], "host-triple=">, def opt_level : Joined<["--"], "opt-level=">, Flags<[WrapperOnlyOption]>, MetaVarName<"">, HelpText<"Optimization level for LTO">; -def bitcode_library_EQ : Joined<["--"], "bitcode-library=">, - Flags<[WrapperOnlyOption]>, MetaVarName<"--=">, - HelpText<"Extra bitcode library to link">; -def builtin_bitcode_EQ : Joined<["--"], "builtin-bitcode=">, - Flags<[WrapperOnlyOption]>, MetaVarName<"=">, - HelpText<"Perform a special internalizing link on the bitcode file. " - "This is necessary for some vendor libraries to be linked correctly">; def device_linker_args_EQ : Joined<["--"], "device-linker=">, Flags<[WrapperOnlyOption]>, MetaVarName<" or =">, HelpText<"Arguments to pass to the device linker invocation">; def device_compiler_args_EQ : Joined<["--"], "device-compiler=">, Flags<[WrapperOnlyOption]>, MetaVarName<" or =">, HelpText<"Arguments to pass to the device compiler invocation">; -def clang_backend : Flag<["--"], "clang-backend">, - Flags<[WrapperOnlyOption]>, - HelpText<"Run the backend using clang rather than the LTO backend">; def dry_run : Flag<["--"], "dry-run">, Flags<[WrapperOnlyOption]>, HelpText<"Print program arguments without running">; diff --git a/clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp b/clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp index b9767a7a03d0b59e8960736aec7a517d767b1442..bc191afdca739dfd2b7ab91af4d64bb231765d87 100644 --- a/clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp +++ b/clang/tools/clang-nvlink-wrapper/ClangNVLinkWrapper.cpp @@ -250,6 +250,7 @@ struct Symbol { }; Symbol() : File(), Flags(None), UsedInRegularObj(false) {} + Symbol(Symbol::Flags Flags) : File(), Flags(Flags), UsedInRegularObj(true) {} Symbol(MemoryBufferRef File, const irsymtab::Reader::SymbolRef Sym) : File(File), Flags(0), UsedInRegularObj(false) { @@ -535,6 +536,8 @@ Expected> getInput(const ArgList &Args) { bool Extracted = true; StringMap SymTab; + for (auto &Sym : Args.getAllArgValues(OPT_u)) + SymTab[Sym] = Symbol(Symbol::Undefined); SmallVector> LinkerInput; while (Extracted) { Extracted = false; diff --git a/clang/tools/clang-nvlink-wrapper/NVLinkOpts.td b/clang/tools/clang-nvlink-wrapper/NVLinkOpts.td index a80c5937b429923ce275fdaeed037e543d9131bd..6de1a25c14f8be02be7567b6472b67621e7d4781 100644 --- a/clang/tools/clang-nvlink-wrapper/NVLinkOpts.td +++ b/clang/tools/clang-nvlink-wrapper/NVLinkOpts.td @@ -43,11 +43,11 @@ def plugin : JoinedOrSeparate<["--", "-"], "plugin">, Flags<[HelpHidden, WrapperOnlyOption]>; def arch : Separate<["--", "-"], "arch">, - HelpText<"Specify the 'sm_' name of the target architecture.">; + HelpText<"Specify the 'sm_' name of the target architecture">; def : Joined<["--", "-"], "plugin-opt=mcpu=">, Flags<[HelpHidden, WrapperOnlyOption]>, Alias; -def g : Flag<["-"], "g">, HelpText<"Specify that this was a debug compile.">; +def g : Flag<["-"], "g">, HelpText<"Specify that this was a debug compile">; def debug : Flag<["--"], "debug">, Alias; def lto_emit_llvm : Flag<["--"], "lto-emit-llvm">, Flags<[WrapperOnlyOption]>, @@ -55,6 +55,9 @@ def lto_emit_llvm : Flag<["--"], "lto-emit-llvm">, Flags<[WrapperOnlyOption]>, def lto_emit_asm : Flag<["--"], "lto-emit-asm">, Flags<[WrapperOnlyOption]>, HelpText<"Emit assembly code">; +def u : JoinedOrSeparate<["-"], "u">, HelpText<"Force undefined symbol during linking">; +def undefined : JoinedOrSeparate<["--"], "undefined">, Alias; + def O : Joined<["--", "-"], "plugin-opt=O">, Flags<[WrapperOnlyOption]>, MetaVarName<"">, HelpText<"Optimization level for LTO">; diff --git a/clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp b/clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp index d696375547acce84a88b570fdb744a2de35a2202..056b7c7b571ef46780ea79353c161a44303b843e 100644 --- a/clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp +++ b/clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp @@ -3342,6 +3342,45 @@ TEST_P(ASTMatchersTest, declStmt(isInTemplateInstantiation()))); } +TEST_P(ASTMatchersTest, IsInstantiated_MatchesVariableInstantiation) { + if (!GetParam().isCXX14OrLater()) { + return; + } + + EXPECT_TRUE(matches("template int V = 10; void x() { V; }", + varDecl(isInstantiated()))); +} + +TEST_P(ASTMatchersTest, IsInstantiated_NotMatchesVariableDefinition) { + if (!GetParam().isCXX14OrLater()) { + return; + } + + EXPECT_TRUE(notMatches("template int V = 10;", + varDecl(isInstantiated()))); +} + +TEST_P(ASTMatchersTest, + IsInTemplateInstantiation_MatchesVariableInstantiationStmt) { + if (!GetParam().isCXX14OrLater()) { + return; + } + + EXPECT_TRUE(matches( + "template auto V = []() { T i; }; void x() { V(); }", + declStmt(isInTemplateInstantiation()))); +} + +TEST_P(ASTMatchersTest, + IsInTemplateInstantiation_NotMatchesVariableDefinitionStmt) { + if (!GetParam().isCXX14OrLater()) { + return; + } + + EXPECT_TRUE(notMatches("template auto V = []() { T i; };", + declStmt(isInTemplateInstantiation()))); +} + TEST_P(ASTMatchersTest, IsInTemplateInstantiation_Sharing) { if (!GetParam().isCXX()) { return; diff --git a/clang/utils/TableGen/ClangBuiltinsEmitter.cpp b/clang/utils/TableGen/ClangBuiltinsEmitter.cpp index 20231ee1502c125a472c0b9f196456935b36b975..57a1fc06b26b1664712b725fbbce92083d84921c 100644 --- a/clang/utils/TableGen/ClangBuiltinsEmitter.cpp +++ b/clang/utils/TableGen/ClangBuiltinsEmitter.cpp @@ -64,7 +64,8 @@ private: // detecting the comma of the template class as a separator for // the parameters of the prototype. Note: the assumption is that // we cannot have nested _ExtVector. - if (Current.starts_with("_ExtVector<")) { + if (Current.starts_with("_ExtVector<") || + Current.starts_with("_Vector<")) { const size_t EndTemplate = Current.find('>', 0); ParseType(Current.substr(0, EndTemplate + 1)); // Move the prototype beyond _ExtVector<...> @@ -123,7 +124,8 @@ private: if (Substitution.empty()) PrintFatalError(Loc, "Not a template"); ParseType(Substitution); - } else if (T.consume_front("_ExtVector")) { + } else if (auto IsExt = T.consume_front("_ExtVector"); + IsExt || T.consume_front("_Vector")) { // Clang extended vector types are mangled as follows: // // '_ExtVector<' ',' '>' @@ -135,7 +137,7 @@ private: unsigned long long Lanes; if (consumeUnsignedInteger(T, 10, Lanes)) PrintFatalError(Loc, "Expected number of lanes after '_ExtVector<'"); - Type += "E" + std::to_string(Lanes); + Type += (IsExt ? "E" : "V") + std::to_string(Lanes); if (!T.consume_front(",")) PrintFatalError(Loc, "Expected ',' after number of lanes in '_ExtVector<'"); diff --git a/compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc b/compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc index 902fa8f79ab8164c41bad326fd2bd9e4b318ee57..e454524c9cb6a2334ca4cc54e1ab476f92b1bb97 100644 --- a/compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc +++ b/compiler-rt/lib/builtins/cpu_model/AArch64CPUFeatures.inc @@ -53,9 +53,9 @@ enum CPUFeatures { FEAT_EBF16, FEAT_RPRES, FEAT_SVE, - FEAT_SVE_BF16, - FEAT_SVE_EBF16, - FEAT_SVE_I8MM, + RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy + RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy + RESERVED_FEAT_SVE_I8MM, // previously used and now ABI legacy FEAT_SVE_F32MM, FEAT_SVE_F64MM, FEAT_SVE2, diff --git a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc index 0c76a4fe9b9f2f2b89eb31f4e3e30c229270ed7a..4e25feb2e90c6355992deb23e6258a9d8682ecbb 100644 --- a/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc +++ b/compiler-rt/lib/builtins/cpu_model/aarch64/fmv/mrs.inc @@ -65,14 +65,10 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_I8MM); if (hwcap2 & HWCAP2_EBF16) setCPUFeature(FEAT_EBF16); - if (hwcap2 & HWCAP2_SVE_EBF16) - setCPUFeature(FEAT_SVE_EBF16); if (hwcap2 & HWCAP2_DGH) setCPUFeature(FEAT_DGH); if (hwcap2 & HWCAP2_FRINT) setCPUFeature(FEAT_FRINTTS); - if (hwcap2 & HWCAP2_SVEI8MM) - setCPUFeature(FEAT_SVE_I8MM); if (hwcap2 & HWCAP2_SVEF32MM) setCPUFeature(FEAT_SVE_F32MM); if (hwcap2 & HWCAP2_SVEF64MM) @@ -119,8 +115,6 @@ static void __init_cpu_features_constructor(unsigned long hwcap, setCPUFeature(FEAT_RCPC3); if (hwcap2 & HWCAP2_BF16) setCPUFeature(FEAT_BF16); - if (hwcap2 & HWCAP2_SVEBF16) - setCPUFeature(FEAT_SVE_BF16); if (hwcap & HWCAP_SVE) setCPUFeature(FEAT_SVE); if (hwcap2 & HWCAP2_SVE2) diff --git a/compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp b/compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp index 890d6c11c407623b239ebbc923be98d1bd13e8e4..a65871b17da5a8b5f6997da59e3ffd71765d4c97 100644 --- a/compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp +++ b/compiler-rt/lib/rtsan/rtsan_interceptors_posix.cpp @@ -431,9 +431,12 @@ INTERCEPTOR(void, free, void *ptr) { if (DlsymAlloc::PointerIsMine(ptr)) return DlsymAlloc::Free(ptr); - if (ptr != NULL) { + // According to the C and C++ standard, freeing a nullptr is guaranteed to be + // a no-op (and thus real-time safe). This can be confirmed for looking at + // __libc_free in the glibc source. + if (ptr != nullptr) __rtsan_notify_intercepted_call("free"); - } + return REAL(free)(ptr); } diff --git a/compiler-rt/test/hwasan/TestCases/many-threads-uaf.c b/compiler-rt/test/hwasan/TestCases/many-threads-uaf.c index 8fa07861371d56d7a3a7fbad9bf63a62582f7a1e..e02ab5b28ce046c65f299c1b820d9f1ee5d3e1f8 100644 --- a/compiler-rt/test/hwasan/TestCases/many-threads-uaf.c +++ b/compiler-rt/test/hwasan/TestCases/many-threads-uaf.c @@ -23,6 +23,7 @@ void *BoringThread(void *arg) { void *UAFThread(void *arg) { char * volatile x = (char*)malloc(10); fprintf(stderr, "ZZZ %p\n", x); + fflush(stderr); free(x); x[5] = 42; // CHECK: ERROR: HWAddressSanitizer: tag-mismatch on address diff --git a/compiler-rt/test/hwasan/TestCases/mem-intrinsics.c b/compiler-rt/test/hwasan/TestCases/mem-intrinsics.c index 78bef538af11610136f0409a430cb3b84b4cfd2f..da1cb686969206638fde0ce9e53a2f284769cb06 100644 --- a/compiler-rt/test/hwasan/TestCases/mem-intrinsics.c +++ b/compiler-rt/test/hwasan/TestCases/mem-intrinsics.c @@ -21,6 +21,7 @@ int main() { memcpy(Q, P, 32); #endif write(STDOUT_FILENO, "recovered\n", 10); + fflush(stdout); // WRITE: ERROR: HWAddressSanitizer: tag-mismatch on address // WRITE: WRITE of size 32 at {{.*}} tags: [[PTR_TAG:..]]/[[MEM_TAG:..]] (ptr/mem) // WRITE: Invalid access starting at offset 16 diff --git a/compiler-rt/test/hwasan/TestCases/use-after-free.c b/compiler-rt/test/hwasan/TestCases/use-after-free.c index 070622f560a22552d0b51eecfab5985ed376cdd9..fe4f8b32ea10060271ff725ec16818082cdeb83f 100644 --- a/compiler-rt/test/hwasan/TestCases/use-after-free.c +++ b/compiler-rt/test/hwasan/TestCases/use-after-free.c @@ -15,6 +15,7 @@ int main() { free(x); __hwasan_disable_allocator_tagging(); fprintf(stderr, ISREAD ? "Going to do a READ\n" : "Going to do a WRITE\n"); + fflush(stderr); // CHECK: Going to do a [[TYPE:[A-Z]*]] int r = 0; if (ISREAD) r = x[5]; else x[5] = 42; // should be on the same line. @@ -31,11 +32,11 @@ int main() { // // CHECK: freed by thread {{.*}} here: // CHECK: #0 {{.*}} in {{.*}}free{{.*}} {{.*}}hwasan_allocation_functions.cpp - // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-19]] + // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-20]] // CHECK: previously allocated by thread {{.*}} here: // CHECK: #0 {{.*}} in {{.*}}malloc{{.*}} {{.*}}hwasan_allocation_functions.cpp - // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-24]] + // CHECK: #1 {{.*}} in main {{.*}}use-after-free.c:[[@LINE-25]] // CHECK: Memory tags around the buggy address (one tag corresponds to 16 bytes): // CHECK: =>{{.*}}[[MEM_TAG]] // CHECK: SUMMARY: HWAddressSanitizer: tag-mismatch {{.*}} in main diff --git a/compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp b/compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp index 92f3c29e970d42c1c489cac0ff0497cf512b4ce7..0dd721571de9b8a981501c0387e67dc1bb286c65 100644 --- a/compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp +++ b/compiler-rt/test/xray/TestCases/Posix/clang-xray-shared.cpp @@ -1,6 +1,6 @@ // Test that the DSO-local runtime library has been linked if -fxray-shared is passed. // -// RUN: %clangxx -fxray-instrument -fxray-shared %s -shared -o %t.so +// RUN: %clangxx -fxray-instrument -fxray-shared -fPIC %s -shared -o %t.so // RUN: llvm-nm %t.so | FileCheck %s --check-prefix ENABLED // RUN: %clangxx -fxray-instrument %s -shared -o %t.so diff --git a/flang/include/flang/Frontend/TargetOptions.h b/flang/include/flang/Frontend/TargetOptions.h index 332adcbe6b6ac3544ac8d8a28eeefb75b5ccdd25..01c878067b921dc1bfc18c5296ee9699ed46a9f0 100644 --- a/flang/include/flang/Frontend/TargetOptions.h +++ b/flang/include/flang/Frontend/TargetOptions.h @@ -44,6 +44,9 @@ public: /// The integer KINDs disabled for this target std::vector disabledIntegerKinds; + + /// Extended Altivec ABI on AIX + bool EnableAIXExtendedAltivecABI; }; } // end namespace Fortran::frontend diff --git a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h index 868a8b4e28742415a78efa27f0da3c59eea4fbb1..f5fb272b4cc3ed28a0bad382c1c9629edbc0ad25 100644 --- a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h @@ -289,6 +289,7 @@ struct IntrinsicLibrary { template mlir::Value genIeeeQuietCompare(mlir::Type resultType, llvm::ArrayRef); + mlir::Value genIeeeReal(mlir::Type, llvm::ArrayRef); mlir::Value genIeeeRint(mlir::Type, llvm::ArrayRef); template void genIeeeSetFlagOrHaltingMode(llvm::ArrayRef); diff --git a/flang/include/flang/Parser/dump-parse-tree.h b/flang/include/flang/Parser/dump-parse-tree.h index 31ad1b7c6ce5b53374836e8d19a545c581eb0ea0..67f7e1aac40edb346cdb8fc4c8808950bae5cb80 100644 --- a/flang/include/flang/Parser/dump-parse-tree.h +++ b/flang/include/flang/Parser/dump-parse-tree.h @@ -517,6 +517,7 @@ public: NODE_ENUM(OmpTaskDependenceType, Type) NODE(parser, OmpDependSinkVec) NODE(parser, OmpDependSinkVecLength) + NODE(parser, OmpDestroyClause) NODE(parser, OmpEndAllocators) NODE(parser, OmpEndAtomic) NODE(parser, OmpEndBlockDirective) @@ -571,6 +572,7 @@ public: NODE_ENUM(OmpDeviceClause, DeviceModifier) NODE(parser, OmpDeviceTypeClause) NODE_ENUM(OmpDeviceTypeClause, Type) + NODE(parser, OmpUpdateClause) NODE(parser, OmpScheduleModifier) NODE(OmpScheduleModifier, Modifier1) NODE(OmpScheduleModifier, Modifier2) @@ -609,6 +611,7 @@ public: NODE(parser, OmpAtomicClauseList) NODE(parser, OmpAtomicDefaultMemOrderClause) NODE_ENUM(common, OmpAtomicDefaultMemOrderType) + NODE(parser, OpenMPDepobjConstruct) NODE(parser, OpenMPFlushConstruct) NODE(parser, OpenMPLoopConstruct) NODE(parser, OpenMPExecutableAllocate) diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h index 174f4c631e9d4cdee83fd1ecae073f2171f00651..13c3353512208bd532f7afa3bcd404262b9f7ef0 100644 --- a/flang/include/flang/Parser/parse-tree.h +++ b/flang/include/flang/Parser/parse-tree.h @@ -3447,7 +3447,7 @@ WRAPPER_CLASS(OmpObjectList, std::list); // MUTEXINOUTSET | DEPOBJ | // since 5.0 // INOUTSET // since 5.2 struct OmpTaskDependenceType { - ENUM_CLASS(Type, In, Out, Inout, Source, Sink) + ENUM_CLASS(Type, In, Out, Inout, Source, Sink, Depobj) WRAPPER_CLASS_BOILERPLATE(OmpTaskDependenceType, Type); }; @@ -3527,19 +3527,6 @@ struct OmpDefaultmapClause { std::tuple> t; }; -// device([ device-modifier :] scalar-integer-expression) -struct OmpDeviceClause { - TUPLE_CLASS_BOILERPLATE(OmpDeviceClause); - ENUM_CLASS(DeviceModifier, Ancestor, Device_Num) - std::tuple, ScalarIntExpr> t; -}; - -// device_type(any | host | nohost) -struct OmpDeviceTypeClause { - ENUM_CLASS(Type, Any, Host, Nohost) - WRAPPER_CLASS_BOILERPLATE(OmpDeviceTypeClause, Type); -}; - // 2.13.9 depend-vec-length -> +/- non-negative-constant struct OmpDependSinkVecLength { TUPLE_CLASS_BOILERPLATE(OmpDependSinkVecLength); @@ -3561,6 +3548,8 @@ struct OmpDependSinkVec { // // depend-modifier -> iterator-modifier // since 5.0 struct OmpDependClause { + OmpTaskDependenceType::Type GetDepType() const; + UNION_CLASS_BOILERPLATE(OmpDependClause); EMPTY_CLASS(Source); WRAPPER_CLASS(Sink, std::list); @@ -3573,6 +3562,26 @@ struct OmpDependClause { std::variant u; }; +// Ref: [5.0:254-255], [5.1:287-288], [5.2:73] +// +// destroy-clause -> +// DESTROY | // since 5.0, until 5.2 +// DESTROY(variable) // since 5.2 +WRAPPER_CLASS(OmpDestroyClause, OmpObject); + +// device([ device-modifier :] scalar-integer-expression) +struct OmpDeviceClause { + TUPLE_CLASS_BOILERPLATE(OmpDeviceClause); + ENUM_CLASS(DeviceModifier, Ancestor, Device_Num) + std::tuple, ScalarIntExpr> t; +}; + +// device_type(any | host | nohost) +struct OmpDeviceTypeClause { + ENUM_CLASS(Type, Any, Host, Nohost) + WRAPPER_CLASS_BOILERPLATE(OmpDeviceTypeClause, Type); +}; + // OMP 5.2 12.6.1 grainsize-clause -> grainsize ([prescriptiveness :] value) struct OmpGrainsizeClause { TUPLE_CLASS_BOILERPLATE(OmpGrainsizeClause); @@ -3716,6 +3725,11 @@ struct OmpNumTasksClause { std::tuple, ScalarIntExpr> t; }; +// Ref: [5.0:254-255], [5.1:287-288], [5.2:321-322] +// +// update-clause -> UPDATE(task-dependence-type) // since 5.0 +WRAPPER_CLASS(OmpUpdateClause, OmpTaskDependenceType); + // OpenMP Clauses struct OmpClause { UNION_CLASS_BOILERPLATE(OmpClause); @@ -4023,6 +4037,18 @@ struct OpenMPCancelConstruct { std::tuple> t; }; +// Ref: [5.0:254-255], [5.1:287-288], [5.2:322-323] +// +// depobj-construct -> DEPOBJ(depend-object) depobj-clause // since 5.0 +// depobj-clause -> depend-clause | // until 5.2 +// destroy-clause | +// update-clause +struct OpenMPDepobjConstruct { + TUPLE_CLASS_BOILERPLATE(OpenMPDepobjConstruct); + CharBlock source; + std::tuple t; +}; + // 2.17.8 flush -> FLUSH [memory-order-clause] [(variable-name-list)] struct OpenMPFlushConstruct { TUPLE_CLASS_BOILERPLATE(OpenMPFlushConstruct); @@ -4047,7 +4073,8 @@ struct OpenMPStandaloneConstruct { UNION_CLASS_BOILERPLATE(OpenMPStandaloneConstruct); CharBlock source; std::variant + OpenMPCancelConstruct, OpenMPCancellationPointConstruct, + OpenMPDepobjConstruct> u; }; diff --git a/flang/include/flang/Runtime/CUDA/kernel.h b/flang/include/flang/Runtime/CUDA/kernel.h index cf07d874a082c0b3916dbeff4bb4bdad84e7b1c6..85afda09e347ae4be9d9ba7f2cfa1e989dda4d44 100644 --- a/flang/include/flang/Runtime/CUDA/kernel.h +++ b/flang/include/flang/Runtime/CUDA/kernel.h @@ -15,13 +15,19 @@ extern "C" { -// This function uses intptr_t instead of CUDA's unsigned int to match +// These functions use intptr_t instead of CUDA's unsigned int to match // the type of MLIR's index type. This avoids the need for casts in the // generated MLIR code. + void RTDEF(CUFLaunchKernel)(const void *kernelName, intptr_t gridX, intptr_t gridY, intptr_t gridZ, intptr_t blockX, intptr_t blockY, intptr_t blockZ, int32_t smem, void **params, void **extra); +void RTDEF(CUFLaunchClusterKernel)(const void *kernelName, intptr_t clusterX, + intptr_t clusterY, intptr_t clusterZ, intptr_t gridX, intptr_t gridY, + intptr_t gridZ, intptr_t blockX, intptr_t blockY, intptr_t blockZ, + int32_t smem, void **params, void **extra); + } // extern "C" #endif // FORTRAN_RUNTIME_CUDA_KERNEL_H_ diff --git a/flang/include/flang/Runtime/CUDA/memory.h b/flang/include/flang/Runtime/CUDA/memory.h index 3c3ae73d4ad7a17d04ccd35bca9e5b460ba79f41..fb48152d707182038d2196ba271cd515f721bd12 100644 --- a/flang/include/flang/Runtime/CUDA/memory.h +++ b/flang/include/flang/Runtime/CUDA/memory.h @@ -36,19 +36,18 @@ void RTDECL(CUFDataTransferPtrPtr)(void *dst, void *src, std::size_t bytes, unsigned mode, const char *sourceFile = nullptr, int sourceLine = 0); /// Data transfer from a pointer to a descriptor. -void RTDECL(CUFDataTransferDescPtr)(const Descriptor &dst, void *src, +void RTDECL(CUFDataTransferDescPtr)(Descriptor *dst, void *src, std::size_t bytes, unsigned mode, const char *sourceFile = nullptr, int sourceLine = 0); /// Data transfer from a descriptor to a pointer. -void RTDECL(CUFDataTransferPtrDesc)(void *dst, const Descriptor &src, +void RTDECL(CUFDataTransferPtrDesc)(void *dst, Descriptor *src, std::size_t bytes, unsigned mode, const char *sourceFile = nullptr, int sourceLine = 0); /// Data transfer from a descriptor to a descriptor. -void RTDECL(CUFDataTransferDescDesc)(const Descriptor &dst, - const Descriptor &src, unsigned mode, const char *sourceFile = nullptr, - int sourceLine = 0); +void RTDECL(CUFDataTransferDescDesc)(Descriptor *dst, Descriptor *src, + unsigned mode, const char *sourceFile = nullptr, int sourceLine = 0); } // extern "C" } // namespace Fortran::runtime::cuda diff --git a/flang/include/flang/Semantics/openmp-directive-sets.h b/flang/include/flang/Semantics/openmp-directive-sets.h index 50d6d5b59ef7dd9a890c5fea6d33999f097414de..55ef1e0ca61b9f6b770a1cccec3879ae2eab80c2 100644 --- a/flang/include/flang/Semantics/openmp-directive-sets.h +++ b/flang/include/flang/Semantics/openmp-directive-sets.h @@ -210,6 +210,7 @@ static const OmpDirectiveSet blockConstructSet{ Directive::OMPD_ordered, Directive::OMPD_parallel, Directive::OMPD_parallel_masked, + Directive::OMPD_parallel_master, Directive::OMPD_parallel_workshare, Directive::OMPD_scope, Directive::OMPD_single, diff --git a/flang/include/flang/Semantics/symbol.h b/flang/include/flang/Semantics/symbol.h index 0767d8ea84bc6ba79c04aea199304c52ee7805d3..b9512f33eaacd5485a2ab8c8d5430965e0812dca 100644 --- a/flang/include/flang/Semantics/symbol.h +++ b/flang/include/flang/Semantics/symbol.h @@ -755,7 +755,7 @@ public: OmpDeclarativeAllocateDirective, OmpExecutableAllocateDirective, OmpDeclareSimd, OmpDeclareTarget, OmpThreadprivate, OmpDeclareReduction, OmpFlushed, OmpCriticalLock, OmpIfSpecified, OmpNone, OmpPreDetermined, - OmpImplicit); + OmpImplicit, OmpDependObject); using Flags = common::EnumSet; const Scope &owner() const { return *owner_; } diff --git a/flang/lib/Frontend/CompilerInstance.cpp b/flang/lib/Frontend/CompilerInstance.cpp index d37430e0e5773e2e298e467b6206620469969d76..35c2ae3c73e69e8c920a6eb4573d60940b4df27b 100644 --- a/flang/lib/Frontend/CompilerInstance.cpp +++ b/flang/lib/Frontend/CompilerInstance.cpp @@ -313,7 +313,6 @@ bool CompilerInstance::setUpTargetMachine() { << error; return false; } - // Create `TargetMachine` const auto &CGOpts = getInvocation().getCodeGenOpts(); std::optional OptLevelOrNone = @@ -322,9 +321,13 @@ bool CompilerInstance::setUpTargetMachine() { llvm::CodeGenOptLevel OptLevel = *OptLevelOrNone; std::string featuresStr = getTargetFeatures(); std::optional cm = getCodeModel(CGOpts.CodeModel); + + llvm::TargetOptions tOpts = llvm::TargetOptions(); + tOpts.EnableAIXExtendedAltivecABI = targetOpts.EnableAIXExtendedAltivecABI; + targetMachine.reset(theTarget->createTargetMachine( theTriple, /*CPU=*/targetOpts.cpu, - /*Features=*/featuresStr, llvm::TargetOptions(), + /*Features=*/featuresStr, /*Options=*/tOpts, /*Reloc::Model=*/CGOpts.getRelocationModel(), /*CodeModel::Model=*/cm, OptLevel)); assert(targetMachine && "Failed to create TargetMachine"); diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp index 94d3d1154178775ca7f8077723b88fa7ca22ae05..1214a2ea6bf1f3fbed17fb79e86a858b10ff1470 100644 --- a/flang/lib/Frontend/CompilerInvocation.cpp +++ b/flang/lib/Frontend/CompilerInvocation.cpp @@ -457,6 +457,16 @@ static void parseTargetArgs(TargetOptions &opts, llvm::opt::ArgList &args) { if (args.hasArg(clang::driver::options::OPT_fdisable_integer_16)) opts.disabledIntegerKinds.push_back(16); + + if (const llvm::opt::Arg *a = + args.getLastArg(clang::driver::options::OPT_mabi_EQ)) { + llvm::StringRef V = a->getValue(); + if (V == "vec-extabi") { + opts.EnableAIXExtendedAltivecABI = true; + } else if (V == "vec-default") { + opts.EnableAIXExtendedAltivecABI = false; + } + } } // Tweak the frontend configuration based on the frontend action static void setUpFrontendBasedOnAction(FrontendOptions &opts) { diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 7c254ce673855ac7dfcd3ede39f358d75340cc3c..8eb1fdb47091784e5c24f368c67f620fa918cac8 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -137,6 +137,8 @@ genDependKindAttr(fir::FirOpBuilder &firOpBuilder, case omp::clause::Depend::TaskDependenceType::Mutexinoutset: case omp::clause::Depend::TaskDependenceType::Inoutset: case omp::clause::Depend::TaskDependenceType::Depobj: + case omp::clause::Depend::TaskDependenceType::Sink: + case omp::clause::Depend::TaskDependenceType::Source: llvm_unreachable("unhandled parser task dependence type"); break; } diff --git a/flang/lib/Lower/OpenMP/Clauses.cpp b/flang/lib/Lower/OpenMP/Clauses.cpp index 9483f643acd55a67cf434aa39d80f4e95ce527ea..45b89de023a4bf7964c39a5a13e2082ce3a91797 100644 --- a/flang/lib/Lower/OpenMP/Clauses.cpp +++ b/flang/lib/Lower/OpenMP/Clauses.cpp @@ -338,6 +338,27 @@ ReductionOperator makeReductionOperator(const parser::OmpReductionOperator &inp, inp.u); } +clause::TaskDependenceType +makeDepType(const parser::OmpTaskDependenceType &inp) { + switch (inp.v) { + case parser::OmpTaskDependenceType::Type::Depobj: + return clause::TaskDependenceType::Depobj; + case parser::OmpTaskDependenceType::Type::In: + return clause::TaskDependenceType::In; + case parser::OmpTaskDependenceType::Type::Inout: + return clause::TaskDependenceType::Inout; + // Inoutset // missing-in-parser + // Mutexinoutset // missing-in-parser + case parser::OmpTaskDependenceType::Type::Out: + return clause::TaskDependenceType::Out; + case parser::OmpTaskDependenceType::Type::Sink: + return clause::TaskDependenceType::Sink; + case parser::OmpTaskDependenceType::Type::Source: + return clause::TaskDependenceType::Source; + } + llvm_unreachable("Unexpected dependence type"); +} + // -------------------------------------------------------------------- // Actual clauses. Each T (where tomp::T exists in ClauseT) has its "make". @@ -554,18 +575,6 @@ Depend make(const parser::OmpClause::Depend &inp, // Iteration is the equivalent of parser::OmpDependSinkVec using Iteration = Doacross::Vector::value_type; // LoopIterationT - CLAUSET_ENUM_CONVERT( // - convert1, parser::OmpTaskDependenceType::Type, Depend::TaskDependenceType, - // clang-format off - MS(In, In) - MS(Out, Out) - MS(Inout, Inout) - // MS(, Mutexinoutset) // missing-in-parser - // MS(, Inputset) // missing-in-parser - // MS(, Depobj) // missing-in-parser - // clang-format on - ); - return Depend{Fortran::common::visit( // common::visitors{ // Doacross @@ -602,7 +611,7 @@ Depend make(const parser::OmpClause::Depend &inp, auto &&maybeIter = maybeApply( [&](auto &&s) { return makeIterator(s, semaCtx); }, t0); - return Depend::DepType{{/*TaskDependenceType=*/convert1(t1.v), + return Depend::DepType{{/*TaskDependenceType=*/makeDepType(t1), /*Iterator=*/std::move(maybeIter), /*LocatorList=*/makeObjects(t2, semaCtx)}}; }, @@ -614,8 +623,14 @@ Depend make(const parser::OmpClause::Depend &inp, Destroy make(const parser::OmpClause::Destroy &inp, semantics::SemanticsContext &semaCtx) { - // inp -> empty - llvm_unreachable("Empty: destroy"); + // inp.v -> std::optional + auto &&maybeObject = maybeApply( + [&](const parser::OmpDestroyClause &c) { + return makeObject(c.v, semaCtx); + }, + inp.v); + + return Destroy{/*DestroyVar=*/std::move(maybeObject)}; } Detach make(const parser::OmpClause::Detach &inp, @@ -1279,8 +1294,8 @@ Uniform make(const parser::OmpClause::Uniform &inp, Update make(const parser::OmpClause::Update &inp, semantics::SemanticsContext &semaCtx) { - // inp -> empty - return Update{/*TaskDependenceType=*/std::nullopt}; + // inp.v -> parser::OmpUpdateClause + return Update{/*TaskDependenceType=*/makeDepType(inp.v.v)}; } Use make(const parser::OmpClause::Use &inp, diff --git a/flang/lib/Lower/OpenMP/Clauses.h b/flang/lib/Lower/OpenMP/Clauses.h index 1e911a204685754c1fa77034a292903f1cfb1dbe..51180ebfe5745e0f20ea4b1112d21ee58e049af1 100644 --- a/flang/lib/Lower/OpenMP/Clauses.h +++ b/flang/lib/Lower/OpenMP/Clauses.h @@ -152,6 +152,7 @@ using IteratorSpecifier = tomp::type::IteratorSpecifierT; using DefinedOperator = tomp::type::DefinedOperatorT; using ProcedureDesignator = tomp::type::ProcedureDesignatorT; using ReductionOperator = tomp::type::ReductionIdentifierT; +using TaskDependenceType = tomp::type::TaskDependenceType; // "Requires" clauses are handled early on, and the aggregated information // is stored in the Symbol details of modules, programs, and subprograms. diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index 01a40d6e2204ef2ff0ac0b4634281b03a75f26a0..84985b880b1ec28cf8b3324e1344e5f3c7b308d6 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -76,6 +76,18 @@ struct EntryBlockArgs { reduction.isValid() && taskReduction.isValid() && useDeviceAddr.isValid() && useDevicePtr.isValid(); } + + auto getSyms() const { + return llvm::concat( + inReduction.syms, map.syms, priv.syms, reduction.syms, + taskReduction.syms, useDeviceAddr.syms, useDevicePtr.syms); + } + + auto getVars() const { + return llvm::concat( + inReduction.vars, map.vars, priv.vars, reduction.vars, + taskReduction.vars, useDeviceAddr.vars, useDevicePtr.vars); + } }; } // namespace @@ -1506,8 +1518,7 @@ genParallelOp(lower::AbstractConverter &converter, lower::SymMap &symTable, genEntryBlock(converter, args, op->getRegion(0)); bindEntryBlockArgs( converter, llvm::cast(op), args); - return llvm::to_vector(llvm::concat( - args.priv.syms, args.reduction.syms)); + return llvm::to_vector(args.getSyms()); }; assert((!enableDelayedPrivatization || dsp) && @@ -1581,11 +1592,11 @@ genSectionsOp(lower::AbstractConverter &converter, lower::SymMap &symTable, mlir::Operation *terminator = lower::genOpenMPTerminator(builder, sectionsOp, loc); - auto reductionCallback = [&](mlir::Operation *op) { + auto genRegionEntryCB = [&](mlir::Operation *op) { genEntryBlock(converter, args, op->getRegion(0)); bindEntryBlockArgs( converter, llvm::cast(op), args); - return reductionSyms; + return llvm::to_vector(args.getSyms()); }; // Generate nested SECTION constructs. @@ -1611,7 +1622,7 @@ genSectionsOp(lower::AbstractConverter &converter, lower::SymMap &symTable, OpWithBodyGenInfo(converter, symTable, semaCtx, loc, nestedEval, llvm::omp::Directive::OMPD_section) .setClauses(§ionQueue.begin()->clauses) - .setGenRegionEntryCb(reductionCallback), + .setGenRegionEntryCb(genRegionEntryCB), sectionQueue, sectionQueue.begin()); } @@ -2699,6 +2710,21 @@ static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, TODO(converter.getCurrentLocation(), "OpenMPCancelConstruct"); } +static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, + semantics::SemanticsContext &semaCtx, + lower::pft::Evaluation &eval, + const parser::OpenMPDepobjConstruct &construct) { + // These values will be ignored until the construct itself is implemented, + // but run them anyway for the sake of testing (via a Todo test). + auto &ompObj = std::get(construct.t); + const Object &depObj = makeObject(ompObj, semaCtx); + Clause clause = makeClause(std::get(construct.t), semaCtx); + (void)depObj; + (void)clause; + + TODO(converter.getCurrentLocation(), "OpenMPDepobjConstruct"); +} + static void genOMP(lower::AbstractConverter &converter, lower::SymMap &symTable, semantics::SemanticsContext &semaCtx, lower::pft::Evaluation &eval, diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp index 462193a850c4872871e0eee57dd14c99e34952aa..7c7c8ee539111db9755476b1e9977935b9fcb527 100644 --- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp @@ -97,7 +97,6 @@ static bool isStaticallyPresent(const fir::ExtendedValue &exv) { /// IEEE module procedure names not yet implemented for genModuleProcTODO. static constexpr char ieee_get_underflow_mode[] = "ieee_get_underflow_mode"; -static constexpr char ieee_real[] = "ieee_real"; static constexpr char ieee_rem[] = "ieee_rem"; static constexpr char ieee_set_underflow_mode[] = "ieee_set_underflow_mode"; @@ -362,7 +361,7 @@ static constexpr IntrinsicHandler handlers[]{ {"ieee_quiet_le", &I::genIeeeQuietCompare}, {"ieee_quiet_lt", &I::genIeeeQuietCompare}, {"ieee_quiet_ne", &I::genIeeeQuietCompare}, - {"ieee_real", &I::genModuleProcTODO}, + {"ieee_real", &I::genIeeeReal}, {"ieee_rem", &I::genModuleProcTODO}, {"ieee_rint", &I::genIeeeRint}, {"ieee_round_eq", &I::genIeeeTypeCompare}, @@ -4799,6 +4798,238 @@ IntrinsicLibrary::genIeeeQuietCompare(mlir::Type resultType, return builder.create(loc, resultType, res); } +// IEEE_REAL +mlir::Value IntrinsicLibrary::genIeeeReal(mlir::Type resultType, + llvm::ArrayRef args) { + // Convert integer or real argument A to a real of a specified kind. + // Round according to the current rounding mode. + // Signal IEEE_INVALID if A is an sNaN, and return a qNaN. + // Signal IEEE_UNDERFLOW for an inexact subnormal or zero result. + // Signal IEEE_OVERFLOW if A is finite and the result is infinite. + // Signal IEEE_INEXACT for an inexact result. + // + // if (type(a) == resultType) { + // // Conversion to the same type is a nop except for sNaN processing. + // result = a + // } else { + // result = r = real(a, kind(result)) + // // Conversion to a larger type is exact. + // if (c_sizeof(a) >= c_sizeof(r)) { + // b = (a is integer) ? int(r, kind(a)) : real(r, kind(a)) + // if (a == b || isNaN(a)) { + // // a is {-0, +0, -inf, +inf, NaN} or exact; result is r + // } else { + // // odd(r) is true if the low bit of significand(r) is 1 + // // rounding mode ieee_other is an alias for mode ieee_nearest + // if (a < b) { + // if (mode == ieee_nearest && odd(r)) result = ieee_next_down(r) + // if (mode == ieee_other && odd(r)) result = ieee_next_down(r) + // if (mode == ieee_to_zero && a > 0) result = ieee_next_down(r) + // if (mode == ieee_away && a < 0) result = ieee_next_down(r) + // if (mode == ieee_down) result = ieee_next_down(r) + // } else { // a > b + // if (mode == ieee_nearest && odd(r)) result = ieee_next_up(r) + // if (mode == ieee_other && odd(r)) result = ieee_next_up(r) + // if (mode == ieee_to_zero && a < 0) result = ieee_next_up(r) + // if (mode == ieee_away && a > 0) result = ieee_next_up(r) + // if (mode == ieee_up) result = ieee_next_up(r) + // } + // } + // } + // } + + assert(args.size() == 2); + mlir::Type i1Ty = builder.getI1Type(); + mlir::Type f32Ty = mlir::FloatType::getF32(builder.getContext()); + mlir::Value a = args[0]; + mlir::Type aType = a.getType(); + + // If the argument is an sNaN, raise an invalid exception and return a qNaN. + // Otherwise return the argument. + auto processSnan = [&](mlir::Value x) { + fir::IfOp ifOp = builder.create(loc, resultType, + genIsFPClass(i1Ty, x, snanTest), + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&ifOp.getThenRegion().front()); + genRaiseExcept(_FORTRAN_RUNTIME_IEEE_INVALID); + builder.create(loc, genQNan(resultType)); + builder.setInsertionPointToStart(&ifOp.getElseRegion().front()); + builder.create(loc, x); + builder.setInsertionPointAfter(ifOp); + return ifOp.getResult(0); + }; + + // Conversion is a nop, except that A may be an sNaN. + if (resultType == aType) + return processSnan(a); + + // Can't directly convert between kind=2 and kind=3. + mlir::Value r, r1; + if ((aType.isBF16() && resultType.isF16()) || + (aType.isF16() && resultType.isBF16())) { + a = builder.createConvert(loc, f32Ty, a); + aType = f32Ty; + } + r = builder.create(loc, resultType, a); + + mlir::IntegerType aIntType = mlir::dyn_cast(aType); + mlir::FloatType aFloatType = mlir::dyn_cast(aType); + mlir::FloatType resultFloatType = mlir::dyn_cast(resultType); + + // Conversion from a smaller type to a larger type is exact. + if ((aIntType ? aIntType.getWidth() : aFloatType.getWidth()) < + resultFloatType.getWidth()) + return aIntType ? r : processSnan(r); + + // A possibly inexact conversion result may need to be rounded up or down. + mlir::Value b = builder.create(loc, aType, r); + mlir::Value aEqB; + if (aIntType) + aEqB = builder.create( + loc, mlir::arith::CmpIPredicate::eq, a, b); + else + aEqB = builder.create( + loc, mlir::arith::CmpFPredicate::UEQ, a, b); + + // [a == b] a is a NaN or r is exact (a may be -0, +0, -inf, +inf) -- return r + fir::IfOp ifOp1 = builder.create(loc, resultType, aEqB, + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&ifOp1.getThenRegion().front()); + builder.create(loc, aIntType ? r : processSnan(r)); + + // Code common to (a < b) and (a > b) branches. + builder.setInsertionPointToStart(&ifOp1.getElseRegion().front()); + mlir::func::FuncOp getRound = fir::factory::getLlvmGetRounding(builder); + mlir::Value mode = builder.create(loc, getRound).getResult(0); + mlir::Value aIsNegative, aIsPositive; + if (aIntType) { + mlir::Value zero = builder.createIntegerConstant(loc, aIntType, 0); + aIsNegative = builder.create( + loc, mlir::arith::CmpIPredicate::slt, a, zero); + aIsPositive = builder.create( + loc, mlir::arith::CmpIPredicate::sgt, a, zero); + } else { + mlir::Value zero = builder.createRealZeroConstant(loc, aFloatType); + aIsNegative = builder.create( + loc, mlir::arith::CmpFPredicate::OLT, a, zero); + aIsPositive = builder.create( + loc, mlir::arith::CmpFPredicate::OGT, a, zero); + } + mlir::Type resultIntType = builder.getIntegerType(resultFloatType.getWidth()); + mlir::Value resultCast = + builder.create(loc, resultIntType, r); + mlir::Value one = builder.createIntegerConstant(loc, resultIntType, 1); + mlir::Value rIsOdd = builder.create( + loc, i1Ty, builder.create(loc, resultCast, one)); + // Check for a rounding mode match. + auto match = [&](int m) { + return builder.create( + loc, mlir::arith::CmpIPredicate::eq, mode, + builder.createIntegerConstant(loc, mode.getType(), m)); + }; + mlir::Value roundToNearestBit = builder.create( + loc, + // IEEE_OTHER is an alias for IEEE_NEAREST. + match(_FORTRAN_RUNTIME_IEEE_NEAREST), match(_FORTRAN_RUNTIME_IEEE_OTHER)); + mlir::Value roundToNearest = + builder.create(loc, roundToNearestBit, rIsOdd); + mlir::Value roundToZeroBit = match(_FORTRAN_RUNTIME_IEEE_TO_ZERO); + mlir::Value roundAwayBit = match(_FORTRAN_RUNTIME_IEEE_AWAY); + mlir::Value roundToZero, roundAway, mustAdjust; + fir::IfOp adjustIfOp; + mlir::Value aLtB; + if (aIntType) + aLtB = builder.create( + loc, mlir::arith::CmpIPredicate::slt, a, b); + else + aLtB = builder.create( + loc, mlir::arith::CmpFPredicate::OLT, a, b); + mlir::Value upResult = + builder.create(loc, resultCast, one); + mlir::Value downResult = + builder.create(loc, resultCast, one); + + // (a < b): r is inexact -- return r or ieee_next_down(r) + fir::IfOp ifOp2 = builder.create(loc, resultType, aLtB, + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&ifOp2.getThenRegion().front()); + roundToZero = + builder.create(loc, roundToZeroBit, aIsPositive); + roundAway = + builder.create(loc, roundAwayBit, aIsNegative); + mlir::Value roundDown = match(_FORTRAN_RUNTIME_IEEE_DOWN); + mustAdjust = + builder.create(loc, roundToNearest, roundToZero); + mustAdjust = builder.create(loc, mustAdjust, roundAway); + mustAdjust = builder.create(loc, mustAdjust, roundDown); + adjustIfOp = builder.create(loc, resultType, mustAdjust, + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&adjustIfOp.getThenRegion().front()); + if (resultType.isF80()) + r1 = fir::runtime::genNearest(builder, loc, r, + builder.createBool(loc, false)); + else + r1 = builder.create( + loc, resultType, + builder.create(loc, aIsNegative, upResult, + downResult)); + builder.create(loc, r1); + builder.setInsertionPointToStart(&adjustIfOp.getElseRegion().front()); + builder.create(loc, r); + builder.setInsertionPointAfter(adjustIfOp); + builder.create(loc, adjustIfOp.getResult(0)); + + // (a > b): r is inexact -- return r or ieee_next_up(r) + builder.setInsertionPointToStart(&ifOp2.getElseRegion().front()); + roundToZero = + builder.create(loc, roundToZeroBit, aIsNegative); + roundAway = + builder.create(loc, roundAwayBit, aIsPositive); + mlir::Value roundUp = match(_FORTRAN_RUNTIME_IEEE_UP); + mustAdjust = + builder.create(loc, roundToNearest, roundToZero); + mustAdjust = builder.create(loc, mustAdjust, roundAway); + mustAdjust = builder.create(loc, mustAdjust, roundUp); + adjustIfOp = builder.create(loc, resultType, mustAdjust, + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&adjustIfOp.getThenRegion().front()); + if (resultType.isF80()) + r1 = fir::runtime::genNearest(builder, loc, r, + builder.createBool(loc, true)); + else + r1 = builder.create( + loc, resultType, + builder.create(loc, aIsPositive, upResult, + downResult)); + builder.create(loc, r1); + builder.setInsertionPointToStart(&adjustIfOp.getElseRegion().front()); + builder.create(loc, r); + builder.setInsertionPointAfter(adjustIfOp); + builder.create(loc, adjustIfOp.getResult(0)); + + // Generate exceptions for (a < b) and (a > b) branches. + builder.setInsertionPointAfter(ifOp2); + r = ifOp2.getResult(0); + fir::IfOp exceptIfOp1 = builder.create( + loc, genIsFPClass(i1Ty, r, infiniteTest), /*withElseRegion=*/true); + builder.setInsertionPointToStart(&exceptIfOp1.getThenRegion().front()); + genRaiseExcept(_FORTRAN_RUNTIME_IEEE_OVERFLOW | + _FORTRAN_RUNTIME_IEEE_INEXACT); + builder.setInsertionPointToStart(&exceptIfOp1.getElseRegion().front()); + fir::IfOp exceptIfOp2 = builder.create( + loc, genIsFPClass(i1Ty, r, subnormalTest | zeroTest), + /*withElseRegion=*/true); + builder.setInsertionPointToStart(&exceptIfOp2.getThenRegion().front()); + genRaiseExcept(_FORTRAN_RUNTIME_IEEE_UNDERFLOW | + _FORTRAN_RUNTIME_IEEE_INEXACT); + builder.setInsertionPointToStart(&exceptIfOp2.getElseRegion().front()); + genRaiseExcept(_FORTRAN_RUNTIME_IEEE_INEXACT); + builder.setInsertionPointAfter(exceptIfOp1); + builder.create(loc, ifOp2.getResult(0)); + builder.setInsertionPointAfter(ifOp1); + return ifOp1.getResult(0); +} + // IEEE_RINT mlir::Value IntrinsicLibrary::genIeeeRint(mlir::Type resultType, llvm::ArrayRef args) { diff --git a/flang/lib/Optimizer/CodeGen/CodeGen.cpp b/flang/lib/Optimizer/CodeGen/CodeGen.cpp index e6eeb0d5db4a841ff3867f6db057e0614fd1a41b..4c8c56e0f21cef18694eecc635003cc8423844cc 100644 --- a/flang/lib/Optimizer/CodeGen/CodeGen.cpp +++ b/flang/lib/Optimizer/CodeGen/CodeGen.cpp @@ -2949,9 +2949,10 @@ struct LoadOpConversion : public fir::FIROpConversion { llvm::LogicalResult matchAndRewrite(fir::LoadOp load, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { + mlir::Type llvmLoadTy = convertObjectType(load.getType()); if (auto boxTy = mlir::dyn_cast(load.getType())) { - // fir.box is a special case because it is considered as an ssa values in + // fir.box is a special case because it is considered an ssa value in // fir, but it is lowered as a pointer to a descriptor. So // fir.ref and fir.box end up being the same llvm types and // loading a fir.ref is implemented as taking a snapshot of the @@ -2960,30 +2961,17 @@ struct LoadOpConversion : public fir::FIROpConversion { mlir::Location loc = load.getLoc(); auto newBoxStorage = genAllocaAndAddrCastWithType(loc, llvmLoadTy, defaultAlign, rewriter); - // TODO: always generate llvm.memcpy, LLVM is better at optimizing it than - // aggregate loads + stores. - if (boxTy.isAssumedRank()) { - - TypePair boxTypePair{boxTy, llvmLoadTy}; - mlir::Value boxSize = - computeBoxSize(loc, boxTypePair, inputBoxStorage, rewriter); - auto memcpy = rewriter.create( - loc, newBoxStorage, inputBoxStorage, boxSize, /*isVolatile=*/false); - if (std::optional optionalTag = load.getTbaa()) - memcpy.setTBAATags(*optionalTag); - else - attachTBAATag(memcpy, boxTy, boxTy, nullptr); - } else { - auto boxValue = rewriter.create(loc, llvmLoadTy, - inputBoxStorage); - if (std::optional optionalTag = load.getTbaa()) - boxValue.setTBAATags(*optionalTag); - else - attachTBAATag(boxValue, boxTy, boxTy, nullptr); - auto storeOp = - rewriter.create(loc, boxValue, newBoxStorage); - attachTBAATag(storeOp, boxTy, boxTy, nullptr); - } + + TypePair boxTypePair{boxTy, llvmLoadTy}; + mlir::Value boxSize = + computeBoxSize(loc, boxTypePair, inputBoxStorage, rewriter); + auto memcpy = rewriter.create( + loc, newBoxStorage, inputBoxStorage, boxSize, /*isVolatile=*/false); + + if (std::optional optionalTag = load.getTbaa()) + memcpy.setTBAATags(*optionalTag); + else + attachTBAATag(memcpy, boxTy, boxTy, nullptr); rewriter.replaceOp(load, newBoxStorage); } else { auto loadOp = rewriter.create( @@ -3227,20 +3215,13 @@ struct StoreOpConversion : public fir::FIROpConversion { mlir::LLVM::AliasAnalysisOpInterface newOp; if (auto boxTy = mlir::dyn_cast(storeTy)) { mlir::Type llvmBoxTy = lowerTy().convertBoxTypeAsStruct(boxTy); - // fir.box value is actually in memory, load it first before storing it, - // or do a memcopy for assumed-rank descriptors. - if (boxTy.isAssumedRank()) { - TypePair boxTypePair{boxTy, llvmBoxTy}; - mlir::Value boxSize = - computeBoxSize(loc, boxTypePair, llvmValue, rewriter); - newOp = rewriter.create( - loc, llvmMemref, llvmValue, boxSize, /*isVolatile=*/false); - } else { - auto val = - rewriter.create(loc, llvmBoxTy, llvmValue); - attachTBAATag(val, boxTy, boxTy, nullptr); - newOp = rewriter.create(loc, val, llvmMemref); - } + // Always use memcpy because LLVM is not as effective at optimizing + // aggregate loads/stores as it is optimizing memcpy. + TypePair boxTypePair{boxTy, llvmBoxTy}; + mlir::Value boxSize = + computeBoxSize(loc, boxTypePair, llvmValue, rewriter); + newOp = rewriter.create( + loc, llvmMemref, llvmValue, boxSize, /*isVolatile=*/false); } else { newOp = rewriter.create(loc, llvmValue, llvmMemref); } diff --git a/flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp b/flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp index 4da06be8ef7dd95e159988d6e00454fca3547361..7cdb2f7ffe27d970b246cf02e9968b1ebb0e0d7b 100644 --- a/flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp +++ b/flang/lib/Optimizer/Transforms/CUFAddConstructor.cpp @@ -6,15 +6,23 @@ // //===----------------------------------------------------------------------===// +#include "flang/Optimizer/Builder/BoxValue.h" #include "flang/Optimizer/Builder/FIRBuilder.h" +#include "flang/Optimizer/Builder/Runtime/RTBuilder.h" +#include "flang/Optimizer/Builder/Todo.h" +#include "flang/Optimizer/CodeGen/Target.h" #include "flang/Optimizer/Dialect/CUF/CUFOps.h" #include "flang/Optimizer/Dialect/FIRAttr.h" #include "flang/Optimizer/Dialect/FIRDialect.h" +#include "flang/Optimizer/Dialect/FIROps.h" #include "flang/Optimizer/Dialect/FIROpsSupport.h" +#include "flang/Optimizer/Support/DataLayout.h" #include "flang/Optimizer/Transforms/CUFCommon.h" +#include "flang/Runtime/CUDA/registration.h" #include "flang/Runtime/entry-names.h" #include "mlir/Dialect/GPU/IR/GPUDialect.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" +#include "mlir/IR/Value.h" #include "mlir/Pass/Pass.h" #include "llvm/ADT/SmallVector.h" @@ -23,6 +31,8 @@ namespace fir { #include "flang/Optimizer/Transforms/Passes.h.inc" } // namespace fir +using namespace Fortran::runtime::cuda; + namespace { static constexpr llvm::StringRef cudaFortranCtorName{ @@ -34,13 +44,23 @@ struct CUFAddConstructor void runOnOperation() override { mlir::ModuleOp mod = getOperation(); mlir::SymbolTable symTab(mod); - mlir::OpBuilder builder{mod.getBodyRegion()}; + mlir::OpBuilder opBuilder{mod.getBodyRegion()}; + fir::FirOpBuilder builder(opBuilder, mod); + fir::KindMapping kindMap{fir::getKindMapping(mod)}; builder.setInsertionPointToEnd(mod.getBody()); mlir::Location loc = mod.getLoc(); auto *ctx = mod.getContext(); auto voidTy = mlir::LLVM::LLVMVoidType::get(ctx); + auto idxTy = builder.getIndexType(); auto funcTy = mlir::LLVM::LLVMFunctionType::get(voidTy, {}, /*isVarArg=*/false); + std::optional dl = + fir::support::getOrSetDataLayout(mod, /*allowDefaultLayout=*/false); + if (!dl) { + mlir::emitError(mod.getLoc(), + "data layout attribute is required to perform " + + getName() + "pass"); + } // Symbol reference to CUFRegisterAllocator. builder.setInsertionPointToEnd(mod.getBody()); @@ -58,12 +78,13 @@ struct CUFAddConstructor builder.setInsertionPointToStart(func.addEntryBlock(builder)); builder.create(loc, funcTy, cufRegisterAllocatorRef); - // Register kernels auto gpuMod = symTab.lookup(cudaDeviceModuleName); if (gpuMod) { auto llvmPtrTy = mlir::LLVM::LLVMPointerType::get(ctx); auto registeredMod = builder.create( loc, llvmPtrTy, mlir::SymbolRefAttr::get(ctx, gpuMod.getName())); + + // Register kernels for (auto func : gpuMod.getOps()) { if (func.isKernel()) { auto kernelName = mlir::SymbolRefAttr::get( @@ -72,12 +93,55 @@ struct CUFAddConstructor builder.create(loc, kernelName, registeredMod); } } + + // Register variables + for (fir::GlobalOp globalOp : mod.getOps()) { + auto attr = globalOp.getDataAttrAttr(); + if (!attr) + continue; + + mlir::func::FuncOp func; + switch (attr.getValue()) { + case cuf::DataAttribute::Device: + case cuf::DataAttribute::Constant: { + func = fir::runtime::getRuntimeFunc( + loc, builder); + auto fTy = func.getFunctionType(); + + // Global variable name + std::string gblNameStr = globalOp.getSymbol().getValue().str(); + gblNameStr += '\0'; + mlir::Value gblName = fir::getBase( + fir::factory::createStringLiteral(builder, loc, gblNameStr)); + + // Global variable size + auto sizeAndAlign = fir::getTypeSizeAndAlignmentOrCrash( + loc, globalOp.getType(), *dl, kindMap); + auto size = + builder.createIntegerConstant(loc, idxTy, sizeAndAlign.first); + + // Global variable address + mlir::Value addr = builder.create( + loc, globalOp.resultType(), globalOp.getSymbol()); + + llvm::SmallVector args{fir::runtime::createArguments( + builder, loc, fTy, registeredMod, addr, gblName, size)}; + builder.create(loc, func, args); + } break; + case cuf::DataAttribute::Managed: + TODO(loc, "registration of managed variables"); + default: + break; + } + if (!func) + continue; + } } builder.create(loc, mlir::ValueRange{}); // Create the llvm.global_ctor with the function. - // TODO: We might want to have a utility that retrieve it if already created - // and adds new functions. + // TODO: We might want to have a utility that retrieve it if already + // created and adds new functions. builder.setInsertionPointToEnd(mod.getBody()); llvm::SmallVector funcs; funcs.push_back( diff --git a/flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp b/flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp index 5645ce6e6858c826f77ed6d5544da3c4d798a883..c64f35542a6e590ff4bc269e0bf959b09e34f2a2 100644 --- a/flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp +++ b/flang/lib/Optimizer/Transforms/CUFGPUToLLVMConversion.cpp @@ -76,11 +76,6 @@ struct GPULaunchKernelConversion mlir::LogicalResult matchAndRewrite(mlir::gpu::LaunchFuncOp op, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { - - if (op.hasClusterSize()) { - return mlir::failure(); - } - mlir::Location loc = op.getLoc(); auto *ctx = rewriter.getContext(); mlir::ModuleOp mod = op->getParentOfType(); @@ -107,37 +102,65 @@ struct GPULaunchKernelConversion rewriter.create(loc, ptrTy, kernel.getName()); } - auto funcOp = mod.lookupSymbol( - RTNAME_STRING(CUFLaunchKernel)); - auto llvmIntPtrType = mlir::IntegerType::get( ctx, this->getTypeConverter()->getPointerBitwidth(0)); auto voidTy = mlir::LLVM::LLVMVoidType::get(ctx); - auto funcTy = mlir::LLVM::LLVMFunctionType::get( - voidTy, - {ptrTy, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, - llvmIntPtrType, llvmIntPtrType, i32Ty, ptrTy, ptrTy}, - /*isVarArg=*/false); - - auto cufLaunchKernel = mlir::SymbolRefAttr::get( - mod.getContext(), RTNAME_STRING(CUFLaunchKernel)); - if (!funcOp) { - mlir::OpBuilder::InsertionGuard insertGuard(rewriter); - rewriter.setInsertionPointToStart(mod.getBody()); - auto launchKernelFuncOp = rewriter.create( - loc, RTNAME_STRING(CUFLaunchKernel), funcTy); - launchKernelFuncOp.setVisibility(mlir::SymbolTable::Visibility::Private); - } mlir::Value nullPtr = rewriter.create(loc, ptrTy); - rewriter.replaceOpWithNewOp( - op, funcTy, cufLaunchKernel, - mlir::ValueRange{kernelPtr, adaptor.getGridSizeX(), - adaptor.getGridSizeY(), adaptor.getGridSizeZ(), - adaptor.getBlockSizeX(), adaptor.getBlockSizeY(), - adaptor.getBlockSizeZ(), dynamicMemorySize, kernelArgs, - nullPtr}); + if (op.hasClusterSize()) { + auto funcOp = mod.lookupSymbol( + RTNAME_STRING(CUFLaunchClusterKernel)); + auto funcTy = mlir::LLVM::LLVMFunctionType::get( + voidTy, + {ptrTy, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, + llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, + llvmIntPtrType, llvmIntPtrType, i32Ty, ptrTy, ptrTy}, + /*isVarArg=*/false); + auto cufLaunchClusterKernel = mlir::SymbolRefAttr::get( + mod.getContext(), RTNAME_STRING(CUFLaunchClusterKernel)); + if (!funcOp) { + mlir::OpBuilder::InsertionGuard insertGuard(rewriter); + rewriter.setInsertionPointToStart(mod.getBody()); + auto launchKernelFuncOp = rewriter.create( + loc, RTNAME_STRING(CUFLaunchClusterKernel), funcTy); + launchKernelFuncOp.setVisibility( + mlir::SymbolTable::Visibility::Private); + } + rewriter.replaceOpWithNewOp( + op, funcTy, cufLaunchClusterKernel, + mlir::ValueRange{kernelPtr, adaptor.getClusterSizeX(), + adaptor.getClusterSizeY(), adaptor.getClusterSizeZ(), + adaptor.getGridSizeX(), adaptor.getGridSizeY(), + adaptor.getGridSizeZ(), adaptor.getBlockSizeX(), + adaptor.getBlockSizeY(), adaptor.getBlockSizeZ(), + dynamicMemorySize, kernelArgs, nullPtr}); + } else { + auto funcOp = mod.lookupSymbol( + RTNAME_STRING(CUFLaunchKernel)); + auto funcTy = mlir::LLVM::LLVMFunctionType::get( + voidTy, + {ptrTy, llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, + llvmIntPtrType, llvmIntPtrType, llvmIntPtrType, i32Ty, ptrTy, ptrTy}, + /*isVarArg=*/false); + auto cufLaunchKernel = mlir::SymbolRefAttr::get( + mod.getContext(), RTNAME_STRING(CUFLaunchKernel)); + if (!funcOp) { + mlir::OpBuilder::InsertionGuard insertGuard(rewriter); + rewriter.setInsertionPointToStart(mod.getBody()); + auto launchKernelFuncOp = rewriter.create( + loc, RTNAME_STRING(CUFLaunchKernel), funcTy); + launchKernelFuncOp.setVisibility( + mlir::SymbolTable::Visibility::Private); + } + rewriter.replaceOpWithNewOp( + op, funcTy, cufLaunchKernel, + mlir::ValueRange{kernelPtr, adaptor.getGridSizeX(), + adaptor.getGridSizeY(), adaptor.getGridSizeZ(), + adaptor.getBlockSizeX(), adaptor.getBlockSizeY(), + adaptor.getBlockSizeZ(), dynamicMemorySize, + kernelArgs, nullPtr}); + } return mlir::success(); } diff --git a/flang/lib/Optimizer/Transforms/CUFOpConversion.cpp b/flang/lib/Optimizer/Transforms/CUFOpConversion.cpp index 9c2b882c7f46fef0274f90aab99f68c6cc01620c..e3e441360e949b9f48260f65ccd6e4afb0ee326c 100644 --- a/flang/lib/Optimizer/Transforms/CUFOpConversion.cpp +++ b/flang/lib/Optimizer/Transforms/CUFOpConversion.cpp @@ -15,6 +15,7 @@ #include "flang/Optimizer/Dialect/FIROps.h" #include "flang/Optimizer/HLFIR/HLFIROps.h" #include "flang/Optimizer/Support/DataLayout.h" +#include "flang/Optimizer/Transforms/CUFCommon.h" #include "flang/Runtime/CUDA/allocatable.h" #include "flang/Runtime/CUDA/common.h" #include "flang/Runtime/CUDA/descriptor.h" @@ -111,7 +112,7 @@ mlir::Value getDeviceAddress(mlir::PatternRewriter &rewriter, switch (attr.getValue()) { case cuf::DataAttribute::Device: case cuf::DataAttribute::Managed: - case cuf::DataAttribute::Pinned: + case cuf::DataAttribute::Constant: isDevGlobal = true; break; default: @@ -172,7 +173,7 @@ static mlir::LogicalResult convertOpToCall(OpTy op, return mlir::success(); } -struct CufAllocateOpConversion +struct CUFAllocateOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; @@ -215,7 +216,7 @@ struct CufAllocateOpConversion } }; -struct CufDeallocateOpConversion +struct CUFDeallocateOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; @@ -283,10 +284,10 @@ static int computeWidth(mlir::Location loc, mlir::Type type, return width; } -struct CufAllocOpConversion : public mlir::OpRewritePattern { +struct CUFAllocOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; - CufAllocOpConversion(mlir::MLIRContext *context, mlir::DataLayout *dl, + CUFAllocOpConversion(mlir::MLIRContext *context, mlir::DataLayout *dl, const fir::LLVMTypeConverter *typeConverter) : OpRewritePattern(context), dl{dl}, typeConverter{typeConverter} {} @@ -379,7 +380,7 @@ private: const fir::LLVMTypeConverter *typeConverter; }; -struct CufFreeOpConversion : public mlir::OpRewritePattern { +struct CUFFreeOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; mlir::LogicalResult @@ -428,11 +429,11 @@ struct CufFreeOpConversion : public mlir::OpRewritePattern { } }; -struct CufDataTransferOpConversion +struct CUFDataTransferOpConversion : public mlir::OpRewritePattern { using OpRewritePattern::OpRewritePattern; - CufDataTransferOpConversion(mlir::MLIRContext *context, + CUFDataTransferOpConversion(mlir::MLIRContext *context, const mlir::SymbolTable &symtab) : OpRewritePattern(context), symtab{symtab} {} @@ -528,8 +529,8 @@ struct CufDataTransferOpConversion mlir::Value sourceFile = fir::factory::locationToFilename(builder, loc); mlir::Value sourceLine = fir::factory::locationToLineNo(builder, loc, fTy.getInput(4)); - mlir::Value dst = builder.loadIfRef(loc, op.getDst()); - mlir::Value src = builder.loadIfRef(loc, op.getSrc()); + mlir::Value dst = op.getDst(); + mlir::Value src = op.getSrc(); llvm::SmallVector args{fir::runtime::createArguments( builder, loc, fTy, dst, src, modeValue, sourceFile, sourceLine)}; builder.create(loc, func, args); @@ -602,11 +603,8 @@ struct CufDataTransferOpConversion mlir::Value sourceFile = fir::factory::locationToFilename(builder, loc); mlir::Value sourceLine = fir::factory::locationToLineNo(builder, loc, fTy.getInput(5)); - mlir::Value dst = - dstIsDesc ? builder.loadIfRef(loc, op.getDst()) : op.getDst(); - mlir::Value src = mlir::isa(srcTy) - ? builder.loadIfRef(loc, op.getSrc()) - : op.getSrc(); + mlir::Value dst = op.getDst(); + mlir::Value src = op.getSrc(); llvm::SmallVector args{ fir::runtime::createArguments(builder, loc, fTy, dst, src, bytes, modeValue, sourceFile, sourceLine)}; @@ -620,6 +618,69 @@ private: const mlir::SymbolTable &symtab; }; +struct CUFLaunchOpConversion + : public mlir::OpRewritePattern { +public: + using OpRewritePattern::OpRewritePattern; + + CUFLaunchOpConversion(mlir::MLIRContext *context, + const mlir::SymbolTable &symTab) + : OpRewritePattern(context), symTab{symTab} {} + + mlir::LogicalResult + matchAndRewrite(cuf::KernelLaunchOp op, + mlir::PatternRewriter &rewriter) const override { + mlir::Location loc = op.getLoc(); + auto idxTy = mlir::IndexType::get(op.getContext()); + auto zero = rewriter.create( + loc, rewriter.getIntegerType(32), rewriter.getI32IntegerAttr(0)); + auto gridSizeX = + rewriter.create(loc, idxTy, op.getGridX()); + auto gridSizeY = + rewriter.create(loc, idxTy, op.getGridY()); + auto gridSizeZ = + rewriter.create(loc, idxTy, op.getGridZ()); + auto blockSizeX = + rewriter.create(loc, idxTy, op.getBlockX()); + auto blockSizeY = + rewriter.create(loc, idxTy, op.getBlockY()); + auto blockSizeZ = + rewriter.create(loc, idxTy, op.getBlockZ()); + auto kernelName = mlir::SymbolRefAttr::get( + rewriter.getStringAttr(cudaDeviceModuleName), + {mlir::SymbolRefAttr::get( + rewriter.getContext(), + op.getCallee().getLeafReference().getValue())}); + mlir::Value clusterDimX, clusterDimY, clusterDimZ; + if (auto funcOp = symTab.lookup( + op.getCallee().getLeafReference())) { + if (auto clusterDimsAttr = funcOp->getAttrOfType( + cuf::getClusterDimsAttrName())) { + clusterDimX = rewriter.create( + loc, clusterDimsAttr.getX().getInt()); + clusterDimY = rewriter.create( + loc, clusterDimsAttr.getY().getInt()); + clusterDimZ = rewriter.create( + loc, clusterDimsAttr.getZ().getInt()); + } + } + auto gpuLaunchOp = rewriter.create( + loc, kernelName, mlir::gpu::KernelDim3{gridSizeX, gridSizeY, gridSizeZ}, + mlir::gpu::KernelDim3{blockSizeX, blockSizeY, blockSizeZ}, zero, + op.getArgs()); + if (clusterDimX && clusterDimY && clusterDimZ) { + gpuLaunchOp.getClusterSizeXMutable().assign(clusterDimX); + gpuLaunchOp.getClusterSizeYMutable().assign(clusterDimY); + gpuLaunchOp.getClusterSizeZMutable().assign(clusterDimZ); + } + rewriter.replaceOp(op, gpuLaunchOp); + return mlir::success(); + } + +private: + const mlir::SymbolTable &symTab; +}; + class CUFOpConversion : public fir::impl::CUFOpConversionBase { public: void runOnOperation() override { @@ -637,7 +698,8 @@ public: fir::support::getOrSetDataLayout(module, /*allowDefaultLayout=*/false); fir::LLVMTypeConverter typeConverter(module, /*applyTBAA=*/false, /*forceUnifiedTBAATree=*/false, *dl); - target.addLegalDialect(); + target.addLegalDialect(); cuf::populateCUFToFIRConversionPatterns(typeConverter, *dl, symtab, patterns); if (mlir::failed(mlir::applyPartialConversion(getOperation(), target, @@ -653,8 +715,9 @@ public: void cuf::populateCUFToFIRConversionPatterns( const fir::LLVMTypeConverter &converter, mlir::DataLayout &dl, const mlir::SymbolTable &symtab, mlir::RewritePatternSet &patterns) { - patterns.insert(patterns.getContext(), &dl, &converter); - patterns.insert(patterns.getContext()); - patterns.insert(patterns.getContext(), symtab); + patterns.insert(patterns.getContext(), &dl, &converter); + patterns.insert(patterns.getContext()); + patterns.insert( + patterns.getContext(), symtab); } diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp index 8e516734a9087904778ce4b92304746ffd8551e3..a070c87137fa16eacd3c0ef62d080b8caed1af77 100644 --- a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp +++ b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp @@ -271,6 +271,19 @@ static bool canCacheThisType(mlir::LLVM::DICompositeTypeAttr comTy) { return true; } +std::pair +DebugTypeGenerator::getFieldSizeAndAlign(mlir::Type fieldTy) { + mlir::Type llvmTy; + if (auto boxTy = mlir::dyn_cast_or_null(fieldTy)) + llvmTy = llvmTypeConverter.convertBoxTypeAsStruct(boxTy, getBoxRank(boxTy)); + else + llvmTy = llvmTypeConverter.convertType(fieldTy); + + uint64_t byteSize = dataLayout->getTypeSize(llvmTy); + unsigned short byteAlign = dataLayout->getTypeABIAlignment(llvmTy); + return std::pair{byteSize, byteAlign}; +} + mlir::LLVM::DITypeAttr DebugTypeGenerator::convertRecordType( fir::RecordType Ty, mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp) { @@ -303,15 +316,7 @@ mlir::LLVM::DITypeAttr DebugTypeGenerator::convertRecordType( mlir::IntegerType intTy = mlir::IntegerType::get(context, 64); std::uint64_t offset = 0; for (auto [fieldName, fieldTy] : Ty.getTypeList()) { - mlir::Type llvmTy; - if (auto boxTy = mlir::dyn_cast_or_null(fieldTy)) - llvmTy = - llvmTypeConverter.convertBoxTypeAsStruct(boxTy, getBoxRank(boxTy)); - else - llvmTy = llvmTypeConverter.convertType(fieldTy); - - uint64_t byteSize = dataLayout->getTypeSize(llvmTy); - unsigned short byteAlign = dataLayout->getTypeABIAlignment(llvmTy); + auto [byteSize, byteAlign] = getFieldSizeAndAlign(fieldTy); std::optional> lowerBounds = fir::getComponentLowerBoundsIfNonDefault(Ty, fieldName, module, symbolTable); @@ -368,6 +373,42 @@ mlir::LLVM::DITypeAttr DebugTypeGenerator::convertRecordType( return finalAttr; } +mlir::LLVM::DITypeAttr DebugTypeGenerator::convertTupleType( + mlir::TupleType Ty, mlir::LLVM::DIFileAttr fileAttr, + mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp) { + // Check if this type has already been converted. + auto iter = typeCache.find(Ty); + if (iter != typeCache.end()) + return iter->second; + + llvm::SmallVector elements; + mlir::MLIRContext *context = module.getContext(); + + std::uint64_t offset = 0; + for (auto fieldTy : Ty.getTypes()) { + auto [byteSize, byteAlign] = getFieldSizeAndAlign(fieldTy); + mlir::LLVM::DITypeAttr elemTy = + convertType(fieldTy, fileAttr, scope, /*declOp=*/nullptr); + offset = llvm::alignTo(offset, byteAlign); + mlir::LLVM::DIDerivedTypeAttr tyAttr = mlir::LLVM::DIDerivedTypeAttr::get( + context, llvm::dwarf::DW_TAG_member, mlir::StringAttr::get(context, ""), + elemTy, byteSize * 8, byteAlign * 8, offset * 8, + /*optional
=*/std::nullopt, + /*extra data=*/nullptr); + elements.push_back(tyAttr); + offset += llvm::alignTo(byteSize, byteAlign); + } + + auto typeAttr = mlir::LLVM::DICompositeTypeAttr::get( + context, llvm::dwarf::DW_TAG_structure_type, + mlir::StringAttr::get(context, ""), fileAttr, /*line=*/0, scope, + /*baseType=*/nullptr, mlir::LLVM::DIFlags::Zero, offset * 8, + /*alignInBits=*/0, elements, /*dataLocation=*/nullptr, /*rank=*/nullptr, + /*allocated=*/nullptr, /*associated=*/nullptr); + typeCache[Ty] = typeAttr; + return typeAttr; +} + mlir::LLVM::DITypeAttr DebugTypeGenerator::convertSequenceType( fir::SequenceType seqTy, mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp) { @@ -574,6 +615,8 @@ DebugTypeGenerator::convertType(mlir::Type Ty, mlir::LLVM::DIFileAttr fileAttr, /*hasDescriptor=*/false); } else if (auto recTy = mlir::dyn_cast_or_null(Ty)) { return convertRecordType(recTy, fileAttr, scope, declOp); + } else if (auto tupleTy = mlir::dyn_cast_if_present(Ty)) { + return convertTupleType(tupleTy, fileAttr, scope, declOp); } else if (auto refTy = mlir::dyn_cast_if_present(Ty)) { auto elTy = refTy.getEleTy(); return convertPointerLikeType(elTy, fileAttr, scope, declOp, diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h index eeefb6c463d936603d42c256ad877caae71fea59..c1fce4bdae5ce5e1186ead5d13896fb7b600b694 100644 --- a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h +++ b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h @@ -39,6 +39,10 @@ private: mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp); + mlir::LLVM::DITypeAttr convertTupleType(mlir::TupleType Ty, + mlir::LLVM::DIFileAttr fileAttr, + mlir::LLVM::DIScopeAttr scope, + fir::cg::XDeclareOp declOp); mlir::LLVM::DITypeAttr convertSequenceType(fir::SequenceType seqTy, mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, @@ -73,6 +77,8 @@ private: mlir::LLVM::DIFileAttr fileAttr, mlir::LLVM::DIScopeAttr scope, fir::cg::XDeclareOp declOp); + std::pair + getFieldSizeAndAlign(mlir::Type fieldTy); mlir::ModuleOp module; mlir::SymbolTable *symbolTable; diff --git a/flang/lib/Parser/openmp-parsers.cpp b/flang/lib/Parser/openmp-parsers.cpp index 598439cbee87e644e8a4a2122c50f0e0113c27eb..6fde70fc5c3878b825cef29e4769c4598b5066ec 100644 --- a/flang/lib/Parser/openmp-parsers.cpp +++ b/flang/lib/Parser/openmp-parsers.cpp @@ -366,9 +366,12 @@ TYPE_PARSER( construct(name, maybe(Parser{}))) TYPE_PARSER(construct( + "DEPOBJ" >> pure(OmpTaskDependenceType::Type::Depobj) || "IN"_id >> pure(OmpTaskDependenceType::Type::In) || "INOUT" >> pure(OmpTaskDependenceType::Type::Inout) || - "OUT" >> pure(OmpTaskDependenceType::Type::Out))) + "OUT" >> pure(OmpTaskDependenceType::Type::Out) || + "SINK" >> pure(OmpTaskDependenceType::Type::Sink) || + "SOURCE" >> pure(OmpTaskDependenceType::Type::Source))) TYPE_CONTEXT_PARSER("Omp Depend clause"_en_US, construct(construct( @@ -454,6 +457,9 @@ TYPE_PARSER( parenthesized(Parser{}))) || "DEPEND" >> construct(construct( parenthesized(Parser{}))) || + "DESTROY" >> + construct(construct(maybe(parenthesized( + construct(Parser{}))))) || "DEVICE" >> construct(construct( parenthesized(Parser{}))) || "DEVICE_TYPE" >> construct(construct( @@ -560,7 +566,9 @@ TYPE_PARSER( construct(construct()) || "UNIFORM" >> construct(construct( parenthesized(nonemptyList(name)))) || - "UNTIED" >> construct(construct())) + "UNTIED" >> construct(construct()) || + "UPDATE" >> construct(construct( + parenthesized(Parser{})))) // [Clause, [Clause], ...] TYPE_PARSER(sourced(construct( @@ -583,12 +591,19 @@ TYPE_PARSER(sourced(construct(first( "MASKED TASKLOOP SIMD" >> pure(llvm::omp::Directive::OMPD_masked_taskloop_simd), "MASKED TASKLOOP" >> pure(llvm::omp::Directive::OMPD_masked_taskloop), + "MASTER TASKLOOP SIMD" >> + pure(llvm::omp::Directive::OMPD_master_taskloop_simd), + "MASTER TASKLOOP" >> pure(llvm::omp::Directive::OMPD_master_taskloop), "PARALLEL DO SIMD" >> pure(llvm::omp::Directive::OMPD_parallel_do_simd), "PARALLEL DO" >> pure(llvm::omp::Directive::OMPD_parallel_do), "PARALLEL MASKED TASKLOOP SIMD" >> pure(llvm::omp::Directive::OMPD_parallel_masked_taskloop_simd), "PARALLEL MASKED TASKLOOP" >> pure(llvm::omp::Directive::OMPD_parallel_masked_taskloop), + "PARALLEL MASTER TASKLOOP SIMD" >> + pure(llvm::omp::Directive::OMPD_parallel_master_taskloop_simd), + "PARALLEL MASTER TASKLOOP" >> + pure(llvm::omp::Directive::OMPD_parallel_master_taskloop), "SIMD" >> pure(llvm::omp::Directive::OMPD_simd), "TARGET LOOP" >> pure(llvm::omp::Directive::OMPD_target_loop), "TARGET PARALLEL DO SIMD" >> @@ -673,6 +688,9 @@ TYPE_PARSER(sourced(construct( TYPE_PARSER(sourced(construct( many(maybe(","_tok) >> sourced(Parser{}))))) +TYPE_PARSER(sourced(construct(verbatim("DEPOBJ"_tok), + parenthesized(Parser{}), sourced(Parser{})))) + TYPE_PARSER(sourced(construct(verbatim("FLUSH"_tok), many(maybe(","_tok) >> sourced(Parser{})), maybe(parenthesized(Parser{}))))) @@ -697,7 +715,8 @@ TYPE_PARSER( construct(Parser{}) || construct(Parser{}) || construct( - Parser{})) / + Parser{}) || + construct(Parser{})) / endOfLine) // Directives enclosing structured-block @@ -706,6 +725,7 @@ TYPE_PARSER(construct(first( "MASTER" >> pure(llvm::omp::Directive::OMPD_master), "ORDERED" >> pure(llvm::omp::Directive::OMPD_ordered), "PARALLEL MASKED" >> pure(llvm::omp::Directive::OMPD_parallel_masked), + "PARALLEL MASTER" >> pure(llvm::omp::Directive::OMPD_parallel_master), "PARALLEL WORKSHARE" >> pure(llvm::omp::Directive::OMPD_parallel_workshare), "PARALLEL" >> pure(llvm::omp::Directive::OMPD_parallel), "SCOPE" >> pure(llvm::omp::Directive::OMPD_scope), diff --git a/flang/lib/Parser/parse-tree.cpp b/flang/lib/Parser/parse-tree.cpp index 948ad04a091a8cf3e63cf821f24ccd5d9a12e0a9..60aef1666e9ba7f9a4b3aa48d3f21ba1c45cfd7e 100644 --- a/flang/lib/Parser/parse-tree.cpp +++ b/flang/lib/Parser/parse-tree.cpp @@ -252,6 +252,23 @@ CharBlock Variable::GetSource() const { llvm::raw_ostream &operator<<(llvm::raw_ostream &os, const Name &x) { return os << x.ToString(); } + +OmpTaskDependenceType::Type OmpDependClause::GetDepType() const { + return common::visit( + common::visitors{ + [&](const parser::OmpDependClause::Source &) { + return parser::OmpTaskDependenceType::Type::Source; + }, + [&](const parser::OmpDependClause::Sink &) { + return parser::OmpTaskDependenceType::Type::Sink; + }, + [&](const parser::OmpDependClause::InOut &y) { + return std::get(y.t).v; + }, + }, + u); +} + } // namespace Fortran::parser template static llvm::omp::Clause getClauseIdForClass(C &&) { diff --git a/flang/lib/Parser/unparse.cpp b/flang/lib/Parser/unparse.cpp index 39fcb61609e33b3f686cb672d68f65b7ae8b5bcb..3b0824f80161f4c177ccd1decbde42a0c18a40a4 100644 --- a/flang/lib/Parser/unparse.cpp +++ b/flang/lib/Parser/unparse.cpp @@ -2215,11 +2215,9 @@ public: Walk(std::get>(x.t)); } void Unparse(const OmpDependClause::InOut &x) { - Put("("); Walk(std::get(x.t)); Put(":"); Walk(std::get(x.t)); - Put(")"); } bool Pre(const OmpDependClause &x) { return common::visit( @@ -2274,6 +2272,12 @@ public: case llvm::omp::Directive::OMPD_masked_taskloop: Word("MASKED TASKLOOP"); break; + case llvm::omp::Directive::OMPD_master_taskloop_simd: + Word("MASTER TASKLOOP SIMD"); + break; + case llvm::omp::Directive::OMPD_master_taskloop: + Word("MASTER TASKLOOP"); + break; case llvm::omp::Directive::OMPD_parallel_do: Word("PARALLEL DO "); break; @@ -2286,6 +2290,12 @@ public: case llvm::omp::Directive::OMPD_parallel_masked_taskloop: Word("PARALLEL MASKED TASKLOOP"); break; + case llvm::omp::Directive::OMPD_parallel_master_taskloop_simd: + Word("PARALLEL MASTER TASKLOOP SIMD"); + break; + case llvm::omp::Directive::OMPD_parallel_master_taskloop: + Word("PARALLEL MASTER TASKLOOP"); + break; case llvm::omp::Directive::OMPD_simd: Word("SIMD "); break; @@ -2390,6 +2400,9 @@ public: case llvm::omp::Directive::OMPD_parallel_masked: Word("PARALLEL MASKED"); break; + case llvm::omp::Directive::OMPD_parallel_master: + Word("PARALLEL MASTER"); + break; case llvm::omp::Directive::OMPD_parallel_workshare: Word("PARALLEL WORKSHARE "); break; @@ -2706,6 +2719,16 @@ public: }, x.u); } + void Unparse(const OpenMPDepobjConstruct &x) { + BeginOpenMP(); + Word("!$OMP DEPOBJ"); + Put("("); + Walk(std::get(x.t)); + Put(") "); + Walk(std::get(x.t)); + Put("\n"); + EndOpenMP(); + } void Unparse(const OpenMPFlushConstruct &x) { BeginOpenMP(); Word("!$OMP FLUSH "); diff --git a/flang/lib/Semantics/check-omp-structure.cpp b/flang/lib/Semantics/check-omp-structure.cpp index c2bd1498dd7ec271b6a35794cf041b36b0c8d984..05d12086956c56e1f9af34b840c2368c7dabcbb8 100644 --- a/flang/lib/Semantics/check-omp-structure.cpp +++ b/flang/lib/Semantics/check-omp-structure.cpp @@ -1261,6 +1261,39 @@ void OmpStructureChecker::Leave(const parser::OpenMPDeclareSimdConstruct &) { dirContext_.pop_back(); } +void OmpStructureChecker::Enter(const parser::OpenMPDepobjConstruct &x) { + const auto &dir{std::get(x.t)}; + PushContextAndClauseSets(dir.source, llvm::omp::Directive::OMPD_depobj); + + // [5.2:73:27-28] + // If the destroy clause appears on a depobj construct, destroy-var must + // refer to the same depend object as the depobj argument of the construct. + auto &clause{std::get(x.t)}; + if (clause.Id() == llvm::omp::Clause::OMPC_destroy) { + auto getSymbol{[&](const parser::OmpObject &obj) { + return common::visit( + [&](auto &&s) { return GetLastName(s).symbol; }, obj.u); + }}; + + auto &wrapper{std::get(clause.u)}; + if (const std::optional &destroy{wrapper.v}) { + const Symbol *constrSym{getSymbol(std::get(x.t))}; + const Symbol *clauseSym{getSymbol(destroy->v)}; + assert(constrSym && "Unresolved depobj construct symbol"); + assert(clauseSym && "Unresolved destroy symbol on depobj construct"); + if (constrSym != clauseSym) { + context_.Say(x.source, + "The DESTROY clause must refer to the same object as the " + "DEPOBJ construct"_err_en_US); + } + } + } +} + +void OmpStructureChecker::Leave(const parser::OpenMPDepobjConstruct &x) { + dirContext_.pop_back(); +} + void OmpStructureChecker::Enter(const parser::OpenMPRequiresConstruct &x) { const auto &dir{std::get(x.t)}; PushContextAndClauseSets(dir.source, llvm::omp::Directive::OMPD_requires); @@ -2476,7 +2509,6 @@ CHECK_SIMPLE_CLAUSE(Capture, OMPC_capture) CHECK_SIMPLE_CLAUSE(Contains, OMPC_contains) CHECK_SIMPLE_CLAUSE(Default, OMPC_default) CHECK_SIMPLE_CLAUSE(Depobj, OMPC_depobj) -CHECK_SIMPLE_CLAUSE(Destroy, OMPC_destroy) CHECK_SIMPLE_CLAUSE(Detach, OMPC_detach) CHECK_SIMPLE_CLAUSE(DeviceType, OMPC_device_type) CHECK_SIMPLE_CLAUSE(DistSchedule, OMPC_dist_schedule) @@ -2519,7 +2551,6 @@ CHECK_SIMPLE_CLAUSE(Uniform, OMPC_uniform) CHECK_SIMPLE_CLAUSE(Unknown, OMPC_unknown) CHECK_SIMPLE_CLAUSE(Untied, OMPC_untied) CHECK_SIMPLE_CLAUSE(UsesAllocators, OMPC_uses_allocators) -CHECK_SIMPLE_CLAUSE(Update, OMPC_update) CHECK_SIMPLE_CLAUSE(Write, OMPC_write) CHECK_SIMPLE_CLAUSE(Init, OMPC_init) CHECK_SIMPLE_CLAUSE(Use, OMPC_use) @@ -2579,6 +2610,22 @@ void OmpStructureChecker::Enter(const parser::OmpClause::SpreadSchedule &x) { // Restrictions specific to each clause are implemented apart from the // generalized restrictions. + +void OmpStructureChecker::Enter(const parser::OmpClause::Destroy &x) { + CheckAllowedClause(llvm::omp::Clause::OMPC_destroy); + + llvm::omp::Directive dir{GetContext().directive}; + unsigned version{context_.langOptions().OpenMPVersion}; + if (dir == llvm::omp::Directive::OMPD_depobj) { + if (version < 52) { + context_.Say(GetContext().clauseSource, + "The object parameter in DESTROY clause in DEPOPJ construct " + "was introduced in %s"_port_en_US, + ThisVersion(52)); + } + } +} + void OmpStructureChecker::Enter(const parser::OmpClause::Reduction &x) { CheckAllowedClause(llvm::omp::Clause::OMPC_reduction); if (CheckReductionOperators(x)) { @@ -3309,16 +3356,63 @@ void OmpStructureChecker::Enter(const parser::OmpClause::Device &x) { void OmpStructureChecker::Enter(const parser::OmpClause::Depend &x) { CheckAllowedClause(llvm::omp::Clause::OMPC_depend); - if ((std::holds_alternative(x.v.u) || - std::holds_alternative(x.v.u)) && - GetContext().directive != llvm::omp::OMPD_ordered) { - context_.Say(GetContext().clauseSource, - "DEPEND(SOURCE) or DEPEND(SINK : vec) can be used only with the ordered" - " directive. Used here in the %s construct."_err_en_US, - parser::ToUpperCaseLetters(getDirectiveName(GetContext().directive))); + llvm::omp::Directive directive{GetContext().directive}; + unsigned version{context_.langOptions().OpenMPVersion}; + + using DepType = parser::OmpTaskDependenceType::Type; + DepType depType = x.v.GetDepType(); + + if (version >= 52) { + switch (depType) { + case DepType::Sink: + case DepType::Source: + context_.Say(GetContext().clauseSource, + "The %s task-dependence-type is deprecated in %s"_warn_en_US, + parser::ToUpperCaseLetters( + parser::OmpTaskDependenceType::EnumToString(depType)), + ThisVersion(version)); + break; + default: + break; + } + } + + if (directive == llvm::omp::OMPD_depobj) { + // [5.0:255:11], [5.1:288:3] + // A depend clause on a depobj construct must not have source, sink [or + // depobj](5.0) as dependence-type. + if (version >= 50) { + bool invalidDep{depType == DepType::Source || depType == DepType::Sink}; + if (version == 50) { + invalidDep = invalidDep || depType == DepType::Depobj; + } + if (invalidDep) { + context_.Say(GetContext().clauseSource, + "A DEPEND clause on a DEPOBJ construct must not have SOURCE%s " + "as dependence-type"_err_en_US, + version == 50 ? ", SINK or DEPOBJ" : " or SINK"); + } + } + } else if (directive != llvm::omp::OMPD_ordered) { + if (depType == DepType::Source || depType == DepType::Sink) { + context_.Say(GetContext().clauseSource, + "DEPEND(SOURCE) or DEPEND(SINK : vec) can be used only with the " + "ordered directive. Used here in the %s construct."_err_en_US, + parser::ToUpperCaseLetters(getDirectiveName(directive))); + } } if (const auto *inOut{std::get_if(&x.v.u)}) { - for (const auto &object : std::get(inOut->t).v) { + auto &objList{std::get(inOut->t)}; + if (directive == llvm::omp::OMPD_depobj) { + // [5.0:255:13], [5.1:288:6], [5.2:322:26] + // A depend clause on a depobj construct must only specify one locator. + if (objList.v.size() != 1) { + context_.Say(GetContext().clauseSource, + "A DEPEND clause on a DEPOBJ construct must only specify " + "one locator"_err_en_US); + } + } + for (const auto &object : objList.v) { if (const auto *name{std::get_if(&object.u)}) { context_.Say(GetContext().clauseSource, "Common block name ('%s') cannot appear in a DEPEND " @@ -3337,12 +3431,18 @@ void OmpStructureChecker::Enter(const parser::OmpClause::Depend &x) { } } if (std::get>(inOut->t)) { - unsigned version{context_.langOptions().OpenMPVersion}; unsigned allowedInVersion{50}; if (version < allowedInVersion) { context_.Say(GetContext().clauseSource, "Iterator modifiers are not supported in %s, %s"_warn_en_US, ThisVersion(version), TryVersion(allowedInVersion)); + } else { + if (directive == llvm::omp::OMPD_depobj) { + context_.Say(GetContext().clauseSource, + "An iterator-modifier may specify multiple locators, " + "a DEPEND clause on a DEPOBJ construct must only specify " + "one locator"_warn_en_US); + } } } } @@ -3457,6 +3557,34 @@ void OmpStructureChecker::CheckStructureElement( return; } +void OmpStructureChecker::Enter(const parser::OmpClause::Update &x) { + CheckAllowedClause(llvm::omp::Clause::OMPC_update); + llvm::omp::Directive directive{GetContext().directive}; + unsigned version{context_.langOptions().OpenMPVersion}; + + // [5.1:288:4-5] + // An update clause on a depobj construct must not have source, sink or depobj + // as dependence-type. + // [5.2:322:3] + // task-dependence-type must not be depobj. + if (directive == llvm::omp::OMPD_depobj) { + if (version >= 51) { + // Update -> OmpUpdateClause -> OmpTaskDependenceType -> Type + switch (x.v.v.v) { + case parser::OmpTaskDependenceType::Type::Source: + case parser::OmpTaskDependenceType::Type::Sink: + case parser::OmpTaskDependenceType::Type::Depobj: + context_.Say(GetContext().clauseSource, + "An UPDATE clause on a DEPOBJ construct must not have SOURCE, " + "SINK or DEPOBJ as dependence-type"_err_en_US); + break; + default: + break; + } + } + } +} + void OmpStructureChecker::Enter(const parser::OmpClause::UseDevicePtr &x) { CheckStructureElement(x.v, llvm::omp::Clause::OMPC_use_device_ptr); CheckAllowedClause(llvm::omp::Clause::OMPC_use_device_ptr); @@ -3640,7 +3768,7 @@ void OmpStructureChecker::CheckDependList(const parser::DataRef &d) { context_.Say(GetContext().clauseSource, "Coarrays are not supported in DEPEND clause"_err_en_US); }, - [&](const parser::Name &) { return; }, + [&](const parser::Name &) {}, }, d.u); } diff --git a/flang/lib/Semantics/check-omp-structure.h b/flang/lib/Semantics/check-omp-structure.h index 237569bc40c483d024059c444dfc64792f026f92..d5fd558cea237203538db90027c2589e786df1eb 100644 --- a/flang/lib/Semantics/check-omp-structure.h +++ b/flang/lib/Semantics/check-omp-structure.h @@ -92,6 +92,8 @@ public: void Leave(const parser::OpenMPDeclarativeAllocate &); void Enter(const parser::OpenMPDeclareTargetConstruct &); void Leave(const parser::OpenMPDeclareTargetConstruct &); + void Enter(const parser::OpenMPDepobjConstruct &); + void Leave(const parser::OpenMPDepobjConstruct &); void Enter(const parser::OmpDeclareTargetWithList &); void Enter(const parser::OmpDeclareTargetWithClause &); void Leave(const parser::OmpDeclareTargetWithClause &); diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp index 014b7987a658bd3598a11c614788e1b69a5e48f6..359dac911b8c7c7c60a8c7add40ea1b166ea8ebb 100644 --- a/flang/lib/Semantics/resolve-directives.cpp +++ b/flang/lib/Semantics/resolve-directives.cpp @@ -383,6 +383,14 @@ public: } void Post(const parser::OpenMPDeclareSimdConstruct &) { PopContext(); } + bool Pre(const parser::OpenMPDepobjConstruct &x) { + PushContext(x.source, llvm::omp::Directive::OMPD_depobj); + auto &object{std::get(x.t)}; + ResolveOmpObject(object, Symbol::Flag::OmpDependObject); + return true; + } + void Post(const parser::OpenMPDepobjConstruct &) { PopContext(); } + bool Pre(const parser::OpenMPRequiresConstruct &x) { using Flags = WithOmpDeclarative::RequiresFlags; using Requires = WithOmpDeclarative::RequiresFlag; @@ -1531,6 +1539,7 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPBlockConstruct &x) { case llvm::omp::Directive::OMPD_masked: case llvm::omp::Directive::OMPD_parallel_masked: case llvm::omp::Directive::OMPD_master: + case llvm::omp::Directive::OMPD_parallel_master: case llvm::omp::Directive::OMPD_ordered: case llvm::omp::Directive::OMPD_parallel: case llvm::omp::Directive::OMPD_scope: @@ -1550,7 +1559,8 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPBlockConstruct &x) { // TODO others break; } - if (beginDir.v == llvm::omp::Directive::OMPD_master) + if (beginDir.v == llvm::omp::Directive::OMPD_master || + beginDir.v == llvm::omp::Directive::OMPD_parallel_master) IssueNonConformanceWarning(beginDir.v, beginDir.source); ClearDataSharingAttributeObjects(); ClearPrivateDataSharingAttributeObjects(); @@ -1563,7 +1573,9 @@ void OmpAttributeVisitor::Post(const parser::OpenMPBlockConstruct &x) { const auto &beginDir{std::get(beginBlockDir.t)}; switch (beginDir.v) { case llvm::omp::Directive::OMPD_masked: + case llvm::omp::Directive::OMPD_master: case llvm::omp::Directive::OMPD_parallel_masked: + case llvm::omp::Directive::OMPD_parallel_master: case llvm::omp::Directive::OMPD_parallel: case llvm::omp::Directive::OMPD_scope: case llvm::omp::Directive::OMPD_single: @@ -1634,10 +1646,14 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPLoopConstruct &x) { case llvm::omp::Directive::OMPD_loop: case llvm::omp::Directive::OMPD_masked_taskloop_simd: case llvm::omp::Directive::OMPD_masked_taskloop: + case llvm::omp::Directive::OMPD_master_taskloop_simd: + case llvm::omp::Directive::OMPD_master_taskloop: case llvm::omp::Directive::OMPD_parallel_do: case llvm::omp::Directive::OMPD_parallel_do_simd: case llvm::omp::Directive::OMPD_parallel_masked_taskloop_simd: case llvm::omp::Directive::OMPD_parallel_masked_taskloop: + case llvm::omp::Directive::OMPD_parallel_master_taskloop_simd: + case llvm::omp::Directive::OMPD_parallel_master_taskloop: case llvm::omp::Directive::OMPD_simd: case llvm::omp::Directive::OMPD_target_loop: case llvm::omp::Directive::OMPD_target_parallel_do: @@ -1662,7 +1678,11 @@ bool OmpAttributeVisitor::Pre(const parser::OpenMPLoopConstruct &x) { default: break; } - if (beginDir.v == llvm::omp::Directive::OMPD_target_loop) + if (beginDir.v == llvm::omp::OMPD_master_taskloop || + beginDir.v == llvm::omp::OMPD_master_taskloop_simd || + beginDir.v == llvm::omp::OMPD_parallel_master_taskloop || + beginDir.v == llvm::omp::OMPD_parallel_master_taskloop_simd || + beginDir.v == llvm::omp::Directive::OMPD_target_loop) IssueNonConformanceWarning(beginDir.v, beginDir.source); ClearDataSharingAttributeObjects(); SetContextAssociatedLoopLevel(GetAssociatedLoopLevelFromClauses(clauseList)); @@ -2891,18 +2911,39 @@ void OmpAttributeVisitor::AddOmpRequiresToScope(Scope &scope, void OmpAttributeVisitor::IssueNonConformanceWarning( llvm::omp::Directive D, parser::CharBlock source) { - std::string warnStr = ""; - std::string dirName = llvm::omp::getOpenMPDirectiveName(D).str(); + std::string warnStr; + llvm::raw_string_ostream warnStrOS(warnStr); + warnStrOS << "OpenMP directive " + << parser::ToUpperCaseLetters( + llvm::omp::getOpenMPDirectiveName(D).str()) + << " has been deprecated"; + + auto setAlternativeStr = [&warnStrOS](llvm::StringRef alt) { + warnStrOS << ", please use " << alt << " instead."; + }; switch (D) { case llvm::omp::OMPD_master: - warnStr = "OpenMP directive '" + dirName + - "' has been deprecated, please use 'masked' instead."; + setAlternativeStr("MASKED"); + break; + case llvm::omp::OMPD_master_taskloop: + setAlternativeStr("MASKED TASKLOOP"); + break; + case llvm::omp::OMPD_master_taskloop_simd: + setAlternativeStr("MASKED TASKLOOP SIMD"); + break; + case llvm::omp::OMPD_parallel_master: + setAlternativeStr("PARALLEL MASKED"); + break; + case llvm::omp::OMPD_parallel_master_taskloop: + setAlternativeStr("PARALLEL MASKED TASKLOOP"); + break; + case llvm::omp::OMPD_parallel_master_taskloop_simd: + setAlternativeStr("PARALLEL_MASKED TASKLOOP SIMD"); break; case llvm::omp::OMPD_target_loop: - default: - warnStr = "OpenMP directive '" + dirName + "' has been deprecated."; + default:; } - context_.Warn( - common::UsageWarning::OpenMPUsage, source, "%s"_warn_en_US, warnStr); + context_.Warn(common::UsageWarning::OpenMPUsage, source, "%s"_warn_en_US, + warnStrOS.str()); } } // namespace Fortran::semantics diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index add4e4befd3a2b2c63ed74a56a1b17025641c707..e0a8246ebc752ebd916e37bcd7f5d156d366337f 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -1538,6 +1538,13 @@ public: void Post(const parser::OpenMPDeclarativeConstruct &) { messageHandler().set_currStmtSource(std::nullopt); } + bool Pre(const parser::OpenMPDepobjConstruct &x) { + AddOmpSourceRange(x.source); + return true; + } + void Post(const parser::OpenMPDepobjConstruct &x) { + messageHandler().set_currStmtSource(std::nullopt); + } bool Pre(const parser::OpenMPAtomicConstruct &x) { return common::visit(common::visitors{[&](const auto &u) -> bool { AddOmpSourceRange(u.source); diff --git a/flang/runtime/CUDA/kernel.cpp b/flang/runtime/CUDA/kernel.cpp index f81153a1af4bc77e703637438785f0ce279eac2b..abb7ebb72e592317c82a9a6d79b8b3b7c016ab92 100644 --- a/flang/runtime/CUDA/kernel.cpp +++ b/flang/runtime/CUDA/kernel.cpp @@ -25,9 +25,32 @@ void RTDEF(CUFLaunchKernel)(const void *kernel, intptr_t gridX, intptr_t gridY, blockDim.x = blockX; blockDim.y = blockY; blockDim.z = blockZ; - cudaStream_t stream = 0; + cudaStream_t stream = 0; // TODO stream managment CUDA_REPORT_IF_ERROR( cudaLaunchKernel(kernel, gridDim, blockDim, params, smem, stream)); } +void RTDEF(CUFLaunchClusterKernel)(const void *kernel, intptr_t clusterX, + intptr_t clusterY, intptr_t clusterZ, intptr_t gridX, intptr_t gridY, + intptr_t gridZ, intptr_t blockX, intptr_t blockY, intptr_t blockZ, + int32_t smem, void **params, void **extra) { + cudaLaunchConfig_t config; + config.gridDim.x = gridX; + config.gridDim.y = gridY; + config.gridDim.z = gridZ; + config.blockDim.x = blockX; + config.blockDim.y = blockY; + config.blockDim.z = blockZ; + config.dynamicSmemBytes = smem; + config.stream = 0; // TODO stream managment + cudaLaunchAttribute launchAttr[1]; + launchAttr[0].id = cudaLaunchAttributeClusterDimension; + launchAttr[0].val.clusterDim.x = clusterX; + launchAttr[0].val.clusterDim.y = clusterY; + launchAttr[0].val.clusterDim.z = clusterZ; + config.numAttrs = 1; + config.attrs = launchAttr; + CUDA_REPORT_IF_ERROR(cudaLaunchKernelExC(&config, kernel, params)); +} + } // extern "C" diff --git a/flang/runtime/CUDA/memory.cpp b/flang/runtime/CUDA/memory.cpp index fc48b4343eea9dd1223cf5173d6af7cf79a7e711..4778a4ae77683f6a4073b6e89e5b70c83945f82e 100644 --- a/flang/runtime/CUDA/memory.cpp +++ b/flang/runtime/CUDA/memory.cpp @@ -73,23 +73,22 @@ void RTDEF(CUFDataTransferPtrPtr)(void *dst, void *src, std::size_t bytes, CUDA_REPORT_IF_ERROR(cudaMemcpy(dst, src, bytes, kind)); } -void RTDEF(CUFDataTransferDescPtr)(const Descriptor &desc, void *addr, +void RTDEF(CUFDataTransferDescPtr)(Descriptor *desc, void *addr, std::size_t bytes, unsigned mode, const char *sourceFile, int sourceLine) { Terminator terminator{sourceFile, sourceLine}; terminator.Crash( "not yet implemented: CUDA data transfer from a pointer to a descriptor"); } -void RTDEF(CUFDataTransferPtrDesc)(void *addr, const Descriptor &desc, +void RTDEF(CUFDataTransferPtrDesc)(void *addr, Descriptor *desc, std::size_t bytes, unsigned mode, const char *sourceFile, int sourceLine) { Terminator terminator{sourceFile, sourceLine}; terminator.Crash( "not yet implemented: CUDA data transfer from a descriptor to a pointer"); } -void RTDECL(CUFDataTransferDescDesc)(const Descriptor &dstDesc, - const Descriptor &srcDesc, unsigned mode, const char *sourceFile, - int sourceLine) { +void RTDECL(CUFDataTransferDescDesc)(Descriptor *dstDesc, Descriptor *srcDesc, + unsigned mode, const char *sourceFile, int sourceLine) { Terminator terminator{sourceFile, sourceLine}; terminator.Crash( "not yet implemented: CUDA data transfer between two descriptors"); diff --git a/flang/test/Driver/mabi.f90 b/flang/test/Driver/mabi.f90 new file mode 100644 index 0000000000000000000000000000000000000000..88fd4d2a993fb04cc3868876222b591c0914b030 --- /dev/null +++ b/flang/test/Driver/mabi.f90 @@ -0,0 +1,17 @@ +! RUN: not %flang -### -c --target=powerpc64le-unknown-linux -mabi=vec-extabi %s 2>&1 | FileCheck --check-prefix=INVALID1 %s +! RUN: not %flang -### -c --target=x86_64-unknown-linux -mabi=vec-extabi %s 2>&1 | FileCheck --check-prefix=INVALID2 %s +! RUN: not %flang -### -c --target=powerpc-unknown-aix -mabi=abc %s 2>&1 | FileCheck --check-prefix=INVALID3 %s +! RUN: %flang -### -c -target powerpc-unknown-aix %s 2>&1 | FileCheck --implicit-check-not=vec-extabi %s +! RUN: %flang -### -c -target powerpc-unknown-aix -mabi=vec-default %s 2>&1 | FileCheck --implicit-check-not=vec-extabi %s +! RUN: %flang -### -c -target powerpc-unknown-aix -mabi=vec-extabi %s 2>&1 | FileCheck --check-prefix=EXTABI %s + +! REQUIRES: target=powerpc{{.*}} + +! INVALID1: error: unsupported option '-mabi=vec-extabi' for target '{{.*}}' +! INVALID2: error: unsupported option '-mabi=' for target '{{.*}}' +! INVALID3: error: unsupported argument 'abc' to option '-mabi=' + +! EXTABI: "-fc1" +! EXTABI-SAME: "-mabi=vec-extabi" + + diff --git a/flang/test/Fir/CUDA/cuda-constructor-2.f90 b/flang/test/Fir/CUDA/cuda-constructor-2.f90 new file mode 100644 index 0000000000000000000000000000000000000000..378dabbb7c7e7d93de08321225ff5f2a7af37f87 --- /dev/null +++ b/flang/test/Fir/CUDA/cuda-constructor-2.f90 @@ -0,0 +1,22 @@ +// RUN: fir-opt --split-input-file --cuf-add-constructor %s | FileCheck %s + +module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>, fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", gpu.container_module, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", llvm.ident = "flang version 20.0.0 (https://github.com/llvm/llvm-project.git cae351f3453a0a26ec8eb2ddaf773c24a29d929e)", llvm.target_triple = "x86_64-unknown-linux-gnu"} { + + fir.global @_QMmtestsEn(dense<[3, 4, 5, 6, 7]> : tensor<5xi32>) {data_attr = #cuf.cuda} : !fir.array<5xi32> + + gpu.module @cuda_device_mod [#nvvm.target] { + } +} + +// CHECK: gpu.module @cuda_device_mod [#nvvm.target] + +// CHECK: llvm.func internal @__cudaFortranConstructor() { +// CHECK-DAG: %[[MODULE:.*]] = cuf.register_module @cuda_device_mod -> !llvm.ptr +// CHECK-DAG: %[[VAR_NAME:.*]] = fir.address_of(@_QQ{{.*}}) : !fir.ref> +// CHECK-DAG: %[[VAR_ADDR:.*]] = fir.address_of(@_QMmtestsEn) : !fir.ref> +// CHECK-DAG: %[[MODULE2:.*]] = fir.convert %[[MODULE]] : (!llvm.ptr) -> !fir.ref> +// CHECK-DAG: %[[VAR_ADDR2:.*]] = fir.convert %[[VAR_ADDR]] : (!fir.ref>) -> !fir.ref +// CHECK-DAG: %[[VAR_NAME2:.*]] = fir.convert %[[VAR_NAME]] : (!fir.ref>) -> !fir.ref +// CHECK-DAG: %[[CST:.*]] = arith.constant 20 : index +// CHECK-DAG %[[CST2:.*]] = fir.convert %[[CST]] : (index) -> i64 +// CHECK fir.call @_FortranACUFRegisterVariable(%[[MODULE2]], %[[VAR_ADDR2]], %[[VAR_NAME2]], %[[CST2]]) : (!fir.ref>, !fir.ref, !fir.ref, i64) -> none diff --git a/flang/test/Fir/CUDA/cuda-data-transfer.fir b/flang/test/Fir/CUDA/cuda-data-transfer.fir index c33c50115b9fc059f534d76fecc7f59945447ed2..b99e09fb76468b032b80fd113e09ad887374235f 100644 --- a/flang/test/Fir/CUDA/cuda-data-transfer.fir +++ b/flang/test/Fir/CUDA/cuda-data-transfer.fir @@ -15,11 +15,9 @@ func.func @_QPsub1() { // CHECK-LABEL: func.func @_QPsub1() // CHECK: %[[ADEV:.*]]:2 = hlfir.declare %{{.*}} {data_attr = #cuf.cuda, fortran_attrs = #fir.var_attrs, uniq_name = "_QFsub1Eadev"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) // CHECK: %[[AHOST:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = "_QFsub1Eahost"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -// CHECK: %[[AHOST_LOAD:.*]] = fir.load %[[AHOST]]#0 : !fir.ref>>> -// CHECK: %[[ADEV_LOAD:.*]] = fir.load %[[ADEV]]#0 : !fir.ref>>> -// CHECK: %[[AHOST_BOX:.*]] = fir.convert %[[AHOST_LOAD]] : (!fir.box>>) -> !fir.box -// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV_LOAD]] : (!fir.box>>) -> !fir.box -// CHECK: fir.call @_FortranACUFDataTransferDescDesc(%[[AHOST_BOX]], %[[ADEV_BOX]], %c1{{.*}}, %{{.*}}, %{{.*}}) : (!fir.box, !fir.box, i32, !fir.ref, i32) -> none +// CHECK: %[[AHOST_BOX:.*]] = fir.convert %[[AHOST]]#0 : (!fir.ref>>>) -> !fir.ref> +// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV]]#0 : (!fir.ref>>>) -> !fir.ref> +// CHECK: fir.call @_FortranACUFDataTransferDescDesc(%[[AHOST_BOX]], %[[ADEV_BOX]], %c1{{.*}}, %{{.*}}, %{{.*}}) : (!fir.ref>, !fir.ref>, i32, !fir.ref, i32) -> none func.func @_QPsub2() { %0 = cuf.alloc !fir.box>> {bindc_name = "adev", data_attr = #cuf.cuda, uniq_name = "_QFsub2Eadev"} -> !fir.ref>>> @@ -76,19 +74,17 @@ func.func @_QPsub4() { // CHECK: %[[NBELEM:.*]] = arith.constant 10 : index // CHECK: %[[WIDTH:.*]] = arith.constant 4 : index // CHECK: %[[BYTES:.*]] = arith.muli %[[NBELEM]], %[[WIDTH]] : index -// CHECK: %[[ADEV_LOAD:.*]] = fir.load %[[ADEV]]#0 : !fir.ref>>> -// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV_LOAD]] : (!fir.box>>) -> !fir.box +// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV]]#0 : (!fir.ref>>>) -> !fir.ref> // CHECK: %[[AHOST_PTR:.*]] = fir.convert %[[AHOST]]#0 : (!fir.ref>) -> !fir.llvm_ptr // CHECK: %[[BYTES_CONV:.*]] = fir.convert %[[BYTES]] : (index) -> i64 -// CHECK: fir.call @_FortranACUFDataTransferDescPtr(%[[ADEV_BOX]], %[[AHOST_PTR]], %[[BYTES_CONV]], %c0{{.*}}, %{{.*}}, %{{.*}}) : (!fir.box, !fir.llvm_ptr, i64, i32, !fir.ref, i32) -> none +// CHECK: fir.call @_FortranACUFDataTransferDescPtr(%[[ADEV_BOX]], %[[AHOST_PTR]], %[[BYTES_CONV]], %c0{{.*}}, %{{.*}}, %{{.*}}) : (!fir.ref>, !fir.llvm_ptr, i64, i32, !fir.ref, i32) -> none // CHECK: %[[NBELEM:.*]] = arith.constant 10 : index // CHECK: %[[WIDTH:.*]] = arith.constant 4 : index // CHECK: %[[BYTES:.*]] = arith.muli %[[NBELEM]], %[[WIDTH]] : index -// CHECK: %[[ADEV_LOAD:.*]] = fir.load %[[ADEV]]#0 : !fir.ref>>> // CHECK: %[[AHOST_PTR:.*]] = fir.convert %[[AHOST]]#0 : (!fir.ref>) -> !fir.llvm_ptr -// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV_LOAD]] : (!fir.box>>) -> !fir.box +// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV]]#0 : (!fir.ref>>>) -> !fir.ref> // CHECK: %[[BYTES_CONV:.*]] = fir.convert %[[BYTES]] : (index) -> i64 -// CHECK: fir.call @_FortranACUFDataTransferPtrDesc(%[[AHOST_PTR]], %[[ADEV_BOX]], %[[BYTES_CONV]], %c1{{.*}}, %{{.*}}, %{{.*}}) : (!fir.llvm_ptr, !fir.box, i64, i32, !fir.ref, i32) -> none +// CHECK: fir.call @_FortranACUFDataTransferPtrDesc(%[[AHOST_PTR]], %[[ADEV_BOX]], %[[BYTES_CONV]], %c1{{.*}}, %{{.*}}, %{{.*}}) : (!fir.llvm_ptr, !fir.ref>, i64, i32, !fir.ref, i32) -> none func.func @_QPsub5(%arg0: !fir.ref {fir.bindc_name = "n"}) { %0 = fir.dummy_scope : !fir.dscope @@ -122,19 +118,17 @@ func.func @_QPsub5(%arg0: !fir.ref {fir.bindc_name = "n"}) { // CHECK: %[[NBELEM:.*]] = arith.muli %[[I1]], %[[I2]] : index // CHECK: %[[WIDTH:.*]] = arith.constant 4 : index // CHECK: %[[BYTES:.*]] = arith.muli %[[NBELEM]], %[[WIDTH]] : index -// CHECK: %[[ADEV_LOAD:.*]] = fir.load %[[ADEV]]#0 : !fir.ref>>> -// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV_LOAD]] : (!fir.box>>) -> !fir.box +// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV]]#0 : (!fir.ref>>>) -> !fir.ref> // CHECK: %[[AHOST_PTR:.*]] = fir.convert %[[AHOST]]#1 : (!fir.ref>) -> !fir.llvm_ptr // CHECK: %[[BYTES_CONV:.*]] = fir.convert %[[BYTES]] : (index) -> i64 -// CHECK: fir.call @_FortranACUFDataTransferDescPtr(%[[ADEV_BOX]], %[[AHOST_PTR]], %[[BYTES_CONV]], %c0{{.*}}, %{{.*}}, %{{.*}}) : (!fir.box, !fir.llvm_ptr, i64, i32, !fir.ref, i32) -> none +// CHECK: fir.call @_FortranACUFDataTransferDescPtr(%[[ADEV_BOX]], %[[AHOST_PTR]], %[[BYTES_CONV]], %c0{{.*}}, %{{.*}}, %{{.*}}) : (!fir.ref>, !fir.llvm_ptr, i64, i32, !fir.ref, i32) -> none // CHECK: %[[NBELEM:.*]] = arith.muli %[[I1]], %[[I2]] : index // CHECK: %[[WIDTH:.*]] = arith.constant 4 : index // CHECK: %[[BYTES:.*]] = arith.muli %[[NBELEM]], %[[WIDTH]] : index -// CHECK: %[[ADEV_LOAD:.*]] = fir.load %[[ADEV]]#0 : !fir.ref>>> // CHECK: %[[AHOST_PTR:.*]] = fir.convert %[[AHOST]]#1 : (!fir.ref>) -> !fir.llvm_ptr -// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV_LOAD]] : (!fir.box>>) -> !fir.box +// CHECK: %[[ADEV_BOX:.*]] = fir.convert %[[ADEV]]#0 : (!fir.ref>>>) -> !fir.ref> // CHECK: %[[BYTES_CONV:.*]] = fir.convert %[[BYTES]] : (index) -> i64 -// CHECK: fir.call @_FortranACUFDataTransferPtrDesc(%[[AHOST_PTR]], %[[ADEV_BOX]], %[[BYTES_CONV]], %c1{{.*}}, %{{.*}}, %{{.*}}) : (!fir.llvm_ptr, !fir.box, i64, i32, !fir.ref, i32) -> none +// CHECK: fir.call @_FortranACUFDataTransferPtrDesc(%[[AHOST_PTR]], %[[ADEV_BOX]], %[[BYTES_CONV]], %c1{{.*}}, %{{.*}}, %{{.*}}) : (!fir.llvm_ptr, !fir.ref>, i64, i32, !fir.ref, i32) -> none func.func @_QPsub6() { %0 = cuf.alloc i32 {bindc_name = "idev", data_attr = #cuf.cuda, uniq_name = "_QFsub6Eidev"} -> !fir.ref diff --git a/flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir b/flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir index f10bd82f978dc4d4326f838368e4ce71a9389fee..7fede7c6c17b7807c5ff0949cf68e180f4fdeebb 100644 --- a/flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir +++ b/flang/test/Fir/CUDA/cuda-gpu-launch-func.mlir @@ -1,4 +1,4 @@ -// RUN: fir-opt --cuf-gpu-convert-to-llvm %s | FileCheck %s +// RUN: fir-opt --split-input-file --cuf-gpu-convert-to-llvm %s | FileCheck %s module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>, fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", gpu.container_module, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", llvm.ident = "flang version 20.0.0 (git@github.com:clementval/llvm-project.git ddcfd4d2dc17bf66cee8c3ef6284118684a2b0e6)", llvm.target_triple = "x86_64-unknown-linux-gnu"} { llvm.func @_QMmod1Phost_sub() { @@ -102,3 +102,25 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : ve // CHECK: %[[KERNEL_PTR:.*]] = llvm.mlir.addressof @_QMmod1Psub1 : !llvm.ptr // CHECK: llvm.call @_FortranACUFLaunchKernel(%[[KERNEL_PTR]], {{.*}}) + +// ----- + +module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>, fir.defaultkind = "a1c4d8i4l4r4", fir.kindmap = "", gpu.container_module, llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", llvm.ident = "flang version 20.0.0 (git@github.com:clementval/llvm-project.git 4116c1370ff76adf1e58eb3c39d0a14721794c70)", llvm.target_triple = "x86_64-unknown-linux-gnu"} { + llvm.func @_FortranACUFLaunchClusterKernel(!llvm.ptr, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, !llvm.ptr, !llvm.ptr) attributes {sym_visibility = "private"} + llvm.func @_QMmod1Psub1() attributes {cuf.cluster_dims = #cuf.cluster_dims} { + llvm.return + } + llvm.func @_QQmain() attributes {fir.bindc_name = "test"} { + %0 = llvm.mlir.constant(1 : index) : i64 + %1 = llvm.mlir.constant(2 : index) : i64 + %2 = llvm.mlir.constant(0 : i32) : i32 + %3 = llvm.mlir.constant(10 : index) : i64 + gpu.launch_func @cuda_device_mod::@_QMmod1Psub1 clusters in (%1, %1, %0) blocks in (%3, %3, %0) threads in (%3, %3, %0) : i64 dynamic_shared_memory_size %2 + llvm.return + } + gpu.binary @cuda_device_mod [#gpu.object<#nvvm.target, "">] +} + +// CHECK-LABEL: llvm.func @_QQmain() +// CHECK: %[[KERNEL_PTR:.*]] = llvm.mlir.addressof @_QMmod1Psub1 +// CHECK: llvm.call @_FortranACUFLaunchClusterKernel(%[[KERNEL_PTR]], {{.*}}) diff --git a/flang/test/Fir/CUDA/cuda-launch.fir b/flang/test/Fir/CUDA/cuda-launch.fir new file mode 100644 index 0000000000000000000000000000000000000000..f11bcbdb7fce55b28029d2d576c2035e835929d5 --- /dev/null +++ b/flang/test/Fir/CUDA/cuda-launch.fir @@ -0,0 +1,64 @@ +// RUN: fir-opt --split-input-file --cuf-convert %s | FileCheck %s + + +module attributes {gpu.container_module, dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>} { + gpu.module @cuda_device_mod { + gpu.func @_QPsub_device1() kernel { + cf.br ^bb1 + ^bb1: // pred: ^bb0 + gpu.return + } + gpu.func @_QPsub_device2(%arg0: !fir.ref) kernel { + cf.br ^bb1(%arg0 : !fir.ref) + ^bb1(%0: !fir.ref): // pred: ^bb0 + %1 = fir.declare %0 {uniq_name = "_QFsub1Ei"} : (!fir.ref) -> !fir.ref + %cst = arith.constant 2.000000e+00 : f32 + fir.store %cst to %1 : !fir.ref + gpu.return + } + } + + func.func @_QQmain() attributes {fir.bindc_name = "main"} { + %0 = fir.alloca f32 + // CHECK: %[[ALLOCA:.*]] = fir.alloca f32 + %c1 = arith.constant 1 : index + %c11_i32 = arith.constant 11 : i32 + %c6_i32 = arith.constant 6 : i32 + %c1_i32 = arith.constant 1 : i32 + // CHECK: gpu.launch_func @cuda_device_mod::@_QPsub_device1 blocks in (%{{.*}}, %{{.*}}, %{{.*}}) threads in (%{{.*}}, %{{.*}}, %{{.*}}) dynamic_shared_memory_size %c0{{.*}} + cuf.kernel_launch @cuda_device_mod::@_QPsub_device1<<<%c1_i32, %c1_i32, %c1_i32, %c1_i32, %c1_i32, %c1_i32>>>() + + // CHECK: gpu.launch_func @cuda_device_mod::@_QPsub_device2 blocks in (%{{.*}}, %{{.*}}, %{{.*}}) threads in (%{{.*}}, %{{.*}}, %{{.*}}) dynamic_shared_memory_size %c0{{.*}} args(%[[ALLOCA]] : !fir.ref) + cuf.kernel_launch @cuda_device_mod::@_QPsub_device2<<<%c1_i32, %c1_i32, %c1_i32, %c1_i32, %c1_i32, %c1_i32>>>(%0) : (!fir.ref) + return + } + +} + +// ----- + +module attributes {gpu.container_module, dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry, dense<64> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry, dense<32> : vector<4xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<2xi64>>, #dlti.dl_entry : vector<4xi64>>, #dlti.dl_entry<"dlti.endianness", "little">, #dlti.dl_entry<"dlti.stack_alignment", 128 : i64>>} { + gpu.module @cuda_device_mod { + gpu.func @_QMmod1Psub1(%arg0: !fir.ref>) kernel { + gpu.return + } + } + + func.func @_QMmod1Psub1(%arg0: !fir.ref> {cuf.data_attr = #cuf.cuda, fir.bindc_name = "adev"}) attributes {cuf.cluster_dims = #cuf.cluster_dims, cuf.proc_attr = #cuf.cuda_proc} { + return + } + func.func @_QMmod1Phost_sub() { + %c10 = arith.constant 10 : index + %0 = cuf.alloc !fir.array<10xi32> {bindc_name = "adev", data_attr = #cuf.cuda, uniq_name = "_QMmod1Fhost_subEadev"} -> !fir.ref> + %1 = fir.shape %c10 : (index) -> !fir.shape<1> + %2:2 = hlfir.declare %0(%1) {data_attr = #cuf.cuda, uniq_name = "_QMmod1Fhost_subEadev"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) + %c1_i32 = arith.constant 1 : i32 + %c10_i32 = arith.constant 10 : i32 + cuf.kernel_launch @_QMmod1Psub1<<<%c1_i32, %c1_i32, %c1_i32, %c10_i32, %c1_i32, %c1_i32>>>(%2#1) : (!fir.ref>) + return + } +} + +// CHECK-LABEL: func.func @_QMmod1Phost_sub() +// CHECK: gpu.launch_func @cuda_device_mod::@_QMmod1Psub1 clusters in (%c2{{.*}}, %c2{{.*}}, %c1{{.*}}) + diff --git a/flang/test/Fir/box.fir b/flang/test/Fir/box.fir index 81a4d8bc13bf01ea1530ba3e9ec4556fd8288fc4..fd9fa1f2b3aabd0580dd478ead1102fa26b40abe 100644 --- a/flang/test/Fir/box.fir +++ b/flang/test/Fir/box.fir @@ -56,12 +56,14 @@ func.func @fa(%a : !fir.ref>) { // CHECK-LABEL: define void @b1( // CHECK-SAME: ptr %[[res:.*]], ptr %[[arg0:.*]], i64 %[[arg1:.*]]) func.func @b1(%arg0 : !fir.ref>, %arg1 : index) -> !fir.box> { + // CHECK: %[[alloca:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8 } // CHECK: %[[size:.*]] = mul i64 ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64), %[[arg1]] // CHECK: insertvalue {{.*}} undef, i64 %[[size]], 1 // CHECK: insertvalue {{.*}} i32 20240719, 2 // CHECK: insertvalue {{.*}} ptr %[[arg0]], 0 %x = fir.embox %arg0 typeparams %arg1 : (!fir.ref>, index) -> !fir.box> - // CHECK: store {{.*}}, ptr %[[res]] + // CHECK: store {{.*}}, ptr %[[alloca]] + // CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %[[res]], ptr %[[alloca]], i32 24, i1 false) return %x : !fir.box> } @@ -71,11 +73,13 @@ func.func @b1(%arg0 : !fir.ref>, %arg1 : index) -> !fir.box>>, %arg1 : index) -> !fir.box>> { %1 = fir.shape %arg1 : (index) -> !fir.shape<1> + // CHECK: %[[alloca:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] } // CHECK: insertvalue {{.*}} { ptr undef, i64 ptrtoint (ptr getelementptr ([5 x i8], ptr null, i32 1) to i64), i32 20240719, i8 1, i8 40, i8 0, i8 0, {{.*}} }, i64 %[[arg1]], 7, 0, 1 // CHECK: insertvalue {{.*}} %{{.*}}, i64 ptrtoint (ptr getelementptr ([5 x i8], ptr null, i32 1) to i64), 7, 0, 2 // CHECK: insertvalue {{.*}} ptr %[[arg0]], 0 %2 = fir.embox %arg0(%1) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> - // CHECK: store {{.*}}, ptr %[[res]] + // CHECK: store {{.*}}, ptr %[[alloca]] + // CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %[[res]], ptr %[[alloca]], i32 48, i1 false) return %2 : !fir.box>> } @@ -84,6 +88,7 @@ func.func @b2(%arg0 : !fir.ref>>, %arg1 : index) -> // CHECK-SAME: ptr %[[res:.*]], ptr %[[arg0:.*]], i64 %[[arg1:.*]], i64 %[[arg2:.*]]) func.func @b3(%arg0 : !fir.ref>>, %arg1 : index, %arg2 : index) -> !fir.box>> { %1 = fir.shape %arg2 : (index) -> !fir.shape<1> + // CHECK: %[[alloca:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] } // CHECK: %[[size:.*]] = mul i64 ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64), %[[arg1]] // CHECK: insertvalue {{.*}} i64 %[[size]], 1 // CHECK: insertvalue {{.*}} i32 20240719, 2 @@ -91,7 +96,8 @@ func.func @b3(%arg0 : !fir.ref>>, %arg1 : index, %ar // CHECK: insertvalue {{.*}} i64 %[[size]], 7, 0, 2 // CHECK: insertvalue {{.*}} ptr %[[arg0]], 0 %2 = fir.embox %arg0(%1) typeparams %arg1 : (!fir.ref>>, !fir.shape<1>, index) -> !fir.box>> - // CHECK: store {{.*}}, ptr %[[res]] + // CHECK: store {{.*}}, ptr %[[alloca]] + // CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %[[res]], ptr %[[alloca]], i32 48, i1 false) return %2 : !fir.box>> } @@ -101,6 +107,7 @@ func.func @b3(%arg0 : !fir.ref>>, %arg1 : index, %ar func.func @b4(%arg0 : !fir.ref>>, %arg1 : index) -> !fir.box>> { %c_7 = arith.constant 7 : index %1 = fir.shape %c_7 : (index) -> !fir.shape<1> + // CHECK: %[[alloca:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] } // CHECK: %[[size:.*]] = mul i64 ptrtoint (ptr getelementptr (i8, ptr null, i32 1) to i64), %[[arg1]] // CHECK: insertvalue {{.*}} i64 %[[size]], 1 // CHECK: insertvalue {{.*}} i32 20240719, 2 @@ -108,7 +115,8 @@ func.func @b4(%arg0 : !fir.ref>>, %arg1 : index) -> // CHECK: insertvalue {{.*}} i64 %[[size]], 7, 0, 2 // CHECK: insertvalue {{.*}} ptr %[[arg0]], 0 %x = fir.embox %arg0(%1) typeparams %arg1 : (!fir.ref>>, !fir.shape<1>, index) -> !fir.box>> - // CHECK: store {{.*}}, ptr %[[res]] + // CHECK: store {{.*}}, ptr %[[alloca]] + // CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %[[res]], ptr %[[alloca]], i32 48, i1 false) return %x : !fir.box>> } @@ -117,8 +125,7 @@ func.func @b4(%arg0 : !fir.ref>>, %arg1 : index) -> // CHECK-SAME: ptr %[[arg0:.*]], ptr %[[arg1:.*]]) func.func @b5(%arg0 : !fir.ref>>>, %arg1 : !fir.box>>) { fir.store %arg1 to %arg0 : !fir.ref>>> - // CHECK: %[[boxLoad:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, [2 x [3 x i64]] }, ptr %[[arg1]] - // CHECK: store { ptr, i64, i32, i8, i8, i8, i8, [2 x [3 x i64]] } %[[boxLoad]], ptr %[[arg0]] + // CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %0, ptr %1, i32 72, i1 false) return } diff --git a/flang/test/Fir/convert-to-llvm-openmp-and-fir.fir b/flang/test/Fir/convert-to-llvm-openmp-and-fir.fir index 335877e7c9a87252b41bf4db941f71d370c25e93..168526518865b4087d829ab8e19816e743d1da85 100644 --- a/flang/test/Fir/convert-to-llvm-openmp-and-fir.fir +++ b/flang/test/Fir/convert-to-llvm-openmp-and-fir.fir @@ -799,8 +799,8 @@ func.func @_QPs(%arg0: !fir.ref> {fir.bindc_name = "x"}) { //CHECK: omp.parallel { //CHECK: %[[CONST_1:.*]] = llvm.mlir.constant(1 : i32) : i32 //CHECK: %[[ALLOCA_1:.*]] = llvm.alloca %[[CONST_1:.*]] x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8)> {alignment = 8 : i64} : (i32) -> !llvm.ptr -//CHECK: %[[LOAD:.*]] = llvm.load %[[ALLOCA]] : !llvm.ptr -> !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8)> -//CHECK: llvm.store %[[LOAD]], %[[ALLOCA_1]] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8)>, !llvm.ptr +//CHECK: %[[SIZE:.*]] = llvm.mlir.constant(24 : i32) : i32 +//CHECK: "llvm.intr.memcpy"(%[[ALLOCA_1]], %[[ALLOCA]], %[[SIZE]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () //CHECK: %[[GEP:.*]] = llvm.getelementptr %[[ALLOCA_1]][0, 0] : (!llvm.ptr) -> !llvm.ptr //CHECK: %[[LOAD_2:.*]] = llvm.load %[[GEP]] : !llvm.ptr -> !llvm.ptr //CHECK: omp.terminator diff --git a/flang/test/Fir/convert-to-llvm.fir b/flang/test/Fir/convert-to-llvm.fir index 1182a0a10f218b3179bc27e5ab2d0f19b9f2550b..fa391fa6cc7a7d8f74d57b9d0eb9a9a3b0cd77e6 100644 --- a/flang/test/Fir/convert-to-llvm.fir +++ b/flang/test/Fir/convert-to-llvm.fir @@ -862,8 +862,8 @@ func.func @test_store_box(%array : !fir.ref>>, %box // CHECK-LABEL: llvm.func @test_store_box // CHECK-SAME: (%[[arg0:.*]]: !llvm.ptr, // CHECK-SAME: %[[arg1:.*]]: !llvm.ptr) { -// CHECK-NEXT: %[[box_to_store:.*]] = llvm.load %arg1 : !llvm.ptr -> !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<2 x array<3 x i{{.*}}>>)> -// CHECK-NEXT: llvm.store %[[box_to_store]], %[[arg0]] : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<2 x array<3 x i{{.*}}>>)>, !llvm.ptr +// CHECK-NEXT: %[[size:.*]] = llvm.mlir.constant(72 : i32) : i32 +// CHECK-NEXT: "llvm.intr.memcpy"(%[[arg0]], %[[arg1]], %[[size]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () // CHECK-NEXT: llvm.return // CHECK-NEXT: } @@ -875,15 +875,17 @@ func.func @store_unlimited_polymorphic_box(%arg0 : !fir.class, %arg1 : !fi fir.store %arg3 to %arg3r : !fir.ref>> return } -// CHECK-LABEL: llvm.func @store_unlimited_polymorphic_box( -// CHECK: %[[VAL_8:.*]] = llvm.load %{{.*}} : !llvm.ptr -> !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, ptr, array<1 x i{{.*}}>)> -// CHECK: llvm.store %[[VAL_8]], %{{.*}} : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, ptr, array<1 x i{{.*}}>)>, !llvm.ptr -// CHECK: %[[VAL_9:.*]] = llvm.load %{{.*}} : !llvm.ptr -> !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i{{.*}}>>, ptr, array<1 x i{{.*}}>)> -// CHECK: llvm.store %[[VAL_9]], %{{.*}} : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i{{.*}}>>, ptr, array<1 x i{{.*}}>)>, !llvm.ptr -// CHECK: %[[VAL_10:.*]] = llvm.load %{{.*}} : !llvm.ptr -> !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, ptr, array<1 x i{{.*}}>)> -// CHECK: llvm.store %[[VAL_10]], %{{.*}} : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, ptr, array<1 x i{{.*}}>)>, !llvm.ptr -// CHECK: %[[VAL_11:.*]] = llvm.load %{{.*}}: !llvm.ptr -// CHECK: llvm.store %[[VAL_11]], %{{.*}} : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i{{.*}}>>, ptr, array<1 x i{{.*}}>)>, !llvm.ptr +// CHECK: llvm.func @store_unlimited_polymorphic_box(%[[VAL_0:.*]]: !llvm.ptr, %[[VAL_1:.*]]: !llvm.ptr, %[[VAL_2:.*]]: !llvm.ptr, %[[VAL_3:.*]]: !llvm.ptr, %[[VAL_4:.*]]: !llvm.ptr, %[[VAL_5:.*]]: !llvm.ptr, %[[VAL_6:.*]]: !llvm.ptr, %[[VAL_7:.*]]: !llvm.ptr) { +// CHECK: %[[VAL_8:.*]] = llvm.mlir.constant(40 : i32) : i32 +// CHECK: "llvm.intr.memcpy"(%[[VAL_4]], %[[VAL_0]], %[[VAL_8]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () +// CHECK: %[[VAL_9:.*]] = llvm.mlir.constant(64 : i32) : i32 +// CHECK: "llvm.intr.memcpy"(%[[VAL_5]], %[[VAL_1]], %[[VAL_9]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () +// CHECK: %[[VAL_10:.*]] = llvm.mlir.constant(40 : i32) : i32 +// CHECK: "llvm.intr.memcpy"(%[[VAL_6]], %[[VAL_2]], %[[VAL_10]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () +// CHECK: %[[VAL_11:.*]] = llvm.mlir.constant(64 : i32) : i32 +// CHECK: "llvm.intr.memcpy"(%[[VAL_7]], %[[VAL_3]], %[[VAL_11]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () +// CHECK: llvm.return +// CHECK: } // ----- @@ -935,8 +937,8 @@ func.func @test_load_box(%addr : !fir.ref>>) { // GENERIC-NEXT: %[[box_copy:.*]] = llvm.alloca %[[c1]] x !llvm.struct<([[DESC_TYPE:.*]])> // AMDGPU-NEXT: %[[alloca_box_copy:.*]] = llvm.alloca %[[c1]] x !llvm.struct<([[DESC_TYPE:.*]])>{{.*}} : (i32) -> !llvm.ptr<5> // AMDGPU-NEXT: %[[box_copy:.*]] = llvm.addrspacecast %[[alloca_box_copy]] : !llvm.ptr<5> to !llvm.ptr -// CHECK-NEXT: %[[box_val:.*]] = llvm.load %[[arg0]] : !llvm.ptr -> !llvm.struct<([[DESC_TYPE]])> -// CHECK-NEXT: llvm.store %[[box_val]], %[[box_copy]] : !llvm.struct<([[DESC_TYPE]])>, !llvm.ptr +// CHECK-NEXT: %[[size:.*]] = llvm.mlir.constant(48 : i32) : i32 +// CHECK-NEXT: "llvm.intr.memcpy"(%[[box_copy]], %[[arg0]], %[[size]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () // CHECK-NEXT: llvm.call @takes_box(%[[box_copy]]) : (!llvm.ptr) -> () // CHECK-NEXT: llvm.return // CHECK-NEXT: } diff --git a/flang/test/Fir/embox-char.fir b/flang/test/Fir/embox-char.fir index bf8344dbb60fc88bba9f06fd8e75a022985445d5..efb069f96520d4e4fbf83bda0480cb46b72af4f0 100644 --- a/flang/test/Fir/embox-char.fir +++ b/flang/test/Fir/embox-char.fir @@ -1,3 +1,10 @@ +// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py + +// The script is designed to make adding checks to +// a test case fast, it is *not* designed to be authoritative +// about what constitutes a good test! The CHECK should be +// minimized and named to reflect the test intent. + // Test that the offset of the first element of the slice // is computed in elements of the type used for the GEP // computing the base of the slice. @@ -10,42 +17,40 @@ // print *, x(2,:) // end subroutine -// CHECK-LABEL: llvm.func @test_char4( -// CHECK-SAME: %[[VAL_0:.*]]: !llvm.ptr, -// CHECK-SAME: %[[VAL_1_SLICE_LB0:.*]]: i64, %[[VAL_2_SLICE_EX0:.*]]: i64, %[[VAL_3_SLICE_ST0:.*]]: i64, %[[VAL_4_SLICE_LB1:.*]]: i64, %[[VAL_5_SLICE_EX1:.*]]: i64, %[[VAL_6_SLICE_ST1:.*]]: i64) { +// CHECK: llvm.func @test_char4(%[[VAL_0:.*]]: !llvm.ptr, %[[VAL_1:.*]]: i64, %[[VAL_2:.*]]: i64, %[[VAL_3:.*]]: i64, %[[VAL_4:.*]]: i64, %[[VAL_5:.*]]: i64, %[[VAL_6:.*]]: i64) { // CHECK: %[[VAL_7:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[VAL_8:.*]] = llvm.alloca %[[VAL_7]] x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr // CHECK: %[[VAL_9:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[VAL_10:.*]] = llvm.alloca %[[VAL_9]] x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr // CHECK: %[[VAL_11:.*]] = llvm.mlir.constant(0 : index) : i64 // CHECK: %[[VAL_12:.*]] = llvm.mlir.constant(1 : index) : i64 -// CHECK: %[[VAL_13_WIDTH:.*]] = llvm.mlir.constant(4 : index) : i64 -// CHECK: %[[VAL_14:.*]] = llvm.load %[[VAL_0]] : !llvm.ptr -> !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: llvm.store %[[VAL_14]], %[[VAL_10]] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)>, !llvm.ptr +// CHECK: %[[VAL_13:.*]] = llvm.mlir.constant(4 : index) : i64 +// CHECK: %[[VAL_14:.*]] = llvm.mlir.constant(72 : i32) : i32 +// CHECK: "llvm.intr.memcpy"(%[[VAL_10]], %[[VAL_0]], %[[VAL_14]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () // CHECK: %[[VAL_15:.*]] = llvm.getelementptr %[[VAL_10]][0, 1] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_16_BYTESIZE:.*]] = llvm.load %[[VAL_15]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_16:.*]] = llvm.load %[[VAL_15]] : !llvm.ptr -> i64 // CHECK: %[[VAL_17:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 0] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_18_LB1:.*]] = llvm.load %[[VAL_17]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_18:.*]] = llvm.load %[[VAL_17]] : !llvm.ptr -> i64 // CHECK: %[[VAL_19:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 1] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_20_EX1:.*]] = llvm.load %[[VAL_19]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_20:.*]] = llvm.load %[[VAL_19]] : !llvm.ptr -> i64 // CHECK: %[[VAL_21:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 2] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_22_ST1:.*]] = llvm.load %[[VAL_21]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_22:.*]] = llvm.load %[[VAL_21]] : !llvm.ptr -> i64 // CHECK: %[[VAL_23:.*]] = llvm.getelementptr %[[VAL_10]][0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_24_BASEPTR:.*]] = llvm.load %[[VAL_23]] : !llvm.ptr -> !llvm.ptr +// CHECK: %[[VAL_24:.*]] = llvm.load %[[VAL_23]] : !llvm.ptr -> !llvm.ptr // CHECK: %[[VAL_25:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 0] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_26_LB0:.*]] = llvm.load %[[VAL_25]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_26:.*]] = llvm.load %[[VAL_25]] : !llvm.ptr -> i64 // CHECK: %[[VAL_27:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 1] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_28_EX0:.*]] = llvm.load %[[VAL_27]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_28:.*]] = llvm.load %[[VAL_27]] : !llvm.ptr -> i64 // CHECK: %[[VAL_29:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 2] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_30_ST0:.*]] = llvm.load %[[VAL_29]] : !llvm.ptr -> i64 -// CHECK: %[[VAL_31_LEN:.*]] = llvm.sdiv %[[VAL_16_BYTESIZE]], %[[VAL_13_WIDTH]] : i64 +// CHECK: %[[VAL_30:.*]] = llvm.load %[[VAL_29]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_31:.*]] = llvm.sdiv %[[VAL_16]], %[[VAL_13]] : i64 // CHECK: %[[VAL_32:.*]] = llvm.mlir.constant(44 : i32) : i32 // CHECK: %[[VAL_33:.*]] = llvm.mlir.zero : !llvm.ptr // CHECK: %[[VAL_34:.*]] = llvm.getelementptr %[[VAL_33]][1] : (!llvm.ptr) -> !llvm.ptr, i32 // CHECK: %[[VAL_35:.*]] = llvm.ptrtoint %[[VAL_34]] : !llvm.ptr to i64 -// CHECK: %[[VAL_36_BYTESIZE:.*]] = llvm.mul %[[VAL_35]], %[[VAL_31_LEN]] : i64 +// CHECK: %[[VAL_36:.*]] = llvm.mul %[[VAL_35]], %[[VAL_31]] : i64 // CHECK: %[[VAL_37:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_38:.*]] = llvm.insertvalue %[[VAL_36_BYTESIZE]], %[[VAL_37]][1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_38:.*]] = llvm.insertvalue %[[VAL_36]], %[[VAL_37]][1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> // CHECK: %[[VAL_39:.*]] = llvm.mlir.constant(20240719 : i32) : i32 // CHECK: %[[VAL_40:.*]] = llvm.insertvalue %[[VAL_39]], %[[VAL_38]][2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> // CHECK: %[[VAL_41:.*]] = llvm.mlir.constant(2 : i32) : i32 @@ -59,39 +64,39 @@ // CHECK: %[[VAL_49:.*]] = llvm.mlir.constant(0 : i32) : i32 // CHECK: %[[VAL_50:.*]] = llvm.trunc %[[VAL_49]] : i32 to i8 // CHECK: %[[VAL_51:.*]] = llvm.insertvalue %[[VAL_50]], %[[VAL_48]][6] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_52_c0:.*]] = llvm.mlir.constant(0 : i64) : i64 +// CHECK: %[[VAL_52:.*]] = llvm.mlir.constant(0 : i64) : i64 // CHECK: %[[VAL_53:.*]] = llvm.mlir.constant(1 : i64) : i64 -// CHECK: %[[VAL_54:.*]] = llvm.sub %[[VAL_1_SLICE_LB0]], %[[VAL_26_LB0]] : i64 -// CHECK: %[[VAL_55:.*]] = llvm.mul %[[VAL_54]], %[[VAL_31_LEN]] : i64 -// CHECK: %[[VAL_56_SLICE_OFF0:.*]] = llvm.add %[[VAL_55]], %[[VAL_52_c0]] : i64 -// CHECK: %[[VAL_57:.*]] = llvm.sub %[[VAL_2_SLICE_EX0]], %[[VAL_1_SLICE_LB0]] : i64 -// CHECK: %[[VAL_58:.*]] = llvm.add %[[VAL_57]], %[[VAL_3_SLICE_ST0]] : i64 -// CHECK: %[[VAL_59:.*]] = llvm.sdiv %[[VAL_58]], %[[VAL_3_SLICE_ST0]] : i64 -// CHECK: %[[VAL_60:.*]] = llvm.icmp "sgt" %[[VAL_59]], %[[VAL_52_c0]] : i64 -// CHECK: %[[VAL_61:.*]] = llvm.select %[[VAL_60]], %[[VAL_59]], %[[VAL_52_c0]] : i1, i64 +// CHECK: %[[VAL_54:.*]] = llvm.sub %[[VAL_1]], %[[VAL_26]] : i64 +// CHECK: %[[VAL_55:.*]] = llvm.mul %[[VAL_54]], %[[VAL_31]] : i64 +// CHECK: %[[VAL_56:.*]] = llvm.add %[[VAL_55]], %[[VAL_52]] : i64 +// CHECK: %[[VAL_57:.*]] = llvm.sub %[[VAL_2]], %[[VAL_1]] : i64 +// CHECK: %[[VAL_58:.*]] = llvm.add %[[VAL_57]], %[[VAL_3]] : i64 +// CHECK: %[[VAL_59:.*]] = llvm.sdiv %[[VAL_58]], %[[VAL_3]] : i64 +// CHECK: %[[VAL_60:.*]] = llvm.icmp "sgt" %[[VAL_59]], %[[VAL_52]] : i64 +// CHECK: %[[VAL_61:.*]] = llvm.select %[[VAL_60]], %[[VAL_59]], %[[VAL_52]] : i1, i64 // CHECK: %[[VAL_62:.*]] = llvm.insertvalue %[[VAL_53]], %[[VAL_51]][7, 0, 0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> // CHECK: %[[VAL_63:.*]] = llvm.insertvalue %[[VAL_61]], %[[VAL_62]][7, 0, 1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_64:.*]] = llvm.mul %[[VAL_36_BYTESIZE]], %[[VAL_3_SLICE_ST0]] : i64 +// CHECK: %[[VAL_64:.*]] = llvm.mul %[[VAL_36]], %[[VAL_3]] : i64 // CHECK: %[[VAL_65:.*]] = llvm.insertvalue %[[VAL_64]], %[[VAL_63]][7, 0, 2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_66:.*]] = llvm.mul %[[VAL_36_BYTESIZE]], %[[VAL_28_EX0]] : i64 -// CHECK: %[[VAL_67:.*]] = llvm.mul %[[VAL_31_LEN]], %[[VAL_28_EX0]] : i64 -// CHECK: %[[VAL_68:.*]] = llvm.sub %[[VAL_4_SLICE_LB1]], %[[VAL_18_LB1]] : i64 -// CHECK: %[[VAL_69_SLICE_OFF1:.*]] = llvm.mul %[[VAL_68]], %[[VAL_67]] : i64 -// CHECK: %[[VAL_70_OFFSET:.*]] = llvm.add %[[VAL_69_SLICE_OFF1]], %[[VAL_56_SLICE_OFF0]] : i64 -// CHECK: %[[VAL_71:.*]] = llvm.sub %[[VAL_5_SLICE_EX1]], %[[VAL_4_SLICE_LB1]] : i64 -// CHECK: %[[VAL_72:.*]] = llvm.add %[[VAL_71]], %[[VAL_6_SLICE_ST1]] : i64 -// CHECK: %[[VAL_73:.*]] = llvm.sdiv %[[VAL_72]], %[[VAL_6_SLICE_ST1]] : i64 -// CHECK: %[[VAL_74:.*]] = llvm.icmp "sgt" %[[VAL_73]], %[[VAL_52_c0]] : i64 -// CHECK: %[[VAL_75:.*]] = llvm.select %[[VAL_74]], %[[VAL_73]], %[[VAL_52_c0]] : i1, i64 +// CHECK: %[[VAL_66:.*]] = llvm.mul %[[VAL_36]], %[[VAL_28]] : i64 +// CHECK: %[[VAL_67:.*]] = llvm.mul %[[VAL_31]], %[[VAL_28]] : i64 +// CHECK: %[[VAL_68:.*]] = llvm.sub %[[VAL_4]], %[[VAL_18]] : i64 +// CHECK: %[[VAL_69:.*]] = llvm.mul %[[VAL_68]], %[[VAL_67]] : i64 +// CHECK: %[[VAL_70:.*]] = llvm.add %[[VAL_69]], %[[VAL_56]] : i64 +// CHECK: %[[VAL_71:.*]] = llvm.sub %[[VAL_5]], %[[VAL_4]] : i64 +// CHECK: %[[VAL_72:.*]] = llvm.add %[[VAL_71]], %[[VAL_6]] : i64 +// CHECK: %[[VAL_73:.*]] = llvm.sdiv %[[VAL_72]], %[[VAL_6]] : i64 +// CHECK: %[[VAL_74:.*]] = llvm.icmp "sgt" %[[VAL_73]], %[[VAL_52]] : i64 +// CHECK: %[[VAL_75:.*]] = llvm.select %[[VAL_74]], %[[VAL_73]], %[[VAL_52]] : i1, i64 // CHECK: %[[VAL_76:.*]] = llvm.insertvalue %[[VAL_53]], %[[VAL_65]][7, 1, 0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> // CHECK: %[[VAL_77:.*]] = llvm.insertvalue %[[VAL_75]], %[[VAL_76]][7, 1, 1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_78:.*]] = llvm.mul %[[VAL_66]], %[[VAL_6_SLICE_ST1]] : i64 +// CHECK: %[[VAL_78:.*]] = llvm.mul %[[VAL_66]], %[[VAL_6]] : i64 // CHECK: %[[VAL_79:.*]] = llvm.insertvalue %[[VAL_78]], %[[VAL_77]][7, 1, 2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_80:.*]] = llvm.mul %[[VAL_66]], %[[VAL_20_EX1]] : i64 -// CHECK: %[[VAL_81:.*]] = llvm.mul %[[VAL_67]], %[[VAL_20_EX1]] : i64 -// CHECK: %[[VAL_82:.*]] = llvm.getelementptr %[[VAL_24_BASEPTR]]{{\[}}%[[VAL_70_OFFSET]]] : (!llvm.ptr, i64) -> !llvm.ptr, i32 -// CHECK: %[[VAL_84:.*]] = llvm.insertvalue %[[VAL_82]], %[[VAL_79]][0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: llvm.store %[[VAL_84]], %[[VAL_8]] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)>, !llvm.ptr +// CHECK: %[[VAL_80:.*]] = llvm.mul %[[VAL_66]], %[[VAL_20]] : i64 +// CHECK: %[[VAL_81:.*]] = llvm.mul %[[VAL_67]], %[[VAL_20]] : i64 +// CHECK: %[[VAL_82:.*]] = llvm.getelementptr %[[VAL_24]]{{\[}}%[[VAL_70]]] : (!llvm.ptr, i64) -> !llvm.ptr, i32 +// CHECK: %[[VAL_83:.*]] = llvm.insertvalue %[[VAL_82]], %[[VAL_79]][0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: llvm.store %[[VAL_83]], %[[VAL_8]] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)>, !llvm.ptr // CHECK: llvm.return // CHECK: } func.func @test_char4(%arg0: !fir.ref>>>>, %arg1 : index, %arg2 : index, %arg3 : index, %arg4 : index, %arg5 : index, %arg6 : index) { @@ -108,86 +113,84 @@ func.func @test_char4(%arg0: !fir.ref>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr // CHECK: %[[VAL_9:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[VAL_10:.*]] = llvm.alloca %[[VAL_9]] x !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr // CHECK: %[[VAL_11:.*]] = llvm.mlir.constant(0 : index) : i64 -// CHECK: %[[VAL_12_c1:.*]] = llvm.mlir.constant(1 : index) : i64 -// CHECK: %[[VAL_14:.*]] = llvm.load %[[VAL_0]] : !llvm.ptr -> !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: llvm.store %[[VAL_14]], %[[VAL_10]] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)>, !llvm.ptr -// CHECK: %[[VAL_15:.*]] = llvm.getelementptr %[[VAL_10]][0, 1] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_16_BYTESIZE:.*]] = llvm.load %[[VAL_15]] : !llvm.ptr -> i64 -// CHECK: %[[VAL_17:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 0] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_18_LB1:.*]] = llvm.load %[[VAL_17]] : !llvm.ptr -> i64 -// CHECK: %[[VAL_19:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 1] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_20_EX1:.*]] = llvm.load %[[VAL_19]] : !llvm.ptr -> i64 -// CHECK: %[[VAL_21:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 2] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_22_ST1:.*]] = llvm.load %[[VAL_21]] : !llvm.ptr -> i64 -// CHECK: %[[VAL_23:.*]] = llvm.getelementptr %[[VAL_10]][0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_24_BASEPTR:.*]] = llvm.load %[[VAL_23]] : !llvm.ptr -> !llvm.ptr -// CHECK: %[[VAL_25:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 0] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_26_LB0:.*]] = llvm.load %[[VAL_25]] : !llvm.ptr -> i64 -// CHECK: %[[VAL_27:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 1] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_28_EX0:.*]] = llvm.load %[[VAL_27]] : !llvm.ptr -> i64 -// CHECK: %[[VAL_29:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 2] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_30_ST0:.*]] = llvm.load %[[VAL_29]] : !llvm.ptr -> i64 -// CHECK: %[[VAL_32:.*]] = llvm.mlir.constant(40 : i32) : i32 -// CHECK: %[[VAL_33:.*]] = llvm.mlir.zero : !llvm.ptr -// CHECK: %[[VAL_34:.*]] = llvm.getelementptr %[[VAL_33]][1] : (!llvm.ptr) -> !llvm.ptr, i8 -// CHECK: %[[VAL_35:.*]] = llvm.ptrtoint %[[VAL_34]] : !llvm.ptr to i64 -// CHECK: %[[VAL_36_BYTESIZE:.*]] = llvm.mul %[[VAL_35]], %[[VAL_16_BYTESIZE]] : i64 -// CHECK: %[[VAL_37:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_38:.*]] = llvm.insertvalue %[[VAL_36_BYTESIZE]], %[[VAL_37]][1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_39:.*]] = llvm.mlir.constant(20240719 : i32) : i32 -// CHECK: %[[VAL_40:.*]] = llvm.insertvalue %[[VAL_39]], %[[VAL_38]][2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_41:.*]] = llvm.mlir.constant(2 : i32) : i32 -// CHECK: %[[VAL_42:.*]] = llvm.trunc %[[VAL_41]] : i32 to i8 -// CHECK: %[[VAL_43:.*]] = llvm.insertvalue %[[VAL_42]], %[[VAL_40]][3] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_44:.*]] = llvm.trunc %[[VAL_32]] : i32 to i8 -// CHECK: %[[VAL_45:.*]] = llvm.insertvalue %[[VAL_44]], %[[VAL_43]][4] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_46:.*]] = llvm.mlir.constant(0 : i32) : i32 -// CHECK: %[[VAL_47:.*]] = llvm.trunc %[[VAL_46]] : i32 to i8 -// CHECK: %[[VAL_48:.*]] = llvm.insertvalue %[[VAL_47]], %[[VAL_45]][5] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_49:.*]] = llvm.mlir.constant(0 : i32) : i32 -// CHECK: %[[VAL_50:.*]] = llvm.trunc %[[VAL_49]] : i32 to i8 -// CHECK: %[[VAL_51:.*]] = llvm.insertvalue %[[VAL_50]], %[[VAL_48]][6] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_52_c0:.*]] = llvm.mlir.constant(0 : i64) : i64 -// CHECK: %[[VAL_53:.*]] = llvm.mlir.constant(1 : i64) : i64 -// CHECK: %[[VAL_54:.*]] = llvm.sub %[[VAL_1_SLICE_LB0]], %[[VAL_26_LB0]] : i64 -// CHECK: %[[VAL_55:.*]] = llvm.mul %[[VAL_54]], %[[VAL_16_BYTESIZE]] : i64 -// CHECK: %[[VAL_56_SLICE_OFF0:.*]] = llvm.add %[[VAL_55]], %[[VAL_52_c0]] : i64 -// CHECK: %[[VAL_57:.*]] = llvm.sub %[[VAL_2_SLICE_EX0]], %[[VAL_1_SLICE_LB0]] : i64 -// CHECK: %[[VAL_58:.*]] = llvm.add %[[VAL_57]], %[[VAL_3_SLICE_ST0]] : i64 -// CHECK: %[[VAL_59:.*]] = llvm.sdiv %[[VAL_58]], %[[VAL_3_SLICE_ST0]] : i64 -// CHECK: %[[VAL_60:.*]] = llvm.icmp "sgt" %[[VAL_59]], %[[VAL_52_c0]] : i64 -// CHECK: %[[VAL_61:.*]] = llvm.select %[[VAL_60]], %[[VAL_59]], %[[VAL_52_c0]] : i1, i64 -// CHECK: %[[VAL_62:.*]] = llvm.insertvalue %[[VAL_53]], %[[VAL_51]][7, 0, 0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_63:.*]] = llvm.insertvalue %[[VAL_61]], %[[VAL_62]][7, 0, 1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_64:.*]] = llvm.mul %[[VAL_36_BYTESIZE]], %[[VAL_3_SLICE_ST0]] : i64 -// CHECK: %[[VAL_65:.*]] = llvm.insertvalue %[[VAL_64]], %[[VAL_63]][7, 0, 2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_66:.*]] = llvm.mul %[[VAL_36_BYTESIZE]], %[[VAL_28_EX0]] : i64 -// CHECK: %[[VAL_67:.*]] = llvm.mul %[[VAL_16_BYTESIZE]], %[[VAL_28_EX0]] : i64 -// CHECK: %[[VAL_68:.*]] = llvm.sub %[[VAL_4_SLICE_LB1]], %[[VAL_18_LB1]] : i64 -// CHECK: %[[VAL_69_SLICE_OFF1:.*]] = llvm.mul %[[VAL_68]], %[[VAL_67]] : i64 -// CHECK: %[[VAL_70_OFFSET:.*]] = llvm.add %[[VAL_69_SLICE_OFF1]], %[[VAL_56_SLICE_OFF0]] : i64 -// CHECK: %[[VAL_71:.*]] = llvm.sub %[[VAL_5_SLICE_EX1]], %[[VAL_4_SLICE_LB1]] : i64 -// CHECK: %[[VAL_72:.*]] = llvm.add %[[VAL_71]], %[[VAL_6_SLICE_ST1]] : i64 -// CHECK: %[[VAL_73:.*]] = llvm.sdiv %[[VAL_72]], %[[VAL_6_SLICE_ST1]] : i64 -// CHECK: %[[VAL_74:.*]] = llvm.icmp "sgt" %[[VAL_73]], %[[VAL_52_c0]] : i64 -// CHECK: %[[VAL_75:.*]] = llvm.select %[[VAL_74]], %[[VAL_73]], %[[VAL_52_c0]] : i1, i64 -// CHECK: %[[VAL_76:.*]] = llvm.insertvalue %[[VAL_53]], %[[VAL_65]][7, 1, 0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_77:.*]] = llvm.insertvalue %[[VAL_75]], %[[VAL_76]][7, 1, 1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_78:.*]] = llvm.mul %[[VAL_66]], %[[VAL_6_SLICE_ST1]] : i64 -// CHECK: %[[VAL_79:.*]] = llvm.insertvalue %[[VAL_78]], %[[VAL_77]][7, 1, 2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: %[[VAL_80:.*]] = llvm.mul %[[VAL_66]], %[[VAL_20_EX1]] : i64 -// CHECK: %[[VAL_81:.*]] = llvm.mul %[[VAL_67]], %[[VAL_20_EX1]] : i64 -// CHECK: %[[VAL_82:.*]] = llvm.getelementptr %[[VAL_24_BASEPTR]]{{\[}}%[[VAL_70_OFFSET]]] : (!llvm.ptr, i64) -> !llvm.ptr, i8 -// CHECK: %[[VAL_84:.*]] = llvm.insertvalue %[[VAL_82]], %[[VAL_79]][0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> -// CHECK: llvm.store %[[VAL_84]], %[[VAL_8]] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)>, !llvm.ptr +// CHECK: %[[VAL_12:.*]] = llvm.mlir.constant(1 : index) : i64 +// CHECK: %[[VAL_13:.*]] = llvm.mlir.constant(72 : i32) : i32 +// CHECK: "llvm.intr.memcpy"(%[[VAL_10]], %[[VAL_0]], %[[VAL_13]]) <{isVolatile = false}> : (!llvm.ptr, !llvm.ptr, i32) -> () +// CHECK: %[[VAL_14:.*]] = llvm.getelementptr %[[VAL_10]][0, 1] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_15:.*]] = llvm.load %[[VAL_14]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_16:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 0] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_17:.*]] = llvm.load %[[VAL_16]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_18:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 1] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_19:.*]] = llvm.load %[[VAL_18]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_20:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_12]], 2] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_21:.*]] = llvm.load %[[VAL_20]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_22:.*]] = llvm.getelementptr %[[VAL_10]][0, 0] : (!llvm.ptr) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_23:.*]] = llvm.load %[[VAL_22]] : !llvm.ptr -> !llvm.ptr +// CHECK: %[[VAL_24:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 0] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_25:.*]] = llvm.load %[[VAL_24]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_26:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 1] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_27:.*]] = llvm.load %[[VAL_26]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_28:.*]] = llvm.getelementptr %[[VAL_10]][0, 7, %[[VAL_11]], 2] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_29:.*]] = llvm.load %[[VAL_28]] : !llvm.ptr -> i64 +// CHECK: %[[VAL_30:.*]] = llvm.mlir.constant(40 : i32) : i32 +// CHECK: %[[VAL_31:.*]] = llvm.mlir.zero : !llvm.ptr +// CHECK: %[[VAL_32:.*]] = llvm.getelementptr %[[VAL_31]][1] : (!llvm.ptr) -> !llvm.ptr, i8 +// CHECK: %[[VAL_33:.*]] = llvm.ptrtoint %[[VAL_32]] : !llvm.ptr to i64 +// CHECK: %[[VAL_34:.*]] = llvm.mul %[[VAL_33]], %[[VAL_15]] : i64 +// CHECK: %[[VAL_35:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_36:.*]] = llvm.insertvalue %[[VAL_34]], %[[VAL_35]][1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_37:.*]] = llvm.mlir.constant(20240719 : i32) : i32 +// CHECK: %[[VAL_38:.*]] = llvm.insertvalue %[[VAL_37]], %[[VAL_36]][2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_39:.*]] = llvm.mlir.constant(2 : i32) : i32 +// CHECK: %[[VAL_40:.*]] = llvm.trunc %[[VAL_39]] : i32 to i8 +// CHECK: %[[VAL_41:.*]] = llvm.insertvalue %[[VAL_40]], %[[VAL_38]][3] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_42:.*]] = llvm.trunc %[[VAL_30]] : i32 to i8 +// CHECK: %[[VAL_43:.*]] = llvm.insertvalue %[[VAL_42]], %[[VAL_41]][4] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_44:.*]] = llvm.mlir.constant(0 : i32) : i32 +// CHECK: %[[VAL_45:.*]] = llvm.trunc %[[VAL_44]] : i32 to i8 +// CHECK: %[[VAL_46:.*]] = llvm.insertvalue %[[VAL_45]], %[[VAL_43]][5] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_47:.*]] = llvm.mlir.constant(0 : i32) : i32 +// CHECK: %[[VAL_48:.*]] = llvm.trunc %[[VAL_47]] : i32 to i8 +// CHECK: %[[VAL_49:.*]] = llvm.insertvalue %[[VAL_48]], %[[VAL_46]][6] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_50:.*]] = llvm.mlir.constant(0 : i64) : i64 +// CHECK: %[[VAL_51:.*]] = llvm.mlir.constant(1 : i64) : i64 +// CHECK: %[[VAL_52:.*]] = llvm.sub %[[VAL_1]], %[[VAL_25]] : i64 +// CHECK: %[[VAL_53:.*]] = llvm.mul %[[VAL_52]], %[[VAL_15]] : i64 +// CHECK: %[[VAL_54:.*]] = llvm.add %[[VAL_53]], %[[VAL_50]] : i64 +// CHECK: %[[VAL_55:.*]] = llvm.sub %[[VAL_2]], %[[VAL_1]] : i64 +// CHECK: %[[VAL_56:.*]] = llvm.add %[[VAL_55]], %[[VAL_3]] : i64 +// CHECK: %[[VAL_57:.*]] = llvm.sdiv %[[VAL_56]], %[[VAL_3]] : i64 +// CHECK: %[[VAL_58:.*]] = llvm.icmp "sgt" %[[VAL_57]], %[[VAL_50]] : i64 +// CHECK: %[[VAL_59:.*]] = llvm.select %[[VAL_58]], %[[VAL_57]], %[[VAL_50]] : i1, i64 +// CHECK: %[[VAL_60:.*]] = llvm.insertvalue %[[VAL_51]], %[[VAL_49]][7, 0, 0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_61:.*]] = llvm.insertvalue %[[VAL_59]], %[[VAL_60]][7, 0, 1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_62:.*]] = llvm.mul %[[VAL_34]], %[[VAL_3]] : i64 +// CHECK: %[[VAL_63:.*]] = llvm.insertvalue %[[VAL_62]], %[[VAL_61]][7, 0, 2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_64:.*]] = llvm.mul %[[VAL_34]], %[[VAL_27]] : i64 +// CHECK: %[[VAL_65:.*]] = llvm.mul %[[VAL_15]], %[[VAL_27]] : i64 +// CHECK: %[[VAL_66:.*]] = llvm.sub %[[VAL_4]], %[[VAL_17]] : i64 +// CHECK: %[[VAL_67:.*]] = llvm.mul %[[VAL_66]], %[[VAL_65]] : i64 +// CHECK: %[[VAL_68:.*]] = llvm.add %[[VAL_67]], %[[VAL_54]] : i64 +// CHECK: %[[VAL_69:.*]] = llvm.sub %[[VAL_5]], %[[VAL_4]] : i64 +// CHECK: %[[VAL_70:.*]] = llvm.add %[[VAL_69]], %[[VAL_6]] : i64 +// CHECK: %[[VAL_71:.*]] = llvm.sdiv %[[VAL_70]], %[[VAL_6]] : i64 +// CHECK: %[[VAL_72:.*]] = llvm.icmp "sgt" %[[VAL_71]], %[[VAL_50]] : i64 +// CHECK: %[[VAL_73:.*]] = llvm.select %[[VAL_72]], %[[VAL_71]], %[[VAL_50]] : i1, i64 +// CHECK: %[[VAL_74:.*]] = llvm.insertvalue %[[VAL_51]], %[[VAL_63]][7, 1, 0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_75:.*]] = llvm.insertvalue %[[VAL_73]], %[[VAL_74]][7, 1, 1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_76:.*]] = llvm.mul %[[VAL_64]], %[[VAL_6]] : i64 +// CHECK: %[[VAL_77:.*]] = llvm.insertvalue %[[VAL_76]], %[[VAL_75]][7, 1, 2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: %[[VAL_78:.*]] = llvm.mul %[[VAL_64]], %[[VAL_19]] : i64 +// CHECK: %[[VAL_79:.*]] = llvm.mul %[[VAL_65]], %[[VAL_19]] : i64 +// CHECK: %[[VAL_80:.*]] = llvm.getelementptr %[[VAL_23]]{{\[}}%[[VAL_68]]] : (!llvm.ptr, i64) -> !llvm.ptr, i8 +// CHECK: %[[VAL_81:.*]] = llvm.insertvalue %[[VAL_80]], %[[VAL_77]][0] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)> +// CHECK: llvm.store %[[VAL_81]], %[[VAL_8]] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<2 x array<3 x i64>>)>, !llvm.ptr // CHECK: llvm.return // CHECK: } func.func @test_char1(%arg0: !fir.ref>>>>, %arg1 : index, %arg2 : index, %arg3 : index, %arg4 : index, %arg5 : index, %arg6 : index) { diff --git a/flang/test/Fir/polymorphic.fir b/flang/test/Fir/polymorphic.fir index 40204314e8df79707fbe0b1c09a1154b0bfd5bae..78e5b8dcf84c781486190ebcb99fe8c726458756 100644 --- a/flang/test/Fir/polymorphic.fir +++ b/flang/test/Fir/polymorphic.fir @@ -14,8 +14,7 @@ func.func @_QMpolymorphic_testPtest_allocate_unlimited_polymorphic_non_derived() // CHECK: %[[MEM:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } // CHECK: %[[DESC:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, i64 1 // CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } { ptr null, i64 0, i32 20240719, i8 0, i8 -1, i8 1, i8 1, ptr null, [1 x i64] zeroinitializer }, ptr %[[MEM]] -// CHECK: %[[LOADED:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[MEM]], align 8 -// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOADED]], ptr %[[DESC]] +// CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %[[DESC]], ptr %[[MEM]], i32 40, i1 false) // CHECK: ret void // CHECK: } @@ -66,8 +65,7 @@ func.func @_QMpolymorphic_testPtest_embox() { // CHECK-LABEL: @_QMpolymorphic_testPtest_embox() // CHECK: %[[ALLOCA_DESC:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } // CHECK: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } { ptr @_QFEy, i64 ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64), i32 20240719, i8 1, i8 9, {{.*}}, ptr %[[ALLOCA_DESC]] -// CHECK: %[[LOADED_DESC:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %[[ALLOCA_DESC]], align 8 -// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } %[[LOADED_DESC]], ptr @_QFEx, align 8 +// CHECK: call void @llvm.memcpy.p0.p0.i32(ptr @_QFEx, ptr %[[ALLOCA_DESC]], i32 64, i1 false) // Test emboxing of an array element from an unlimited polymorphic array. @@ -158,8 +156,7 @@ func.func @_QQmain() { // CHECK: %[[CLASS_NONE:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } // CHECK: %[[DESC:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, i64 1 // CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } { ptr @_QMmod1Ea, i64 ptrtoint (ptr getelementptr (%_QMmod1TtK2, ptr null, i32 1) to i64), i32 20240719, i8 0, i8 42, i8 1, i8 1, ptr @_QMmod1EXdtXtX2, [1 x i64] zeroinitializer }, ptr %[[CLASS_NONE]], align 8 -// CHECK: %[[LOAD:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[CLASS_NONE]] -// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOAD]], ptr %[[DESC]] +// CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %[[DESC]], ptr %[[CLASS_NONE]], i32 40, i1 false) // CHECK: call void @_QMmod1Psub1(ptr %[[DESC]]) fir.global @_QMmod2Ep : !fir.class> { @@ -180,8 +177,7 @@ func.func private @_FortranAPointerAssociate(!fir.ref>, !fir.box< // CHECK-LABEL: define void @_QMmod2Pinitp( // CHECK-SAME: ptr %[[ARG0:.*]]){{.*}}{ // CHECK: %[[ALLOCA_CLASS_NONE:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } -// CHECK: %[[LOAD:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ARG0]] -// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOAD]], ptr %[[ALLOCA_CLASS_NONE]] +// CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %[[ALLOCA_CLASS_NONE]], ptr %[[ARG0]], i32 40, i1 false) // CHECK: %{{.*}} = call {} @_FortranAPointerAssociate(ptr @_QMmod2Ep, ptr %[[ALLOCA_CLASS_NONE]]) // CHECK: ret void diff --git a/flang/test/Fir/tbaa.fir b/flang/test/Fir/tbaa.fir index 809ab3a922a0fecdd4caf8e16026383bead98105..401ebbc8c49fe6b79805d211274017ce041587f3 100644 --- a/flang/test/Fir/tbaa.fir +++ b/flang/test/Fir/tbaa.fir @@ -137,8 +137,8 @@ module { // CHECK: %[[VAL_7:.*]] = llvm.mlir.addressof @_QFEx : !llvm.ptr // CHECK: %[[VAL_8:.*]] = llvm.mlir.addressof @_QQclX2E2F64756D6D792E66393000 : !llvm.ptr // CHECK: %[[VAL_10:.*]] = llvm.call @_FortranAioBeginExternalListOutput(%[[VAL_6]], %[[VAL_8]], %[[VAL_5]]) {fastmathFlags = #llvm.fastmath} : (i32, !llvm.ptr, i32) -> !llvm.ptr -// CHECK: %[[VAL_11:.*]] = llvm.load %[[VAL_7]] {tbaa = [#[[$BOXT]]]} : !llvm.ptr -> !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>, ptr, array<1 x i64>)> -// CHECK: llvm.store %[[VAL_11]], %[[VAL_3]] {tbaa = [#[[$BOXT]]]} : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>, ptr, array<1 x i64>)>, !llvm.ptr +// CHECK: %[[VAL_11:.*]] = llvm.mlir.constant(64 : i32) : i32 +// CHECK: "llvm.intr.memcpy"(%[[VAL_3]], %[[VAL_7]], %[[VAL_11]]) <{isVolatile = false, tbaa = [#[[$BOXT]]]}> // CHECK: %[[VAL_12:.*]] = llvm.getelementptr %[[VAL_3]][0, 7, %[[VAL_4]], 0] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>, ptr, array<1 x i64>)> // CHECK: %[[VAL_13:.*]] = llvm.load %[[VAL_12]] {tbaa = [#[[$BOXT]]]} : !llvm.ptr -> i64 // CHECK: %[[VAL_14:.*]] = llvm.getelementptr %[[VAL_3]][0, 7, %[[VAL_4]], 1] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>, ptr, array<1 x i64>)> diff --git a/flang/test/Integration/OpenMP/private-global.f90 b/flang/test/Integration/OpenMP/private-global.f90 index 62d0a3faf0c59384d483a9ec5dbb732208aec436..63ac6fbe05ee0e4b5f31bc929e346fc6caa519a1 100644 --- a/flang/test/Integration/OpenMP/private-global.f90 +++ b/flang/test/Integration/OpenMP/private-global.f90 @@ -31,8 +31,9 @@ End Program ! CHECK: %[[TABLE_BOX_ADDR2:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, i64 1, align 8 ! CHECK: %[[TABLE_BOX_VAL:.*]] = insertvalue { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] } { ptr undef, i64 ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64), i32 20240719, i8 1, i8 9, i8 0, i8 0, [1 x [3 x i64]] {{\[\[}}3 x i64] [i64 1, i64 10, i64 ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64)]] }, ptr %[[PRIV_TABLE]], 0 ! CHECK: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] } %[[TABLE_BOX_VAL]], ptr %[[TABLE_BOX_ADDR]], align 8 -! CHECK: %[[TABLE_BOX_VAL2:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[TABLE_BOX_ADDR]], align 8 -! CHECK: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] } %[[TABLE_BOX_VAL2]], ptr %[[TABLE_BOX_ADDR2]], align 8 +! CHECK : %[[TABLE_BOX_VAL2:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr %[[TABLE_BOX_ADDR]], align 8 +! CHECK : store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] } %[[TABLE_BOX_VAL2]], ptr %[[TABLE_BOX_ADDR2]], align 8 +! CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %[[TABLE_BOX_ADDR2]], ptr %[[TABLE_BOX_ADDR]], i32 48, i1 false) ! CHECK: %[[VAL_26:.*]] = call {} @_FortranAAssign(ptr %[[TABLE_BOX_ADDR2]], ptr %[[BOXED_FIFTY]], ptr @{{.*}}, i32 9) ! ... ! check that we use the private copy of table for table/=50 diff --git a/flang/test/Lower/Intrinsics/ieee_real.f90 b/flang/test/Lower/Intrinsics/ieee_real.f90 new file mode 100644 index 0000000000000000000000000000000000000000..20b7441e6e3a2a3adc48ee0b883a6a372ceb7e48 --- /dev/null +++ b/flang/test/Lower/Intrinsics/ieee_real.f90 @@ -0,0 +1,217 @@ +! RUN: bbc -emit-hlfir -o - %s | FileCheck %s + +! CHECK-LABEL: c.func @_QQmain +program p + use ieee_arithmetic, only: ieee_real + + ! CHECK: %[[V_0:[0-9]+]] = fir.alloca i16 {bindc_name = "j2", uniq_name = "_QFEj2"} + ! CHECK: %[[V_1:[0-9]+]]:2 = hlfir.declare %[[V_0]] {uniq_name = "_QFEj2"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[V_2:[0-9]+]] = fir.alloca i64 {bindc_name = "j8", uniq_name = "_QFEj8"} + ! CHECK: %[[V_3:[0-9]+]]:2 = hlfir.declare %[[V_2]] {uniq_name = "_QFEj8"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[V_4:[0-9]+]] = fir.alloca f16 {bindc_name = "x2", uniq_name = "_QFEx2"} + ! CHECK: %[[V_5:[0-9]+]]:2 = hlfir.declare %[[V_4]] {uniq_name = "_QFEx2"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[V_6:[0-9]+]] = fir.alloca f32 {bindc_name = "x4", uniq_name = "_QFEx4"} + ! CHECK: %[[V_7:[0-9]+]]:2 = hlfir.declare %[[V_6]] {uniq_name = "_QFEx4"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[V_8:[0-9]+]] = fir.alloca f64 {bindc_name = "x8", uniq_name = "_QFEx8"} + ! CHECK: %[[V_9:[0-9]+]]:2 = hlfir.declare %[[V_8]] {uniq_name = "_QFEx8"} : (!fir.ref) -> (!fir.ref, !fir.ref) + integer(2) :: j2 + integer(8) :: j8 + real(2) :: x2 + real(4) :: x4 + real(8) :: x8 + + ! CHECK: hlfir.assign %c-32768{{.*}} to %[[V_1]]#0 : i16, !fir.ref + j2 = -huge(j2) - 1 + + ! CHECK: %[[V_10:[0-9]+]] = fir.load %[[V_1]]#0 : !fir.ref + ! CHECK: %[[V_11:[0-9]+]] = fir.convert %[[V_10]] : (i16) -> f32 + ! CHECK: hlfir.assign %[[V_11]] to %[[V_7]]#0 : f32, !fir.ref + x4 = ieee_real(j2,4) ! exact +! print*, j2, ' -> ', x4 + + ! CHECK: hlfir.assign %c33{{.*}} to %[[V_3]]#0 : i64, !fir.ref + j8 = 33 + + ! CHECK: %[[V_12:[0-9]+]] = fir.load %[[V_3]]#0 : !fir.ref + ! CHECK: %[[V_13:[0-9]+]] = fir.convert %[[V_12]] : (i64) -> f32 + ! CHECK: %[[V_14:[0-9]+]] = fir.convert %[[V_13]] : (f32) -> i64 + ! CHECK: %[[V_15:[0-9]+]] = arith.cmpi eq, %[[V_12]], %[[V_14]] : i64 + ! CHECK: %[[V_16:[0-9]+]] = fir.if %[[V_15]] -> (f32) { + ! CHECK: fir.result %[[V_13]] : f32 + ! CHECK: } else { + ! CHECK: %[[V_27:[0-9]+]] = fir.call @llvm.get.rounding() fastmath : () -> i32 + ! CHECK-DAG: %[[V_28:[0-9]+]] = arith.cmpi slt, %[[V_12]], %c0{{.*}} : i64 + ! CHECK-DAG: %[[V_29:[0-9]+]] = arith.cmpi sgt, %[[V_12]], %c0{{.*}} : i64 + ! CHECK-DAG: %[[V_30:[0-9]+]] = arith.bitcast %[[V_13]] : f32 to i32 + ! CHECK-DAG: %[[V_31:[0-9]+]] = arith.andi %[[V_30]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_32:[0-9]+]] = fir.convert %[[V_31]] : (i32) -> i1 + ! CHECK-DAG: %[[V_33:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c5{{.*}} : i32 + ! CHECK-DAG: %[[V_34:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_35:[0-9]+]] = arith.ori %[[V_34]], %[[V_33]] : i1 + ! CHECK-DAG: %[[V_36:[0-9]+]] = arith.andi %[[V_35]], %[[V_32]] : i1 + ! CHECK-DAG: %[[V_37:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c0{{.*}} : i32 + ! CHECK-DAG: %[[V_38:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c4{{.*}} : i32 + ! CHECK-DAG: %[[V_39:[0-9]+]] = arith.cmpi slt, %[[V_12]], %[[V_14]] : i64 + ! CHECK-DAG: %[[V_40:[0-9]+]] = arith.addi %[[V_30]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_41:[0-9]+]] = arith.subi %[[V_30]], %c1{{.*}} : i32 + ! CHECK: %[[V_42:[0-9]+]] = fir.if %[[V_39]] -> (f32) { + ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_29]] : i1 + ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_28]] : i1 + ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c3{{.*}} : i32 + ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1 + ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1 + ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) { + ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_28]], %[[V_40]], %[[V_41]] : i32 + ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32 + ! CHECK: fir.result %[[V_52]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_13]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_50]] : f32 + ! CHECK: } else { + ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_28]] : i1 + ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_29]] : i1 + ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c2{{.*}} : i32 + ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1 + ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1 + ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) { + ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_29]], %[[V_40]], %[[V_41]] : i32 + ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32 + ! CHECK: fir.result %[[V_52]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_13]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_50]] : f32 + ! CHECK: } + ! CHECK: %[[V_43:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 516 : i32}> : (f32) -> i1 + ! CHECK: fir.if %[[V_43]] { + ! CHECK: %[[V_44:[0-9]+]] = fir.call @_FortranAMapException(%c40{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_45:[0-9]+]] = fir.call @feraiseexcept(%[[V_44]]) fastmath : (i32) -> i32 + ! CHECK: } else { + ! CHECK: %[[V_44:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 240 : i32}> : (f32) -> i1 + ! CHECK: fir.if %[[V_44]] { + ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c48{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_46:[0-9]+]] = fir.call @feraiseexcept(%[[V_45]]) fastmath : (i32) -> i32 + ! CHECK: } else { + ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c32{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_46:[0-9]+]] = fir.call @feraiseexcept(%[[V_45]]) fastmath : (i32) -> i32 + ! CHECK: } + ! CHECK: } + ! CHECK: fir.result %[[V_42]] : f32 + ! CHECK: } + ! CHECK: hlfir.assign %[[V_16]] to %[[V_7]]#0 : f32, !fir.ref + x4 = ieee_real(j8,4) +! print*, j8, ' -> ', x4 + + ! CHECK: hlfir.assign %cst{{[_0-9]*}} to %[[V_5]]#0 : f16, !fir.ref + x2 = 3.33 + + ! CHECK: %[[V_17:[0-9]+]] = fir.load %[[V_5]]#0 : !fir.ref + ! CHECK: %[[V_18:[0-9]+]] = fir.convert %[[V_17]] : (f16) -> f32 + ! CHECK: %[[V_19:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_18]]) <{bit = 1 : i32}> : (f32) -> i1 + ! CHECK: %[[V_20:[0-9]+]] = fir.if %[[V_19]] -> (f32) { + ! CHECK: %[[V_27:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_28:[0-9]+]] = fir.call @feraiseexcept(%[[V_27]]) fastmath : (i32) -> i32 + ! CHECK: %[[V_29:[0-9]+]] = fir.address_of(@_FortranAIeeeValueTable_4) : !fir.ref> + ! CHECK: %[[V_30:[0-9]+]] = fir.coordinate_of %[[V_29]], %c2{{.*}} : (!fir.ref>, i8) -> !fir.ref + ! CHECK: %[[V_31:[0-9]+]] = fir.load %[[V_30]] : !fir.ref + ! CHECK: %[[V_32:[0-9]+]] = arith.bitcast %[[V_31]] : i32 to f32 + ! CHECK: fir.result %[[V_32]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_18]] : f32 + ! CHECK: } + ! CHECK: %[[V_21:[0-9]+]] = fir.convert %[[V_20]] : (f32) -> f16 + ! CHECK: hlfir.assign %[[V_21]] to %[[V_5]]#0 : f16, !fir.ref + x2 = ieee_real(x2,4) ! exact +! print*, x2, ' -> ', x2 + + ! CHECK: hlfir.assign %cst{{[_0-9]*}} to %[[V_9]]#0 : f64, !fir.ref + x8 = -0. + + ! CHECK: %[[V_22:[0-9]+]] = fir.load %[[V_9]]#0 : !fir.ref + ! CHECK: %[[V_23:[0-9]+]] = fir.convert %[[V_22]] : (f64) -> f32 + ! CHECK: %[[V_24:[0-9]+]] = fir.convert %[[V_23]] : (f32) -> f64 + ! CHECK: %[[V_25:[0-9]+]] = arith.cmpf ueq, %[[V_22]], %[[V_24]] fastmath : f64 + ! CHECK: %[[V_26:[0-9]+]] = fir.if %[[V_25]] -> (f32) { + ! CHECK: %[[V_27:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_23]]) <{bit = 1 : i32}> : (f32) -> i1 + ! CHECK: %[[V_28:[0-9]+]] = fir.if %[[V_27]] -> (f32) { + ! CHECK: %[[V_29:[0-9]+]] = fir.call @_FortranAMapException(%c1{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_30:[0-9]+]] = fir.call @feraiseexcept(%[[V_29]]) fastmath : (i32) -> i32 + ! CHECK: %[[V_31:[0-9]+]] = fir.address_of(@_FortranAIeeeValueTable_4) : !fir.ref> + ! CHECK: %[[V_32:[0-9]+]] = fir.coordinate_of %[[V_31]], %c2{{.*}} : (!fir.ref>, i8) -> !fir.ref + ! CHECK: %[[V_33:[0-9]+]] = fir.load %[[V_32]] : !fir.ref + ! CHECK: %[[V_34:[0-9]+]] = arith.bitcast %[[V_33]] : i32 to f32 + ! CHECK: fir.result %[[V_34]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_23]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_28]] : f32 + ! CHECK: } else { + ! CHECK-DAG: %[[V_27:[0-9]+]] = fir.call @llvm.get.rounding() fastmath : () -> i32 + ! CHECK-DAG: %[[V_28:[0-9]+]] = arith.cmpf olt, %[[V_22]], %cst{{[_0-9]*}} fastmath : f64 + ! CHECK-DAG: %[[V_29:[0-9]+]] = arith.cmpf ogt, %[[V_22]], %cst{{[_0-9]*}} fastmath : f64 + ! CHECK-DAG: %[[V_30:[0-9]+]] = arith.bitcast %[[V_23]] : f32 to i32 + ! CHECK-DAG: %[[V_31:[0-9]+]] = arith.andi %[[V_30]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_32:[0-9]+]] = fir.convert %[[V_31]] : (i32) -> i1 + ! CHECK-DAG: %[[V_33:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c5{{.*}} : i32 + ! CHECK-DAG: %[[V_34:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_35:[0-9]+]] = arith.ori %[[V_34]], %[[V_33]] : i1 + ! CHECK-DAG: %[[V_36:[0-9]+]] = arith.andi %[[V_35]], %[[V_32]] : i1 + ! CHECK-DAG: %[[V_37:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c0{{.*}} : i32 + ! CHECK-DAG: %[[V_38:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c4{{.*}} : i32 + ! CHECK-DAG: %[[V_39:[0-9]+]] = arith.cmpf olt, %[[V_22]], %[[V_24]] fastmath : f64 + ! CHECK-DAG: %[[V_40:[0-9]+]] = arith.addi %[[V_30]], %c1{{.*}} : i32 + ! CHECK-DAG: %[[V_41:[0-9]+]] = arith.subi %[[V_30]], %c1{{.*}} : i32 + ! CHECK: %[[V_42:[0-9]+]] = fir.if %[[V_39]] -> (f32) { + ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_29]] : i1 + ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_28]] : i1 + ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c3{{.*}} : i32 + ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1 + ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1 + ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) { + ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_28]], %[[V_40]], %[[V_41]] : i32 + ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32 + ! CHECK: fir.result %[[V_52]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_23]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_50]] : f32 + ! CHECK: } else { + ! CHECK-DAG: %[[V_44:[0-9]+]] = arith.andi %[[V_37]], %[[V_28]] : i1 + ! CHECK-DAG: %[[V_45:[0-9]+]] = arith.andi %[[V_38]], %[[V_29]] : i1 + ! CHECK-DAG: %[[V_46:[0-9]+]] = arith.cmpi eq, %[[V_27]], %c2{{.*}} : i32 + ! CHECK-DAG: %[[V_47:[0-9]+]] = arith.ori %[[V_36]], %[[V_44]] : i1 + ! CHECK-DAG: %[[V_48:[0-9]+]] = arith.ori %[[V_47]], %[[V_45]] : i1 + ! CHECK-DAG: %[[V_49:[0-9]+]] = arith.ori %[[V_48]], %[[V_46]] : i1 + ! CHECK: %[[V_50:[0-9]+]] = fir.if %[[V_49]] -> (f32) { + ! CHECK: %[[V_51:[0-9]+]] = arith.select %[[V_29]], %[[V_40]], %[[V_41]] : i32 + ! CHECK: %[[V_52:[0-9]+]] = arith.bitcast %[[V_51]] : i32 to f32 + ! CHECK: fir.result %[[V_52]] : f32 + ! CHECK: } else { + ! CHECK: fir.result %[[V_23]] : f32 + ! CHECK: } + ! CHECK: fir.result %[[V_50]] : f32 + ! CHECK: } + ! CHECK: %[[V_43:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 516 : i32}> : (f32) -> i1 + ! CHECK: fir.if %[[V_43]] { + ! CHECK: %[[V_44:[0-9]+]] = fir.call @_FortranAMapException(%c40{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_45:[0-9]+]] = fir.call @feraiseexcept(%[[V_44]]) fastmath : (i32) -> i32 + ! CHECK: } else { + ! CHECK: %[[V_44:[0-9]+]] = "llvm.intr.is.fpclass"(%[[V_42]]) <{bit = 240 : i32}> : (f32) -> i1 + ! CHECK: fir.if %[[V_44]] { + ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c48{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_46:[0-9]+]] = fir.call @feraiseexcept(%[[V_45]]) fastmath : (i32) -> i32 + ! CHECK: } else { + ! CHECK: %[[V_45:[0-9]+]] = fir.call @_FortranAMapException(%c32{{.*}}) fastmath : (i32) -> i32 + ! CHECK: %[[V_46:[0-9]+]] = fir.call @feraiseexcept(%[[V_45]]) fastmath : (i32) -> i32 + ! CHECK: } + ! CHECK: } + ! CHECK: fir.result %[[V_42]] : f32 + ! CHECK: } + ! CHECK: hlfir.assign %[[V_26]] to %[[V_7]]#0 : f32, !fir.ref + x4 = ieee_real(x8,4) +! print*, x8, ' -> ', x4 +end diff --git a/flang/test/Lower/OpenMP/Todo/depobj-construct.f90 b/flang/test/Lower/OpenMP/Todo/depobj-construct.f90 new file mode 100644 index 0000000000000000000000000000000000000000..2b3c4d92c4a4f8dc70254d832be166024224aa50 --- /dev/null +++ b/flang/test/Lower/OpenMP/Todo/depobj-construct.f90 @@ -0,0 +1,9 @@ +!RUN: %not_todo_cmd bbc -emit-hlfir -fopenmp -fopenmp-version=50 -o - %s 2>&1 | FileCheck %s +!RUN: %not_todo_cmd %flang_fc1 -emit-hlfir -fopenmp -fopenmp-version=50 -o - %s 2>&1 | FileCheck %s + +!CHECK: not yet implemented: OpenMPDepobjConstruct +subroutine f00() + integer :: obj + integer :: x + !$omp depobj(obj) depend(in: x) +end diff --git a/flang/test/Lower/OpenMP/delayed-privatization-allocatable-firstprivate.f90 b/flang/test/Lower/OpenMP/delayed-privatization-allocatable-firstprivate.f90 index 9c97c689dad7093f650e887f64c7b169143f7cd5..b3a668018df1d55ee996045dc4ec9b1b9f7b69ad 100644 --- a/flang/test/Lower/OpenMP/delayed-privatization-allocatable-firstprivate.f90 +++ b/flang/test/Lower/OpenMP/delayed-privatization-allocatable-firstprivate.f90 @@ -57,5 +57,4 @@ end program compilation_to_obj ! LLVM: @[[GLOB_VAR:[^[:space:]]+]]t = internal global ! LLVM: define internal void @_QQmain..omp_par -! LLVM: %[[GLOB_VAL:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] }, ptr @[[GLOB_VAR]]t, align 8 -! LLVM-NEXT: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]] } %[[GLOB_VAL]], ptr %{{.*}}, align 8 +! LLVM: call void @llvm.memcpy.p0.p0.i32(ptr %{{.+}}, ptr @[[GLOB_VAR]]t, i32 48, i1 false) diff --git a/flang/test/Lower/OpenMP/master_taskloop.f90 b/flang/test/Lower/OpenMP/master_taskloop.f90 new file mode 100644 index 0000000000000000000000000000000000000000..26f664b2662dcb0202f22736f741518888b033c2 --- /dev/null +++ b/flang/test/Lower/OpenMP/master_taskloop.f90 @@ -0,0 +1,14 @@ +! This test checks lowering of OpenMP master taskloop Directive. + +! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s + +subroutine test_master_taskloop + integer :: i, j = 1 + !CHECK: not yet implemented: Taskloop construct + !$omp master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop +end subroutine diff --git a/flang/test/Lower/OpenMP/master_taskloop_simd.f90 b/flang/test/Lower/OpenMP/master_taskloop_simd.f90 new file mode 100644 index 0000000000000000000000000000000000000000..e928afd65244a4dd9bcf5bf81b6376f691085c36 --- /dev/null +++ b/flang/test/Lower/OpenMP/master_taskloop_simd.f90 @@ -0,0 +1,14 @@ +! This test checks lowering of OpenMP master taskloop simd Directive. + +! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s + +subroutine test_master_taskloop_simd() + integer :: i, j = 1 + !CHECK: not yet implemented: Composite TASKLOOP SIMD + !$omp master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop simd +end subroutine diff --git a/flang/test/Lower/OpenMP/parallel-master-taskloop-simd.f90 b/flang/test/Lower/OpenMP/parallel-master-taskloop-simd.f90 new file mode 100644 index 0000000000000000000000000000000000000000..086ed01d16d364d8c1c282d0d017819be14f4317 --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-master-taskloop-simd.f90 @@ -0,0 +1,14 @@ +! This test checks lowering of OpenMP parallel master taskloop simd Directive. + +! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s + +subroutine test_parallel_master_taskloop_simd + integer :: i, j = 1 + !CHECK: not yet implemented: Composite TASKLOOP SIMD + !$omp parallel master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop simd +end subroutine diff --git a/flang/test/Lower/OpenMP/parallel-master-taskloop.f90 b/flang/test/Lower/OpenMP/parallel-master-taskloop.f90 new file mode 100644 index 0000000000000000000000000000000000000000..17ceb9496c8d34223ff8c4819ee91880ea4a714c --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-master-taskloop.f90 @@ -0,0 +1,14 @@ +! This test checks lowering of OpenMP parallel master taskloop Directive. + +! RUN: %not_todo_cmd bbc -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %not_todo_cmd %flang_fc1 -emit-fir -fopenmp -o - %s 2>&1 | FileCheck %s + +subroutine test_parallel_master_taskloop + integer :: i, j = 1 + !CHECK: not yet implemented: Taskloop construct + !$omp parallel master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop +end subroutine diff --git a/flang/test/Lower/OpenMP/parallel-master.f90 b/flang/test/Lower/OpenMP/parallel-master.f90 new file mode 100644 index 0000000000000000000000000000000000000000..8f3ee31b328537ecc8408e5d9d45055a8ee846c2 --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-master.f90 @@ -0,0 +1,16 @@ +! This test checks lowering of the parallel master combined construct. + +! RUN: bbc -fopenmp -emit-hlfir %s -o - | FileCheck %s +! RUN: %flang_fc1 -fopenmp -emit-hlfir %s -o - | FileCheck %s + +! CHECK-LABEL: func @_QPparallel_master +subroutine parallel_master(x) + integer :: x + !CHECK: omp.parallel { + !CHECK: omp.master { + !$omp parallel master + x = 1 + !$omp end parallel master + !CHECK: } + !CHECK: } +end subroutine parallel_master diff --git a/flang/test/Lower/OpenMP/parallel-reduction-mixed.f90 b/flang/test/Lower/OpenMP/parallel-reduction-mixed.f90 index 262075ec9b25d0ede3d8a03bb973df3877d4522f..8e6f55abd5671c93c44e9b3a81acde813f2282ed 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction-mixed.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction-mixed.f90 @@ -17,7 +17,7 @@ subroutine proc end subroutine proc !CHECK-LABEL: define void @proc_() -!CHECK: call void +!CHECK: call void (ptr, i32, ptr, ...) !CHECK-SAME: @__kmpc_fork_call(ptr {{.*}}, i32 1, ptr @[[OMP_PAR:.*]], {{.*}}) !CHECK: define internal void @[[OMP_PAR]](ptr {{.*}} %[[TID_ADDR:.*]], ptr noalias diff --git a/flang/test/Lower/allocatable-polymorphic.f90 b/flang/test/Lower/allocatable-polymorphic.f90 index e23e38ffb4b013980bc98f593eb606677ce6d88c..4d70e1ea4c739ab7152d186c9a9285d58d5ccbf2 100644 --- a/flang/test/Lower/allocatable-polymorphic.f90 +++ b/flang/test/Lower/allocatable-polymorphic.f90 @@ -603,10 +603,9 @@ end ! LLVM: %{{.*}} = call {} @_FortranAAllocatableInitDerivedForAllocate(ptr %{{.*}}, ptr @_QMpolyEXdtXp2, i32 1, i32 0) ! LLVM: %{{.*}} = call {} @_FortranAAllocatableSetBounds(ptr %{{.*}}, i32 0, i64 1, i64 20) ! LLVM: %{{.*}} = call i32 @_FortranAAllocatableAllocate(ptr %{{.*}}, i1 false, ptr null, ptr @_QQclX{{.*}}, i32 {{.*}}) -! LLVM-COUNT-2: call void %{{.*}}() +! LLVM-COUNT-2: call void %{{[0-9]*}}() -! LLVM: %[[C1_LOAD:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %{{.*}} -! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[C1_LOAD]], ptr %{{.*}} +! LLVM: call void @llvm.memcpy.p0.p0.i32 ! LLVM: %[[GEP_TDESC_C1:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 7 ! LLVM: %[[TDESC_C1:.*]] = load ptr, ptr %[[GEP_TDESC_C1]] ! LLVM: %[[ELEM_SIZE_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 1 @@ -620,8 +619,7 @@ end ! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %{{.*}}, ptr %[[TMP:.*]] ! LLVM: call void %{{.*}}(ptr %{{.*}}) -! LLVM: %[[LOAD_C2:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %{{.*}} -! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOAD_C2]], ptr %{{.*}} +! LLVM: call void @llvm.memcpy.p0.p0.i32 ! LLVM: %[[GEP_TDESC_C2:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 7 ! LLVM: %[[TDESC_C2:.*]] = load ptr, ptr %[[GEP_TDESC_C2]] ! LLVM: %[[ELEM_SIZE_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 1 @@ -635,9 +633,7 @@ end ! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %{{.*}}, ptr %{{.*}} ! LLVM: call void %{{.*}}(ptr %{{.*}}) -! LLVM: %[[C3_LOAD:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %{{.*}} -! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } %[[C3_LOAD]], ptr %{{.*}} - +! LLVM: call void @llvm.memcpy.p0.p0.i32 ! LLVM: %[[GEP_TDESC_C3:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 8 ! LLVM: %[[TDESC_C3:.*]] = load ptr, ptr %[[GEP_TDESC_C3]] ! LLVM: %[[ELE_SIZE_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 1 @@ -658,8 +654,7 @@ end ! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[BOX7]], ptr %{{.*}} ! LLVM: call void %{{.*}}(ptr %{{.*}}) -! LLVM: %[[C4_LOAD:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %{{.*}} -! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } %[[C4_LOAD]], ptr %{{.*}} +! LLVM: call void @llvm.memcpy.p0.p0.i32 ! LLVM: %[[GEP_TDESC_C4:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 8 ! LLVM: %[[TDESC_C4:.*]] = load ptr, ptr %[[GEP_TDESC_C4]] ! LLVM: %[[ELE_SIZE_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 1 @@ -686,8 +681,7 @@ end ! LLVM-LABEL: define void @_QMpolyPtest_deallocate() ! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } { ptr null, i64 ptrtoint (ptr getelementptr (%_QMpolyTp1, ptr null, i32 1) to i64), i32 20240719, i8 0, i8 42, i8 2, i8 1, ptr @_QMpolyEXdtXp1, [1 x i64] zeroinitializer }, ptr %[[ALLOCA1:[0-9]*]] -! LLVM: %[[LOAD:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[ALLOCA1]] -! LLVM: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOAD]], ptr %[[ALLOCA2:[0-9]*]] +! LLVM: call void @llvm.memcpy.p0.p0.i32(ptr %[[ALLOCA2:[0-9]+]], ptr %[[ALLOCA1]], i32 40, i1 false) ! LLVM: %{{.*}} = call {} @_FortranAAllocatableInitDerivedForAllocate(ptr %[[ALLOCA2]], ptr @_QMpolyEXdtXp1, i32 0, i32 0) ! LLVM: %{{.*}} = call i32 @_FortranAAllocatableAllocate(ptr %[[ALLOCA2]], i1 false, ptr null, ptr @_QQclX{{.*}}, i32 {{.*}}) ! LLVM: %{{.*}} = call i32 @_FortranAAllocatableDeallocatePolymorphic(ptr %[[ALLOCA2]], ptr {{.*}}, i1 false, ptr null, ptr @_QQclX{{.*}}, i32 {{.*}}) diff --git a/flang/test/Parser/OpenMP/depobj-construct.f90 b/flang/test/Parser/OpenMP/depobj-construct.f90 new file mode 100644 index 0000000000000000000000000000000000000000..7c474071bc1e678889085f52ae631edb45b804d0 --- /dev/null +++ b/flang/test/Parser/OpenMP/depobj-construct.f90 @@ -0,0 +1,64 @@ +!RUN: %flang_fc1 -fdebug-unparse -fopenmp -fopenmp-version=52 %s | FileCheck --ignore-case --check-prefix="UNPARSE" %s +!RUN: %flang_fc1 -fdebug-dump-parse-tree -fopenmp -fopenmp-version=52 %s | FileCheck --check-prefix="PARSE-TREE" %s + +subroutine f00 + integer :: x, y + !$omp depobj(x) depend(in: y) +end + +!UNPARSE: SUBROUTINE f00 +!UNPARSE: INTEGER x, y +!UNPARSE: !$OMP DEPOBJ(x) DEPEND(IN:y) +!UNPARSE: END SUBROUTINE + +!PARSE-TREE: ExecutionPartConstruct -> ExecutableConstruct -> OpenMPConstruct -> OpenMPStandaloneConstruct -> OpenMPDepobjConstruct +!PARSE-TREE: | Verbatim +!PARSE-TREE: | OmpObject -> Designator -> DataRef -> Name = 'x' +!PARSE-TREE: | OmpClause -> Depend -> OmpDependClause -> InOut +!PARSE-TREE: | | OmpTaskDependenceType -> Type = In +!PARSE-TREE: | | OmpObjectList -> OmpObject -> Designator -> DataRef -> Name = 'y' + +subroutine f01 + integer :: x + !$omp depobj(x) update(out) +end + +!UNPARSE: SUBROUTINE f01 +!UNPARSE: INTEGER x +!UNPARSE: !$OMP DEPOBJ(x) UPDATE(OUT) +!UNPARSE: END SUBROUTINE + +!PARSE-TREE: ExecutionPartConstruct -> ExecutableConstruct -> OpenMPConstruct -> OpenMPStandaloneConstruct -> OpenMPDepobjConstruct +!PARSE-TREE: | Verbatim +!PARSE-TREE: | OmpObject -> Designator -> DataRef -> Name = 'x' +!PARSE-TREE: | OmpClause -> Update -> OmpUpdateClause -> OmpTaskDependenceType -> Type = Out + +subroutine f02 + integer :: x + !$omp depobj(x) destroy(x) +end + +!UNPARSE: SUBROUTINE f02 +!UNPARSE: INTEGER x +!UNPARSE: !$OMP DEPOBJ(x) DESTROY(x) +!UNPARSE: END SUBROUTINE + +!PARSE-TREE: ExecutionPartConstruct -> ExecutableConstruct -> OpenMPConstruct -> OpenMPStandaloneConstruct -> OpenMPDepobjConstruct +!PARSE-TREE: | Verbatim +!PARSE-TREE: | OmpObject -> Designator -> DataRef -> Name = 'x' +!PARSE-TREE: | OmpClause -> Destroy -> OmpDestroyClause -> OmpObject -> Designator -> DataRef -> Name = 'x' + +subroutine f03 + integer :: x + !$omp depobj(x) destroy +end + +!UNPARSE: SUBROUTINE f03 +!UNPARSE: INTEGER x +!UNPARSE: !$OMP DEPOBJ(x) DESTROY +!UNPARSE: END SUBROUTINE + +!PARSE-TREE: ExecutionPartConstruct -> ExecutableConstruct -> OpenMPConstruct -> OpenMPStandaloneConstruct -> OpenMPDepobjConstruct +!PARSE-TREE: | Verbatim +!PARSE-TREE: | OmpObject -> Designator -> DataRef -> Name = 'x' +!PARSE-TREE: | OmpClause -> Destroy -> diff --git a/flang/test/Parser/OpenMP/master-unparse.f90 b/flang/test/Parser/OpenMP/master-unparse.f90 new file mode 100644 index 0000000000000000000000000000000000000000..30c293a521b5d1eaaa3bda7557284100cedb08f4 --- /dev/null +++ b/flang/test/Parser/OpenMP/master-unparse.f90 @@ -0,0 +1,73 @@ +! RUN: %flang_fc1 -fdebug-unparse -fopenmp %s | FileCheck --ignore-case %s +! RUN: %flang_fc1 -fdebug-dump-parse-tree -fopenmp %s | FileCheck --check-prefix="PARSE-TREE" %s + +! Check for parsing of master directive + + +subroutine test_master() + integer :: c = 1 + !PARSE-TREE: OmpBeginBlockDirective + !PARSE-TREE-NEXT: OmpBlockDirective -> llvm::omp::Directive = master + !CHECK: !$omp master + !$omp master + c = c + 1 + !$omp end master +end subroutine + +subroutine test_master_taskloop_simd() + integer :: i, j = 1 + !PARSE-TREE: OmpBeginLoopDirective + !PARSE-TREE-NEXT: OmpLoopDirective -> llvm::omp::Directive = master taskloop simd + !CHECK: !$omp master taskloop simd + !$omp master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop simd +end subroutine + +subroutine test_master_taskloop + integer :: i, j = 1 + !PARSE-TREE: OmpBeginLoopDirective + !PARSE-TREE-NEXT: OmpLoopDirective -> llvm::omp::Directive = master taskloop + !CHECK: !$omp master taskloop + !$omp master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop +end subroutine + +subroutine test_parallel_master + integer :: c = 2 + !PARSE-TREE: OmpBeginBlockDirective + !PARSE-TREE-NEXT: OmpBlockDirective -> llvm::omp::Directive = parallel master + !CHECK: !$omp parallel master + !$omp parallel master + c = c + 2 + !$omp end parallel master +end subroutine + +subroutine test_parallel_master_taskloop_simd + integer :: i, j = 1 + !PARSE-TREE: OmpBeginLoopDirective + !PARSE-TREE-NEXT: OmpLoopDirective -> llvm::omp::Directive = parallel master taskloop simd + !CHECK: !$omp parallel master taskloop simd + !$omp parallel master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop simd +end subroutine + +subroutine test_parallel_master_taskloop + integer :: i, j = 1 + !PARSE-TREE: OmpBeginLoopDirective + !PARSE-TREE-NEXT: OmpLoopDirective -> llvm::omp::Directive = parallel master taskloop + !CHECK: !$omp parallel master taskloop + !$omp parallel master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop +end subroutine diff --git a/flang/test/Semantics/OpenMP/clause-validity01.f90 b/flang/test/Semantics/OpenMP/clause-validity01.f90 index 1a7a57b124e9bda42a58c8e7f37a6f111f2e3b38..124f1a02d99fba7114836c53da5315cc65951f33 100644 --- a/flang/test/Semantics/OpenMP/clause-validity01.f90 +++ b/flang/test/Semantics/OpenMP/clause-validity01.f90 @@ -476,14 +476,14 @@ use omp_lib ! 2.13.1 master !$omp parallel - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master a=3.14 !$omp end master !$omp end parallel !$omp parallel - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: NUM_THREADS clause is not allowed on the MASTER directive !$omp master num_threads(4) a=3.14 diff --git a/flang/test/Semantics/OpenMP/depobj-construct-v50.f90 b/flang/test/Semantics/OpenMP/depobj-construct-v50.f90 new file mode 100644 index 0000000000000000000000000000000000000000..e7fa24d521b63b714d67c5be231985f36c151f47 --- /dev/null +++ b/flang/test/Semantics/OpenMP/depobj-construct-v50.f90 @@ -0,0 +1,28 @@ +!RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=50 + +subroutine f00 + integer :: obj +!ERROR: A DEPEND clause on a DEPOBJ construct must not have SOURCE, SINK or DEPOBJ as dependence-type + !$omp depobj(obj) depend(source) +end + +subroutine f01 + integer :: obj + integer :: x, y +!ERROR: A DEPEND clause on a DEPOBJ construct must only specify one locator + !$omp depobj(obj) depend(in: x, y) +end + +subroutine f02 + integer :: obj + integer :: x(10) +!WARNING: An iterator-modifier may specify multiple locators, a DEPEND clause on a DEPOBJ construct must only specify one locator + !$omp depobj(obj) depend(iterator(i = 1:10), in: x(i)) +end + +subroutine f03 + integer :: obj, jbo +!ERROR: The DESTROY clause must refer to the same object as the DEPOBJ construct +!PORTABILITY: The object parameter in DESTROY clause in DEPOPJ construct was introduced in OpenMP v5.2 + !$omp depobj(obj) destroy(jbo) +end diff --git a/flang/test/Semantics/OpenMP/depobj-construct-v51.f90 b/flang/test/Semantics/OpenMP/depobj-construct-v51.f90 new file mode 100644 index 0000000000000000000000000000000000000000..fa0c025a1101000e1d6a68d55b2b9b9fef9cfe27 --- /dev/null +++ b/flang/test/Semantics/OpenMP/depobj-construct-v51.f90 @@ -0,0 +1,13 @@ +!RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=51 + +subroutine f04 + integer :: obj +!ERROR: An UPDATE clause on a DEPOBJ construct must not have SOURCE, SINK or DEPOBJ as dependence-type + !$omp depobj(obj) update(source) +end + +subroutine f05 + integer :: obj +!ERROR: An UPDATE clause on a DEPOBJ construct must not have SOURCE, SINK or DEPOBJ as dependence-type + !$omp depobj(obj) update(depobj) +end diff --git a/flang/test/Semantics/OpenMP/depobj-construct-v52.f90 b/flang/test/Semantics/OpenMP/depobj-construct-v52.f90 new file mode 100644 index 0000000000000000000000000000000000000000..f2e66485c6c8017de701b01ed4105fe781cfbef6 --- /dev/null +++ b/flang/test/Semantics/OpenMP/depobj-construct-v52.f90 @@ -0,0 +1,15 @@ +!RUN: %python %S/../test_errors.py %s %flang -fopenmp -fopenmp-version=52 + +subroutine f00 + integer :: obj +!WARNING: The SOURCE task-dependence-type is deprecated in OpenMP v5.2 +!ERROR: A DEPEND clause on a DEPOBJ construct must not have SOURCE or SINK as dependence-type + !$omp depobj(obj) depend(source) +end + +subroutine f03 + integer :: obj, jbo +!Note: no portability message +!ERROR: The DESTROY clause must refer to the same object as the DEPOBJ construct + !$omp depobj(obj) destroy(jbo) +end diff --git a/flang/test/Semantics/OpenMP/deprecation.f90 b/flang/test/Semantics/OpenMP/deprecation.f90 new file mode 100644 index 0000000000000000000000000000000000000000..e04f43026bbce27fe15f0808bf5598d87979aee5 --- /dev/null +++ b/flang/test/Semantics/OpenMP/deprecation.f90 @@ -0,0 +1,59 @@ +! RUN: %python %S/../test_errors.py %s %flang_fc1 -fopenmp -Werror + +! Check for deprecation of master directive and its combined/composite variants + +subroutine test_master() + integer :: c = 1 +!WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. + !$omp master + c = c + 1 + !$omp end master +end subroutine + +subroutine test_parallel_master + integer :: c = 2 +!WARNING: OpenMP directive PARALLEL MASTER has been deprecated, please use PARALLEL MASKED instead. + !$omp parallel master + c = c + 2 + !$omp end parallel master +end subroutine + +subroutine test_master_taskloop_simd() + integer :: i, j = 1 +!WARNING: OpenMP directive MASTER TASKLOOP SIMD has been deprecated, please use MASKED TASKLOOP SIMD instead. + !$omp master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop simd +end subroutine + +subroutine test_master_taskloop + integer :: i, j = 1 +!WARNING: OpenMP directive MASTER TASKLOOP has been deprecated, please use MASKED TASKLOOP instead. + !$omp master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end master taskloop +end subroutine + +subroutine test_parallel_master_taskloop_simd + integer :: i, j = 1 +!WARNING: OpenMP directive PARALLEL MASTER TASKLOOP SIMD has been deprecated, please use PARALLEL_MASKED TASKLOOP SIMD instead. + !$omp parallel master taskloop simd + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop simd +end subroutine + +subroutine test_parallel_master_taskloop + integer :: i, j = 1 +!WARNING: OpenMP directive PARALLEL MASTER TASKLOOP has been deprecated, please use PARALLEL MASKED TASKLOOP instead. + !$omp parallel master taskloop + do i=1,10 + j = j + 1 + end do + !$omp end parallel master taskloop +end subroutine diff --git a/flang/test/Semantics/OpenMP/flush02.f90 b/flang/test/Semantics/OpenMP/flush02.f90 index f06719f302fd7a7025711c13eb66e4c942969a07..ed0cf6602d574afb96e9415ad3e14ed72943e19b 100644 --- a/flang/test/Semantics/OpenMP/flush02.f90 +++ b/flang/test/Semantics/OpenMP/flush02.f90 @@ -80,7 +80,7 @@ use omp_lib !$omp parallel num_threads(4) array = (/1, 2, 3, 4, 5, 6, 7, 8, 9, 10/) - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master !$omp flush (array) !$omp end master diff --git a/flang/test/Semantics/OpenMP/nested-barrier.f90 b/flang/test/Semantics/OpenMP/nested-barrier.f90 index aae283229e330d1ff1f6f6303c2655d1d53b1051..7c635d8e23cc0d1df87d3d3b43a3b7cdca2d1bbb 100644 --- a/flang/test/Semantics/OpenMP/nested-barrier.f90 +++ b/flang/test/Semantics/OpenMP/nested-barrier.f90 @@ -75,7 +75,7 @@ program omp_nest_barrier end do !$omp end critical - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master do i = 1, 10 k = k + 1 @@ -108,7 +108,7 @@ program omp_nest_barrier end do !$omp end ordered - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master do i = 1, 10 !ERROR: `DISTRIBUTE` region has to be strictly nested inside `TEAMS` region. diff --git a/flang/test/Semantics/OpenMP/nested-master.f90 b/flang/test/Semantics/OpenMP/nested-master.f90 index 069de67cafae2864824c74c2e9e785243e7f7ae2..b21ca5d141593186e98d6157051ee42ad8365e07 100644 --- a/flang/test/Semantics/OpenMP/nested-master.f90 +++ b/flang/test/Semantics/OpenMP/nested-master.f90 @@ -9,7 +9,7 @@ program omp_nest_master !$omp do do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 @@ -17,7 +17,7 @@ program omp_nest_master end do !$omp sections - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master do i = 1, 10 @@ -27,7 +27,7 @@ program omp_nest_master !$omp end sections !$omp single - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master do i = 1, 10 @@ -41,7 +41,7 @@ program omp_nest_master !$omp task do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 @@ -52,7 +52,7 @@ program omp_nest_master !$omp taskloop do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 @@ -63,7 +63,7 @@ program omp_nest_master !$omp target parallel do simd do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: The only OpenMP constructs that can be encountered during execution of a 'SIMD' region are the `ATOMIC` construct, the `LOOP` construct, the `SIMD` construct and the `ORDERED` construct with the `SIMD` clause. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master @@ -75,7 +75,7 @@ program omp_nest_master !$omp critical do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master j = j -1 !$omp end master @@ -85,7 +85,7 @@ program omp_nest_master !$omp ordered do i = 1, 10 k = k + 1 - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master j = j -1 !$omp end master @@ -99,7 +99,7 @@ program omp_nest_master !$omp distribute do k =1, 10 print *, "hello" - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master j = j -1 !$omp end master @@ -116,7 +116,7 @@ program omp_nest_master !$omp distribute do k =1, 10 print *, "hello" - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master j = j -1 !$omp end master @@ -133,7 +133,7 @@ program omp_nest_master !$omp distribute do k =1, 10 print *, "hello" - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 @@ -151,7 +151,7 @@ program omp_nest_master !$omp distribute do k =1, 10 print *, "hello" - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$omp master j = j -1 diff --git a/flang/test/Semantics/OpenMP/nested-teams.f90 b/flang/test/Semantics/OpenMP/nested-teams.f90 index f3b96b0ab439036b3a8f809c149aad5f94921262..06eea12aba55956b983548b5febadab8a67d3371 100644 --- a/flang/test/Semantics/OpenMP/nested-teams.f90 +++ b/flang/test/Semantics/OpenMP/nested-teams.f90 @@ -42,7 +42,7 @@ program main !$omp end teams end do - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$omp master !ERROR: TEAMS region can only be strictly nested within the implicit parallel region or TARGET region !$omp teams diff --git a/flang/test/Semantics/OpenMP/ordered-simd.f90 b/flang/test/Semantics/OpenMP/ordered-simd.f90 index ed52b759491002842f144fb9780db14121dd6e6c..716dc42c28bb644c204ceda22f1c6c5edbff9427 100644 --- a/flang/test/Semantics/OpenMP/ordered-simd.f90 +++ b/flang/test/Semantics/OpenMP/ordered-simd.f90 @@ -95,7 +95,7 @@ SUBROUTINE ORDERED_BAD(N) !$OMP CRITICAL C = C - A * B - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$OMP MASTER DO I = 1,N !ERROR: `ORDERED` region may not be closely nested inside of `CRITICAL`, `ORDERED`, explicit `TASK` or `TASKLOOP` region. @@ -108,7 +108,7 @@ SUBROUTINE ORDERED_BAD(N) !$OMP ORDERED C = C - A * B - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !$OMP MASTER DO I = 1,N !ERROR: `ORDERED` region may not be closely nested inside of `CRITICAL`, `ORDERED`, explicit `TASK` or `TASKLOOP` region. @@ -121,7 +121,7 @@ SUBROUTINE ORDERED_BAD(N) !$OMP TASK C = C - A * B - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$OMP MASTER DO I = 1,N @@ -136,7 +136,7 @@ SUBROUTINE ORDERED_BAD(N) !$OMP TASKLOOP DO J= 1,N C = C - A * B - !WARNING: OpenMP directive 'master' has been deprecated, please use 'masked' instead. + !WARNING: OpenMP directive MASTER has been deprecated, please use MASKED instead. !ERROR: `MASTER` region may not be closely nested inside of `WORKSHARING`, `LOOP`, `TASK`, `TASKLOOP`, or `ATOMIC` region. !$OMP MASTER DO I = 1,N diff --git a/flang/test/Transforms/debug-tuple-type.fir b/flang/test/Transforms/debug-tuple-type.fir new file mode 100644 index 0000000000000000000000000000000000000000..c9b0d16c06e1ae2f5b4f11c5c5fb0f7852fc6b85 --- /dev/null +++ b/flang/test/Transforms/debug-tuple-type.fir @@ -0,0 +1,15 @@ +// RUN: fir-opt --add-debug-info --mlir-print-debuginfo %s | FileCheck %s + +module attributes {dlti.dl_spec = #dlti.dl_spec<>} { + func.func private @fn1(!fir.ref>) + func.func private @_FortranAioOutputDerivedType(!fir.ref>) +} + +// CHECK: #[[F64:.*]] = #llvm.di_basic_type +// CHECK: #[[CU:.*]] = #llvm.di_compile_unit<{{.*}}> +// CHECK: #[[DTY1:.*]] = #llvm.di_derived_type +// CHECK: #[[DTY2:.*]] = #llvm.di_derived_type +// CHECK: #[[COM_TY1:.*]] = #llvm.di_composite_type +// CHECK: #[[COM_TY2:.*]] = #llvm.di_composite_type +// CHECK: #llvm.di_subroutine_type +// CHECK: #llvm.di_subroutine_type diff --git a/flang/tools/CMakeLists.txt b/flang/tools/CMakeLists.txt index 337545ae0d4d7a244a036713549e2944abc44a6d..1d2d2c608faf954fbd796d412259dee6047076dc 100644 --- a/flang/tools/CMakeLists.txt +++ b/flang/tools/CMakeLists.txt @@ -12,3 +12,4 @@ add_subdirectory(flang-driver) add_subdirectory(tco) add_subdirectory(f18-parse-demo) add_subdirectory(fir-opt) +add_subdirectory(fir-lsp-server) diff --git a/flang/tools/fir-lsp-server/CMakeLists.txt b/flang/tools/fir-lsp-server/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..ff0ced6693b97f3a4e9cefd647417061b80eb929 --- /dev/null +++ b/flang/tools/fir-lsp-server/CMakeLists.txt @@ -0,0 +1,17 @@ +set(LLVM_LINK_COMPONENTS + Core + Support + AsmParser + ) + +add_flang_tool(fir-lsp-server fir-lsp-server.cpp) + +get_property(dialect_libs GLOBAL PROPERTY MLIR_DIALECT_LIBS) +get_property(extension_libs GLOBAL PROPERTY MLIR_EXTENSION_LIBS) +target_link_libraries(fir-lsp-server PRIVATE + CUFDialect + FIRDialect + HLFIRDialect + MLIRLspServerLib + ${dialect_libs} + ${extension_libs}) diff --git a/flang/tools/fir-lsp-server/fir-lsp-server.cpp b/flang/tools/fir-lsp-server/fir-lsp-server.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8b724e292b5abbc71a6180f6453377f6fd18aa7e --- /dev/null +++ b/flang/tools/fir-lsp-server/fir-lsp-server.cpp @@ -0,0 +1,9 @@ +#include "mlir/Tools/mlir-lsp-server/MlirLspServerMain.h" +#include "flang/Optimizer/Support/InitFIR.h" + +int main(int argc, char **argv) { + mlir::DialectRegistry registry; + fir::support::registerNonCodegenDialects(registry); + fir::support::addFIRExtensions(registry); + return mlir::failed(mlir::MlirLspServerMain(argc, argv, registry)); +} diff --git a/libc/include/llvm-libc-macros/linux/signal-macros.h b/libc/include/llvm-libc-macros/linux/signal-macros.h index e379fc41efd02f53aa65767d0e0d71317622788e..0b7317ebc9b80a1dbd5965a6dd68b7e3068413d0 100644 --- a/libc/include/llvm-libc-macros/linux/signal-macros.h +++ b/libc/include/llvm-libc-macros/linux/signal-macros.h @@ -76,15 +76,12 @@ #define SS_ONSTACK 0x1 #define SS_DISABLE 0x2 -#ifdef __x86_64__ +#if defined(__x86_64__) || defined(__i386__) || defined(__riscv) #define MINSIGSTKSZ 2048 #define SIGSTKSZ 8192 #elif defined(__aarch64__) #define MINSIGSTKSZ 5120 #define SIGSTKSZ 16384 -#elif defined(__riscv) -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 #else #error "Signal stack sizes not defined for your platform." #endif diff --git a/libc/include/llvm-libc-types/fexcept_t.h b/libc/include/llvm-libc-types/fexcept_t.h index 60687bd1318aa4d34abea0887e4c7e1aed2b26b1..5aa09fbbaffc77d10e63164fa5da884eda90acff 100644 --- a/libc/include/llvm-libc-types/fexcept_t.h +++ b/libc/include/llvm-libc-types/fexcept_t.h @@ -9,6 +9,10 @@ #ifndef LLVM_LIBC_TYPES_FEXCEPT_T_H #define LLVM_LIBC_TYPES_FEXCEPT_T_H -typedef int fexcept_t; +#if defined(__x86_64__) || defined(__i386__) +typedef unsigned short int fexcept_t; +#else +typedef unsigned int fexcept_t; +#endif #endif // LLVM_LIBC_TYPES_FEXCEPT_T_H diff --git a/libc/include/llvm-libc-types/jmp_buf.h b/libc/include/llvm-libc-types/jmp_buf.h index 60e033c6c65a95d026be270a61b138ebc09f08a7..f246e6491cf5549a64fa4cb97e2425250a352a24 100644 --- a/libc/include/llvm-libc-types/jmp_buf.h +++ b/libc/include/llvm-libc-types/jmp_buf.h @@ -19,6 +19,13 @@ typedef struct { __UINT64_TYPE__ r15; __UINTPTR_TYPE__ rsp; __UINTPTR_TYPE__ rip; +#elif defined(__i386__) + long ebx; + long esi; + long edi; + long ebp; + long esp; + long eip; #elif defined(__riscv) /* Program counter. */ long int __pc; diff --git a/libc/src/setjmp/x86_64/longjmp.cpp b/libc/src/setjmp/x86_64/longjmp.cpp index c293c55a6f9fb2bec416f4c238e57be2d57825aa..143c9deb11e9aafafcabac0f58fd2d5a827f97b1 100644 --- a/libc/src/setjmp/x86_64/longjmp.cpp +++ b/libc/src/setjmp/x86_64/longjmp.cpp @@ -11,12 +11,34 @@ #include "src/__support/common.h" #include "src/__support/macros/config.h" -#if !defined(LIBC_TARGET_ARCH_IS_X86_64) +#if !defined(LIBC_TARGET_ARCH_IS_X86) #error "Invalid file include" #endif namespace LIBC_NAMESPACE_DECL { +#ifdef __i386__ +[[gnu::naked]] +LLVM_LIBC_FUNCTION(void, longjmp, (jmp_buf, int)) { + asm(R"( + mov 0x4(%%esp), %%ecx + mov 0x8(%%esp), %%eax + cmpl $0x1, %%eax + adcl $0x0, %%eax + + mov %c[ebx](%%ecx), %%ebx + mov %c[esi](%%ecx), %%esi + mov %c[edi](%%ecx), %%edi + mov %c[ebp](%%ecx), %%ebp + mov %c[esp](%%ecx), %%esp + + jmp *%c[eip](%%ecx) + )" ::[ebx] "i"(offsetof(__jmp_buf, ebx)), + [esi] "i"(offsetof(__jmp_buf, esi)), [edi] "i"(offsetof(__jmp_buf, edi)), + [ebp] "i"(offsetof(__jmp_buf, ebp)), [esp] "i"(offsetof(__jmp_buf, esp)), + [eip] "i"(offsetof(__jmp_buf, eip))); +} +#else [[gnu::naked]] LLVM_LIBC_FUNCTION(void, longjmp, (jmp_buf, int)) { asm(R"( @@ -38,5 +60,6 @@ LLVM_LIBC_FUNCTION(void, longjmp, (jmp_buf, int)) { [r15] "i"(offsetof(__jmp_buf, r15)), [rsp] "i"(offsetof(__jmp_buf, rsp)), [rip] "i"(offsetof(__jmp_buf, rip))); } +#endif } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/setjmp/x86_64/setjmp.cpp b/libc/src/setjmp/x86_64/setjmp.cpp index f6e82642edd7da68d2eec1a9dda83ef59d496eca..5ac10fa87b39a3bd2566460e4ab159b7a8a4d61c 100644 --- a/libc/src/setjmp/x86_64/setjmp.cpp +++ b/libc/src/setjmp/x86_64/setjmp.cpp @@ -11,12 +11,37 @@ #include "src/__support/macros/config.h" #include "src/setjmp/setjmp_impl.h" -#if !defined(LIBC_TARGET_ARCH_IS_X86_64) +#if !defined(LIBC_TARGET_ARCH_IS_X86) #error "Invalid file include" #endif namespace LIBC_NAMESPACE_DECL { +#ifdef __i386__ +[[gnu::naked]] +LLVM_LIBC_FUNCTION(int, setjmp, (jmp_buf buf)) { + asm(R"( + mov 4(%%esp), %%eax + + mov %%ebx, %c[ebx](%%eax) + mov %%esi, %c[esi](%%eax) + mov %%edi, %c[edi](%%eax) + mov %%ebp, %c[ebp](%%eax) + + lea 4(%%esp), %%ecx + mov %%ecx, %c[esp](%%eax) + + mov (%%esp), %%ecx + mov %%ecx, %c[eip](%%eax) + + xorl %%eax, %%eax + retl)" ::[ebx] "i"(offsetof(__jmp_buf, ebx)), + [esi] "i"(offsetof(__jmp_buf, esi)), [edi] "i"(offsetof(__jmp_buf, edi)), + [ebp] "i"(offsetof(__jmp_buf, ebp)), [esp] "i"(offsetof(__jmp_buf, esp)), + [eip] "i"(offsetof(__jmp_buf, eip)) + : "eax", "ecx"); +} +#else [[gnu::naked]] LLVM_LIBC_FUNCTION(int, setjmp, (jmp_buf buf)) { asm(R"( @@ -41,5 +66,6 @@ LLVM_LIBC_FUNCTION(int, setjmp, (jmp_buf buf)) { [rip] "i"(offsetof(__jmp_buf, rip)) : "rax"); } +#endif } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/string/string_utils.h b/libc/src/string/string_utils.h index 78381e46e480ddd333c39da868ec3ca3febe4866..22a1876da5369ce840464c2e9fc481e0cc144c1d 100644 --- a/libc/src/string/string_utils.h +++ b/libc/src/string/string_utils.h @@ -221,7 +221,7 @@ LIBC_INLINE size_t strlcpy(char *__restrict dst, const char *__restrict src, return len; size_t n = len < size - 1 ? len : size - 1; inline_memcpy(dst, src, n); - inline_bzero(dst + n, size - n); + dst[n] = '\0'; return len; } @@ -239,11 +239,13 @@ LIBC_INLINE constexpr static char *strrchr_implementation(const char *src, int c) { char ch = static_cast(c); char *last_occurrence = nullptr; - for (; *src; ++src) { + while (true) { if (*src == ch) last_occurrence = const_cast(src); + if (!*src) + return last_occurrence; + ++src; } - return last_occurrence; } } // namespace internal diff --git a/libc/test/UnitTest/LibcTest.h b/libc/test/UnitTest/LibcTest.h index 2b972004e9eeaa94a8f58425faf878c49830d489..b4e3819ea958de5dd85c42857613afc63ba567a1 100644 --- a/libc/test/UnitTest/LibcTest.h +++ b/libc/test/UnitTest/LibcTest.h @@ -162,6 +162,14 @@ protected: (unsigned long long)RHS, LHSStr, RHSStr, Loc); } + // Helper to allow macro invocations like `ASSERT_EQ(foo, nullptr)`. + template , ValType> = nullptr> + bool test(TestCond Cond, ValType LHS, cpp::nullptr_t, const char *LHSStr, + const char *RHSStr, internal::Location Loc) { + return test(Cond, LHS, static_cast(nullptr), LHSStr, RHSStr, Loc); + } + template < typename ValType, cpp::enable_if_t< diff --git a/libc/test/src/math/exhaustive/sinpif_test.cpp b/libc/test/src/math/exhaustive/sinpif_test.cpp index 8bc1d81eb7e3d26d047c709c633a46179f238dbe..81abac0b73f27a0232c23a03becf7cc61feb76da 100644 --- a/libc/test/src/math/exhaustive/sinpif_test.cpp +++ b/libc/test/src/math/exhaustive/sinpif_test.cpp @@ -7,10 +7,8 @@ //===----------------------------------------------------------------------===// #include "exhaustive_test.h" -#include "mpfr.h" #include "src/math/sinpif.h" #include "utils/MPFRWrapper/MPFRUtils.h" -#include namespace mpfr = LIBC_NAMESPACE::testing::mpfr; diff --git a/libc/test/src/string/StrchrTest.h b/libc/test/src/string/StrchrTest.h index 74e172de95953e7030092ce172e667222b6ab07f..8c3fe5293008a198cbdd040d46b82afbdc5747a3 100644 --- a/libc/test/src/string/StrchrTest.h +++ b/libc/test/src/string/StrchrTest.h @@ -40,14 +40,16 @@ template struct StrchrTest : public LIBC_NAMESPACE::testing::Test { const char *src = "abcde"; // Should return null terminator. - ASSERT_STREQ(Func(src, '\0'), ""); + const char *nul_terminator = Func(src, '\0'); + ASSERT_NE(nul_terminator, nullptr); + ASSERT_STREQ(nul_terminator, ""); // Source string should not change. ASSERT_STREQ(src, "abcde"); } void characterNotWithinStringShouldReturnNullptr() { // Since 'z' is not within the string, should return nullptr. - ASSERT_STREQ(Func("123?", 'z'), nullptr); + ASSERT_EQ(Func("123?", 'z'), nullptr); } void theSourceShouldNotChange() { @@ -74,11 +76,13 @@ template struct StrchrTest : public LIBC_NAMESPACE::testing::Test { void emptyStringShouldOnlyMatchNullTerminator() { // Null terminator should match. - ASSERT_STREQ(Func("", '\0'), ""); + const char empty_string[] = ""; + ASSERT_EQ(static_cast(Func(empty_string, '\0')), + empty_string); // All other characters should not match. - ASSERT_STREQ(Func("", 'Z'), nullptr); - ASSERT_STREQ(Func("", '3'), nullptr); - ASSERT_STREQ(Func("", '*'), nullptr); + ASSERT_EQ(Func("", 'Z'), nullptr); + ASSERT_EQ(Func("", '3'), nullptr); + ASSERT_EQ(Func("", '*'), nullptr); } }; @@ -114,7 +118,9 @@ template struct StrrchrTest : public LIBC_NAMESPACE::testing::Test { const char *src = "abcde"; // Should return null terminator. - ASSERT_STREQ(Func(src, '\0'), ""); + const char *nul_terminator = Func(src, '\0'); + ASSERT_NE(nul_terminator, nullptr); + ASSERT_STREQ(nul_terminator, ""); // Source string should not change. ASSERT_STREQ(src, "abcde"); } @@ -122,9 +128,9 @@ template struct StrrchrTest : public LIBC_NAMESPACE::testing::Test { void findsLastBehindFirstNullTerminator() { static const char src[6] = {'a', 'a', '\0', 'b', '\0', 'c'}; // 'b' is behind a null terminator, so should not be found. - ASSERT_STREQ(Func(src, 'b'), nullptr); + ASSERT_EQ(Func(src, 'b'), nullptr); // Same goes for 'c'. - ASSERT_STREQ(Func(src, 'c'), nullptr); + ASSERT_EQ(Func(src, 'c'), nullptr); // Should find the second of the two a's. ASSERT_STREQ(Func(src, 'a'), "a"); @@ -132,7 +138,7 @@ template struct StrrchrTest : public LIBC_NAMESPACE::testing::Test { void characterNotWithinStringShouldReturnNullptr() { // Since 'z' is not within the string, should return nullptr. - ASSERT_STREQ(Func("123?", 'z'), nullptr); + ASSERT_EQ(Func("123?", 'z'), nullptr); } void shouldFindLastOfDuplicates() { @@ -146,11 +152,13 @@ template struct StrrchrTest : public LIBC_NAMESPACE::testing::Test { void emptyStringShouldOnlyMatchNullTerminator() { // Null terminator should match. - ASSERT_STREQ(Func("", '\0'), ""); + const char empty_string[] = ""; + ASSERT_EQ(static_cast(Func(empty_string, '\0')), + empty_string); // All other characters should not match. - ASSERT_STREQ(Func("", 'A'), nullptr); - ASSERT_STREQ(Func("", '2'), nullptr); - ASSERT_STREQ(Func("", '*'), nullptr); + ASSERT_EQ(Func("", 'A'), nullptr); + ASSERT_EQ(Func("", '2'), nullptr); + ASSERT_EQ(Func("", '*'), nullptr); } }; diff --git a/libc/test/src/string/strlcat_test.cpp b/libc/test/src/string/strlcat_test.cpp index 1ffa4b0e921e2b5d4bb1847d7dabe8fa8d5b3946..5757fc92b39d2aea754f98beb1c23af30a900b61 100644 --- a/libc/test/src/string/strlcat_test.cpp +++ b/libc/test/src/string/strlcat_test.cpp @@ -27,6 +27,15 @@ TEST(LlvmLibcStrlcatTest, Smaller) { EXPECT_STREQ(buf, "abcd"); } +TEST(LlvmLibcStrlcatTest, SmallerNoOverwriteAfter0) { + const char *str = "cd"; + char buf[8]{"ab\0\0efg"}; + + EXPECT_EQ(LIBC_NAMESPACE::strlcat(buf, str, 8), size_t(4)); + EXPECT_STREQ(buf, "abcd"); + EXPECT_STREQ(buf + 5, "fg"); +} + TEST(LlvmLibcStrlcatTest, No0) { const char *str = "cd"; char buf[7]{"ab"}; diff --git a/libc/test/src/string/strlcpy_test.cpp b/libc/test/src/string/strlcpy_test.cpp index 5a1e30c12963f36ac2cc3db5b8c393ba7fe43fbf..ecf0e925a265c3aded4f7c392a965f6f99afc391 100644 --- a/libc/test/src/string/strlcpy_test.cpp +++ b/libc/test/src/string/strlcpy_test.cpp @@ -25,6 +25,5 @@ TEST(LlvmLibcStrlcpyTest, Smaller) { EXPECT_EQ(LIBC_NAMESPACE::strlcpy(buf, str, 7), size_t(3)); EXPECT_STREQ(buf, "abc"); - for (const char *p = buf + 3; p < buf + 7; p++) - EXPECT_EQ(*p, '\0'); + EXPECT_STREQ(buf + 4, "11"); } diff --git a/libc/test/src/sys/statvfs/linux/CMakeLists.txt b/libc/test/src/sys/statvfs/linux/CMakeLists.txt index 1f8688868e0438ee7d1b16f1d140fd376373af11..fa1e9052d1cac4119c7e7e480d5c251c5d9cd8b6 100644 --- a/libc/test/src/sys/statvfs/linux/CMakeLists.txt +++ b/libc/test/src/sys/statvfs/linux/CMakeLists.txt @@ -8,8 +8,9 @@ add_libc_unittest( statvfs_test.cpp DEPENDS libc.src.errno.errno - libc.src.sys.statvfs.linux.statfs_utils libc.src.sys.statvfs.statvfs + libc.src.sys.stat.mkdirat + libc.src.sys.stat.rmdir libc.test.UnitTest.ErrnoSetterMatcher ) @@ -21,8 +22,9 @@ add_libc_unittest( fstatvfs_test.cpp DEPENDS libc.src.errno.errno - libc.src.sys.statvfs.linux.statfs_utils libc.src.sys.statvfs.fstatvfs + libc.src.sys.stat.mkdirat + libc.src.sys.stat.rmdir libc.src.fcntl.open libc.src.unistd.close libc.test.UnitTest.ErrnoSetterMatcher diff --git a/libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp b/libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp index 2f3e0b96ff09574ab5efc717dd84bb22ab535e65..efd1e688280b5f1aabae50dc562cf960c288bba9 100644 --- a/libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp +++ b/libc/test/src/sys/statvfs/linux/fstatvfs_test.cpp @@ -1,49 +1,56 @@ +//===-- Unittests for fstatvfs --------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + #include "hdr/fcntl_macros.h" #include "src/__support/macros/config.h" #include "src/fcntl/open.h" +#include "src/sys/stat/mkdirat.h" #include "src/sys/statvfs/fstatvfs.h" -#include "src/sys/statvfs/linux/statfs_utils.h" #include "src/unistd/close.h" +#include "src/unistd/rmdir.h" #include "test/UnitTest/ErrnoSetterMatcher.h" -#include "test/UnitTest/LibcTest.h" -#include +#include "test/UnitTest/Test.h" + using namespace LIBC_NAMESPACE::testing::ErrnoSetterMatcher; -#ifdef SYS_statfs64 -using StatFs = statfs64; -#else -using StatFs = statfs; -#endif - -namespace LIBC_NAMESPACE_DECL { -static int fstatfs(int fd, StatFs *buf) { - using namespace statfs_utils; - if (cpp::optional result = linux_fstatfs(fd)) { - *buf = *result; - return 0; - } - return -1; -} -} // namespace LIBC_NAMESPACE_DECL - -struct PathFD { - int fd; - explicit PathFD(const char *path) - : fd(LIBC_NAMESPACE::open(path, O_CLOEXEC | O_PATH)) {} - ~PathFD() { LIBC_NAMESPACE::close(fd); } - operator int() const { return fd; } -}; - -TEST(LlvmLibcSysStatvfsTest, FstatfsBasic) { - StatFs buf; - ASSERT_THAT(LIBC_NAMESPACE::fstatfs(PathFD("/"), &buf), Succeeds()); - ASSERT_THAT(LIBC_NAMESPACE::fstatfs(PathFD("/proc"), &buf), Succeeds()); - ASSERT_EQ(buf.f_type, static_cast(PROC_SUPER_MAGIC)); - ASSERT_THAT(LIBC_NAMESPACE::fstatfs(PathFD("/sys"), &buf), Succeeds()); - ASSERT_EQ(buf.f_type, static_cast(SYSFS_MAGIC)); +TEST(LlvmLibcSysFStatvfsTest, FStatvfsBasic) { + struct statvfs buf; + + int fd = LIBC_NAMESPACE::open("/", O_PATH); + ASSERT_ERRNO_SUCCESS(); + ASSERT_GT(fd, 0); + + // The root of the file directory must always exist + ASSERT_THAT(LIBC_NAMESPACE::fstatvfs(fd, &buf), Succeeds()); + ASSERT_THAT(LIBC_NAMESPACE::close(fd), Succeeds(0)); } -TEST(LlvmLibcSysStatvfsTest, FstatvfsInvalidFD) { +TEST(LlvmLibcSysFStatvfsTest, FStatvfsInvalidPath) { struct statvfs buf; - ASSERT_THAT(LIBC_NAMESPACE::fstatvfs(-1, &buf), Fails(EBADF)); + + constexpr const char *FILENAME = "testdata/statvfs.testdir"; + auto TEST_DIR = libc_make_test_file_path(FILENAME); + + ASSERT_THAT(LIBC_NAMESPACE::mkdirat(AT_FDCWD, TEST_DIR, S_IRWXU), + Succeeds(0)); + + int fd = LIBC_NAMESPACE::open(TEST_DIR, O_PATH); + ASSERT_ERRNO_SUCCESS(); + ASSERT_GT(fd, 0); + + // create the file, assert it exists, then delete it and assert it doesn't + // exist anymore. + + ASSERT_THAT(LIBC_NAMESPACE::fstatvfs(fd, &buf), Succeeds()); + + ASSERT_THAT(LIBC_NAMESPACE::rmdir(TEST_DIR), Succeeds(0)); + + ASSERT_THAT(LIBC_NAMESPACE::fstatvfs(fd, &buf), Fails(ENOENT)); + ASSERT_THAT(LIBC_NAMESPACE::close(fd), Succeeds(0)); + ASSERT_THAT(LIBC_NAMESPACE::fstatvfs(fd, &buf), Fails(ENOENT)); } diff --git a/libc/test/src/sys/statvfs/linux/statvfs_test.cpp b/libc/test/src/sys/statvfs/linux/statvfs_test.cpp index 5329adb54d64d015733c613637161367f0a065b5..0b154e7aa3fb7cf1dcb0f9c121b019410c5ab3e8 100644 --- a/libc/test/src/sys/statvfs/linux/statvfs_test.cpp +++ b/libc/test/src/sys/statvfs/linux/statvfs_test.cpp @@ -1,54 +1,43 @@ +//===-- Unittests for statvfs ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "hdr/fcntl_macros.h" #include "src/__support/macros/config.h" -#include "src/sys/statvfs/linux/statfs_utils.h" +#include "src/sys/stat/mkdirat.h" #include "src/sys/statvfs/statvfs.h" +#include "src/unistd/rmdir.h" #include "test/UnitTest/ErrnoSetterMatcher.h" -#include "test/UnitTest/LibcTest.h" -#include +#include "test/UnitTest/Test.h" + using namespace LIBC_NAMESPACE::testing::ErrnoSetterMatcher; -#ifdef SYS_statfs64 -using StatFs = statfs64; -#else -using StatFs = statfs; -#endif - -namespace LIBC_NAMESPACE_DECL { -static int statfs(const char *path, StatFs *buf) { - using namespace statfs_utils; - if (cpp::optional result = linux_statfs(path)) { - *buf = *result; - return 0; - } - return -1; -} -} // namespace LIBC_NAMESPACE_DECL - -TEST(LlvmLibcSysStatfsTest, StatfsBasic) { - StatFs buf; - ASSERT_THAT(LIBC_NAMESPACE::statfs("/", &buf), Succeeds()); - ASSERT_THAT(LIBC_NAMESPACE::statfs("/proc", &buf), Succeeds()); - ASSERT_EQ(buf.f_type, static_cast(PROC_SUPER_MAGIC)); - ASSERT_THAT(LIBC_NAMESPACE::statfs("/sys", &buf), Succeeds()); - ASSERT_EQ(buf.f_type, static_cast(SYSFS_MAGIC)); +TEST(LlvmLibcSysStatvfsTest, StatvfsBasic) { + struct statvfs buf; + // The root of the file directory must always exist + ASSERT_THAT(LIBC_NAMESPACE::statvfs("/", &buf), Succeeds()); } -TEST(LlvmLibcSysStatfsTest, StatvfsInvalidPath) { +TEST(LlvmLibcSysStatvfsTest, StatvfsInvalidPath) { struct statvfs buf; + ASSERT_THAT(LIBC_NAMESPACE::statvfs("", &buf), Fails(ENOENT)); - ASSERT_THAT(LIBC_NAMESPACE::statvfs("/nonexistent", &buf), Fails(ENOENT)); - ASSERT_THAT(LIBC_NAMESPACE::statvfs("/dev/null/whatever", &buf), - Fails(ENOTDIR)); - ASSERT_THAT(LIBC_NAMESPACE::statvfs(nullptr, &buf), Fails(EFAULT)); -} -TEST(LlvmLibcSysStatfsTest, StatvfsNameTooLong) { - struct statvfs buf; - ASSERT_THAT(LIBC_NAMESPACE::statvfs("/", &buf), Succeeds()); - char *name = static_cast(__builtin_alloca(buf.f_namemax + 3)); - name[0] = '/'; - name[buf.f_namemax + 2] = '\0'; - for (unsigned i = 1; i < buf.f_namemax + 2; ++i) { - name[i] = 'a'; - } - ASSERT_THAT(LIBC_NAMESPACE::statvfs(name, &buf), Fails(ENAMETOOLONG)); + // create the file, assert it exists, then delete it and assert it doesn't + // exist anymore. + constexpr const char *FILENAME = "testdata/statvfs.testdir"; + auto TEST_DIR = libc_make_test_file_path(FILENAME); + + ASSERT_THAT(LIBC_NAMESPACE::mkdirat(AT_FDCWD, TEST_DIR, S_IRWXU), + Succeeds(0)); + + ASSERT_THAT(LIBC_NAMESPACE::statvfs(TEST_DIR, &buf), Succeeds()); + + ASSERT_THAT(LIBC_NAMESPACE::rmdir(TEST_DIR), Succeeds(0)); + + ASSERT_THAT(LIBC_NAMESPACE::statvfs(TEST_DIR, &buf), Fails(ENOENT)); } diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 574b262018cd3a5c92342b222a55f9c6030487f0..95a7d10f055ea70fefc2a2321e7827ab23de35bd 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -45,10 +45,6 @@ include(CMakeDependentOption) include(HandleCompilerRT) # Basic options --------------------------------------------------------------- -option(LIBCXX_ENABLE_ASSERTIONS - "Enable assertions inside the compiled library, and at the same time make it the - default when compiling user code. Note that assertions can be enabled or disabled - by users in their own code regardless of this option." OFF) option(LIBCXX_ENABLE_SHARED "Build libc++ as a shared library." ON) option(LIBCXX_ENABLE_STATIC "Build libc++ as a static library." ON) option(LIBCXX_ENABLE_FILESYSTEM @@ -759,9 +755,9 @@ config_define_if_not(LIBCXX_ENABLE_WIDE_CHARACTERS _LIBCPP_HAS_NO_WIDE_CHARACTER config_define_if_not(LIBCXX_ENABLE_TIME_ZONE_DATABASE _LIBCPP_HAS_NO_TIME_ZONE_DATABASE) config_define_if_not(LIBCXX_ENABLE_VENDOR_AVAILABILITY_ANNOTATIONS _LIBCPP_HAS_NO_VENDOR_AVAILABILITY_ANNOTATIONS) +# TODO: Remove in LLVM 21. We're leaving an error to make this fail explicitly. if (LIBCXX_ENABLE_ASSERTIONS) - message(DEPRECATION "LIBCXX_ENABLE_ASSERTIONS is deprecated and will be removed in LLVM 20. Please use LIBCXX_HARDENING_MODE instead.") - set(LIBCXX_HARDENING_MODE "extensive") + message(FATAL_ERROR "LIBCXX_ENABLE_ASSERTIONS has been removed. Please use LIBCXX_HARDENING_MODE instead.") endif() if (LIBCXX_HARDENING_MODE STREQUAL "none") config_define(2 _LIBCPP_HARDENING_MODE_DEFAULT) diff --git a/libcxx/docs/ReleaseNotes/20.rst b/libcxx/docs/ReleaseNotes/20.rst index 84080e7cbafe2c4ae712204d595cee6a75852e82..bf3aafe6139ee957c5d55d0c77a1a5227f22a951 100644 --- a/libcxx/docs/ReleaseNotes/20.rst +++ b/libcxx/docs/ReleaseNotes/20.rst @@ -38,6 +38,7 @@ What's New in Libc++ 20.0.0? Implemented Papers ------------------ +- P0619R4: Reviewing Deprecated Facilities of C++17 for C++20 (`Github `__) - P2747R2: ``constexpr`` placement new (`Github `__) - P2609R3: Relaxing Ranges Just A Smidge (`Github `__) - P2985R0: A type trait for detecting virtual base classes (`Github `__) @@ -64,8 +65,9 @@ Improvements and New Features Deprecations and Removals ------------------------- -- TODO: The ``LIBCXX_ENABLE_ASSERTIONS`` CMake variable and the ``_LIBCPP_ENABLE_ASSERTIONS`` macro that were used to - enable the safe mode will be removed in LLVM 20. +- The ``LIBCXX_ENABLE_ASSERTIONS`` CMake variable and the ``_LIBCPP_ENABLE_ASSERTIONS`` macro that were used to + enable the safe mode have been removed in LLVM 20. Please use :ref:`support for hardening ` + instead. - Support for the C++20 synchronization library (````, ````, ``atomic::wait``, etc.) has been removed in language modes prior to C++20. If you are using these features prior to C++20, you will need to @@ -88,15 +90,14 @@ Deprecations and Removals the ``_LIBCPP_VERBOSE_ABORT_NOT_NOEXCEPT`` macro can be defined to make the function non-``noexcept``. That macro will be removed in LLVM 21. +- ````, ```` (previously missing), ````, and ```` are deprecated since C++17 as + specified by the standard. They, together with ````, are removed in C++20, but libc++ still provides these + headers as an extension and only deprecates them. The ``_LIBCPP_DISABLE_DEPRECATION_WARNINGS`` macro can be defined to + suppress deprecation for these headers. + Upcoming Deprecations and Removals ---------------------------------- -LLVM 20 -~~~~~~~ - -- TODO - - LLVM 21 ~~~~~~~ diff --git a/libcxx/docs/Status/Cxx20Papers.csv b/libcxx/docs/Status/Cxx20Papers.csv index 9a057be8ad0519c0f4aafb154cdec581d8328a00..5cd77be4d58def7d3a90a1031424f259a89a30e8 100644 --- a/libcxx/docs/Status/Cxx20Papers.csv +++ b/libcxx/docs/Status/Cxx20Papers.csv @@ -34,7 +34,7 @@ "`P0528R3 `__","The Curious Case of Padding Bits, Featuring Atomic Compare-and-Exchange","2018-06 (Rapperswil)","","","" "`P0542R5 `__","Support for contract based programming in C++","2018-06 (Rapperswil)","|Nothing To Do|","n/a","Pulled at the 2019-07 meeting in Cologne" "`P0556R3 `__","Integral power-of-2 operations","2018-06 (Rapperswil)","|Complete|","9.0","" -"`P0619R4 `__","Reviewing Deprecated Facilities of C++17 for C++20","2018-06 (Rapperswil)","|Partial|","","Only sections D.7, D.8, D.9, D.10, D.11, D.12, and D.13 are implemented. Section D.4 remains undone." +"`P0619R4 `__","Reviewing Deprecated Facilities of C++17 for C++20","2018-06 (Rapperswil)","|Complete|","20.0","Removed headers are still provided as an extension, but with deprecation warnings" "`P0646R1 `__","Improving the Return Value of Erase-Like Algorithms","2018-06 (Rapperswil)","|Complete|","10.0","" "`P0722R3 `__","Efficient sized delete for variable sized classes","2018-06 (Rapperswil)","|Complete|","9.0","" "`P0758R1 `__","Implicit conversion traits and utility functions","2018-06 (Rapperswil)","|Complete|","","" diff --git a/libcxx/include/CMakeLists.txt b/libcxx/include/CMakeLists.txt index e84a55e25f2fa427137efba1b071775915febc63..87eaf64b245017180b009600a72f153da095fb1d 100644 --- a/libcxx/include/CMakeLists.txt +++ b/libcxx/include/CMakeLists.txt @@ -923,6 +923,7 @@ set(files coroutine csetjmp csignal + cstdalign cstdarg cstdbool cstddef diff --git a/libcxx/include/__algorithm/comp.h b/libcxx/include/__algorithm/comp.h index 1f38f5d2d99b43cf48f452783cd28140c42eff39..ab3c598418828af7051aad7a00f173c313c45d93 100644 --- a/libcxx/include/__algorithm/comp.h +++ b/libcxx/include/__algorithm/comp.h @@ -42,6 +42,9 @@ struct __less { } }; +template +inline const bool __desugars_to_v<__less_tag, __less<>, _Tp, _Tp> = true; + template inline const bool __desugars_to_v<__totally_ordered_less_tag, __less<>, _Tp, _Tp> = is_integral<_Tp>::value; diff --git a/libcxx/include/__algorithm/copy_move_common.h b/libcxx/include/__algorithm/copy_move_common.h index 8a98451a8f9653ccec214dc76ab0c8f8de975d40..d76bf4903aaa9b489d285656eca5dbb157d9e298 100644 --- a/libcxx/include/__algorithm/copy_move_common.h +++ b/libcxx/include/__algorithm/copy_move_common.h @@ -13,6 +13,7 @@ #include <__algorithm/unwrap_iter.h> #include <__algorithm/unwrap_range.h> #include <__config> +#include <__cstddef/size_t.h> #include <__iterator/iterator_traits.h> #include <__memory/pointer_traits.h> #include <__string/constexpr_c_functions.h> @@ -24,7 +25,6 @@ #include <__type_traits/is_volatile.h> #include <__utility/move.h> #include <__utility/pair.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__algorithm/inplace_merge.h b/libcxx/include/__algorithm/inplace_merge.h index 62a8bc53e23f3c66572e15144ac605ee2fdf4d4d..ad3fe6a7a505d91cf43fe4f8612147e4b06f7f6e 100644 --- a/libcxx/include/__algorithm/inplace_merge.h +++ b/libcxx/include/__algorithm/inplace_merge.h @@ -18,6 +18,7 @@ #include <__algorithm/rotate.h> #include <__algorithm/upper_bound.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__functional/identity.h> #include <__iterator/advance.h> #include <__iterator/distance.h> diff --git a/libcxx/include/__algorithm/mismatch.h b/libcxx/include/__algorithm/mismatch.h index cb83347584b1a55ef2720dcf4aa9b19d43477228..556bd4216307d53e0704bc3116a84d1b33521a3d 100644 --- a/libcxx/include/__algorithm/mismatch.h +++ b/libcxx/include/__algorithm/mismatch.h @@ -15,6 +15,7 @@ #include <__algorithm/simd_utils.h> #include <__algorithm/unwrap_iter.h> #include <__config> +#include <__cstddef/size_t.h> #include <__functional/identity.h> #include <__iterator/aliasing_iterator.h> #include <__iterator/iterator_traits.h> @@ -27,7 +28,6 @@ #include <__utility/move.h> #include <__utility/pair.h> #include <__utility/unreachable.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__algorithm/ranges_minmax.h b/libcxx/include/__algorithm/ranges_minmax.h index 4f2b2bf26382da3ec016edd2283c462bb1018f18..5f2e5cb2a1eeab7b23f68b7b2d1deb4075418950 100644 --- a/libcxx/include/__algorithm/ranges_minmax.h +++ b/libcxx/include/__algorithm/ranges_minmax.h @@ -89,7 +89,7 @@ struct __minmax { // vectorize the code. if constexpr (contiguous_range<_Range> && is_integral_v<_ValueT> && __is_cheap_to_copy<_ValueT> & __is_identity<_Proj>::value && - __desugars_to_v<__totally_ordered_less_tag, _Comp, _ValueT, _ValueT>) { + __desugars_to_v<__less_tag, _Comp, _ValueT, _ValueT>) { minmax_result<_ValueT> __result = {__r[0], __r[0]}; for (auto __e : __r) { if (__e < __result.min) diff --git a/libcxx/include/__algorithm/shuffle.h b/libcxx/include/__algorithm/shuffle.h index c9c56ce8c2c0b1e81b047ff56ce8718cf9173992..7177fbb469ba7cc9039ac143739af3ba986e673b 100644 --- a/libcxx/include/__algorithm/shuffle.h +++ b/libcxx/include/__algorithm/shuffle.h @@ -11,12 +11,12 @@ #include <__algorithm/iterator_operations.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/iterator_traits.h> #include <__random/uniform_int_distribution.h> #include <__utility/forward.h> #include <__utility/move.h> #include <__utility/swap.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__algorithm/simd_utils.h b/libcxx/include/__algorithm/simd_utils.h index 56518dafa3193bf2bb5a9f3da450c6698d123eb4..4e3e4f2b9404e384f6ead78fa89ef598828c2ebc 100644 --- a/libcxx/include/__algorithm/simd_utils.h +++ b/libcxx/include/__algorithm/simd_utils.h @@ -14,10 +14,10 @@ #include <__bit/countl.h> #include <__bit/countr.h> #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/is_arithmetic.h> #include <__type_traits/is_same.h> #include <__utility/integer_sequence.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__algorithm/sort.h b/libcxx/include/__algorithm/sort.h index 0b2137dee2f77e39b5f318d35fef31364738a588..39868b8b6a30aefc58d2dafc8188dc4bea6c5cc7 100644 --- a/libcxx/include/__algorithm/sort.h +++ b/libcxx/include/__algorithm/sort.h @@ -27,11 +27,13 @@ #include <__functional/ranges_operations.h> #include <__iterator/iterator_traits.h> #include <__type_traits/conditional.h> +#include <__type_traits/desugars_to.h> #include <__type_traits/disjunction.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_arithmetic.h> #include <__type_traits/is_constant_evaluated.h> #include <__type_traits/is_same.h> +#include <__type_traits/is_trivially_copyable.h> #include <__type_traits/remove_cvref.h> #include <__utility/move.h> #include <__utility/pair.h> @@ -47,110 +49,11 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD -// stable, 2-3 compares, 0-2 swaps - -template -_LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 unsigned -__sort3(_ForwardIterator __x, _ForwardIterator __y, _ForwardIterator __z, _Compare __c) { - using _Ops = _IterOps<_AlgPolicy>; - - unsigned __r = 0; - if (!__c(*__y, *__x)) // if x <= y - { - if (!__c(*__z, *__y)) // if y <= z - return __r; // x <= y && y <= z - // x <= y && y > z - _Ops::iter_swap(__y, __z); // x <= z && y < z - __r = 1; - if (__c(*__y, *__x)) // if x > y - { - _Ops::iter_swap(__x, __y); // x < y && y <= z - __r = 2; - } - return __r; // x <= y && y < z - } - if (__c(*__z, *__y)) // x > y, if y > z - { - _Ops::iter_swap(__x, __z); // x < y && y < z - __r = 1; - return __r; - } - _Ops::iter_swap(__x, __y); // x > y && y <= z - __r = 1; // x < y && x <= z - if (__c(*__z, *__y)) // if y > z - { - _Ops::iter_swap(__y, __z); // x <= y && y < z - __r = 2; - } - return __r; -} // x <= y && y <= z - -// stable, 3-6 compares, 0-5 swaps - -template -_LIBCPP_HIDE_FROM_ABI void -__sort4(_ForwardIterator __x1, _ForwardIterator __x2, _ForwardIterator __x3, _ForwardIterator __x4, _Compare __c) { - using _Ops = _IterOps<_AlgPolicy>; - std::__sort3<_AlgPolicy, _Compare>(__x1, __x2, __x3, __c); - if (__c(*__x4, *__x3)) { - _Ops::iter_swap(__x3, __x4); - if (__c(*__x3, *__x2)) { - _Ops::iter_swap(__x2, __x3); - if (__c(*__x2, *__x1)) { - _Ops::iter_swap(__x1, __x2); - } - } - } -} - -// stable, 4-10 compares, 0-9 swaps - -template -_LIBCPP_HIDE_FROM_ABI void -__sort5(_ForwardIterator __x1, - _ForwardIterator __x2, - _ForwardIterator __x3, - _ForwardIterator __x4, - _ForwardIterator __x5, - _Comp __comp) { - using _Ops = _IterOps<_AlgPolicy>; - - std::__sort4<_AlgPolicy, _Comp>(__x1, __x2, __x3, __x4, __comp); - if (__comp(*__x5, *__x4)) { - _Ops::iter_swap(__x4, __x5); - if (__comp(*__x4, *__x3)) { - _Ops::iter_swap(__x3, __x4); - if (__comp(*__x3, *__x2)) { - _Ops::iter_swap(__x2, __x3); - if (__comp(*__x2, *__x1)) { - _Ops::iter_swap(__x1, __x2); - } - } - } - } -} - -// The comparator being simple is a prerequisite for using the branchless optimization. -template -struct __is_simple_comparator : false_type {}; -template <> -struct __is_simple_comparator<__less<>&> : true_type {}; -template -struct __is_simple_comparator&> : true_type {}; -template -struct __is_simple_comparator&> : true_type {}; -#if _LIBCPP_STD_VER >= 20 -template <> -struct __is_simple_comparator : true_type {}; -template <> -struct __is_simple_comparator : true_type {}; -#endif - template ::value_type> -using __use_branchless_sort = - integral_constant::value && sizeof(_Tp) <= sizeof(void*) && - is_arithmetic<_Tp>::value && __is_simple_comparator<_Compare>::value>; +inline const bool __use_branchless_sort = + __libcpp_is_contiguous_iterator<_Iter>::value && __is_cheap_to_copy<_Tp> && is_arithmetic<_Tp>::value && + (__desugars_to_v<__less_tag, __remove_cvref_t<_Compare>, _Tp, _Tp> || + __desugars_to_v<__greater_tag, __remove_cvref_t<_Compare>, _Tp, _Tp>); namespace __detail { @@ -161,59 +64,88 @@ enum { __block_size = sizeof(uint64_t) * 8 }; // Ensures that __c(*__x, *__y) is true by swapping *__x and *__y if necessary. template -inline _LIBCPP_HIDE_FROM_ABI void __cond_swap(_RandomAccessIterator __x, _RandomAccessIterator __y, _Compare __c) { +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool +__cond_swap(_RandomAccessIterator __x, _RandomAccessIterator __y, _Compare __c) { // Note: this function behaves correctly even with proxy iterators (because it relies on `value_type`). using value_type = typename iterator_traits<_RandomAccessIterator>::value_type; bool __r = __c(*__x, *__y); value_type __tmp = __r ? *__x : *__y; *__y = __r ? *__y : *__x; *__x = __tmp; + return !__r; } // Ensures that *__x, *__y and *__z are ordered according to the comparator __c, // under the assumption that *__y and *__z are already ordered. template -inline _LIBCPP_HIDE_FROM_ABI void +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool __partially_sorted_swap(_RandomAccessIterator __x, _RandomAccessIterator __y, _RandomAccessIterator __z, _Compare __c) { // Note: this function behaves correctly even with proxy iterators (because it relies on `value_type`). using value_type = typename iterator_traits<_RandomAccessIterator>::value_type; - bool __r = __c(*__z, *__x); - value_type __tmp = __r ? *__z : *__x; - *__z = __r ? *__x : *__z; - __r = __c(__tmp, *__y); - *__x = __r ? *__x : *__y; - *__y = __r ? *__y : __tmp; + bool __r1 = __c(*__z, *__x); + value_type __tmp = __r1 ? *__z : *__x; + *__z = __r1 ? *__x : *__z; + bool __r2 = __c(__tmp, *__y); + *__x = __r2 ? *__x : *__y; + *__y = __r2 ? *__y : __tmp; + return !__r1 || !__r2; } +// stable, 2-3 compares, 0-2 swaps + template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort3_maybe_branchless( - _RandomAccessIterator __x1, _RandomAccessIterator __x2, _RandomAccessIterator __x3, _Compare __c) { - std::__cond_swap<_Compare>(__x2, __x3, __c); - std::__partially_sorted_swap<_Compare>(__x1, __x2, __x3, __c); + __enable_if_t<__use_branchless_sort<_Compare, _RandomAccessIterator>, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool +__sort3(_RandomAccessIterator __x1, _RandomAccessIterator __x2, _RandomAccessIterator __x3, _Compare __c) { + bool __swapped1 = std::__cond_swap<_Compare>(__x2, __x3, __c); + bool __swapped2 = std::__partially_sorted_swap<_Compare>(__x1, __x2, __x3, __c); + return __swapped1 || __swapped2; } template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort3_maybe_branchless( - _RandomAccessIterator __x1, _RandomAccessIterator __x2, _RandomAccessIterator __x3, _Compare __c) { - std::__sort3<_AlgPolicy, _Compare>(__x1, __x2, __x3, __c); -} + __enable_if_t, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 bool +__sort3(_RandomAccessIterator __x, _RandomAccessIterator __y, _RandomAccessIterator __z, _Compare __c) { + using _Ops = _IterOps<_AlgPolicy>; + + if (!__c(*__y, *__x)) // if x <= y + { + if (!__c(*__z, *__y)) // if y <= z + return false; // x <= y && y <= z + // x <= y && y > z + _Ops::iter_swap(__y, __z); // x <= z && y < z + if (__c(*__y, *__x)) // if x > y + _Ops::iter_swap(__x, __y); // x < y && y <= z + return true; // x <= y && y < z + } + if (__c(*__z, *__y)) // x > y, if y > z + { + _Ops::iter_swap(__x, __z); // x < y && y < z + return true; + } + _Ops::iter_swap(__x, __y); // x > y && y <= z + // x < y && x <= z + if (__c(*__z, *__y)) // if y > z + _Ops::iter_swap(__y, __z); // x <= y && y < z + return true; +} // x <= y && y <= z + +// stable, 3-6 compares, 0-5 swaps template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort4_maybe_branchless( - _RandomAccessIterator __x1, - _RandomAccessIterator __x2, - _RandomAccessIterator __x3, - _RandomAccessIterator __x4, - _Compare __c) { + __enable_if_t<__use_branchless_sort<_Compare, _RandomAccessIterator>, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI void +__sort4(_RandomAccessIterator __x1, + _RandomAccessIterator __x2, + _RandomAccessIterator __x3, + _RandomAccessIterator __x4, + _Compare __c) { std::__cond_swap<_Compare>(__x1, __x3, __c); std::__cond_swap<_Compare>(__x2, __x4, __c); std::__cond_swap<_Compare>(__x1, __x2, __c); @@ -224,27 +156,39 @@ inline _LIBCPP_HIDE_FROM_ABI void __sort4_maybe_branchless( template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort4_maybe_branchless( - _RandomAccessIterator __x1, - _RandomAccessIterator __x2, - _RandomAccessIterator __x3, - _RandomAccessIterator __x4, - _Compare __c) { - std::__sort4<_AlgPolicy, _Compare>(__x1, __x2, __x3, __x4, __c); + __enable_if_t, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI void +__sort4(_RandomAccessIterator __x1, + _RandomAccessIterator __x2, + _RandomAccessIterator __x3, + _RandomAccessIterator __x4, + _Compare __c) { + using _Ops = _IterOps<_AlgPolicy>; + std::__sort3<_AlgPolicy, _Compare>(__x1, __x2, __x3, __c); + if (__c(*__x4, *__x3)) { + _Ops::iter_swap(__x3, __x4); + if (__c(*__x3, *__x2)) { + _Ops::iter_swap(__x2, __x3); + if (__c(*__x2, *__x1)) { + _Ops::iter_swap(__x1, __x2); + } + } + } } +// stable, 4-10 compares, 0-9 swaps + template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort5_maybe_branchless( - _RandomAccessIterator __x1, - _RandomAccessIterator __x2, - _RandomAccessIterator __x3, - _RandomAccessIterator __x4, - _RandomAccessIterator __x5, - _Compare __c) { + __enable_if_t<__use_branchless_sort<_Compare, _RandomAccessIterator>, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI void +__sort5(_RandomAccessIterator __x1, + _RandomAccessIterator __x2, + _RandomAccessIterator __x3, + _RandomAccessIterator __x4, + _RandomAccessIterator __x5, + _Compare __c) { std::__cond_swap<_Compare>(__x1, __x2, __c); std::__cond_swap<_Compare>(__x4, __x5, __c); std::__partially_sorted_swap<_Compare>(__x3, __x4, __x5, __c); @@ -256,16 +200,29 @@ inline _LIBCPP_HIDE_FROM_ABI void __sort5_maybe_branchless( template ::value, int> = 0> -inline _LIBCPP_HIDE_FROM_ABI void __sort5_maybe_branchless( - _RandomAccessIterator __x1, - _RandomAccessIterator __x2, - _RandomAccessIterator __x3, - _RandomAccessIterator __x4, - _RandomAccessIterator __x5, - _Compare __c) { - std::__sort5<_AlgPolicy, _Compare, _RandomAccessIterator>( - std::move(__x1), std::move(__x2), std::move(__x3), std::move(__x4), std::move(__x5), __c); + __enable_if_t, int> = 0> +inline _LIBCPP_HIDE_FROM_ABI void +__sort5(_RandomAccessIterator __x1, + _RandomAccessIterator __x2, + _RandomAccessIterator __x3, + _RandomAccessIterator __x4, + _RandomAccessIterator __x5, + _Compare __comp) { + using _Ops = _IterOps<_AlgPolicy>; + + std::__sort4<_AlgPolicy, _Compare>(__x1, __x2, __x3, __x4, __comp); + if (__comp(*__x5, *__x4)) { + _Ops::iter_swap(__x4, __x5); + if (__comp(*__x4, *__x3)) { + _Ops::iter_swap(__x3, __x4); + if (__comp(*__x3, *__x2)) { + _Ops::iter_swap(__x2, __x3); + if (__comp(*__x2, *__x1)) { + _Ops::iter_swap(__x1, __x2); + } + } + } + } } // Assumes size > 0 @@ -355,14 +312,14 @@ __insertion_sort_incomplete(_RandomAccessIterator __first, _RandomAccessIterator _Ops::iter_swap(__first, __last); return true; case 3: - std::__sort3_maybe_branchless<_AlgPolicy, _Comp>(__first, __first + difference_type(1), --__last, __comp); + std::__sort3<_AlgPolicy, _Comp>(__first, __first + difference_type(1), --__last, __comp); return true; case 4: - std::__sort4_maybe_branchless<_AlgPolicy, _Comp>( + std::__sort4<_AlgPolicy, _Comp>( __first, __first + difference_type(1), __first + difference_type(2), --__last, __comp); return true; case 5: - std::__sort5_maybe_branchless<_AlgPolicy, _Comp>( + std::__sort5<_AlgPolicy, _Comp>( __first, __first + difference_type(1), __first + difference_type(2), @@ -373,7 +330,7 @@ __insertion_sort_incomplete(_RandomAccessIterator __first, _RandomAccessIterator } typedef typename iterator_traits<_RandomAccessIterator>::value_type value_type; _RandomAccessIterator __j = __first + difference_type(2); - std::__sort3_maybe_branchless<_AlgPolicy, _Comp>(__first, __first + difference_type(1), __j, __comp); + std::__sort3<_AlgPolicy, _Comp>(__first, __first + difference_type(1), __j, __comp); const unsigned __limit = 8; unsigned __count = 0; for (_RandomAccessIterator __i = __j + difference_type(1); __i != __last; ++__i) { @@ -780,14 +737,14 @@ void __introsort(_RandomAccessIterator __first, _Ops::iter_swap(__first, __last); return; case 3: - std::__sort3_maybe_branchless<_AlgPolicy, _Compare>(__first, __first + difference_type(1), --__last, __comp); + std::__sort3<_AlgPolicy, _Compare>(__first, __first + difference_type(1), --__last, __comp); return; case 4: - std::__sort4_maybe_branchless<_AlgPolicy, _Compare>( + std::__sort4<_AlgPolicy, _Compare>( __first, __first + difference_type(1), __first + difference_type(2), --__last, __comp); return; case 5: - std::__sort5_maybe_branchless<_AlgPolicy, _Compare>( + std::__sort5<_AlgPolicy, _Compare>( __first, __first + difference_type(1), __first + difference_type(2), @@ -928,10 +885,8 @@ __sort_dispatch(_RandomAccessIterator __first, _RandomAccessIterator __last, _Co // Only use bitset partitioning for arithmetic types. We should also check // that the default comparator is in use so that we are sure that there are no // branches in the comparator. - std::__introsort<_AlgPolicy, - _Comp&, - _RandomAccessIterator, - __use_branchless_sort<_Comp, _RandomAccessIterator>::value>(__first, __last, __comp, __depth_limit); + std::__introsort<_AlgPolicy, _Comp&, _RandomAccessIterator, __use_branchless_sort<_Comp, _RandomAccessIterator> >( + __first, __last, __comp, __depth_limit); } template diff --git a/libcxx/include/__algorithm/stable_partition.h b/libcxx/include/__algorithm/stable_partition.h index 5df5e8eaf689ba3085457a847878138ebba289fd..0438f589a39d7a61326dab2ab23742aad2189911 100644 --- a/libcxx/include/__algorithm/stable_partition.h +++ b/libcxx/include/__algorithm/stable_partition.h @@ -12,6 +12,7 @@ #include <__algorithm/iterator_operations.h> #include <__algorithm/rotate.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/advance.h> #include <__iterator/distance.h> #include <__iterator/iterator_traits.h> diff --git a/libcxx/include/__algorithm/stable_sort.h b/libcxx/include/__algorithm/stable_sort.h index ec556aad82e8d806963de3d5fe4ae79d48e9cc87..43f591ac02b01df614a9db5ab02a337732b51e03 100644 --- a/libcxx/include/__algorithm/stable_sort.h +++ b/libcxx/include/__algorithm/stable_sort.h @@ -15,6 +15,7 @@ #include <__algorithm/iterator_operations.h> #include <__algorithm/sort.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__debug_utils/strict_weak_ordering_check.h> #include <__iterator/iterator_traits.h> #include <__memory/destruct_n.h> diff --git a/libcxx/include/__atomic/aliases.h b/libcxx/include/__atomic/aliases.h index afc64eaaa69e7bff59b26886031cd3f783d34313..3c84747bebb8161e75e940fd687ba33e179831ef 100644 --- a/libcxx/include/__atomic/aliases.h +++ b/libcxx/include/__atomic/aliases.h @@ -14,9 +14,10 @@ #include <__atomic/contention_t.h> #include <__atomic/is_always_lock_free.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> +#include <__cstddef/size_t.h> #include <__type_traits/conditional.h> #include <__type_traits/make_unsigned.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__atomic/atomic.h b/libcxx/include/__atomic/atomic.h index af6d12b5e4ce913988d3765ad7fcdd3491ec1ea0..113475cb1f0079fc3d406667895d52b57fd27675 100644 --- a/libcxx/include/__atomic/atomic.h +++ b/libcxx/include/__atomic/atomic.h @@ -14,6 +14,7 @@ #include <__atomic/cxx_atomic_impl.h> #include <__atomic/memory_order.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__functional/operations.h> #include <__memory/addressof.h> #include <__type_traits/enable_if.h> @@ -25,7 +26,6 @@ #include <__type_traits/remove_pointer.h> #include <__type_traits/remove_volatile.h> #include <__utility/forward.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__atomic/atomic_ref.h b/libcxx/include/__atomic/atomic_ref.h index 465cd9a77ea792cafb130687e20324d58fd900d8..eef15983b983318687c91fb0cf25e2837bb85fb3 100644 --- a/libcxx/include/__atomic/atomic_ref.h +++ b/libcxx/include/__atomic/atomic_ref.h @@ -25,10 +25,11 @@ #include <__concepts/arithmetic.h> #include <__concepts/same_as.h> #include <__config> +#include <__cstddef/byte.h> +#include <__cstddef/ptrdiff_t.h> #include <__memory/addressof.h> #include <__type_traits/has_unique_object_representation.h> #include <__type_traits/is_trivially_copyable.h> -#include #include #include diff --git a/libcxx/include/__atomic/cxx_atomic_impl.h b/libcxx/include/__atomic/cxx_atomic_impl.h index 18e88aa97bec755dc3396bd84eff693b7954122f..86a57d1d5d8ff23503def6218c10699d71426afe 100644 --- a/libcxx/include/__atomic/cxx_atomic_impl.h +++ b/libcxx/include/__atomic/cxx_atomic_impl.h @@ -12,11 +12,12 @@ #include <__atomic/memory_order.h> #include <__atomic/to_gcc_order.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__memory/addressof.h> +#include <__type_traits/enable_if.h> #include <__type_traits/is_assignable.h> #include <__type_traits/is_trivially_copyable.h> #include <__type_traits/remove_const.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__charconv/from_chars_floating_point.h b/libcxx/include/__charconv/from_chars_floating_point.h index 5cd3fc4a41ea1db295eb92267020e67f06c6687f..811e518a81db70c92bb581c56e85a84ed0aa6201 100644 --- a/libcxx/include/__charconv/from_chars_floating_point.h +++ b/libcxx/include/__charconv/from_chars_floating_point.h @@ -14,8 +14,8 @@ #include <__charconv/chars_format.h> #include <__charconv/from_chars_result.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__system_error/errc.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__charconv/to_chars_integral.h b/libcxx/include/__charconv/to_chars_integral.h index fd92be4b4ce91e2ffdce96d8951416c25295bc93..710299df9b4da8d8ac5788f4042155ba19a258b2 100644 --- a/libcxx/include/__charconv/to_chars_integral.h +++ b/libcxx/include/__charconv/to_chars_integral.h @@ -18,6 +18,7 @@ #include <__charconv/to_chars_result.h> #include <__charconv/traits.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__system_error/errc.h> #include <__type_traits/enable_if.h> #include <__type_traits/integral_constant.h> @@ -26,7 +27,6 @@ #include <__type_traits/make_32_64_or_128_bit.h> #include <__type_traits/make_unsigned.h> #include <__utility/unreachable.h> -#include #include #include diff --git a/libcxx/include/__compare/common_comparison_category.h b/libcxx/include/__compare/common_comparison_category.h index 7aeb3da03a4f4a9975fa022a90ebcf63c2dc5a05..215922abad6b0eac00e143c88d0f6dfc20afe916 100644 --- a/libcxx/include/__compare/common_comparison_category.h +++ b/libcxx/include/__compare/common_comparison_category.h @@ -11,8 +11,8 @@ #include <__compare/ordering.h> #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/is_same.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__concepts/swappable.h b/libcxx/include/__concepts/swappable.h index d339488a087a5c4157f9b338556102bde0207c27..985c733021a0d78c0b0bb347c665e6858290a748 100644 --- a/libcxx/include/__concepts/swappable.h +++ b/libcxx/include/__concepts/swappable.h @@ -14,6 +14,7 @@ #include <__concepts/common_reference_with.h> #include <__concepts/constructible.h> #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/extent.h> #include <__type_traits/is_nothrow_assignable.h> #include <__type_traits/is_nothrow_constructible.h> @@ -22,7 +23,6 @@ #include <__utility/forward.h> #include <__utility/move.h> #include <__utility/swap.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__config b/libcxx/include/__config index fc09a97274d7c781f20b168206103ab48ce3420b..1cf80a46686ab913f9b8d8f49545a38fff1b87f6 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -39,16 +39,9 @@ // HARDENING { -// This is for backward compatibility -- make enabling `_LIBCPP_ENABLE_ASSERTIONS` (which predates hardening modes) -// equivalent to setting the extensive mode. This is deprecated and will be removed in LLVM 20. +// TODO: Remove in LLVM 21. We're making this an error to catch folks who might not have migrated. # ifdef _LIBCPP_ENABLE_ASSERTIONS -# warning "_LIBCPP_ENABLE_ASSERTIONS is deprecated, please use _LIBCPP_HARDENING_MODE instead" -# if _LIBCPP_ENABLE_ASSERTIONS != 0 && _LIBCPP_ENABLE_ASSERTIONS != 1 -# error "_LIBCPP_ENABLE_ASSERTIONS must be set to 0 or 1" -# endif -# if _LIBCPP_ENABLE_ASSERTIONS -# define _LIBCPP_HARDENING_MODE _LIBCPP_HARDENING_MODE_EXTENSIVE -# endif +# error "_LIBCPP_ENABLE_ASSERTIONS has been removed, please use _LIBCPP_HARDENING_MODE instead" # endif // The library provides the macro `_LIBCPP_HARDENING_MODE` which can be set to one of the following values: diff --git a/libcxx/include/__coroutine/coroutine_handle.h b/libcxx/include/__coroutine/coroutine_handle.h index 4557a6643c2393b844b42c9a1060349b9a2cffc2..e2cde20498d8434149d5bf57c07da10f599b4674 100644 --- a/libcxx/include/__coroutine/coroutine_handle.h +++ b/libcxx/include/__coroutine/coroutine_handle.h @@ -11,11 +11,12 @@ #include <__assert> #include <__config> +#include <__cstddef/nullptr_t.h> +#include <__cstddef/size_t.h> #include <__functional/hash.h> #include <__memory/addressof.h> #include <__type_traits/remove_cv.h> #include -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__exception/exception_ptr.h b/libcxx/include/__exception/exception_ptr.h index 2cb250dfd42da7a7830b96388b3c1555f6f6748a..32c56fc5cc1263bf64e70b11a996151a5ac2ec3b 100644 --- a/libcxx/include/__exception/exception_ptr.h +++ b/libcxx/include/__exception/exception_ptr.h @@ -14,7 +14,6 @@ #include <__memory/addressof.h> #include <__memory/construct_at.h> #include <__type_traits/decay.h> -#include #include #include #include diff --git a/libcxx/include/__exception/nested_exception.h b/libcxx/include/__exception/nested_exception.h index cc20b038c871ba85f289e3c27f93d1c3483ae553..d560b6bbc35a7b83f36a80e572c5d8900e471998 100644 --- a/libcxx/include/__exception/nested_exception.h +++ b/libcxx/include/__exception/nested_exception.h @@ -22,7 +22,6 @@ #include <__type_traits/is_final.h> #include <__type_traits/is_polymorphic.h> #include <__utility/forward.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__exception/operations.h b/libcxx/include/__exception/operations.h index c8744eb297a4e82de0b8b4e3229a08eece81172c..15520c558a0b4ee065645db422d5159fa416c83f 100644 --- a/libcxx/include/__exception/operations.h +++ b/libcxx/include/__exception/operations.h @@ -10,7 +10,6 @@ #define _LIBCPP___EXCEPTION_OPERATIONS_H #include <__config> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__filesystem/directory_iterator.h b/libcxx/include/__filesystem/directory_iterator.h index e0246d8001e1952bef0d20835aa9c7032194ffd2..621e9bf9258efb023c4505536ddd89a10d9f379a 100644 --- a/libcxx/include/__filesystem/directory_iterator.h +++ b/libcxx/include/__filesystem/directory_iterator.h @@ -22,7 +22,6 @@ #include <__ranges/enable_view.h> #include <__system_error/error_code.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__filesystem/path.h b/libcxx/include/__filesystem/path.h index 2eb60810af02b5a7c35ff2642afac622a8063fe3..88c800fdf86d089138bf9f618d66ce82092b33c5 100644 --- a/libcxx/include/__filesystem/path.h +++ b/libcxx/include/__filesystem/path.h @@ -22,7 +22,6 @@ #include <__type_traits/remove_const.h> #include <__type_traits/remove_pointer.h> #include <__utility/move.h> -#include #include #include diff --git a/libcxx/include/__filesystem/path_iterator.h b/libcxx/include/__filesystem/path_iterator.h index f4d486d86cf380911af385b0f28459862acb6ae2..e0f601662d4620e5da473d14269c33a8f8ba9051 100644 --- a/libcxx/include/__filesystem/path_iterator.h +++ b/libcxx/include/__filesystem/path_iterator.h @@ -14,9 +14,6 @@ #include <__config> #include <__filesystem/path.h> #include <__iterator/iterator_traits.h> -#include -#include -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__filesystem/recursive_directory_iterator.h b/libcxx/include/__filesystem/recursive_directory_iterator.h index caa1396eb301fc96427f3e1be1febfc506888f78..1be92a8bd5f49256dd9de69aff7aa268e97bc2bd 100644 --- a/libcxx/include/__filesystem/recursive_directory_iterator.h +++ b/libcxx/include/__filesystem/recursive_directory_iterator.h @@ -21,7 +21,6 @@ #include <__ranges/enable_view.h> #include <__system_error/error_code.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__flat_map/flat_map.h b/libcxx/include/__flat_map/flat_map.h index 9ca32d5295bd27d093ec441d487758a0dc8b4b69..5c14c0ac693b08a4845ea7f5d089d1547ac6d784 100644 --- a/libcxx/include/__flat_map/flat_map.h +++ b/libcxx/include/__flat_map/flat_map.h @@ -23,6 +23,7 @@ #include <__concepts/convertible_to.h> #include <__concepts/swappable.h> #include <__config> +#include <__cstddef/byte.h> #include <__flat_map/sorted_unique.h> #include <__functional/invoke.h> #include <__functional/is_transparent.h> diff --git a/libcxx/include/__format/buffer.h b/libcxx/include/__format/buffer.h index ce9ac0c81e315a36c6de12e831ec1f36852ee07c..618b8ef02564322fdfd05aee9db43f29da84823c 100644 --- a/libcxx/include/__format/buffer.h +++ b/libcxx/include/__format/buffer.h @@ -37,7 +37,6 @@ #include <__type_traits/conditional.h> #include <__utility/exception_guard.h> #include <__utility/move.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__format/escaped_output_table.h b/libcxx/include/__format/escaped_output_table.h index bdf86cb6f99ccb338d70e865402d621d04d22fa3..7a0b35239861e08be0d2e4b36bf46cc711eec42b 100644 --- a/libcxx/include/__format/escaped_output_table.h +++ b/libcxx/include/__format/escaped_output_table.h @@ -63,7 +63,7 @@ #include <__algorithm/ranges_upper_bound.h> #include <__config> -#include +#include <__cstddef/ptrdiff_t.h> #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__format/extended_grapheme_cluster_table.h b/libcxx/include/__format/extended_grapheme_cluster_table.h index 7dbc239f5f5cd681c88d74841a80b499b1d4506d..7653a9e03b815dc9aedfa16e8b11922e6d84c787 100644 --- a/libcxx/include/__format/extended_grapheme_cluster_table.h +++ b/libcxx/include/__format/extended_grapheme_cluster_table.h @@ -63,8 +63,8 @@ #include <__algorithm/ranges_upper_bound.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/access.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__format/format_arg.h b/libcxx/include/__format/format_arg.h index 3f39d2aec81f7567cef0b3ca50331c1aba926bf8..a973ccd43c42071448427b7a28de89e139c270ef 100644 --- a/libcxx/include/__format/format_arg.h +++ b/libcxx/include/__format/format_arg.h @@ -13,6 +13,7 @@ #include <__assert> #include <__concepts/arithmetic.h> #include <__config> +#include <__cstddef/size_t.h> #include <__format/concepts.h> #include <__format/format_parse_context.h> #include <__functional/invoke.h> diff --git a/libcxx/include/__format/format_args.h b/libcxx/include/__format/format_args.h index e19b4458e41a5bd9f500ae839b664d7bb260acb2..b98663c06ea4d89b22e66ba3eb44e34c272214b8 100644 --- a/libcxx/include/__format/format_args.h +++ b/libcxx/include/__format/format_args.h @@ -11,10 +11,10 @@ #define _LIBCPP___FORMAT_FORMAT_ARGS_H #include <__config> +#include <__cstddef/size_t.h> #include <__format/format_arg.h> #include <__format/format_arg_store.h> #include <__fwd/format.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__format/format_context.h b/libcxx/include/__format/format_context.h index 019a71011a71405d633e9eec341ede28226c4da2..ecbf62770cdeadcba98daa70bdb5aa52019ac805 100644 --- a/libcxx/include/__format/format_context.h +++ b/libcxx/include/__format/format_context.h @@ -23,7 +23,6 @@ #include <__memory/addressof.h> #include <__utility/move.h> #include <__variant/monostate.h> -#include #ifndef _LIBCPP_HAS_NO_LOCALIZATION # include <__locale> diff --git a/libcxx/include/__format/format_string.h b/libcxx/include/__format/format_string.h index a499afee8874a561013df622d6648d6e61ccf394..5db5973dd5889ff7408e59c47773d1636271b2cc 100644 --- a/libcxx/include/__format/format_string.h +++ b/libcxx/include/__format/format_string.h @@ -12,10 +12,10 @@ #include <__assert> #include <__config> +#include <__cstddef/size_t.h> #include <__format/format_error.h> #include <__iterator/concepts.h> #include <__iterator/iterator_traits.h> // iter_value_t -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__format/formatter_floating_point.h b/libcxx/include/__format/formatter_floating_point.h index fc95dd3f22bbe7ae238a68398196463159acedbb..9ffe20a1a72a0678053a7ddfcac6ffd92cddd139 100644 --- a/libcxx/include/__format/formatter_floating_point.h +++ b/libcxx/include/__format/formatter_floating_point.h @@ -36,7 +36,6 @@ #include <__utility/move.h> #include <__utility/unreachable.h> #include -#include #ifndef _LIBCPP_HAS_NO_LOCALIZATION # include <__locale> diff --git a/libcxx/include/__format/formatter_output.h b/libcxx/include/__format/formatter_output.h index 34c4c87313a450b62463dbd9deb5845acbd35369..457f5f53b2dc55751d56ceac229929be3531b862 100644 --- a/libcxx/include/__format/formatter_output.h +++ b/libcxx/include/__format/formatter_output.h @@ -16,6 +16,8 @@ #include <__bit/countl.h> #include <__concepts/same_as.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> +#include <__cstddef/size_t.h> #include <__format/buffer.h> #include <__format/concepts.h> #include <__format/formatter.h> @@ -28,7 +30,6 @@ #include <__memory/pointer_traits.h> #include <__utility/move.h> #include <__utility/unreachable.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__format/formatter_pointer.h b/libcxx/include/__format/formatter_pointer.h index 6e0fa9a1b4f196bed41772e185271ff3d44b19cd..4ef48c168d0d8b8e8c1cafc6e51f78da11010474 100644 --- a/libcxx/include/__format/formatter_pointer.h +++ b/libcxx/include/__format/formatter_pointer.h @@ -11,13 +11,13 @@ #define _LIBCPP___FORMAT_FORMATTER_POINTER_H #include <__config> +#include <__cstddef/nullptr_t.h> #include <__format/concepts.h> #include <__format/format_parse_context.h> #include <__format/formatter.h> #include <__format/formatter_integral.h> #include <__format/formatter_output.h> #include <__format/parser_std_format_spec.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__format/indic_conjunct_break_table.h b/libcxx/include/__format/indic_conjunct_break_table.h index 39dd45da771fc2ee3a25e8e6ada9563d64b229a7..df6cfe6a02f3485a8f67c826650c1378ab8b4a9a 100644 --- a/libcxx/include/__format/indic_conjunct_break_table.h +++ b/libcxx/include/__format/indic_conjunct_break_table.h @@ -63,8 +63,8 @@ #include <__algorithm/ranges_upper_bound.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/access.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__format/width_estimation_table.h b/libcxx/include/__format/width_estimation_table.h index 23a08746b910314c679a439923ee7c4423e81241..5b4b3950c6a1d0c61dc226c01f35087c3a4904b8 100644 --- a/libcxx/include/__format/width_estimation_table.h +++ b/libcxx/include/__format/width_estimation_table.h @@ -63,7 +63,7 @@ #include <__algorithm/ranges_upper_bound.h> #include <__config> -#include +#include <__cstddef/ptrdiff_t.h> #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__functional/bind.h b/libcxx/include/__functional/bind.h index 4251ef74ab7bd4934b9c0dd2a687379016a60c62..f82c1517249b16b4b99963a0a13b9da8f4390abf 100644 --- a/libcxx/include/__functional/bind.h +++ b/libcxx/include/__functional/bind.h @@ -17,7 +17,6 @@ #include <__type_traits/invoke.h> #include <__type_traits/is_reference_wrapper.h> #include <__type_traits/is_void.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__functional/hash.h b/libcxx/include/__functional/hash.h index 8abec99f7290571e2295b5994de726f227ed4661..f7b89f759b5f5c5f4882ef69cddd83f2e55040ba 100644 --- a/libcxx/include/__functional/hash.h +++ b/libcxx/include/__functional/hash.h @@ -20,7 +20,6 @@ #include <__type_traits/underlying_type.h> #include <__utility/pair.h> #include <__utility/swap.h> -#include #include #include diff --git a/libcxx/include/__functional/operations.h b/libcxx/include/__functional/operations.h index 6022bd679ed3e3cb9b970b8d9aa45b5061bfac8f..67d9da289aead3fe8e0062b39aa7b8007c290319 100644 --- a/libcxx/include/__functional/operations.h +++ b/libcxx/include/__functional/operations.h @@ -362,6 +362,9 @@ struct _LIBCPP_TEMPLATE_VIS less : __binary_function<_Tp, _Tp, bool> { }; _LIBCPP_CTAD_SUPPORTED_FOR_TYPE(less); +template +inline const bool __desugars_to_v<__less_tag, less<_Tp>, _Tp, _Tp> = true; + template inline const bool __desugars_to_v<__totally_ordered_less_tag, less<_Tp>, _Tp, _Tp> = is_integral<_Tp>::value; @@ -377,6 +380,9 @@ struct _LIBCPP_TEMPLATE_VIS less { typedef void is_transparent; }; +template +inline const bool __desugars_to_v<__less_tag, less<>, _Tp, _Up> = true; + template inline const bool __desugars_to_v<__totally_ordered_less_tag, less<>, _Tp, _Tp> = is_integral<_Tp>::value; #endif @@ -446,6 +452,9 @@ struct _LIBCPP_TEMPLATE_VIS greater : __binary_function<_Tp, _Tp, bool> { }; _LIBCPP_CTAD_SUPPORTED_FOR_TYPE(greater); +template +inline const bool __desugars_to_v<__greater_tag, greater<_Tp>, _Tp, _Tp> = true; + #if _LIBCPP_STD_VER >= 14 template <> struct _LIBCPP_TEMPLATE_VIS greater { @@ -457,6 +466,9 @@ struct _LIBCPP_TEMPLATE_VIS greater { } typedef void is_transparent; }; + +template +inline const bool __desugars_to_v<__greater_tag, greater<>, _Tp, _Up> = true; #endif // Logical operations diff --git a/libcxx/include/__functional/ranges_operations.h b/libcxx/include/__functional/ranges_operations.h index f023d765a6c8ab2ca60cd7a0f09a9f5570254182..df95843e7c9af61edc3321d144db57b838c5cd70 100644 --- a/libcxx/include/__functional/ranges_operations.h +++ b/libcxx/include/__functional/ranges_operations.h @@ -102,6 +102,12 @@ inline const bool __desugars_to_v<__equal_tag, ranges::equal_to, _Tp, _Up> = tru template inline const bool __desugars_to_v<__totally_ordered_less_tag, ranges::less, _Tp, _Up> = true; +template +inline const bool __desugars_to_v<__less_tag, ranges::less, _Tp, _Up> = true; + +template +inline const bool __desugars_to_v<__greater_tag, ranges::greater, _Tp, _Up> = true; + #endif // _LIBCPP_STD_VER >= 20 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__hash_table b/libcxx/include/__hash_table index 560e873adc3846b62cd6bc3036606aaddec2642b..8e4cb3c914dc4347c6224297991add2c7d62efa6 100644 --- a/libcxx/include/__hash_table +++ b/libcxx/include/__hash_table @@ -15,6 +15,7 @@ #include <__assert> #include <__bit/countl.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__functional/hash.h> #include <__iterator/iterator_traits.h> #include <__math/rounding_functions.h> diff --git a/libcxx/include/__iterator/access.h b/libcxx/include/__iterator/access.h index acc4f60bf697eac924b018469f60d6e51b69aaf0..d42855f925487346d71f154e271777fc8aa0865a 100644 --- a/libcxx/include/__iterator/access.h +++ b/libcxx/include/__iterator/access.h @@ -11,7 +11,7 @@ #define _LIBCPP___ITERATOR_ACCESS_H #include <__config> -#include +#include <__cstddef/size_t.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/aliasing_iterator.h b/libcxx/include/__iterator/aliasing_iterator.h index 94ba577078b5e8c9ca7c1ffb304f0279896ea055..aeb5b4a88ec37514ccca9d6f8bfcb3de4ea07d38 100644 --- a/libcxx/include/__iterator/aliasing_iterator.h +++ b/libcxx/include/__iterator/aliasing_iterator.h @@ -10,10 +10,10 @@ #define _LIBCPP___ITERATOR_ALIASING_ITERATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/iterator_traits.h> #include <__memory/pointer_traits.h> #include <__type_traits/is_trivial.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/back_insert_iterator.h b/libcxx/include/__iterator/back_insert_iterator.h index 6d3dd4b12966fe7547fcbfd73173b60c6569a20b..9a594875338854a326fd385d280199490da4d9e3 100644 --- a/libcxx/include/__iterator/back_insert_iterator.h +++ b/libcxx/include/__iterator/back_insert_iterator.h @@ -11,11 +11,11 @@ #define _LIBCPP___ITERATOR_BACK_INSERT_ITERATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> #include <__memory/addressof.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/data.h b/libcxx/include/__iterator/data.h index b7c1603652b0e6c49a7d35cfa4a30020f2d1d791..5f2624c2b819ed08a70e0ddae61ed8b64cf56958 100644 --- a/libcxx/include/__iterator/data.h +++ b/libcxx/include/__iterator/data.h @@ -11,7 +11,6 @@ #define _LIBCPP___ITERATOR_DATA_H #include <__config> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__iterator/empty.h b/libcxx/include/__iterator/empty.h index 773f2776955b2a16707e1805e40967e35757cbef..f2c653bcb329bab56ca2506a879a68d1304b54a6 100644 --- a/libcxx/include/__iterator/empty.h +++ b/libcxx/include/__iterator/empty.h @@ -11,7 +11,6 @@ #define _LIBCPP___ITERATOR_EMPTY_H #include <__config> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__iterator/front_insert_iterator.h b/libcxx/include/__iterator/front_insert_iterator.h index 7f2c54ec87442e20004b4d9e2f2066e81dd3aa9b..80819cd22ae6c1852805edd098bf86ea2327874a 100644 --- a/libcxx/include/__iterator/front_insert_iterator.h +++ b/libcxx/include/__iterator/front_insert_iterator.h @@ -11,11 +11,11 @@ #define _LIBCPP___ITERATOR_FRONT_INSERT_ITERATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> #include <__memory/addressof.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/incrementable_traits.h b/libcxx/include/__iterator/incrementable_traits.h index a228b228f6e552046314d7dceeddf7d196327137..37c8daddf8a861c26cca5d12b8679fb15b3285c0 100644 --- a/libcxx/include/__iterator/incrementable_traits.h +++ b/libcxx/include/__iterator/incrementable_traits.h @@ -12,13 +12,13 @@ #include <__concepts/arithmetic.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__type_traits/conditional.h> #include <__type_traits/is_object.h> #include <__type_traits/is_primary_template.h> #include <__type_traits/make_signed.h> #include <__type_traits/remove_cvref.h> #include <__utility/declval.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/insert_iterator.h b/libcxx/include/__iterator/insert_iterator.h index 8b7574dc9ec0afdfafb59854360d74a743631fc3..b3311042014f8fe70c0405a70f15f5f0a1059fb6 100644 --- a/libcxx/include/__iterator/insert_iterator.h +++ b/libcxx/include/__iterator/insert_iterator.h @@ -11,12 +11,12 @@ #define _LIBCPP___ITERATOR_INSERT_ITERATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> #include <__memory/addressof.h> #include <__ranges/access.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/istream_iterator.h b/libcxx/include/__iterator/istream_iterator.h index 58c9ac6d4ccceab42066051f90192e20dcb5640b..a6c74d00178d295b8aed11190f1f0090f0326c18 100644 --- a/libcxx/include/__iterator/istream_iterator.h +++ b/libcxx/include/__iterator/istream_iterator.h @@ -11,13 +11,13 @@ #define _LIBCPP___ITERATOR_ISTREAM_ITERATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__fwd/istream.h> #include <__fwd/string.h> #include <__iterator/default_sentinel.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> #include <__memory/addressof.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/istreambuf_iterator.h b/libcxx/include/__iterator/istreambuf_iterator.h index 51c4ecff351f52b8009fa0c0519c072af1487b1e..162873b9559ec63bcdadf975275d9dc47d8b876b 100644 --- a/libcxx/include/__iterator/istreambuf_iterator.h +++ b/libcxx/include/__iterator/istreambuf_iterator.h @@ -16,6 +16,8 @@ #include <__iterator/default_sentinel.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> +#include <__string/char_traits.h> +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/iterator.h b/libcxx/include/__iterator/iterator.h index ba9308f3c2243013da46ccef745c2082dc95054a..1591655313ddec05b8c1eeccf044f933b9e30d9c 100644 --- a/libcxx/include/__iterator/iterator.h +++ b/libcxx/include/__iterator/iterator.h @@ -11,7 +11,7 @@ #define _LIBCPP___ITERATOR_ITERATOR_H #include <__config> -#include +#include <__cstddef/ptrdiff_t.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/iterator_traits.h b/libcxx/include/__iterator/iterator_traits.h index 4d9ad480cc4a298141a85e90b97bc9e93cfe6475..eb6ba8b62fb30f8f4674db8c80a8392936853ebd 100644 --- a/libcxx/include/__iterator/iterator_traits.h +++ b/libcxx/include/__iterator/iterator_traits.h @@ -18,6 +18,7 @@ #include <__concepts/same_as.h> #include <__concepts/totally_ordered.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__fwd/pair.h> #include <__iterator/incrementable_traits.h> #include <__iterator/readable_traits.h> @@ -36,7 +37,6 @@ #include <__type_traits/remove_cvref.h> #include <__type_traits/void_t.h> #include <__utility/declval.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/ostream_iterator.h b/libcxx/include/__iterator/ostream_iterator.h index 05697e62d9dcb9751e425af65d676d1817cb121d..93ecc03010d07ce24ca96f3a2e8ca8d4deceb3f6 100644 --- a/libcxx/include/__iterator/ostream_iterator.h +++ b/libcxx/include/__iterator/ostream_iterator.h @@ -11,12 +11,12 @@ #define _LIBCPP___ITERATOR_OSTREAM_ITERATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__fwd/ostream.h> #include <__fwd/string.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> #include <__memory/addressof.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/ostreambuf_iterator.h b/libcxx/include/__iterator/ostreambuf_iterator.h index 401b6f3f2360324e34beadcd9daed9925ec99dc8..621ffd4f988c31927c3717895e369a396cc5dc66 100644 --- a/libcxx/include/__iterator/ostreambuf_iterator.h +++ b/libcxx/include/__iterator/ostreambuf_iterator.h @@ -11,12 +11,12 @@ #define _LIBCPP___ITERATOR_OSTREAMBUF_ITERATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__fwd/ios.h> #include <__fwd/ostream.h> #include <__fwd/streambuf.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> -#include #include // for forward declaration of ostreambuf_iterator #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__iterator/reverse_access.h b/libcxx/include/__iterator/reverse_access.h index 54d7270b04a53784a2a791fc97f3bdbe86e0ada0..f6e60c3fb75b3484a9ec2e8aa69f6a1c368568ed 100644 --- a/libcxx/include/__iterator/reverse_access.h +++ b/libcxx/include/__iterator/reverse_access.h @@ -12,7 +12,6 @@ #include <__config> #include <__iterator/reverse_iterator.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__iterator/segmented_iterator.h b/libcxx/include/__iterator/segmented_iterator.h index f3cd1e5fa1f5da2e03800d96e9e17fdfdef50811..8cb54a35a7f5eacb5c6dc781e6843b92377167db 100644 --- a/libcxx/include/__iterator/segmented_iterator.h +++ b/libcxx/include/__iterator/segmented_iterator.h @@ -41,8 +41,8 @@ // Returns the iterator composed of the segment iterator and local iterator. #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/integral_constant.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/size.h b/libcxx/include/__iterator/size.h index 876e6963f77d91eda9a6ace89372af3270062d18..84e2e3b21f1d5da3776eb45c9e112fa5a3c3a1c1 100644 --- a/libcxx/include/__iterator/size.h +++ b/libcxx/include/__iterator/size.h @@ -11,9 +11,10 @@ #define _LIBCPP___ITERATOR_SIZE_H #include <__config> +#include <__cstddef/ptrdiff_t.h> +#include <__cstddef/size_t.h> #include <__type_traits/common_type.h> #include <__type_traits/make_signed.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__iterator/wrap_iter.h b/libcxx/include/__iterator/wrap_iter.h index 549d8ff2dbd7db1a939535e3e668441958e70617..2856833e600798ef771965cc66d3a3eeaf88c763 100644 --- a/libcxx/include/__iterator/wrap_iter.h +++ b/libcxx/include/__iterator/wrap_iter.h @@ -13,13 +13,13 @@ #include <__compare/ordering.h> #include <__compare/three_way_comparable.h> #include <__config> +#include <__cstddef/size_t.h> #include <__iterator/iterator_traits.h> #include <__memory/addressof.h> #include <__memory/pointer_traits.h> #include <__type_traits/enable_if.h> #include <__type_traits/integral_constant.h> #include <__type_traits/is_convertible.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__mdspan/default_accessor.h b/libcxx/include/__mdspan/default_accessor.h index 1cc5f15545fc8cb8d50c8d74a896b89a955456e2..d6f3ddb998e96209ca50c6a7173a4a52507ca5dc 100644 --- a/libcxx/include/__mdspan/default_accessor.h +++ b/libcxx/include/__mdspan/default_accessor.h @@ -18,12 +18,11 @@ #define _LIBCPP___MDSPAN_DEFAULT_ACCESSOR_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/is_abstract.h> #include <__type_traits/is_array.h> #include <__type_traits/is_convertible.h> #include <__type_traits/remove_const.h> -#include -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__mdspan/extents.h b/libcxx/include/__mdspan/extents.h index 3d2c2771a834b4a04cbf2fc9e2b7be5215da5477..edbc30a7a40e422ad8d4c29beb51de5d74b7ea34 100644 --- a/libcxx/include/__mdspan/extents.h +++ b/libcxx/include/__mdspan/extents.h @@ -21,6 +21,7 @@ #include <__config> #include <__concepts/arithmetic.h> +#include <__cstddef/byte.h> #include <__type_traits/common_type.h> #include <__type_traits/is_convertible.h> #include <__type_traits/is_nothrow_constructible.h> @@ -29,9 +30,7 @@ #include <__utility/integer_sequence.h> #include <__utility/unreachable.h> #include -#include #include -#include #include #include diff --git a/libcxx/include/__mdspan/layout_left.h b/libcxx/include/__mdspan/layout_left.h index 59574e83b0d7b1ee754746dd7926c627bb8cc3c1..288b3dd8038ee29169b34879f975c7e20c789c9a 100644 --- a/libcxx/include/__mdspan/layout_left.h +++ b/libcxx/include/__mdspan/layout_left.h @@ -27,9 +27,6 @@ #include <__type_traits/is_nothrow_constructible.h> #include <__utility/integer_sequence.h> #include -#include -#include -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__mdspan/layout_right.h b/libcxx/include/__mdspan/layout_right.h index d1acdb41238f7f11c897cf51effaa6df0c019f61..72922d1049c7a19c4726ccc528bef4be6ca277e6 100644 --- a/libcxx/include/__mdspan/layout_right.h +++ b/libcxx/include/__mdspan/layout_right.h @@ -19,6 +19,7 @@ #include <__assert> #include <__config> +#include <__cstddef/size_t.h> #include <__fwd/mdspan.h> #include <__mdspan/extents.h> #include <__type_traits/common_type.h> @@ -26,9 +27,6 @@ #include <__type_traits/is_convertible.h> #include <__type_traits/is_nothrow_constructible.h> #include <__utility/integer_sequence.h> -#include -#include -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__mdspan/layout_stride.h b/libcxx/include/__mdspan/layout_stride.h index c57f596431c7c5661c4eba75cd18851dcb71d37b..bb93de97751457973dc1636d7196632d5530c197 100644 --- a/libcxx/include/__mdspan/layout_stride.h +++ b/libcxx/include/__mdspan/layout_stride.h @@ -32,8 +32,6 @@ #include <__utility/integer_sequence.h> #include <__utility/swap.h> #include -#include -#include #include #include diff --git a/libcxx/include/__mdspan/mdspan.h b/libcxx/include/__mdspan/mdspan.h index 1ff4fd4ba4a8298d3eb5b3b1702e9eca46cbbac8..3f9b35b185b16767a9d7aac1503601037493020f 100644 --- a/libcxx/include/__mdspan/mdspan.h +++ b/libcxx/include/__mdspan/mdspan.h @@ -37,9 +37,6 @@ #include <__type_traits/remove_reference.h> #include <__utility/integer_sequence.h> #include -#include -#include -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/align.h b/libcxx/include/__memory/align.h index bbb995f4a8c8eddb34c3911a8b4adfa4256bc89b..402eac3380925d32079b2ee17fadbd37681a5498 100644 --- a/libcxx/include/__memory/align.h +++ b/libcxx/include/__memory/align.h @@ -10,7 +10,7 @@ #define _LIBCPP___MEMORY_ALIGN_H #include <__config> -#include +#include <__cstddef/size_t.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory/aligned_alloc.h b/libcxx/include/__memory/aligned_alloc.h index 33fe8af77df7b51af9302fd5197c295478b04659..fb36983d9c3dc8d9c47592fad9ece9acdc98332e 100644 --- a/libcxx/include/__memory/aligned_alloc.h +++ b/libcxx/include/__memory/aligned_alloc.h @@ -10,7 +10,6 @@ #define _LIBCPP___MEMORY_ALIGNED_ALLOC_H #include <__config> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/allocate_at_least.h b/libcxx/include/__memory/allocate_at_least.h index a10e4fbaead38b3a80df5c870b2b20cacd2a3a00..9b5a8bcbd4596b770975d35542c398e3166c6b25 100644 --- a/libcxx/include/__memory/allocate_at_least.h +++ b/libcxx/include/__memory/allocate_at_least.h @@ -10,8 +10,8 @@ #define _LIBCPP___MEMORY_ALLOCATE_AT_LEAST_H #include <__config> +#include <__cstddef/size_t.h> #include <__memory/allocator_traits.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory/allocation_guard.h b/libcxx/include/__memory/allocation_guard.h index cb870af7be6760ea780921b0708ef301411c41a0..66d6a5002c299e3d85f93de95f51b88469610178 100644 --- a/libcxx/include/__memory/allocation_guard.h +++ b/libcxx/include/__memory/allocation_guard.h @@ -14,7 +14,6 @@ #include <__memory/addressof.h> #include <__memory/allocator_traits.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory/allocator.h b/libcxx/include/__memory/allocator.h index cd146da8e7eb5cd962a17c024f1254122ea06792..ddb4179940b8b19c78f30d422c168abb884a3963 100644 --- a/libcxx/include/__memory/allocator.h +++ b/libcxx/include/__memory/allocator.h @@ -11,6 +11,7 @@ #define _LIBCPP___MEMORY_ALLOCATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__memory/addressof.h> #include <__memory/allocate_at_least.h> #include <__memory/allocator_traits.h> @@ -20,7 +21,6 @@ #include <__type_traits/is_void.h> #include <__type_traits/is_volatile.h> #include <__utility/forward.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/allocator_traits.h b/libcxx/include/__memory/allocator_traits.h index f4d9679807ae01aff48c5a159a6e0b4b40578984..499b30b85b6c9b9fbaaf0be39202613e3734e313 100644 --- a/libcxx/include/__memory/allocator_traits.h +++ b/libcxx/include/__memory/allocator_traits.h @@ -11,6 +11,7 @@ #define _LIBCPP___MEMORY_ALLOCATOR_TRAITS_H #include <__config> +#include <__cstddef/size_t.h> #include <__fwd/memory.h> #include <__memory/construct_at.h> #include <__memory/pointer_traits.h> @@ -23,7 +24,6 @@ #include <__type_traits/void_t.h> #include <__utility/declval.h> #include <__utility/forward.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/array_cookie.h b/libcxx/include/__memory/array_cookie.h index 10b29c9dcc78e34585945c09f36d6d01e51145c3..806a9e99ecafe74f2053c222958c923fdafce90b 100644 --- a/libcxx/include/__memory/array_cookie.h +++ b/libcxx/include/__memory/array_cookie.h @@ -12,10 +12,10 @@ #include <__config> #include <__configuration/abi.h> +#include <__cstddef/size_t.h> #include <__type_traits/integral_constant.h> #include <__type_traits/is_trivially_destructible.h> #include <__type_traits/negation.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory/assume_aligned.h b/libcxx/include/__memory/assume_aligned.h index c7ba2a99c7e2260d1803dce7ed4fc5299a46e641..08f1772cd6dfa6b91af52b11347ea6d870fefde1 100644 --- a/libcxx/include/__memory/assume_aligned.h +++ b/libcxx/include/__memory/assume_aligned.h @@ -12,8 +12,8 @@ #include <__assert> #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/is_constant_evaluated.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/builtin_new_allocator.h b/libcxx/include/__memory/builtin_new_allocator.h index c6f7f3c5ff52a13db06617db2c2ffab3577ca139..128288efb05bc16525edf2a65497766b20d27d62 100644 --- a/libcxx/include/__memory/builtin_new_allocator.h +++ b/libcxx/include/__memory/builtin_new_allocator.h @@ -11,7 +11,6 @@ #include <__config> #include <__memory/unique_ptr.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/compressed_pair.h b/libcxx/include/__memory/compressed_pair.h index 9d44775bdb4871f7ed4889752acb4468ea2faebc..a7acaaff9da09960ae730938ddd163c119157d94 100644 --- a/libcxx/include/__memory/compressed_pair.h +++ b/libcxx/include/__memory/compressed_pair.h @@ -11,6 +11,7 @@ #define _LIBCPP___MEMORY_COMPRESSED_PAIR_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/datasizeof.h> #include <__type_traits/is_empty.h> #include <__type_traits/is_final.h> diff --git a/libcxx/include/__memory/destruct_n.h b/libcxx/include/__memory/destruct_n.h index 78635ad0af04bdb160083a69a1be4caac6ca08cc..66adefb0f51fc7aa5ed382a50a616a96cb7d9b43 100644 --- a/libcxx/include/__memory/destruct_n.h +++ b/libcxx/include/__memory/destruct_n.h @@ -10,9 +10,9 @@ #define _LIBCPP___MEMORY_DESTRUCT_N_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/integral_constant.h> #include <__type_traits/is_trivially_destructible.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory/pointer_traits.h b/libcxx/include/__memory/pointer_traits.h index 98961ddf9709f6876eb57662f4526cf1cb9bf3a8..4acf3d18401ae4d649f7f9fdaa65d64bf06e895b 100644 --- a/libcxx/include/__memory/pointer_traits.h +++ b/libcxx/include/__memory/pointer_traits.h @@ -11,6 +11,7 @@ #define _LIBCPP___MEMORY_POINTER_TRAITS_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__memory/addressof.h> #include <__type_traits/conditional.h> #include <__type_traits/conjunction.h> @@ -23,7 +24,6 @@ #include <__type_traits/void_t.h> #include <__utility/declval.h> #include <__utility/forward.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory/raw_storage_iterator.h b/libcxx/include/__memory/raw_storage_iterator.h index 774878aa1c5e81e7a2c806cb659ec5d8711e6532..2ee4c074d8d33786026473f4b9cbc8a76e75e6fa 100644 --- a/libcxx/include/__memory/raw_storage_iterator.h +++ b/libcxx/include/__memory/raw_storage_iterator.h @@ -11,11 +11,11 @@ #define _LIBCPP___MEMORY_RAW_STORAGE_ITERATOR_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/iterator.h> #include <__iterator/iterator_traits.h> #include <__memory/addressof.h> #include <__utility/move.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/shared_ptr.h b/libcxx/include/__memory/shared_ptr.h index 65870ba574c25bc7d77cbb09cb2b0ba88387bf2e..e5adbedce1a2d8ce1a26795f7aee9823a907ea8c 100644 --- a/libcxx/include/__memory/shared_ptr.h +++ b/libcxx/include/__memory/shared_ptr.h @@ -13,6 +13,7 @@ #include <__compare/compare_three_way.h> #include <__compare/ordering.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__exception/exception.h> #include <__functional/binary_function.h> #include <__functional/operations.h> @@ -51,7 +52,6 @@ #include <__utility/move.h> #include <__utility/swap.h> #include <__verbose_abort> -#include #include #include #if _LIBCPP_HAS_ATOMIC_HEADER diff --git a/libcxx/include/__memory/temporary_buffer.h b/libcxx/include/__memory/temporary_buffer.h index 219e03f99bc01d9412fc88873f2efc76c1f704d6..d18717f52d1cddcf2f99e931271482127010e0ad 100644 --- a/libcxx/include/__memory/temporary_buffer.h +++ b/libcxx/include/__memory/temporary_buffer.h @@ -11,10 +11,9 @@ #define _LIBCPP___MEMORY_TEMPORARY_BUFFER_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__memory/unique_temporary_buffer.h> #include <__utility/pair.h> -#include -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory/unique_ptr.h b/libcxx/include/__memory/unique_ptr.h index 6e42ef1eaa1a3cdd7fe717a9f1e7a3e9bcbd898d..4ed6393b1209f5ac64fae2c22fdf8ba3dcb51d04 100644 --- a/libcxx/include/__memory/unique_ptr.h +++ b/libcxx/include/__memory/unique_ptr.h @@ -15,6 +15,8 @@ #include <__compare/compare_three_way_result.h> #include <__compare/three_way_comparable.h> #include <__config> +#include <__cstddef/nullptr_t.h> +#include <__cstddef/size_t.h> #include <__functional/hash.h> #include <__functional/operations.h> #include <__memory/allocator_traits.h> // __pointer @@ -46,7 +48,6 @@ #include <__utility/forward.h> #include <__utility/move.h> #include <__utility/private_constructor_tag.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/unique_temporary_buffer.h b/libcxx/include/__memory/unique_temporary_buffer.h index 8a8c327be69fe72888b1d2b2f907e761672cb7c3..4f47c84e2f8dbe854e7592d73d4f22b23ca1a6b7 100644 --- a/libcxx/include/__memory/unique_temporary_buffer.h +++ b/libcxx/include/__memory/unique_temporary_buffer.h @@ -13,10 +13,10 @@ #include <__assert> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__memory/allocator.h> #include <__memory/unique_ptr.h> #include <__type_traits/is_constant_evaluated.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory/uses_allocator.h b/libcxx/include/__memory/uses_allocator.h index 16504e8b2a998954a12fc90df0f42fa9c1526167..20aa0e6b7f27246173242032fe688ec295c51a28 100644 --- a/libcxx/include/__memory/uses_allocator.h +++ b/libcxx/include/__memory/uses_allocator.h @@ -13,7 +13,6 @@ #include <__config> #include <__type_traits/integral_constant.h> #include <__type_traits/is_convertible.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory_resource/memory_resource.h b/libcxx/include/__memory_resource/memory_resource.h index ea85e50cd568bc38e22c22fa1a0a8109a9f4c945..f93f10fe21a2d00386b9c774f0b0980e2a3299ce 100644 --- a/libcxx/include/__memory_resource/memory_resource.h +++ b/libcxx/include/__memory_resource/memory_resource.h @@ -10,8 +10,9 @@ #define _LIBCPP___MEMORY_RESOURCE_MEMORY_RESOURCE_H #include <__config> +#include <__cstddef/max_align_t.h> +#include <__cstddef/size_t.h> #include <__fwd/memory_resource.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory_resource/monotonic_buffer_resource.h b/libcxx/include/__memory_resource/monotonic_buffer_resource.h index f45b30fdb38616d071dfbd5daaad0a16032272fb..c5a2b556707f6a2b79906328046552cbc068fd70 100644 --- a/libcxx/include/__memory_resource/monotonic_buffer_resource.h +++ b/libcxx/include/__memory_resource/monotonic_buffer_resource.h @@ -10,9 +10,9 @@ #define _LIBCPP___MEMORY_RESOURCE_MONOTONIC_BUFFER_RESOURCE_H #include <__config> +#include <__cstddef/size_t.h> #include <__memory/addressof.h> #include <__memory_resource/memory_resource.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory_resource/polymorphic_allocator.h b/libcxx/include/__memory_resource/polymorphic_allocator.h index fb36d5cad78ec64e739607e2a103d0603e295b01..30fa5c2170d5025652b15ae991e824adf81d60b8 100644 --- a/libcxx/include/__memory_resource/polymorphic_allocator.h +++ b/libcxx/include/__memory_resource/polymorphic_allocator.h @@ -11,10 +11,11 @@ #include <__assert> #include <__config> +#include <__cstddef/byte.h> +#include <__cstddef/max_align_t.h> #include <__fwd/pair.h> #include <__memory_resource/memory_resource.h> #include <__utility/exception_guard.h> -#include #include #include #include diff --git a/libcxx/include/__memory_resource/pool_options.h b/libcxx/include/__memory_resource/pool_options.h index 442959836c7ef3f5dcc349fbcdd5837fd34ffe1a..324b8aaa8502b13403e06a17d1ecb702d77581bd 100644 --- a/libcxx/include/__memory_resource/pool_options.h +++ b/libcxx/include/__memory_resource/pool_options.h @@ -10,7 +10,7 @@ #define _LIBCPP___MEMORY_RESOURCE_POOL_OPTIONS_H #include <__config> -#include +#include <__cstddef/size_t.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__memory_resource/synchronized_pool_resource.h b/libcxx/include/__memory_resource/synchronized_pool_resource.h index 50a673c2861d103551ebeeaa9cb3a3c8da594d4b..2679afc16617ba7e48ad6611d3a5dacd24a5ded4 100644 --- a/libcxx/include/__memory_resource/synchronized_pool_resource.h +++ b/libcxx/include/__memory_resource/synchronized_pool_resource.h @@ -13,7 +13,6 @@ #include <__memory_resource/memory_resource.h> #include <__memory_resource/pool_options.h> #include <__memory_resource/unsynchronized_pool_resource.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__memory_resource/unsynchronized_pool_resource.h b/libcxx/include/__memory_resource/unsynchronized_pool_resource.h index 783db84262af723058f759fc76565dd286ff8868..92da16c559fea84ebe7c316a8520ef9d2e63a5f3 100644 --- a/libcxx/include/__memory_resource/unsynchronized_pool_resource.h +++ b/libcxx/include/__memory_resource/unsynchronized_pool_resource.h @@ -10,9 +10,9 @@ #define _LIBCPP___MEMORY_RESOURCE_UNSYNCHRONIZED_POOL_RESOURCE_H #include <__config> +#include <__cstddef/size_t.h> #include <__memory_resource/memory_resource.h> #include <__memory_resource/pool_options.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__numeric/midpoint.h b/libcxx/include/__numeric/midpoint.h index 5ef30d4ec50f5ad625f6607805adf230193de3ac..2ba80e5cca07d3d87840e14c2da970f14c4cec80 100644 --- a/libcxx/include/__numeric/midpoint.h +++ b/libcxx/include/__numeric/midpoint.h @@ -11,6 +11,7 @@ #define _LIBCPP___NUMERIC_MIDPOINT_H #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_floating_point.h> #include <__type_traits/is_integral.h> @@ -21,7 +22,6 @@ #include <__type_traits/is_void.h> #include <__type_traits/make_unsigned.h> #include <__type_traits/remove_pointer.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__ostream/basic_ostream.h b/libcxx/include/__ostream/basic_ostream.h index 1b1c026706cdfd138c63d9dd2a234fa293638980..fc72247725b490d476afedac4956ab313f349e04 100644 --- a/libcxx/include/__ostream/basic_ostream.h +++ b/libcxx/include/__ostream/basic_ostream.h @@ -23,7 +23,6 @@ # include <__type_traits/void_t.h> # include <__utility/declval.h> # include -# include # include # include # include // for __throw_bad_alloc diff --git a/libcxx/include/__pstl/backends/libdispatch.h b/libcxx/include/__pstl/backends/libdispatch.h index a92d0978e5c640409c9632b2a19014a04de0a9e0..701367b505c8b78add28607185459edd3097d588 100644 --- a/libcxx/include/__pstl/backends/libdispatch.h +++ b/libcxx/include/__pstl/backends/libdispatch.h @@ -16,6 +16,7 @@ #include <__algorithm/upper_bound.h> #include <__atomic/atomic.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__exception/terminate.h> #include <__iterator/iterator_traits.h> #include <__iterator/move_iterator.h> @@ -37,7 +38,6 @@ #include <__utility/exception_guard.h> #include <__utility/move.h> #include <__utility/pair.h> -#include #include #include diff --git a/libcxx/include/__pstl/backends/std_thread.h b/libcxx/include/__pstl/backends/std_thread.h index 19b985f860a1744562373d6a16e6a75b12dcbe5d..dd2c3f15403e3d1a82d62fe74d6e5a0abaf39ce4 100644 --- a/libcxx/include/__pstl/backends/std_thread.h +++ b/libcxx/include/__pstl/backends/std_thread.h @@ -22,7 +22,6 @@ #include <__pstl/cpu_algos/transform_reduce.h> #include <__utility/empty.h> #include <__utility/move.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__pstl/cpu_algos/cpu_traits.h b/libcxx/include/__pstl/cpu_algos/cpu_traits.h index 5e59752fa5723cc180069cc3b6778ff6bb0897ea..ec1622419d04903bde0c951708d10fa192b2cadd 100644 --- a/libcxx/include/__pstl/cpu_algos/cpu_traits.h +++ b/libcxx/include/__pstl/cpu_algos/cpu_traits.h @@ -10,7 +10,6 @@ #define _LIBCPP___PSTL_CPU_ALGOS_CPU_TRAITS_H #include <__config> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__pstl/cpu_algos/find_if.h b/libcxx/include/__pstl/cpu_algos/find_if.h index cd92e5a99f12f855069999f9e1d68a5a533d5e8b..ebb4ecb4a0ed36d6e7eb5dd38dafd087512aec45 100644 --- a/libcxx/include/__pstl/cpu_algos/find_if.h +++ b/libcxx/include/__pstl/cpu_algos/find_if.h @@ -21,7 +21,6 @@ #include <__type_traits/is_execution_policy.h> #include <__utility/move.h> #include <__utility/pair.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__pstl/cpu_algos/transform_reduce.h b/libcxx/include/__pstl/cpu_algos/transform_reduce.h index aafbf1ca96b40d27310ea348946c7daa0aa7397c..e9f622d832cd5cdf2a84481515c79695e49e71c3 100644 --- a/libcxx/include/__pstl/cpu_algos/transform_reduce.h +++ b/libcxx/include/__pstl/cpu_algos/transform_reduce.h @@ -20,7 +20,6 @@ #include <__type_traits/is_arithmetic.h> #include <__type_traits/is_execution_policy.h> #include <__utility/move.h> -#include #include #include diff --git a/libcxx/include/__random/discard_block_engine.h b/libcxx/include/__random/discard_block_engine.h index 07f599067279e6786a3f65be19e9cbec0de6c926..f319557a57365792e1d7d4ec40a13f901a3eecc8 100644 --- a/libcxx/include/__random/discard_block_engine.h +++ b/libcxx/include/__random/discard_block_engine.h @@ -10,11 +10,11 @@ #define _LIBCPP___RANDOM_DISCARD_BLOCK_ENGINE_H #include <__config> +#include <__cstddef/size_t.h> #include <__random/is_seed_sequence.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_convertible.h> #include <__utility/move.h> -#include #include #include diff --git a/libcxx/include/__random/discrete_distribution.h b/libcxx/include/__random/discrete_distribution.h index 931f7704ff97678391e2f15b7cb6a9f308b232d5..3ce4a495fb0c34369ee20a741504ed7e3c13c22d 100644 --- a/libcxx/include/__random/discrete_distribution.h +++ b/libcxx/include/__random/discrete_distribution.h @@ -14,7 +14,6 @@ #include <__random/is_valid.h> #include <__random/uniform_real_distribution.h> #include <__vector/vector.h> -#include #include #include #include diff --git a/libcxx/include/__random/independent_bits_engine.h b/libcxx/include/__random/independent_bits_engine.h index 0f4a7b82b98f898878557bdd74719bbcb2c76275..20f56e9b5756092a2c389aadf73f4836f07f0974 100644 --- a/libcxx/include/__random/independent_bits_engine.h +++ b/libcxx/include/__random/independent_bits_engine.h @@ -10,6 +10,7 @@ #define _LIBCPP___RANDOM_INDEPENDENT_BITS_ENGINE_H #include <__config> +#include <__cstddef/size_t.h> #include <__fwd/istream.h> #include <__fwd/ostream.h> #include <__random/is_seed_sequence.h> @@ -18,7 +19,6 @@ #include <__type_traits/enable_if.h> #include <__type_traits/is_convertible.h> #include <__utility/move.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__random/log2.h b/libcxx/include/__random/log2.h index c96a5247ff6dbe0919e0096646be6ca2a01e9819..fbf35bab9172861f82266400ab41e66fa30944f6 100644 --- a/libcxx/include/__random/log2.h +++ b/libcxx/include/__random/log2.h @@ -10,8 +10,8 @@ #define _LIBCPP___RANDOM_LOG2_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/conditional.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__random/mersenne_twister_engine.h b/libcxx/include/__random/mersenne_twister_engine.h index 1f50e608ce8d4e96ac4f6b594067b7b3be02331b..9dd87f9ce71a115b7e1ab279538951e631fe4aae 100644 --- a/libcxx/include/__random/mersenne_twister_engine.h +++ b/libcxx/include/__random/mersenne_twister_engine.h @@ -12,9 +12,9 @@ #include <__algorithm/equal.h> #include <__algorithm/min.h> #include <__config> +#include <__cstddef/size_t.h> #include <__random/is_seed_sequence.h> #include <__type_traits/enable_if.h> -#include #include #include #include diff --git a/libcxx/include/__random/piecewise_constant_distribution.h b/libcxx/include/__random/piecewise_constant_distribution.h index a864f848143ba179f54c1b897381c0b6acce45d8..5afe2ebeda3bb6964f4ebd9a73ec7d4a89f79f1b 100644 --- a/libcxx/include/__random/piecewise_constant_distribution.h +++ b/libcxx/include/__random/piecewise_constant_distribution.h @@ -11,6 +11,7 @@ #include <__algorithm/upper_bound.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__random/is_valid.h> #include <__random/uniform_real_distribution.h> #include <__vector/vector.h> diff --git a/libcxx/include/__random/piecewise_linear_distribution.h b/libcxx/include/__random/piecewise_linear_distribution.h index 24aa6cce91cf2d52458a1d5eb05fec106eda6942..0d14f882cbbb28d2f1848b16c6cc357b59aeb926 100644 --- a/libcxx/include/__random/piecewise_linear_distribution.h +++ b/libcxx/include/__random/piecewise_linear_distribution.h @@ -11,6 +11,7 @@ #include <__algorithm/upper_bound.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__random/is_valid.h> #include <__random/uniform_real_distribution.h> #include <__vector/comparison.h> diff --git a/libcxx/include/__random/shuffle_order_engine.h b/libcxx/include/__random/shuffle_order_engine.h index f54ed17e38383afbba3eb22a59e3db319db95e06..53f6c08971105e8edeeeaf2b69abd1a169f798fb 100644 --- a/libcxx/include/__random/shuffle_order_engine.h +++ b/libcxx/include/__random/shuffle_order_engine.h @@ -11,12 +11,12 @@ #include <__algorithm/equal.h> #include <__config> +#include <__cstddef/size_t.h> #include <__random/is_seed_sequence.h> #include <__type_traits/enable_if.h> #include <__type_traits/integral_constant.h> #include <__type_traits/is_convertible.h> #include <__utility/move.h> -#include #include #include diff --git a/libcxx/include/__random/subtract_with_carry_engine.h b/libcxx/include/__random/subtract_with_carry_engine.h index 926333cdda45ee8cd743e419b7d9b8de0b433ef1..e087ab4a3c2c7bb51b9a1273f555b401b9186b58 100644 --- a/libcxx/include/__random/subtract_with_carry_engine.h +++ b/libcxx/include/__random/subtract_with_carry_engine.h @@ -12,10 +12,10 @@ #include <__algorithm/equal.h> #include <__algorithm/min.h> #include <__config> +#include <__cstddef/size_t.h> #include <__random/is_seed_sequence.h> #include <__random/linear_congruential_engine.h> #include <__type_traits/enable_if.h> -#include #include #include #include diff --git a/libcxx/include/__random/uniform_int_distribution.h b/libcxx/include/__random/uniform_int_distribution.h index 4e3ca3efe568665c094939b1c5adc803f5da2539..fa2c33755b7398d68531a854ec71e7955383b79c 100644 --- a/libcxx/include/__random/uniform_int_distribution.h +++ b/libcxx/include/__random/uniform_int_distribution.h @@ -11,11 +11,11 @@ #include <__bit/countl.h> #include <__config> +#include <__cstddef/size_t.h> #include <__random/is_valid.h> #include <__random/log2.h> #include <__type_traits/conditional.h> #include <__type_traits/make_unsigned.h> -#include #include #include #include diff --git a/libcxx/include/__ranges/access.h b/libcxx/include/__ranges/access.h index c0a40c5e10178a8f8cfad0fd28a46fe951b4fe67..bbacef3eae6be16880900bc6592d239fee52c729 100644 --- a/libcxx/include/__ranges/access.h +++ b/libcxx/include/__ranges/access.h @@ -12,6 +12,7 @@ #include <__concepts/class_or_enum.h> #include <__config> +#include <__cstddef/size_t.h> #include <__iterator/concepts.h> #include <__iterator/readable_traits.h> #include <__ranges/enable_borrowed_range.h> @@ -21,7 +22,6 @@ #include <__type_traits/remove_reference.h> #include <__utility/auto_cast.h> #include <__utility/declval.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__ranges/counted.h b/libcxx/include/__ranges/counted.h index e365deca4e632d89b8f4304cd172826720e93c02..65bf1a371ec780ea33d5f1193cc3030277736576 100644 --- a/libcxx/include/__ranges/counted.h +++ b/libcxx/include/__ranges/counted.h @@ -12,6 +12,7 @@ #include <__concepts/convertible_to.h> #include <__config> +#include <__cstddef/size_t.h> #include <__iterator/concepts.h> #include <__iterator/counted_iterator.h> #include <__iterator/default_sentinel.h> @@ -22,7 +23,6 @@ #include <__type_traits/decay.h> #include <__utility/forward.h> #include <__utility/move.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__ranges/drop_view.h b/libcxx/include/__ranges/drop_view.h index bd66371f4ed218e1ad9f353cedd4a29c198933a3..87f66f17a2abe6d5112fbe462f033cf3581e9e2c 100644 --- a/libcxx/include/__ranges/drop_view.h +++ b/libcxx/include/__ranges/drop_view.h @@ -15,6 +15,7 @@ #include <__concepts/constructible.h> #include <__concepts/convertible_to.h> #include <__config> +#include <__cstddef/size_t.h> #include <__functional/bind_back.h> #include <__fwd/span.h> #include <__fwd/string_view.h> @@ -42,7 +43,6 @@ #include <__utility/auto_cast.h> #include <__utility/forward.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__ranges/elements_view.h b/libcxx/include/__ranges/elements_view.h index ac0d8dbbd52b7782bee0b09f3ffc6d49cd6e4667..c99282f37960c3736c6b00681d266214d5b0ef9a 100644 --- a/libcxx/include/__ranges/elements_view.h +++ b/libcxx/include/__ranges/elements_view.h @@ -37,7 +37,6 @@ #include <__utility/declval.h> #include <__utility/forward.h> #include <__utility/move.h> -#include #include // std::get #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__ranges/empty_view.h b/libcxx/include/__ranges/empty_view.h index 6c04b0200c35f2c5cd0f5378a5384591e3c2d799..fc08492110f53c196c4f4f73aeea0108958e2f01 100644 --- a/libcxx/include/__ranges/empty_view.h +++ b/libcxx/include/__ranges/empty_view.h @@ -11,10 +11,10 @@ #define _LIBCPP___RANGES_EMPTY_VIEW_H #include <__config> +#include <__cstddef/size_t.h> #include <__ranges/enable_borrowed_range.h> #include <__ranges/view_interface.h> #include <__type_traits/is_object.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__ranges/istream_view.h b/libcxx/include/__ranges/istream_view.h index cd7096d35c2c1f63d216d9d06c56834275990894..1820ef2a4c1f7e7229d67126e1f7eb41391d705a 100644 --- a/libcxx/include/__ranges/istream_view.h +++ b/libcxx/include/__ranges/istream_view.h @@ -14,6 +14,7 @@ #include <__concepts/derived_from.h> #include <__concepts/movable.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__fwd/istream.h> #include <__fwd/string.h> #include <__iterator/default_sentinel.h> @@ -22,7 +23,6 @@ #include <__ranges/view_interface.h> #include <__type_traits/remove_cvref.h> #include <__utility/forward.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__ranges/repeat_view.h b/libcxx/include/__ranges/repeat_view.h index 53e4beb270ad010c444f4b75807086be2d8d5fb5..93ceaf1711d329cd52add6d5fb0cfa4616f7110e 100644 --- a/libcxx/include/__ranges/repeat_view.h +++ b/libcxx/include/__ranges/repeat_view.h @@ -15,6 +15,7 @@ #include <__concepts/same_as.h> #include <__concepts/semiregular.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/concepts.h> #include <__iterator/iterator_traits.h> #include <__iterator/unreachable_sentinel.h> diff --git a/libcxx/include/__ranges/single_view.h b/libcxx/include/__ranges/single_view.h index 45244f34994d7472592551bd9753205dfffd62d0..955578b99cf58bfc90e28a55a4494a5f5495639f 100644 --- a/libcxx/include/__ranges/single_view.h +++ b/libcxx/include/__ranges/single_view.h @@ -12,6 +12,8 @@ #include <__concepts/constructible.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> +#include <__cstddef/size_t.h> #include <__ranges/movable_box.h> #include <__ranges/range_adaptor.h> #include <__ranges/view_interface.h> @@ -20,7 +22,6 @@ #include <__utility/forward.h> #include <__utility/in_place.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__ranges/size.h b/libcxx/include/__ranges/size.h index 40b0c6b6aad7a332403eb8e72717ef486edfc3ea..5da3a6ff268e80d5aecc597e3e7d92891aad21f2 100644 --- a/libcxx/include/__ranges/size.h +++ b/libcxx/include/__ranges/size.h @@ -13,6 +13,8 @@ #include <__concepts/arithmetic.h> #include <__concepts/class_or_enum.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> +#include <__cstddef/size_t.h> #include <__iterator/concepts.h> #include <__iterator/iterator_traits.h> #include <__ranges/access.h> @@ -22,7 +24,6 @@ #include <__type_traits/remove_cvref.h> #include <__utility/auto_cast.h> #include <__utility/declval.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__ranges/subrange.h b/libcxx/include/__ranges/subrange.h index 144746babb325f70b3a9b0483ba3c59bb2cd1ad7..a40eab3c5a257e15e94d2d2e3470851c47db3e92 100644 --- a/libcxx/include/__ranges/subrange.h +++ b/libcxx/include/__ranges/subrange.h @@ -17,6 +17,7 @@ #include <__concepts/derived_from.h> #include <__concepts/different_from.h> #include <__config> +#include <__cstddef/size_t.h> #include <__fwd/subrange.h> #include <__iterator/advance.h> #include <__iterator/concepts.h> @@ -40,7 +41,6 @@ #include <__type_traits/remove_const.h> #include <__type_traits/remove_pointer.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__ranges/take_view.h b/libcxx/include/__ranges/take_view.h index 8e2d354b58a554598a7e34766e64932f041ba5d3..39f99cee6b4dadfc0e8fbb2716cf99ab60b1068b 100644 --- a/libcxx/include/__ranges/take_view.h +++ b/libcxx/include/__ranges/take_view.h @@ -42,7 +42,6 @@ #include <__utility/auto_cast.h> #include <__utility/forward.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__ranges/to.h b/libcxx/include/__ranges/to.h index 52666075da3e263cae7ac50577b1a8db97151c48..76249bdd9891c8d68a81fa65851e784ea05dea83 100644 --- a/libcxx/include/__ranges/to.h +++ b/libcxx/include/__ranges/to.h @@ -15,6 +15,7 @@ #include <__concepts/derived_from.h> #include <__concepts/same_as.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__functional/bind_back.h> #include <__iterator/iterator_traits.h> #include <__ranges/access.h> @@ -30,7 +31,6 @@ #include <__type_traits/type_identity.h> #include <__utility/declval.h> #include <__utility/forward.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__split_buffer b/libcxx/include/__split_buffer index c4817601039f3bf199ad3413cab9b887ec7ced0e..6fc3d9255946ce0001e9a5aa5bcff83cd23a5386 100644 --- a/libcxx/include/__split_buffer +++ b/libcxx/include/__split_buffer @@ -14,6 +14,7 @@ #include <__algorithm/move.h> #include <__algorithm/move_backward.h> #include <__config> +#include <__cstddef/size_t.h> #include <__iterator/distance.h> #include <__iterator/iterator_traits.h> #include <__iterator/move_iterator.h> @@ -35,7 +36,6 @@ #include <__type_traits/remove_reference.h> #include <__utility/forward.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__stop_token/intrusive_shared_ptr.h b/libcxx/include/__stop_token/intrusive_shared_ptr.h index f00cea5bc2b670687b3bf3f1ec039229faa881e3..d20c5227ec7291721f48b858b65fb0a57affa8fc 100644 --- a/libcxx/include/__stop_token/intrusive_shared_ptr.h +++ b/libcxx/include/__stop_token/intrusive_shared_ptr.h @@ -13,10 +13,10 @@ #include <__atomic/atomic.h> #include <__atomic/memory_order.h> #include <__config> +#include <__cstddef/nullptr_t.h> #include <__type_traits/is_reference.h> #include <__utility/move.h> #include <__utility/swap.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__string/char_traits.h b/libcxx/include/__string/char_traits.h index 107f0a96a022776d23bf6603ad53cd864b5ea2e4..fff045be01805b19f308f268970cae0013b4f20d 100644 --- a/libcxx/include/__string/char_traits.h +++ b/libcxx/include/__string/char_traits.h @@ -24,7 +24,6 @@ #include <__string/constexpr_c_functions.h> #include <__type_traits/is_constant_evaluated.h> #include <__utility/is_pointer_in_range.h> -#include #include #include #include diff --git a/libcxx/include/__string/constexpr_c_functions.h b/libcxx/include/__string/constexpr_c_functions.h index e62a7b0cd1b3bb86f93c015b72b4957323a5382f..f50eac34a1c05a801d1052288d21cb58c9c0c8c6 100644 --- a/libcxx/include/__string/constexpr_c_functions.h +++ b/libcxx/include/__string/constexpr_c_functions.h @@ -10,6 +10,7 @@ #define _LIBCPP___STRING_CONSTEXPR_C_FUNCTIONS_H #include <__config> +#include <__cstddef/size_t.h> #include <__memory/addressof.h> #include <__memory/construct_at.h> #include <__type_traits/datasizeof.h> @@ -25,7 +26,6 @@ #include <__type_traits/is_trivially_lexicographically_comparable.h> #include <__type_traits/remove_cv.h> #include <__utility/is_pointer_in_range.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__system_error/error_code.h b/libcxx/include/__system_error/error_code.h index 475f2bb96a56d93597d2b67eeb0b3305aef13f97..6fa673b4ff713b36ec16742c781fe9a5b8298767 100644 --- a/libcxx/include/__system_error/error_code.h +++ b/libcxx/include/__system_error/error_code.h @@ -17,7 +17,6 @@ #include <__system_error/errc.h> #include <__system_error/error_category.h> #include <__system_error/error_condition.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__system_error/error_condition.h b/libcxx/include/__system_error/error_condition.h index 42898c1f0e901338caa5d082035247a861f9e424..bfee6528c3f1d267887994f0a23937fac0ae5877 100644 --- a/libcxx/include/__system_error/error_condition.h +++ b/libcxx/include/__system_error/error_condition.h @@ -16,7 +16,6 @@ #include <__functional/unary_function.h> #include <__system_error/errc.h> #include <__system_error/error_category.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__type_traits/desugars_to.h b/libcxx/include/__type_traits/desugars_to.h index b0ce7c414e5d778e574314435efc0251972847d1..452c70bfbad66deed7e8d1876c1ee0394ab5e4cc 100644 --- a/libcxx/include/__type_traits/desugars_to.h +++ b/libcxx/include/__type_traits/desugars_to.h @@ -25,6 +25,12 @@ struct __equal_tag {}; // syntactically, the operation is equivalent to calling `a + b` struct __plus_tag {}; +// syntactically, the operation is equivalent to calling `a < b` +struct __less_tag {}; + +// syntactically, the operation is equivalent to calling `a > b` +struct __greater_tag {}; + // syntactically, the operation is equivalent to calling `a < b`, and these expressions // have to be true for any `a` and `b`: // - `(a < b) == (b > a)` diff --git a/libcxx/include/__type_traits/is_trivially_copyable.h b/libcxx/include/__type_traits/is_trivially_copyable.h index e92af126ee94d937f4361120a834bc2b0e5eccf5..8eb3ba7581af159a4a33e2a20a0786fbaa45ce5d 100644 --- a/libcxx/include/__type_traits/is_trivially_copyable.h +++ b/libcxx/include/__type_traits/is_trivially_copyable.h @@ -27,10 +27,8 @@ template inline constexpr bool is_trivially_copyable_v = __is_trivially_copyable(_Tp); #endif -#if _LIBCPP_STD_VER >= 20 template -inline constexpr bool __is_cheap_to_copy = is_trivially_copyable_v<_Tp> && sizeof(_Tp) <= sizeof(std::intmax_t); -#endif +inline const bool __is_cheap_to_copy = __is_trivially_copyable(_Tp) && sizeof(_Tp) <= sizeof(std::intmax_t); _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__utility/in_place.h b/libcxx/include/__utility/in_place.h index 459b271675261cb084ddb001cd2aa54b034b26a8..edaa4e02c55f542fd004f954b6d06308a1533219 100644 --- a/libcxx/include/__utility/in_place.h +++ b/libcxx/include/__utility/in_place.h @@ -10,9 +10,9 @@ #define _LIBCPP___UTILITY_IN_PLACE_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/integral_constant.h> #include <__type_traits/remove_cvref.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__utility/integer_sequence.h b/libcxx/include/__utility/integer_sequence.h index ccce9433e7a801093d372099f7a40fe2af76e32f..35eb606ee37f67f6a0781db8f0d8dd0d244212df 100644 --- a/libcxx/include/__utility/integer_sequence.h +++ b/libcxx/include/__utility/integer_sequence.h @@ -10,8 +10,8 @@ #define _LIBCPP___UTILITY_INTEGER_SEQUENCE_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/is_integral.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__utility/pair.h b/libcxx/include/__utility/pair.h index 78534a3f399f25e4f829eabaac7967d07c16d8e9..cca6490476db11a84d299b5fbe16fbbb3d8afe78 100644 --- a/libcxx/include/__utility/pair.h +++ b/libcxx/include/__utility/pair.h @@ -13,6 +13,7 @@ #include <__compare/synth_three_way.h> #include <__concepts/different_from.h> #include <__config> +#include <__cstddef/size_t.h> #include <__fwd/array.h> #include <__fwd/pair.h> #include <__fwd/tuple.h> @@ -43,7 +44,6 @@ #include <__utility/forward.h> #include <__utility/move.h> #include <__utility/piecewise_construct.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__utility/priority_tag.h b/libcxx/include/__utility/priority_tag.h index a159ce7f1afb347dac9bfb246fe5227b78d4b722..ef7cf162b9b4ca51614e13244b0f45228a553296 100644 --- a/libcxx/include/__utility/priority_tag.h +++ b/libcxx/include/__utility/priority_tag.h @@ -10,7 +10,7 @@ #define _LIBCPP___UTILITY_PRIORITY_TAG_H #include <__config> -#include +#include <__cstddef/size_t.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__utility/small_buffer.h b/libcxx/include/__utility/small_buffer.h index 9e13797573d2d788dcb5250a7c8d2e7a9666ed44..70e068f89f62ed06795625d1c7821d25d85e7aab 100644 --- a/libcxx/include/__utility/small_buffer.h +++ b/libcxx/include/__utility/small_buffer.h @@ -10,13 +10,13 @@ #define _LIBCPP___UTILITY_SMALL_BUFFER_H #include <__config> +#include <__cstddef/byte.h> #include <__memory/construct_at.h> #include <__type_traits/decay.h> #include <__type_traits/is_trivially_constructible.h> #include <__type_traits/is_trivially_destructible.h> #include <__utility/exception_guard.h> #include <__utility/forward.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/include/__utility/swap.h b/libcxx/include/__utility/swap.h index ecfbdec75a2aeb42c69f1261735ced0d30fc2a8a..666d6d50f0d916bc6872162d71c0c94bb7d2cb65 100644 --- a/libcxx/include/__utility/swap.h +++ b/libcxx/include/__utility/swap.h @@ -10,6 +10,7 @@ #define _LIBCPP___UTILITY_SWAP_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_assignable.h> #include <__type_traits/is_constructible.h> @@ -18,7 +19,6 @@ #include <__type_traits/is_swappable.h> #include <__utility/declval.h> #include <__utility/move.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__variant/monostate.h b/libcxx/include/__variant/monostate.h index 16f156609eb7dfb7d4a53f02d74bc8be772d0978..c5d2dacaf42051d92944eef00de53a44a1bd9012 100644 --- a/libcxx/include/__variant/monostate.h +++ b/libcxx/include/__variant/monostate.h @@ -12,8 +12,8 @@ #include <__compare/ordering.h> #include <__config> +#include <__cstddef/size_t.h> #include <__functional/hash.h> -#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/array b/libcxx/include/array index 0e9af4198632d1b70005d7c433fdc7738505a741..b1a9f0d29e68a8b2f2493637e744cc8c606cda8d 100644 --- a/libcxx/include/array +++ b/libcxx/include/array @@ -118,6 +118,7 @@ template const T&& get(const array&&) noexce #include <__algorithm/swap_ranges.h> #include <__assert> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__fwd/array.h> #include <__iterator/reverse_iterator.h> #include <__iterator/wrap_iter.h> diff --git a/libcxx/include/atomic b/libcxx/include/atomic index ebd46238eec986083327699a8c7ec91217f56ef3..716d198bc236bbcce3f60e884469adac4b418f3f 100644 --- a/libcxx/include/atomic +++ b/libcxx/include/atomic @@ -620,6 +620,7 @@ template #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include # include +# include # include # include # include diff --git a/libcxx/include/barrier b/libcxx/include/barrier index abc014e8aaf5c06593da847c977a20659e49f127..36c30c7fe2e75567b9ecff2bc1f02cc18fea1ff7 100644 --- a/libcxx/include/barrier +++ b/libcxx/include/barrier @@ -52,11 +52,11 @@ namespace std # include <__assert> # include <__atomic/atomic_base.h> # include <__atomic/memory_order.h> +# include <__cstddef/ptrdiff_t.h> # include <__memory/unique_ptr.h> # include <__thread/poll_with_backoff.h> # include <__thread/timed_backoff_policy.h> # include <__utility/move.h> -# include # include # include # include diff --git a/libcxx/include/bitset b/libcxx/include/bitset index 645c172f3be499cc565f1d0fd75fdfcc0c23cda5..9f14b69e7a9b40b80369a74385ca968be59108b0 100644 --- a/libcxx/include/bitset +++ b/libcxx/include/bitset @@ -136,7 +136,6 @@ template struct hash>; #include <__functional/unary_function.h> #include <__type_traits/is_char_like_type.h> #include -#include #include #include #include diff --git a/libcxx/include/ccomplex b/libcxx/include/ccomplex index 94d2c8d7d003d4fb64f500de3214910295ad1caa..d379c9e7f0174a96abbda1bfeb028d0ffad7e96f 100644 --- a/libcxx/include/ccomplex +++ b/libcxx/include/ccomplex @@ -23,4 +23,16 @@ # pragma GCC system_header #endif +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_ccomplex _LIBCPP_DEPRECATED_("removed in C++20. Include instead.") = void; +using __use_standard_header_ccomplex = __standard_header_ccomplex; + +#elif _LIBCPP_STD_VER >= 17 + +using __standard_header_ccomplex _LIBCPP_DEPRECATED_("Include instead.") = void; +using __use_standard_header_ccomplex = __standard_header_ccomplex; + +#endif + #endif // _LIBCPP_CCOMPLEX diff --git a/libcxx/include/charconv b/libcxx/include/charconv index 29c6875008abb459eb3bbe467a5fb28181fc84aa..8f5e697eec439654ccbc41e93757bcf71a876cd4 100644 --- a/libcxx/include/charconv +++ b/libcxx/include/charconv @@ -111,6 +111,7 @@ _LIBCPP_END_NAMESPACE_STD #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include # include +# include # include # include # include diff --git a/libcxx/include/ciso646 b/libcxx/include/ciso646 index 1d859f08fac572ea686a6d51a28a928de337fcbc..5fcac79e38a7f2fa72e9045b464278d5650bdb91 100644 --- a/libcxx/include/ciso646 +++ b/libcxx/include/ciso646 @@ -21,4 +21,11 @@ # pragma GCC system_header #endif +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_ciso646 _LIBCPP_DEPRECATED_("removed in C++20. Include instead.") = void; +using __use_standard_header_ciso646 = __standard_header_ciso646; + +#endif + #endif // _LIBCPP_CISO646 diff --git a/libcxx/include/compare b/libcxx/include/compare index 8a41835b148978cadee96871ffd9c854f188fb7e..de0e4c7ec2280c430dd73678995d686c6ea41000 100644 --- a/libcxx/include/compare +++ b/libcxx/include/compare @@ -172,6 +172,7 @@ namespace std { #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include +# include # include #endif diff --git a/libcxx/include/complex b/libcxx/include/complex index 4030d96b003d568e2674381985721d267cda8e7d..15e42800fbfa0a66d0f9cb9894e18c819d0dd63f 100644 --- a/libcxx/include/complex +++ b/libcxx/include/complex @@ -1097,20 +1097,20 @@ inline _LIBCPP_HIDE_FROM_ABI complex<_Tp> pow(const complex<_Tp>& __x, const com return std::exp(__y * std::log(__x)); } -template +template ::value && is_floating_point<_Up>::value, int> = 0> inline _LIBCPP_HIDE_FROM_ABI complex::type> pow(const complex<_Tp>& __x, const complex<_Up>& __y) { typedef complex::type> result_type; return std::pow(result_type(__x), result_type(__y)); } -template ::value, int> = 0> +template ::value && is_arithmetic<_Up>::value, int> = 0> inline _LIBCPP_HIDE_FROM_ABI complex::type> pow(const complex<_Tp>& __x, const _Up& __y) { typedef complex::type> result_type; return std::pow(result_type(__x), result_type(__y)); } -template ::value, int> = 0> +template ::value && is_floating_point<_Up>::value, int> = 0> inline _LIBCPP_HIDE_FROM_ABI complex::type> pow(const _Tp& __x, const complex<_Up>& __y) { typedef complex::type> result_type; return std::pow(result_type(__x), result_type(__y)); diff --git a/libcxx/include/complex.h b/libcxx/include/complex.h index a3da21c843f3650f4936d0cce79036b9887d51bf..89595ae2068a6416b5375aad71a70fb93ebc0893 100644 --- a/libcxx/include/complex.h +++ b/libcxx/include/complex.h @@ -24,7 +24,7 @@ #endif #ifdef __cplusplus -# include +# include #elif __has_include_next() # include_next #endif diff --git a/libcxx/include/concepts b/libcxx/include/concepts index e89d216a593725f302cb2f7673e7a8016f1bf3b9..6db2caebaf5b1a447227ec49dbab9d83b7f7a7c1 100644 --- a/libcxx/include/concepts +++ b/libcxx/include/concepts @@ -158,11 +158,8 @@ namespace std { #include -#if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 17 +#if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include -#endif - -#if _LIBCPP_STD_VER <= 20 && !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) # include #endif diff --git a/libcxx/include/coroutine b/libcxx/include/coroutine index ee54388ad5aaf854f62c8774b2e9b41762f6efb4..18601717768c072df81e14447722a9e0c5c196a0 100644 --- a/libcxx/include/coroutine +++ b/libcxx/include/coroutine @@ -59,6 +59,7 @@ struct suspend_always; #endif #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include # include diff --git a/libcxx/include/cstdalign b/libcxx/include/cstdalign new file mode 100644 index 0000000000000000000000000000000000000000..e6a2a3c717742204045f20b257173ff8558925f1 --- /dev/null +++ b/libcxx/include/cstdalign @@ -0,0 +1,55 @@ +// -*- C++ -*- +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _LIBCPP_CSTDALIGN +#define _LIBCPP_CSTDALIGN + +/* + cstdalign synopsis + +Macros: + + __alignas_is_defined + __alignof_is_defined + +*/ + +#include <__config> + +// is not provided by libc++ +#if __has_include() +# include +# ifdef _LIBCPP_STDALIGN_H +# error "If libc++ starts defining , the __has_include check should move to libc++'s " +# endif +#endif + +#if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) +# pragma GCC system_header +#endif + +#undef __alignas_is_defined +#define __alignas_is_defined 1 + +#undef __alignof_is_defined +#define __alignof_is_defined 1 + +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_cstdalign _LIBCPP_DEPRECATED_("removed in C++20.") = void; +using __use_standard_header_cstdalign = __standard_header_cstdalign; + +#elif _LIBCPP_STD_VER >= 17 + +using __standard_header_cstdalign _LIBCPP_DEPRECATED = void; +using __use_standard_header_cstdalign = __standard_header_cstdalign; + +#endif + +#endif // _LIBCPP_CSTDALIGN diff --git a/libcxx/include/cstdbool b/libcxx/include/cstdbool index ef731c021a4ab887c4a7a649c2253bef79d329c8..1d627258e10c094e66f68b096fc437d74271e92b 100644 --- a/libcxx/include/cstdbool +++ b/libcxx/include/cstdbool @@ -28,4 +28,16 @@ Macros: #undef __bool_true_false_are_defined #define __bool_true_false_are_defined 1 +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_cstdbool _LIBCPP_DEPRECATED_("removed in C++20.") = void; +using __use_standard_header_cstdbool = __standard_header_cstdbool; + +#elif _LIBCPP_STD_VER >= 17 + +using __standard_header_cstdbool _LIBCPP_DEPRECATED = void; +using __use_standard_header_cstdbool = __standard_header_cstdbool; + +#endif + #endif // _LIBCPP_CSTDBOOL diff --git a/libcxx/include/ctgmath b/libcxx/include/ctgmath index 6237979be4906cc2fff21be5d0b6300f8dee33f4..7dbe952f021b74f75dbedd0af511b5664744a761 100644 --- a/libcxx/include/ctgmath +++ b/libcxx/include/ctgmath @@ -18,11 +18,23 @@ */ -#include #include +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header #endif +#if _LIBCPP_STD_VER >= 20 + +using __standard_header_ctgmath _LIBCPP_DEPRECATED_("removed in C++20. Include and instead.") = void; +using __use_standard_header_ctgmath = __standard_header_ctgmath; + +#elif _LIBCPP_STD_VER >= 17 + +using __standard_header_ctgmath _LIBCPP_DEPRECATED_("Include and instead.") = void; +using __use_standard_header_ctgmath = __standard_header_ctgmath; + +#endif + #endif // _LIBCPP_CTGMATH diff --git a/libcxx/include/exception b/libcxx/include/exception index 64463e02cb16aa4dbfb93dbd4ea5779960c5fe1a..88eaaf06bf4a2646cca04c6dce98c14d05b31922 100644 --- a/libcxx/include/exception +++ b/libcxx/include/exception @@ -89,6 +89,7 @@ template void rethrow_if_nested(const E& e); #endif #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include #endif diff --git a/libcxx/include/experimental/__simd/aligned_tag.h b/libcxx/include/experimental/__simd/aligned_tag.h index e364e146a601169c1c5bf6fe0d9ec98989f7dba7..d208bf5c4fbb97342067555554023a6a9b15ad63 100644 --- a/libcxx/include/experimental/__simd/aligned_tag.h +++ b/libcxx/include/experimental/__simd/aligned_tag.h @@ -11,9 +11,9 @@ #define _LIBCPP_EXPERIMENTAL___SIMD_ALIGNED_TAG_H #include <__config> +#include <__cstddef/size_t.h> #include <__memory/assume_aligned.h> #include <__type_traits/remove_const.h> -#include #include #if _LIBCPP_STD_VER >= 17 && defined(_LIBCPP_ENABLE_EXPERIMENTAL) diff --git a/libcxx/include/experimental/__simd/declaration.h b/libcxx/include/experimental/__simd/declaration.h index 2ac7224159cf35d04d11eae64ccf4f3d7f659186..1b4fcf958516c98fa274e4099969873d4a7af34f 100644 --- a/libcxx/include/experimental/__simd/declaration.h +++ b/libcxx/include/experimental/__simd/declaration.h @@ -11,7 +11,7 @@ #define _LIBCPP_EXPERIMENTAL___SIMD_DECLARATION_H #include <__config> -#include +#include <__cstddef/size_t.h> #if _LIBCPP_STD_VER >= 17 && defined(_LIBCPP_ENABLE_EXPERIMENTAL) diff --git a/libcxx/include/experimental/__simd/reference.h b/libcxx/include/experimental/__simd/reference.h index cba460baaa95bbc7240b2607f52504829f0fdccd..b9fe962348adc9f2814512b3e097686d4e1c4f26 100644 --- a/libcxx/include/experimental/__simd/reference.h +++ b/libcxx/include/experimental/__simd/reference.h @@ -11,13 +11,13 @@ #define _LIBCPP_EXPERIMENTAL___SIMD_REFERENCE_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_assignable.h> #include <__type_traits/is_same.h> #include <__utility/declval.h> #include <__utility/forward.h> #include <__utility/move.h> -#include #include _LIBCPP_PUSH_MACROS diff --git a/libcxx/include/experimental/__simd/scalar.h b/libcxx/include/experimental/__simd/scalar.h index d7ac1225fd7896551be94889a4f81ee1d57e46bf..da318d2f4650fd0bfcc2fd5e212527ef2389ac12 100644 --- a/libcxx/include/experimental/__simd/scalar.h +++ b/libcxx/include/experimental/__simd/scalar.h @@ -12,8 +12,8 @@ #include <__assert> #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/integral_constant.h> -#include #include #include diff --git a/libcxx/include/experimental/__simd/simd.h b/libcxx/include/experimental/__simd/simd.h index 8d8d96518d97b0307160e35a50b474310b243886..fd919e75e32f51b269f1ed3b10081e93dde253d2 100644 --- a/libcxx/include/experimental/__simd/simd.h +++ b/libcxx/include/experimental/__simd/simd.h @@ -11,12 +11,12 @@ #define _LIBCPP_EXPERIMENTAL___SIMD_SIMD_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_integral.h> #include <__type_traits/is_same.h> #include <__type_traits/remove_cvref.h> #include <__utility/forward.h> -#include #include #include #include diff --git a/libcxx/include/experimental/__simd/simd_mask.h b/libcxx/include/experimental/__simd/simd_mask.h index 03e9da8519bfb935c9f46b50a1e93f777ce48789..6b6f671bf3e64c01e1d7aed7414b6cd577f4ddcd 100644 --- a/libcxx/include/experimental/__simd/simd_mask.h +++ b/libcxx/include/experimental/__simd/simd_mask.h @@ -11,9 +11,9 @@ #define _LIBCPP_EXPERIMENTAL___SIMD_SIMD_MASK_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_same.h> -#include #include #include #include diff --git a/libcxx/include/experimental/__simd/traits.h b/libcxx/include/experimental/__simd/traits.h index b817df604ef72e5918f35e8c5e9d3f30424b3fb9..0bcc2eeba5ce8b524627ab0ef15ce3fb9e70cb4c 100644 --- a/libcxx/include/experimental/__simd/traits.h +++ b/libcxx/include/experimental/__simd/traits.h @@ -12,9 +12,9 @@ #include <__bit/bit_ceil.h> #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/integral_constant.h> #include <__type_traits/is_same.h> -#include #include #include diff --git a/libcxx/include/experimental/__simd/utility.h b/libcxx/include/experimental/__simd/utility.h index 01736925d155c4cbf41b8f639d91a84edcddcec1..fd9fcecc7986570158022550385c0b263206a163 100644 --- a/libcxx/include/experimental/__simd/utility.h +++ b/libcxx/include/experimental/__simd/utility.h @@ -11,6 +11,7 @@ #define _LIBCPP_EXPERIMENTAL___SIMD_UTILITY_H #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/is_arithmetic.h> #include <__type_traits/is_const.h> #include <__type_traits/is_constant_evaluated.h> @@ -21,7 +22,6 @@ #include <__type_traits/void_t.h> #include <__utility/declval.h> #include <__utility/integer_sequence.h> -#include #include #include diff --git a/libcxx/include/experimental/__simd/vec_ext.h b/libcxx/include/experimental/__simd/vec_ext.h index 6e8400948d46a72d97ff72c3c558652ff9cdd498..abc7e9595be9c832c1e4381c1758bb91f0e8fccf 100644 --- a/libcxx/include/experimental/__simd/vec_ext.h +++ b/libcxx/include/experimental/__simd/vec_ext.h @@ -13,10 +13,10 @@ #include <__assert> #include <__bit/bit_ceil.h> #include <__config> +#include <__cstddef/size_t.h> #include <__type_traits/integral_constant.h> #include <__utility/forward.h> #include <__utility/integer_sequence.h> -#include #include #include #include diff --git a/libcxx/include/experimental/iterator b/libcxx/include/experimental/iterator index e3a9c771fe61cf6223e5e1100f88fc00b9c5b3bf..2488bcfc155a8de305d55b4f702871b3b8b449fa 100644 --- a/libcxx/include/experimental/iterator +++ b/libcxx/include/experimental/iterator @@ -122,6 +122,7 @@ _LIBCPP_END_NAMESPACE_LFTS _LIBCPP_POP_MACROS #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include #endif diff --git a/libcxx/include/experimental/memory b/libcxx/include/experimental/memory index bf8a154690af019dda21f634ae4e4e04963f4bc4..48e42a0a88a6493951157aa7a176c3a405389ce2 100644 --- a/libcxx/include/experimental/memory +++ b/libcxx/include/experimental/memory @@ -50,6 +50,8 @@ public: */ #include <__config> +#include <__cstddef/nullptr_t.h> +#include <__cstddef/size_t.h> #include <__functional/hash.h> #include <__functional/operations.h> #include <__type_traits/add_lvalue_reference.h> @@ -57,7 +59,7 @@ public: #include <__type_traits/common_type.h> #include <__type_traits/enable_if.h> #include <__type_traits/is_convertible.h> -#include +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -192,6 +194,7 @@ _LIBCPP_END_NAMESPACE_STD #endif // _LIBCPP_ENABLE_EXPERIMENTAL #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include #endif diff --git a/libcxx/include/experimental/propagate_const b/libcxx/include/experimental/propagate_const index 510d374bb4bf948b736c05ec7697c1d211408415..8466d4e9c7ef3cfda0717c86467d5adda0566478 100644 --- a/libcxx/include/experimental/propagate_const +++ b/libcxx/include/experimental/propagate_const @@ -108,6 +108,8 @@ */ #include <__config> +#include <__cstddef/nullptr_t.h> +#include <__cstddef/size_t.h> #include <__functional/operations.h> #include <__fwd/functional.h> #include <__type_traits/conditional.h> @@ -128,7 +130,7 @@ #include <__utility/forward.h> #include <__utility/move.h> #include <__utility/swap.h> -#include +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -484,6 +486,7 @@ _LIBCPP_END_NAMESPACE_STD _LIBCPP_POP_MACROS #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include #endif diff --git a/libcxx/include/experimental/simd b/libcxx/include/experimental/simd index 35120b4b4aab421d1bb5bb28bb0c08eff3e37cb3..1a868513d160b6642a54950dc2ad1613cd050d46 100644 --- a/libcxx/include/experimental/simd +++ b/libcxx/include/experimental/simd @@ -85,4 +85,8 @@ inline namespace parallelism_v2 { #include #include +#if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include +#endif + #endif /* _LIBCPP_EXPERIMENTAL_SIMD */ diff --git a/libcxx/include/experimental/type_traits b/libcxx/include/experimental/type_traits index a4bb59afaf4ac2729d66d8cc3df7e51218b95411..6980fc3c51e4650b3ce8df09a0a0dfdc7e17bdb0 100644 --- a/libcxx/include/experimental/type_traits +++ b/libcxx/include/experimental/type_traits @@ -148,6 +148,10 @@ constexpr bool is_detected_convertible_v = is_detected_convertible<_To, _Op, _Ar _LIBCPP_END_NAMESPACE_LFTS +# if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include +# endif + #endif /* _LIBCPP_STD_VER >= 14 */ #endif /* _LIBCPP_EXPERIMENTAL_TYPE_TRAITS */ diff --git a/libcxx/include/experimental/utility b/libcxx/include/experimental/utility index cbc7ad140e40c11dfa5c8ad40fa815196dea6517..00151b967e496de0da44ce325662e8dbe6d5c0a7 100644 --- a/libcxx/include/experimental/utility +++ b/libcxx/include/experimental/utility @@ -43,4 +43,8 @@ struct _LIBCPP_TEMPLATE_VIS erased_type {}; _LIBCPP_END_NAMESPACE_LFTS +#if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include +#endif + #endif /* _LIBCPP_EXPERIMENTAL_UTILITY */ diff --git a/libcxx/include/initializer_list b/libcxx/include/initializer_list index 680ca1cd20d550121818b230320a00dd2e337dfb..8b9325069c129640ec56b9b32c8864f8deea57f6 100644 --- a/libcxx/include/initializer_list +++ b/libcxx/include/initializer_list @@ -43,7 +43,8 @@ template const E* end(initializer_list il) noexcept; // constexpr in */ #include <__config> -#include +#include <__cstddef/size_t.h> +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -95,4 +96,8 @@ inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 const _Ep* end(initia } // namespace std +#if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include +#endif + #endif // _LIBCPP_INITIALIZER_LIST diff --git a/libcxx/include/iterator b/libcxx/include/iterator index fca75f0a19ed1b97a0273745d1c3cb59fb7eb953..63fbae220b604ed386a9d6938fce560b4a99ee1f 100644 --- a/libcxx/include/iterator +++ b/libcxx/include/iterator @@ -743,6 +743,7 @@ template constexpr const E* data(initializer_list il) noexcept; #endif #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include # include diff --git a/libcxx/include/latch b/libcxx/include/latch index b56e49bc768bf921d5a69453e7dfa625cd790daf..92dadf68bcaabb84b9e3b76de676e336a3e27152 100644 --- a/libcxx/include/latch +++ b/libcxx/include/latch @@ -48,7 +48,7 @@ namespace std # include <__atomic/atomic_base.h> # include <__atomic/atomic_sync.h> # include <__atomic/memory_order.h> -# include +# include <__cstddef/ptrdiff_t.h> # include # include @@ -124,6 +124,7 @@ _LIBCPP_POP_MACROS #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include +# include #endif #endif // _LIBCPP_LATCH diff --git a/libcxx/include/module.modulemap b/libcxx/include/module.modulemap index c3561590e06d8a7fa0a4acee228adcb7290652af..70f91249a58ec0eb7466d017436fd2763c691176 100644 --- a/libcxx/include/module.modulemap +++ b/libcxx/include/module.modulemap @@ -13,7 +13,10 @@ module std_config [system] { module std_core [system] { module cstddef { module byte { header "__cstddef/byte.h" } - module max_align_t { header "__cstddef/max_align_t.h" } + module max_align_t { + header "__cstddef/max_align_t.h" + export * + } module nullptr_t { header "__cstddef/nullptr_t.h" } module ptrdiff_t { header "__cstddef/ptrdiff_t.h" } module size_t { header "__cstddef/size_t.h" } @@ -1109,6 +1112,11 @@ module std [system] { export * } + module cstdalign { + header "cstdalign" + export * + } + module cstdarg { header "cstdarg" export * @@ -1229,7 +1237,7 @@ module std [system] { header "flat_map" export * } - + module format { module buffer { header "__format/buffer.h" } module concepts { header "__format/concepts.h" } @@ -1403,7 +1411,10 @@ module std [system] { module indirectly_comparable { header "__iterator/indirectly_comparable.h" } module insert_iterator { header "__iterator/insert_iterator.h" } module istream_iterator { header "__iterator/istream_iterator.h" } - module istreambuf_iterator { header "__iterator/istreambuf_iterator.h" } + module istreambuf_iterator { + header "__iterator/istreambuf_iterator.h" + export std.string.char_traits + } module iter_move { header "__iterator/iter_move.h" } module iter_swap { header "__iterator/iter_swap.h" } module iterator_traits { diff --git a/libcxx/include/mutex b/libcxx/include/mutex index 02c52dd72f02b078c12415500e62da86c79b1ceb..427fce5f3ec46326c26e9565ee6e5e32ce1e1876 100644 --- a/libcxx/include/mutex +++ b/libcxx/include/mutex @@ -199,7 +199,6 @@ template #include <__thread/id.h> #include <__thread/support.h> #include <__utility/forward.h> -#include #include #ifndef _LIBCPP_CXX03_LANG # include diff --git a/libcxx/include/new b/libcxx/include/new index 75e2b8742df6bdef588597a41661e2546fd790c4..290ad9e97f8ded9ccc0003214a32a538749f35ed 100644 --- a/libcxx/include/new +++ b/libcxx/include/new @@ -87,12 +87,12 @@ void operator delete[](void* ptr, void*) noexcept; */ #include <__config> +#include <__cstddef/size_t.h> #include <__exception/exception.h> #include <__type_traits/is_function.h> #include <__type_traits/is_same.h> #include <__type_traits/remove_cv.h> #include <__verbose_abort> -#include #include #if defined(_LIBCPP_ABI_VCRUNTIME) @@ -367,6 +367,7 @@ inline constexpr size_t hardware_constructive_interference_size = __GCC_CONSTRUC _LIBCPP_END_NAMESPACE_STD #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include #endif diff --git a/libcxx/include/numbers b/libcxx/include/numbers index f48ba4baf38ffd07b32a29f59cbd0bd45860ee0e..191563c3d8a5ffc77eb6c0ffe4fc5c223cc1933e 100644 --- a/libcxx/include/numbers +++ b/libcxx/include/numbers @@ -158,6 +158,7 @@ _LIBCPP_END_NAMESPACE_STD #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include +# include # include #endif diff --git a/libcxx/include/semaphore b/libcxx/include/semaphore index bf6317c587e2f9768acd0c6c038d8077ade4a5a9..98122c96459a2944868c3b5f2e15f4fd7998380c 100644 --- a/libcxx/include/semaphore +++ b/libcxx/include/semaphore @@ -54,10 +54,10 @@ using binary_semaphore = counting_semaphore<1>; // since C++20 # include <__atomic/atomic_sync.h> # include <__atomic/memory_order.h> # include <__chrono/time_point.h> +# include <__cstddef/ptrdiff_t.h> # include <__thread/poll_with_backoff.h> # include <__thread/support.h> # include <__thread/timed_backoff_policy.h> -# include # include # include @@ -181,6 +181,7 @@ _LIBCPP_POP_MACROS #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 # include +# include #endif #endif // _LIBCPP_SEMAPHORE diff --git a/libcxx/include/span b/libcxx/include/span index a32f7a372e2ae1f08e4b61b5fe3fe30b135ea558..896a3cd890186c3050c91250f3d4ee94b804d030 100644 --- a/libcxx/include/span +++ b/libcxx/include/span @@ -148,6 +148,8 @@ template #include <__concepts/convertible_to.h> #include <__concepts/equality_comparable.h> #include <__config> +#include <__cstddef/byte.h> +#include <__cstddef/ptrdiff_t.h> #include <__fwd/array.h> #include <__fwd/span.h> #include <__iterator/bounded_iter.h> @@ -173,7 +175,6 @@ template #include <__type_traits/remove_reference.h> #include <__type_traits/type_identity.h> #include <__utility/forward.h> -#include // for byte #include #include #include diff --git a/libcxx/include/stdexcept b/libcxx/include/stdexcept index daa7b501a86999b3bf80dfb2d04986c864ee28de..8415d3339f7e3a8913cb48882f0ff33e7a0ef408 100644 --- a/libcxx/include/stdexcept +++ b/libcxx/include/stdexcept @@ -278,6 +278,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD _LIBCPP_END_NAMESPACE_STD #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include # include diff --git a/libcxx/include/stop_token b/libcxx/include/stop_token index d4e651d9541f4ed239228a55d706811a9e105396..cf8d0cf9b91916962b2a8ff9022609ec91d65e2b 100644 --- a/libcxx/include/stop_token +++ b/libcxx/include/stop_token @@ -50,6 +50,7 @@ namespace std { #endif // !defined(_LIBCPP_HAS_NO_THREADS) #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include #endif diff --git a/libcxx/include/string_view b/libcxx/include/string_view index 5beac404fb5b54f51b947bde5cbcde9f8825f182..0edda7aeb1a77c8a687a4d45aef2d4bfa3d59433 100644 --- a/libcxx/include/string_view +++ b/libcxx/include/string_view @@ -208,6 +208,8 @@ namespace std { #include <__algorithm/min.h> #include <__assert> #include <__config> +#include <__cstddef/ptrdiff_t.h> +#include <__cstddef/size_t.h> #include <__functional/hash.h> #include <__functional/unary_function.h> #include <__fwd/ostream.h> @@ -233,7 +235,6 @@ namespace std { #include <__type_traits/remove_cvref.h> #include <__type_traits/remove_reference.h> #include <__type_traits/type_identity.h> -#include #include #include #include diff --git a/libcxx/include/tgmath.h b/libcxx/include/tgmath.h index e6f0a4ab2611fa8f8105396741d42b0c3a29031a..1c5058cb065a91c99320517d6cbaa6b7b4ebbd66 100644 --- a/libcxx/include/tgmath.h +++ b/libcxx/include/tgmath.h @@ -24,7 +24,8 @@ #endif #ifdef __cplusplus -# include +# include +# include #else # if __has_include_next() # include_next diff --git a/libcxx/include/tuple b/libcxx/include/tuple index e7e14b8d12d42a43e55f3a681c0fe6f2f86faa06..c3f7b8041686d1e6b061867686502ab8a30959e7 100644 --- a/libcxx/include/tuple +++ b/libcxx/include/tuple @@ -214,6 +214,7 @@ template #include <__compare/ordering.h> #include <__compare/synth_three_way.h> #include <__config> +#include <__cstddef/size_t.h> #include <__fwd/array.h> #include <__fwd/pair.h> #include <__fwd/tuple.h> @@ -262,7 +263,6 @@ template #include <__utility/move.h> #include <__utility/piecewise_construct.h> #include <__utility/swap.h> -#include #include // standard-mandated includes @@ -1411,6 +1411,7 @@ _LIBCPP_POP_MACROS // clang-format on #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include # include diff --git a/libcxx/include/typeindex b/libcxx/include/typeindex index 6398aa40d616a7656571737f79bc29fb8ee68d18..9f8e65befcba41d36b8797c680dc736b11c40a95 100644 --- a/libcxx/include/typeindex +++ b/libcxx/include/typeindex @@ -98,6 +98,7 @@ struct _LIBCPP_TEMPLATE_VIS hash : public __unary_function # include # include # include diff --git a/libcxx/include/typeinfo b/libcxx/include/typeinfo index 252afe59a0aa6d5861142a2fd53171c98edd33cf..28713077c688c1d7005337d790323a173bbad635 100644 --- a/libcxx/include/typeinfo +++ b/libcxx/include/typeinfo @@ -57,12 +57,13 @@ public: */ #include <__config> +#include <__cstddef/size_t.h> #include <__exception/exception.h> #include <__type_traits/integral_constant.h> #include <__type_traits/is_constant_evaluated.h> #include <__verbose_abort> -#include #include +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -383,6 +384,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD _LIBCPP_END_NAMESPACE_STD #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include #endif diff --git a/libcxx/include/utility b/libcxx/include/utility index f97907fbf72e9d40ea54ecfb60ffca8729a86d61..138cc3ba31893e7543f28e7c37a3f4e01f3c4f73 100644 --- a/libcxx/include/utility +++ b/libcxx/include/utility @@ -301,6 +301,7 @@ template #endif #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include # include diff --git a/libcxx/include/valarray b/libcxx/include/valarray index b3b48958f92bd76ff5a7cbf930428888fca209ae..2f7a1a7c5b49e33ac85544345a67afe223c27240 100644 --- a/libcxx/include/valarray +++ b/libcxx/include/valarray @@ -352,6 +352,7 @@ template unspecified2 end(const valarray& v); #include <__algorithm/unwrap_iter.h> #include <__assert> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__functional/operations.h> #include <__memory/addressof.h> #include <__memory/allocator.h> @@ -361,7 +362,6 @@ template unspecified2 end(const valarray& v); #include <__utility/move.h> #include <__utility/swap.h> #include -#include #include #include diff --git a/libcxx/include/variant b/libcxx/include/variant index 2e158a4eea31457e43493dcc22521ba26b009207..ee80fb0b5ab5bedf42618b4a776c85ec26c7725b 100644 --- a/libcxx/include/variant +++ b/libcxx/include/variant @@ -1631,6 +1631,7 @@ _LIBCPP_END_NAMESPACE_STD _LIBCPP_POP_MACROS #if !defined(_LIBCPP_REMOVE_TRANSITIVE_INCLUDES) && _LIBCPP_STD_VER <= 20 +# include # include # include # include diff --git a/libcxx/src/algorithm.cpp b/libcxx/src/algorithm.cpp index af9d60a8e271e84f56fe4a2f1f2e8cbc7af5d958..a7c39b5e5183a4da4afe199ea3d233e97c2cbdbf 100644 --- a/libcxx/src/algorithm.cpp +++ b/libcxx/src/algorithm.cpp @@ -21,8 +21,7 @@ void __sort(RandomAccessIterator first, RandomAccessIterator last, Comp comp) { std::__introsort<_ClassicAlgPolicy, ranges::less, RandomAccessIterator, - __use_branchless_sort::value>( - first, last, ranges::less{}, depth_limit); + __use_branchless_sort>(first, last, ranges::less{}, depth_limit); } // clang-format off diff --git a/libcxx/src/memory_resource.cpp b/libcxx/src/memory_resource.cpp index 299f810948fd14348aacef0ff8a98d39e2b0706e..3d0d4ead1be74c13f59a99dda29dba01bb1905ab 100644 --- a/libcxx/src/memory_resource.cpp +++ b/libcxx/src/memory_resource.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include #include #include diff --git a/libcxx/test/libcxx/algorithms/alg.modifying.operations/alg.random.shuffle/random_shuffle.cxx1z.pass.cpp b/libcxx/test/libcxx/algorithms/alg.modifying.operations/alg.random.shuffle/random_shuffle.cxx1z.pass.cpp index c1acc100a66098fbb30d283f7d992dfd13c7b364..4e51014f20b18b6466c4fbdd1d83b63afd6f3185 100644 --- a/libcxx/test/libcxx/algorithms/alg.modifying.operations/alg.random.shuffle/random_shuffle.cxx1z.pass.cpp +++ b/libcxx/test/libcxx/algorithms/alg.modifying.operations/alg.random.shuffle/random_shuffle.cxx1z.pass.cpp @@ -26,6 +26,7 @@ // ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include +#include #include #include "test_macros.h" diff --git a/libcxx/test/libcxx/algorithms/alg.modifying.operations/copy_move_unwrap_reverse.pass.cpp b/libcxx/test/libcxx/algorithms/alg.modifying.operations/copy_move_unwrap_reverse.pass.cpp index f295b807864ead8cfe7f37a977784a33300bd4c7..2a85e7b5ddcc37f66ce3c2eeec320988d74481e9 100644 --- a/libcxx/test/libcxx/algorithms/alg.modifying.operations/copy_move_unwrap_reverse.pass.cpp +++ b/libcxx/test/libcxx/algorithms/alg.modifying.operations/copy_move_unwrap_reverse.pass.cpp @@ -15,9 +15,9 @@ #include #include +#include #include #include -#include #include #include "test_iterators.h" diff --git a/libcxx/test/libcxx/algorithms/robust_against_using_non_transparent_comparators.pass.cpp b/libcxx/test/libcxx/algorithms/robust_against_using_non_transparent_comparators.pass.cpp index eaa5d44385be638ba7317b1470fd89266579b4ee..39870ebe7ff02db7b2f83776fc4be240bf1c129e 100644 --- a/libcxx/test/libcxx/algorithms/robust_against_using_non_transparent_comparators.pass.cpp +++ b/libcxx/test/libcxx/algorithms/robust_against_using_non_transparent_comparators.pass.cpp @@ -8,6 +8,7 @@ #include #include +#include #include #include "test_macros.h" diff --git a/libcxx/test/libcxx/assertions/modes/enabling_assertions_enables_extensive_mode.pass.cpp b/libcxx/test/libcxx/assertions/modes/enabling_assertions_enables_extensive_mode.pass.cpp deleted file mode 100644 index c496fc32dc939f381b37846157be89687313ab84..0000000000000000000000000000000000000000 --- a/libcxx/test/libcxx/assertions/modes/enabling_assertions_enables_extensive_mode.pass.cpp +++ /dev/null @@ -1,35 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// TODO(hardening): remove in LLVM 20. -// This test ensures that enabling assertions with the legacy `_LIBCPP_ENABLE_ASSERTIONS` now enables the extensive -// hardening mode. - -// `check_assertion.h` is only available starting from C++11 and requires Unix headers and regex support. -// REQUIRES: has-unix-headers -// UNSUPPORTED: c++03, no-localization -// The ability to set a custom abort message is required to compare the assertion message (which only happens in the -// debug mode). -// XFAIL: libcpp-hardening-mode=debug && availability-verbose_abort-missing -// HWASAN replaces TRAP with abort or error exit code. -// XFAIL: hwasan -// Note that GCC doesn't support `-Wno-macro-redefined`. -// ADDITIONAL_COMPILE_FLAGS: -U_LIBCPP_HARDENING_MODE -D_LIBCPP_ENABLE_ASSERTIONS=1 -Wno-#warnings -Wno-cpp - -#include -#include "check_assertion.h" - -int main(int, char**) { - static_assert(_LIBCPP_HARDENING_MODE == _LIBCPP_HARDENING_MODE_EXTENSIVE, - "The extensive hardening mode should be implicitly enabled"); - - _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(true, "Should not fire"); - TEST_LIBCPP_ASSERT_FAILURE([] { _LIBCPP_ASSERT_VALID_ELEMENT_ACCESS(false, "Should fire"); }(), "Should fire"); - - return 0; -} diff --git a/libcxx/test/libcxx/clang_modules_include.gen.py b/libcxx/test/libcxx/clang_modules_include.gen.py index bc028f2a0809aa01afbfd2321122d3ee0e9f8f68..b897984f898819fdd9515d525e5f424248455477 100644 --- a/libcxx/test/libcxx/clang_modules_include.gen.py +++ b/libcxx/test/libcxx/clang_modules_include.gen.py @@ -17,10 +17,15 @@ import sys sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: - print(f"""\ + print( + f"""\ //--- {header}.compile.pass.cpp // RUN: %{{cxx}} %s %{{flags}} %{{compile_flags}} -fmodules -fcxx-modules -fmodules-cache-path=%t -fsyntax-only @@ -41,9 +46,11 @@ for header in public_headers: // UNSUPPORTED: LIBCXX-PICOLIBC-FIXME {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #include <{header}> -""") +""" + ) print( f"""\ diff --git a/libcxx/test/libcxx/containers/sequences/deque/asan_turning_off.pass.cpp b/libcxx/test/libcxx/containers/sequences/deque/asan_turning_off.pass.cpp index e9b9cde64ee91ad2edee015331c4bd4714a7e638..b31775a873481d75fff91302b08d9cf834c63475 100644 --- a/libcxx/test/libcxx/containers/sequences/deque/asan_turning_off.pass.cpp +++ b/libcxx/test/libcxx/containers/sequences/deque/asan_turning_off.pass.cpp @@ -17,6 +17,7 @@ // This test confirms that those allocators work after turning off annotations. #include +#include #include #include diff --git a/libcxx/test/libcxx/double_include.gen.py b/libcxx/test/libcxx/double_include.gen.py index afc2947dbece94d2308c932f33b4c31c7cfc8918..f58e72f94a353353ee5ed6bd4e6206c1e1d16d98 100644 --- a/libcxx/test/libcxx/double_include.gen.py +++ b/libcxx/test/libcxx/double_include.gen.py @@ -15,12 +15,18 @@ import sys sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: - print(f"""\ + print( + f"""\ //--- {header}.sh.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} // RUN: %{{cxx}} -c %s -o %t.first.o %{{flags}} %{{compile_flags}} // RUN: %{{cxx}} -c %s -o %t.second.o -DWITH_MAIN %{{flags}} %{{compile_flags}} @@ -32,4 +38,5 @@ for header in public_headers: #if defined(WITH_MAIN) int main(int, char**) {{ return 0; }} #endif -""") +""" + ) diff --git a/libcxx/test/libcxx/header_inclusions.gen.py b/libcxx/test/libcxx/header_inclusions.gen.py index e5def1ad4cb70d9c75d70d3a68d0fc841324e8da..739caf915c09a0c98d30d564decabd0204d46310 100644 --- a/libcxx/test/libcxx/header_inclusions.gen.py +++ b/libcxx/test/libcxx/header_inclusions.gen.py @@ -12,32 +12,43 @@ # RUN: %{python} %s %{libcxx-dir}/utils import sys + sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers, mandatory_inclusions +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, + mandatory_inclusions, +) for header in public_headers: - header_guard = lambda h: f"_LIBCPP_{str(h).upper().replace('.', '_').replace('/', '_')}" + header_guard = ( + lambda h: f"_LIBCPP_{str(h).upper().replace('.', '_').replace('/', '_')}" + ) - # has no header guards - if header == 'cassert': - checks = '' - else: - checks = f''' + # has no header guards + if header == "cassert": + checks = "" + else: + checks = f""" #ifndef {header_guard(header)} # error <{header}> was expected to define a header guard {header_guard(header)} #endif -''' - for includee in mandatory_inclusions.get(header, []): - checks += f''' +""" + for includee in mandatory_inclusions.get(header, []): + checks += f""" #ifndef {header_guard(includee)} # error <{header}> was expected to include <{includee}> #endif -''' +""" - print(f"""\ + print( + f"""\ //--- {header}.compile.pass.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #include <{header}> {checks} -""") +""" + ) diff --git a/libcxx/test/libcxx/include_as_c.sh.cpp b/libcxx/test/libcxx/include_as_c.sh.cpp index c9f8dfd9a5a92226353c2e5a15386589f07f52b7..204b830462cf94425efbee4740ad391f82418012 100644 --- a/libcxx/test/libcxx/include_as_c.sh.cpp +++ b/libcxx/test/libcxx/include_as_c.sh.cpp @@ -34,6 +34,7 @@ #endif #include #include +#include #include #include #include diff --git a/libcxx/test/libcxx/libcpp_version.gen.py b/libcxx/test/libcxx/libcpp_version.gen.py index a9995295e21e4f461757e1d8a0c8a959fec306d8..b30623fe2c388bc1b63b0c759d7435aeb418c95d 100644 --- a/libcxx/test/libcxx/libcpp_version.gen.py +++ b/libcxx/test/libcxx/libcpp_version.gen.py @@ -12,16 +12,23 @@ import sys sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: - print(f"""\ + print( + f"""\ //--- {header}.compile.pass.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #include <{header}> #ifndef _LIBCPP_VERSION # error <{header}> does not seem to define _LIBCPP_VERSION #endif -""") +""" + ) diff --git a/libcxx/test/libcxx/no_assert_include.gen.py b/libcxx/test/libcxx/no_assert_include.gen.py index 67ab98603ca8fde7a3d377fe43d473ef195b6b1b..e0dbc3d815f31b1ef93f3a22dcc28db601f0d171 100644 --- a/libcxx/test/libcxx/no_assert_include.gen.py +++ b/libcxx/test/libcxx/no_assert_include.gen.py @@ -12,20 +12,28 @@ # RUN: %{python} %s %{libcxx-dir}/utils import sys + sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: - if header == 'cassert': - continue + if header == "cassert": + continue - print(f"""\ + print( + f"""\ //--- {header}.compile.pass.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #include <{header}> #ifdef assert # error "Do not include cassert or assert.h in standard header files" #endif -""") +""" + ) diff --git a/libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp b/libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..1c790c283e43876f9ecac619e4484e03247e9e72 --- /dev/null +++ b/libcxx/test/libcxx/numerics/complex.number/cmplx.over.pow.pass.cpp @@ -0,0 +1,84 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// template complex<__promote::type> pow(const complex&, const U&); +// template complex<__promote::type> pow(const complex&, const complex&); +// template complex<__promote::type> pow(const T&, const complex&); + +// Test that these additional overloads are free from catching std::complex, +// which is expected by several 3rd party libraries, see https://github.com/llvm/llvm-project/issues/109858. +// +// Note that we reserve the right to break this in the future if we have a reason to, but for the time being, +// make sure we don't break this property unintentionally. +#include +#include +#include +#include + +#include "test_macros.h" + +namespace usr { +struct usr_tag {}; + +template +typename std::enable_if<(std::is_same::value && std::is_floating_point::value) || + (std::is_floating_point::value && std::is_same::value), + int>::type +pow(const T&, const std::complex&) { + return std::is_same::value ? 0 : 1; +} + +template +typename std::enable_if<(std::is_same::value && std::is_floating_point::value) || + (std::is_floating_point::value && std::is_same::value), + int>::type +pow(const std::complex&, const U&) { + return std::is_same::value ? 2 : 3; +} + +template +typename std::enable_if<(std::is_same::value && std::is_floating_point::value) || + (std::is_floating_point::value && std::is_same::value), + int>::type +pow(const std::complex&, const std::complex&) { + return std::is_same::value ? 4 : 5; +} +} // namespace usr + +int main(int, char**) { + using std::pow; + using usr::pow; + + usr::usr_tag tag; + const std::complex ctag; + + assert(pow(tag, std::complex(1.0f)) == 0); + assert(pow(std::complex(1.0f), tag) == 2); + assert(pow(tag, std::complex(1.0)) == 0); + assert(pow(std::complex(1.0), tag) == 2); + assert(pow(tag, std::complex(1.0l)) == 0); + assert(pow(std::complex(1.0l), tag) == 2); + + assert(pow(1.0f, ctag) == 1); + assert(pow(ctag, 1.0f) == 3); + assert(pow(1.0, ctag) == 1); + assert(pow(ctag, 1.0) == 3); + assert(pow(1.0l, ctag) == 1); + assert(pow(ctag, 1.0l) == 3); + + assert(pow(ctag, std::complex(1.0f)) == 4); + assert(pow(std::complex(1.0f), ctag) == 5); + assert(pow(ctag, std::complex(1.0)) == 4); + assert(pow(std::complex(1.0), ctag) == 5); + assert(pow(ctag, std::complex(1.0l)) == 4); + assert(pow(std::complex(1.0l), ctag) == 5); + + return 0; +} diff --git a/libcxx/test/libcxx/system_reserved_names.gen.py b/libcxx/test/libcxx/system_reserved_names.gen.py index e29e7a2cdd61449f2fe4ee605ee05c601278333d..f01126249c881714c453828b3746bf44ae04a889 100644 --- a/libcxx/test/libcxx/system_reserved_names.gen.py +++ b/libcxx/test/libcxx/system_reserved_names.gen.py @@ -13,14 +13,20 @@ # RUN: %{python} %s %{libcxx-dir}/utils import sys + sys.path.append(sys.argv[1]) -from libcxx.header_information import lit_header_restrictions, public_headers +from libcxx.header_information import ( + lit_header_restrictions, + lit_header_undeprecations, + public_headers, +) for header in public_headers: print( f"""\ //--- {header}.compile.pass.cpp {lit_header_restrictions.get(header, '')} +{lit_header_undeprecations.get(header, '')} #define SYSTEM_RESERVED_NAME This name should not be used in libc++ diff --git a/libcxx/test/libcxx/transitive_includes.gen.py b/libcxx/test/libcxx/transitive_includes.gen.py index 2693617bcb0e5b4cedb043d525cbd988c25cb133..f01dbac26a8e8aeb82744e2f70cde3cd6995e270 100644 --- a/libcxx/test/libcxx/transitive_includes.gen.py +++ b/libcxx/test/libcxx/transitive_includes.gen.py @@ -73,7 +73,7 @@ else: {lit_header_restrictions.get(header, '')} // TODO: Fix this test to make it work with localization or wide characters disabled -// UNSUPPORTED: no-localization, no-wide-characters, no-threads, no-filesystem, libcpp-has-no-experimental-tzdb, no-tzdb +// UNSUPPORTED: no-localization, no-wide-characters, no-threads, no-filesystem, libcpp-has-no-experimental-tzdb // When built with modules, this test doesn't work because --trace-includes doesn't // report the stack of includes correctly. diff --git a/libcxx/test/libcxx/transitive_includes/cxx03.csv b/libcxx/test/libcxx/transitive_includes/cxx03.csv index 2dc84963f0891eea6a9f6c40bf9e1e5b675fa5e8..ae4254183fc84e95d84a18ec081685846a531527 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx03.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx03.csv @@ -7,6 +7,7 @@ algorithm compare algorithm concepts algorithm cstddef algorithm cstdint +algorithm cstdio algorithm cstdlib algorithm cstring algorithm ctime @@ -86,6 +87,7 @@ array compare array concepts array cstddef array cstdint +array cstdio array cstdlib array cstring array ctime @@ -458,7 +460,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits @@ -1182,13 +1183,17 @@ istream utility istream variant istream vector istream version +iterator cctype iterator cmath iterator compare iterator concepts iterator cstddef iterator cstdint +iterator cstdio iterator cstdlib iterator cstring +iterator cwchar +iterator cwctype iterator exception iterator initializer_list iterator iosfwd @@ -1398,15 +1403,19 @@ mdspan variant mdspan vector mdspan version memory atomic +memory cctype memory climits memory cmath memory compare memory concepts memory cstddef memory cstdint +memory cstdio memory cstdlib memory cstring memory ctime +memory cwchar +memory cwctype memory exception memory initializer_list memory iosfwd @@ -1552,15 +1561,19 @@ numeric variant numeric vector numeric version optional atomic +optional cctype optional climits optional cmath optional compare optional concepts optional cstddef optional cstdint +optional cstdio optional cstdlib optional cstring optional ctime +optional cwchar +optional cwctype optional exception optional initializer_list optional iosfwd @@ -1872,15 +1885,19 @@ regex variant regex vector regex version scoped_allocator atomic +scoped_allocator cctype scoped_allocator climits scoped_allocator cmath scoped_allocator compare scoped_allocator concepts scoped_allocator cstddef scoped_allocator cstdint +scoped_allocator cstdio scoped_allocator cstdlib scoped_allocator cstring scoped_allocator ctime +scoped_allocator cwchar +scoped_allocator cwctype scoped_allocator exception scoped_allocator initializer_list scoped_allocator iosfwd @@ -2500,6 +2517,7 @@ unordered_map compare unordered_map concepts unordered_map cstddef unordered_map cstdint +unordered_map cstdio unordered_map cstdlib unordered_map cstring unordered_map ctime diff --git a/libcxx/test/libcxx/transitive_includes/cxx11.csv b/libcxx/test/libcxx/transitive_includes/cxx11.csv index 2dc84963f0891eea6a9f6c40bf9e1e5b675fa5e8..ae4254183fc84e95d84a18ec081685846a531527 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx11.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx11.csv @@ -7,6 +7,7 @@ algorithm compare algorithm concepts algorithm cstddef algorithm cstdint +algorithm cstdio algorithm cstdlib algorithm cstring algorithm ctime @@ -86,6 +87,7 @@ array compare array concepts array cstddef array cstdint +array cstdio array cstdlib array cstring array ctime @@ -458,7 +460,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits @@ -1182,13 +1183,17 @@ istream utility istream variant istream vector istream version +iterator cctype iterator cmath iterator compare iterator concepts iterator cstddef iterator cstdint +iterator cstdio iterator cstdlib iterator cstring +iterator cwchar +iterator cwctype iterator exception iterator initializer_list iterator iosfwd @@ -1398,15 +1403,19 @@ mdspan variant mdspan vector mdspan version memory atomic +memory cctype memory climits memory cmath memory compare memory concepts memory cstddef memory cstdint +memory cstdio memory cstdlib memory cstring memory ctime +memory cwchar +memory cwctype memory exception memory initializer_list memory iosfwd @@ -1552,15 +1561,19 @@ numeric variant numeric vector numeric version optional atomic +optional cctype optional climits optional cmath optional compare optional concepts optional cstddef optional cstdint +optional cstdio optional cstdlib optional cstring optional ctime +optional cwchar +optional cwctype optional exception optional initializer_list optional iosfwd @@ -1872,15 +1885,19 @@ regex variant regex vector regex version scoped_allocator atomic +scoped_allocator cctype scoped_allocator climits scoped_allocator cmath scoped_allocator compare scoped_allocator concepts scoped_allocator cstddef scoped_allocator cstdint +scoped_allocator cstdio scoped_allocator cstdlib scoped_allocator cstring scoped_allocator ctime +scoped_allocator cwchar +scoped_allocator cwctype scoped_allocator exception scoped_allocator initializer_list scoped_allocator iosfwd @@ -2500,6 +2517,7 @@ unordered_map compare unordered_map concepts unordered_map cstddef unordered_map cstdint +unordered_map cstdio unordered_map cstdlib unordered_map cstring unordered_map ctime diff --git a/libcxx/test/libcxx/transitive_includes/cxx14.csv b/libcxx/test/libcxx/transitive_includes/cxx14.csv index 27e229755735840c4d52a2ff02d16deaa613e801..f14b3170003705c9d6a5e5243000688a1d5d56da 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx14.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx14.csv @@ -7,6 +7,7 @@ algorithm compare algorithm concepts algorithm cstddef algorithm cstdint +algorithm cstdio algorithm cstdlib algorithm cstring algorithm ctime @@ -88,6 +89,7 @@ array compare array concepts array cstddef array cstdint +array cstdio array cstdlib array cstring array ctime @@ -467,7 +469,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits @@ -1210,13 +1211,17 @@ istream utility istream variant istream vector istream version +iterator cctype iterator cmath iterator compare iterator concepts iterator cstddef iterator cstdint +iterator cstdio iterator cstdlib iterator cstring +iterator cwchar +iterator cwctype iterator exception iterator initializer_list iterator iosfwd @@ -1430,15 +1435,19 @@ mdspan variant mdspan vector mdspan version memory atomic +memory cctype memory climits memory cmath memory compare memory concepts memory cstddef memory cstdint +memory cstdio memory cstdlib memory cstring memory ctime +memory cwchar +memory cwctype memory exception memory initializer_list memory iosfwd @@ -1586,15 +1595,19 @@ numeric variant numeric vector numeric version optional atomic +optional cctype optional climits optional cmath optional compare optional concepts optional cstddef optional cstdint +optional cstdio optional cstdlib optional cstring optional ctime +optional cwchar +optional cwctype optional exception optional initializer_list optional iosfwd @@ -1911,15 +1924,19 @@ regex variant regex vector regex version scoped_allocator atomic +scoped_allocator cctype scoped_allocator climits scoped_allocator cmath scoped_allocator compare scoped_allocator concepts scoped_allocator cstddef scoped_allocator cstdint +scoped_allocator cstdio scoped_allocator cstdlib scoped_allocator cstring scoped_allocator ctime +scoped_allocator cwchar +scoped_allocator cwctype scoped_allocator exception scoped_allocator initializer_list scoped_allocator iosfwd @@ -2551,6 +2568,7 @@ unordered_map compare unordered_map concepts unordered_map cstddef unordered_map cstdint +unordered_map cstdio unordered_map cstdlib unordered_map cstring unordered_map ctime diff --git a/libcxx/test/libcxx/transitive_includes/cxx17.csv b/libcxx/test/libcxx/transitive_includes/cxx17.csv index b17eb1f2347a86c2e07a1f181ea3cd7edf1035be..d4bc0a38c1643956f981827a706d5469b298877a 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx17.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx17.csv @@ -7,6 +7,7 @@ algorithm compare algorithm concepts algorithm cstddef algorithm cstdint +algorithm cstdio algorithm cstdlib algorithm cstring algorithm ctime @@ -86,6 +87,7 @@ array compare array concepts array cstddef array cstdint +array cstdio array cstdlib array cstring array ctime @@ -458,7 +460,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits @@ -1206,13 +1207,17 @@ istream utility istream variant istream vector istream version +iterator cctype iterator cmath iterator compare iterator concepts iterator cstddef iterator cstdint +iterator cstdio iterator cstdlib iterator cstring +iterator cwchar +iterator cwctype iterator exception iterator initializer_list iterator iosfwd @@ -1422,15 +1427,19 @@ mdspan variant mdspan vector mdspan version memory atomic +memory cctype memory climits memory cmath memory compare memory concepts memory cstddef memory cstdint +memory cstdio memory cstdlib memory cstring memory ctime +memory cwchar +memory cwctype memory exception memory initializer_list memory iosfwd @@ -1576,15 +1585,19 @@ numeric variant numeric vector numeric version optional atomic +optional cctype optional climits optional cmath optional compare optional concepts optional cstddef optional cstdint +optional cstdio optional cstdlib optional cstring optional ctime +optional cwchar +optional cwctype optional exception optional initializer_list optional iosfwd @@ -1896,15 +1909,19 @@ regex variant regex vector regex version scoped_allocator atomic +scoped_allocator cctype scoped_allocator climits scoped_allocator cmath scoped_allocator compare scoped_allocator concepts scoped_allocator cstddef scoped_allocator cstdint +scoped_allocator cstdio scoped_allocator cstdlib scoped_allocator cstring scoped_allocator ctime +scoped_allocator cwchar +scoped_allocator cwctype scoped_allocator exception scoped_allocator initializer_list scoped_allocator iosfwd @@ -2524,6 +2541,7 @@ unordered_map compare unordered_map concepts unordered_map cstddef unordered_map cstdint +unordered_map cstdio unordered_map cstdlib unordered_map cstring unordered_map ctime diff --git a/libcxx/test/libcxx/transitive_includes/cxx20.csv b/libcxx/test/libcxx/transitive_includes/cxx20.csv index 9efec327889c1debf775408f81f434dcf4231d0e..304166547abf32ca0080d6b9ca57eadc843b449b 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx20.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx20.csv @@ -7,6 +7,7 @@ algorithm compare algorithm concepts algorithm cstddef algorithm cstdint +algorithm cstdio algorithm cstdlib algorithm cstring algorithm ctime @@ -29,15 +30,19 @@ algorithm utility algorithm variant algorithm version any atomic +any cctype any climits any cmath any compare any concepts any cstddef any cstdint +any cstdio any cstdlib any cstring any ctime +any cwchar +any cwctype any exception any initializer_list any iosfwd @@ -63,6 +68,7 @@ array compare array concepts array cstddef array cstdint +array cstdio array cstdlib array cstring array ctime @@ -97,15 +103,19 @@ atomic ratio atomic type_traits atomic version barrier atomic +barrier cctype barrier climits barrier cmath barrier compare barrier concepts barrier cstddef barrier cstdint +barrier cstdio barrier cstdlib barrier cstring barrier ctime +barrier cwchar +barrier cwctype barrier exception barrier initializer_list barrier iosfwd @@ -446,7 +456,6 @@ ctgmath array ctgmath atomic ctgmath bit ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits @@ -1192,13 +1201,17 @@ istream utility istream variant istream vector istream version +iterator cctype iterator cmath iterator compare iterator concepts iterator cstddef iterator cstdint +iterator cstdio iterator cstdlib iterator cstring +iterator cwchar +iterator cwctype iterator exception iterator initializer_list iterator iosfwd @@ -1408,15 +1421,19 @@ mdspan variant mdspan vector mdspan version memory atomic +memory cctype memory climits memory cmath memory compare memory concepts memory cstddef memory cstdint +memory cstdio memory cstdlib memory cstring memory ctime +memory cwchar +memory cwctype memory exception memory initializer_list memory iosfwd @@ -1562,15 +1579,19 @@ numeric variant numeric vector numeric version optional atomic +optional cctype optional climits optional cmath optional compare optional concepts optional cstddef optional cstdint +optional cstdio optional cstdlib optional cstring optional ctime +optional cwchar +optional cwctype optional exception optional initializer_list optional iosfwd @@ -1882,15 +1903,19 @@ regex variant regex vector regex version scoped_allocator atomic +scoped_allocator cctype scoped_allocator climits scoped_allocator cmath scoped_allocator compare scoped_allocator concepts scoped_allocator cstddef scoped_allocator cstdint +scoped_allocator cstdio scoped_allocator cstdlib scoped_allocator cstring scoped_allocator ctime +scoped_allocator cwchar +scoped_allocator cwctype scoped_allocator exception scoped_allocator initializer_list scoped_allocator iosfwd @@ -2520,6 +2545,7 @@ unordered_map compare unordered_map concepts unordered_map cstddef unordered_map cstdint +unordered_map cstdio unordered_map cstdlib unordered_map cstring unordered_map ctime diff --git a/libcxx/test/libcxx/transitive_includes/cxx23.csv b/libcxx/test/libcxx/transitive_includes/cxx23.csv index e17f732663a9b28c7ee7ae352ec0f5b91b5ab7cf..48d4425c0333ffc36c8e3034b0b7f2d36e8fa6e7 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx23.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx23.csv @@ -1,7 +1,6 @@ algorithm cctype algorithm climits algorithm compare -algorithm cstddef algorithm cstdint algorithm cstring algorithm ctime @@ -15,7 +14,6 @@ algorithm optional algorithm ratio algorithm tuple algorithm version -any cstddef any cstdint any cstring any initializer_list @@ -25,7 +23,6 @@ any typeinfo any version array cctype array compare -array cstddef array cstdint array cwchar array cwctype @@ -35,7 +32,6 @@ array new array stdexcept array version atomic climits -atomic cstddef atomic cstdint atomic cstring atomic ctime @@ -43,7 +39,6 @@ atomic limits atomic ratio atomic version barrier climits -barrier cstddef barrier cstdint barrier cstring barrier ctime @@ -57,7 +52,6 @@ bit version bitset cctype bitset climits bitset compare -bitset cstddef bitset cstdint bitset cstdio bitset cstring @@ -105,7 +99,6 @@ ccomplex tuple ccomplex typeinfo ccomplex version charconv cerrno -charconv cstddef charconv cstdint charconv initializer_list charconv limits @@ -170,7 +163,6 @@ codecvt string_view codecvt tuple codecvt typeinfo codecvt version -compare cstddef compare cstdint compare limits compare version @@ -205,14 +197,12 @@ complex string_view complex tuple complex typeinfo complex version -concepts cstddef concepts version condition_variable atomic condition_variable cctype condition_variable cerrno condition_variable climits condition_variable compare -condition_variable cstddef condition_variable cstdint condition_variable cstdio condition_variable cstring @@ -231,14 +221,12 @@ condition_variable tuple condition_variable typeinfo condition_variable version coroutine compare -coroutine cstddef coroutine cstdint coroutine cstring coroutine limits coroutine version cstddef version ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits @@ -275,7 +263,6 @@ cwchar cwctype cwctype cctype deque cctype deque compare -deque cstddef deque cstdint deque cstring deque cwchar @@ -286,14 +273,12 @@ deque new deque stdexcept deque tuple deque version -exception cstddef exception cstdint exception cstdlib exception new exception typeinfo exception version execution version -expected cstddef expected cstdint expected initializer_list expected new @@ -329,23 +314,18 @@ experimental/iterator tuple experimental/iterator typeinfo experimental/iterator variant experimental/iterator version -experimental/memory cstddef experimental/memory cstdint experimental/memory cstring experimental/memory version -experimental/propagate_const cstddef experimental/propagate_const version -experimental/simd cstddef experimental/simd cstdint experimental/simd limits experimental/simd version -experimental/type_traits cstddef experimental/type_traits cstdint experimental/type_traits initializer_list experimental/type_traits type_traits experimental/type_traits version experimental/utility compare -experimental/utility cstddef experimental/utility cstdint experimental/utility initializer_list experimental/utility limits @@ -433,7 +413,6 @@ format typeinfo format version forward_list cctype forward_list compare -forward_list cstddef forward_list cstdint forward_list cwchar forward_list cwctype @@ -482,7 +461,6 @@ fstream version functional array functional cctype functional compare -functional cstddef functional cstdint functional cstring functional cwchar @@ -530,7 +508,6 @@ future thread future tuple future typeinfo future version -initializer_list cstddef initializer_list version iomanip bitset iomanip cctype @@ -649,11 +626,14 @@ istream string_view istream tuple istream typeinfo istream version +iterator cctype iterator compare iterator concepts -iterator cstddef iterator cstdint +iterator cstdio iterator cstring +iterator cwchar +iterator cwctype iterator initializer_list iterator iosfwd iterator limits @@ -661,7 +641,6 @@ iterator new iterator variant iterator version latch climits -latch cstddef latch cstdint latch cstring latch ctime @@ -671,7 +650,6 @@ latch version limits version list cctype list compare -list cstddef list cstdint list cstring list cwchar @@ -709,7 +687,6 @@ locale typeinfo locale version map cctype map compare -map cstddef map cstdint map cstring map cwchar @@ -723,10 +700,8 @@ map tuple map version mdspan array mdspan cctype -mdspan cinttypes mdspan compare mdspan concepts -mdspan cstddef mdspan cstdint mdspan cwchar mdspan cwctype @@ -737,7 +712,6 @@ mdspan span mdspan stdexcept mdspan version memory compare -memory cstddef memory cstdint memory cstring memory initializer_list @@ -750,7 +724,6 @@ memory_resource cctype memory_resource cerrno memory_resource climits memory_resource compare -memory_resource cstddef memory_resource cstdint memory_resource cstdio memory_resource cstring @@ -773,7 +746,6 @@ mutex cctype mutex cerrno mutex climits mutex compare -mutex cstddef mutex cstdint mutex cstdio mutex cstring @@ -791,12 +763,10 @@ mutex string_view mutex tuple mutex typeinfo mutex version -new cstddef new version numbers version numeric climits numeric compare -numeric cstddef numeric cstdint numeric cstring numeric ctime @@ -808,7 +778,6 @@ numeric ratio numeric tuple numeric version optional compare -optional cstddef optional cstdint optional cstring optional initializer_list @@ -903,7 +872,6 @@ random cctype random climits random cmath random compare -random cstddef random cstdint random cstdio random cstring @@ -925,8 +893,8 @@ random version ranges cctype ranges compare ranges concepts -ranges cstddef ranges cstdint +ranges cstdio ranges cstring ranges cwchar ranges cwctype @@ -970,14 +938,12 @@ regex typeinfo regex vector regex version scoped_allocator compare -scoped_allocator cstddef scoped_allocator cstdint scoped_allocator limits scoped_allocator new scoped_allocator tuple scoped_allocator version semaphore climits -semaphore cstddef semaphore cstdint semaphore cstring semaphore ctime @@ -986,7 +952,6 @@ semaphore ratio semaphore version set cctype set compare -set cstddef set cstdint set cstring set cwchar @@ -1001,7 +966,6 @@ shared_mutex cctype shared_mutex cerrno shared_mutex climits shared_mutex compare -shared_mutex cstddef shared_mutex cstdint shared_mutex cstdio shared_mutex cstring @@ -1020,7 +984,6 @@ shared_mutex tuple shared_mutex version source_location cstdint source_location version -span cstddef span initializer_list span limits span stdexcept @@ -1056,7 +1019,6 @@ sstream typeinfo sstream version stack cctype stack compare -stack cstddef stack cstdint stack cstring stack cwchar @@ -1070,7 +1032,6 @@ stack tuple stack version stop_token atomic stop_token climits -stop_token cstddef stop_token cstdint stop_token cstring stop_token ctime @@ -1105,7 +1066,6 @@ streambuf version string cctype string climits string compare -string cstddef string cstdint string cstdio string cstring @@ -1121,7 +1081,6 @@ string tuple string version string_view cctype string_view compare -string_view cstddef string_view cstdint string_view cstdio string_view cstring @@ -1209,7 +1168,6 @@ system_error cctype system_error cerrno system_error climits system_error compare -system_error cstddef system_error cstdint system_error cstdio system_error cstring @@ -1257,23 +1215,19 @@ thread tuple thread typeinfo thread version tuple compare -tuple cstddef tuple cstdint tuple limits tuple version type_traits cstdint type_traits version typeindex compare -typeindex cstddef typeindex cstdint typeindex limits typeindex typeinfo typeindex version -typeinfo cstddef typeinfo cstdint typeinfo version unordered_map compare -unordered_map cstddef unordered_map cstdint unordered_map cstring unordered_map initializer_list @@ -1284,7 +1238,6 @@ unordered_map stdexcept unordered_map tuple unordered_map version unordered_set compare -unordered_set cstddef unordered_set cstdint unordered_set cstring unordered_set initializer_list @@ -1294,20 +1247,17 @@ unordered_set optional unordered_set tuple unordered_set version utility compare -utility cstddef utility cstdint utility initializer_list utility limits utility version valarray cmath -valarray cstddef valarray cstdint valarray initializer_list valarray limits valarray new valarray version variant compare -variant cstddef variant cstdint variant cstring variant initializer_list diff --git a/libcxx/test/libcxx/transitive_includes/cxx26.csv b/libcxx/test/libcxx/transitive_includes/cxx26.csv index c56f5cdfad00727a41dd1728cf84a7c655c94d98..944002f4974d0c09ff0e40e75c3f2a854ef71b15 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx26.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx26.csv @@ -1,7 +1,6 @@ algorithm cctype algorithm climits algorithm compare -algorithm cstddef algorithm cstdint algorithm cstring algorithm ctime @@ -15,7 +14,6 @@ algorithm optional algorithm ratio algorithm tuple algorithm version -any cstddef any cstdint any cstring any initializer_list @@ -25,7 +23,6 @@ any typeinfo any version array cctype array compare -array cstddef array cstdint array cwchar array cwctype @@ -35,7 +32,6 @@ array new array stdexcept array version atomic climits -atomic cstddef atomic cstdint atomic cstring atomic ctime @@ -43,7 +39,6 @@ atomic limits atomic ratio atomic version barrier climits -barrier cstddef barrier cstdint barrier cstring barrier ctime @@ -57,7 +52,6 @@ bit version bitset cctype bitset climits bitset compare -bitset cstddef bitset cstdint bitset cstdio bitset cstring @@ -105,7 +99,6 @@ ccomplex tuple ccomplex typeinfo ccomplex version charconv cerrno -charconv cstddef charconv cstdint charconv initializer_list charconv limits @@ -170,7 +163,6 @@ codecvt string_view codecvt tuple codecvt typeinfo codecvt version -compare cstddef compare cstdint compare limits compare version @@ -205,14 +197,12 @@ complex string_view complex tuple complex typeinfo complex version -concepts cstddef concepts version condition_variable atomic condition_variable cctype condition_variable cerrno condition_variable climits condition_variable compare -condition_variable cstddef condition_variable cstdint condition_variable cstdio condition_variable cstring @@ -231,14 +221,12 @@ condition_variable tuple condition_variable typeinfo condition_variable version coroutine compare -coroutine cstddef coroutine cstdint coroutine cstring coroutine limits coroutine version cstddef version ctgmath bitset -ctgmath ccomplex ctgmath cctype ctgmath cerrno ctgmath climits @@ -275,7 +263,6 @@ cwchar cwctype cwctype cctype deque cctype deque compare -deque cstddef deque cstdint deque cstring deque cwchar @@ -286,14 +273,12 @@ deque new deque stdexcept deque tuple deque version -exception cstddef exception cstdint exception cstdlib exception new exception typeinfo exception version execution version -expected cstddef expected cstdint expected initializer_list expected new @@ -329,23 +314,18 @@ experimental/iterator tuple experimental/iterator typeinfo experimental/iterator variant experimental/iterator version -experimental/memory cstddef experimental/memory cstdint experimental/memory cstring experimental/memory version -experimental/propagate_const cstddef experimental/propagate_const version -experimental/simd cstddef experimental/simd cstdint experimental/simd limits experimental/simd version -experimental/type_traits cstddef experimental/type_traits cstdint experimental/type_traits initializer_list experimental/type_traits type_traits experimental/type_traits version experimental/utility compare -experimental/utility cstddef experimental/utility cstdint experimental/utility initializer_list experimental/utility limits @@ -433,7 +413,6 @@ format typeinfo format version forward_list cctype forward_list compare -forward_list cstddef forward_list cstdint forward_list cwchar forward_list cwctype @@ -481,7 +460,6 @@ fstream version functional array functional cctype functional compare -functional cstddef functional cstdint functional cstring functional cwchar @@ -529,7 +507,6 @@ future thread future tuple future typeinfo future version -initializer_list cstddef initializer_list version iomanip bitset iomanip cctype @@ -648,11 +625,14 @@ istream string_view istream tuple istream typeinfo istream version +iterator cctype iterator compare iterator concepts -iterator cstddef iterator cstdint +iterator cstdio iterator cstring +iterator cwchar +iterator cwctype iterator initializer_list iterator iosfwd iterator limits @@ -660,7 +640,6 @@ iterator new iterator variant iterator version latch climits -latch cstddef latch cstdint latch cstring latch ctime @@ -670,7 +649,6 @@ latch version limits version list cctype list compare -list cstddef list cstdint list cstring list cwchar @@ -708,7 +686,6 @@ locale typeinfo locale version map cctype map compare -map cstddef map cstdint map cstring map cwchar @@ -722,10 +699,8 @@ map tuple map version mdspan array mdspan cctype -mdspan cinttypes mdspan compare mdspan concepts -mdspan cstddef mdspan cstdint mdspan cwchar mdspan cwctype @@ -736,7 +711,6 @@ mdspan span mdspan stdexcept mdspan version memory compare -memory cstddef memory cstdint memory cstring memory initializer_list @@ -749,7 +723,6 @@ memory_resource cctype memory_resource cerrno memory_resource climits memory_resource compare -memory_resource cstddef memory_resource cstdint memory_resource cstdio memory_resource cstring @@ -772,7 +745,6 @@ mutex cctype mutex cerrno mutex climits mutex compare -mutex cstddef mutex cstdint mutex cstdio mutex cstring @@ -790,12 +762,10 @@ mutex string_view mutex tuple mutex typeinfo mutex version -new cstddef new version numbers version numeric climits numeric compare -numeric cstddef numeric cstdint numeric cstring numeric ctime @@ -807,7 +777,6 @@ numeric ratio numeric tuple numeric version optional compare -optional cstddef optional cstdint optional cstring optional initializer_list @@ -902,7 +871,6 @@ random cctype random climits random cmath random compare -random cstddef random cstdint random cstdio random cstring @@ -924,8 +892,8 @@ random version ranges cctype ranges compare ranges concepts -ranges cstddef ranges cstdint +ranges cstdio ranges cstring ranges cwchar ranges cwctype @@ -969,14 +937,12 @@ regex typeinfo regex vector regex version scoped_allocator compare -scoped_allocator cstddef scoped_allocator cstdint scoped_allocator limits scoped_allocator new scoped_allocator tuple scoped_allocator version semaphore climits -semaphore cstddef semaphore cstdint semaphore cstring semaphore ctime @@ -985,7 +951,6 @@ semaphore ratio semaphore version set cctype set compare -set cstddef set cstdint set cstring set cwchar @@ -1000,7 +965,6 @@ shared_mutex cctype shared_mutex cerrno shared_mutex climits shared_mutex compare -shared_mutex cstddef shared_mutex cstdint shared_mutex cstdio shared_mutex cstring @@ -1019,7 +983,6 @@ shared_mutex tuple shared_mutex version source_location cstdint source_location version -span cstddef span initializer_list span limits span stdexcept @@ -1055,7 +1018,6 @@ sstream typeinfo sstream version stack cctype stack compare -stack cstddef stack cstdint stack cstring stack cwchar @@ -1069,7 +1031,6 @@ stack tuple stack version stop_token atomic stop_token climits -stop_token cstddef stop_token cstdint stop_token cstring stop_token ctime @@ -1104,7 +1065,6 @@ streambuf version string cctype string climits string compare -string cstddef string cstdint string cstdio string cstring @@ -1120,7 +1080,6 @@ string tuple string version string_view cctype string_view compare -string_view cstddef string_view cstdint string_view cstdio string_view cstring @@ -1208,7 +1167,6 @@ system_error cctype system_error cerrno system_error climits system_error compare -system_error cstddef system_error cstdint system_error cstdio system_error cstring @@ -1256,23 +1214,19 @@ thread tuple thread typeinfo thread version tuple compare -tuple cstddef tuple cstdint tuple limits tuple version type_traits cstdint type_traits version typeindex compare -typeindex cstddef typeindex cstdint typeindex limits typeindex typeinfo typeindex version -typeinfo cstddef typeinfo cstdint typeinfo version unordered_map compare -unordered_map cstddef unordered_map cstdint unordered_map cstring unordered_map initializer_list @@ -1283,7 +1237,6 @@ unordered_map stdexcept unordered_map tuple unordered_map version unordered_set compare -unordered_set cstddef unordered_set cstdint unordered_set cstring unordered_set initializer_list @@ -1293,20 +1246,17 @@ unordered_set optional unordered_set tuple unordered_set version utility compare -utility cstddef utility cstdint utility initializer_list utility limits utility version valarray cmath -valarray cstddef valarray cstdint valarray initializer_list valarray limits valarray new valarray version variant compare -variant cstddef variant cstdint variant cstring variant initializer_list diff --git a/libcxx/test/libcxx/utilities/template.bitset/includes.pass.cpp b/libcxx/test/libcxx/utilities/template.bitset/includes.pass.cpp index 42deaaa4b2d37ecb5f35c550df5c85d6781139d9..214b0eff8d9d2613cbfb3e0d4de03290e588ff4c 100644 --- a/libcxx/test/libcxx/utilities/template.bitset/includes.pass.cpp +++ b/libcxx/test/libcxx/utilities/template.bitset/includes.pass.cpp @@ -6,16 +6,12 @@ // //===----------------------------------------------------------------------===// -// test that includes , , and +// test that includes , and #include #include "test_macros.h" -#ifndef _LIBCPP_CSTDDEF -#error has not been included -#endif - #ifndef _LIBCPP_STRING #error has not been included #endif diff --git a/libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp b/libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp index 481d565961b2b5c14377395a4a8c4488fbd284e5..619dc7242a3660851de16c1b9cf8a122624bdad6 100644 --- a/libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp +++ b/libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/fill.pass.cpp @@ -16,6 +16,7 @@ #include #include #include +#include #include #include "test_macros.h" diff --git a/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp b/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp index 7654a4b0c7f007a5cc04157f3a184577daf5f405..7250c49a7ff952807394d6ddabda91427e62fe27 100644 --- a/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp +++ b/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/count.pass.cpp @@ -18,6 +18,7 @@ #include #include +#include #include #include "test_macros.h" diff --git a/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/ranges.count.pass.cpp b/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/ranges.count.pass.cpp index b6631add7e48a70a0f517e7419bd07c2caf0d32f..6030bed47ec6a76bb866cec6dd9ba14c72783589 100644 --- a/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/ranges.count.pass.cpp +++ b/libcxx/test/std/algorithms/alg.nonmodifying/alg.count/ranges.count.pass.cpp @@ -25,6 +25,7 @@ #include #include #include +#include #include #include diff --git a/libcxx/test/std/algorithms/alg.nonmodifying/mismatch/mismatch.pass.cpp b/libcxx/test/std/algorithms/alg.nonmodifying/mismatch/mismatch.pass.cpp index 2a51127a459146dde344d824d2c2aae0c0e8d312..56af9f234d075fde999902d8c7a8f2d13ed22572 100644 --- a/libcxx/test/std/algorithms/alg.nonmodifying/mismatch/mismatch.pass.cpp +++ b/libcxx/test/std/algorithms/alg.nonmodifying/mismatch/mismatch.pass.cpp @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/libcxx/test/std/atomics/atomics.types.generic/address.pass.cpp b/libcxx/test/std/atomics/atomics.types.generic/address.pass.cpp index 0926628a2e9a895e97401cf86911f025cd04e546..dbe1841762f2012c006c4c597eb3f62f1c6b82cc 100644 --- a/libcxx/test/std/atomics/atomics.types.generic/address.pass.cpp +++ b/libcxx/test/std/atomics/atomics.types.generic/address.pass.cpp @@ -65,9 +65,10 @@ // }; #include +#include +#include #include #include -#include #include diff --git a/libcxx/test/std/concepts/concepts.callable/concept.invocable/invocable.compile.pass.cpp b/libcxx/test/std/concepts/concepts.callable/concept.invocable/invocable.compile.pass.cpp index 9b9bac27174e0fa22e050f246f6ea7a3bc812a49..f9c8f645b284f431613f004e1044297aca1216c5 100644 --- a/libcxx/test/std/concepts/concepts.callable/concept.invocable/invocable.compile.pass.cpp +++ b/libcxx/test/std/concepts/concepts.callable/concept.invocable/invocable.compile.pass.cpp @@ -11,8 +11,8 @@ // template // concept invocable; -#include #include +#include #include #include #include diff --git a/libcxx/test/std/concepts/concepts.callable/concept.regularinvocable/regular_invocable.compile.pass.cpp b/libcxx/test/std/concepts/concepts.callable/concept.regularinvocable/regular_invocable.compile.pass.cpp index bfd20751861d124e914e0c8fde496ad8eeb18fe0..f3547a3ad97cbe8d83c1bf1c2910362456858def 100644 --- a/libcxx/test/std/concepts/concepts.callable/concept.regularinvocable/regular_invocable.compile.pass.cpp +++ b/libcxx/test/std/concepts/concepts.callable/concept.regularinvocable/regular_invocable.compile.pass.cpp @@ -11,11 +11,10 @@ // template // concept regular_invocable; -#include #include +#include #include #include -#include #include template diff --git a/libcxx/test/std/concepts/concepts.compare/concept.equalitycomparable/equality_comparable.compile.pass.cpp b/libcxx/test/std/concepts/concepts.compare/concept.equalitycomparable/equality_comparable.compile.pass.cpp index 126606ef7ab3cd3716860070108218ec2fa08d13..ca0f40eb77d49ea07371978f7c09ea8dc0e3c903 100644 --- a/libcxx/test/std/concepts/concepts.compare/concept.equalitycomparable/equality_comparable.compile.pass.cpp +++ b/libcxx/test/std/concepts/concepts.compare/concept.equalitycomparable/equality_comparable.compile.pass.cpp @@ -14,11 +14,11 @@ #include #include +#include #include #include #include #include -#include #include #include #include diff --git a/libcxx/test/std/concepts/concepts.compare/concept.equalitycomparable/equality_comparable_with.compile.pass.cpp b/libcxx/test/std/concepts/concepts.compare/concept.equalitycomparable/equality_comparable_with.compile.pass.cpp index e0edd1f332f811d10727762ec1ab3f6cc443ed19..0afbe582ba896627e4d81a4013bbb2efab83a989 100644 --- a/libcxx/test/std/concepts/concepts.compare/concept.equalitycomparable/equality_comparable_with.compile.pass.cpp +++ b/libcxx/test/std/concepts/concepts.compare/concept.equalitycomparable/equality_comparable_with.compile.pass.cpp @@ -14,15 +14,12 @@ #include #include +#include #include #include #include #include -#include #include -#include -#include -#include #include #include "test_macros.h" diff --git a/libcxx/test/std/concepts/concepts.compare/concepts.totallyordered/totally_ordered.compile.pass.cpp b/libcxx/test/std/concepts/concepts.compare/concepts.totallyordered/totally_ordered.compile.pass.cpp index d95de10f35cd97ac3492000f6b42c7be1441d3fa..6f8324eaf76471ba78dd4532237e99f2bca00d19 100644 --- a/libcxx/test/std/concepts/concepts.compare/concepts.totallyordered/totally_ordered.compile.pass.cpp +++ b/libcxx/test/std/concepts/concepts.compare/concepts.totallyordered/totally_ordered.compile.pass.cpp @@ -14,11 +14,10 @@ #include #include +#include #include #include #include -#include -#include #include #include #include diff --git a/libcxx/test/std/concepts/concepts.compare/concepts.totallyordered/totally_ordered_with.compile.pass.cpp b/libcxx/test/std/concepts/concepts.compare/concepts.totallyordered/totally_ordered_with.compile.pass.cpp index 0d7bd288c0a18b061fabb49f91a3ed28ad4c90ce..dffc33265aebfd1e79f177843338ebc53bd05395 100644 --- a/libcxx/test/std/concepts/concepts.compare/concepts.totallyordered/totally_ordered_with.compile.pass.cpp +++ b/libcxx/test/std/concepts/concepts.compare/concepts.totallyordered/totally_ordered_with.compile.pass.cpp @@ -14,15 +14,12 @@ #include #include +#include #include #include #include #include -#include #include -#include -#include -#include #include #include "compare_types.h" diff --git a/libcxx/test/std/concepts/concepts.lang/concept.constructible/constructible_from.compile.pass.cpp b/libcxx/test/std/concepts/concepts.lang/concept.constructible/constructible_from.compile.pass.cpp index fe0ecece3382f9a034cafcfe5f0bc1128746bc46..e3b58d622e4506bd89d82c100031f45cb74d3396 100644 --- a/libcxx/test/std/concepts/concepts.lang/concept.constructible/constructible_from.compile.pass.cpp +++ b/libcxx/test/std/concepts/concepts.lang/concept.constructible/constructible_from.compile.pass.cpp @@ -14,6 +14,7 @@ #include #include +#include #include #include #include diff --git a/libcxx/test/std/containers/sequences/vector/vector.modifiers/destroy_elements.pass.cpp b/libcxx/test/std/containers/sequences/vector/vector.modifiers/destroy_elements.pass.cpp index 6cbf1441b46470a6f6e13cc2605dedaffac2fcc8..a245131c7869da7595926639b72eb14050ca1080 100644 --- a/libcxx/test/std/containers/sequences/vector/vector.modifiers/destroy_elements.pass.cpp +++ b/libcxx/test/std/containers/sequences/vector/vector.modifiers/destroy_elements.pass.cpp @@ -13,6 +13,7 @@ #include #include #include +#include #include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h index fe7f0e1f238379004f77dcb129638ab9a60573ac..1d1a2c3752102dd2a1786fabf542e1709b4f43a3 100644 --- a/libcxx/test/std/containers/views/mdspan/MinimalElementType.h +++ b/libcxx/test/std/containers/views/mdspan/MinimalElementType.h @@ -9,6 +9,7 @@ #ifndef TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H #define TEST_STD_CONTAINERS_VIEWS_MDSPAN_MINIMAL_ELEMENT_TYPE_H +#include #include #include diff --git a/libcxx/test/std/containers/views/mdspan/extents/CtorTestCombinations.h b/libcxx/test/std/containers/views/mdspan/extents/CtorTestCombinations.h index 18d4f4b61fb2315ec44406cf81ab3894919e55a4..36f95704631f50eebe0c68fedf7ba1bf723b5fcb 100644 --- a/libcxx/test/std/containers/views/mdspan/extents/CtorTestCombinations.h +++ b/libcxx/test/std/containers/views/mdspan/extents/CtorTestCombinations.h @@ -9,9 +9,10 @@ // -#include -#include #include +#include +#include +#include #include #include "../ConvertibleToIntegral.h" diff --git a/libcxx/test/std/containers/views/mdspan/extents/comparison.pass.cpp b/libcxx/test/std/containers/views/mdspan/extents/comparison.pass.cpp index 574290ebec85472d0c2457e77f49c0ad9ab1a426..1d713044e60f7913335bf10a93be4a42f6f6230f 100644 --- a/libcxx/test/std/containers/views/mdspan/extents/comparison.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/extents/comparison.pass.cpp @@ -17,11 +17,10 @@ // if lhs.extent(r) equals rhs.extent(r) for every rank index r of rhs, otherwise false. // -#include #include -#include +#include +#include #include // dynamic_extent -#include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/extents/conversion.pass.cpp b/libcxx/test/std/containers/views/mdspan/extents/conversion.pass.cpp index f6834b0b4133e64a870f019e7883ee4af21a5558..7baaa7ec9898e46eb19f75cfaef6323ea33c17a3 100644 --- a/libcxx/test/std/containers/views/mdspan/extents/conversion.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/extents/conversion.pass.cpp @@ -28,15 +28,13 @@ // (((Extents != dynamic_extent) && (OtherExtents == dynamic_extent)) || ... ) || // (numeric_limits::max() < numeric_limits::max()) -#include #include -#include +#include #include +#include #include // dynamic_extent #include -#include "test_macros.h" - template constexpr void test_implicit_conversion(To dest, From src) { assert(dest == src); diff --git a/libcxx/test/std/containers/views/mdspan/extents/ctad.pass.cpp b/libcxx/test/std/containers/views/mdspan/extents/ctad.pass.cpp index 1a6501b391396596277a0a8b9214306738117acd..82f111153ce6ab9f6467bffc245af0ce83536dfa 100644 --- a/libcxx/test/std/containers/views/mdspan/extents/ctad.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/extents/ctad.pass.cpp @@ -16,8 +16,9 @@ // Remarks: The deduced type is dextents. // until C++26 // Remarks: The deduced type is extents...>. // since C++26 -#include #include +#include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/extents/obs_static.pass.cpp b/libcxx/test/std/containers/views/mdspan/extents/obs_static.pass.cpp index 29dd9e2d2707214ef4ffff45015462b876f55d40..1d5f61d02e4ff75a01c9c07c4c39807dc9d9785d 100644 --- a/libcxx/test/std/containers/views/mdspan/extents/obs_static.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/extents/obs_static.pass.cpp @@ -26,8 +26,9 @@ // Returns: Di. // -#include #include +#include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/extents/types.pass.cpp b/libcxx/test/std/containers/views/mdspan/extents/types.pass.cpp index 2924da91f77ee474dca3a232ed49b0280b20d270..10bc769473951e1a8e923e34b2dc61ddbaa937c5 100644 --- a/libcxx/test/std/containers/views/mdspan/extents/types.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/extents/types.pass.cpp @@ -22,9 +22,10 @@ // ... // } -#include #include #include +#include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/comparison.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/comparison.pass.cpp index c8b4083291a684f5d39a7335aa6ab591df76a4b5..151da5ba617403275d06f9bf3245d6970433da66 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/comparison.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/comparison.pass.cpp @@ -15,11 +15,10 @@ // ` // Constraints: extents_type::rank() == OtherExtents::rank() is true. -#include #include -#include +#include +#include #include // dynamic_extent -#include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.default.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.default.pass.cpp index 5a4040317d243ff684368192a29cdd9a54e1f0c2..12c59a4caf10e0b65c15f28816f5d085b3b96d0b 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.default.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.default.pass.cpp @@ -14,9 +14,10 @@ // // constexpr mapping() noexcept = default; -#include #include +#include #include +#include #include // dynamic_extent #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.extents.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.extents.pass.cpp index 46505cb961bbdfaa4abf29ec81484d4c8a1d035a..299012dc5af84d1e02bdc7e1946c3c4c3717f4ab 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.extents.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.extents.pass.cpp @@ -17,9 +17,10 @@ // // Effects: Direct-non-list-initializes extents_ with e. -#include #include +#include #include +#include #include // dynamic_extent #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp index 5f9bd4344d0ec7771bcae6fdc515ab9e8bab8b31..1e8f8fb54d5ef833a2d6533824628cdc94571621 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_right.pass.cpp @@ -20,9 +20,10 @@ // // Preconditions: other.required_span_size() is representable as a value of type index_type -#include #include +#include #include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp index 34489b7c52d7db383f2f82b7e5ab50e8d8de6e7a..1668c26a697d45849c39d81da31d7247add43728 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.layout_stride.pass.cpp @@ -23,10 +23,10 @@ // // Effects: Direct-non-list-initializes extents_ with other.extents(). -#include #include #include -#include +#include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp index 63b3c50c73175d6c0ee1c078aaea6976fbea50f2..737e5f3d25728bc12ffed7797639e539ac4855dd 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/ctor.mapping.pass.cpp @@ -18,9 +18,10 @@ // // Preconditions: other.required_span_size() is representable as a value of type index_type -#include #include +#include #include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/index_operator.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/index_operator.pass.cpp index 40cd6bc2812e397801581b6a3858d88b80201f8f..84c3ef45c69b6ba89eac8436705309ab9b55967c 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/index_operator.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/index_operator.pass.cpp @@ -23,11 +23,12 @@ // Preconditions: // * extents_type::index-cast(i) is a multidimensional index in extents_. -#include -#include #include +#include #include +#include #include // dynamic_extent +#include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp index 19f523824cfc48d9ac4f8bd1da4260a2c6f09f08..32442ecd5a0e6de786ba14b363246cfd5661f2c0 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/properties.pass.cpp @@ -26,11 +26,10 @@ // }; // } -#include #include -#include +#include +#include #include // dynamic_extent -#include #include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/required_span_size.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/required_span_size.pass.cpp index 4cb111d29827a7689d9c5d4ca482f18dd4684e9b..9ad61b0799c15f3d6d2a02ee25a9c8e165c15542 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/required_span_size.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/required_span_size.pass.cpp @@ -14,9 +14,10 @@ // // Returns: extents().fwd-prod-of-extents(extents_type::rank()). -#include #include +#include #include +#include #include // dynamic_extent #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_left/static_requirements.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_left/static_requirements.pass.cpp index 7a6add60efcd1123e0881f2d108d898eeee191c2..6410fecdab59e2789ed8726b4cb19f46876b9567 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_left/static_requirements.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_left/static_requirements.pass.cpp @@ -76,9 +76,9 @@ // Result: A constant expression ([expr.const]) of type bool. // Returns: true only if m.is_strided() is true for all possible objects m of type M. -#include #include -#include +#include +#include #include // dynamic_extent #include #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/comparison.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/comparison.pass.cpp index 03c78ca5e91d96f29920a588754d5490cb8228d0..a65d7d39db8e22e23d6bd86de47fec38125fd158 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/comparison.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/comparison.pass.cpp @@ -15,11 +15,10 @@ // ` // Constraints: extents_type::rank() == OtherExtents::rank() is true. -#include #include -#include +#include +#include #include // dynamic_extent -#include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.default.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.default.pass.cpp index f02174416f33cc9c95d1fba7b6dcc3b89df8b491..d644b0ff18d82bcc084c0f81c18bb6c7147d253f 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.default.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.default.pass.cpp @@ -14,9 +14,10 @@ // // constexpr mapping() noexcept = default; -#include #include +#include #include +#include #include // dynamic_extent #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.extents.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.extents.pass.cpp index 9c2c39bc3cb3a5931b4901eba21de056f42a5f9d..cd0cff838fac53a7c9c772d669211be5f5978cee 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.extents.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.extents.pass.cpp @@ -17,9 +17,10 @@ // // Effects: Direct-non-list-initializes extents_ with e. -#include #include +#include #include +#include #include // dynamic_extent #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp index 61aba5dae682944ae7b9bc38a86c1d08061cae05..994d98a80321192bfaf6d70596d0c8543574cf0d 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_left.pass.cpp @@ -20,9 +20,10 @@ // // Preconditions: other.required_span_size() is representable as a value of type index_type -#include #include +#include #include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp index 3bc7d82f8ed8dc237e4a61e58a09f9caea6bd92a..89321f860dc3a9b6e2280a0fe63d437fd4709a91 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.layout_stride.pass.cpp @@ -23,10 +23,10 @@ // // Effects: Direct-non-list-initializes extents_ with other.extents(). -#include #include #include -#include +#include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp index eeea5ab021e973594da5e16ede398b93a95564cd..ee00c688301ef851f7c859c4e34ca3feb910f07a 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/ctor.mapping.pass.cpp @@ -18,9 +18,10 @@ // // Preconditions: other.required_span_size() is representable as a value of type index_type -#include #include +#include #include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/index_operator.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/index_operator.pass.cpp index 989078f17d303b7ba2b02743d7b1239545731b2d..42d4e9a2d24b6f0f2e7b4a94d8c970c6b0476947 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/index_operator.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/index_operator.pass.cpp @@ -23,9 +23,10 @@ // Preconditions: // * extents_type::index-cast(i) is a multidimensional index in extents_. -#include #include +#include #include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp index 674a7ac98cbf7b0bbe7c3048b2b59047802442df..857ec3cb05835dbc68e6d5848142031402c46e25 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/properties.pass.cpp @@ -26,11 +26,10 @@ // }; // } -#include #include -#include +#include +#include #include // dynamic_extent -#include #include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/required_span_size.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/required_span_size.pass.cpp index 0128d8c26a83e78ba5c3eef6dff3dafb64d4fcc6..2ffd1f41f9638f1921d4ade18ebeaa9f8f1d5163 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/required_span_size.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/required_span_size.pass.cpp @@ -14,10 +14,10 @@ // // Returns: extents().fwd-prod-of-extents(extents_type::rank()). - -#include #include +#include #include +#include #include // dynamic_extent #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_right/static_requirements.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_right/static_requirements.pass.cpp index 2b11d17c6717a37f3182604cec618ed1860d7c56..b7e01d14532d4a2a845cc3e9b33d0aedd2803727 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_right/static_requirements.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_right/static_requirements.pass.cpp @@ -76,9 +76,9 @@ // Result: A constant expression ([expr.const]) of type bool. // Returns: true only if m.is_strided() is true for all possible objects m of type M. -#include #include -#include +#include +#include #include // dynamic_extent #include #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.default.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.default.pass.cpp index 108c4c6fca98e11dd87521ca61c0a831c5135b00..055986d80c7263c445b334f3b29569f427e3dd96 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.default.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.default.pass.cpp @@ -20,9 +20,10 @@ // Effects: Direct-non-list-initializes extents_ with extents_type(), and for all d in the range [0, rank_), // direct-non-list-initializes strides_[d] with layout_right::mapping().stride(d). -#include #include +#include #include +#include #include // dynamic_extent #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_array.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_array.pass.cpp index cecfb79ea6867552b7d6c052bd6046e707bcb71a..bbda6d4a736318e45fab6af2ed422507e7c185da 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_array.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_array.pass.cpp @@ -27,10 +27,11 @@ // Effects: Direct-non-list-initializes extents_ with e, and for all d in the range [0, rank_), // direct-non-list-initializes strides_[d] with as_const(s[d]). -#include #include #include +#include #include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_span.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_span.pass.cpp index d0f26ad23df987e858d8b152d8b8b5823b3b7c6b..f5db6768f2c0ecbf7289442313f0907ca770c9df 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_span.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/ctor.extents_span.pass.cpp @@ -27,10 +27,11 @@ // Effects: Direct-non-list-initializes extents_ with e, and for all d in the range [0, rank_), // direct-non-list-initializes strides_[d] with as_const(s[d]). -#include #include #include +#include #include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp index ca88a9f8e0440e5cff9cfd61af41510e808a5f67..233eebff0ccd0f480832ca80c1a8e40e4ddf8fef 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/deduction.pass.cpp @@ -10,13 +10,12 @@ // -#include #include #include -#include +#include #include +#include #include // dynamic_extent -#include #include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp index 589e32f86e39d32acab41ecb996dec9788427842..9f51cc01cf9dfa67d92ace1974b95938abd5ed91 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/is_exhaustive_corner_case.pass.cpp @@ -19,14 +19,11 @@ // range [1, rank_), where pi is the ith element of P. // - Otherwise, false. -#include #include #include -#include +#include +#include #include // dynamic_extent -#include - -#include "test_macros.h" template constexpr void diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp index b1eb84b375b6edf13fb77584a0de6c95788fb525..eac1029882e3a365cdd2e6b92955ec6eb621847f 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/properties.pass.cpp @@ -38,10 +38,11 @@ // range [1, rank_), where pi is the ith element of P. // - Otherwise, false. -#include #include #include #include +#include +#include #include // dynamic_extent #include diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/required_span_size.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/required_span_size.pass.cpp index 870518994a9392795cc4ab9bf7f622ad6e7694f3..629849646bb228aefac9cbf3f189c524654ba7d8 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/required_span_size.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/required_span_size.pass.cpp @@ -19,10 +19,11 @@ // // Returns: REQUIRED-SPAN-SIZE(extents(), strides_). -#include #include #include +#include #include +#include #include // dynamic_extent #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/mdspan/layout_stride/static_requirements.pass.cpp b/libcxx/test/std/containers/views/mdspan/layout_stride/static_requirements.pass.cpp index a69fb4f287c3e832d73fed336612fc9a0ba58dae..8131ecde5d769e6b84d25b500efb501323b06a21 100644 --- a/libcxx/test/std/containers/views/mdspan/layout_stride/static_requirements.pass.cpp +++ b/libcxx/test/std/containers/views/mdspan/layout_stride/static_requirements.pass.cpp @@ -76,9 +76,9 @@ // Result: A constant expression ([expr.const]) of type bool. // Returns: true only if m.is_strided() is true for all possible objects m of type M. -#include #include -#include +#include +#include #include // dynamic_extent #include #include diff --git a/libcxx/test/std/containers/views/mdspan/mdspan/CustomTestAccessors.h b/libcxx/test/std/containers/views/mdspan/mdspan/CustomTestAccessors.h index b68268d172a1fe9d6722edadcf8939b64a2db227..0795926cb43ff8b7999b115e317b40691683b813 100644 --- a/libcxx/test/std/containers/views/mdspan/mdspan/CustomTestAccessors.h +++ b/libcxx/test/std/containers/views/mdspan/mdspan/CustomTestAccessors.h @@ -17,9 +17,10 @@ #ifndef TEST_STD_CONTAINERS_VIEWS_MDSPAN_MDSPAN_CUSTOM_TEST_ACCESSORS_H #define TEST_STD_CONTAINERS_VIEWS_MDSPAN_MDSPAN_CUSTOM_TEST_ACCESSORS_H +#include +#include #include #include -#include // This contains a bunch of accessors and handles which have different properties // regarding constructibility and convertibility in order to test mdspan constraints diff --git a/libcxx/test/std/containers/views/views.span/span.cons/iterator_len.pass.cpp b/libcxx/test/std/containers/views/views.span/span.cons/iterator_len.pass.cpp index fbbd3d6ff40444f799b1b6924e572997ff17e3d2..fcc2625ee6596a56b23047b053dee25c124fabcf 100644 --- a/libcxx/test/std/containers/views/views.span/span.cons/iterator_len.pass.cpp +++ b/libcxx/test/std/containers/views/views.span/span.cons/iterator_len.pass.cpp @@ -14,10 +14,10 @@ // If Extent is not equal to dynamic_extent, then count shall be equal to Extent. // - -#include #include +#include #include +#include #include template diff --git a/libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.verify.cpp b/libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.verify.cpp index a31aa2af7b9dd70c6629e4e6b928063789b026b2..937d8d921ea0b10880edf1ad576d8b0d0f5dbb77 100644 --- a/libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.verify.cpp +++ b/libcxx/test/std/containers/views/views.span/span.cons/iterator_sentinel.verify.cpp @@ -15,8 +15,9 @@ // If Extent is not equal to dynamic_extent, then last - first shall be equal to Extent. // -#include +#include #include +#include template std::span createImplicitSpan(T* first, T* last) { diff --git a/libcxx/test/std/containers/views/views.span/span.objectrep/as_bytes.pass.cpp b/libcxx/test/std/containers/views/views.span/span.objectrep/as_bytes.pass.cpp index 1f58d0f969f70e057fd89d2efc42f032ee55a842..44b658fb83759b83bb102f56a829a02081421a1b 100644 --- a/libcxx/test/std/containers/views/views.span/span.objectrep/as_bytes.pass.cpp +++ b/libcxx/test/std/containers/views/views.span/span.objectrep/as_bytes.pass.cpp @@ -16,9 +16,9 @@ // : sizeof(ElementType) * Extent> // as_bytes(span s) noexcept; - -#include #include +#include +#include #include #include "test_macros.h" diff --git a/libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.pass.cpp b/libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.pass.cpp index 6b7bd5dcf0c1e834ce0110482604f8e45017a1c4..d38d69d9fee1d049a741c555dbb1e3b360328623 100644 --- a/libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.pass.cpp +++ b/libcxx/test/std/containers/views/views.span/span.objectrep/as_writable_bytes.pass.cpp @@ -16,9 +16,9 @@ // : sizeof(ElementType) * Extent> // as_writable_bytes(span s) noexcept; - -#include #include +#include +#include #include #include "test_macros.h" diff --git a/libcxx/test/std/depr/depr.c.headers/ciso646.compile.pass.cpp b/libcxx/test/std/depr/depr.c.headers/ciso646.compile.pass.cpp index 4dff57f84f202cd42cfc03b151dfb2c19733892a..764f4d02f44f44aabdb640dda583a90156fc7115 100644 --- a/libcxx/test/std/depr/depr.c.headers/ciso646.compile.pass.cpp +++ b/libcxx/test/std/depr/depr.c.headers/ciso646.compile.pass.cpp @@ -6,6 +6,8 @@ // //===----------------------------------------------------------------------===// -// +// // removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include diff --git a/libcxx/test/std/depr/depr.c.headers/stdalign_h.compile.pass.cpp b/libcxx/test/std/depr/depr.c.headers/stdalign_h.compile.pass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..e7290aab2c6616bae9b377afef423df95f4d6eb3 --- /dev/null +++ b/libcxx/test/std/depr/depr.c.headers/stdalign_h.compile.pass.cpp @@ -0,0 +1,33 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// test +// +// Even though is not provided by libc++, +// we still test that using it with libc++ on the search path will work. + +// TODO: GCC doesn't provide a proper for C++ until 15. +// UNSUPPORTED: gcc + +#include + +#ifndef __alignas_is_defined +# error __alignas_is_defined not defined +#endif + +#ifndef __alignof_is_defined +# error __alignof_is_defined not defined +#endif + +#ifdef alignas +# error alignas should not be defined +#endif + +#ifdef alignof +# error alignof should not be defined +#endif diff --git a/libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0eaf82ce5cef016ff8d3ed23d6f688639c5cafa4 --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/ccomplex.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is deprecated in C++17 and removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: clang-modules-build + +#include "test_macros.h" + +#include + +#if TEST_STD_VER >= 20 +// expected-warning@ccomplex:* {{'__standard_header_ccomplex' is deprecated: removed in C++20. Include instead.}} +#else +// expected-warning@ccomplex:* {{'__standard_header_ccomplex' is deprecated: Include instead.}} +#endif diff --git a/libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp new file mode 100644 index 0000000000000000000000000000000000000000..04acd10081548560d6a63021aab4de8f73249707 --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/ciso646.verify.cpp @@ -0,0 +1,18 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14, c++17 +// UNSUPPORTED: clang-modules-build + +#include +// expected-warning@ciso646:* {{'__standard_header_ciso646' is deprecated: removed in C++20. Include instead.}} diff --git a/libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc9f1af55b3f14b1af95891fd6ac3a7a6333ebd4 --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/cstdalign.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is deprecated in C++17 and removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: clang-modules-build + +#include "test_macros.h" + +#include + +#if TEST_STD_VER >= 20 +// expected-warning@cstdalign:* {{'__standard_header_cstdalign' is deprecated: removed in C++20.}} +#else +// expected-warning@cstdalign:* {{'__standard_header_cstdalign' is deprecated}} +#endif diff --git a/libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eddefe14d35eac8b16b4c5f1b2cae42628a91796 --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/cstdbool.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is deprecated in C++17 and removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: clang-modules-build + +#include "test_macros.h" + +#include + +#if TEST_STD_VER >= 20 +// expected-warning@cstdbool:* {{'__standard_header_cstdbool' is deprecated: removed in C++20.}} +#else +// expected-warning@cstdbool:* {{'__standard_header_cstdbool' is deprecated}} +#endif diff --git a/libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp b/libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp new file mode 100644 index 0000000000000000000000000000000000000000..097ab1643d15afdcea1e54ddbb3395b48f8b5c89 --- /dev/null +++ b/libcxx/test/std/depr/depr.cpp.headers/ctgmath.verify.cpp @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// check that is deprecated in C++17 and removed in C++20 +// When built with modules, should be omitted. + +// UNSUPPORTED: c++03, c++11, c++14 +// UNSUPPORTED: clang-modules-build + +#include "test_macros.h" + +#include + +#if TEST_STD_VER >= 20 +// expected-warning@ctgmath:* {{'__standard_header_ctgmath' is deprecated: removed in C++20. Include and instead.}} +#else +// expected-warning@ctgmath:* {{'__standard_header_ctgmath' is deprecated: Include and instead.}} +#endif diff --git a/libcxx/test/std/diagnostics/syserr/is_error_code_enum.pass.cpp b/libcxx/test/std/diagnostics/syserr/is_error_code_enum.pass.cpp index 3f614efee203615efbe34da1917f3f89e25c4482..437d0f0a91177af2258ff0d83ccce6f6c888307e 100644 --- a/libcxx/test/std/diagnostics/syserr/is_error_code_enum.pass.cpp +++ b/libcxx/test/std/diagnostics/syserr/is_error_code_enum.pass.cpp @@ -12,8 +12,10 @@ // template <> struct is_error_code_enum<> : public false_type {}; -#include +#include #include +#include + #include "test_macros.h" template diff --git a/libcxx/test/std/diagnostics/syserr/is_error_condition_enum.pass.cpp b/libcxx/test/std/diagnostics/syserr/is_error_condition_enum.pass.cpp index e9916f2427a554626a56f45ab5340e69254771ee..f4d5057948acde677eed7e38dc091778e81ff113 100644 --- a/libcxx/test/std/diagnostics/syserr/is_error_condition_enum.pass.cpp +++ b/libcxx/test/std/diagnostics/syserr/is_error_condition_enum.pass.cpp @@ -12,9 +12,11 @@ // template constexpr bool is_error_condition_enum_v; +#include #include #include #include + #include "test_macros.h" template diff --git a/libcxx/test/std/experimental/simd/simd.class/simd_ctor_broadcast.pass.cpp b/libcxx/test/std/experimental/simd/simd.class/simd_ctor_broadcast.pass.cpp index 8a291632a8ab1eb069f206307b98158389b9974d..fbdaa438f7886c2133d6c91648c8e58542b64c85 100644 --- a/libcxx/test/std/experimental/simd/simd.class/simd_ctor_broadcast.pass.cpp +++ b/libcxx/test/std/experimental/simd/simd.class/simd_ctor_broadcast.pass.cpp @@ -14,6 +14,9 @@ // [simd.class] // template simd(U&& value) noexcept; +#include +#include + #include "../test_utils.h" namespace ex = std::experimental::parallelism_v2; diff --git a/libcxx/test/std/experimental/simd/test_utils.h b/libcxx/test/std/experimental/simd/test_utils.h index 3c227a43c2f4ddbe5841ee70f9a982dd56499c66..4c7b459cc8eb1146b9cd85645d9707a2f53685d4 100644 --- a/libcxx/test/std/experimental/simd/test_utils.h +++ b/libcxx/test/std/experimental/simd/test_utils.h @@ -9,12 +9,13 @@ #ifndef LIBCXX_TEST_STD_EXPERIMENTAL_SIMD_TEST_UTILS_H #define LIBCXX_TEST_STD_EXPERIMENTAL_SIMD_TEST_UTILS_H -#include #include #include +#include +#include #include #include -#include + #include "type_algorithms.h" namespace ex = std::experimental::parallelism_v2; diff --git a/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/incrementable.traits/incrementable_traits.compile.pass.cpp b/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/incrementable.traits/incrementable_traits.compile.pass.cpp index 8413f912e576200c0cb18d7deadfe5ce2ee45509..6d07e973ec306e0d97d4058ff23dbbc8fbac7e8a 100644 --- a/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/incrementable.traits/incrementable_traits.compile.pass.cpp +++ b/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/incrementable.traits/incrementable_traits.compile.pass.cpp @@ -11,12 +11,9 @@ // template // struct incrementable_traits; -#include - #include #include - -#include "test_macros.h" +#include template concept check_has_difference_type = requires { diff --git a/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/incrementable.traits/iter_difference_t.compile.pass.cpp b/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/incrementable.traits/iter_difference_t.compile.pass.cpp index bd6664fe957a2e0ae4c314e31daac4fc77acabe0..99512f7c3ba1c602f00c2836726787cab1a8c8ed 100644 --- a/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/incrementable.traits/iter_difference_t.compile.pass.cpp +++ b/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/incrementable.traits/iter_difference_t.compile.pass.cpp @@ -14,6 +14,7 @@ #include #include +#include #include template diff --git a/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/readable.traits/indirectly_readable_traits.compile.pass.cpp b/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/readable.traits/indirectly_readable_traits.compile.pass.cpp index 835aa9c7be278f43f78d024f177f2517616f707e..4fd935e460ca841a62b205eb13dd370ce9a38f11 100644 --- a/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/readable.traits/indirectly_readable_traits.compile.pass.cpp +++ b/libcxx/test/std/iterators/iterator.requirements/iterator.assoc.types/readable.traits/indirectly_readable_traits.compile.pass.cpp @@ -14,9 +14,9 @@ #include #include +#include #include #include -#include #include template diff --git a/libcxx/test/std/iterators/predef.iterators/insert.iterators/back.insert.iterator/types.pass.cpp b/libcxx/test/std/iterators/predef.iterators/insert.iterators/back.insert.iterator/types.pass.cpp index f8d3e2b4fdc7b26b7f5f6c0388d344d251bfccf2..68edbb1cb91dea2d11692b7568b8d49b8c766f45 100644 --- a/libcxx/test/std/iterators/predef.iterators/insert.iterators/back.insert.iterator/types.pass.cpp +++ b/libcxx/test/std/iterators/predef.iterators/insert.iterators/back.insert.iterator/types.pass.cpp @@ -27,6 +27,7 @@ // typedef void pointer; // }; +#include #include #include #include diff --git a/libcxx/test/std/iterators/predef.iterators/insert.iterators/front.insert.iterator/types.pass.cpp b/libcxx/test/std/iterators/predef.iterators/insert.iterators/front.insert.iterator/types.pass.cpp index f71ba368ab8612fe9ed2576747792a9ca4a640e4..c74f9704d0c35c069ff43c8491e47414cbd9e9ab 100644 --- a/libcxx/test/std/iterators/predef.iterators/insert.iterators/front.insert.iterator/types.pass.cpp +++ b/libcxx/test/std/iterators/predef.iterators/insert.iterators/front.insert.iterator/types.pass.cpp @@ -28,6 +28,7 @@ // typedef output_iterator_tag iterator_category; // }; +#include #include #include #include diff --git a/libcxx/test/std/iterators/predef.iterators/insert.iterators/insert.iterator/types.pass.cpp b/libcxx/test/std/iterators/predef.iterators/insert.iterators/insert.iterator/types.pass.cpp index 08864868342aed91daa223a17e2de2720d450809..faf5ca5d61836dc07b704049b09cf3bf767a6460 100644 --- a/libcxx/test/std/iterators/predef.iterators/insert.iterators/insert.iterator/types.pass.cpp +++ b/libcxx/test/std/iterators/predef.iterators/insert.iterators/insert.iterator/types.pass.cpp @@ -28,9 +28,11 @@ // typedef void pointer; // }; +#include #include #include #include + #include "test_macros.h" template diff --git a/libcxx/test/std/language.support/support.runtime/cstdalign.compile.pass.cpp b/libcxx/test/std/language.support/support.runtime/cstdalign.compile.pass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fbbaf9b2d136f94f56bc8fd5091eafe81e6c74e4 --- /dev/null +++ b/libcxx/test/std/language.support/support.runtime/cstdalign.compile.pass.cpp @@ -0,0 +1,29 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// test // deprecated in C++17, removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS + +#include + +#ifndef __alignas_is_defined +# error __alignas_is_defined not defined +#endif + +#ifndef __alignof_is_defined +# error __alignof_is_defined not defined +#endif + +#ifdef alignas +# error alignas should not be defined +#endif + +#ifdef alignof +# error alignof should not be defined +#endif diff --git a/libcxx/test/std/language.support/support.runtime/cstdbool.pass.cpp b/libcxx/test/std/language.support/support.runtime/cstdbool.pass.cpp index 1d0e9b06a43d2ebdc637cabf21368b4be1373a0d..9a35eea507c40ad055e348ec0a08599fe66d0706 100644 --- a/libcxx/test/std/language.support/support.runtime/cstdbool.pass.cpp +++ b/libcxx/test/std/language.support/support.runtime/cstdbool.pass.cpp @@ -6,7 +6,9 @@ // //===----------------------------------------------------------------------===// -// test +// test // deprecated in C++17, removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include diff --git a/libcxx/test/std/numerics/bit/byteswap.pass.cpp b/libcxx/test/std/numerics/bit/byteswap.pass.cpp index b87faf150177f37bffa80a367544d572bc02d123..9d4e328ed9d0f7b8a3683543d27ef8fd04ce49ab 100644 --- a/libcxx/test/std/numerics/bit/byteswap.pass.cpp +++ b/libcxx/test/std/numerics/bit/byteswap.pass.cpp @@ -10,6 +10,7 @@ #include #include +#include #include #include diff --git a/libcxx/test/std/numerics/c.math/ctgmath.pass.cpp b/libcxx/test/std/numerics/c.math/ctgmath.pass.cpp index 2c8d054fbc527df3dcf37dd77a4928fe295a0245..2e4679980577a9bad6bc6e2b1fabb2c2fb546ea8 100644 --- a/libcxx/test/std/numerics/c.math/ctgmath.pass.cpp +++ b/libcxx/test/std/numerics/c.math/ctgmath.pass.cpp @@ -6,7 +6,9 @@ // //===----------------------------------------------------------------------===// -// +// // deprecated in C++17, removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include diff --git a/libcxx/test/std/numerics/complex.number/ccmplx/ccomplex.pass.cpp b/libcxx/test/std/numerics/complex.number/ccmplx/ccomplex.pass.cpp index cc3f8cd6a9beb95e24612656efc95e04d0503f29..0ed116c6410639c3c6d1a11722a6969fdd8af988 100644 --- a/libcxx/test/std/numerics/complex.number/ccmplx/ccomplex.pass.cpp +++ b/libcxx/test/std/numerics/complex.number/ccmplx/ccomplex.pass.cpp @@ -6,7 +6,9 @@ // //===----------------------------------------------------------------------===// -// +// // deprecated in C++17, removed in C++20, but still provided by libc++ as an extension + +// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS #include diff --git a/libcxx/test/std/numerics/numeric.ops/exclusive.scan/exclusive_scan.pass.cpp b/libcxx/test/std/numerics/numeric.ops/exclusive.scan/exclusive_scan.pass.cpp index bef2dd7866964c56fccbd9511e1a06c5c048ee7d..f6cac33e944387e1bf1cc45df067837ca1023482 100644 --- a/libcxx/test/std/numerics/numeric.ops/exclusive.scan/exclusive_scan.pass.cpp +++ b/libcxx/test/std/numerics/numeric.ops/exclusive.scan/exclusive_scan.pass.cpp @@ -16,12 +16,11 @@ // OutputIterator result, T init); // -#include #include #include #include -#include -#include +#include +#include #include "test_macros.h" #include "test_iterators.h" diff --git a/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan.pass.cpp b/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan.pass.cpp index 299d085d01a062d5233b4a184fec55452af30067..1c79eebb8ee2c6dcb75ce233ef38e373520f644f 100644 --- a/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan.pass.cpp +++ b/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan.pass.cpp @@ -16,12 +16,11 @@ // OutputIterator result, T init); // -#include #include #include #include -#include -#include +#include +#include #include "test_macros.h" #include "test_iterators.h" diff --git a/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan_op.pass.cpp b/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan_op.pass.cpp index 87bea923eed3fd0296fdd3d86e9e0dd787eec5da..fb39b4f06ece7981e4ab8dfddbaeacded5c27fb8 100644 --- a/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan_op.pass.cpp +++ b/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan_op.pass.cpp @@ -17,12 +17,12 @@ // OutputIterator result, // BinaryOperation binary_op); // C++17 -#include #include #include #include +#include #include -#include +#include #include "test_macros.h" #include "test_iterators.h" diff --git a/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan_op_init.pass.cpp b/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan_op_init.pass.cpp index 2e21d38f473441bcde5a2ee07f9b3fa19e77ae77..4e07306c293111bd9fcd1391dbe5639ca04f84cf 100644 --- a/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan_op_init.pass.cpp +++ b/libcxx/test/std/numerics/numeric.ops/inclusive.scan/inclusive_scan_op_init.pass.cpp @@ -17,12 +17,12 @@ // OutputIterator result, // BinaryOperation binary_op, T init); // C++17 -#include #include #include #include +#include #include -#include +#include #include "test_macros.h" #include "test_iterators.h" diff --git a/libcxx/test/std/numerics/numeric.ops/transform.exclusive.scan/transform_exclusive_scan_init_bop_uop.pass.cpp b/libcxx/test/std/numerics/numeric.ops/transform.exclusive.scan/transform_exclusive_scan_init_bop_uop.pass.cpp index 52272205307a9f48fbe74beeef7053e4c69484a2..7e1017d4e3040bcd34023e6a71d24d4978f5d67e 100644 --- a/libcxx/test/std/numerics/numeric.ops/transform.exclusive.scan/transform_exclusive_scan_init_bop_uop.pass.cpp +++ b/libcxx/test/std/numerics/numeric.ops/transform.exclusive.scan/transform_exclusive_scan_init_bop_uop.pass.cpp @@ -18,13 +18,12 @@ // BinaryOperation binary_op, // UnaryOperation unary_op); - -#include #include #include #include +#include #include -#include +#include #include "test_macros.h" #include "test_iterators.h" diff --git a/libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/transform_inclusive_scan_bop_uop.pass.cpp b/libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/transform_inclusive_scan_bop_uop.pass.cpp index 80ead01e9a7958c2d45e1592f716ebb0ca2ee06c..1dd7661bb42ed92708d311d1459c423ad7599d2f 100644 --- a/libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/transform_inclusive_scan_bop_uop.pass.cpp +++ b/libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/transform_inclusive_scan_bop_uop.pass.cpp @@ -18,13 +18,12 @@ // BinaryOperation binary_op, // UnaryOperation unary_op); - -#include #include #include #include +#include #include -#include +#include #include "test_macros.h" #include "test_iterators.h" diff --git a/libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/transform_inclusive_scan_bop_uop_init.pass.cpp b/libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/transform_inclusive_scan_bop_uop_init.pass.cpp index 18be676c7a54d0daadac7926379014afd465ad78..1269c3f68236bed64e7533892cbf9deefdb60d30 100644 --- a/libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/transform_inclusive_scan_bop_uop_init.pass.cpp +++ b/libcxx/test/std/numerics/numeric.ops/transform.inclusive.scan/transform_inclusive_scan_bop_uop_init.pass.cpp @@ -19,13 +19,12 @@ // UnaryOperation unary_op, // T init); - -#include #include #include #include +#include #include -#include +#include #include "test_macros.h" #include "test_iterators.h" diff --git a/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.plinear/eval.pass.cpp b/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.plinear/eval.pass.cpp index ec7f72edf9ee9b3662ba59c6bddb4ba7a945a04c..c2d280406852a9e909320eb992c9965aab696575 100644 --- a/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.plinear/eval.pass.cpp +++ b/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.plinear/eval.pass.cpp @@ -15,13 +15,12 @@ // template result_type operator()(_URNG& g); -#include #include #include #include -#include +#include #include -#include +#include #include #include "test_macros.h" diff --git a/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.plinear/eval_param.pass.cpp b/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.plinear/eval_param.pass.cpp index 9bcb2ed3afac12a9dfff6cbb3f482181af38f7ee..e31b4c5837fe91598a50c88a0af22947c1d65e68 100644 --- a/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.plinear/eval_param.pass.cpp +++ b/libcxx/test/std/numerics/rand/rand.dist/rand.dist.samp/rand.dist.samp.plinear/eval_param.pass.cpp @@ -15,13 +15,12 @@ // template result_type operator()(_URNG& g, const param_type& parm); -#include #include // for sort #include #include -#include +#include #include -#include +#include #include #include "test_macros.h" diff --git a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/ctor.default.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/ctor.default.pass.cpp index 98c6cb7af5f56333bd0e7e6606cb2a688f2bd306..96d96053f74ba52a52473e33edf9c80fa4c4feaa 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/ctor.default.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/ctor.default.pass.cpp @@ -16,6 +16,7 @@ #include #include +#include #include constexpr int buff[] = {-2, 1, -1, 2}; diff --git a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/deref.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/deref.pass.cpp index 8cc9bdac0b1d8de2afd2afed7737f758b1b7fdab..6a5ce1335eccf88dca0e405efb0111f1fc7a767f 100644 --- a/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/deref.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/deref.pass.cpp @@ -17,13 +17,12 @@ #include #include #include +#include #include #include -#include #include "../types.h" #include "test_iterators.h" -#include "test_macros.h" template > constexpr void test() { diff --git a/libcxx/test/std/ranges/range.factories/range.repeat.view/iterator/member_typedefs.compile.pass.cpp b/libcxx/test/std/ranges/range.factories/range.repeat.view/iterator/member_typedefs.compile.pass.cpp index 2ef09a6d9216985a46a3d3b4bf55e6a1620d32fd..d7202e35e66d3d82bb8c0e9c48b0ffe68f31c519 100644 --- a/libcxx/test/std/ranges/range.factories/range.repeat.view/iterator/member_typedefs.compile.pass.cpp +++ b/libcxx/test/std/ranges/range.factories/range.repeat.view/iterator/member_typedefs.compile.pass.cpp @@ -20,6 +20,7 @@ #include #include +#include #include #include #include diff --git a/libcxx/test/std/ranges/range.factories/range.repeat.view/iterator/minus.pass.cpp b/libcxx/test/std/ranges/range.factories/range.repeat.view/iterator/minus.pass.cpp index 3a373741f4c0e4ba2258e6090daa611403b97d89..523eefa69b4ca1c87410418688edd505f2d44826 100644 --- a/libcxx/test/std/ranges/range.factories/range.repeat.view/iterator/minus.pass.cpp +++ b/libcxx/test/std/ranges/range.factories/range.repeat.view/iterator/minus.pass.cpp @@ -11,10 +11,10 @@ // friend constexpr iterator operator-(iterator i, difference_type n); // friend constexpr difference_type operator-(const iterator& x, const iterator& y); -#include #include -#include #include +#include +#include constexpr bool test() { // - difference_type diff --git a/libcxx/test/std/ranges/range.utility/range.subrange/ctad.compile.pass.cpp b/libcxx/test/std/ranges/range.utility/range.subrange/ctad.compile.pass.cpp index 670f9808b902cabd92727f2162eae29eabecf037..2bf6ca6fb0a0c39714d0d7b51d4bd7d11ff33194 100644 --- a/libcxx/test/std/ranges/range.utility/range.subrange/ctad.compile.pass.cpp +++ b/libcxx/test/std/ranges/range.utility/range.subrange/ctad.compile.pass.cpp @@ -13,7 +13,8 @@ #include #include -#include "test_macros.h" +#include + #include "test_iterators.h" using FI = forward_iterator; diff --git a/libcxx/test/std/strings/basic.string/string.capacity/deallocate_size.pass.cpp b/libcxx/test/std/strings/basic.string/string.capacity/deallocate_size.pass.cpp index 1203b2f3ec18f9274a90a06c7b4144f44a15f636..00f9e2b8467837d86eea17d7c4b79c5cd533963f 100644 --- a/libcxx/test/std/strings/basic.string/string.capacity/deallocate_size.pass.cpp +++ b/libcxx/test/std/strings/basic.string/string.capacity/deallocate_size.pass.cpp @@ -34,15 +34,32 @@ struct test_alloc { typedef test_alloc other; }; - TEST_CONSTEXPR_CXX14 pointer allocate(size_type n, const void* = nullptr) { + TEST_CONSTEXPR test_alloc() TEST_NOEXCEPT {} + + template + TEST_CONSTEXPR test_alloc(const test_alloc&) TEST_NOEXCEPT {} + + pointer allocate(size_type n, const void* = nullptr) { allocated_ += n; return std::allocator().allocate(n); } - TEST_CONSTEXPR_CXX14 void deallocate(pointer p, size_type s) { + void deallocate(pointer p, size_type s) { allocated_ -= s; std::allocator().deallocate(p, s); } + + template + friend TEST_CONSTEXPR bool operator==(const test_alloc&, const test_alloc&) TEST_NOEXCEPT { + return true; + } + +#if TEST_STD_VER < 20 + template + friend TEST_CONSTEXPR bool operator!=(const test_alloc&, const test_alloc&) TEST_NOEXCEPT { + return false; + } +#endif }; template diff --git a/libcxx/test/std/strings/string.view/string.view.modifiers/remove_prefix.pass.cpp b/libcxx/test/std/strings/string.view/string.view.modifiers/remove_prefix.pass.cpp index 4bfa0f38829dda7ba1953b85623cb2a1cc6dc177..26db908428c3208b1d988288c39e38f4759d7233 100644 --- a/libcxx/test/std/strings/string.view/string.view.modifiers/remove_prefix.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.modifiers/remove_prefix.pass.cpp @@ -12,8 +12,9 @@ // void remove_prefix(size_type _n) -#include #include +#include +#include #include "test_macros.h" diff --git a/libcxx/test/std/strings/string.view/string.view.modifiers/remove_suffix.pass.cpp b/libcxx/test/std/strings/string.view/string.view.modifiers/remove_suffix.pass.cpp index 6d57f6c24a487740570aeb6a02bf1dd8ed83ff03..b6edccc68c9e8d43c83db237cf41fc174672aeb0 100644 --- a/libcxx/test/std/strings/string.view/string.view.modifiers/remove_suffix.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.modifiers/remove_suffix.pass.cpp @@ -12,8 +12,9 @@ // void remove_suffix(size_type _n) -#include #include +#include +#include #include "test_macros.h" diff --git a/libcxx/test/std/strings/string.view/string.view.modifiers/swap.pass.cpp b/libcxx/test/std/strings/string.view/string.view.modifiers/swap.pass.cpp index de0c5f423c4e8ee8cf23e6fc4667ac399ba6e1d2..d18a7b28688dcd2b5fd4d0b03185333c492e1d4b 100644 --- a/libcxx/test/std/strings/string.view/string.view.modifiers/swap.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.modifiers/swap.pass.cpp @@ -12,8 +12,9 @@ // void swap(basic_string_view& _other) noexcept -#include #include +#include +#include #include "test_macros.h" diff --git a/libcxx/test/std/strings/string.view/string.view.ops/copy.pass.cpp b/libcxx/test/std/strings/string.view/string.view.ops/copy.pass.cpp index 1d97723b90edce5c08c2ce19c8a89ec5cad4c820..0b27a05056c68e9b7a10ba3b40d450112c279400 100644 --- a/libcxx/test/std/strings/string.view/string.view.ops/copy.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.ops/copy.pass.cpp @@ -18,10 +18,11 @@ // Effects: Equivalent to std::copy_n(begin() + pos, rlen, s). // Returns: rlen. -#include #include #include +#include #include +#include #include "test_macros.h" diff --git a/libcxx/test/std/strings/string.view/string.view.ops/substr.pass.cpp b/libcxx/test/std/strings/string.view/string.view.ops/substr.pass.cpp index 1c8e0aebabd4127ecb5edbaf05b3ea83b1c76b90..62b0259c175f8f664e1f2f764bbab39830ec9125 100644 --- a/libcxx/test/std/strings/string.view/string.view.ops/substr.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.ops/substr.pass.cpp @@ -16,10 +16,11 @@ // Effects: Determines the effective length rlen of the string to reference as the smaller of n and size() - pos. // Returns: basic_string_view(data()+pos, rlen). -#include #include -#include #include +#include +#include +#include #include "test_macros.h" diff --git a/libcxx/test/std/utilities/function.objects/func.search/func.search.bm/hash.pass.cpp b/libcxx/test/std/utilities/function.objects/func.search/func.search.bm/hash.pass.cpp index 1704eb67562e1ff29700e7cb1945105a9370a830..b9209ac2c89b657148ffd578fbeedcecc4991fc9 100644 --- a/libcxx/test/std/utilities/function.objects/func.search/func.search.bm/hash.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.search/func.search.bm/hash.pass.cpp @@ -33,9 +33,9 @@ #include #include +#include #include -#include "test_macros.h" #include "test_iterators.h" template struct MyHash { diff --git a/libcxx/test/std/utilities/function.objects/func.search/func.search.bm/hash.pred.pass.cpp b/libcxx/test/std/utilities/function.objects/func.search/func.search.bm/hash.pred.pass.cpp index 3648be9bb06acc2b5b57166bdeefb38706e88b6d..d616301767ede645859a3504d2696cb386b71432 100644 --- a/libcxx/test/std/utilities/function.objects/func.search/func.search.bm/hash.pred.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.search/func.search.bm/hash.pred.pass.cpp @@ -33,9 +33,9 @@ #include #include +#include #include -#include "test_macros.h" #include "test_iterators.h" template struct MyHash { diff --git a/libcxx/test/std/utilities/function.objects/func.search/func.search.bmh/hash.pass.cpp b/libcxx/test/std/utilities/function.objects/func.search/func.search.bmh/hash.pass.cpp index d0e6d5f8bfb6b5389b9170b20cb27f16b1d5e701..19f5710819c46336f110ed4d84c198a34ccb83ae 100644 --- a/libcxx/test/std/utilities/function.objects/func.search/func.search.bmh/hash.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.search/func.search.bmh/hash.pass.cpp @@ -31,10 +31,10 @@ // }; #include -#include #include +#include +#include -#include "test_macros.h" #include "test_iterators.h" template struct MyHash { diff --git a/libcxx/test/std/utilities/function.objects/func.search/func.search.bmh/hash.pred.pass.cpp b/libcxx/test/std/utilities/function.objects/func.search/func.search.bmh/hash.pred.pass.cpp index 59b5b30d7f1b5e92461e41e68e9dffba1f9807c7..3d29a05efd40c0c9d7075ee8e7144e6ca02b8f54 100644 --- a/libcxx/test/std/utilities/function.objects/func.search/func.search.bmh/hash.pred.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.search/func.search.bmh/hash.pred.pass.cpp @@ -31,10 +31,10 @@ // }; #include -#include #include +#include +#include -#include "test_macros.h" #include "test_iterators.h" template struct MyHash { diff --git a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp index 381bcda761700c31b40e36905390d66d95f53301..064f7acdf71a03b4466cb66d4b059396e76d2de2 100644 --- a/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/func.wrap/func.wrap.func/func.wrap.func.con/deduct_F.pass.cpp @@ -13,8 +13,8 @@ // UNSUPPORTED: c++03, c++11, c++14 +#include #include -#include #include #include "test_macros.h" @@ -153,4 +153,3 @@ struct invalid_c_vararg { R operator()(int, ...) { return {}; } }; static_assert(!can_deduce); static_assert(!can_deduce); static_assert(!can_deduce); - diff --git a/libcxx/test/std/utilities/function.objects/unord.hash/pointer.pass.cpp b/libcxx/test/std/utilities/function.objects/unord.hash/pointer.pass.cpp index 577a9bf0e15ba725411e8d268ed796148a58cae3..448c5ba143c10128530c6b8e592121266f2327f5 100644 --- a/libcxx/test/std/utilities/function.objects/unord.hash/pointer.pass.cpp +++ b/libcxx/test/std/utilities/function.objects/unord.hash/pointer.pass.cpp @@ -19,10 +19,10 @@ // Not very portable -#include #include +#include +#include #include -#include #include "test_macros.h" diff --git a/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.construct/construct_at.pass.cpp b/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.construct/construct_at.pass.cpp index 272441ebedc2f2dcd6f5e63e9b0b351370fc6abf..92e8879d05bf01e60ee25d54a32fabe56262c006 100644 --- a/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.construct/construct_at.pass.cpp +++ b/libcxx/test/std/utilities/memory/specialized.algorithms/specialized.construct/construct_at.pass.cpp @@ -13,8 +13,9 @@ // template // constexpr T* construct_at(T* location, Args&& ...args); -#include #include +#include +#include #include #include "test_iterators.h" diff --git a/libcxx/test/std/utilities/memory/temporary.buffer/overaligned.pass.cpp b/libcxx/test/std/utilities/memory/temporary.buffer/overaligned.pass.cpp index 4c66370fac9221de15df12f7402dc1fa401c6e9d..3fa9355270866a90161a4b18feae5e19497dfc98 100644 --- a/libcxx/test/std/utilities/memory/temporary.buffer/overaligned.pass.cpp +++ b/libcxx/test/std/utilities/memory/temporary.buffer/overaligned.pass.cpp @@ -22,12 +22,11 @@ // return_temporary_buffer(T* p); #include +#include #include #include #include -#include "test_macros.h" - struct alignas(32) A { int field; }; diff --git a/libcxx/test/std/utilities/memory/temporary.buffer/temporary_buffer.pass.cpp b/libcxx/test/std/utilities/memory/temporary.buffer/temporary_buffer.pass.cpp index 5f7fc4571906cc8042fab51b3e3afebebb2e94e8..39a4767d874e39a9210fe2f63bd8ba5afc85f300 100644 --- a/libcxx/test/std/utilities/memory/temporary.buffer/temporary_buffer.pass.cpp +++ b/libcxx/test/std/utilities/memory/temporary.buffer/temporary_buffer.pass.cpp @@ -19,12 +19,11 @@ // void // return_temporary_buffer(T* p); -#include #include +#include +#include #include -#include "test_macros.h" - int main(int, char**) { std::pair ip = std::get_temporary_buffer(5); diff --git a/libcxx/test/std/utilities/meta/meta.rel/is_invocable.pass.cpp b/libcxx/test/std/utilities/meta/meta.rel/is_invocable.pass.cpp index 32db9d12099f2679c51697077c9ee3289d8e437c..2eecf7925d7395962c457b40c1d8647ec8f1fb6f 100644 --- a/libcxx/test/std/utilities/meta/meta.rel/is_invocable.pass.cpp +++ b/libcxx/test/std/utilities/meta/meta.rel/is_invocable.pass.cpp @@ -18,13 +18,12 @@ // Fn and all types in the template parameter pack ArgTypes shall be // complete types, cv void, or arrays of unknown bound. -#include +#include #include #include +#include #include -#include "test_macros.h" - struct Tag {}; struct DerFromTag : Tag {}; diff --git a/libcxx/test/std/utilities/meta/meta.rel/is_nothrow_invocable.pass.cpp b/libcxx/test/std/utilities/meta/meta.rel/is_nothrow_invocable.pass.cpp index fa6048e869e18284e33fe78e5f75ca0deaf9d37d..47e81f38e54b367a28903ec6af1dc70f0dac3f29 100644 --- a/libcxx/test/std/utilities/meta/meta.rel/is_nothrow_invocable.pass.cpp +++ b/libcxx/test/std/utilities/meta/meta.rel/is_nothrow_invocable.pass.cpp @@ -12,12 +12,10 @@ // is_nothrow_invocable +#include #include -#include #include -#include "test_macros.h" - struct Tag {}; struct Implicit { diff --git a/libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_overaligned_request.pass.cpp b/libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_overaligned_request.pass.cpp index cf3dfe21d96755ed6f0af9fc6088cc5582d8b2f7..ad967798747abc8a3fd0bfcfee914be6cb13941f 100644 --- a/libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_overaligned_request.pass.cpp +++ b/libcxx/test/std/utilities/utility/mem.res/mem.res.monotonic.buffer/mem.res.monotonic.buffer.mem/allocate_overaligned_request.pass.cpp @@ -14,8 +14,9 @@ // class monotonic_buffer_resource -#include #include +#include +#include #include "test_macros.h" #include "count_new.h" diff --git a/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate_overaligned_request.pass.cpp b/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate_overaligned_request.pass.cpp index 35a6a8f135a406509bca8ec5a638ce03ae9fc89e..f3e1e4c026ef7200b3b80c27b20c7a2eb14ca874 100644 --- a/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate_overaligned_request.pass.cpp +++ b/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_allocate_overaligned_request.pass.cpp @@ -14,9 +14,10 @@ // class synchronized_pool_resource -#include #include +#include #include // std::align +#include #include "count_new.h" #include "test_macros.h" diff --git a/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_deallocate_matches_allocate.pass.cpp b/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_deallocate_matches_allocate.pass.cpp index d5b3b6e08a42a89034766fc7884cf677ef416f41..f55ab1d1aa5c1967b94737bd182864234a9052a7 100644 --- a/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_deallocate_matches_allocate.pass.cpp +++ b/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/sync_deallocate_matches_allocate.pass.cpp @@ -15,9 +15,10 @@ // class synchronized_pool_resource -#include #include #include +#include +#include #include #include diff --git a/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate_overaligned_request.pass.cpp b/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate_overaligned_request.pass.cpp index cd8d8a774592528cd205b53242ee36d682a6db7f..5153a54ef3f14ff011f4ce17b6cb710ecf7cfc0d 100644 --- a/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate_overaligned_request.pass.cpp +++ b/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_allocate_overaligned_request.pass.cpp @@ -14,9 +14,10 @@ // class unsynchronized_pool_resource -#include #include +#include #include // std::align +#include #include "count_new.h" #include "test_macros.h" diff --git a/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_deallocate_matches_allocate.pass.cpp b/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_deallocate_matches_allocate.pass.cpp index fe5f4736a7b1a84bdd8ad184a237999a61eaf63d..a0e86f82e9b2dc72748e6c4b450201021d82afa4 100644 --- a/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_deallocate_matches_allocate.pass.cpp +++ b/libcxx/test/std/utilities/utility/mem.res/mem.res.pool/mem.res.pool.mem/unsync_deallocate_matches_allocate.pass.cpp @@ -15,9 +15,10 @@ // class unsynchronized_pool_resource -#include #include #include +#include +#include #include #include diff --git a/libcxx/utils/generate_escaped_output_table.py b/libcxx/utils/generate_escaped_output_table.py index 41524e8fe7186c5b2d7c4f882d40ebcae59b314c..59dd707ae6126d40985e17463d34078ff8e32554 100755 --- a/libcxx/utils/generate_escaped_output_table.py +++ b/libcxx/utils/generate_escaped_output_table.py @@ -218,7 +218,7 @@ TABLES_HPP_TEMPLATE = """ #include <__algorithm/ranges_upper_bound.h> #include <__config> -#include +#include <__cstddef/ptrdiff_t.h> #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/utils/generate_extended_grapheme_cluster_table.py b/libcxx/utils/generate_extended_grapheme_cluster_table.py index 558b606186130ffca0940d7b5d798cce48714e6d..eba88a4f487767b32f343b363db083c61644bf8c 100755 --- a/libcxx/utils/generate_extended_grapheme_cluster_table.py +++ b/libcxx/utils/generate_extended_grapheme_cluster_table.py @@ -214,8 +214,8 @@ MSVC_FORMAT_UCD_TABLES_HPP_TEMPLATE = """ #include <__algorithm/ranges_upper_bound.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/access.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/utils/generate_indic_conjunct_break_table.py b/libcxx/utils/generate_indic_conjunct_break_table.py index e41f6e9be233d75b7efe4a232f8b77c2e2a80333..580d8157ffebf9ad9c4d78497691590f0d1d01bb 100755 --- a/libcxx/utils/generate_indic_conjunct_break_table.py +++ b/libcxx/utils/generate_indic_conjunct_break_table.py @@ -207,8 +207,8 @@ MSVC_FORMAT_UCD_TABLES_HPP_TEMPLATE = """ #include <__algorithm/ranges_upper_bound.h> #include <__config> +#include <__cstddef/ptrdiff_t.h> #include <__iterator/access.h> -#include #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/utils/generate_width_estimation_table.py b/libcxx/utils/generate_width_estimation_table.py index d8c036f34e8353d2f441b8006de5880cafcde49b..f81f0ba77489eb79b79ff095c1978cafcdad60b7 100644 --- a/libcxx/utils/generate_width_estimation_table.py +++ b/libcxx/utils/generate_width_estimation_table.py @@ -246,7 +246,7 @@ TABLES_HPP_TEMPLATE = """ #include <__algorithm/ranges_upper_bound.h> #include <__config> -#include +#include <__cstddef/ptrdiff_t.h> #include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) diff --git a/libcxx/utils/libcxx/header_information.py b/libcxx/utils/libcxx/header_information.py index 3b12dcb9f56c0b74cda14a04c0b7531b7449217b..cac620e4f1fe77797830e693b5e7894ff5091007 100644 --- a/libcxx/utils/libcxx/header_information.py +++ b/libcxx/utils/libcxx/header_information.py @@ -66,6 +66,7 @@ class Header: "cmath", "csetjmp", "csignal", + "cstdalign", "cstdarg", "cstdbool", "cstddef", @@ -92,7 +93,7 @@ class Header: experimental headers. """ # These headers have been removed in C++20 so are never part of a module. - removed_in_20 = ["ccomplex", "ciso646", "cstdbool", "ctgmath"] + removed_in_20 = ["ccomplex", "ciso646", "cstdalign", "cstdbool", "ctgmath"] return self.is_public() and not self.is_experimental() and not self.is_C_compatibility() and not self._name in removed_in_20 def is_cxx03_frozen_header(self) -> bool: @@ -236,6 +237,15 @@ lit_header_restrictions = { "wctype.h": "// UNSUPPORTED: no-wide-characters", } +# Undeprecate headers that are deprecated in C++17 and removed in C++20. +lit_header_undeprecations = { + "ccomplex": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", + "ciso646": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", + "cstdalign": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", + "cstdbool": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", + "ctgmath": "// ADDITIONAL_COMPILE_FLAGS: -D_LIBCPP_DISABLE_DEPRECATION_WARNINGS", +} + # This table was produced manually, by grepping the TeX source of the Standard's # library clauses for the string "#include". Each header's synopsis contains # explicit "#include" directives for its mandatory inclusions. diff --git a/libcxxabi/src/private_typeinfo.cpp b/libcxxabi/src/private_typeinfo.cpp index 9dba91e1985e346d29a4ded66842674e287c7954..2f631041f74c94a8ebfe3e8b1266017101289ac7 100644 --- a/libcxxabi/src/private_typeinfo.cpp +++ b/libcxxabi/src/private_typeinfo.cpp @@ -41,9 +41,11 @@ // Defining _LIBCXXABI_FORGIVING_DYNAMIC_CAST does not help since can_catch() calls // is_equal() with use_strcmp=false so the string names are not compared. -#include #include +#include +#include #include + #include "abort_message.h" #ifdef _LIBCXXABI_FORGIVING_DYNAMIC_CAST diff --git a/libcxxabi/test/test_aux_runtime.pass.cpp b/libcxxabi/test/test_aux_runtime.pass.cpp index dde553864e38e7506dceb0cab9e5a762953c430d..499382c782acd16c4a4f099273ed0fa5565586cc 100644 --- a/libcxxabi/test/test_aux_runtime.pass.cpp +++ b/libcxxabi/test/test_aux_runtime.pass.cpp @@ -25,9 +25,13 @@ bool bad_typeid_test () { class A { virtual void f() {}}; class B { virtual void g() {}}; - B *bp = NULL; - try {bool b = typeid(*bp) == typeid (A); ((void)b); } - catch ( const std::bad_typeid &) { return true; } + B* bp = nullptr; + try { + bool b = typeid(*bp) == typeid(A); + ((void)b); + } catch (const std::bad_typeid&) { + return true; + } return false; } diff --git a/lld/ELF/Options.td b/lld/ELF/Options.td index c80c4017d3512cf8d1c33ef6a3166f001059f55a..ebe772042642106f8d084c50df50c0560969385b 100644 --- a/lld/ELF/Options.td +++ b/lld/ELF/Options.td @@ -720,7 +720,7 @@ def: J<"plugin-opt=opt-remarks-format=">, HelpText<"Alias for --opt-remarks-format">; def: F<"plugin-opt=opt-remarks-with-hotness">, Alias, - HelpText<"Alias for --opt-remarks-with_hotness">; + HelpText<"Alias for --opt-remarks-with-hotness">; def: J<"plugin-opt=opt-remarks-hotness-threshold=">, Alias, HelpText<"Alias for --opt-remarks-hotness-threshold">; diff --git a/lldb/docs/index.rst b/lldb/docs/index.rst index e2c15d872b4be2d69e6dd5da8b1c8406380dab62..fb22bdecad37e7b4c0333e4a12635636f8df3fa2 100644 --- a/lldb/docs/index.rst +++ b/lldb/docs/index.rst @@ -181,6 +181,7 @@ interesting areas to contribute to lldb. Source Code Releases + Discord Discussion Forums Developer Policy Bug Reports diff --git a/lldb/docs/resources/test.rst b/lldb/docs/resources/test.rst index 715d3772fe2787c0640ff25a0bbdcdee006b1222..5f1bd0d5738305e357b50a97fe0cd3acc6957082 100644 --- a/lldb/docs/resources/test.rst +++ b/lldb/docs/resources/test.rst @@ -418,8 +418,8 @@ An overview of all LLDB builders can be found here: `https://lab.llvm.org/buildbot/#/builders?tags=lldb `_ Building and testing for macOS uses a different platform called GreenDragon. It -has a dedicated tab for LLDB: `https://green.lab.llvm.org/green/view/LLDB/ -`_ +has a dedicated tab for LLDB: `https://green.lab.llvm.org/job/llvm.org/view/LLDB/ +`_ Running The Tests diff --git a/lldb/include/lldb/Breakpoint/BreakpointLocation.h b/lldb/include/lldb/Breakpoint/BreakpointLocation.h index cca00335bc3c67d44c16eef71fb7bb304037b4ee..3592291bb2d06e9ad28a9807c44199ae8504e4cf 100644 --- a/lldb/include/lldb/Breakpoint/BreakpointLocation.h +++ b/lldb/include/lldb/Breakpoint/BreakpointLocation.h @@ -11,10 +11,12 @@ #include #include +#include #include "lldb/Breakpoint/BreakpointOptions.h" #include "lldb/Breakpoint/StoppointHitCounter.h" #include "lldb/Core/Address.h" +#include "lldb/Symbol/LineEntry.h" #include "lldb/Utility/UserID.h" #include "lldb/lldb-private.h" @@ -282,6 +284,25 @@ public: /// Returns the breakpoint location ID. lldb::break_id_t GetID() const { return m_loc_id; } + /// Set the line entry that should be shown to users for this location. + /// It is up to the caller to verify that this is a valid entry to show. + /// The current use of this is to distinguish among line entries from a + /// virtual inlined call stack that all share the same address. + /// The line entry must have the same start address as the address for this + /// location. + bool SetPreferredLineEntry(const LineEntry &line_entry) { + if (m_address == line_entry.range.GetBaseAddress()) { + m_preferred_line_entry = line_entry; + return true; + } + assert(0 && "Tried to set a preferred line entry with a different address"); + return false; + } + + const std::optional GetPreferredLineEntry() { + return m_preferred_line_entry; + } + protected: friend class BreakpointSite; friend class BreakpointLocationList; @@ -306,6 +327,16 @@ protected: /// If it returns false we should continue, otherwise stop. bool IgnoreCountShouldStop(); + /// If this location knows that the virtual stack frame it represents is + /// not frame 0, return the suggested stack frame instead. This will happen + /// when the location's address contains a "virtual inlined call stack" and + /// the breakpoint was set on a file & line that are not at the bottom of that + /// stack. For now we key off the "preferred line entry" - looking for that + /// in the blocks that start with the stop PC. + /// This version of the API doesn't take an "inlined" parameter because it + /// only changes frames in the inline stack. + std::optional GetSuggestedStackFrameIndex(); + private: void SwapLocation(lldb::BreakpointLocationSP swap_from); @@ -369,6 +400,11 @@ private: lldb::break_id_t m_loc_id; ///< Breakpoint location ID. StoppointHitCounter m_hit_counter; ///< Number of times this breakpoint /// location has been hit. + /// If this exists, use it to print the stop description rather than the + /// LineEntry m_address resolves to directly. Use this for instance when the + /// location was given somewhere in the virtual inlined call stack since the + /// Address always resolves to the lowest entry in the stack. + std::optional m_preferred_line_entry; void SetShouldResolveIndirectFunctions(bool do_resolve) { m_should_resolve_indirect_functions = do_resolve; diff --git a/lldb/include/lldb/Breakpoint/BreakpointSite.h b/lldb/include/lldb/Breakpoint/BreakpointSite.h index 17b76d51c1ae53a980ca488c52f4f73885d70587..7b3f7be23639f27c22919b31d32cd8b3721557d7 100644 --- a/lldb/include/lldb/Breakpoint/BreakpointSite.h +++ b/lldb/include/lldb/Breakpoint/BreakpointSite.h @@ -170,6 +170,11 @@ public: /// \see lldb::DescriptionLevel void GetDescription(Stream *s, lldb::DescriptionLevel level); + // This runs through all the breakpoint locations owning this site and returns + // the greatest of their suggested stack frame indexes. This only handles + // inlined stack changes. + std::optional GetSuggestedStackFrameIndex(); + /// Tell whether a breakpoint has a location at this site. /// /// \param[in] bp_id diff --git a/lldb/include/lldb/Core/Declaration.h b/lldb/include/lldb/Core/Declaration.h index 4a0e9047b54695e4d555ac90cd3fa0ea92ae7c26..c864b88c6b32a37dcc5296671fa4a86cddf0371b 100644 --- a/lldb/include/lldb/Core/Declaration.h +++ b/lldb/include/lldb/Core/Declaration.h @@ -84,10 +84,14 @@ public: /// \param[in] declaration /// The const Declaration object to compare with. /// + /// \param[in] full + /// Same meaning as Full in FileSpec::Equal. True means an empty + /// directory is not equal to a specified one, false means it is equal. + /// /// \return /// Returns \b true if \b declaration is at the same file and /// line, \b false otherwise. - bool FileAndLineEqual(const Declaration &declaration) const; + bool FileAndLineEqual(const Declaration &declaration, bool full) const; /// Dump a description of this object to a Stream. /// diff --git a/lldb/include/lldb/Host/Editline.h b/lldb/include/lldb/Host/Editline.h index a02f90891599adbcd28c6dadb2560c733dfd035e..57e2c831e3499dfb072131add85c47f0b9c042d7 100644 --- a/lldb/include/lldb/Host/Editline.h +++ b/lldb/include/lldb/Host/Editline.h @@ -30,9 +30,6 @@ #include "lldb/Host/Config.h" -#if LLDB_EDITLINE_USE_WCHAR -#include -#endif #include #include #include @@ -57,23 +54,6 @@ #include "llvm/ADT/FunctionExtras.h" -#if defined(__clang__) && defined(__has_warning) -#if __has_warning("-Wdeprecated-declarations") -#define LLDB_DEPRECATED_WARNING_DISABLE \ - _Pragma("clang diagnostic push") \ - _Pragma("clang diagnostic ignored \"-Wdeprecated-declarations\"") -#define LLDB_DEPRECATED_WARNING_RESTORE _Pragma("clang diagnostic pop") -#endif -#elif defined(__GNUC__) && __GNUC__ > 6 -#define LLDB_DEPRECATED_WARNING_DISABLE \ - _Pragma("GCC diagnostic push") \ - _Pragma("GCC diagnostic ignored \"-Wdeprecated-declarations\"") -#define LLDB_DEPRECATED_WARNING_RESTORE _Pragma("GCC diagnostic pop") -#else -#define LLDB_DEPRECATED_WARNING_DISABLE -#define LLDB_DEPRECATED_WARNING_RESTORE -#endif - namespace lldb_private { namespace line_editor { @@ -383,11 +363,6 @@ private: void SetEditLinePromptCallback(EditlinePromptCallbackType callbackFn); void SetGetCharacterFunction(EditlineGetCharCallbackType callbackFn); -#if LLDB_EDITLINE_USE_WCHAR - LLDB_DEPRECATED_WARNING_DISABLE - std::wstring_convert> m_utf8conv; - LLDB_DEPRECATED_WARNING_RESTORE -#endif ::EditLine *m_editline = nullptr; EditlineHistorySP m_history_sp; bool m_in_history = false; diff --git a/lldb/include/lldb/Target/StopInfo.h b/lldb/include/lldb/Target/StopInfo.h index fae90364deaf0a3b6907a0094092d9918bebf5d1..45beac129e86f7af801959cd0787d1dc30374c14 100644 --- a/lldb/include/lldb/Target/StopInfo.h +++ b/lldb/include/lldb/Target/StopInfo.h @@ -77,6 +77,18 @@ public: m_description.clear(); } + /// This gives the StopInfo a chance to suggest a stack frame to select. + /// Passing true for inlined_stack will request changes to the inlined + /// call stack. Passing false will request changes to the real stack + /// frame. The inlined stack gets adjusted before we call into the thread + /// plans so they can reason based on the correct values. The real stack + /// adjustment is handled after the frame recognizers get a chance to adjust + /// the frame. + virtual std::optional + GetSuggestedStackFrameIndex(bool inlined_stack) { + return {}; + } + virtual bool IsValidForOperatingSystemThread(Thread &thread) { return true; } /// A Continue operation can result in a false stop event diff --git a/lldb/include/lldb/Target/ThreadPlanStepInRange.h b/lldb/include/lldb/Target/ThreadPlanStepInRange.h index f9ef87942a7c03d3eb96a190aa0c240a70aa60ae..9da8370ef1c9250bc8832ddeff3251d4ef23cb51 100644 --- a/lldb/include/lldb/Target/ThreadPlanStepInRange.h +++ b/lldb/include/lldb/Target/ThreadPlanStepInRange.h @@ -80,8 +80,8 @@ private: bool m_step_past_prologue; // FIXME: For now hard-coded to true, we could put // a switch in for this if there's // demand for that. - bool m_virtual_step; // true if we've just done a "virtual step", i.e. just - // moved the inline stack depth. + LazyBool m_virtual_step; // true if we've just done a "virtual step", i.e. + // just moved the inline stack depth. ConstString m_step_into_target; ThreadPlanStepInRange(const ThreadPlanStepInRange &) = delete; const ThreadPlanStepInRange & diff --git a/lldb/packages/Python/lldbsuite/test/configuration.py b/lldb/packages/Python/lldbsuite/test/configuration.py index 1bacd74a968c319803ac1cdc64b1fd1f191a768c..bcc179346836d1086ce96408e3ab710c2443abb5 100644 --- a/lldb/packages/Python/lldbsuite/test/configuration.py +++ b/lldb/packages/Python/lldbsuite/test/configuration.py @@ -46,6 +46,10 @@ sdkroot = None make_path = None # The overriden dwarf verison. +# Don't use this to test the current compiler's +# DWARF version, as this won't be set if the +# version isn't overridden. +# Use lldbplatformutils.getDwarfVersion() instead. dwarf_version = 0 # Any overridden settings. diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py index 63748a71f1122d83dea31a753ae2a4cdee6b7ebf..c29992ce9c7848e9d8254910b2599758270b11e1 100644 --- a/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py +++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-dap/dap_server.py @@ -793,8 +793,6 @@ class DebugCommunication(object): args_dict["env"] = env if stopOnEntry: args_dict["stopOnEntry"] = stopOnEntry - if disableASLR: - args_dict["disableASLR"] = disableASLR if disableSTDIO: args_dict["disableSTDIO"] = disableSTDIO if shellExpandArguments: @@ -829,6 +827,7 @@ class DebugCommunication(object): if customThreadFormat: args_dict["customThreadFormat"] = customThreadFormat + args_dict["disableASLR"] = disableASLR args_dict["enableAutoVariableSummaries"] = enableAutoVariableSummaries args_dict["enableSyntheticChildDebugging"] = enableSyntheticChildDebugging args_dict["displayExtendedBacktrace"] = displayExtendedBacktrace diff --git a/lldb/source/Breakpoint/BreakpointLocation.cpp b/lldb/source/Breakpoint/BreakpointLocation.cpp index ad9057c8141e99b9bfb09215b8da563481463cab..c7ea50407ae1c776947ad0a9d433f29578d7b523 100644 --- a/lldb/source/Breakpoint/BreakpointLocation.cpp +++ b/lldb/source/Breakpoint/BreakpointLocation.cpp @@ -508,8 +508,20 @@ void BreakpointLocation::GetDescription(Stream *s, s->PutCString("re-exported target = "); else s->PutCString("where = "); + + // If there's a preferred line entry for printing, use that. + bool show_function_info = true; + if (auto preferred = GetPreferredLineEntry()) { + sc.line_entry = *preferred; + // FIXME: We're going to get the function name wrong when the preferred + // line entry is not the lowest one. For now, just leave the function + // out in this case, but we really should also figure out how to easily + // fake the function name here. + show_function_info = false; + } sc.DumpStopContext(s, m_owner.GetTarget().GetProcessSP().get(), m_address, - false, true, false, true, true, true); + false, true, false, show_function_info, + show_function_info, show_function_info); } else { if (sc.module_sp) { s->EOL(); @@ -537,7 +549,10 @@ void BreakpointLocation::GetDescription(Stream *s, if (sc.line_entry.line > 0) { s->EOL(); s->Indent("location = "); - sc.line_entry.DumpStopContext(s, true); + if (auto preferred = GetPreferredLineEntry()) + preferred->DumpStopContext(s, true); + else + sc.line_entry.DumpStopContext(s, true); } } else { @@ -656,6 +671,50 @@ void BreakpointLocation::SendBreakpointLocationChangedEvent( } } +std::optional BreakpointLocation::GetSuggestedStackFrameIndex() { + auto preferred_opt = GetPreferredLineEntry(); + if (!preferred_opt) + return {}; + LineEntry preferred = *preferred_opt; + SymbolContext sc; + if (!m_address.CalculateSymbolContext(&sc)) + return {}; + // Don't return anything special if frame 0 is the preferred line entry. + // We not really telling the stack frame list to do anything special in that + // case. + if (!LineEntry::Compare(sc.line_entry, preferred)) + return {}; + + if (!sc.block) + return {}; + + // Blocks have their line info in Declaration form, so make one here: + Declaration preferred_decl(preferred.GetFile(), preferred.line, + preferred.column); + + uint32_t depth = 0; + Block *inlined_block = sc.block->GetContainingInlinedBlock(); + while (inlined_block) { + // If we've moved to a block that this isn't the start of, that's not + // our inlining info or call site, so we can stop here. + Address start_address; + if (!inlined_block->GetStartAddress(start_address) || + start_address != m_address) + return {}; + + const InlineFunctionInfo *info = inlined_block->GetInlinedFunctionInfo(); + if (info) { + if (preferred_decl == info->GetDeclaration()) + return depth; + if (preferred_decl == info->GetCallSite()) + return depth + 1; + } + inlined_block = inlined_block->GetInlinedParent(); + depth++; + } + return {}; +} + void BreakpointLocation::SwapLocation(BreakpointLocationSP swap_from) { m_address = swap_from->m_address; m_should_resolve_indirect_functions = diff --git a/lldb/source/Breakpoint/BreakpointResolver.cpp b/lldb/source/Breakpoint/BreakpointResolver.cpp index 8307689c7640cfe9f333e83e3ee31fd316cf0103..9643602d78c751d73af597030d16cb1f6cfa2dee 100644 --- a/lldb/source/Breakpoint/BreakpointResolver.cpp +++ b/lldb/source/Breakpoint/BreakpointResolver.cpp @@ -340,6 +340,21 @@ void BreakpointResolver::AddLocation(SearchFilter &filter, } BreakpointLocationSP bp_loc_sp(AddLocation(line_start)); + // If the address that we resolved the location to returns a different + // LineEntry from the one in the incoming SC, we're probably dealing with an + // inlined call site, so set that as the preferred LineEntry: + LineEntry resolved_entry; + if (!skipped_prologue && bp_loc_sp && + line_start.CalculateSymbolContextLineEntry(resolved_entry) && + LineEntry::Compare(resolved_entry, sc.line_entry)) { + // FIXME: The function name will also be wrong here. Do we need to record + // that as well, or can we figure that out again when we report this + // breakpoint location. + if (!bp_loc_sp->SetPreferredLineEntry(sc.line_entry)) { + LLDB_LOG(log, "Tried to add a preferred line entry that didn't have the " + "same address as this location's address."); + } + } if (log && bp_loc_sp && !GetBreakpoint()->IsInternal()) { StreamString s; bp_loc_sp->GetDescription(&s, lldb::eDescriptionLevelVerbose); diff --git a/lldb/source/Breakpoint/BreakpointSite.cpp b/lldb/source/Breakpoint/BreakpointSite.cpp index 3ca93f908e30b8be99c593391d7e2e7695d3e4df..9700a57d3346e0b1d895e713cdb16e56d7a602b3 100644 --- a/lldb/source/Breakpoint/BreakpointSite.cpp +++ b/lldb/source/Breakpoint/BreakpointSite.cpp @@ -87,6 +87,23 @@ void BreakpointSite::GetDescription(Stream *s, lldb::DescriptionLevel level) { m_constituents.GetDescription(s, level); } +std::optional BreakpointSite::GetSuggestedStackFrameIndex() { + + std::optional result; + std::lock_guard guard(m_constituents_mutex); + for (BreakpointLocationSP loc_sp : m_constituents.BreakpointLocations()) { + std::optional loc_frame_index = + loc_sp->GetSuggestedStackFrameIndex(); + if (loc_frame_index) { + if (result) + result = std::max(*loc_frame_index, *result); + else + result = loc_frame_index; + } + } + return result; +} + bool BreakpointSite::IsInternal() const { return m_constituents.IsInternal(); } uint8_t *BreakpointSite::GetTrapOpcodeBytes() { return &m_trap_opcode[0]; } diff --git a/lldb/source/Commands/CommandObjectType.cpp b/lldb/source/Commands/CommandObjectType.cpp index f9786529bcdb1c89ffcffda028aeec0d4ebcf507..e4c6e374446e8277bcb7c1cca4aecc9a7cb2191b 100644 --- a/lldb/source/Commands/CommandObjectType.cpp +++ b/lldb/source/Commands/CommandObjectType.cpp @@ -2649,6 +2649,8 @@ public: return false; LanguageType lt1 = lang1->GetLanguageType(); LanguageType lt2 = lang2->GetLanguageType(); + if (lt1 == lt2) + return false; if (lt1 == guessed_language) return true; // make the selected frame's language come first if (lt2 == guessed_language) diff --git a/lldb/source/Core/Declaration.cpp b/lldb/source/Core/Declaration.cpp index 579a3999d14ea09737f819c3b26a6f0e33095198..a485c4b9ba48a7d5d1d55b1c52808287f8ec92a1 100644 --- a/lldb/source/Core/Declaration.cpp +++ b/lldb/source/Core/Declaration.cpp @@ -70,8 +70,9 @@ int Declaration::Compare(const Declaration &a, const Declaration &b) { return 0; } -bool Declaration::FileAndLineEqual(const Declaration &declaration) const { - int file_compare = FileSpec::Compare(this->m_file, declaration.m_file, true); +bool Declaration::FileAndLineEqual(const Declaration &declaration, + bool full) const { + int file_compare = FileSpec::Compare(this->m_file, declaration.m_file, full); return file_compare == 0 && this->m_line == declaration.m_line; } diff --git a/lldb/source/Core/SourceManager.cpp b/lldb/source/Core/SourceManager.cpp index fd5b49946c6a927ff6cb55f9f6ba2eab14cd1e04..27a9edeef4249e0fbba82eda0524b6e70ec8bb30 100644 --- a/lldb/source/Core/SourceManager.cpp +++ b/lldb/source/Core/SourceManager.cpp @@ -430,7 +430,7 @@ SourceManager::GetDefaultFileAndLine() { false; // Force it to be a debug symbol. function_options.include_inlines = true; executable_ptr->FindFunctions(main_name, CompilerDeclContext(), - lldb::eFunctionNameTypeBase, + lldb::eFunctionNameTypeFull, function_options, sc_list); for (const SymbolContext &sc : sc_list) { if (sc.function) { diff --git a/lldb/source/Host/common/Editline.cpp b/lldb/source/Host/common/Editline.cpp index 60117cb5f0e615a61bba5c4fc92a64cdbf515dac..f95f854c5f220c5dff5e0867edc9ae6fc9f7188d 100644 --- a/lldb/source/Host/common/Editline.cpp +++ b/lldb/source/Host/common/Editline.cpp @@ -10,9 +10,8 @@ #include #include -#include "lldb/Host/Editline.h" - #include "lldb/Host/ConnectionFileDescriptor.h" +#include "lldb/Host/Editline.h" #include "lldb/Host/FileSystem.h" #include "lldb/Host/Host.h" #include "lldb/Utility/CompletionRequest.h" @@ -23,6 +22,7 @@ #include "lldb/Utility/StreamString.h" #include "lldb/Utility/StringList.h" #include "lldb/Utility/Timeout.h" +#include "llvm/Support/ConvertUTF.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Locale.h" @@ -444,7 +444,9 @@ StringList Editline::GetInputAsStringList(int line_count) { if (line_count == 0) break; #if LLDB_EDITLINE_USE_WCHAR - lines.AppendString(m_utf8conv.to_bytes(line)); + std::string buffer; + llvm::convertWideToUTF8(line, buffer); + lines.AppendString(buffer); #else lines.AppendString(line); #endif @@ -636,7 +638,9 @@ unsigned char Editline::BreakLineCommand(int ch) { if (m_fix_indentation_callback) { StringList lines = GetInputAsStringList(m_current_line_index + 1); #if LLDB_EDITLINE_USE_WCHAR - lines.AppendString(m_utf8conv.to_bytes(new_line_fragment)); + std::string buffer; + llvm::convertWideToUTF8(new_line_fragment, buffer); + lines.AppendString(buffer); #else lines.AppendString(new_line_fragment); #endif @@ -684,8 +688,9 @@ unsigned char Editline::EndOrAddLineCommand(int ch) { m_input_lines.clear(); for (unsigned index = 0; index < lines.GetSize(); index++) { #if LLDB_EDITLINE_USE_WCHAR - m_input_lines.insert(m_input_lines.end(), - m_utf8conv.from_bytes(lines[index])); + std::wstring wbuffer; + llvm::ConvertUTF8toWide(lines[index], wbuffer); + m_input_lines.insert(m_input_lines.end(), wbuffer); #else m_input_lines.insert(m_input_lines.end(), lines[index]); #endif @@ -869,7 +874,9 @@ unsigned char Editline::FixIndentationCommand(int ch) { currentLine = currentLine.erase(0, -indent_correction); } #if LLDB_EDITLINE_USE_WCHAR - m_input_lines[m_current_line_index] = m_utf8conv.from_bytes(currentLine); + std::wstring wbuffer; + llvm::ConvertUTF8toWide(currentLine, wbuffer); + m_input_lines[m_current_line_index] = wbuffer; #else m_input_lines[m_current_line_index] = currentLine; #endif @@ -1502,7 +1509,7 @@ bool Editline::GetLine(std::string &line, bool &interrupted) { } else { m_history_sp->Enter(input); #if LLDB_EDITLINE_USE_WCHAR - line = m_utf8conv.to_bytes(SplitLines(input)[0]); + llvm::convertWideToUTF8(SplitLines(input)[0], line); #else line = SplitLines(input)[0]; #endif @@ -1574,25 +1581,22 @@ bool Editline::CompleteCharacter(char ch, EditLineGetCharType &out) { out = (unsigned char)ch; return true; #else - LLDB_DEPRECATED_WARNING_DISABLE - std::codecvt_utf8 cvt; - LLDB_DEPRECATED_WARNING_RESTORE llvm::SmallString<4> input; for (;;) { - const char *from_next; - wchar_t *to_next; - std::mbstate_t state = std::mbstate_t(); input.push_back(ch); - switch (cvt.in(state, input.begin(), input.end(), from_next, &out, &out + 1, - to_next)) { - case std::codecvt_base::ok: + auto *cur_ptr = reinterpret_cast(input.begin()); + auto *end_ptr = reinterpret_cast(input.end()); + llvm::UTF32 code_point = 0; + llvm::ConversionResult cr = llvm::convertUTF8Sequence( + &cur_ptr, end_ptr, &code_point, llvm::lenientConversion); + switch (cr) { + case llvm::conversionOK: + out = code_point; return out != (EditLineGetCharType)WEOF; - - case std::codecvt_base::error: - case std::codecvt_base::noconv: + case llvm::targetExhausted: + case llvm::sourceIllegal: return false; - - case std::codecvt_base::partial: + case llvm::sourceExhausted: lldb::ConnectionStatus status; size_t read_count = m_input_connection.Read( &ch, 1, std::chrono::seconds(0), status, nullptr); diff --git a/lldb/source/Host/common/FileAction.cpp b/lldb/source/Host/common/FileAction.cpp index f980d3224640e070d345561c2cd50aaf8ceb7f18..e1c3e14a165ea97fa0b66e2513e733edbcbbb06e 100644 --- a/lldb/source/Host/common/FileAction.cpp +++ b/lldb/source/Host/common/FileAction.cpp @@ -41,7 +41,7 @@ bool FileAction::Open(int fd, const FileSpec &file_spec, bool read, else if (read) m_arg = O_NOCTTY | O_RDONLY; else - m_arg = O_NOCTTY | O_CREAT | O_WRONLY; + m_arg = O_NOCTTY | O_CREAT | O_WRONLY | O_TRUNC; m_file_spec = file_spec; return true; } else { diff --git a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp index 7cc38da6a6a94b964184b16907f1b1ba3aed29b6..7c2b6517468ff4c424fea835acd6bc44716c3934 100644 --- a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp +++ b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp @@ -92,7 +92,33 @@ namespace { struct InitializePythonRAII { public: InitializePythonRAII() { - InitializePythonHome(); +#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 8) || (PY_MAJOR_VERSION > 3) + PyConfig config; + PyConfig_InitPythonConfig(&config); +#endif + +#if LLDB_EMBED_PYTHON_HOME + static std::string g_python_home = []() -> std::string { + if (llvm::sys::path::is_absolute(LLDB_PYTHON_HOME)) + return LLDB_PYTHON_HOME; + + FileSpec spec = HostInfo::GetShlibDir(); + if (!spec) + return {}; + spec.AppendPathComponent(LLDB_PYTHON_HOME); + return spec.GetPath(); + }(); + if (!g_python_home.empty()) { +#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 8) || (PY_MAJOR_VERSION > 3) + PyConfig_SetBytesString(&config, &config.home, g_python_home.c_str()); +#else + size_t size = 0; + wchar_t *python_home_w = Py_DecodeLocale(g_python_home.c_str(), &size); + Py_SetPythonHome(python_home_w); + PyMem_RawFree(python_home_w); +#endif + } +#endif // The table of built-in modules can only be extended before Python is // initialized. @@ -117,15 +143,22 @@ public: PyImport_AppendInittab("_lldb", LLDBSwigPyInit); } +#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 8) || (PY_MAJOR_VERSION > 3) + config.install_signal_handlers = 0; + Py_InitializeFromConfig(&config); + PyConfig_Clear(&config); + InitializeThreadsPrivate(); +#else // Python < 3.2 and Python >= 3.2 reversed the ordering requirements for // calling `Py_Initialize` and `PyEval_InitThreads`. < 3.2 requires that you // call `PyEval_InitThreads` first, and >= 3.2 requires that you call it last. -#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 2) || (PY_MAJOR_VERSION > 3) +#if (PY_MAJOR_VERSION == 3 && PY_MINOR_VERSION >= 2) Py_InitializeEx(0); InitializeThreadsPrivate(); #else InitializeThreadsPrivate(); Py_InitializeEx(0); +#endif #endif } @@ -142,32 +175,6 @@ public: } private: - void InitializePythonHome() { -#if LLDB_EMBED_PYTHON_HOME - typedef wchar_t *str_type; - static str_type g_python_home = []() -> str_type { - const char *lldb_python_home = LLDB_PYTHON_HOME; - const char *absolute_python_home = nullptr; - llvm::SmallString<64> path; - if (llvm::sys::path::is_absolute(lldb_python_home)) { - absolute_python_home = lldb_python_home; - } else { - FileSpec spec = HostInfo::GetShlibDir(); - if (!spec) - return nullptr; - spec.GetPath(path); - llvm::sys::path::append(path, lldb_python_home); - absolute_python_home = path.c_str(); - } - size_t size = 0; - return Py_DecodeLocale(absolute_python_home, &size); - }(); - if (g_python_home != nullptr) { - Py_SetPythonHome(g_python_home); - } -#endif - } - void InitializeThreadsPrivate() { // Since Python 3.7 `Py_Initialize` calls `PyEval_InitThreads` inside itself, // so there is no way to determine whether the embedded interpreter @@ -446,8 +453,9 @@ ScriptInterpreterPythonImpl::ScriptInterpreterPythonImpl(Debugger &debugger) // Reloading modules requires a different syntax in Python 2 and Python 3. // This provides a consistent syntax no matter what version of Python. run_string.Clear(); - run_string.Printf("run_one_line (%s, 'from importlib import reload as reload_module')", - m_dictionary_name.c_str()); + run_string.Printf( + "run_one_line (%s, 'from importlib import reload as reload_module')", + m_dictionary_name.c_str()); PyRun_SimpleString(run_string.GetData()); // WARNING: temporary code that loads Cocoa formatters - this should be done @@ -763,21 +771,19 @@ llvm::Expected ScriptInterpreterPythonImpl::GetMaxPositionalArgumentsForCallable( const llvm::StringRef &callable_name) { if (callable_name.empty()) { - return llvm::createStringError( - llvm::inconvertibleErrorCode(), - "called with empty callable name."); - } - Locker py_lock(this, Locker::AcquireLock | - Locker::InitSession | - Locker::NoSTDIN); - auto dict = PythonModule::MainModule() - .ResolveName(m_dictionary_name); + return llvm::createStringError(llvm::inconvertibleErrorCode(), + "called with empty callable name."); + } + Locker py_lock(this, + Locker::AcquireLock | Locker::InitSession | Locker::NoSTDIN); + auto dict = PythonModule::MainModule().ResolveName( + m_dictionary_name); auto pfunc = PythonObject::ResolveNameWithDictionary( callable_name, dict); if (!pfunc.IsAllocated()) { - return llvm::createStringError( - llvm::inconvertibleErrorCode(), - "can't find callable: %s", callable_name.str().c_str()); + return llvm::createStringError(llvm::inconvertibleErrorCode(), + "can't find callable: %s", + callable_name.str().c_str()); } llvm::Expected arg_info = pfunc.GetArgInfo(); if (!arg_info) @@ -1259,8 +1265,7 @@ Status ScriptInterpreterPythonImpl::SetBreakpointCommandCallback( // Set a Python one-liner as the callback for the watchpoint. void ScriptInterpreterPythonImpl::SetWatchpointCommandCallback( - WatchpointOptions *wp_options, const char *user_input, - bool is_callback) { + WatchpointOptions *wp_options, const char *user_input, bool is_callback) { auto data_up = std::make_unique(); // It's necessary to set both user_source and script_source to the oneliner. @@ -1286,8 +1291,7 @@ Status ScriptInterpreterPythonImpl::ExportFunctionDefinitionToInterpreter( std::string function_def_string(function_def.CopyList()); Status error = ExecuteMultipleLines( - function_def_string.c_str(), - ExecuteScriptOptions().SetEnableIO(false)); + function_def_string.c_str(), ExecuteScriptOptions().SetEnableIO(false)); return error; } @@ -2068,7 +2072,8 @@ int ScriptInterpreterPythonImpl::GetIndexOfChildWithName( { Locker py_lock(this, Locker::AcquireLock | Locker::InitSession | Locker::NoSTDIN); - ret_val = SWIGBridge::LLDBSwigPython_GetIndexOfChildWithName(implementor, child_name); + ret_val = SWIGBridge::LLDBSwigPython_GetIndexOfChildWithName(implementor, + child_name); } return ret_val; @@ -2460,7 +2465,8 @@ bool ScriptInterpreterPythonImpl::LoadScriptingModule( // the lifetime of the process in which this LLDB framework is living. const bool does_contain_executed = ExecuteOneLineWithReturn( command_stream.GetData(), - ScriptInterpreterPythonImpl::eScriptReturnTypeBool, &does_contain, exc_options); + ScriptInterpreterPythonImpl::eScriptReturnTypeBool, &does_contain, + exc_options); const bool was_imported_globally = does_contain_executed && does_contain; const bool was_imported_locally = @@ -2677,7 +2683,7 @@ bool ScriptInterpreterPythonImpl::RunScriptBasedParsedCommand( args_arr_sp->AddStringItem(entry.ref()); } StructuredDataImpl args_impl(args_arr_sp); - + ret_val = SWIGBridge::LLDBSwigPythonCallParsedCommandObject( static_cast(impl_obj_sp->GetValue()), debugger_sp, args_impl, cmd_retobj, exe_ctx_ref_sp); @@ -2779,8 +2785,7 @@ bool ScriptInterpreterPythonImpl::GetDocumentationForItem(const char *item, if (ExecuteOneLineWithReturn( command, ScriptInterpreter::eScriptReturnTypeCharStrOrNone, - &result_ptr, - ExecuteScriptOptions().SetEnableIO(false))) { + &result_ptr, ExecuteScriptOptions().SetEnableIO(false))) { if (result_ptr) dest.assign(result_ptr); return true; @@ -2878,7 +2883,7 @@ uint32_t ScriptInterpreterPythonImpl::GetFlagsForCommandObject( return result; } -StructuredData::ObjectSP +StructuredData::ObjectSP ScriptInterpreterPythonImpl::GetOptionsForCommandObject( StructuredData::GenericSP cmd_obj_sp) { StructuredData::ObjectSP result = {}; @@ -2923,10 +2928,10 @@ ScriptInterpreterPythonImpl::GetOptionsForCommandObject( PyErr_Clear(); return {}; } - return py_return.CreateStructuredObject(); + return py_return.CreateStructuredObject(); } -StructuredData::ObjectSP +StructuredData::ObjectSP ScriptInterpreterPythonImpl::GetArgumentsForCommandObject( StructuredData::GenericSP cmd_obj_sp) { StructuredData::ObjectSP result = {}; @@ -2971,11 +2976,10 @@ ScriptInterpreterPythonImpl::GetArgumentsForCommandObject( PyErr_Clear(); return {}; } - return py_return.CreateStructuredObject(); + return py_return.CreateStructuredObject(); } -void -ScriptInterpreterPythonImpl::OptionParsingStartedForCommandObject( +void ScriptInterpreterPythonImpl::OptionParsingStartedForCommandObject( StructuredData::GenericSP cmd_obj_sp) { Locker py_lock(this, Locker::AcquireLock | Locker::NoSTDIN, Locker::FreeLock); @@ -2983,7 +2987,7 @@ ScriptInterpreterPythonImpl::OptionParsingStartedForCommandObject( static char callee_name[] = "option_parsing_started"; if (!cmd_obj_sp) - return ; + return; PythonObject implementor(PyRefType::Borrowed, (PyObject *)cmd_obj_sp->GetValue()); @@ -3009,10 +3013,9 @@ ScriptInterpreterPythonImpl::OptionParsingStartedForCommandObject( if (PyErr_Occurred()) PyErr_Clear(); - // option_parsing_starting doesn't return anything, ignore anything but + // option_parsing_starting doesn't return anything, ignore anything but // python errors. - unwrapOrSetPythonException( - As(implementor.CallMethod(callee_name))); + unwrapOrSetPythonException(As(implementor.CallMethod(callee_name))); // if it fails, print the error but otherwise go on if (PyErr_Occurred()) { @@ -3022,8 +3025,7 @@ ScriptInterpreterPythonImpl::OptionParsingStartedForCommandObject( } } -bool -ScriptInterpreterPythonImpl::SetOptionValueForCommandObject( +bool ScriptInterpreterPythonImpl::SetOptionValueForCommandObject( StructuredData::GenericSP cmd_obj_sp, ExecutionContext *exe_ctx, llvm::StringRef long_option, llvm::StringRef value) { StructuredData::ObjectSP result = {}; @@ -3058,15 +3060,15 @@ ScriptInterpreterPythonImpl::SetOptionValueForCommandObject( if (PyErr_Occurred()) PyErr_Clear(); - + lldb::ExecutionContextRefSP exe_ctx_ref_sp; if (exe_ctx) exe_ctx_ref_sp.reset(new ExecutionContextRef(exe_ctx)); PythonObject ctx_ref_obj = SWIGBridge::ToSWIGWrapper(exe_ctx_ref_sp); - - bool py_return = unwrapOrSetPythonException( - As(implementor.CallMethod(callee_name, ctx_ref_obj, long_option.str().c_str(), - value.str().c_str()))); + + bool py_return = unwrapOrSetPythonException(As( + implementor.CallMethod(callee_name, ctx_ref_obj, + long_option.str().c_str(), value.str().c_str()))); // if it fails, print the error but otherwise go on if (PyErr_Occurred()) { diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp index dee90804c52584056a9fd3823d7fedd990059b4d..c18edd10b9681997b791fb2417c253760dd21820 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp @@ -151,3 +151,19 @@ bool DWARFIndex::ProcessTypeDIEMatchQuery( return true; return callback(die); } + +void DWARFIndex::GetNamespacesWithParents( + ConstString name, const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref callback) { + GetNamespaces(name, [&](DWARFDIE die) { + return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, callback); + }); +} + +bool DWARFIndex::ProcessNamespaceDieMatchParents( + const CompilerDeclContext &parent_decl_ctx, DWARFDIE die, + llvm::function_ref callback) { + if (!SymbolFileDWARF::DIEInDeclContext(parent_decl_ctx, die)) + return true; + return callback(die); +} diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h index fea3a4fd697389f67d40ddb90ce4c18860654d99..ac1f75e91c2195469084c3a57903a0016a60f4f0 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h @@ -71,6 +71,14 @@ public: virtual void GetTypesWithQuery(TypeQuery &query, llvm::function_ref callback); + /// Get namespace DIEs whose base name match \param name with \param + /// parent_decl_ctx in its decl parent chain. A base implementation + /// is provided. Specializations should override this if they are able to + /// provide a faster implementation. + virtual void + GetNamespacesWithParents(ConstString name, + const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref callback); virtual void GetFunctions(const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, @@ -127,6 +135,9 @@ protected: bool ProcessTypeDIEMatchQuery(TypeQuery &query, DWARFDIE die, llvm::function_ref callback); + bool ProcessNamespaceDieMatchParents( + const CompilerDeclContext &parent_decl_ctx, DWARFDIE die, + llvm::function_ref callback); }; } // namespace dwarf } // namespace lldb_private::plugin diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp index c809e5ff7f85353da87cf1bc53df226a4fe51dd5..6f2cb455ec00e154464c81d6f8a2988f87be3bc8 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.cpp @@ -368,9 +368,10 @@ void DebugNamesDWARFIndex::GetFullyQualifiedType( continue; } - if (SameParentChain(parent_names, *parent_chain) && - !ProcessEntry(entry, callback)) - return; + if (SameParentChain(parent_names, *parent_chain)) { + if (!ProcessEntry(entry, callback)) + return; + } } m_fallback.GetFullyQualifiedType(context, callback); } @@ -554,17 +555,60 @@ void DebugNamesDWARFIndex::GetTypesWithQuery( continue; } - if (WithinParentChain(parent_contexts, *parent_chain) && - !ProcessEntry(entry, [&](DWARFDIE die) { - // After .debug_names filtering still sending to base class for - // further filtering before calling the callback. - return ProcessTypeDIEMatchQuery(query, die, callback); - })) - return; + if (WithinParentChain(parent_contexts, *parent_chain)) { + if (!ProcessEntry(entry, [&](DWARFDIE die) { + // After .debug_names filtering still sending to base class for + // further filtering before calling the callback. + return ProcessTypeDIEMatchQuery(query, die, callback); + })) + // If the callback returns false, we're done. + return; + } } m_fallback.GetTypesWithQuery(query, callback); } +void DebugNamesDWARFIndex::GetNamespacesWithParents( + ConstString name, const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref callback) { + std::vector parent_contexts = + parent_decl_ctx.GetCompilerContext(); + llvm::SmallVector parent_named_contexts; + std::copy_if(parent_contexts.rbegin(), parent_contexts.rend(), + std::back_inserter(parent_named_contexts), + [](const CompilerContext &ctx) { return !ctx.name.IsEmpty(); }); + for (const DebugNames::Entry &entry : + m_debug_names_up->equal_range(name.GetStringRef())) { + lldb_private::dwarf::Tag entry_tag = entry.tag(); + if (entry_tag == DW_TAG_namespace || + entry_tag == DW_TAG_imported_declaration) { + std::optional> parent_chain = + getParentChain(entry); + if (!parent_chain) { + // Fallback: use the base class implementation. + if (!ProcessEntry(entry, [&](DWARFDIE die) { + return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, + callback); + })) + return; + continue; + } + + if (WithinParentChain(parent_named_contexts, *parent_chain)) { + if (!ProcessEntry(entry, [&](DWARFDIE die) { + // After .debug_names filtering still sending to base class for + // further filtering before calling the callback. + return ProcessNamespaceDieMatchParents(parent_decl_ctx, die, + callback); + })) + // If the callback returns false, we're done. + return; + } + } + } + m_fallback.GetNamespacesWithParents(name, parent_decl_ctx, callback); +} + void DebugNamesDWARFIndex::GetFunctions( const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h index 074f68a8c55963df129aadc456bd752bd9ed6139..ab6cde12623f6ab897d9907b5dd7cb87b0184b45 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DebugNamesDWARFIndex.h @@ -55,7 +55,9 @@ public: void GetTypesWithQuery(TypeQuery &query, llvm::function_ref callback) override; - + void GetNamespacesWithParents( + ConstString name, const CompilerDeclContext &parent_decl_ctx, + llvm::function_ref callback) override; void GetFunctions(const Module::LookupInfo &lookup_info, SymbolFileDWARF &dwarf, const CompilerDeclContext &parent_decl_ctx, diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp index e5b8eee8d08c24641c8d4299ea7e2bfc93dde127..f23f8cc3d781d036e571a5e9294ed37f17437f8b 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp @@ -2900,7 +2900,7 @@ SymbolFileDWARF::FindNamespace(ConstString name, if (!DeclContextMatchesThisSymbolFile(parent_decl_ctx)) return namespace_decl_ctx; - m_index->GetNamespaces(name, [&](DWARFDIE die) { + m_index->GetNamespacesWithParents(name, parent_decl_ctx, [&](DWARFDIE die) { if (!DIEInDeclContext(parent_decl_ctx, die, only_root_namespaces)) return true; // The containing decl contexts don't match diff --git a/lldb/source/Symbol/Block.cpp b/lldb/source/Symbol/Block.cpp index f7d9c0d2d3306565b28728fdfc5d3a3cdea6bd03..5c7772a6db780d3d78a4c6d735789cc1c0efa63c 100644 --- a/lldb/source/Symbol/Block.cpp +++ b/lldb/source/Symbol/Block.cpp @@ -230,7 +230,7 @@ Block *Block::GetContainingInlinedBlockWithCallSite( const auto *function_info = inlined_block->GetInlinedFunctionInfo(); if (function_info && - function_info->GetCallSite().FileAndLineEqual(find_call_site)) + function_info->GetCallSite().FileAndLineEqual(find_call_site, true)) return inlined_block; inlined_block = inlined_block->GetInlinedParent(); } diff --git a/lldb/source/Symbol/CompileUnit.cpp b/lldb/source/Symbol/CompileUnit.cpp index db8f8ce6bcbc9235d406c49bb37d7af7ab82a2ee..73389b2e8479b37443188f211cb7a7e73b94b760 100644 --- a/lldb/source/Symbol/CompileUnit.cpp +++ b/lldb/source/Symbol/CompileUnit.cpp @@ -251,7 +251,10 @@ void CompileUnit::ResolveSymbolContext( SymbolContextItem resolve_scope, SymbolContextList &sc_list, RealpathPrefixes *realpath_prefixes) { const FileSpec file_spec = src_location_spec.GetFileSpec(); - const uint32_t line = src_location_spec.GetLine().value_or(0); + const uint32_t line = + src_location_spec.GetLine().value_or(LLDB_INVALID_LINE_NUMBER); + const uint32_t column_num = + src_location_spec.GetColumn().value_or(LLDB_INVALID_COLUMN_NUMBER); const bool check_inlines = src_location_spec.GetCheckInlines(); // First find all of the file indexes that match our "file_spec". If @@ -268,7 +271,7 @@ void CompileUnit::ResolveSymbolContext( SymbolContext sc(GetModule()); sc.comp_unit = this; - if (line == 0) { + if (line == LLDB_INVALID_LINE_NUMBER) { if (file_spec_matches_cu_file_spec && !check_inlines) { // only append the context if we aren't looking for inline call sites by // file and line and if the file spec matches that of the compile unit @@ -312,6 +315,112 @@ void CompileUnit::ResolveSymbolContext( 0, file_indexes, src_location_spec, &line_entry); } + // If we didn't manage to find a breakpoint that matched the line number + // requested, that might be because it is only an inline call site, and + // doesn't have a line entry in the line table. Scan for that here. + // + // We are making the assumption that if there was an inlined function it will + // contribute at least 1 non-call-site entry to the line table. That's handy + // because we don't move line breakpoints over function boundaries, so if we + // found a hit, and there were also a call site entry, it would have to be in + // the function containing the PC of the line table match. That way we can + // limit the call site search to that function. + // We will miss functions that ONLY exist as a call site entry. + + if (line_entry.IsValid() && + (line_entry.line != line || line_entry.column != column_num) && + resolve_scope & eSymbolContextLineEntry && check_inlines) { + // We don't move lines over function boundaries, so the address in the + // line entry will be the in function that contained the line that might + // be a CallSite, and we can just iterate over that function to find any + // inline records, and dig up their call sites. + Address start_addr = line_entry.range.GetBaseAddress(); + Function *function = start_addr.CalculateSymbolContextFunction(); + + Declaration sought_decl(file_spec, line, column_num); + // We use this recursive function to descend the block structure looking + // for a block that has this Declaration as in it's CallSite info. + // This function recursively scans the sibling blocks of the incoming + // block parameter. + std::function examine_block = + [&sought_decl, &sc_list, &src_location_spec, resolve_scope, + &examine_block](Block &block) -> void { + // Iterate over the sibling child blocks of the incoming block. + Block *sibling_block = block.GetFirstChild(); + while (sibling_block) { + // We only have to descend through the regular blocks, looking for + // immediate inlines, since those are the only ones that will have this + // callsite. + const InlineFunctionInfo *inline_info = + sibling_block->GetInlinedFunctionInfo(); + if (inline_info) { + // If this is the call-site we are looking for, record that: + // We need to be careful because the call site from the debug info + // will generally have a column, but the user might not have specified + // it. + Declaration found_decl = inline_info->GetCallSite(); + uint32_t sought_column = sought_decl.GetColumn(); + if (found_decl.FileAndLineEqual(sought_decl, false) && + (sought_column == LLDB_INVALID_COLUMN_NUMBER || + sought_column == found_decl.GetColumn())) { + // If we found a call site, it belongs not in this inlined block, + // but in the parent block that inlined it. + Address parent_start_addr; + if (sibling_block->GetParent()->GetStartAddress( + parent_start_addr)) { + SymbolContext sc; + parent_start_addr.CalculateSymbolContext(&sc, resolve_scope); + // Now swap out the line entry for the one we found. + LineEntry call_site_line = sc.line_entry; + call_site_line.line = found_decl.GetLine(); + call_site_line.column = found_decl.GetColumn(); + bool matches_spec = true; + // If the user asked for an exact match, we need to make sure the + // call site we found actually matches the location. + if (src_location_spec.GetExactMatch()) { + matches_spec = false; + if ((src_location_spec.GetFileSpec() == + sc.line_entry.GetFile()) && + (src_location_spec.GetLine() && + *src_location_spec.GetLine() == call_site_line.line) && + (src_location_spec.GetColumn() && + *src_location_spec.GetColumn() == call_site_line.column)) + matches_spec = true; + } + if (matches_spec && + sibling_block->GetRangeAtIndex(0, call_site_line.range)) { + SymbolContext call_site_sc(sc.target_sp, sc.module_sp, + sc.comp_unit, sc.function, sc.block, + &call_site_line, sc.symbol); + sc_list.Append(call_site_sc); + } + } + } + } + + // Descend into the child blocks: + examine_block(*sibling_block); + // Now go to the next sibling: + sibling_block = sibling_block->GetSibling(); + } + }; + + if (function) { + // We don't need to examine the function block, it can't be inlined. + Block &func_block = function->GetBlock(true); + examine_block(func_block); + } + // If we found entries here, we are done. We only get here because we + // didn't find an exact line entry for this line & column, but if we found + // an exact match from the call site info that's strictly better than + // continuing to look for matches further on in the file. + // FIXME: Should I also do this for "call site line exists between the + // given line number and the later line we found in the line table"? That's + // a closer approximation to our general sliding algorithm. + if (sc_list.GetSize()) + return; + } + // If "exact == true", then "found_line" will be the same as "line". If // "exact == false", the "found_line" will be the closest line entry // with a line number greater than "line" and we will use this for our diff --git a/lldb/source/Target/StackFrameList.cpp b/lldb/source/Target/StackFrameList.cpp index 3849ec5ed178d9a7c38e23ed3b60eec489d3f696..94a381edd5e202793e6762d8548eb3ac3138088b 100644 --- a/lldb/source/Target/StackFrameList.cpp +++ b/lldb/source/Target/StackFrameList.cpp @@ -85,121 +85,32 @@ void StackFrameList::ResetCurrentInlinedDepth() { return; std::lock_guard guard(m_mutex); - - GetFramesUpTo(0, DoNotAllowInterruption); - if (m_frames.empty()) - return; - if (!m_frames[0]->IsInlined()) { - m_current_inlined_depth = UINT32_MAX; - m_current_inlined_pc = LLDB_INVALID_ADDRESS; - Log *log = GetLog(LLDBLog::Step); - if (log && log->GetVerbose()) - LLDB_LOGF( - log, - "ResetCurrentInlinedDepth: Invalidating current inlined depth.\n"); - return; - } - // We only need to do something special about inlined blocks when we are - // at the beginning of an inlined function: - // FIXME: We probably also have to do something special if the PC is at - // the END of an inlined function, which coincides with the end of either - // its containing function or another inlined function. - - Block *block_ptr = m_frames[0]->GetFrameBlock(); - if (!block_ptr) - return; + m_current_inlined_pc = LLDB_INVALID_ADDRESS; + m_current_inlined_depth = UINT32_MAX; - Address pc_as_address; - lldb::addr_t curr_pc = m_thread.GetRegisterContext()->GetPC(); - pc_as_address.SetLoadAddress(curr_pc, &(m_thread.GetProcess()->GetTarget())); - AddressRange containing_range; - if (!block_ptr->GetRangeContainingAddress(pc_as_address, containing_range) || - pc_as_address != containing_range.GetBaseAddress()) - return; - - // If we got here because of a breakpoint hit, then set the inlined depth - // depending on where the breakpoint was set. If we got here because of a - // crash, then set the inlined depth to the deepest most block. Otherwise, - // we stopped here naturally as the result of a step, so set ourselves in the - // containing frame of the whole set of nested inlines, so the user can then - // "virtually" step into the frames one by one, or next over the whole mess. - // Note: We don't have to handle being somewhere in the middle of the stack - // here, since ResetCurrentInlinedDepth doesn't get called if there is a - // valid inlined depth set. StopInfoSP stop_info_sp = m_thread.GetStopInfo(); if (!stop_info_sp) return; - switch (stop_info_sp->GetStopReason()) { - case eStopReasonWatchpoint: - case eStopReasonException: - case eStopReasonExec: - case eStopReasonFork: - case eStopReasonVFork: - case eStopReasonVForkDone: - case eStopReasonSignal: - // In all these cases we want to stop in the deepest frame. - m_current_inlined_pc = curr_pc; - m_current_inlined_depth = 0; - break; - case eStopReasonBreakpoint: { - // FIXME: Figure out what this break point is doing, and set the inline - // depth appropriately. Be careful to take into account breakpoints that - // implement step over prologue, since that should do the default - // calculation. For now, if the breakpoints corresponding to this hit are - // all internal, I set the stop location to the top of the inlined stack, - // since that will make things like stepping over prologues work right. - // But if there are any non-internal breakpoints I do to the bottom of the - // stack, since that was the old behavior. - uint32_t bp_site_id = stop_info_sp->GetValue(); - BreakpointSiteSP bp_site_sp( - m_thread.GetProcess()->GetBreakpointSiteList().FindByID(bp_site_id)); - bool all_internal = true; - if (bp_site_sp) { - uint32_t num_owners = bp_site_sp->GetNumberOfConstituents(); - for (uint32_t i = 0; i < num_owners; i++) { - Breakpoint &bp_ref = - bp_site_sp->GetConstituentAtIndex(i)->GetBreakpoint(); - if (!bp_ref.IsInternal()) { - all_internal = false; - } - } - } - if (!all_internal) { - m_current_inlined_pc = curr_pc; - m_current_inlined_depth = 0; - break; - } - } - [[fallthrough]]; - default: { - // Otherwise, we should set ourselves at the container of the inlining, so - // that the user can descend into them. So first we check whether we have - // more than one inlined block sharing this PC: - int num_inlined_functions = 0; - - for (Block *container_ptr = block_ptr->GetInlinedParent(); - container_ptr != nullptr; - container_ptr = container_ptr->GetInlinedParent()) { - if (!container_ptr->GetRangeContainingAddress(pc_as_address, - containing_range)) - break; - if (pc_as_address != containing_range.GetBaseAddress()) - break; - num_inlined_functions++; - } - m_current_inlined_pc = curr_pc; - m_current_inlined_depth = num_inlined_functions + 1; - Log *log = GetLog(LLDBLog::Step); + bool inlined = true; + auto inline_depth = stop_info_sp->GetSuggestedStackFrameIndex(inlined); + // We're only adjusting the inlined stack here. + Log *log = GetLog(LLDBLog::Step); + if (inline_depth) { + m_current_inlined_depth = *inline_depth; + m_current_inlined_pc = m_thread.GetRegisterContext()->GetPC(); + if (log && log->GetVerbose()) LLDB_LOGF(log, "ResetCurrentInlinedDepth: setting inlined " "depth: %d 0x%" PRIx64 ".\n", - m_current_inlined_depth, curr_pc); - - break; - } + m_current_inlined_depth, m_current_inlined_pc); + } else { + if (log && log->GetVerbose()) + LLDB_LOGF( + log, + "ResetCurrentInlinedDepth: Invalidating current inlined depth.\n"); } } @@ -816,19 +727,48 @@ void StackFrameList::SelectMostRelevantFrame() { RecognizedStackFrameSP recognized_frame_sp = frame_sp->GetRecognizedFrame(); - if (!recognized_frame_sp) { - LLDB_LOG(log, "Frame #0 not recognized"); - return; + if (recognized_frame_sp) { + if (StackFrameSP most_relevant_frame_sp = + recognized_frame_sp->GetMostRelevantFrame()) { + LLDB_LOG(log, "Found most relevant frame at index {0}", + most_relevant_frame_sp->GetFrameIndex()); + SetSelectedFrame(most_relevant_frame_sp.get()); + return; + } } + LLDB_LOG(log, "Frame #0 not recognized"); - if (StackFrameSP most_relevant_frame_sp = - recognized_frame_sp->GetMostRelevantFrame()) { - LLDB_LOG(log, "Found most relevant frame at index {0}", - most_relevant_frame_sp->GetFrameIndex()); - SetSelectedFrame(most_relevant_frame_sp.get()); - } else { - LLDB_LOG(log, "No relevant frame!"); + // If this thread has a non-trivial StopInof, then let it suggest + // a most relevant frame: + StopInfoSP stop_info_sp = m_thread.GetStopInfo(); + uint32_t stack_idx = 0; + bool found_relevant = false; + if (stop_info_sp) { + // Here we're only asking the stop info if it wants to adjust the real stack + // index. We have to ask about the m_inlined_stack_depth in + // Thread::ShouldStop since the plans need to reason with that info. + bool inlined = false; + std::optional stack_opt = + stop_info_sp->GetSuggestedStackFrameIndex(inlined); + if (stack_opt) { + stack_idx = *stack_opt; + found_relevant = true; + } } + + frame_sp = GetFrameAtIndex(stack_idx); + if (!frame_sp) + LLDB_LOG(log, "Stop info suggested relevant frame {0} but it didn't exist", + stack_idx); + else if (found_relevant) + LLDB_LOG(log, "Setting selected frame from stop info to {0}", stack_idx); + // Note, we don't have to worry about "inlined" frames here, because we've + // already calculated the inlined frame in Thread::ShouldStop, and + // SetSelectedFrame will take care of that adjustment for us. + SetSelectedFrame(frame_sp.get()); + + if (!found_relevant) + LLDB_LOG(log, "No relevant frame!"); } uint32_t StackFrameList::GetSelectedFrameIndex( @@ -841,6 +781,7 @@ uint32_t StackFrameList::GetSelectedFrameIndex( // isn't set, then don't force a selection here, just return 0. if (!select_most_relevant) return 0; + // If the inlined stack frame is set, then use that: m_selected_frame_idx = 0; } return *m_selected_frame_idx; diff --git a/lldb/source/Target/StopInfo.cpp b/lldb/source/Target/StopInfo.cpp index 60aa65ed38c7494fa4e908ceac08808c0bb8018a..f6387d47504e626a1b3ccabe83e734abd967fcfe 100644 --- a/lldb/source/Target/StopInfo.cpp +++ b/lldb/source/Target/StopInfo.cpp @@ -15,6 +15,7 @@ #include "lldb/Breakpoint/WatchpointResource.h" #include "lldb/Core/Debugger.h" #include "lldb/Expression/UserExpression.h" +#include "lldb/Symbol/Block.h" #include "lldb/Target/Process.h" #include "lldb/Target/StopInfo.h" #include "lldb/Target/Target.h" @@ -246,6 +247,22 @@ public: return m_description.c_str(); } + std::optional + GetSuggestedStackFrameIndex(bool inlined_stack) override { + if (!inlined_stack) + return {}; + + ThreadSP thread_sp(m_thread_wp.lock()); + if (!thread_sp) + return {}; + BreakpointSiteSP bp_site_sp( + thread_sp->GetProcess()->GetBreakpointSiteList().FindByID(m_value)); + if (!bp_site_sp) + return {}; + + return bp_site_sp->GetSuggestedStackFrameIndex(); + } + protected: bool ShouldStop(Event *event_ptr) override { // This just reports the work done by PerformAction or the synchronous @@ -1164,6 +1181,44 @@ public: else return m_description.c_str(); } + + std::optional + GetSuggestedStackFrameIndex(bool inlined_stack) override { + // Trace only knows how to adjust inlined stacks: + if (!inlined_stack) + return {}; + + ThreadSP thread_sp = GetThread(); + StackFrameSP frame_0_sp = thread_sp->GetStackFrameAtIndex(0); + if (!frame_0_sp) + return {}; + if (!frame_0_sp->IsInlined()) + return {}; + Block *block_ptr = frame_0_sp->GetFrameBlock(); + if (!block_ptr) + return {}; + Address pc_address = frame_0_sp->GetFrameCodeAddress(); + AddressRange containing_range; + if (!block_ptr->GetRangeContainingAddress(pc_address, containing_range) || + pc_address != containing_range.GetBaseAddress()) + return {}; + + int num_inlined_functions = 0; + + for (Block *container_ptr = block_ptr->GetInlinedParent(); + container_ptr != nullptr; + container_ptr = container_ptr->GetInlinedParent()) { + if (!container_ptr->GetRangeContainingAddress(pc_address, + containing_range)) + break; + if (pc_address != containing_range.GetBaseAddress()) + break; + + num_inlined_functions++; + } + inlined_stack = true; + return num_inlined_functions + 1; + } }; // StopInfoException diff --git a/lldb/source/Target/Thread.cpp b/lldb/source/Target/Thread.cpp index 8373cdc36268f8d56133d19e39e720957f6e4861..735295e6f25937afaa5d3487fb85a0eb57812a2f 100644 --- a/lldb/source/Target/Thread.cpp +++ b/lldb/source/Target/Thread.cpp @@ -619,6 +619,14 @@ void Thread::WillStop() { void Thread::SetupForResume() { if (GetResumeState() != eStateSuspended) { + // First check whether this thread is going to "actually" resume at all. + // For instance, if we're stepping from one level to the next of an + // virtual inlined call stack, we just change the inlined call stack index + // without actually running this thread. In that case, for this thread we + // shouldn't push a step over breakpoint plan or do that work. + if (GetCurrentPlan()->IsVirtualStep()) + return; + // If we're at a breakpoint push the step-over breakpoint plan. Do this // before telling the current plan it will resume, since we might change // what the current plan is. diff --git a/lldb/source/Target/ThreadPlanStepInRange.cpp b/lldb/source/Target/ThreadPlanStepInRange.cpp index 567dcc26d0d3727c8152a8bb9d2b76c3d09ecf86..224a17d896ccf02da6237c8683ba1d822572b76b 100644 --- a/lldb/source/Target/ThreadPlanStepInRange.cpp +++ b/lldb/source/Target/ThreadPlanStepInRange.cpp @@ -41,7 +41,7 @@ ThreadPlanStepInRange::ThreadPlanStepInRange( "Step Range stepping in", thread, range, addr_context, stop_others), ThreadPlanShouldStopHere(this), m_step_past_prologue(true), - m_virtual_step(false), m_step_into_target(step_into_target) { + m_virtual_step(eLazyBoolCalculate), m_step_into_target(step_into_target) { SetCallbacks(); SetFlagsToDefault(); SetupAvoidNoDebug(step_in_avoids_code_without_debug_info, @@ -149,7 +149,7 @@ bool ThreadPlanStepInRange::ShouldStop(Event *event_ptr) { m_sub_plan_sp.reset(); } - if (m_virtual_step) { + if (m_virtual_step == eLazyBoolYes) { // If we've just completed a virtual step, all we need to do is check for a // ShouldStopHere plan, and otherwise we're done. // FIXME - This can be both a step in and a step out. Probably should @@ -431,7 +431,7 @@ bool ThreadPlanStepInRange::DoPlanExplainsStop(Event *event_ptr) { bool return_value = false; - if (m_virtual_step) { + if (m_virtual_step == eLazyBoolYes) { return_value = true; } else { StopInfoSP stop_info_sp = GetPrivateStopInfo(); @@ -460,10 +460,13 @@ bool ThreadPlanStepInRange::DoPlanExplainsStop(Event *event_ptr) { bool ThreadPlanStepInRange::DoWillResume(lldb::StateType resume_state, bool current_plan) { - m_virtual_step = false; + m_virtual_step = eLazyBoolCalculate; if (resume_state == eStateStepping && current_plan) { Thread &thread = GetThread(); // See if we are about to step over a virtual inlined call. + // But if we already know we're virtual stepping, don't decrement the + // inlined depth again... + bool step_without_resume = thread.DecrementCurrentInlinedDepth(); if (step_without_resume) { Log *log = GetLog(LLDBLog::Step); @@ -476,11 +479,21 @@ bool ThreadPlanStepInRange::DoWillResume(lldb::StateType resume_state, // FIXME: Maybe it would be better to create a InlineStep stop reason, but // then // the whole rest of the world would have to handle that stop reason. - m_virtual_step = true; + m_virtual_step = eLazyBoolYes; } return !step_without_resume; } return true; } -bool ThreadPlanStepInRange::IsVirtualStep() { return m_virtual_step; } +bool ThreadPlanStepInRange::IsVirtualStep() { + if (m_virtual_step == eLazyBoolCalculate) { + Thread &thread = GetThread(); + uint32_t cur_inline_depth = thread.GetCurrentInlinedDepth(); + if (cur_inline_depth == UINT32_MAX || cur_inline_depth == 0) + m_virtual_step = eLazyBoolNo; + else + m_virtual_step = eLazyBoolYes; + } + return m_virtual_step == eLazyBoolYes; +} diff --git a/lldb/source/Target/ThreadPlanStepOverRange.cpp b/lldb/source/Target/ThreadPlanStepOverRange.cpp index ef5b4b5c434d16ed6fe260cb2a5a3d378dd218d3..643ee827c865cb88b906aa8e74c058a5563c8a59 100644 --- a/lldb/source/Target/ThreadPlanStepOverRange.cpp +++ b/lldb/source/Target/ThreadPlanStepOverRange.cpp @@ -402,7 +402,7 @@ bool ThreadPlanStepOverRange::DoWillResume(lldb::StateType resume_state, if (in_inlined_stack) { Log *log = GetLog(LLDBLog::Step); LLDB_LOGF(log, - "ThreadPlanStepInRange::DoWillResume: adjusting range to " + "ThreadPlanStepOverRange::DoWillResume: adjusting range to " "the frame at inlined depth %d.", thread.GetCurrentInlinedDepth()); StackFrameSP stack_sp = thread.GetStackFrameAtIndex(0); diff --git a/lldb/test/API/commands/settings/TestSettings.py b/lldb/test/API/commands/settings/TestSettings.py index 385acceb7a8b5c1d94cdb2ec8f554c79d3014b55..2dd813f6b155b3651f82622b77e7e0835befb29c 100644 --- a/lldb/test/API/commands/settings/TestSettings.py +++ b/lldb/test/API/commands/settings/TestSettings.py @@ -528,6 +528,59 @@ class SettingsCommandTestCase(TestBase): output, exe=False, startstr="This message should go to standard out." ) + @skipIfDarwinEmbedded # debugserver on ios etc can't write files + def test_same_error_output_path(self): + """Test that setting target.error and output-path to the same file path for the launched process works.""" + self.build() + + exe = self.getBuildArtifact("a.out") + self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET) + + # Set the error-path and output-path and verify both are set. + self.runCmd( + "settings set target.error-path '{0}'".format( + lldbutil.append_to_process_working_directory(self, "output.txt") + ) + ) + self.runCmd( + "settings set target.output-path '{0}".format( + lldbutil.append_to_process_working_directory(self, "output.txt") + ) + ) + # And add hooks to restore the original settings during tearDown(). + self.addTearDownHook(lambda: self.runCmd("settings clear target.output-path")) + self.addTearDownHook(lambda: self.runCmd("settings clear target.error-path")) + + self.expect( + "settings show target.error-path", + SETTING_MSG("target.error-path"), + substrs=["target.error-path (file)", 'output.txt"'], + ) + + self.expect( + "settings show target.output-path", + SETTING_MSG("target.output-path"), + substrs=["target.output-path (file)", 'output.txt"'], + ) + + self.runCmd( + "process launch --working-dir '{0}'".format( + self.get_process_working_directory() + ), + RUN_SUCCEEDED, + ) + + output = lldbutil.read_file_from_process_wd(self, "output.txt") + err_message = "This message should go to standard error." + out_message = "This message should go to standard out." + # Error msg should get flushed by the output msg + self.expect(output, exe=False, substrs=[out_message]) + self.assertNotIn( + err_message, + output, + "Race condition when both stderr/stdout redirects to the same file", + ) + def test_print_dictionary_setting(self): self.runCmd("settings clear target.env-vars") self.runCmd('settings set target.env-vars ["MY_VAR"]=some-value') diff --git a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/TestInitializerList.py b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/TestInitializerList.py index 0919eb3c5dd8127ffccd3e31a43079dbda64ca44..93d5392830b508ebc4cc214e01e1ed3f244417bd 100644 --- a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/TestInitializerList.py +++ b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/initializerlist/TestInitializerList.py @@ -40,5 +40,3 @@ class InitializerListTestCase(TestBase): "frame variable ils", substrs=['[4] = "surprise it is a long string!! yay!!"'], ) - - self.expect("image list", substrs=self.getLibcPlusPlusLibs()) diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py b/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py index 5eb3fc3cada921abb5fea430de4a668e2f3bfba9..08ac9290ee85accaee02db31107b2936a7736a26 100644 --- a/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py +++ b/lldb/test/API/functionalities/gdb_remote_client/TestGDBRemoteClient.py @@ -132,12 +132,39 @@ class TestGDBRemoteClient(GDBRemoteTestBase): target = self.createTarget("a.yaml") process = self.connect(target) - self.assertEqual(1, self.server.responder.packetLog.count("g")) - self.server.responder.packetLog = [] + # We want to make sure that the process is using the g packet, but it's + # not required the "connect" should read all registers. However, it might + # have... So we need to wait till we explicitly 'read_registers' to do + # test. + # Also, even with the use-g-packet-for-reading lldb will sometimes send p0 + # early on to see if the packet is supported. So we can't say that there + # will be NO p packets. + # But there certainly should be no p packets after the g packet. + self.read_registers(process) - # Reading registers should not cause any 'p' packets to be exchanged. + print(f"\nPACKET LOG:\n{self.server.responder.packetLog}\n") + g_pos = 0 + try: + g_pos = self.server.responder.packetLog.index("g") + except err: + self.fail("'g' packet not found after fetching registers") + + try: + second_g = self.server.responder.packetLog.index("g", g_pos) + self.fail("Found more than one 'g' packet") + except: + pass + + # Make sure there aren't any `p` packets after the `g` packet: self.assertEqual( - 0, len([p for p in self.server.responder.packetLog if p.startswith("p")]) + 0, + len( + [ + p + for p in self.server.responder.packetLog[g_pos:] + if p.startswith("p") + ] + ), ) def test_read_registers_using_p_packets(self): diff --git a/lldb/test/API/functionalities/inline-stepping/TestInlineStepping.py b/lldb/test/API/functionalities/inline-stepping/TestInlineStepping.py index 752c3a9cbd286a8423932806614aeb4be450bc32..3283918f8527431a15af7e555618ab40e6b3aea7 100644 --- a/lldb/test/API/functionalities/inline-stepping/TestInlineStepping.py +++ b/lldb/test/API/functionalities/inline-stepping/TestInlineStepping.py @@ -32,6 +32,12 @@ class TestInlineStepping(TestBase): self.build() self.step_in_template() + @add_test_categories(["pyapi"]) + def test_virtual_inline_stepping(self): + """Test stepping through a virtual inlined call stack""" + self.build() + self.virtual_inline_stepping() + def setUp(self): # Call super's setUp(). TestBase.setUp(self) @@ -357,3 +363,76 @@ class TestInlineStepping(TestBase): step_sequence = [["// In max_value specialized", "into"]] self.run_step_sequence(step_sequence) + + def run_to_call_site_and_step( + self, source_regex, func_name, start_pos, one_more_step_loc=None + ): + main_spec = lldb.SBFileSpec("calling.cpp") + # Set the breakpoint by file and line, not sourced regex because + # we want to make sure we can set breakpoints on call sites: + call_site_line_num = line_number(self.main_source, source_regex) + target, process, thread, bkpt = lldbutil.run_to_line_breakpoint( + self, main_spec, call_site_line_num + ) + + # Make sure that the location is at the call site (run_to_line_breakpoint already asserted + # that there's one location.): + bkpt_loc = bkpt.location[0] + strm = lldb.SBStream() + result = bkpt_loc.GetDescription(strm, lldb.eDescriptionLevelFull) + + self.assertTrue(result, "Got a location description") + desc = strm.GetData() + self.assertIn(f"calling.cpp:{call_site_line_num}", desc, "Right line listed") + # We don't get the function name right yet - so we omit it in printing. + # Turn on this test when that is working. + # self.assertIn(func_name, desc, "Right function listed") + + pc = thread.frame[0].pc + for i in range(start_pos, 3): + thread.StepInto() + frame_0 = thread.frame[0] + + trivial_line_num = line_number( + self.main_source, f"In caller_trivial_inline_{i}." + ) + self.assertEqual( + frame_0.line_entry.line, + trivial_line_num, + f"Stepped into the caller_trivial_inline_{i}", + ) + if pc != frame_0.pc: + # If we get here, we stepped to the expected line number, but + # the compiler on this system has decided to insert an instruction + # between the call site of an inlined function with no arguments, + # returning void, and its immediate call to another void inlined function + # with no arguments. We aren't going to be testing virtual inline + # stepping for this function... + break + + if one_more_step_loc: + thread.StepInto() + frame_0 = thread.frame[0] + self.assertEqual( + frame_0.line_entry.line, + line_number(self.main_source, one_more_step_loc), + "Was able to step one more time", + ) + process.Kill() + target.Clear() + + def virtual_inline_stepping(self): + """Use the Python API's to step through a virtual inlined stack""" + self.run_to_call_site_and_step("At caller_trivial_inline_1", "main", 1) + self.run_to_call_site_and_step( + "In caller_trivial_inline_1", "caller_trivial_inline_1", 2 + ) + self.run_to_call_site_and_step( + "In caller_trivial_inline_2", "caller_trivial_inline_2", 3 + ) + self.run_to_call_site_and_step( + "In caller_trivial_inline_3", + "caller_trivial_inline_3", + 4, + "After caller_trivial_inline_3", + ) diff --git a/lldb/test/API/functionalities/inline-stepping/calling.cpp b/lldb/test/API/functionalities/inline-stepping/calling.cpp index 49179ce7c97883cbf83b54419a70036a98ab72b1..ba71c25a3c648f8bcf1e3bab153b8ca56c8a54ce 100644 --- a/lldb/test/API/functionalities/inline-stepping/calling.cpp +++ b/lldb/test/API/functionalities/inline-stepping/calling.cpp @@ -13,6 +13,12 @@ int called_by_inline_ref (int &value); inline void inline_trivial_1 () __attribute__((always_inline)); inline void inline_trivial_2 () __attribute__((always_inline)); +// These three should share the same initial pc so we can test +// virtual inline stepping. +inline void caller_trivial_inline_1() __attribute__((always_inline)); +inline void caller_trivial_inline_2() __attribute__((always_inline)); +inline void caller_trivial_inline_3() __attribute__((always_inline)); + void caller_trivial_1 (); void caller_trivial_2 (); @@ -79,6 +85,23 @@ caller_trivial_2 () inline_value += 1; // At increment in caller_trivial_2. } +// When you call caller_trivial_inline_1, the inlined call-site +// should share a PC with all three of the following inlined +// functions, so we can exercise "virtual inline stepping". +void caller_trivial_inline_1() { + caller_trivial_inline_2(); // In caller_trivial_inline_1. + inline_value += 1; +} + +void caller_trivial_inline_2() { + caller_trivial_inline_3(); // In caller_trivial_inline_2. + inline_value += 1; // After caller_trivial_inline_3 +} + +void caller_trivial_inline_3() { + inline_value += 1; // In caller_trivial_inline_3. +} + void called_by_inline_trivial () { @@ -132,5 +155,7 @@ main (int argc, char **argv) max_value(123, 456); // Call max_value template max_value(std::string("abc"), std::string("0022")); // Call max_value specialized + caller_trivial_inline_1(); // At caller_trivial_inline_1. + return 0; // About to return from main. } diff --git a/lldb/test/API/lang/cpp/namespace/TestNamespaceLookup.py b/lldb/test/API/lang/cpp/namespace/TestNamespaceLookup.py index b5e8115160d209ec75ac621ca2e70739396113d5..41141164769ec27a2c19868a795854a16f795ba3 100644 --- a/lldb/test/API/lang/cpp/namespace/TestNamespaceLookup.py +++ b/lldb/test/API/lang/cpp/namespace/TestNamespaceLookup.py @@ -8,7 +8,7 @@ import lldb from lldbsuite.test.decorators import * from lldbsuite.test.lldbtest import * from lldbsuite.test import lldbutil - +from lldbsuite.test import lldbplatformutil class NamespaceLookupTestCase(TestBase): def setUp(self): @@ -167,7 +167,10 @@ class NamespaceLookupTestCase(TestBase): self.runToBkpt("continue") # FIXME: In DWARF 5 with dsyms, the ordering of functions is slightly # different, which also hits the same issues mentioned previously. - if configuration.dwarf_version <= 4 or self.getDebugInfo() == "dwarf": + if ( + int(lldbplatformutil.getDwarfVersion()) <= 4 + or self.getDebugInfo() == "dwarf" + ): self.expect_expr("func()", result_type="int", result_value="2") # Continue to BP_ns_scope at ns scope diff --git a/lldb/test/API/python_api/process/io/TestProcessIO.py b/lldb/test/API/python_api/process/io/TestProcessIO.py index 5bb91d2758312df049e15f9dbb098112578aafc9..5d9727add399b59eaa894313b3803ea699d90e71 100644 --- a/lldb/test/API/python_api/process/io/TestProcessIO.py +++ b/lldb/test/API/python_api/process/io/TestProcessIO.py @@ -95,6 +95,43 @@ class ProcessIOTestCase(TestBase): error = self.read_error_file_and_delete() self.check_process_output(output, error) + @skipIfWindows # stdio manipulation unsupported on Windows + @expectedFlakeyLinux(bugnumber="llvm.org/pr26437") + @skipIfDarwinEmbedded # debugserver can't create/write files on the device + def test_stdout_stderr_redirection_to_existing_files(self): + """Exercise SBLaunchInfo::AddOpenFileAction() for STDOUT and STDERR redirect to output files already exist.""" + self.setup_test() + self.build() + self.create_target() + + # Create the output and error files with placeholder + placeholder = "This content should be overwritten." + # Local file directory and working directory are the same for local debugging + f = open(self.local_output_file, "w") + f.write(placeholder) + f.close() + f = open(self.local_error_file, "w") + f.write(placeholder) + f.close() + if lldb.remote_platform: + self.runCmd( + 'platform put-file "{local}" "{remote}"'.format( + local=self.local_output_file, remote=self.output_file + ) + ) + self.runCmd( + 'platform put-file "{local}" "{remote}"'.format( + local=self.local_error_file, remote=self.error_file + ) + ) + + self.redirect_stdout() + self.redirect_stderr() + self.run_process(True) + output = self.read_output_file_and_delete() + error = self.read_error_file_and_delete() + self.check_process_output(output, error) + # target_file - path on local file system or remote file system if running remote # local_file - path on local system def read_file_and_delete(self, target_file, local_file): diff --git a/lldb/test/API/python_api/type/TestTypeList.py b/lldb/test/API/python_api/type/TestTypeList.py index bc4d00c17c55511fbf904e682c4d6cc869defd53..09879276b44aa38dde24b02480105184649227e8 100644 --- a/lldb/test/API/python_api/type/TestTypeList.py +++ b/lldb/test/API/python_api/type/TestTypeList.py @@ -6,7 +6,7 @@ import lldb from lldbsuite.test.decorators import * from lldbsuite.test.lldbtest import * from lldbsuite.test import lldbutil - +from lldbsuite.test import lldbplatformutil class TypeAndTypeListTestCase(TestBase): def setUp(self): @@ -248,7 +248,7 @@ class TypeAndTypeListTestCase(TestBase): self.assertEqual(myint_arr_element_type, myint_type) # Test enum methods. Requires DW_AT_enum_class which was added in Dwarf 4. - if configuration.dwarf_version >= 4: + if int(lldbplatformutil.getDwarfVersion()) >= 4: enum_type = target.FindFirstType("EnumType") self.assertTrue(enum_type) self.DebugSBType(enum_type) diff --git a/lldb/tools/lldb-dap/ProgressEvent.cpp b/lldb/tools/lldb-dap/ProgressEvent.cpp index 8a660b50af1205b3390af9b5646f003281d58192..0dcc2ee81001d501aa5d232859048167c18d97b5 100644 --- a/lldb/tools/lldb-dap/ProgressEvent.cpp +++ b/lldb/tools/lldb-dap/ProgressEvent.cpp @@ -110,7 +110,6 @@ json::Value ProgressEvent::ToJSON() const { std::string progress_id_str; llvm::raw_string_ostream progress_id_strm(progress_id_str); progress_id_strm << m_progress_id; - progress_id_strm.flush(); body.try_emplace("progressId", progress_id_str); if (m_event_type == progressStart) { diff --git a/lldb/unittests/Expression/DWARFExpressionTest.cpp b/lldb/unittests/Expression/DWARFExpressionTest.cpp index f9e0605fce29d61da8c43bdc0a63b3018d252577..fdc9bfae1876c518182f2c0ba933b31e3f551d4d 100644 --- a/lldb/unittests/Expression/DWARFExpressionTest.cpp +++ b/lldb/unittests/Expression/DWARFExpressionTest.cpp @@ -181,6 +181,9 @@ TEST(DWARFExpression, DW_OP_bra) { }), // clang-format on llvm::HasValue(0x42)); + + EXPECT_THAT_ERROR(Evaluate({DW_OP_bra, 0x01, 0x00}).takeError(), + llvm::Failed()); } TEST(DWARFExpression, DW_OP_convert) { diff --git a/lldb/unittests/Host/FileActionTest.cpp b/lldb/unittests/Host/FileActionTest.cpp index b208169aac20e60f75a1a3e270a55dee6e04e32d..56227cd587e5bbea171fd403e5fd36bc4e13b7bd 100644 --- a/lldb/unittests/Host/FileActionTest.cpp +++ b/lldb/unittests/Host/FileActionTest.cpp @@ -6,8 +6,13 @@ // //===----------------------------------------------------------------------===// +#include + #include "lldb/Host/FileAction.h" #include "gtest/gtest.h" +#if defined(_WIN32) +#include "lldb/Host/windows/PosixApi.h" +#endif using namespace lldb_private; @@ -17,3 +22,26 @@ TEST(FileActionTest, Open) { EXPECT_EQ(Action.GetAction(), FileAction::eFileActionOpen); EXPECT_EQ(Action.GetFileSpec(), FileSpec("/tmp")); } + +TEST(FileActionTest, OpenReadWrite) { + FileAction Action; + Action.Open(48, FileSpec("/tmp_0"), /*read*/ true, /*write*/ true); + EXPECT_TRUE(Action.GetActionArgument() & (O_NOCTTY | O_CREAT | O_RDWR)); + EXPECT_FALSE(Action.GetActionArgument() & O_RDONLY); + EXPECT_FALSE(Action.GetActionArgument() & O_WRONLY); +} + +TEST(FileActionTest, OpenReadOnly) { + FileAction Action; + Action.Open(49, FileSpec("/tmp_1"), /*read*/ true, /*write*/ false); + EXPECT_TRUE(Action.GetActionArgument() & (O_NOCTTY | O_RDONLY)); + EXPECT_FALSE(Action.GetActionArgument() & O_WRONLY); +} + +TEST(FileActionTest, OpenWriteOnly) { + FileAction Action; + Action.Open(50, FileSpec("/tmp_2"), /*read*/ false, /*write*/ true); + EXPECT_TRUE(Action.GetActionArgument() & + (O_NOCTTY | O_CREAT | O_WRONLY | O_TRUNC)); + EXPECT_FALSE(Action.GetActionArgument() & O_RDONLY); +} diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 92a45d845f1db8ed3a96650aeeb42ece5be34c4b..d5c650e74eeb28ecb877cfc0f897b8f25f63d9ba 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -301,6 +301,8 @@ Changes to LLDB * LLDB can now read the `fpmr` register from AArch64 Linux processes and core files. +* Program stdout/stderr redirection will now open the file with O_TRUNC flag, make sure to truncate the file if path already exists. + * eg. `settings set target.output-path/target.error-path ` Changes to BOLT --------------------------------- diff --git a/llvm/include/llvm/ADT/StringRef.h b/llvm/include/llvm/ADT/StringRef.h index 0dcd4d90086eff5fec5f47f43615b6d623f4f176..5b525c8e56ecc9f2d795a2b99efa1e26eb6d4e71 100644 --- a/llvm/include/llvm/ADT/StringRef.h +++ b/llvm/include/llvm/ADT/StringRef.h @@ -60,7 +60,11 @@ namespace llvm { using const_reverse_iterator = std::reverse_iterator; private: - std::string_view View; + /// The start of the string, in an external buffer. + const char *Data = nullptr; + + /// The length of the string. + size_t Length = 0; // Workaround memcmp issue with null pointers (undefined behavior) // by providing a specialized version @@ -82,26 +86,28 @@ namespace llvm { /// Construct a string ref from a cstring. /*implicit*/ constexpr StringRef(const char *Str LLVM_LIFETIME_BOUND) - : View(Str, Str ? + : Data(Str), Length(Str ? // GCC 7 doesn't have constexpr char_traits. Fall back to __builtin_strlen. #if defined(_GLIBCXX_RELEASE) && _GLIBCXX_RELEASE < 8 - __builtin_strlen(Str) + __builtin_strlen(Str) #else - std::char_traits::length(Str) + std::char_traits::length(Str) #endif - : 0) { + : 0) { } /// Construct a string ref from a pointer and length. /*implicit*/ constexpr StringRef(const char *data LLVM_LIFETIME_BOUND, size_t length) - : View(data, length) {} + : Data(data), Length(length) {} /// Construct a string ref from an std::string. - /*implicit*/ StringRef(const std::string &Str) : View(Str) {} + /*implicit*/ StringRef(const std::string &Str) + : Data(Str.data()), Length(Str.length()) {} /// Construct a string ref from an std::string_view. - /*implicit*/ constexpr StringRef(std::string_view Str) : View(Str) {} + /*implicit*/ constexpr StringRef(std::string_view Str) + : Data(Str.data()), Length(Str.size()) {} /// @} /// @name Iterators @@ -135,13 +141,13 @@ namespace llvm { /// data - Get a pointer to the start of the string (which may not be null /// terminated). - [[nodiscard]] constexpr const char *data() const { return View.data(); } + [[nodiscard]] constexpr const char *data() const { return Data; } /// empty - Check if the string is empty. [[nodiscard]] constexpr bool empty() const { return size() == 0; } /// size - Get the string size. - [[nodiscard]] constexpr size_t size() const { return View.size(); } + [[nodiscard]] constexpr size_t size() const { return Length; } /// front - Get the first character in the string. [[nodiscard]] char front() const { diff --git a/llvm/include/llvm/ADT/TrieHashIndexGenerator.h b/llvm/include/llvm/ADT/TrieHashIndexGenerator.h new file mode 100644 index 0000000000000000000000000000000000000000..6f7e53b6b11b53975b943e0c54a618ceb23c7bb6 --- /dev/null +++ b/llvm/include/llvm/ADT/TrieHashIndexGenerator.h @@ -0,0 +1,122 @@ +//===- TrieHashIndexGenerator.h ---------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ADT_TRIEHASHINDEXGENERATOR_H +#define LLVM_ADT_TRIEHASHINDEXGENERATOR_H + +#include "llvm/ADT/ArrayRef.h" +#include + +namespace llvm { + +/// The utility class that helps computing the index of the object inside trie +/// from its hash. The generator can be configured with the number of bits +/// used for each level of trie structure with \c NumRootsBits and \c +/// NumSubtrieBits. +/// For example, try computing indexes for a 16-bit hash 0x1234 with 8-bit root +/// and 4-bit sub-trie: +/// +/// IndexGenerator IndexGen{8, 4, Hash}; +/// size_t index1 = IndexGen.next(); // index 18 in root node. +/// size_t index2 = IndexGen.next(); // index 3 in sub-trie level 1. +/// size_t index3 = IndexGen.next(); // index 4 in sub-tire level 2. +/// +/// This is used by different trie implementation to figure out where to +/// insert/find the object in the data structure. +struct TrieHashIndexGenerator { + size_t NumRootBits; + size_t NumSubtrieBits; + ArrayRef Bytes; + std::optional StartBit = std::nullopt; + + // Get the number of bits used to generate current index. + size_t getNumBits() const { + assert(StartBit); + size_t TotalNumBits = Bytes.size() * 8; + assert(*StartBit <= TotalNumBits); + return std::min(*StartBit ? NumSubtrieBits : NumRootBits, + TotalNumBits - *StartBit); + } + + // Get the index of the object in the next level of trie. + size_t next() { + if (!StartBit) { + // Compute index for root when StartBit is not set. + StartBit = 0; + return getIndex(Bytes, *StartBit, NumRootBits); + } + if (*StartBit < Bytes.size() * 8) { + // Compute index for sub-trie. + *StartBit += *StartBit ? NumSubtrieBits : NumRootBits; + assert((*StartBit - NumRootBits) % NumSubtrieBits == 0); + return getIndex(Bytes, *StartBit, NumSubtrieBits); + } + // All the bits are consumed. + return end(); + } + + // Provide a hint to speed up the index generation by providing the + // information of the hash in current level. For example, if the object is + // known to have \c Index on a level that already consumes first n \c Bits of + // the hash, it can start index generation from this level by calling \c hint + // function. + size_t hint(unsigned Index, unsigned Bit) { + assert(Bit < Bytes.size() * 8); + assert(Bit == 0 || (Bit - NumRootBits) % NumSubtrieBits == 0); + StartBit = Bit; + return Index; + } + + // Utility function for looking up the index in the trie for an object that + // has colliding hash bits in the front as the hash of the object that is + // currently being computed. + size_t getCollidingBits(ArrayRef CollidingBits) const { + assert(StartBit); + return getIndex(CollidingBits, *StartBit, NumSubtrieBits); + } + + size_t end() const { return SIZE_MAX; } + + // Compute the index for the object from its hash, current start bits, and + // the number of bits used for current level. + static size_t getIndex(ArrayRef Bytes, size_t StartBit, + size_t NumBits) { + assert(StartBit < Bytes.size() * 8); + // Drop all the bits before StartBit. + Bytes = Bytes.drop_front(StartBit / 8u); + StartBit %= 8u; + size_t Index = 0; + // Compute the index using the bits in range [StartBit, StartBit + NumBits), + // note the range can spread across few `uint8_t` in the array. + for (uint8_t Byte : Bytes) { + size_t ByteStart = 0, ByteEnd = 8; + if (StartBit) { + ByteStart = StartBit; + Byte &= (1u << (8 - StartBit)) - 1u; + StartBit = 0; + } + size_t CurrentNumBits = ByteEnd - ByteStart; + if (CurrentNumBits > NumBits) { + Byte >>= CurrentNumBits - NumBits; + CurrentNumBits = NumBits; + } + Index <<= CurrentNumBits; + Index |= Byte & ((1u << CurrentNumBits) - 1u); + + assert(NumBits >= CurrentNumBits); + NumBits -= CurrentNumBits; + if (!NumBits) + break; + } + return Index; + } +}; + +} // namespace llvm + +#endif // LLVM_ADT_TRIEHASHINDEXGENERATOR_H diff --git a/llvm/include/llvm/ADT/TrieRawHashMap.h b/llvm/include/llvm/ADT/TrieRawHashMap.h new file mode 100644 index 0000000000000000000000000000000000000000..5bfe5c9e6a0f49588718d3226a737aaa5cf60272 --- /dev/null +++ b/llvm/include/llvm/ADT/TrieRawHashMap.h @@ -0,0 +1,377 @@ +//===- TrieRawHashMap.h -----------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ADT_TRIERAWHASHMAP_H +#define LLVM_ADT_TRIERAWHASHMAP_H + +#include "llvm/ADT/ArrayRef.h" +#include +#include + +namespace llvm { + +class raw_ostream; + +/// TrieRawHashMap - is a lock-free thread-safe trie that is can be used to +/// store/index data based on a hash value. It can be customized to work with +/// any hash algorithm or store any data. +/// +/// Data structure: +/// Data node stored in the Trie contains both hash and data: +/// struct { +/// HashT Hash; +/// DataT Data; +/// }; +/// +/// Data is stored/indexed via a prefix tree, where each node in the tree can be +/// either the root, a sub-trie or a data node. Assuming a 4-bit hash and two +/// data objects {0001, A} and {0100, B}, it can be stored in a trie +/// (assuming Root has 2 bits, SubTrie has 1 bit): +/// +--------+ +/// |Root[00]| -> {0001, A} +/// | [01]| -> {0100, B} +/// | [10]| (empty) +/// | [11]| (empty) +/// +--------+ +/// +/// Inserting a new object {0010, C} will result in: +/// +--------+ +----------+ +/// |Root[00]| -> |SubTrie[0]| -> {0001, A} +/// | | | [1]| -> {0010, C} +/// | | +----------+ +/// | [01]| -> {0100, B} +/// | [10]| (empty) +/// | [11]| (empty) +/// +--------+ +/// Note object A is sunk down to a sub-trie during the insertion. All the +/// nodes are inserted through compare-exchange to ensure thread-safe and +/// lock-free. +/// +/// To find an object in the trie, walk the tree with prefix of the hash until +/// the data node is found. Then the hash is compared with the hash stored in +/// the data node to see if the is the same object. +/// +/// Hash collision is not allowed so it is recommended to use trie with a +/// "strong" hashing algorithm. A well-distributed hash can also result in +/// better performance and memory usage. +/// +/// It currently does not support iteration and deletion. + +/// Base class for a lock-free thread-safe hash-mapped trie. +class ThreadSafeTrieRawHashMapBase { +public: + static constexpr size_t TrieContentBaseSize = 4; + static constexpr size_t DefaultNumRootBits = 6; + static constexpr size_t DefaultNumSubtrieBits = 4; + +private: + template struct AllocValueType { + char Base[TrieContentBaseSize]; + std::aligned_union_t Content; + }; + +protected: + template + static constexpr size_t DefaultContentAllocSize = sizeof(AllocValueType); + + template + static constexpr size_t DefaultContentAllocAlign = alignof(AllocValueType); + + template + static constexpr size_t DefaultContentOffset = + offsetof(AllocValueType, Content); + +public: + static void *operator new(size_t Size) { return ::operator new(Size); } + void operator delete(void *Ptr) { ::operator delete(Ptr); } + + LLVM_DUMP_METHOD void dump() const; + void print(raw_ostream &OS) const; + +protected: + /// Result of a lookup. Suitable for an insertion hint. Maybe could be + /// expanded into an iterator of sorts, but likely not useful (visiting + /// everything in the trie should probably be done some way other than + /// through an iterator pattern). + class PointerBase { + protected: + void *get() const { return I == -2u ? P : nullptr; } + + public: + PointerBase() noexcept = default; + + private: + friend class ThreadSafeTrieRawHashMapBase; + explicit PointerBase(void *Content) : P(Content), I(-2u) {} + PointerBase(void *P, unsigned I, unsigned B) : P(P), I(I), B(B) {} + + bool isHint() const { return I != -1u && I != -2u; } + + void *P = nullptr; + unsigned I = -1u; + unsigned B = 0; + }; + + /// Find the stored content with hash. + PointerBase find(ArrayRef Hash) const; + + /// Insert and return the stored content. + PointerBase + insert(PointerBase Hint, ArrayRef Hash, + function_ref Hash)> + Constructor); + + ThreadSafeTrieRawHashMapBase() = delete; + + ThreadSafeTrieRawHashMapBase( + size_t ContentAllocSize, size_t ContentAllocAlign, size_t ContentOffset, + std::optional NumRootBits = std::nullopt, + std::optional NumSubtrieBits = std::nullopt); + + /// Destructor, which asserts if there's anything to do. Subclasses should + /// call \a destroyImpl(). + /// + /// \pre \a destroyImpl() was already called. + ~ThreadSafeTrieRawHashMapBase(); + void destroyImpl(function_ref Destructor); + + ThreadSafeTrieRawHashMapBase(ThreadSafeTrieRawHashMapBase &&RHS); + + // Move assignment is not supported as it is not thread-safe. + ThreadSafeTrieRawHashMapBase & + operator=(ThreadSafeTrieRawHashMapBase &&RHS) = delete; + + // No copy. + ThreadSafeTrieRawHashMapBase(const ThreadSafeTrieRawHashMapBase &) = delete; + ThreadSafeTrieRawHashMapBase & + operator=(const ThreadSafeTrieRawHashMapBase &) = delete; + + // Debug functions. Implementation details and not guaranteed to be + // thread-safe. + PointerBase getRoot() const; + unsigned getStartBit(PointerBase P) const; + unsigned getNumBits(PointerBase P) const; + unsigned getNumSlotUsed(PointerBase P) const; + std::string getTriePrefixAsString(PointerBase P) const; + unsigned getNumTries() const; + // Visit next trie in the allocation chain. + PointerBase getNextTrie(PointerBase P) const; + +private: + friend class TrieRawHashMapTestHelper; + const unsigned short ContentAllocSize; + const unsigned short ContentAllocAlign; + const unsigned short ContentOffset; + unsigned short NumRootBits; + unsigned short NumSubtrieBits; + class ImplType; + // ImplPtr is owned by ThreadSafeTrieRawHashMapBase and needs to be freed in + // destroyImpl. + std::atomic ImplPtr; + ImplType &getOrCreateImpl(); + ImplType *getImpl() const; +}; + +/// Lock-free thread-safe hash-mapped trie. +template +class ThreadSafeTrieRawHashMap : public ThreadSafeTrieRawHashMapBase { +public: + using HashT = std::array; + + class LazyValueConstructor; + struct value_type { + const HashT Hash; + T Data; + + value_type(value_type &&) = default; + value_type(const value_type &) = default; + + value_type(ArrayRef Hash, const T &Data) + : Hash(makeHash(Hash)), Data(Data) {} + value_type(ArrayRef Hash, T &&Data) + : Hash(makeHash(Hash)), Data(std::move(Data)) {} + + private: + friend class LazyValueConstructor; + + struct EmplaceTag {}; + template + value_type(ArrayRef Hash, EmplaceTag, ArgsT &&...Args) + : Hash(makeHash(Hash)), Data(std::forward(Args)...) {} + + static HashT makeHash(ArrayRef HashRef) { + HashT Hash; + std::copy(HashRef.begin(), HashRef.end(), Hash.data()); + return Hash; + } + }; + + using ThreadSafeTrieRawHashMapBase::operator delete; + using HashType = HashT; + + using ThreadSafeTrieRawHashMapBase::dump; + using ThreadSafeTrieRawHashMapBase::print; + +private: + template class PointerImpl : PointerBase { + friend class ThreadSafeTrieRawHashMap; + + ValueT *get() const { + return reinterpret_cast(PointerBase::get()); + } + + public: + ValueT &operator*() const { + assert(get()); + return *get(); + } + ValueT *operator->() const { + assert(get()); + return get(); + } + explicit operator bool() const { return get(); } + + PointerImpl() = default; + + protected: + PointerImpl(PointerBase Result) : PointerBase(Result) {} + }; + +public: + class pointer; + class const_pointer; + class pointer : public PointerImpl { + friend class ThreadSafeTrieRawHashMap; + friend class const_pointer; + + public: + pointer() = default; + + private: + pointer(PointerBase Result) : pointer::PointerImpl(Result) {} + }; + + class const_pointer : public PointerImpl { + friend class ThreadSafeTrieRawHashMap; + + public: + const_pointer() = default; + const_pointer(const pointer &P) : const_pointer::PointerImpl(P) {} + + private: + const_pointer(PointerBase Result) : const_pointer::PointerImpl(Result) {} + }; + + class LazyValueConstructor { + public: + value_type &operator()(T &&RHS) { + assert(Mem && "Constructor already called, or moved away"); + return assign(::new (Mem) value_type(Hash, std::move(RHS))); + } + value_type &operator()(const T &RHS) { + assert(Mem && "Constructor already called, or moved away"); + return assign(::new (Mem) value_type(Hash, RHS)); + } + template value_type &emplace(ArgsT &&...Args) { + assert(Mem && "Constructor already called, or moved away"); + return assign(::new (Mem) + value_type(Hash, typename value_type::EmplaceTag{}, + std::forward(Args)...)); + } + + LazyValueConstructor(LazyValueConstructor &&RHS) + : Mem(RHS.Mem), Result(RHS.Result), Hash(RHS.Hash) { + RHS.Mem = nullptr; // Moved away, cannot call. + } + ~LazyValueConstructor() { assert(!Mem && "Constructor never called!"); } + + private: + value_type &assign(value_type *V) { + Mem = nullptr; + Result = V; + return *V; + } + friend class ThreadSafeTrieRawHashMap; + LazyValueConstructor() = delete; + LazyValueConstructor(void *Mem, value_type *&Result, ArrayRef Hash) + : Mem(Mem), Result(Result), Hash(Hash) { + assert(Hash.size() == sizeof(HashT) && "Invalid hash"); + assert(Mem && "Invalid memory for construction"); + } + void *Mem; + value_type *&Result; + ArrayRef Hash; + }; + + /// Insert with a hint. Default-constructed hint will work, but it's + /// recommended to start with a lookup to avoid overhead in object creation + /// if it already exists. + pointer insertLazy(const_pointer Hint, ArrayRef Hash, + function_ref OnConstruct) { + return pointer(ThreadSafeTrieRawHashMapBase::insert( + Hint, Hash, [&](void *Mem, ArrayRef Hash) { + value_type *Result = nullptr; + OnConstruct(LazyValueConstructor(Mem, Result, Hash)); + return Result->Hash.data(); + })); + } + + pointer insertLazy(ArrayRef Hash, + function_ref OnConstruct) { + return insertLazy(const_pointer(), Hash, OnConstruct); + } + + pointer insert(const_pointer Hint, value_type &&HashedData) { + return insertLazy(Hint, HashedData.Hash, [&](LazyValueConstructor C) { + C(std::move(HashedData.Data)); + }); + } + + pointer insert(const_pointer Hint, const value_type &HashedData) { + return insertLazy(Hint, HashedData.Hash, + [&](LazyValueConstructor C) { C(HashedData.Data); }); + } + + pointer find(ArrayRef Hash) { + assert(Hash.size() == std::tuple_size::value); + return ThreadSafeTrieRawHashMapBase::find(Hash); + } + + const_pointer find(ArrayRef Hash) const { + assert(Hash.size() == std::tuple_size::value); + return ThreadSafeTrieRawHashMapBase::find(Hash); + } + + ThreadSafeTrieRawHashMap(std::optional NumRootBits = std::nullopt, + std::optional NumSubtrieBits = std::nullopt) + : ThreadSafeTrieRawHashMapBase(DefaultContentAllocSize, + DefaultContentAllocAlign, + DefaultContentOffset, + NumRootBits, NumSubtrieBits) {} + + ~ThreadSafeTrieRawHashMap() { + if constexpr (std::is_trivially_destructible::value) + this->destroyImpl(nullptr); + else + this->destroyImpl( + [](void *P) { static_cast(P)->~value_type(); }); + } + + // Move constructor okay. + ThreadSafeTrieRawHashMap(ThreadSafeTrieRawHashMap &&) = default; + + // No move assignment or any copy. + ThreadSafeTrieRawHashMap &operator=(ThreadSafeTrieRawHashMap &&) = delete; + ThreadSafeTrieRawHashMap(const ThreadSafeTrieRawHashMap &) = delete; + ThreadSafeTrieRawHashMap & + operator=(const ThreadSafeTrieRawHashMap &) = delete; +}; + +} // namespace llvm + +#endif // LLVM_ADT_TRIERAWHASHMAP_H diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.def b/llvm/include/llvm/BinaryFormat/Dwarf.def index 9336f2a454ae47b110799a23b486f823abf5f691..0cbbbe823c06b5058821d07c7079a0744f25411c 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.def +++ b/llvm/include/llvm/BinaryFormat/Dwarf.def @@ -728,7 +728,7 @@ HANDLE_DW_OP(0x24, shl, 0, 2, 2, DWARF) HANDLE_DW_OP(0x25, shr, 0, 2, 2, DWARF) HANDLE_DW_OP(0x26, shra, 0, 2, 2, DWARF) HANDLE_DW_OP(0x27, xor, 0, 2, 2, DWARF) -HANDLE_DW_OP(0x28, bra, 1, 0, 2, DWARF) +HANDLE_DW_OP(0x28, bra, 1, 1, 2, DWARF) HANDLE_DW_OP(0x29, eq, 0, 2, 2, DWARF) HANDLE_DW_OP(0x2a, ge, 0, 2, 2, DWARF) HANDLE_DW_OP(0x2b, gt, 0, 2, 2, DWARF) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h index 816e94362f0262c8528aeb7def6a99bc55f79fec..8ce6eaa69c4ab7ffe0029c25e5d5e69f4bd0718d 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CSEInfo.h @@ -17,6 +17,7 @@ #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" #include "llvm/CodeGen/GlobalISel/GISelWorkList.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/CodeGen.h" @@ -177,6 +178,8 @@ public: const GISelInstProfileBuilder &addNodeIDOpcode(unsigned Opc) const; const GISelInstProfileBuilder &addNodeIDRegType(const LLT Ty) const; const GISelInstProfileBuilder &addNodeIDRegType(const Register) const; + const GISelInstProfileBuilder & + addNodeIDRegType(MachineRegisterInfo::VRegAttrs) const; const GISelInstProfileBuilder & addNodeIDRegType(const TargetRegisterClass *RC) const; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h index 7b42722ca8d4f104620feaa2d947f8756b843829..b4ff4cd178d757588c3c29a3d53a810861cf26be 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h @@ -24,6 +24,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGenTypes/LowLevelType.h" #include "llvm/IR/Function.h" +#include "llvm/Transforms/Utils/SizeOpts.h" #include #include #include @@ -635,8 +636,12 @@ protected: bool shouldOptForSize(const MachineFunction *MF) const { const auto &F = MF->getFunction(); - return F.hasOptSize() || F.hasMinSize() || - (PSI && BFI && CurMBB && llvm::shouldOptForSize(*CurMBB, PSI, BFI)); + if (F.hasOptSize()) + return true; + if (CurMBB) + if (auto *BB = CurMBB->getBasicBlock()) + return llvm::shouldOptimizeForSize(BB, PSI, BFI); + return false; } public: diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h index b6309a9ea0ec78cf2dc8b332e79ff0e1c8d0e7dc..cd7ebcf54c9e1e8d9e8b146e751eb7dab6ddd926 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h @@ -28,7 +28,7 @@ namespace llvm { class GenericMachineInstr : public MachineInstr { constexpr static unsigned PoisonFlags = NoUWrap | NoSWrap | NoUSWrap | IsExact | Disjoint | NonNeg | - FmNoNans | FmNoInfs; + FmNoNans | FmNoInfs | SameSign; public: GenericMachineInstr() = delete; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index ab3025e4923cd0c23ae9cfdfa605f1d90f606701..14a641512a67d620fd0ec7552f2156a909977f0e 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -72,15 +72,20 @@ class DstOp { LLT LLTTy; Register Reg; const TargetRegisterClass *RC; + MachineRegisterInfo::VRegAttrs Attrs; }; public: - enum class DstType { Ty_LLT, Ty_Reg, Ty_RC }; + enum class DstType { Ty_LLT, Ty_Reg, Ty_RC, Ty_VRegAttrs }; DstOp(unsigned R) : Reg(R), Ty(DstType::Ty_Reg) {} DstOp(Register R) : Reg(R), Ty(DstType::Ty_Reg) {} DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {} DstOp(const LLT T) : LLTTy(T), Ty(DstType::Ty_LLT) {} DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} + DstOp(MachineRegisterInfo::VRegAttrs Attrs) + : Attrs(Attrs), Ty(DstType::Ty_VRegAttrs) {} + DstOp(RegClassOrRegBank RCOrRB, LLT Ty) + : Attrs({RCOrRB, Ty}), Ty(DstType::Ty_VRegAttrs) {} void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const { switch (Ty) { @@ -93,6 +98,9 @@ public: case DstType::Ty_RC: MIB.addDef(MRI.createVirtualRegister(RC)); break; + case DstType::Ty_VRegAttrs: + MIB.addDef(MRI.createVirtualRegister(Attrs)); + break; } } @@ -104,6 +112,8 @@ public: return LLTTy; case DstType::Ty_Reg: return MRI.getType(Reg); + case DstType::Ty_VRegAttrs: + return Attrs.Ty; } llvm_unreachable("Unrecognised DstOp::DstType enum"); } @@ -114,12 +124,13 @@ public: } const TargetRegisterClass *getRegClass() const { - switch (Ty) { - case DstType::Ty_RC: - return RC; - default: - llvm_unreachable("Not a RC Operand"); - } + assert(Ty == DstType::Ty_RC && "Not a RC Operand"); + return RC; + } + + MachineRegisterInfo::VRegAttrs getVRegAttrs() const { + assert(Ty == DstType::Ty_VRegAttrs && "Not a VRegAttrs Operand"); + return Attrs; } DstType getDstOpKind() const { return Ty; } @@ -1255,7 +1266,8 @@ public: /// /// \return a MachineInstrBuilder for the newly created instruction. MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, - const SrcOp &Op0, const SrcOp &Op1); + const SrcOp &Op0, const SrcOp &Op1, + std::optional Flgs = std::nullopt); /// Build and insert a \p Res = G_FCMP \p Pred\p Op0, \p Op1 /// diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h index 95a8234d3c60808c50811b84b11338688a31f246..37653631cc2388173aaad49f4239efd506025bd8 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -180,7 +180,7 @@ std::optional getIConstantVRegSExtVal(Register VReg, const MachineRegisterInfo &MRI); /// \p VReg is defined by a G_CONSTANT, return the corresponding value. -APInt getIConstantFromReg(Register VReg, const MachineRegisterInfo &MRI); +const APInt &getIConstantFromReg(Register VReg, const MachineRegisterInfo &MRI); /// Simple struct used to hold a constant integer value and a virtual /// register. @@ -542,10 +542,6 @@ bool isConstFalseVal(const TargetLowering &TLI, int64_t Val, bool IsVector, /// TargetBooleanContents. int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP); -/// Returns true if the given block should be optimized for size. -bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI, - BlockFrequencyInfo *BFI); - using SmallInstListTy = GISelWorkList<4>; void saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 76a7b8662bae66c39275e2507e2d08223c59a3a4..ead6bbe1d5f6410b5b7e39a90e843ae98c79efff 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -119,6 +119,7 @@ public: Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs. NoUSWrap = 1 << 20, // Instruction supports geps // no unsigned signed wrap. + SameSign = 1 << 21 // Both operands have the same sign. }; private: @@ -1764,8 +1765,8 @@ public: bool isDereferenceableInvariantLoad() const; /// If the specified instruction is a PHI that always merges together the - /// same virtual register, return the register, otherwise return 0. - unsigned isConstantValuePHI() const; + /// same virtual register, return the register, otherwise return Register(). + Register isConstantValuePHI() const; /// Return true if this instruction has side effects that are not modeled /// by mayLoad / mayStore, etc. diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h index 7a2c23c13a3ce6ed7fa8751c2bcc248063622d3c..5dc51aaed81c7bef21ff95c471a22bac36151384 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -754,7 +754,7 @@ public: /// Returns register class or bank and low level type of \p Reg. Always safe /// to use. Special values are returned when \p Reg does not have some of the /// attributes. - VRegAttrs getVRegAttrs(Register Reg) { + VRegAttrs getVRegAttrs(Register Reg) const { return {getRegClassOrRegBank(Reg), getType(Reg)}; } diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index e12c1f076f133c921fdcd0fb54fcdce9a77f4288..d1c71fc95818c806fd08c4f8596af22c62c084a3 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -261,11 +261,11 @@ namespace llvm { /// TailDuplicate - Duplicate blocks with unconditional branches /// into tails of their predecessors. - extern char &TailDuplicateID; + extern char &TailDuplicateLegacyID; /// Duplicate blocks with unconditional branches into tails of their /// predecessors. Variant that works before register allocation. - extern char &EarlyTailDuplicateID; + extern char &EarlyTailDuplicateLegacyID; /// MachineTraceMetrics - This pass computes critical path and CPU resource /// usage in an ensemble of traces. diff --git a/llvm/include/llvm/CodeGen/SDPatternMatch.h b/llvm/include/llvm/CodeGen/SDPatternMatch.h index b3e249b7ebd5c4aec4d6937fdcbd0a6970d7744c..96667952a16efcf83fa984c5fb94ec79c3fed748 100644 --- a/llvm/include/llvm/CodeGen/SDPatternMatch.h +++ b/llvm/include/llvm/CodeGen/SDPatternMatch.h @@ -533,9 +533,7 @@ struct BinaryOpc_match { if (!Flags.has_value()) return true; - SDNodeFlags TmpFlags = *Flags; - TmpFlags.intersectWith(N->getFlags()); - return TmpFlags == *Flags; + return (*Flags & N->getFlags()) == *Flags; } return false; @@ -668,9 +666,7 @@ inline BinaryOpc_match m_Or(const LHS &L, const RHS &R) { template inline BinaryOpc_match m_DisjointOr(const LHS &L, const RHS &R) { - SDNodeFlags Flags; - Flags.setDisjoint(true); - return BinaryOpc_match(ISD::OR, L, R, Flags); + return BinaryOpc_match(ISD::OR, L, R, SDNodeFlags::Disjoint); } template @@ -813,9 +809,7 @@ template struct UnaryOpc_match { if (!Flags.has_value()) return true; - SDNodeFlags TmpFlags = *Flags; - TmpFlags.intersectWith(N->getFlags()); - return TmpFlags == *Flags; + return (*Flags & N->getFlags()) == *Flags; } return false; @@ -848,9 +842,7 @@ template inline UnaryOpc_match m_ZExt(const Opnd &Op) { template inline UnaryOpc_match m_NNegZExt(const Opnd &Op) { - SDNodeFlags Flags; - Flags.setNonNeg(true); - return UnaryOpc_match(ISD::ZERO_EXTEND, Op, Flags); + return UnaryOpc_match(ISD::ZERO_EXTEND, Op, SDNodeFlags::NonNeg); } template inline auto m_SExt(const Opnd &Op) { diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index e82bdb6906163caf67ae87cf683a3b5c68e1a82a..db111b0875a6eebdb327fee4ba8f74206ff9af64 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1064,17 +1064,13 @@ public: /// addressing some offset of an object. i.e. if a load is split into multiple /// components, create an add nuw from the base pointer to the offset. SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset) { - SDNodeFlags Flags; - Flags.setNoUnsignedWrap(true); - return getMemBasePlusOffset(Ptr, Offset, SL, Flags); + return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap); } SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, SDValue Offset) { // The object itself can't wrap around the address space, so it shouldn't be // possible for the adds of the offsets to the split parts to overflow. - SDNodeFlags Flags; - Flags.setNoUnsignedWrap(true); - return getMemBasePlusOffset(Ptr, Offset, SL, Flags); + return getMemBasePlusOffset(Ptr, Offset, SL, SDNodeFlags::NoUnsignedWrap); } /// Return a new CALLSEQ_START node, that starts new call frame, in which diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index bda0120a2df4aa2a7ec681dbbe10cd581b53066e..ae07420479e14eb6cd31a9936e5fc117314e1aa9 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -378,36 +378,49 @@ template<> struct simplify_type { /// the backend. struct SDNodeFlags { private: - bool NoUnsignedWrap : 1; - bool NoSignedWrap : 1; - bool Exact : 1; - bool Disjoint : 1; - bool NonNeg : 1; - bool NoNaNs : 1; - bool NoInfs : 1; - bool NoSignedZeros : 1; - bool AllowReciprocal : 1; - bool AllowContract : 1; - bool ApproximateFuncs : 1; - bool AllowReassociation : 1; - - // We assume instructions do not raise floating-point exceptions by default, - // and only those marked explicitly may do so. We could choose to represent - // this via a positive "FPExcept" flags like on the MI level, but having a - // negative "NoFPExcept" flag here makes the flag intersection logic more - // straightforward. - bool NoFPExcept : 1; - // Instructions with attached 'unpredictable' metadata on IR level. - bool Unpredictable : 1; + friend class SDNode; + + unsigned Flags = 0; + + template void setFlag(bool B) { + Flags = (Flags & ~Flag) | (B ? Flag : 0); + } public: + enum : unsigned { + None = 0, + NoUnsignedWrap = 1 << 0, + NoSignedWrap = 1 << 1, + NoWrap = NoUnsignedWrap | NoSignedWrap, + Exact = 1 << 2, + Disjoint = 1 << 3, + NonNeg = 1 << 4, + NoNaNs = 1 << 5, + NoInfs = 1 << 6, + NoSignedZeros = 1 << 7, + AllowReciprocal = 1 << 8, + AllowContract = 1 << 9, + ApproximateFuncs = 1 << 10, + AllowReassociation = 1 << 11, + + // We assume instructions do not raise floating-point exceptions by default, + // and only those marked explicitly may do so. We could choose to represent + // this via a positive "FPExcept" flags like on the MI level, but having a + // negative "NoFPExcept" flag here makes the flag intersection logic more + // straightforward. + NoFPExcept = 1 << 12, + // Instructions with attached 'unpredictable' metadata on IR level. + Unpredictable = 1 << 13, + + // NOTE: Please update LargestValue in LLVM_DECLARE_ENUM_AS_BITMASK below + // the class definition when adding new flags. + + PoisonGeneratingFlags = NoUnsignedWrap | NoSignedWrap | Exact | Disjoint | + NonNeg | NoNaNs | NoInfs, + }; + /// Default constructor turns off all optimization flags. - SDNodeFlags() - : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), - Disjoint(false), NonNeg(false), NoNaNs(false), NoInfs(false), - NoSignedZeros(false), AllowReciprocal(false), AllowContract(false), - ApproximateFuncs(false), AllowReassociation(false), NoFPExcept(false), - Unpredictable(false) {} + SDNodeFlags(unsigned Flags = SDNodeFlags::None) : Flags(Flags) {} /// Propagate the fast-math-flags from an IR FPMathOperator. void copyFMF(const FPMathOperator &FPMO) { @@ -421,71 +434,57 @@ public: } // These are mutators for each flag. - void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; } - void setNoSignedWrap(bool b) { NoSignedWrap = b; } - void setExact(bool b) { Exact = b; } - void setDisjoint(bool b) { Disjoint = b; } - void setNonNeg(bool b) { NonNeg = b; } - void setNoNaNs(bool b) { NoNaNs = b; } - void setNoInfs(bool b) { NoInfs = b; } - void setNoSignedZeros(bool b) { NoSignedZeros = b; } - void setAllowReciprocal(bool b) { AllowReciprocal = b; } - void setAllowContract(bool b) { AllowContract = b; } - void setApproximateFuncs(bool b) { ApproximateFuncs = b; } - void setAllowReassociation(bool b) { AllowReassociation = b; } - void setNoFPExcept(bool b) { NoFPExcept = b; } - void setUnpredictable(bool b) { Unpredictable = b; } + void setNoUnsignedWrap(bool b) { setFlag(b); } + void setNoSignedWrap(bool b) { setFlag(b); } + void setExact(bool b) { setFlag(b); } + void setDisjoint(bool b) { setFlag(b); } + void setNonNeg(bool b) { setFlag(b); } + void setNoNaNs(bool b) { setFlag(b); } + void setNoInfs(bool b) { setFlag(b); } + void setNoSignedZeros(bool b) { setFlag(b); } + void setAllowReciprocal(bool b) { setFlag(b); } + void setAllowContract(bool b) { setFlag(b); } + void setApproximateFuncs(bool b) { setFlag(b); } + void setAllowReassociation(bool b) { setFlag(b); } + void setNoFPExcept(bool b) { setFlag(b); } + void setUnpredictable(bool b) { setFlag(b); } // These are accessors for each flag. - bool hasNoUnsignedWrap() const { return NoUnsignedWrap; } - bool hasNoSignedWrap() const { return NoSignedWrap; } - bool hasExact() const { return Exact; } - bool hasDisjoint() const { return Disjoint; } - bool hasNonNeg() const { return NonNeg; } - bool hasNoNaNs() const { return NoNaNs; } - bool hasNoInfs() const { return NoInfs; } - bool hasNoSignedZeros() const { return NoSignedZeros; } - bool hasAllowReciprocal() const { return AllowReciprocal; } - bool hasAllowContract() const { return AllowContract; } - bool hasApproximateFuncs() const { return ApproximateFuncs; } - bool hasAllowReassociation() const { return AllowReassociation; } - bool hasNoFPExcept() const { return NoFPExcept; } - bool hasUnpredictable() const { return Unpredictable; } + bool hasNoUnsignedWrap() const { return Flags & NoUnsignedWrap; } + bool hasNoSignedWrap() const { return Flags & NoSignedWrap; } + bool hasExact() const { return Flags & Exact; } + bool hasDisjoint() const { return Flags & Disjoint; } + bool hasNonNeg() const { return Flags & NonNeg; } + bool hasNoNaNs() const { return Flags & NoNaNs; } + bool hasNoInfs() const { return Flags & NoInfs; } + bool hasNoSignedZeros() const { return Flags & NoSignedZeros; } + bool hasAllowReciprocal() const { return Flags & AllowReciprocal; } + bool hasAllowContract() const { return Flags & AllowContract; } + bool hasApproximateFuncs() const { return Flags & ApproximateFuncs; } + bool hasAllowReassociation() const { return Flags & AllowReassociation; } + bool hasNoFPExcept() const { return Flags & NoFPExcept; } + bool hasUnpredictable() const { return Flags & Unpredictable; } bool operator==(const SDNodeFlags &Other) const { - return NoUnsignedWrap == Other.NoUnsignedWrap && - NoSignedWrap == Other.NoSignedWrap && Exact == Other.Exact && - Disjoint == Other.Disjoint && NonNeg == Other.NonNeg && - NoNaNs == Other.NoNaNs && NoInfs == Other.NoInfs && - NoSignedZeros == Other.NoSignedZeros && - AllowReciprocal == Other.AllowReciprocal && - AllowContract == Other.AllowContract && - ApproximateFuncs == Other.ApproximateFuncs && - AllowReassociation == Other.AllowReassociation && - NoFPExcept == Other.NoFPExcept && - Unpredictable == Other.Unpredictable; - } - - /// Clear any flags in this flag set that aren't also set in Flags. All - /// flags will be cleared if Flags are undefined. - void intersectWith(const SDNodeFlags Flags) { - NoUnsignedWrap &= Flags.NoUnsignedWrap; - NoSignedWrap &= Flags.NoSignedWrap; - Exact &= Flags.Exact; - Disjoint &= Flags.Disjoint; - NonNeg &= Flags.NonNeg; - NoNaNs &= Flags.NoNaNs; - NoInfs &= Flags.NoInfs; - NoSignedZeros &= Flags.NoSignedZeros; - AllowReciprocal &= Flags.AllowReciprocal; - AllowContract &= Flags.AllowContract; - ApproximateFuncs &= Flags.ApproximateFuncs; - AllowReassociation &= Flags.AllowReassociation; - NoFPExcept &= Flags.NoFPExcept; - Unpredictable &= Flags.Unpredictable; + return Flags == Other.Flags; } + void operator&=(const SDNodeFlags &OtherFlags) { Flags &= OtherFlags.Flags; } + void operator|=(const SDNodeFlags &OtherFlags) { Flags |= OtherFlags.Flags; } }; +LLVM_DECLARE_ENUM_AS_BITMASK(decltype(SDNodeFlags::None), + SDNodeFlags::Unpredictable); + +inline SDNodeFlags operator|(SDNodeFlags LHS, SDNodeFlags RHS) { + LHS |= RHS; + return LHS; +} + +inline SDNodeFlags operator&(SDNodeFlags LHS, SDNodeFlags RHS) { + LHS &= RHS; + return LHS; +} + /// Represents one node in the SelectionDAG. /// class SDNode : public FoldingSetNode, public ilist_node { @@ -1023,16 +1022,14 @@ public: SDNodeFlags getFlags() const { return Flags; } void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; } + void dropFlags(unsigned Mask) { Flags &= ~Mask; } /// Clear any flags in this node that aren't also set in Flags. /// If Flags is not in a defined state then this has no effect. void intersectFlagsWith(const SDNodeFlags Flags); bool hasPoisonGeneratingFlags() const { - SDNodeFlags Flags = getFlags(); - return Flags.hasNoUnsignedWrap() || Flags.hasNoSignedWrap() || - Flags.hasExact() || Flags.hasDisjoint() || Flags.hasNonNeg() || - Flags.hasNoNaNs() || Flags.hasNoInfs(); + return Flags.Flags & SDNodeFlags::PoisonGeneratingFlags; } void setCFIType(uint32_t Type) { CFIType = Type; } diff --git a/llvm/include/llvm/CodeGen/TailDuplication.h b/llvm/include/llvm/CodeGen/TailDuplication.h new file mode 100644 index 0000000000000000000000000000000000000000..687a592ccf2fbfe2a51cc65c9657d05e9e3c1f01 --- /dev/null +++ b/llvm/include/llvm/CodeGen/TailDuplication.h @@ -0,0 +1,47 @@ +//===- llvm/CodeGen/TailDuplication.h ---------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_TAILDUPLICATIONPASS_H +#define LLVM_CODEGEN_TAILDUPLICATIONPASS_H + +#include "llvm/CodeGen/MBFIWrapper.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { + +template +class TailDuplicatePassBase : public PassInfoMixin { +private: + std::unique_ptr MBFIW; + +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +class EarlyTailDuplicatePass + : public TailDuplicatePassBase { +public: + MachineFunctionProperties getClearedProperties() const { + return MachineFunctionProperties().set( + MachineFunctionProperties::Property::NoPHIs); + } +}; + +class TailDuplicatePass + : public TailDuplicatePassBase {}; + +} // namespace llvm + +extern template class llvm::TailDuplicatePassBase; +extern template class llvm::TailDuplicatePassBase; + +#endif // LLVM_CODEGEN_TAILDUPLICATIONPASS_H diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h index 5adf86832672a4ac235662df96d2c1dc62ca858f..4de109739227ad25822a3dbf38a0bb750ecae0fa 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.h +++ b/llvm/include/llvm/CodeGen/ValueTypes.h @@ -231,7 +231,7 @@ namespace llvm { /// Return true if this is an overloaded type for TableGen. bool isOverloaded() const { return (V == MVT::iAny || V == MVT::fAny || V == MVT::vAny || - V == MVT::iPTRAny); + V == MVT::pAny); } /// Return true if the bit size is a multiple of 8. diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td index 493c0cfcab60ce4c19f3fee4fe7f63003042c721..6d6b92958b43218b47eedaafa2a82359123787d5 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.td +++ b/llvm/include/llvm/CodeGen/ValueTypes.td @@ -338,9 +338,9 @@ def MetadataVT : ValueType<0, 505> { // Metadata let LLVMName = "Metadata"; } -// Pseudo valuetype mapped to the current pointer size to any address space. +// Pseudo valuetype to represent "pointer to any address space" // Should only be used in TableGen. -def iPTRAny : VTAny<506>; +def pAny : VTAny<506>; // Pseudo valuetype to represent "vector of any size" // Should only be used in TableGen. diff --git a/llvm/include/llvm/CodeGenTypes/MachineValueType.h b/llvm/include/llvm/CodeGenTypes/MachineValueType.h index c9a5098ef1623edbd460d50755ebacb22dd2132f..5c47ad4824a7911aac23a78484b09258b4246b51 100644 --- a/llvm/include/llvm/CodeGenTypes/MachineValueType.h +++ b/llvm/include/llvm/CodeGenTypes/MachineValueType.h @@ -320,7 +320,7 @@ namespace llvm { llvm_unreachable("Value type is non-standard value, Other."); case iPTR: llvm_unreachable("Value type size is target-dependent. Ask TLI."); - case iPTRAny: + case pAny: case iAny: case fAny: case vAny: diff --git a/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h b/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h index ef42cc5f798fd930fd6613a514189a2eb8b5978e..8a4740c1dd9cb937bf6d98b11ed90820b3ee1d16 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h @@ -10,8 +10,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLEMANAGER_H -#define LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLEMANAGER_H +#ifndef LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLESYMBOLMANAGER_H +#define LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLESYMBOLMANAGER_H #include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h" #include "llvm/ExecutionEngine/Orc/RedirectionManager.h" @@ -103,4 +103,4 @@ private: } // namespace orc } // namespace llvm -#endif +#endif // LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLESYMBOLMANAGER_H diff --git a/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h b/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h index 4adc3efad557307c4a15493dcd7330c7dfcae320..cd185d54b2e7c80b95fd3d5a17ca33d15f204d72 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h @@ -178,4 +178,4 @@ private: } // namespace orc } // namespace llvm -#endif +#endif // LLVM_EXECUTIONENGINE_ORC_REOPTIMIZELAYER_H diff --git a/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h b/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h index 4004c42d91468436bdf68f11aa4b56357b134153..f2ea1f5b64c5332dee590df9c82858010afe305e 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h @@ -32,8 +32,8 @@ public: /// Change the redirection destination of given symbol to new destination /// symbol. - virtual Error redirect(JITDylib &JD, SymbolStringPtr Symbol, - ExecutorSymbolDef NewDest) { + Error redirect(JITDylib &JD, SymbolStringPtr Symbol, + ExecutorSymbolDef NewDest) { return redirect(JD, {{Symbol, NewDest}}); } diff --git a/llvm/include/llvm/Frontend/OpenMP/ClauseT.h b/llvm/include/llvm/Frontend/OpenMP/ClauseT.h index 2a890905dc6323e4b369a786b660bc725029454a..8ff15b51f1abdf59d91bebf7f73a553fd31d0e01 100644 --- a/llvm/include/llvm/Frontend/OpenMP/ClauseT.h +++ b/llvm/include/llvm/Frontend/OpenMP/ClauseT.h @@ -239,7 +239,8 @@ struct MapperT { ENUM(MemoryOrder, AcqRel, Acquire, Relaxed, Release, SeqCst); ENUM(MotionExpectation, Present); // V5.2: [15.9.1] `task-dependence-type` modifier -ENUM(TaskDependenceType, In, Out, Inout, Mutexinoutset, Inoutset, Depobj); +ENUM(TaskDependenceType, Depobj, In, Inout, Inoutset, Mutexinoutset, Out, Sink, + Source); template // struct LoopIterationT { diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.td b/llvm/include/llvm/Frontend/OpenMP/OMP.td index b4e228f0424145459cb81db1c3012fad4e48d79b..5d7bb01ec4b6b807ade99adbe54b6c177a222e1e 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMP.td +++ b/llvm/include/llvm/Frontend/OpenMP/OMP.td @@ -130,6 +130,8 @@ def OMPC_Depobj : Clause<"depobj"> { } def OMPC_Destroy : Clause<"destroy"> { let clangClass = "OMPDestroyClause"; + let flangClass = "OmpDestroyClause"; + let isValueOptional = true; } def OMPC_Detach : Clause<"detach"> { let clangClass = "OMPDetachClause"; @@ -496,6 +498,7 @@ def OMPC_Untied : Clause<"untied"> { } def OMPC_Update : Clause<"update"> { let clangClass = "OMPUpdateClause"; + let flangClass = "OmpUpdateClause"; } def OMPC_Use : Clause<"use"> { let clangClass = "OMPUseClause"; diff --git a/llvm/include/llvm/IR/Intrinsics.h b/llvm/include/llvm/IR/Intrinsics.h index e893295e3272b908d6f38330750ce164b421e74f..89dfff256e0c4327ece2425766bd38257e7e62c7 100644 --- a/llvm/include/llvm/IR/Intrinsics.h +++ b/llvm/include/llvm/IR/Intrinsics.h @@ -92,7 +92,7 @@ namespace Intrinsic { /// return the existing declaration. /// /// The \p Tys parameter is for intrinsics with overloaded types (e.g., those - /// using iAny, fAny, vAny, or iPTRAny). For a declaration of an overloaded + /// using iAny, fAny, vAny, or pAny). For a declaration of an overloaded /// intrinsic, Tys must provide exactly one type for each overloaded type in /// the intrinsic. Function *getOrInsertDeclaration(Module *M, ID id, ArrayRef Tys = {}); diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index 214186cd3ed6ebce053a2e79bb91d6f02db4f366..eddfbdfb177052e747f00d5f58c471d577b790df 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -388,7 +388,7 @@ class LLVMAnyType : LLVMType { !eq(vt, iAny) : ArgKind.AnyInteger, !eq(vt, fAny) : ArgKind.AnyFloat, !eq(vt, vAny) : ArgKind.AnyVector, - !eq(vt, iPTRAny) : ArgKind.AnyPointer, + !eq(vt, pAny) : ArgKind.AnyPointer, ); let Sig = [ IIT_ARG.Number, @@ -412,8 +412,8 @@ class LLVMQualPointerType ]); } -class LLVMAnyPointerType : LLVMAnyType { - assert isAny, "iPTRAny should have isOverloaded"; +class LLVMAnyPointerType : LLVMAnyType { + assert isAny, "pAny should have isOverloaded"; } // Match the type of another intrinsic parameter. Number is an index into the diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td b/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td index 4279661473d85032c3081ff477e42f33176b01e7..bf20080229aa4ff2085b3d9cf50244d3cb79780f 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCVXsf.td @@ -10,13 +10,6 @@ // //===----------------------------------------------------------------------===// -class VCIXSuffix { - list suffix = !cond(!eq(range, "c"): ["e8mf8", "e8mf4", "e8mf2", "e8m1", "e8m2", "e8m4", "e8m8"], - !eq(range, "s"): ["e16mf4", "e16mf2", "e16m1", "e16m2", "e16m4", "e16m8"], - !eq(range, "i"): ["e32mf2", "e32m1", "e32m2", "e32m4", "e32m8"], - !eq(range, "l"): ["e64m1", "e64m2", "e64m4", "e64m8"]); -} - let TargetPrefix = "riscv" in { // Output: (vector_out) // Input: (bit<27-26>, bit<24-20>, scalar_in, vl) or diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 6df2eb156a077494686ab19212358744340a38a9..ddb47390537412ac9af192d53c1e3a6cf468ebd9 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -87,6 +87,7 @@ let TargetPrefix = "spv" in { def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>; def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>; def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; + def int_spv_group_memory_barrier_with_group_sync : DefaultAttrsIntrinsic<[], [], []>; // Create resource handle given the binding information. Returns a // type appropriate for the kind of resource given the set id, binding id, diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td index 0ecca157077fdc19122220c2705e0858da1f1bc7..d1807d26a874ba8fe1b03e1cda56ced444210082 100644 --- a/llvm/include/llvm/IR/IntrinsicsX86.td +++ b/llvm/include/llvm/IR/IntrinsicsX86.td @@ -5994,6 +5994,23 @@ let TargetPrefix = "x86" in { [llvm_i16_ty, llvm_i16_ty, llvm_i16_ty, llvm_x86amx_ty, llvm_x86amx_ty, llvm_x86amx_ty], []>; + + def int_x86_tdpbf8ps : ClangBuiltin<"__builtin_ia32_tdpbf8ps">, + Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty], + [ImmArg>, + ImmArg>, ImmArg>]>; + def int_x86_tdpbhf8ps : ClangBuiltin<"__builtin_ia32_tdpbhf8ps">, + Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty], + [ImmArg>, + ImmArg>, ImmArg>]>; + def int_x86_tdphbf8ps : ClangBuiltin<"__builtin_ia32_tdphbf8ps">, + Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty], + [ImmArg>, + ImmArg>, ImmArg>]>; + def int_x86_tdphf8ps : ClangBuiltin<"__builtin_ia32_tdphf8ps">, + Intrinsic<[], [llvm_i8_ty, llvm_i8_ty, llvm_i8_ty], + [ImmArg>, + ImmArg>, ImmArg>]>; } //===----------------------------------------------------------------------===// diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index 899d8e025483ea439f8c1d6ab2ae83a17588a27f..ca0eab5f9d0c719f457d0e9739ab8c34f1ef1517 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -101,7 +101,7 @@ void initializeEarlyCSEMemSSALegacyPassPass(PassRegistry &); void initializeEarlyIfConverterLegacyPass(PassRegistry &); void initializeEarlyIfPredicatorPass(PassRegistry &); void initializeEarlyMachineLICMPass(PassRegistry &); -void initializeEarlyTailDuplicatePass(PassRegistry &); +void initializeEarlyTailDuplicateLegacyPass(PassRegistry &); void initializeEdgeBundlesPass(PassRegistry &); void initializeEHContGuardCatchretPass(PassRegistry &); void initializeExpandLargeFpConvertLegacyPassPass(PassRegistry &); @@ -300,7 +300,7 @@ void initializeStraightLineStrengthReduceLegacyPassPass(PassRegistry &); void initializeStripDebugMachineModulePass(PassRegistry &); void initializeStructurizeCFGLegacyPassPass(PassRegistry &); void initializeTailCallElimPass(PassRegistry &); -void initializeTailDuplicatePass(PassRegistry &); +void initializeTailDuplicateLegacyPass(PassRegistry &); void initializeTargetLibraryInfoWrapperPassPass(PassRegistry &); void initializeTargetPassConfigPass(PassRegistry &); void initializeTargetTransformInfoWrapperPassPass(PassRegistry &); diff --git a/llvm/include/llvm/MC/MCInstPrinter.h b/llvm/include/llvm/MC/MCInstPrinter.h index 60a901e3d0deae6d9bb8f5cd1d902e92af991168..e825c04a6dba6f9e3ccf2305461edfdc54e7fc04 100644 --- a/llvm/include/llvm/MC/MCInstPrinter.h +++ b/llvm/include/llvm/MC/MCInstPrinter.h @@ -9,8 +9,10 @@ #ifndef LLVM_MC_MCINSTPRINTER_H #define LLVM_MC_MCINSTPRINTER_H +#include "llvm/ADT/SmallVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Format.h" +#include "llvm/Support/raw_ostream.h" #include namespace llvm { @@ -24,7 +26,6 @@ class MCRegister; class MCRegisterInfo; class MCSubtargetInfo; class StringRef; -class raw_ostream; /// Convert `Bytes' to a hex string and output to `OS' void dumpBytes(ArrayRef Bytes, raw_ostream &OS); @@ -76,6 +77,8 @@ protected: /// If true, symbolize branch target and memory reference operands. bool SymbolizeOperands = false; + SmallVector ColorStack{raw_ostream::Colors::RESET}; + /// Utility function for printing annotations. void printAnnotation(raw_ostream &OS, StringRef Annot); @@ -98,8 +101,8 @@ public: class WithMarkup { public: - LLVM_CTOR_NODISCARD WithMarkup(raw_ostream &OS, Markup M, bool EnableMarkup, - bool EnableColor); + LLVM_CTOR_NODISCARD WithMarkup(MCInstPrinter &IP, raw_ostream &OS, Markup M, + bool EnableMarkup, bool EnableColor); ~WithMarkup(); template WithMarkup &operator<<(T &O) { @@ -113,6 +116,7 @@ public: } private: + MCInstPrinter &IP; raw_ostream &OS; bool EnableMarkup; bool EnableColor; @@ -144,7 +148,7 @@ public: StringRef getOpcodeName(unsigned Opcode) const; /// Print the assembler register name. - virtual void printRegName(raw_ostream &OS, MCRegister Reg) const; + virtual void printRegName(raw_ostream &OS, MCRegister Reg); bool getUseMarkup() const { return UseMarkup; } void setUseMarkup(bool Value) { UseMarkup = Value; } @@ -152,7 +156,7 @@ public: bool getUseColor() const { return UseColor; } void setUseColor(bool Value) { UseColor = Value; } - WithMarkup markup(raw_ostream &OS, Markup M) const; + WithMarkup markup(raw_ostream &OS, Markup M); bool getPrintImmHex() const { return PrintImmHex; } void setPrintImmHex(bool Value) { PrintImmHex = Value; } diff --git a/llvm/include/llvm/MC/MCParser/MCAsmParser.h b/llvm/include/llvm/MC/MCParser/MCAsmParser.h index faa72d5f3144c43a5a5d52f9ed75c2bcd1e14b11..70fba69778536e41cde1a16033a809425a7801a7 100644 --- a/llvm/include/llvm/MC/MCParser/MCAsmParser.h +++ b/llvm/include/llvm/MC/MCParser/MCAsmParser.h @@ -206,7 +206,7 @@ public: SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, const MCInstrInfo *MII, - const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) = 0; + MCInstPrinter *IP, MCAsmParserSemaCallback &SI) = 0; /// Emit a note at the location \p L, with the message \p Msg. virtual void Note(SMLoc L, const Twine &Msg, diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index ad80c661147d6f5c7efbcc15141cf55ac9369cef..9e95625fd1d881e804892fce5650e62d1c179b06 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -60,6 +60,7 @@ #include "llvm/CodeGen/SjLjEHPrepare.h" #include "llvm/CodeGen/StackColoring.h" #include "llvm/CodeGen/StackProtector.h" +#include "llvm/CodeGen/TailDuplication.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TwoAddressInstructionPass.h" #include "llvm/CodeGen/UnreachableBlockElim.h" diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index 4f32a917738c134d72ad77258d96e05348f952ed..9d12a120ff7ac6d894fb92b8717d7179a9344e6b 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -133,6 +133,7 @@ MACHINE_FUNCTION_ANALYSIS("virtregmap", VirtRegMapAnalysis()) MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass()) MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass()) MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass()) +MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass()) MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass()) MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass()) MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass()) @@ -157,6 +158,7 @@ MACHINE_FUNCTION_PASS("print", VirtRegMapPrinterPass(dbgs())) MACHINE_FUNCTION_PASS("require-all-machine-function-properties", RequireAllMachineFunctionPropertiesPass()) MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass()) +MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass()) MACHINE_FUNCTION_PASS("trigger-verifier-error", TriggerVerifierErrorPass()) MACHINE_FUNCTION_PASS("two-address-instruction", TwoAddressInstructionPass()) MACHINE_FUNCTION_PASS("verify", MachineVerifierPass()) @@ -210,7 +212,6 @@ DUMMY_MACHINE_FUNCTION_PASS("cfi-fixup", CFIFixupPass) DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass) DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass) DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter) -DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass) DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass) DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", FixupStatepointCallerSavedPass) DUMMY_MACHINE_FUNCTION_PASS("fs-profile-loader", MIRProfileLoaderNewPass) @@ -262,7 +263,6 @@ DUMMY_MACHINE_FUNCTION_PASS("simple-register-coalescing", RegisterCoalescerPass) DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass) DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass) DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass) -DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass) DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass) DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass) DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass) diff --git a/llvm/include/llvm/ProfileData/InstrProfWriter.h b/llvm/include/llvm/ProfileData/InstrProfWriter.h index b8b6c684717b0585b7a303e5f1d6b066bab4589c..559549b0a22cc97215e2f082ac5a16778c63d28d 100644 --- a/llvm/include/llvm/ProfileData/InstrProfWriter.h +++ b/llvm/include/llvm/ProfileData/InstrProfWriter.h @@ -78,12 +78,20 @@ private: // Whether to serialize the full schema. bool MemProfFullSchema; + // Whether to generated random memprof hotness for testing. + bool MemprofGenerateRandomHotness; + public: + // For memprof testing, random hotness can be assigned to the contexts if + // MemprofGenerateRandomHotness is enabled. The random seed can be either + // provided by MemprofGenerateRandomHotnessSeed, or if that is 0, one will be + // generated in the writer using the current time. InstrProfWriter( bool Sparse = false, uint64_t TemporalProfTraceReservoirSize = 0, uint64_t MaxTemporalProfTraceLength = 0, bool WritePrevVersion = false, memprof::IndexedVersion MemProfVersionRequested = memprof::Version0, - bool MemProfFullSchema = false); + bool MemProfFullSchema = false, bool MemprofGenerateRandomHotness = false, + unsigned MemprofGenerateRandomHotnessSeed = 0); ~InstrProfWriter(); StringMap &getProfileData() { return FunctionData; } diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h index f8121d35732518be04685db1de8827cbdd97348a..da2cc807370095da38442b1313872fd10d778971 100644 --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -147,6 +147,15 @@ struct PortableMemInfoBlock { return Name; \ } #include "llvm/ProfileData/MIBEntryDef.inc" +#undef MIBEntryDef + + // Define setters for each type which can be called by the writer. +#define MIBEntryDef(NameTag, Name, Type) \ + void set##Name(Type NewVal) { \ + assert(Schema[llvm::to_underlying(Meta::Name)]); \ + Name = NewVal; \ + } +#include "llvm/ProfileData/MIBEntryDef.inc" #undef MIBEntryDef void clear() { *this = PortableMemInfoBlock(); } diff --git a/llvm/include/llvm/SandboxIR/Context.h b/llvm/include/llvm/SandboxIR/Context.h index 1285598a1c0282218da73c5417c722239859bf59..f2056de87cb946cf82c74f52aa9898f6b4bc404a 100644 --- a/llvm/include/llvm/SandboxIR/Context.h +++ b/llvm/include/llvm/SandboxIR/Context.h @@ -9,18 +9,39 @@ #ifndef LLVM_SANDBOXIR_CONTEXT_H #define LLVM_SANDBOXIR_CONTEXT_H +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/MapVector.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/IR/LLVMContext.h" #include "llvm/SandboxIR/Tracker.h" #include "llvm/SandboxIR/Type.h" +#include + namespace llvm::sandboxir { -class Module; -class Value; class Argument; +class BBIterator; class Constant; +class Module; +class Value; class Context { +public: + // A EraseInstrCallback receives the instruction about to be erased. + using EraseInstrCallback = std::function; + // A CreateInstrCallback receives the instruction about to be created. + using CreateInstrCallback = std::function; + // A MoveInstrCallback receives the instruction about to be moved, the + // destination BB and an iterator pointing to the insertion position. + using MoveInstrCallback = + std::function; + + /// An ID for a registered callback. Used for deregistration. Using a 64-bit + /// integer so we don't have to worry about the unlikely case of overflowing + /// a 32-bit counter. + using CallbackID = uint64_t; + protected: LLVMContext &LLVMCtx; friend class Type; // For LLVMCtx. @@ -48,6 +69,21 @@ protected: /// Type objects. DenseMap> LLVMTypeToTypeMap; + /// Callbacks called when an IR instruction is about to get erased. Keys are + /// used as IDs for deregistration. + MapVector EraseInstrCallbacks; + /// Callbacks called when an IR instruction is about to get created. Keys are + /// used as IDs for deregistration. + MapVector CreateInstrCallbacks; + /// Callbacks called when an IR instruction is about to get moved. Keys are + /// used as IDs for deregistration. + MapVector MoveInstrCallbacks; + + /// A counter used for assigning callback IDs during registration. The same + /// counter is used for all kinds of callbacks so we can detect mismatched + /// registration/deregistration. + CallbackID NextCallbackID = 0; + /// Remove \p V from the maps and returns the unique_ptr. std::unique_ptr detachLLVMValue(llvm::Value *V); /// Remove \p SBV from all SandboxIR maps and stop owning it. This effectively @@ -70,6 +106,10 @@ protected: Constant *getOrCreateConstant(llvm::Constant *LLVMC); friend class Utils; // For getMemoryBase + void runEraseInstrCallbacks(Instruction *I); + void runCreateInstrCallbacks(Instruction *I); + void runMoveInstrCallbacks(Instruction *I, const BBIterator &Where); + // Friends for getOrCreateConstant(). #define DEF_CONST(ID, CLASS) friend class CLASS; #include "llvm/SandboxIR/Values.def" @@ -198,6 +238,28 @@ public: /// \Returns the number of values registered with Context. size_t getNumValues() const { return LLVMValueToValueMap.size(); } + + /// Register a callback that gets called when a SandboxIR instruction is about + /// to be removed from its parent. Note that this will also be called when + /// reverting the creation of an instruction. + /// \Returns a callback ID for later deregistration. + CallbackID registerEraseInstrCallback(EraseInstrCallback CB); + void unregisterEraseInstrCallback(CallbackID ID); + + /// Register a callback that gets called right after a SandboxIR instruction + /// is created. Note that this will also be called when reverting the removal + /// of an instruction. + /// \Returns a callback ID for later deregistration. + CallbackID registerCreateInstrCallback(CreateInstrCallback CB); + void unregisterCreateInstrCallback(CallbackID ID); + + /// Register a callback that gets called when a SandboxIR instruction is about + /// to be moved. Note that this will also be called when reverting a move. + /// \Returns a callback ID for later deregistration. + CallbackID registerMoveInstrCallback(MoveInstrCallback CB); + void unregisterMoveInstrCallback(CallbackID ID); + + // TODO: Add callbacks for instructions inserted/removed if needed. }; } // namespace llvm::sandboxir diff --git a/llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc b/llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc index 902fa8f79ab8164c41bad326fd2bd9e4b318ee57..e454524c9cb6a2334ca4cc54e1ab476f92b1bb97 100644 --- a/llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc +++ b/llvm/include/llvm/TargetParser/AArch64CPUFeatures.inc @@ -53,9 +53,9 @@ enum CPUFeatures { FEAT_EBF16, FEAT_RPRES, FEAT_SVE, - FEAT_SVE_BF16, - FEAT_SVE_EBF16, - FEAT_SVE_I8MM, + RESERVED_FEAT_SVE_BF16, // previously used and now ABI legacy + RESERVED_FEAT_SVE_EBF16, // previously used and now ABI legacy + RESERVED_FEAT_SVE_I8MM, // previously used and now ABI legacy FEAT_SVE_F32MM, FEAT_SVE_F64MM, FEAT_SVE2, diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def index 073e19f8187c65e62462c68a82cedd0759cf8f27..19e8e0013ef6a052b61c0df0702b3d1c6ebb837d 100644 --- a/llvm/include/llvm/TargetParser/X86TargetParser.def +++ b/llvm/include/llvm/TargetParser/X86TargetParser.def @@ -264,6 +264,7 @@ X86_FEATURE_COMPAT(AVX10_2_512, "avx10.2-512", 0) //FIXME: make MOVRS _COMPAT defined when gcc landed relate patch. X86_FEATURE (MOVRS, "movrs") X86_FEATURE (ZU, "zu") +X86_FEATURE (AMX_FP8, "amx-fp8") // These features aren't really CPU features, but the frontend can set them. X86_FEATURE (RETPOLINE_EXTERNAL_THUNK, "retpoline-external-thunk") X86_FEATURE (RETPOLINE_INDIRECT_BRANCHES, "retpoline-indirect-branches") diff --git a/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h b/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h index eb682c437b94bca55108ebe6fd68464ffaf28b7d..02adcd8bfd45d055dd1e7d60511c46674b7ddc74 100644 --- a/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h +++ b/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h @@ -195,6 +195,13 @@ struct ByteArrayBuilder { bool isJumpTableCanonical(Function *F); +/// Specifies how to drop type tests. +enum class DropTestKind { + None, /// Do not drop type tests (default). + Assume, /// Drop only llvm.assumes using type test value. + All, /// Drop the type test and all uses. +}; + } // end namespace lowertypetests class LowerTypeTestsPass : public PassInfoMixin { @@ -202,13 +209,15 @@ class LowerTypeTestsPass : public PassInfoMixin { ModuleSummaryIndex *ExportSummary = nullptr; const ModuleSummaryIndex *ImportSummary = nullptr; - bool DropTypeTests = true; + lowertypetests::DropTestKind DropTypeTests = + lowertypetests::DropTestKind::None; public: LowerTypeTestsPass() : UseCommandLine(true) {} LowerTypeTestsPass(ModuleSummaryIndex *ExportSummary, const ModuleSummaryIndex *ImportSummary, - bool DropTypeTests = false) + lowertypetests::DropTestKind DropTypeTests = + lowertypetests::DropTestKind::None) : ExportSummary(ExportSummary), ImportSummary(ImportSummary), DropTypeTests(DropTypeTests) {} PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); diff --git a/llvm/include/llvm/Transforms/Utils/Cloning.h b/llvm/include/llvm/Transforms/Utils/Cloning.h index a4be24e32c527946e3230b3daa28cd9e864ff8f5..1e8ef0102450e4dc629cc797eca96f228bf374bd 100644 --- a/llvm/include/llvm/Transforms/Utils/Cloning.h +++ b/llvm/include/llvm/Transforms/Utils/Cloning.h @@ -175,6 +175,14 @@ void CloneFunctionInto(Function *NewFunc, const Function *OldFunc, ValueMapTypeRemapper *TypeMapper = nullptr, ValueMaterializer *Materializer = nullptr); +/// Clone OldFunc's attributes into NewFunc, transforming values based on the +/// mappings in VMap. +void CloneFunctionAttributesInto(Function *NewFunc, const Function *OldFunc, + ValueToValueMapTy &VMap, + bool ModuleLevelChanges, + ValueMapTypeRemapper *TypeMapper = nullptr, + ValueMaterializer *Materializer = nullptr); + void CloneAndPruneIntoFromInst(Function *NewFunc, const Function *OldFunc, const Instruction *StartingInst, ValueToValueMapTy &VMap, bool ModuleLevelChanges, diff --git a/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h b/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h index 49dcec26dbc559966c1fd0dffbd19cdfc6b3b3f9..77ba5cd7f002e914adc45e761fb2a9e0a173f3f6 100644 --- a/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h +++ b/llvm/include/llvm/Transforms/Vectorize/SandboxVectorizer/Legality.h @@ -32,6 +32,7 @@ enum class ResultReason { DiffOpcodes, DiffTypes, DiffMathFlags, + DiffWrapFlags, }; #ifndef NDEBUG @@ -56,6 +57,8 @@ struct ToStr { return "DiffTypes"; case ResultReason::DiffMathFlags: return "DiffMathFlags"; + case ResultReason::DiffWrapFlags: + return "DiffWrapFlags"; } llvm_unreachable("Unknown ResultReason enum"); } diff --git a/llvm/lib/Analysis/StackSafetyAnalysis.cpp b/llvm/lib/Analysis/StackSafetyAnalysis.cpp index 27360d0e84cb2b8a4fd8f3d48147a75ec01a32e9..5d81658409dae85095a0d6743ed5fc26fa98e52e 100644 --- a/llvm/lib/Analysis/StackSafetyAnalysis.cpp +++ b/llvm/lib/Analysis/StackSafetyAnalysis.cpp @@ -528,7 +528,7 @@ void StackSafetyLocalAnalysis::analyzeAllUses(Value *Ptr, // dso_preemptable aliases or aliases with interposable linkage. const GlobalValue *Callee = dyn_cast(CB.getCalledOperand()->stripPointerCasts()); - if (!Callee) { + if (!Callee || isa(Callee)) { US.addRange(I, UnknownRange, /*IsSafe=*/false); break; } diff --git a/llvm/lib/AsmParser/LLLexer.cpp b/llvm/lib/AsmParser/LLLexer.cpp index 759db6db60774c2f685bd5ac96b3cfb985f48615..56abd03d62354151bbb2f438e88fdeed0ba44b8d 100644 --- a/llvm/lib/AsmParser/LLLexer.cpp +++ b/llvm/lib/AsmParser/LLLexer.cpp @@ -60,8 +60,8 @@ uint64_t LLLexer::atoull(const char *Buffer, const char *End) { uint64_t OldRes = Result; Result *= 10; Result += *Buffer-'0'; - if (Result < OldRes) { // Uh, oh, overflow detected!!! - LexError("constant bigger than 64 bits detected!"); + if (Result < OldRes) { // overflow detected. + LexError("constant bigger than 64 bits detected"); return 0; } } @@ -75,8 +75,8 @@ uint64_t LLLexer::HexIntToVal(const char *Buffer, const char *End) { Result *= 16; Result += hexDigitValue(*Buffer); - if (Result < OldRes) { // Uh, oh, overflow detected!!! - LexError("constant bigger than 64 bits detected!"); + if (Result < OldRes) { // overflow detected. + LexError("constant bigger than 64 bits detected"); return 0; } } @@ -99,7 +99,7 @@ void LLLexer::HexToIntPair(const char *Buffer, const char *End, Pair[1] += hexDigitValue(*Buffer); } if (Buffer != End) - LexError("constant bigger than 128 bits detected!"); + LexError("constant bigger than 128 bits detected"); } /// FP80HexToIntPair - translate an 80 bit FP80 number (20 hexits) into @@ -118,7 +118,7 @@ void LLLexer::FP80HexToIntPair(const char *Buffer, const char *End, Pair[0] += hexDigitValue(*Buffer); } if (Buffer != End) - LexError("constant bigger than 128 bits detected!"); + LexError("constant bigger than 128 bits detected"); } // UnEscapeLexed - Run through the specified buffer and change \xx codes to the @@ -292,7 +292,7 @@ lltok::Kind LLLexer::LexDollar() { StrVal.assign(TokStart + 2, CurPtr - 1); UnEscapeLexed(StrVal); if (StringRef(StrVal).contains(0)) { - LexError("Null bytes are not allowed in names"); + LexError("NUL character is not allowed in names"); return lltok::Error; } return lltok::ComdatVar; @@ -354,7 +354,7 @@ lltok::Kind LLLexer::LexUIntID(lltok::Kind Token) { uint64_t Val = atoull(TokStart + 1, CurPtr); if ((unsigned)Val != Val) - LexError("invalid value number (too large)!"); + LexError("invalid value number (too large)"); UIntVal = unsigned(Val); return Token; } @@ -375,7 +375,7 @@ lltok::Kind LLLexer::LexVar(lltok::Kind Var, lltok::Kind VarID) { StrVal.assign(TokStart+2, CurPtr-1); UnEscapeLexed(StrVal); if (StringRef(StrVal).contains(0)) { - LexError("Null bytes are not allowed in names"); + LexError("NUL character is not allowed in names"); return lltok::Error; } return Var; @@ -410,7 +410,7 @@ lltok::Kind LLLexer::LexQuote() { if (CurPtr[0] == ':') { ++CurPtr; if (StringRef(StrVal).contains(0)) { - LexError("Null bytes are not allowed in names"); + LexError("NUL character is not allowed in names"); kind = lltok::Error; } else { kind = lltok::LabelStr; @@ -492,7 +492,7 @@ lltok::Kind LLLexer::LexIdentifier() { uint64_t NumBits = atoull(StartChar, CurPtr); if (NumBits < IntegerType::MIN_INT_BITS || NumBits > IntegerType::MAX_INT_BITS) { - LexError("bitwidth for integer type out of range!"); + LexError("bitwidth for integer type out of range"); return lltok::Error; } TyVal = IntegerType::get(Context, NumBits); @@ -1122,7 +1122,7 @@ lltok::Kind LLLexer::LexDigitOrNegative() { uint64_t Val = atoull(TokStart, CurPtr); ++CurPtr; // Skip the colon. if ((unsigned)Val != Val) - LexError("invalid value number (too large)!"); + LexError("invalid value number (too large)"); UIntVal = unsigned(Val); return lltok::LabelID; } diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp index cf5c35fe81b4c712e34b9365d6b1326e7f172d2d..39fba1d0b527ef680de57b840fa4db6f660822b5 100644 --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -38,7 +38,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeEarlyIfConverterLegacyPass(Registry); initializeEarlyIfPredicatorPass(Registry); initializeEarlyMachineLICMPass(Registry); - initializeEarlyTailDuplicatePass(Registry); + initializeEarlyTailDuplicateLegacyPass(Registry); initializeExpandLargeDivRemLegacyPassPass(Registry); initializeExpandLargeFpConvertLegacyPassPass(Registry); initializeExpandMemCmpLegacyPassPass(Registry); @@ -131,7 +131,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) { initializeStackProtectorPass(Registry); initializeStackSlotColoringPass(Registry); initializeStripDebugMachineModulePass(Registry); - initializeTailDuplicatePass(Registry); + initializeTailDuplicateLegacyPass(Registry); initializeTargetPassConfigPass(Registry); initializeTwoAddressInstructionLegacyPassPass(Registry); initializeTypePromotionLegacyPass(Registry); diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp index ca4d0986b4426ccde16b4cc52eae9e0f69f2cd60..cfb4ae85aa4f77cd214a17a80fe9e68bab1df899 100644 --- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp @@ -356,6 +356,20 @@ GISelInstProfileBuilder::addNodeIDRegType(const RegisterBank *RB) const { return *this; } +const GISelInstProfileBuilder &GISelInstProfileBuilder::addNodeIDRegType( + MachineRegisterInfo::VRegAttrs Attrs) const { + addNodeIDRegType(Attrs.Ty); + + const RegClassOrRegBank &RCOrRB = Attrs.RCOrRB; + if (RCOrRB) { + if (const auto *RB = dyn_cast_if_present(RCOrRB)) + addNodeIDRegType(RB); + else + addNodeIDRegType(cast(RCOrRB)); + } + return *this; +} + const GISelInstProfileBuilder & GISelInstProfileBuilder::addNodeIDImmediate(int64_t Imm) const { ID.AddInteger(Imm); @@ -389,17 +403,7 @@ GISelInstProfileBuilder::addNodeIDFlag(unsigned Flag) const { const GISelInstProfileBuilder & GISelInstProfileBuilder::addNodeIDReg(Register Reg) const { - LLT Ty = MRI.getType(Reg); - if (Ty.isValid()) - addNodeIDRegType(Ty); - - if (const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg)) { - if (const auto *RB = dyn_cast_if_present(RCOrRB)) - addNodeIDRegType(RB); - else if (const auto *RC = - dyn_cast_if_present(RCOrRB)) - addNodeIDRegType(RC); - } + addNodeIDRegType(MRI.getVRegAttrs(Reg)); return *this; } diff --git a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp index 547529bbe699abf022daa1d07935b8f0b4f0e8c3..bf8e847011d7c1b24662e97f0fe28ea28b110c3f 100644 --- a/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp @@ -73,18 +73,24 @@ bool CSEMIRBuilder::canPerformCSEForOpc(unsigned Opc) const { void CSEMIRBuilder::profileDstOp(const DstOp &Op, GISelInstProfileBuilder &B) const { switch (Op.getDstOpKind()) { - case DstOp::DstType::Ty_RC: + case DstOp::DstType::Ty_RC: { B.addNodeIDRegType(Op.getRegClass()); break; + } case DstOp::DstType::Ty_Reg: { // Regs can have LLT&(RB|RC). If those exist, profile them as well. B.addNodeIDReg(Op.getReg()); break; } - default: + case DstOp::DstType::Ty_LLT: { B.addNodeIDRegType(Op.getLLTTy(*getMRI())); break; } + case DstOp::DstType::Ty_VRegAttrs: { + B.addNodeIDRegType(Op.getVRegAttrs()); + break; + } + } } void CSEMIRBuilder::profileSrcOp(const SrcOp &Op, diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 5381dce58f9e65de08dc65f9204b8cacdd9972a3..a87754389cc8ed3dc6539d341b702bc2dfb94b9d 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -340,20 +340,17 @@ bool IRTranslator::translateCompare(const User &U, Register Op1 = getOrCreateVReg(*U.getOperand(1)); Register Res = getOrCreateVReg(U); CmpInst::Predicate Pred = CI->getPredicate(); + uint32_t Flags = MachineInstr::copyFlagsFromInstruction(*CI); if (CmpInst::isIntPredicate(Pred)) - MIRBuilder.buildICmp(Pred, Res, Op0, Op1); + MIRBuilder.buildICmp(Pred, Res, Op0, Op1, Flags); else if (Pred == CmpInst::FCMP_FALSE) MIRBuilder.buildCopy( Res, getOrCreateVReg(*Constant::getNullValue(U.getType()))); else if (Pred == CmpInst::FCMP_TRUE) MIRBuilder.buildCopy( Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType()))); - else { - uint32_t Flags = 0; - if (CI) - Flags = MachineInstr::copyFlagsFromInstruction(*CI); + else MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, Flags); - } return true; } diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 59f2fc633f5de7f04d2b973256b6f2e8f6bab8e3..15b9164247846c28b6bd16417ee06b1d0267cdfe 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -898,8 +898,9 @@ MachineIRBuilder::buildFPTrunc(const DstOp &Res, const SrcOp &Op, MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, - const SrcOp &Op1) { - return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}); + const SrcOp &Op1, + std::optional Flags) { + return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}, Flags); } MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index 513a49b4fc2e4dffc5088f47042d8133f6c6dff1..5cee07461d7e22fb46b4fd149306624a0b4ae2e5 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -287,7 +287,8 @@ std::optional llvm::getIConstantVRegVal(Register VReg, return ValAndVReg->Value; } -APInt llvm::getIConstantFromReg(Register Reg, const MachineRegisterInfo &MRI) { +const APInt &llvm::getIConstantFromReg(Register Reg, + const MachineRegisterInfo &MRI) { MachineInstr *Const = MRI.getVRegDef(Reg); assert((Const && Const->getOpcode() == TargetOpcode::G_CONSTANT) && "expected a G_CONSTANT on Reg"); @@ -1619,11 +1620,6 @@ int64_t llvm::getICmpTrueVal(const TargetLowering &TLI, bool IsVector, llvm_unreachable("Invalid boolean contents"); } -bool llvm::shouldOptForSize(const MachineBasicBlock &MBB, - ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) { - return llvm::shouldOptimizeForSize(MBB.getBasicBlock(), PSI, BFI); -} - void llvm::saveUsesAndErase(MachineInstr &MI, MachineRegisterInfo &MRI, LostDebugLocObserver *LocObserver, SmallInstListTy &DeadInstChain) { diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp index 5a3806ce57335aeacd1f8e775ce6987590847eca..1c450b05f49e93a3b79cb92e977f9b6431c9e83e 100644 --- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp +++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp @@ -216,6 +216,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) { .Case("exact", MIToken::kw_exact) .Case("nneg", MIToken::kw_nneg) .Case("disjoint", MIToken::kw_disjoint) + .Case("samesign", MIToken::kw_samesign) .Case("nofpexcept", MIToken::kw_nofpexcept) .Case("unpredictable", MIToken::kw_unpredictable) .Case("debug-location", MIToken::kw_debug_location) diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h index 3931da3eaae1d3ace90978f34fff6ca210d50844..d7cd06759cfbb880dd03f281e351cfb6adcb8bbd 100644 --- a/llvm/lib/CodeGen/MIRParser/MILexer.h +++ b/llvm/lib/CodeGen/MIRParser/MILexer.h @@ -77,6 +77,7 @@ struct MIToken { kw_unpredictable, kw_nneg, kw_disjoint, + kw_samesign, kw_debug_location, kw_debug_instr_number, kw_dbg_instr_ref, diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp index 45847b5830da656a8c233422b13ba586ffd0c255..059814c70f828de2301d1fab12fbb96a494aa6ce 100644 --- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp @@ -1476,7 +1476,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) { Token.is(MIToken::kw_noconvergent) || Token.is(MIToken::kw_unpredictable) || Token.is(MIToken::kw_nneg) || - Token.is(MIToken::kw_disjoint)) { + Token.is(MIToken::kw_disjoint) || + Token.is(MIToken::kw_samesign)) { // clang-format on // Mine frame and fast math flags if (Token.is(MIToken::kw_frame_setup)) @@ -1513,6 +1514,8 @@ bool MIParser::parseInstruction(unsigned &OpCode, unsigned &Flags) { Flags |= MachineInstr::NonNeg; if (Token.is(MIToken::kw_disjoint)) Flags |= MachineInstr::Disjoint; + if (Token.is(MIToken::kw_samesign)) + Flags |= MachineInstr::SameSign; lex(); } diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index a015cd3c2a55f9b36ca0cd328c45cd606142dadd..658bbe0e577e5c5dced18e4d3f395ef91ad158ea 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -837,6 +837,8 @@ void MIPrinter::print(const MachineInstr &MI) { OS << "disjoint "; if (MI.getFlag(MachineInstr::NoUSWrap)) OS << "nusw "; + if (MI.getFlag(MachineInstr::SameSign)) + OS << "samesign "; OS << TII->getName(MI.getOpcode()); if (I < E) diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 0d78c2cafbaf63c182614523833f070d04a82c5d..941861da5c569373f42215b206783fbbc2232114 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -596,6 +596,11 @@ uint32_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) { MIFlags |= MachineInstr::MIFlag::Disjoint; } + // Copy the samesign flag. + if (const ICmpInst *ICmp = dyn_cast(&I)) + if (ICmp->hasSameSign()) + MIFlags |= MachineInstr::MIFlag::SameSign; + // Copy the exact flag. if (const PossiblyExactOperator *PE = dyn_cast(&I)) if (PE->isExact()) @@ -1535,19 +1540,16 @@ bool MachineInstr::isDereferenceableInvariantLoad() const { return true; } -/// isConstantValuePHI - If the specified instruction is a PHI that always -/// merges together the same virtual register, return the register, otherwise -/// return 0. -unsigned MachineInstr::isConstantValuePHI() const { +Register MachineInstr::isConstantValuePHI() const { if (!isPHI()) - return 0; + return {}; assert(getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"); Register Reg = getOperand(1).getReg(); for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) if (getOperand(i).getReg() != Reg) - return 0; + return {}; return Reg; } @@ -1773,6 +1775,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << "nneg "; if (getFlag(MachineInstr::Disjoint)) OS << "disjoint "; + if (getFlag(MachineInstr::SameSign)) + OS << "samesign "; // Print the opcode name. if (TII) diff --git a/llvm/lib/CodeGen/MachineSSAUpdater.cpp b/llvm/lib/CodeGen/MachineSSAUpdater.cpp index c7a673b12d8c5091747678c5d001177ea65578c8..f0a136751bbffaacd137d6701a70855f31c9c021 100644 --- a/llvm/lib/CodeGen/MachineSSAUpdater.cpp +++ b/llvm/lib/CodeGen/MachineSSAUpdater.cpp @@ -201,7 +201,7 @@ Register MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB, // See if the PHI node can be merged to a single value. This can happen in // loop cases when we get a PHI of itself and one other value. - if (unsigned ConstVal = InsertedPHI->isConstantValuePHI()) { + if (Register ConstVal = InsertedPHI->isConstantValuePHI()) { InsertedPHI->eraseFromParent(); return ConstVal; } diff --git a/llvm/lib/CodeGen/MachineStripDebug.cpp b/llvm/lib/CodeGen/MachineStripDebug.cpp index 6128248a028e3e01100165585adcc4fa2f68f7d6..ea291f64bff4321a472a3089dedc51250eee83ca 100644 --- a/llvm/lib/CodeGen/MachineStripDebug.cpp +++ b/llvm/lib/CodeGen/MachineStripDebug.cpp @@ -50,7 +50,7 @@ struct StripDebugMachineModule : public ModulePass { continue; MachineFunction &MF = *MaybeMF; for (MachineBasicBlock &MBB : MF) { - for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) { + for (MachineInstr &MI : llvm::make_early_inc_range(MBB.instrs())) { if (MI.isDebugInstr()) { // FIXME: We should remove all of them. However, AArch64 emits an // invalid `DBG_VALUE $lr` with only one operand instead of diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 5daf43f500c940e57cb064cc65812c4792f08924..fe5450557b78b84015870d04764edbd2e12bcb1b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1213,7 +1213,7 @@ SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDNodeFlags NewFlags; if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() && Flags.hasNoUnsignedWrap()) - NewFlags.setNoUnsignedWrap(true); + NewFlags |= SDNodeFlags::NoUnsignedWrap; if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) { // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2)) @@ -2895,11 +2895,11 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) { if (N->getFlags().hasNoUnsignedWrap() && N0->getFlags().hasNoUnsignedWrap() && N0.getOperand(0)->getFlags().hasNoUnsignedWrap()) { - Flags.setNoUnsignedWrap(true); + Flags |= SDNodeFlags::NoUnsignedWrap; if (N->getFlags().hasNoSignedWrap() && N0->getFlags().hasNoSignedWrap() && N0.getOperand(0)->getFlags().hasNoSignedWrap()) - Flags.setNoSignedWrap(true); + Flags |= SDNodeFlags::NoSignedWrap; } SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N1), VT, A, DAG.getConstant(CM, DL, VT), Flags); @@ -2923,12 +2923,12 @@ SDValue DAGCombiner::visitADDLike(SDNode *N) { N0->getFlags().hasNoUnsignedWrap() && OMul->getFlags().hasNoUnsignedWrap() && OMul.getOperand(0)->getFlags().hasNoUnsignedWrap()) { - Flags.setNoUnsignedWrap(true); + Flags |= SDNodeFlags::NoUnsignedWrap; if (N->getFlags().hasNoSignedWrap() && N0->getFlags().hasNoSignedWrap() && OMul->getFlags().hasNoSignedWrap() && OMul.getOperand(0)->getFlags().hasNoSignedWrap()) - Flags.setNoSignedWrap(true); + Flags |= SDNodeFlags::NoSignedWrap; } SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N1), VT, A, DAG.getConstant(CM, DL, VT), Flags); @@ -2990,11 +2990,8 @@ SDValue DAGCombiner::visitADD(SDNode *N) { // fold (a+b) -> (a|b) iff a and b share no bits. if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && - DAG.haveNoCommonBitsSet(N0, N1)) { - SDNodeFlags Flags; - Flags.setDisjoint(true); - return DAG.getNode(ISD::OR, DL, VT, N0, N1, Flags); - } + DAG.haveNoCommonBitsSet(N0, N1)) + return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint); // Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)). if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { @@ -7372,7 +7369,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) { // Fold (and X, (bswap (not Y))) -> (and X, (not (bswap Y))) // Fold (and X, (bitreverse (not Y))) -> (and X, (not (bitreverse Y))) - SDValue X, Y, NotY; + SDValue X, Y, Z, NotY; for (unsigned Opc : {ISD::BSWAP, ISD::BITREVERSE}) if (sd_match(N, m_And(m_Value(X), m_OneUse(m_UnaryOp(Opc, m_Value(NotY))))) && @@ -7381,6 +7378,15 @@ SDValue DAGCombiner::visitAND(SDNode *N) { return DAG.getNode(ISD::AND, DL, VT, X, DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y), VT)); + // Fold (and X, (rot (not Y), Z)) -> (and X, (not (rot Y, Z))) + for (unsigned Opc : {ISD::ROTL, ISD::ROTR}) + if (sd_match(N, m_And(m_Value(X), + m_OneUse(m_BinOp(Opc, m_Value(NotY), m_Value(Z))))) && + sd_match(NotY, m_Not(m_Value(Y))) && + (TLI.hasAndNot(SDValue(N, 0)) || NotY->hasOneUse())) + return DAG.getNode(ISD::AND, DL, VT, X, + DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y, Z), VT)); + // Masking the negated extension of a boolean is just the zero-extended // boolean: // and (sub 0, zext(bool X)), 1 --> zext(bool X) @@ -9564,11 +9570,8 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { // fold (a^b) -> (a|b) iff a and b share no bits. if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) && - DAG.haveNoCommonBitsSet(N0, N1)) { - SDNodeFlags Flags; - Flags.setDisjoint(true); - return DAG.getNode(ISD::OR, DL, VT, N0, N1, Flags); - } + DAG.haveNoCommonBitsSet(N0, N1)) + return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint); // look for 'add-like' folds: // XOR(N0,MIN_SIGNED_VALUE) == ADD(N0,MIN_SIGNED_VALUE) @@ -10218,7 +10221,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) { SDNodeFlags Flags; // Preserve the disjoint flag for Or. if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint()) - Flags.setDisjoint(true); + Flags |= SDNodeFlags::Disjoint; return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags); } } @@ -14066,11 +14069,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { // fold (sext x) -> (zext x) if the sign bit is known zero. if (!TLI.isSExtCheaperThanZExt(N0.getValueType(), VT) && (!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && - DAG.SignBitIsZero(N0)) { - SDNodeFlags Flags; - Flags.setNonNeg(true); - return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0, Flags); - } + DAG.SignBitIsZero(N0)) + return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0, SDNodeFlags::NonNeg); if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N)) return NewVSel; @@ -14951,10 +14951,9 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) { uint64_t PtrOff = PtrAdjustmentInBits / 8; SDLoc DL(LN0); // The original load itself didn't wrap, so an offset within it doesn't. - SDNodeFlags Flags; - Flags.setNoUnsignedWrap(true); - SDValue NewPtr = DAG.getMemBasePlusOffset( - LN0->getBasePtr(), TypeSize::getFixed(PtrOff), DL, Flags); + SDValue NewPtr = + DAG.getMemBasePlusOffset(LN0->getBasePtr(), TypeSize::getFixed(PtrOff), + DL, SDNodeFlags::NoUnsignedWrap); AddToWorklist(NewPtr.getNode()); SDValue Load; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 6ba12cfb8c51481eab951d930abcb0962af3fa6b..4ea2054360a45668787f113c825fa17efd68ff0a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1697,12 +1697,9 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const { SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit); } - SDNodeFlags Flags; - Flags.setDisjoint(true); - // Store the part with the modified sign and convert back to float. - SDValue CopiedSign = - DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit, Flags); + SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit, + SDNodeFlags::Disjoint); return modifySignAsInt(MagAsInt, DL, CopiedSign); } @@ -1773,7 +1770,7 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, Tmp1 = DAG.getNode(Opc, dl, VT, SP, Size); // Value if (Alignment > StackAlign) Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, - DAG.getConstant(-Alignment.value(), dl, VT)); + DAG.getSignedConstant(-Alignment.value(), dl, VT)); Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain Tmp2 = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), dl); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index ee9c95c85937664f31196757a9cd14455af22167..45487c887b74dd1f79cc9e3a3f15d0da1cba84d4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -4674,9 +4674,9 @@ void DAGTypeLegalizer::ExpandIntRes_ShiftThroughStack(SDNode *N, SDValue &Lo, DAG.getNode(ISD::SHL, dl, ShAmtVT, SrlTmp, DAG.getConstant(Log2_32(ShiftUnitInBits), dl, ShAmtVT)); - Flags.setExact(true); - SDValue ByteOffset = DAG.getNode(ISD::SRL, dl, ShAmtVT, BitOffset, - DAG.getConstant(3, dl, ShAmtVT), Flags); + SDValue ByteOffset = + DAG.getNode(ISD::SRL, dl, ShAmtVT, BitOffset, + DAG.getConstant(3, dl, ShAmtVT), SDNodeFlags::Exact); // And clamp it, because OOB load is an immediate UB, // while shift overflow would have *just* been poison. ByteOffset = DAG.getNode(ISD::AND, dl, ShAmtVT, ByteOffset, diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index c80da28b3dc34d509ef2ece4484bdd7f6caed753..a8a171d932ff4bdb34fdf910ed2e7f8c765b0b63 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -1700,11 +1700,8 @@ SDValue VectorLegalizer::ExpandVP_FCOPYSIGN(SDNode *Node) { SDValue ClearedSign = DAG.getNode(ISD::VP_AND, DL, IntVT, Mag, ClearSignMask, Mask, EVL); - SDNodeFlags Flags; - Flags.setDisjoint(true); - SDValue CopiedSign = DAG.getNode(ISD::VP_OR, DL, IntVT, ClearedSign, SignBit, - Mask, EVL, Flags); + Mask, EVL, SDNodeFlags::Disjoint); return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign); } @@ -1886,11 +1883,8 @@ SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) { APInt::getSignedMaxValue(IntVT.getScalarSizeInBits()), DL, IntVT); SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, Mag, ClearSignMask); - SDNodeFlags Flags; - Flags.setDisjoint(true); - - SDValue CopiedSign = - DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit, Flags); + SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit, + SDNodeFlags::Disjoint); return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign); } diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index ccd849ecfeee37b7b7ba46858a750069d591013e..20da9cb68c62f39c723d01c7980afe9befe311ef 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -1382,16 +1382,14 @@ void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT, unsigned IncrementSize = MemVT.getSizeInBits().getKnownMinValue() / 8; if (MemVT.isScalableVector()) { - SDNodeFlags Flags; SDValue BytesIncrement = DAG.getVScale( DL, Ptr.getValueType(), APInt(Ptr.getValueSizeInBits().getFixedValue(), IncrementSize)); MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace()); - Flags.setNoUnsignedWrap(true); if (ScaledOffset) *ScaledOffset += IncrementSize; Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, BytesIncrement, - Flags); + SDNodeFlags::NoUnsignedWrap); } else { MPI = N->getPointerInfo().getWithOffset(IncrementSize); // Increment the pointer to the other half. diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 87206865724720d345238285423ad6eb2dfbf728..e948d9e26a840057447e48aea847e33ea4d33fde 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -12410,7 +12410,7 @@ bool SDNode::hasPredecessor(const SDNode *N) const { } void SDNode::intersectFlagsWith(const SDNodeFlags Flags) { - this->Flags.intersectWith(Flags); + this->Flags &= Flags; } SDValue diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 5496a1d03fd87a7f816ebb05245613d7c183f4a1..3d04d5e069a74ccbb90dfda9df2cbfbd9b48f29c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -4334,7 +4334,7 @@ void SelectionDAGBuilder::visitGetElementPtr(const User &I) { SDNodeFlags Flags; if (NW.hasNoUnsignedWrap() || (int64_t(Offset) >= 0 && NW.hasNoUnsignedSignedWrap())) - Flags.setNoUnsignedWrap(true); + Flags |= SDNodeFlags::NoUnsignedWrap; N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, DAG.getConstant(Offset, dl, N.getValueType()), Flags); @@ -4527,10 +4527,9 @@ void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { // Round the size of the allocation up to the stack alignment size // by add SA-1 to the size. This doesn't overflow because we're computing // an address inside an alloca. - SDNodeFlags Flags; - Flags.setNoUnsignedWrap(true); AllocSize = DAG.getNode(ISD::ADD, dl, AllocSize.getValueType(), AllocSize, - DAG.getConstant(StackAlignMask, dl, IntPtr), Flags); + DAG.getConstant(StackAlignMask, dl, IntPtr), + SDNodeFlags::NoUnsignedWrap); // Mask out the low bits for alignment purposes. AllocSize = DAG.getNode(ISD::AND, dl, AllocSize.getValueType(), AllocSize, @@ -11430,15 +11429,13 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const { // An aggregate return value cannot wrap around the address space, so // offsets to its parts don't wrap either. - SDNodeFlags Flags; - Flags.setNoUnsignedWrap(true); - MachineFunction &MF = CLI.DAG.getMachineFunction(); Align HiddenSRetAlign = MF.getFrameInfo().getObjectAlign(DemoteStackIdx); for (unsigned i = 0; i < NumValues; ++i) { - SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot, - CLI.DAG.getConstant(Offsets[i], CLI.DL, - PtrVT), Flags); + SDValue Add = + CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot, + CLI.DAG.getConstant(Offsets[i], CLI.DL, PtrVT), + SDNodeFlags::NoUnsignedWrap); SDValue L = CLI.DAG.getLoad( RetTys[i], CLI.DL, CLI.Chain, Add, MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(), diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 981ab18b59c1c1d464b82df69aecb2a58a109bca..0d99ae9cdebd5044d4d2e5a2ad409d53340581ab 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -4224,11 +4224,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch, // Set the NoFPExcept flag when no original matched node could // raise an FP exception, but the new node potentially might. - if (!MayRaiseFPException && mayRaiseFPException(Res)) { - SDNodeFlags Flags = Res->getFlags(); - Flags.setNoFPExcept(true); - Res->setFlags(Flags); - } + if (!MayRaiseFPException && mayRaiseFPException(Res)) + Res->setFlags(Res->getFlags() | SDNodeFlags::NoFPExcept); // If the node had chain/glue results, update our notion of the current // chain and glue. diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 3cbe9aa63a0324501f15205be8125b1aa2c03d88..fa3567016e97be352265fc9ec3621065fce6106d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1486,22 +1486,15 @@ bool TargetLowering::SimplifyDemandedBits( case ISD::OR: { SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); - SDNodeFlags Flags = Op.getNode()->getFlags(); if (SimplifyDemandedBits(Op1, DemandedBits, DemandedElts, Known, TLO, Depth + 1)) { - if (Flags.hasDisjoint()) { - Flags.setDisjoint(false); - Op->setFlags(Flags); - } + Op->dropFlags(SDNodeFlags::Disjoint); return true; } if (SimplifyDemandedBits(Op0, ~Known.One & DemandedBits, DemandedElts, Known2, TLO, Depth + 1)) { - if (Flags.hasDisjoint()) { - Flags.setDisjoint(false); - Op->setFlags(Flags); - } + Op->dropFlags(SDNodeFlags::Disjoint); return true; } @@ -1806,14 +1799,9 @@ bool TargetLowering::SimplifyDemandedBits( APInt InDemandedMask = DemandedBits.lshr(ShAmt); if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO, Depth + 1)) { - SDNodeFlags Flags = Op.getNode()->getFlags(); - if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) { - // Disable the nsw and nuw flags. We can no longer guarantee that we - // won't wrap after simplification. - Flags.setNoSignedWrap(false); - Flags.setNoUnsignedWrap(false); - Op->setFlags(Flags); - } + // Disable the nsw and nuw flags. We can no longer guarantee that we + // won't wrap after simplification. + Op->dropFlags(SDNodeFlags::NoWrap); return true; } Known.Zero <<= ShAmt; @@ -1897,14 +1885,9 @@ bool TargetLowering::SimplifyDemandedBits( APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ)); if (SimplifyDemandedBits(Op0, DemandedFromOp, DemandedElts, Known, TLO, Depth + 1)) { - SDNodeFlags Flags = Op.getNode()->getFlags(); - if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) { - // Disable the nsw and nuw flags. We can no longer guarantee that we - // won't wrap after simplification. - Flags.setNoSignedWrap(false); - Flags.setNoUnsignedWrap(false); - Op->setFlags(Flags); - } + // Disable the nsw and nuw flags. We can no longer guarantee that we + // won't wrap after simplification. + Op->dropFlags(SDNodeFlags::NoWrap); return true; } Known.resetAll(); @@ -2456,15 +2439,11 @@ bool TargetLowering::SimplifyDemandedBits( return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src)); } - SDNodeFlags Flags = Op->getFlags(); APInt InDemandedBits = DemandedBits.trunc(InBits); APInt InDemandedElts = DemandedElts.zext(InElts); if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, Depth + 1)) { - if (Flags.hasNonNeg()) { - Flags.setNonNeg(false); - Op->setFlags(Flags); - } + Op->dropFlags(SDNodeFlags::NonNeg); return true; } assert(Known.getBitWidth() == InBits && "Src width has changed?"); @@ -2528,7 +2507,7 @@ bool TargetLowering::SimplifyDemandedBits( if (!TLO.LegalOperations() || isOperationLegal(Opc, VT)) { SDNodeFlags Flags; if (!IsVecInReg) - Flags.setNonNeg(true); + Flags |= SDNodeFlags::NonNeg; return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, Src, Flags)); } } @@ -2836,13 +2815,9 @@ bool TargetLowering::SimplifyDemandedBits( DemandedElts, KnownOp0, TLO, Depth + 1) || // See if the operation should be performed at a smaller bit width. ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO)) { - if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) { - // Disable the nsw and nuw flags. We can no longer guarantee that we - // won't wrap after simplification. - Flags.setNoSignedWrap(false); - Flags.setNoUnsignedWrap(false); - Op->setFlags(Flags); - } + // Disable the nsw and nuw flags. We can no longer guarantee that we + // won't wrap after simplification. + Op->dropFlags(SDNodeFlags::NoWrap); return true; } @@ -2858,12 +2833,10 @@ bool TargetLowering::SimplifyDemandedBits( SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( Op1, LoMask, DemandedElts, TLO.DAG, Depth + 1); if (DemandedOp0 || DemandedOp1) { - Flags.setNoSignedWrap(false); - Flags.setNoUnsignedWrap(false); Op0 = DemandedOp0 ? DemandedOp0 : Op0; Op1 = DemandedOp1 ? DemandedOp1 : Op1; - SDValue NewOp = - TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags); + SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, + Flags & ~SDNodeFlags::NoWrap); return TLO.CombineTo(Op, NewOp); } } @@ -2880,9 +2853,8 @@ bool TargetLowering::SimplifyDemandedBits( SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT); // Disable the nsw and nuw flags. We can no longer guarantee that we // won't wrap after simplification. - Flags.setNoSignedWrap(false); - Flags.setNoUnsignedWrap(false); - SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, Flags); + SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Neg1, + Flags & ~SDNodeFlags::NoWrap); return TLO.CombineTo(Op, NewOp); } @@ -6157,9 +6129,7 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDNode *N, SDValue Res = Op0; if (UseSRA) { - SDNodeFlags Flags; - Flags.setExact(true); - Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, Flags); + Res = DAG.getNode(ISD::SRA, dl, VT, Res, Shift, SDNodeFlags::Exact); Created.push_back(Res.getNode()); } @@ -6220,9 +6190,7 @@ static SDValue BuildExactUDIV(const TargetLowering &TLI, SDNode *N, SDValue Res = N->getOperand(0); if (UseSRL) { - SDNodeFlags Flags; - Flags.setExact(true); - Res = DAG.getNode(ISD::SRL, dl, VT, Res, Shift, Flags); + Res = DAG.getNode(ISD::SRL, dl, VT, Res, Shift, SDNodeFlags::Exact); Created.push_back(Res.getNode()); } @@ -8447,9 +8415,7 @@ TargetLowering::createSelectForFMINNUM_FMAXNUM(SDNode *Node, SDValue SelCC = DAG.getSelectCC(SDLoc(Node), Op1, Op2, Op1, Op2, Pred); // Copy FMF flags, but always set the no-signed-zeros flag // as this is implied by the FMINNUM/FMAXNUM semantics. - SDNodeFlags Flags = Node->getFlags(); - Flags.setNoSignedZeros(true); - SelCC->setFlags(Flags); + SelCC->setFlags(Node->getFlags() | SDNodeFlags::NoSignedZeros); return SelCC; } @@ -11808,10 +11774,8 @@ SDValue TargetLowering::expandVECTOR_COMPRESS(SDNode *Node, // Re-write the last ValI if all lanes were selected. Otherwise, // overwrite the last write it with the passthru value. - SDNodeFlags Flags{}; - Flags.setUnpredictable(true); LastWriteVal = DAG.getSelect(DL, ScalarVT, AllLanesSelected, ValI, - LastWriteVal, Flags); + LastWriteVal, SDNodeFlags::Unpredictable); Chain = DAG.getStore( Chain, DL, LastWriteVal, OutPtr, MachinePointerInfo::getUnknownStack(DAG.getMachineFunction())); diff --git a/llvm/lib/CodeGen/TailDuplication.cpp b/llvm/lib/CodeGen/TailDuplication.cpp index 25f20d9c899bb07c1fe91c781ab7a9c5425d5085..b698ca675b65e2d104d6ae65400e17bbc48715a6 100644 --- a/llvm/lib/CodeGen/TailDuplication.cpp +++ b/llvm/lib/CodeGen/TailDuplication.cpp @@ -12,13 +12,16 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/TailDuplication.h" #include "llvm/Analysis/ProfileSummaryInfo.h" #include "llvm/CodeGen/LazyMachineBlockFrequencyInfo.h" #include "llvm/CodeGen/MBFIWrapper.h" #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachinePassManager.h" #include "llvm/CodeGen/TailDuplicator.h" +#include "llvm/IR/Analysis.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" #include "llvm/PassRegistry.h" @@ -29,13 +32,13 @@ using namespace llvm; namespace { -class TailDuplicateBase : public MachineFunctionPass { +class TailDuplicateBaseLegacy : public MachineFunctionPass { TailDuplicator Duplicator; std::unique_ptr MBFIW; bool PreRegAlloc; public: - TailDuplicateBase(char &PassID, bool PreRegAlloc) - : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {} + TailDuplicateBaseLegacy(char &PassID, bool PreRegAlloc) + : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {} bool runOnMachineFunction(MachineFunction &MF) override; @@ -47,19 +50,19 @@ public: } }; -class TailDuplicate : public TailDuplicateBase { +class TailDuplicateLegacy : public TailDuplicateBaseLegacy { public: static char ID; - TailDuplicate() : TailDuplicateBase(ID, false) { - initializeTailDuplicatePass(*PassRegistry::getPassRegistry()); + TailDuplicateLegacy() : TailDuplicateBaseLegacy(ID, false) { + initializeTailDuplicateLegacyPass(*PassRegistry::getPassRegistry()); } }; -class EarlyTailDuplicate : public TailDuplicateBase { +class EarlyTailDuplicateLegacy : public TailDuplicateBaseLegacy { public: static char ID; - EarlyTailDuplicate() : TailDuplicateBase(ID, true) { - initializeEarlyTailDuplicatePass(*PassRegistry::getPassRegistry()); + EarlyTailDuplicateLegacy() : TailDuplicateBaseLegacy(ID, true) { + initializeEarlyTailDuplicateLegacyPass(*PassRegistry::getPassRegistry()); } MachineFunctionProperties getClearedProperties() const override { @@ -70,17 +73,18 @@ public: } // end anonymous namespace -char TailDuplicate::ID; -char EarlyTailDuplicate::ID; +char TailDuplicateLegacy::ID; +char EarlyTailDuplicateLegacy::ID; -char &llvm::TailDuplicateID = TailDuplicate::ID; -char &llvm::EarlyTailDuplicateID = EarlyTailDuplicate::ID; +char &llvm::TailDuplicateLegacyID = TailDuplicateLegacy::ID; +char &llvm::EarlyTailDuplicateLegacyID = EarlyTailDuplicateLegacy::ID; -INITIALIZE_PASS(TailDuplicate, DEBUG_TYPE, "Tail Duplication", false, false) -INITIALIZE_PASS(EarlyTailDuplicate, "early-tailduplication", +INITIALIZE_PASS(TailDuplicateLegacy, DEBUG_TYPE, "Tail Duplication", false, + false) +INITIALIZE_PASS(EarlyTailDuplicateLegacy, "early-tailduplication", "Early Tail Duplication", false, false) -bool TailDuplicateBase::runOnMachineFunction(MachineFunction &MF) { +bool TailDuplicateBaseLegacy::runOnMachineFunction(MachineFunction &MF) { if (skipFunction(MF.getFunction())) return false; @@ -100,3 +104,36 @@ bool TailDuplicateBase::runOnMachineFunction(MachineFunction &MF) { return MadeChange; } + +template +PreservedAnalyses TailDuplicatePassBase::run( + MachineFunction &MF, MachineFunctionAnalysisManager &MFAM) { + MFPropsModifier _(static_cast(*this), MF); + + if (MF.getFunction().hasOptNone()) + return PreservedAnalyses::all(); + + auto *MBPI = &MFAM.getResult(MF); + auto *PSI = MFAM.getResult(MF) + .getCachedResult( + *MF.getFunction().getParent()); + auto *MBFI = (PSI && PSI->hasProfileSummary() + ? &MFAM.getResult(MF) + : nullptr); + if (MBFI) + MBFIW = std::make_unique(*MBFI); + + TailDuplicator Duplicator; + Duplicator.initMF(MF, PreRegAlloc, MBPI, MBFI ? MBFIW.get() : nullptr, PSI, + /*LayoutMode=*/false); + bool MadeChange = false; + while (Duplicator.tailDuplicateBlocks()) + MadeChange = true; + + if (!MadeChange) + return PreservedAnalyses::all(); + return getMachineFunctionPassPreservedAnalyses(); +} + +template class llvm::TailDuplicatePassBase; +template class llvm::TailDuplicatePassBase; diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 12225c9946e9fc7ce07652592fc6a6df98cc521a..aff74104006e5a75b9d5fd4f82eeb313f185020e 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -290,10 +290,10 @@ static IdentifyingPassPtr overridePass(AnalysisID StandardID, if (StandardID == &BranchFolderPassID) return applyDisable(TargetID, DisableBranchFold); - if (StandardID == &TailDuplicateID) + if (StandardID == &TailDuplicateLegacyID) return applyDisable(TargetID, DisableTailDuplicate); - if (StandardID == &EarlyTailDuplicateID) + if (StandardID == &EarlyTailDuplicateLegacyID) return applyDisable(TargetID, DisableEarlyTailDup); if (StandardID == &MachineBlockPlacementID) @@ -1279,7 +1279,7 @@ void TargetPassConfig::addMachinePasses() { /// Add passes that optimize machine instructions in SSA form. void TargetPassConfig::addMachineSSAOptimization() { // Pre-ra tail duplication. - addPass(&EarlyTailDuplicateID); + addPass(&EarlyTailDuplicateLegacyID); // Optimize PHIs before DCE: removing dead PHI cycles may make more // instructions dead. @@ -1507,7 +1507,7 @@ void TargetPassConfig::addMachineLateOptimization() { // performance for targets that require Structured Control Flow. // In addition it can also make CFG irreducible. Thus we disable it. if (!TM->requiresStructuredCFG()) - addPass(&TailDuplicateID); + addPass(&TailDuplicateLegacyID); // Copy propagation. addPass(&MachineCopyPropagationID); diff --git a/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp b/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp index 4ef217e6c562db2330c0d9fa7328a372efd3c94e..81294cad4d7d426de0a993c95170f239831b4377 100644 --- a/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp +++ b/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp @@ -52,17 +52,18 @@ void JITLinkRedirectableSymbolManager::emitRedirectableSymbols( return; } + // FIXME: return stubs to the pool here too. if (auto Err = R->replace(absoluteSymbols(NewSymbolDefs))) { ES.reportError(std::move(Err)); R->failMaterialization(); return; } - auto Err = R->withResourceKeyDo([&](ResourceKey Key) { - TrackedResources[Key].insert(TrackedResources[Key].end(), Symbols.begin(), - Symbols.end()); - }); - if (Err) { + // FIXME: return stubs to the pool here too. + if (auto Err = R->withResourceKeyDo([&](ResourceKey Key) { + TrackedResources[Key].insert(TrackedResources[Key].end(), + Symbols.begin(), Symbols.end()); + })) { ES.reportError(std::move(Err)); R->failMaterialization(); return; diff --git a/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp b/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp index 25ab154a01d674f5450d6ceba7c53b57a13c7e40..86c08cbdee5f32ee29a2ccd34a80a5dbfb1a1204 100644 --- a/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/ObjectLinkingLayer.cpp @@ -701,16 +701,15 @@ Error ObjectLinkingLayer::handleRemoveResources(JITDylib &JD, ResourceKey K) { void ObjectLinkingLayer::handleTransferResources(JITDylib &JD, ResourceKey DstKey, ResourceKey SrcKey) { - auto I = Allocs.find(SrcKey); - if (I != Allocs.end()) { - auto &SrcAllocs = I->second; + if (Allocs.contains(SrcKey)) { + // DstKey may not be in the DenseMap yet, so the following line may resize + // the container and invalidate iterators and value references. auto &DstAllocs = Allocs[DstKey]; + auto &SrcAllocs = Allocs[SrcKey]; DstAllocs.reserve(DstAllocs.size() + SrcAllocs.size()); for (auto &Alloc : SrcAllocs) DstAllocs.push_back(std::move(Alloc)); - // Erase SrcKey entry using value rather than iterator I: I may have been - // invalidated when we looked up DstKey. Allocs.erase(SrcKey); } diff --git a/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp b/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp index bc3433d011551c2ec3de680076429c9d1a3426e3..a73b2310d193aa9d8d16c1d1f86f5c48df806d58 100644 --- a/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.cpp @@ -430,16 +430,15 @@ Error RTDyldObjectLinkingLayer::handleRemoveResources(JITDylib &JD, void RTDyldObjectLinkingLayer::handleTransferResources(JITDylib &JD, ResourceKey DstKey, ResourceKey SrcKey) { - auto I = MemMgrs.find(SrcKey); - if (I != MemMgrs.end()) { - auto &SrcMemMgrs = I->second; + if (MemMgrs.contains(SrcKey)) { + // DstKey may not be in the DenseMap yet, so the following line may resize + // the container and invalidate iterators and value references. auto &DstMemMgrs = MemMgrs[DstKey]; + auto &SrcMemMgrs = MemMgrs[SrcKey]; DstMemMgrs.reserve(DstMemMgrs.size() + SrcMemMgrs.size()); for (auto &MemMgr : SrcMemMgrs) DstMemMgrs.push_back(std::move(MemMgr)); - // Erase SrcKey entry using value rather than iterator I: I may have been - // invalidated when we looked up DstKey. MemMgrs.erase(SrcKey); } } diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index f6f2b9e60c8e72e006fbce8102bad3912d2d64e9..d484463b7edf89972227af0093fa0446977b54ec 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -4122,8 +4122,9 @@ void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) { GetElementPtrInst::getIndexedType(GEP.getSourceElementType(), Idxs); Check(ElTy, "Invalid indices for GEP pointer type!", &GEP); - Check(GEP.getType()->isPtrOrPtrVectorTy() && - GEP.getResultElementType() == ElTy, + PointerType *PtrTy = dyn_cast(GEP.getType()->getScalarType()); + + Check(PtrTy && GEP.getResultElementType() == ElTy, "GEP is not of right type for indices!", &GEP, ElTy); if (auto *GEPVTy = dyn_cast(GEP.getType())) { @@ -4145,10 +4146,8 @@ void Verifier::visitGetElementPtrInst(GetElementPtrInst &GEP) { } } - if (auto *PTy = dyn_cast(GEP.getType())) { - Check(GEP.getAddressSpace() == PTy->getAddressSpace(), - "GEP address space doesn't match type", &GEP); - } + Check(GEP.getAddressSpace() == PtrTy->getAddressSpace(), + "GEP address space doesn't match type", &GEP); visitInstruction(GEP); } diff --git a/llvm/lib/MC/MCInstPrinter.cpp b/llvm/lib/MC/MCInstPrinter.cpp index e4faeba04a8fd7fada21a566d355b77997c612c6..069716a3ecf9b70ff8abc0315913df0ea8ad8c7c 100644 --- a/llvm/lib/MC/MCInstPrinter.cpp +++ b/llvm/lib/MC/MCInstPrinter.cpp @@ -43,7 +43,7 @@ StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const { return MII.getName(Opcode); } -void MCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void MCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { llvm_unreachable("Target should implement this"); } @@ -224,29 +224,32 @@ format_object MCInstPrinter::formatHex(uint64_t Value) const { llvm_unreachable("unsupported print style"); } -MCInstPrinter::WithMarkup MCInstPrinter::markup(raw_ostream &OS, - Markup S) const { - return WithMarkup(OS, S, getUseMarkup(), getUseColor()); +MCInstPrinter::WithMarkup MCInstPrinter::markup(raw_ostream &OS, Markup S) { + return WithMarkup(*this, OS, S, getUseMarkup(), getUseColor()); } -MCInstPrinter::WithMarkup::WithMarkup(raw_ostream &OS, Markup M, - bool EnableMarkup, bool EnableColor) - : OS(OS), EnableMarkup(EnableMarkup), EnableColor(EnableColor) { +MCInstPrinter::WithMarkup::WithMarkup(MCInstPrinter &IP, raw_ostream &OS, + Markup M, bool EnableMarkup, + bool EnableColor) + : IP(IP), OS(OS), EnableMarkup(EnableMarkup), EnableColor(EnableColor) { if (EnableColor) { + raw_ostream::Colors Color = raw_ostream::Colors::RESET; switch (M) { case Markup::Immediate: - OS.changeColor(raw_ostream::RED); + Color = raw_ostream::RED; break; case Markup::Register: - OS.changeColor(raw_ostream::CYAN); + Color = raw_ostream::CYAN; break; case Markup::Target: - OS.changeColor(raw_ostream::YELLOW); + Color = raw_ostream::YELLOW; break; case Markup::Memory: - OS.changeColor(raw_ostream::GREEN); + Color = raw_ostream::GREEN; break; } + IP.ColorStack.push_back(Color); + OS.changeColor(Color); } if (EnableMarkup) { @@ -270,6 +273,8 @@ MCInstPrinter::WithMarkup::WithMarkup(raw_ostream &OS, Markup M, MCInstPrinter::WithMarkup::~WithMarkup() { if (EnableMarkup) OS << '>'; - if (EnableColor) - OS.resetColor(); + if (!EnableColor) + return; + IP.ColorStack.pop_back(); + OS << IP.ColorStack.back(); } diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp index 4774e5112af535f3a693c3eb9b3cbf4104ba4d61..ecccb228c8c387533c8fda5cf73d817170de3d1f 100644 --- a/llvm/lib/MC/MCParser/AsmParser.cpp +++ b/llvm/lib/MC/MCParser/AsmParser.cpp @@ -264,7 +264,7 @@ public: SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, - const MCInstrInfo *MII, const MCInstPrinter *IP, + const MCInstrInfo *MII, MCInstPrinter *IP, MCAsmParserSemaCallback &SI) override; bool parseExpression(const MCExpr *&Res); @@ -6006,7 +6006,7 @@ bool AsmParser::parseMSInlineAsm( SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, const MCInstrInfo *MII, - const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) { + MCInstPrinter *IP, MCAsmParserSemaCallback &SI) { SmallVector InputDecls; SmallVector OutputDecls; SmallVector InputDeclsAddressOf; diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp index d88fd09a1aa07c6009b0f2295bfd8d0e39cd2353..a7f37d81f64092987b4496f342b549f4ae1a1a88 100644 --- a/llvm/lib/MC/MCParser/MasmParser.cpp +++ b/llvm/lib/MC/MCParser/MasmParser.cpp @@ -539,7 +539,7 @@ public: SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, - const MCInstrInfo *MII, const MCInstPrinter *IP, + const MCInstrInfo *MII, MCInstPrinter *IP, MCAsmParserSemaCallback &SI) override; bool parseExpression(const MCExpr *&Res); @@ -7340,7 +7340,7 @@ bool MasmParser::parseMSInlineAsm( SmallVectorImpl> &OpDecls, SmallVectorImpl &Constraints, SmallVectorImpl &Clobbers, const MCInstrInfo *MII, - const MCInstPrinter *IP, MCAsmParserSemaCallback &SI) { + MCInstPrinter *IP, MCAsmParserSemaCallback &SI) { SmallVector InputDecls; SmallVector OutputDecls; SmallVector InputDeclsAddressOf; diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 8da8b58e767037d91096fc62b844dc7d106cb56d..d2ce6a81ffde988e95e10499f6285708ed092ef3 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -125,6 +125,7 @@ #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/CodeGen/StackColoring.h" #include "llvm/CodeGen/StackProtector.h" +#include "llvm/CodeGen/TailDuplication.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TwoAddressInstructionPass.h" #include "llvm/CodeGen/TypePromotion.h" diff --git a/llvm/lib/Passes/PassBuilderPipelines.cpp b/llvm/lib/Passes/PassBuilderPipelines.cpp index ab9594bd2799ba3e09210b201ee6677e36bc0b78..e674ea217f0cf3a06161fa21ca6b564616f63663 100644 --- a/llvm/lib/Passes/PassBuilderPipelines.cpp +++ b/llvm/lib/Passes/PassBuilderPipelines.cpp @@ -1147,7 +1147,8 @@ PassBuilder::buildModuleSimplificationPipeline(OptimizationLevel Level, // post link pipeline after ICP. This is to enable usage of the type // tests in ICP sequences. if (Phase == ThinOrFullLTOPhase::ThinLTOPostLink) - MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, + lowertypetests::DropTestKind::Assume)); invokePipelineEarlySimplificationEPCallbacks(MPM, Level); @@ -1800,7 +1801,8 @@ ModulePassManager PassBuilder::buildThinLTODefaultPipeline( if (Level == OptimizationLevel::O0) { // Run a second time to clean up any type tests left behind by WPD for use // in ICP. - MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, + lowertypetests::DropTestKind::Assume)); // Drop available_externally and unreferenced globals. This is necessary // with ThinLTO in order to avoid leaving undefined references to dead // globals in the object file. @@ -1851,7 +1853,8 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, MPM.addPass(LowerTypeTestsPass(ExportSummary, nullptr)); // Run a second time to clean up any type tests left behind by WPD for use // in ICP. - MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, + lowertypetests::DropTestKind::Assume)); invokeFullLinkTimeOptimizationLastEPCallbacks(MPM, Level); @@ -1929,7 +1932,8 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, // Run a second time to clean up any type tests left behind by WPD for use // in ICP (which is performed earlier than this in the regular LTO // pipeline). - MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, + lowertypetests::DropTestKind::Assume)); invokeFullLinkTimeOptimizationLastEPCallbacks(MPM, Level); @@ -2110,7 +2114,8 @@ PassBuilder::buildLTODefaultPipeline(OptimizationLevel Level, MPM.addPass(LowerTypeTestsPass(ExportSummary, nullptr)); // Run a second time to clean up any type tests left behind by WPD for use // in ICP (which is performed earlier than this in the regular LTO pipeline). - MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, true)); + MPM.addPass(LowerTypeTestsPass(nullptr, nullptr, + lowertypetests::DropTestKind::Assume)); // Enable splitting late in the FullLTO post-link pipeline. if (EnableHotColdSplit) diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp index 1a3721bf103503363c02360ba2aedf7e6228026e..0ab9f942a085895e026af552c3199d6bbdda6507 100644 --- a/llvm/lib/ProfileData/InstrProfWriter.cpp +++ b/llvm/lib/ProfileData/InstrProfWriter.cpp @@ -19,6 +19,7 @@ #include "llvm/ProfileData/InstrProf.h" #include "llvm/ProfileData/MemProf.h" #include "llvm/ProfileData/ProfileCommon.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Compression.h" #include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" @@ -28,6 +29,7 @@ #include "llvm/Support/OnDiskHashTable.h" #include "llvm/Support/raw_ostream.h" #include +#include #include #include #include @@ -184,13 +186,25 @@ public: InstrProfWriter::InstrProfWriter( bool Sparse, uint64_t TemporalProfTraceReservoirSize, uint64_t MaxTemporalProfTraceLength, bool WritePrevVersion, - memprof::IndexedVersion MemProfVersionRequested, bool MemProfFullSchema) + memprof::IndexedVersion MemProfVersionRequested, bool MemProfFullSchema, + bool MemprofGenerateRandomHotness, + unsigned MemprofGenerateRandomHotnessSeed) : Sparse(Sparse), MaxTemporalProfTraceLength(MaxTemporalProfTraceLength), TemporalProfTraceReservoirSize(TemporalProfTraceReservoirSize), InfoObj(new InstrProfRecordWriterTrait()), WritePrevVersion(WritePrevVersion), MemProfVersionRequested(MemProfVersionRequested), - MemProfFullSchema(MemProfFullSchema) {} + MemProfFullSchema(MemProfFullSchema), + MemprofGenerateRandomHotness(MemprofGenerateRandomHotness) { + // Set up the random number seed if requested. + if (MemprofGenerateRandomHotness) { + unsigned seed = MemprofGenerateRandomHotnessSeed + ? MemprofGenerateRandomHotnessSeed + : std::time(nullptr); + errs() << "random hotness seed = " << seed << "\n"; + std::srand(seed); + } +} InstrProfWriter::~InstrProfWriter() { delete InfoObj; } @@ -273,13 +287,34 @@ void InstrProfWriter::addRecord(StringRef Name, uint64_t Hash, void InstrProfWriter::addMemProfRecord( const Function::GUID Id, const memprof::IndexedMemProfRecord &Record) { - auto [Iter, Inserted] = MemProfData.Records.insert({Id, Record}); + auto NewRecord = Record; + // Provoke random hotness values if requested. We specify the lifetime access + // density and lifetime length that will result in a cold or not cold hotness. + // See the logic in getAllocType() in Analysis/MemoryProfileInfo.cpp. + if (MemprofGenerateRandomHotness) { + for (auto &Alloc : NewRecord.AllocSites) { + // To get a not cold context, set the lifetime access density to the + // maximum value and the lifetime to 0. + uint64_t NewTLAD = std::numeric_limits::max(); + uint64_t NewTL = 0; + bool IsCold = std::rand() % 2; + if (IsCold) { + // To get a cold context, set the lifetime access density to 0 and the + // lifetime to the maximum value. + NewTLAD = 0; + NewTL = std::numeric_limits::max(); + } + Alloc.Info.setTotalLifetimeAccessDensity(NewTLAD); + Alloc.Info.setTotalLifetime(NewTL); + } + } + auto [Iter, Inserted] = MemProfData.Records.insert({Id, NewRecord}); // If we inserted a new record then we are done. if (Inserted) { return; } memprof::IndexedMemProfRecord &Existing = Iter->second; - Existing.merge(Record); + Existing.merge(NewRecord); } bool InstrProfWriter::addMemProfFrame(const memprof::FrameId Id, diff --git a/llvm/lib/SandboxIR/Context.cpp b/llvm/lib/SandboxIR/Context.cpp index 486e935bc35fba84a5d180bd27f4337cb29257a6..b86ed5864c1ac1de18964253d13ab91766f7b279 100644 --- a/llvm/lib/SandboxIR/Context.cpp +++ b/llvm/lib/SandboxIR/Context.cpp @@ -35,17 +35,20 @@ Value *Context::registerValue(std::unique_ptr &&VPtr) { assert(VPtr->getSubclassID() != Value::ClassID::User && "Can't register a user!"); + Value *V = VPtr.get(); + [[maybe_unused]] auto Pair = + LLVMValueToValueMap.insert({VPtr->Val, std::move(VPtr)}); + assert(Pair.second && "Already exists!"); + // Track creation of instructions. // Please note that we don't allow the creation of detached instructions, // meaning that the instructions need to be inserted into a block upon // creation. This is why the tracker class combines creation and insertion. - if (auto *I = dyn_cast(VPtr.get())) + if (auto *I = dyn_cast(V)) { getTracker().emplaceIfTracking(I); + runCreateInstrCallbacks(I); + } - Value *V = VPtr.get(); - [[maybe_unused]] auto Pair = - LLVMValueToValueMap.insert({VPtr->Val, std::move(VPtr)}); - assert(Pair.second && "Already exists!"); return V; } @@ -660,4 +663,64 @@ Module *Context::createModule(llvm::Module *LLVMM) { return M; } +void Context::runEraseInstrCallbacks(Instruction *I) { + for (const auto &CBEntry : EraseInstrCallbacks) + CBEntry.second(I); +} + +void Context::runCreateInstrCallbacks(Instruction *I) { + for (auto &CBEntry : CreateInstrCallbacks) + CBEntry.second(I); +} + +void Context::runMoveInstrCallbacks(Instruction *I, const BBIterator &WhereIt) { + for (auto &CBEntry : MoveInstrCallbacks) + CBEntry.second(I, WhereIt); +} + +// An arbitrary limit, to check for accidental misuse. We expect a small number +// of callbacks to be registered at a time, but we can increase this number if +// we discover we needed more. +[[maybe_unused]] static constexpr int MaxRegisteredCallbacks = 16; + +Context::CallbackID Context::registerEraseInstrCallback(EraseInstrCallback CB) { + assert(EraseInstrCallbacks.size() <= MaxRegisteredCallbacks && + "EraseInstrCallbacks size limit exceeded"); + CallbackID ID = NextCallbackID++; + EraseInstrCallbacks[ID] = CB; + return ID; +} +void Context::unregisterEraseInstrCallback(CallbackID ID) { + [[maybe_unused]] bool Erased = EraseInstrCallbacks.erase(ID); + assert(Erased && + "Callback ID not found in EraseInstrCallbacks during deregistration"); +} + +Context::CallbackID +Context::registerCreateInstrCallback(CreateInstrCallback CB) { + assert(CreateInstrCallbacks.size() <= MaxRegisteredCallbacks && + "CreateInstrCallbacks size limit exceeded"); + CallbackID ID = NextCallbackID++; + CreateInstrCallbacks[ID] = CB; + return ID; +} +void Context::unregisterCreateInstrCallback(CallbackID ID) { + [[maybe_unused]] bool Erased = CreateInstrCallbacks.erase(ID); + assert(Erased && + "Callback ID not found in CreateInstrCallbacks during deregistration"); +} + +Context::CallbackID Context::registerMoveInstrCallback(MoveInstrCallback CB) { + assert(MoveInstrCallbacks.size() <= MaxRegisteredCallbacks && + "MoveInstrCallbacks size limit exceeded"); + CallbackID ID = NextCallbackID++; + MoveInstrCallbacks[ID] = CB; + return ID; +} +void Context::unregisterMoveInstrCallback(CallbackID ID) { + [[maybe_unused]] bool Erased = MoveInstrCallbacks.erase(ID); + assert(Erased && + "Callback ID not found in MoveInstrCallbacks during deregistration"); +} + } // namespace llvm::sandboxir diff --git a/llvm/lib/SandboxIR/Instruction.cpp b/llvm/lib/SandboxIR/Instruction.cpp index d80d10370e32d8edd5811f293cd5e479499e0067..096b827541eeafa288cd1917dc8dbfe7e51bb141 100644 --- a/llvm/lib/SandboxIR/Instruction.cpp +++ b/llvm/lib/SandboxIR/Instruction.cpp @@ -73,6 +73,8 @@ void Instruction::removeFromParent() { void Instruction::eraseFromParent() { assert(users().empty() && "Still connected to users, can't erase!"); + + Ctx.runEraseInstrCallbacks(this); std::unique_ptr Detached = Ctx.detach(this); auto LLVMInstrs = getLLVMInstrs(); @@ -100,6 +102,7 @@ void Instruction::moveBefore(BasicBlock &BB, const BBIterator &WhereIt) { // Destination is same as origin, nothing to do. return; + Ctx.runMoveInstrCallbacks(this, WhereIt); Ctx.getTracker().emplaceIfTracking(this); auto *LLVMBB = cast(BB.Val); diff --git a/llvm/lib/Support/CMakeLists.txt b/llvm/lib/Support/CMakeLists.txt index 531bdeaca12614fda247d79182e6c2a2786568f4..2ecaea4b02bf61839dd22723a3b14d7f492fd4ac 100644 --- a/llvm/lib/Support/CMakeLists.txt +++ b/llvm/lib/Support/CMakeLists.txt @@ -256,6 +256,7 @@ add_llvm_component_library(LLVMSupport TimeProfiler.cpp Timer.cpp ToolOutputFile.cpp + TrieRawHashMap.cpp Twine.cpp TypeSize.cpp Unicode.cpp diff --git a/llvm/lib/Support/TrieRawHashMap.cpp b/llvm/lib/Support/TrieRawHashMap.cpp new file mode 100644 index 0000000000000000000000000000000000000000..11d79a62d011ddf87ad4edd12c357d1fbc592bc3 --- /dev/null +++ b/llvm/lib/Support/TrieRawHashMap.cpp @@ -0,0 +1,515 @@ +//===- TrieRawHashMap.cpp -------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/TrieRawHashMap.h" +#include "llvm/ADT/LazyAtomicPointer.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/TrieHashIndexGenerator.h" +#include "llvm/Support/Allocator.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ThreadSafeAllocator.h" +#include "llvm/Support/TrailingObjects.h" +#include "llvm/Support/raw_ostream.h" +#include + +using namespace llvm; + +namespace { +struct TrieNode { + const bool IsSubtrie = false; + + TrieNode(bool IsSubtrie) : IsSubtrie(IsSubtrie) {} + + static void *operator new(size_t Size) { return ::operator new(Size); } + void operator delete(void *Ptr) { ::operator delete(Ptr); } +}; + +struct TrieContent final : public TrieNode { + const uint8_t ContentOffset; + const uint8_t HashSize; + const uint8_t HashOffset; + + void *getValuePointer() const { + auto *Content = reinterpret_cast(this) + ContentOffset; + return const_cast(Content); + } + + ArrayRef getHash() const { + auto *Begin = reinterpret_cast(this) + HashOffset; + return ArrayRef(Begin, Begin + HashSize); + } + + TrieContent(size_t ContentOffset, size_t HashSize, size_t HashOffset) + : TrieNode(/*IsSubtrie=*/false), ContentOffset(ContentOffset), + HashSize(HashSize), HashOffset(HashOffset) {} + + static bool classof(const TrieNode *TN) { return !TN->IsSubtrie; } +}; + +static_assert(sizeof(TrieContent) == + ThreadSafeTrieRawHashMapBase::TrieContentBaseSize, + "Check header assumption!"); + +class TrieSubtrie final + : public TrieNode, + private TrailingObjects> { +public: + using Slot = LazyAtomicPointer; + + Slot &get(size_t I) { return getTrailingObjects()[I]; } + TrieNode *load(size_t I) { return get(I).load(); } + + unsigned size() const { return Size; } + + TrieSubtrie * + sink(size_t I, TrieContent &Content, size_t NumSubtrieBits, size_t NewI, + function_ref)> Saver); + + static std::unique_ptr create(size_t StartBit, size_t NumBits); + + explicit TrieSubtrie(size_t StartBit, size_t NumBits); + + static bool classof(const TrieNode *TN) { return TN->IsSubtrie; } + + static constexpr size_t sizeToAlloc(unsigned NumBits) { + assert(NumBits < 20 && "Tries should have fewer than ~1M slots"); + unsigned Count = 1u << NumBits; + return totalSizeToAlloc>(Count); + } + +private: + // FIXME: Use a bitset to speed up access: + // + // std::array, NumSlots/64> IsSet; + // + // This will avoid needing to visit sparsely filled slots in + // \a ThreadSafeTrieRawHashMapBase::destroyImpl() when there's a non-trivial + // destructor. + // + // It would also greatly speed up iteration, if we add that some day, and + // allow get() to return one level sooner. + // + // This would be the algorithm for updating IsSet (after updating Slots): + // + // std::atomic &Bits = IsSet[I.High]; + // const uint64_t NewBit = 1ULL << I.Low; + // uint64_t Old = 0; + // while (!Bits.compare_exchange_weak(Old, Old | NewBit)) + // ; + + // For debugging. + unsigned StartBit = 0; + unsigned NumBits = 0; + unsigned Size = 0; + friend class llvm::ThreadSafeTrieRawHashMapBase; + friend class TrailingObjects; + +public: + /// Linked list for ownership of tries. The pointer is owned by TrieSubtrie. + std::atomic Next; +}; +} // end namespace + +std::unique_ptr TrieSubtrie::create(size_t StartBit, + size_t NumBits) { + void *Memory = ::operator new(sizeToAlloc(NumBits)); + TrieSubtrie *S = ::new (Memory) TrieSubtrie(StartBit, NumBits); + return std::unique_ptr(S); +} + +TrieSubtrie::TrieSubtrie(size_t StartBit, size_t NumBits) + : TrieNode(true), StartBit(StartBit), NumBits(NumBits), Size(1u << NumBits), + Next(nullptr) { + for (unsigned I = 0; I < Size; ++I) + new (&get(I)) Slot(nullptr); + + static_assert( + std::is_trivially_destructible>::value, + "Expected no work in destructor for TrieNode"); +} + +// Sink the nodes down sub-trie when the object being inserted collides with +// the index of existing object in the trie. In this case, a new sub-trie needs +// to be allocated to hold existing object. +TrieSubtrie *TrieSubtrie::sink( + size_t I, TrieContent &Content, size_t NumSubtrieBits, size_t NewI, + function_ref)> Saver) { + // Create a new sub-trie that points to the existing object with the new + // index for the next level. + assert(NumSubtrieBits > 0); + std::unique_ptr S = create(StartBit + NumBits, NumSubtrieBits); + + assert(NewI < Size); + S->get(NewI).store(&Content); + + // Using compare_exchange to atomically add back the new sub-trie to the trie + // in the place of the exsiting object. + TrieNode *ExistingNode = &Content; + assert(I < Size); + if (get(I).compare_exchange_strong(ExistingNode, S.get())) + return Saver(std::move(S)); + + // Another thread created a subtrie already. Return it and let "S" be + // destructed. + return cast(ExistingNode); +} + +class ThreadSafeTrieRawHashMapBase::ImplType final + : private TrailingObjects { +public: + static std::unique_ptr create(size_t StartBit, size_t NumBits) { + size_t Size = sizeof(ImplType) + TrieSubtrie::sizeToAlloc(NumBits); + void *Memory = ::operator new(Size); + ImplType *Impl = ::new (Memory) ImplType(StartBit, NumBits); + return std::unique_ptr(Impl); + } + + // Save the Subtrie into the ownship list of the trie structure in a + // thread-safe way. The ownership transfer is done by compare_exchange the + // pointer value inside the unique_ptr. + TrieSubtrie *save(std::unique_ptr S) { + assert(!S->Next && "Expected S to a freshly-constructed leaf"); + + TrieSubtrie *CurrentHead = nullptr; + // Add ownership of "S" to front of the list, so that Root -> S -> + // Root.Next. This works by repeatedly setting S->Next to a candidate value + // of Root.Next (initially nullptr), then setting Root.Next to S once the + // candidate matches reality. + while (!getRoot()->Next.compare_exchange_weak(CurrentHead, S.get())) + S->Next.exchange(CurrentHead); + + // Ownership transferred to subtrie successfully. Release the unique_ptr. + return S.release(); + } + + // Get the root which is the trailing object. + TrieSubtrie *getRoot() { return getTrailingObjects(); } + + static void *operator new(size_t Size) { return ::operator new(Size); } + void operator delete(void *Ptr) { ::operator delete(Ptr); } + + /// FIXME: This should take a function that allocates and constructs the + /// content lazily (taking the hash as a separate parameter), in case of + /// collision. + ThreadSafeAllocator ContentAlloc; + +private: + friend class TrailingObjects; + + ImplType(size_t StartBit, size_t NumBits) { + ::new (getRoot()) TrieSubtrie(StartBit, NumBits); + } +}; + +ThreadSafeTrieRawHashMapBase::ImplType & +ThreadSafeTrieRawHashMapBase::getOrCreateImpl() { + if (ImplType *Impl = ImplPtr.load()) + return *Impl; + + // Create a new ImplType and store it if another thread doesn't do so first. + // If another thread wins this one is destroyed locally. + std::unique_ptr Impl = ImplType::create(0, NumRootBits); + ImplType *ExistingImpl = nullptr; + + // If the ownership transferred succesfully, release unique_ptr and return + // the pointer to the new ImplType. + if (ImplPtr.compare_exchange_strong(ExistingImpl, Impl.get())) + return *Impl.release(); + + // Already created, return the existing ImplType. + return *ExistingImpl; +} + +ThreadSafeTrieRawHashMapBase::PointerBase +ThreadSafeTrieRawHashMapBase::find(ArrayRef Hash) const { + assert(!Hash.empty() && "Uninitialized hash"); + + ImplType *Impl = ImplPtr.load(); + if (!Impl) + return PointerBase(); + + TrieSubtrie *S = Impl->getRoot(); + TrieHashIndexGenerator IndexGen{NumRootBits, NumSubtrieBits, Hash}; + size_t Index = IndexGen.next(); + while (Index != IndexGen.end()) { + // Try to set the content. + TrieNode *Existing = S->get(Index); + if (!Existing) + return PointerBase(S, Index, *IndexGen.StartBit); + + // Check for an exact match. + if (auto *ExistingContent = dyn_cast(Existing)) + return ExistingContent->getHash() == Hash + ? PointerBase(ExistingContent->getValuePointer()) + : PointerBase(S, Index, *IndexGen.StartBit); + + Index = IndexGen.next(); + S = cast(Existing); + } + llvm_unreachable("failed to locate the node after consuming all hash bytes"); +} + +ThreadSafeTrieRawHashMapBase::PointerBase ThreadSafeTrieRawHashMapBase::insert( + PointerBase Hint, ArrayRef Hash, + function_ref Hash)> + Constructor) { + assert(!Hash.empty() && "Uninitialized hash"); + + ImplType &Impl = getOrCreateImpl(); + TrieSubtrie *S = Impl.getRoot(); + TrieHashIndexGenerator IndexGen{NumRootBits, NumSubtrieBits, Hash}; + size_t Index; + if (Hint.isHint()) { + S = static_cast(Hint.P); + Index = IndexGen.hint(Hint.I, Hint.B); + } else { + Index = IndexGen.next(); + } + + while (Index != IndexGen.end()) { + // Load the node from the slot, allocating and calling the constructor if + // the slot is empty. + bool Generated = false; + TrieNode &Existing = S->get(Index).loadOrGenerate([&]() { + Generated = true; + + // Construct the value itself at the tail. + uint8_t *Memory = reinterpret_cast( + Impl.ContentAlloc.Allocate(ContentAllocSize, ContentAllocAlign)); + const uint8_t *HashStorage = Constructor(Memory + ContentOffset, Hash); + + // Construct the TrieContent header, passing in the offset to the hash. + TrieContent *Content = ::new (Memory) + TrieContent(ContentOffset, Hash.size(), HashStorage - Memory); + assert(Hash == Content->getHash() && "Hash not properly initialized"); + return Content; + }); + // If we just generated it, return it! + if (Generated) + return PointerBase(cast(Existing).getValuePointer()); + + if (auto *ST = dyn_cast(&Existing)) { + S = ST; + Index = IndexGen.next(); + continue; + } + + // Return the existing content if it's an exact match! + auto &ExistingContent = cast(Existing); + if (ExistingContent.getHash() == Hash) + return PointerBase(ExistingContent.getValuePointer()); + + // Sink the existing content as long as the indexes match. + size_t NextIndex = IndexGen.next(); + while (NextIndex != IndexGen.end()) { + size_t NewIndexForExistingContent = + IndexGen.getCollidingBits(ExistingContent.getHash()); + S = S->sink(Index, ExistingContent, IndexGen.getNumBits(), + NewIndexForExistingContent, + [&Impl](std::unique_ptr S) { + return Impl.save(std::move(S)); + }); + Index = NextIndex; + + // Found the difference. + if (NextIndex != NewIndexForExistingContent) + break; + + NextIndex = IndexGen.next(); + } + } + llvm_unreachable("failed to insert the node after consuming all hash bytes"); +} + +ThreadSafeTrieRawHashMapBase::ThreadSafeTrieRawHashMapBase( + size_t ContentAllocSize, size_t ContentAllocAlign, size_t ContentOffset, + std::optional NumRootBits, std::optional NumSubtrieBits) + : ContentAllocSize(ContentAllocSize), ContentAllocAlign(ContentAllocAlign), + ContentOffset(ContentOffset), + NumRootBits(NumRootBits ? *NumRootBits : DefaultNumRootBits), + NumSubtrieBits(NumSubtrieBits ? *NumSubtrieBits : DefaultNumSubtrieBits), + ImplPtr(nullptr) { + // Assertion checks for reasonable configuration. The settings below are not + // hard limits on most platforms, but a reasonable configuration should fall + // within those limits. + assert((!NumRootBits || *NumRootBits < 20) && + "Root should have fewer than ~1M slots"); + assert((!NumSubtrieBits || *NumSubtrieBits < 10) && + "Subtries should have fewer than ~1K slots"); +} + +ThreadSafeTrieRawHashMapBase::ThreadSafeTrieRawHashMapBase( + ThreadSafeTrieRawHashMapBase &&RHS) + : ContentAllocSize(RHS.ContentAllocSize), + ContentAllocAlign(RHS.ContentAllocAlign), + ContentOffset(RHS.ContentOffset), NumRootBits(RHS.NumRootBits), + NumSubtrieBits(RHS.NumSubtrieBits) { + // Steal the root from RHS. + ImplPtr = RHS.ImplPtr.exchange(nullptr); +} + +ThreadSafeTrieRawHashMapBase::~ThreadSafeTrieRawHashMapBase() { + assert(!ImplPtr.load() && "Expected subclass to call destroyImpl()"); +} + +void ThreadSafeTrieRawHashMapBase::destroyImpl( + function_ref Destructor) { + std::unique_ptr Impl(ImplPtr.exchange(nullptr)); + if (!Impl) + return; + + // Destroy content nodes throughout trie. Avoid destroying any subtries since + // we need TrieNode::classof() to find the content nodes. + // + // FIXME: Once we have bitsets (see FIXME in TrieSubtrie class), use them + // facilitate sparse iteration here. + if (Destructor) + for (TrieSubtrie *Trie = Impl->getRoot(); Trie; Trie = Trie->Next.load()) + for (unsigned I = 0; I < Trie->size(); ++I) + if (auto *Content = dyn_cast_or_null(Trie->load(I))) + Destructor(Content->getValuePointer()); + + // Destroy the subtries. Incidentally, this destroys them in the reverse order + // of saving. + TrieSubtrie *Trie = Impl->getRoot()->Next; + while (Trie) { + TrieSubtrie *Next = Trie->Next.exchange(nullptr); + delete Trie; + Trie = Next; + } +} + +ThreadSafeTrieRawHashMapBase::PointerBase +ThreadSafeTrieRawHashMapBase::getRoot() const { + ImplType *Impl = ImplPtr.load(); + if (!Impl) + return PointerBase(); + return PointerBase(Impl->getRoot()); +} + +unsigned ThreadSafeTrieRawHashMapBase::getStartBit( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return 0; + if (auto *S = dyn_cast((TrieNode *)P.P)) + return S->StartBit; + return 0; +} + +unsigned ThreadSafeTrieRawHashMapBase::getNumBits( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return 0; + if (auto *S = dyn_cast((TrieNode *)P.P)) + return S->NumBits; + return 0; +} + +unsigned ThreadSafeTrieRawHashMapBase::getNumSlotUsed( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return 0; + auto *S = dyn_cast((TrieNode *)P.P); + if (!S) + return 0; + unsigned Num = 0; + for (unsigned I = 0, E = S->size(); I < E; ++I) + if (S->load(I)) + ++Num; + return Num; +} + +std::string ThreadSafeTrieRawHashMapBase::getTriePrefixAsString( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return ""; + + auto *S = dyn_cast((TrieNode *)P.P); + if (!S || !S->IsSubtrie) + return ""; + + // Find a TrieContent node which has hash stored. Depth search following the + // first used slot until a TrieContent node is found. + TrieSubtrie *Current = S; + TrieContent *Node = nullptr; + while (Current) { + TrieSubtrie *Next = nullptr; + // Find first used slot in the trie. + for (unsigned I = 0, E = Current->size(); I < E; ++I) { + auto *S = Current->load(I); + if (!S) + continue; + + if (auto *Content = dyn_cast(S)) + Node = Content; + else if (auto *Sub = dyn_cast(S)) + Next = Sub; + break; + } + + // Found the node. + if (Node) + break; + + // Continue to the next level if the node is not found. + Current = Next; + } + + assert(Node && "malformed trie, cannot find TrieContent on leaf node"); + // The prefix for the current trie is the first `StartBit` of the content + // stored underneath this subtrie. + std::string Str; + raw_string_ostream SS(Str); + + unsigned StartFullBytes = (S->StartBit + 1) / 8 - 1; + SS << toHex(toStringRef(Node->getHash()).take_front(StartFullBytes), + /*LowerCase=*/true); + + // For the part of the prefix that doesn't fill a byte, print raw bit values. + std::string Bits; + for (unsigned I = StartFullBytes * 8, E = S->StartBit; I < E; ++I) { + unsigned Index = I / 8; + unsigned Offset = 7 - I % 8; + Bits.push_back('0' + ((Node->getHash()[Index] >> Offset) & 1)); + } + + if (!Bits.empty()) + SS << "[" << Bits << "]"; + + return SS.str(); +} + +unsigned ThreadSafeTrieRawHashMapBase::getNumTries() const { + ImplType *Impl = ImplPtr.load(); + if (!Impl) + return 0; + unsigned Num = 0; + for (TrieSubtrie *Trie = Impl->getRoot(); Trie; Trie = Trie->Next.load()) + ++Num; + return Num; +} + +ThreadSafeTrieRawHashMapBase::PointerBase +ThreadSafeTrieRawHashMapBase::getNextTrie( + ThreadSafeTrieRawHashMapBase::PointerBase P) const { + assert(!P.isHint() && "Not a valid trie"); + if (!P.P) + return PointerBase(); + auto *S = dyn_cast((TrieNode *)P.P); + if (!S) + return PointerBase(); + if (auto *E = S->Next.load()) + return PointerBase(E); + return PointerBase(); +} diff --git a/llvm/lib/TableGen/TGLexer.cpp b/llvm/lib/TableGen/TGLexer.cpp index 8fe7f69ecf8e5930f308a483ef153dd1e7fba396..1e93b2c160ba58e6bc5ccf603e57b3cf50dd5280 100644 --- a/llvm/lib/TableGen/TGLexer.cpp +++ b/llvm/lib/TableGen/TGLexer.cpp @@ -89,7 +89,7 @@ TGLexer::TGLexer(SourceMgr &SM, ArrayRef Macros) : SrcMgr(SM) { for (StringRef MacroName : Macros) { const char *End = lexMacroName(MacroName); if (End != MacroName.end()) - PrintFatalError("Invalid macro name `" + MacroName + + PrintFatalError("invalid macro name `" + MacroName + "` specified on command line"); DefinedMacros.insert(MacroName); @@ -188,7 +188,7 @@ tgtok::TokKind TGLexer::LexToken(bool FileOrLineStart) { return LexIdentifier(); // Unknown character, emit an error. - return ReturnError(TokStart, "Unexpected character"); + return ReturnError(TokStart, "unexpected character"); case EOF: // Lex next token, if we just left an include file. // Note that leaving an include file means that the next @@ -231,7 +231,7 @@ tgtok::TokKind TGLexer::LexToken(bool FileOrLineStart) { ++CurPtr; // Eat third dot. return tgtok::dotdotdot; } - return ReturnError(TokStart, "Invalid '..' punctuation"); + return ReturnError(TokStart, "invalid '..' punctuation"); } return tgtok::dot; @@ -255,7 +255,7 @@ tgtok::TokKind TGLexer::LexToken(bool FileOrLineStart) { if (SkipCComment()) return tgtok::Error; } else // Otherwise, this is an error. - return ReturnError(TokStart, "Unexpected character"); + return ReturnError(TokStart, "unexpected character"); return LexToken(FileOrLineStart); case '-': case '+': case '0': case '1': case '2': case '3': case '4': case '5': case '6': @@ -313,10 +313,10 @@ tgtok::TokKind TGLexer::LexString() { while (*CurPtr != '"') { // If we hit the end of the buffer, report an error. if (*CurPtr == 0 && CurPtr == CurBuf.end()) - return ReturnError(StrStart, "End of file in string literal"); + return ReturnError(StrStart, "end of file in string literal"); if (*CurPtr == '\n' || *CurPtr == '\r') - return ReturnError(StrStart, "End of line in string literal"); + return ReturnError(StrStart, "end of line in string literal"); if (*CurPtr != '\\') { CurStrVal += *CurPtr++; @@ -346,7 +346,7 @@ tgtok::TokKind TGLexer::LexString() { // If we hit the end of the buffer, report an error. case '\0': if (CurPtr == CurBuf.end()) - return ReturnError(StrStart, "End of file in string literal"); + return ReturnError(StrStart, "end of file in string literal"); [[fallthrough]]; default: return ReturnError(CurPtr, "invalid escape in string literal"); @@ -359,7 +359,7 @@ tgtok::TokKind TGLexer::LexString() { tgtok::TokKind TGLexer::LexVarName() { if (!isValidIDChar(CurPtr[0], /*First=*/true)) - return ReturnError(TokStart, "Invalid variable name"); + return ReturnError(TokStart, "invalid variable name"); // Otherwise, we're ok, consume the rest of the characters. const char *VarNameStart = CurPtr++; @@ -433,7 +433,7 @@ bool TGLexer::LexInclude() { tgtok::TokKind Tok = LexToken(); if (Tok == tgtok::Error) return true; if (Tok != tgtok::StrVal) { - PrintError(getLoc(), "Expected filename after include"); + PrintError(getLoc(), "expected filename after include"); return true; } @@ -444,7 +444,7 @@ bool TGLexer::LexInclude() { CurBuffer = SrcMgr.AddIncludeFile(Filename, SMLoc::getFromPointer(CurPtr), IncludedFile); if (!CurBuffer) { - PrintError(getLoc(), "Could not find include file '" + Filename + "'"); + PrintError(getLoc(), "could not find include file '" + Filename + "'"); return true; } @@ -476,7 +476,7 @@ bool TGLexer::SkipCComment() { int CurChar = getNextChar(); switch (CurChar) { case EOF: - PrintError(TokStart, "Unterminated comment!"); + PrintError(TokStart, "unterminated comment"); return true; case '*': // End of the comment? @@ -543,7 +543,7 @@ tgtok::TokKind TGLexer::LexNumber() { // Requires at least one digit. if (CurPtr == NumStart) - return ReturnError(TokStart, "Invalid number"); + return ReturnError(TokStart, "invalid number"); errno = 0; if (IsMinus) @@ -552,9 +552,9 @@ tgtok::TokKind TGLexer::LexNumber() { CurIntVal = strtoull(NumStart, nullptr, Base); if (errno == EINVAL) - return ReturnError(TokStart, "Invalid number"); + return ReturnError(TokStart, "invalid number"); if (errno == ERANGE) - return ReturnError(TokStart, "Number out of range"); + return ReturnError(TokStart, "number out of range"); return Base == 2 ? tgtok::BinaryIntVal : tgtok::IntVal; } @@ -580,13 +580,13 @@ tgtok::TokKind TGLexer::LexBracket() { } } - return ReturnError(CodeStart - 2, "Unterminated code block"); + return ReturnError(CodeStart - 2, "unterminated code block"); } /// LexExclaim - Lex '!' and '![a-zA-Z]+'. tgtok::TokKind TGLexer::LexExclaim() { if (!isAlpha(*CurPtr)) - return ReturnError(CurPtr - 1, "Invalid \"!operator\""); + return ReturnError(CurPtr - 1, "invalid \"!operator\""); const char *Start = CurPtr++; while (isAlpha(*CurPtr)) @@ -648,7 +648,8 @@ tgtok::TokKind TGLexer::LexExclaim() { .Case("repr", tgtok::XRepr) .Default(tgtok::Error); - return Kind != tgtok::Error ? Kind : ReturnError(Start-1, "Unknown operator"); + return Kind != tgtok::Error ? Kind + : ReturnError(Start - 1, "unknown operator"); } bool TGLexer::prepExitInclude(bool IncludeStackMustBeEmpty) { @@ -662,17 +663,17 @@ bool TGLexer::prepExitInclude(bool IncludeStackMustBeEmpty) { // Pop the preprocessing controls from the include stack. if (PrepIncludeStack.empty()) { - PrintFatalError("Preprocessor include stack is empty"); + PrintFatalError("preprocessor include stack is empty"); } PrepIncludeStack.pop_back(); if (IncludeStackMustBeEmpty) { if (!PrepIncludeStack.empty()) - PrintFatalError("Preprocessor include stack is not empty"); + PrintFatalError("preprocessor include stack is not empty"); } else { if (PrepIncludeStack.empty()) - PrintFatalError("Preprocessor include stack is empty"); + PrintFatalError("preprocessor include stack is empty"); } return true; @@ -732,7 +733,7 @@ bool TGLexer::prepEatPreprocessorDirective(tgtok::TokKind Kind) { return true; } - PrintFatalError("Unsupported preprocessing token in " + PrintFatalError("unsupported preprocessing token in " "prepEatPreprocessorDirective()"); return false; } @@ -748,7 +749,7 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, StringRef MacroName = prepLexMacroName(); StringRef IfTokName = Kind == tgtok::Ifdef ? "#ifdef" : "#ifndef"; if (MacroName.empty()) - return ReturnError(TokStart, "Expected macro name after " + IfTokName); + return ReturnError(TokStart, "expected macro name after " + IfTokName); bool MacroIsDefined = DefinedMacros.count(MacroName) != 0; @@ -763,7 +764,7 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, {tgtok::Ifdef, MacroIsDefined, SMLoc::getFromPointer(TokStart)}); if (!prepSkipDirectiveEnd()) - return ReturnError(CurPtr, "Only comments are supported after " + + return ReturnError(CurPtr, "only comments are supported after " + IfTokName + " NAME"); // If we were not processing tokens before this #ifdef, @@ -794,7 +795,7 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, if (IfdefEntry.Kind != tgtok::Ifdef) { PrintError(TokStart, "double #else"); - return ReturnError(IfdefEntry.SrcPos, "Previous #else is here"); + return ReturnError(IfdefEntry.SrcPos, "previous #else is here"); } // Replace the corresponding #ifdef's control with its negation @@ -804,7 +805,7 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, {Kind, !IfdefEntry.IsDefined, SMLoc::getFromPointer(TokStart)}); if (!prepSkipDirectiveEnd()) - return ReturnError(CurPtr, "Only comments are supported after #else"); + return ReturnError(CurPtr, "only comments are supported after #else"); // If we were processing tokens before this #else, // we have to start skipping lines until the matching #endif. @@ -827,12 +828,12 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, if (IfdefOrElseEntry.Kind != tgtok::Ifdef && IfdefOrElseEntry.Kind != tgtok::Else) { - PrintFatalError("Invalid preprocessor control on the stack"); + PrintFatalError("invalid preprocessor control on the stack"); return tgtok::Error; } if (!prepSkipDirectiveEnd()) - return ReturnError(CurPtr, "Only comments are supported after #endif"); + return ReturnError(CurPtr, "only comments are supported after #endif"); PrepIncludeStack.back()->pop_back(); @@ -847,15 +848,15 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, } else if (Kind == tgtok::Define) { StringRef MacroName = prepLexMacroName(); if (MacroName.empty()) - return ReturnError(TokStart, "Expected macro name after #define"); + return ReturnError(TokStart, "expected macro name after #define"); if (!DefinedMacros.insert(MacroName).second) PrintWarning(getLoc(), - "Duplicate definition of macro: " + Twine(MacroName)); + "duplicate definition of macro: " + Twine(MacroName)); if (!prepSkipDirectiveEnd()) return ReturnError(CurPtr, - "Only comments are supported after #define NAME"); + "only comments are supported after #define NAME"); if (!ReturnNextLiveToken) { PrintFatalError("#define must be ignored during the lines skipping"); @@ -865,13 +866,13 @@ tgtok::TokKind TGLexer::lexPreprocessor(tgtok::TokKind Kind, return LexToken(); } - PrintFatalError("Preprocessing directive is not supported"); + PrintFatalError("preprocessing directive is not supported"); return tgtok::Error; } bool TGLexer::prepSkipRegion(bool MustNeverBeFalse) { if (!MustNeverBeFalse) - PrintFatalError("Invalid recursion."); + PrintFatalError("invalid recursion."); do { // Skip all symbols to the line end. @@ -917,7 +918,7 @@ bool TGLexer::prepSkipRegion(bool MustNeverBeFalse) { // due to #else or #endif. if (prepIsProcessingEnabled()) { if (Kind != tgtok::Else && Kind != tgtok::Endif) { - PrintFatalError("Tokens processing was enabled by an unexpected " + PrintFatalError("tokens processing was enabled by an unexpected " "preprocessing directive"); return false; } @@ -1032,7 +1033,7 @@ bool TGLexer::prepSkipDirectiveEnd() { return false; } else { TokStart = CurPtr; - PrintError(CurPtr, "Unexpected character"); + PrintError(CurPtr, "unexpected character"); return false; } @@ -1067,8 +1068,8 @@ void TGLexer::prepReportPreprocessorStackError() { "empty control stack"); auto &PrepControl = PrepIncludeStack.back()->back(); - PrintError(CurBuf.end(), "Reached EOF without matching #endif"); - PrintError(PrepControl.SrcPos, "The latest preprocessor control is here"); + PrintError(CurBuf.end(), "reached EOF without matching #endif"); + PrintError(PrepControl.SrcPos, "the latest preprocessor control is here"); TokStart = CurPtr; } diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 9bb508b783c36a00ead83689381a8b5b22052f30..6854cccaafa1d78750141df87e8370405cb80049 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -73,7 +73,8 @@ def SVEUnsupported : AArch64Unsupported { SVE2Unsupported.F); } -let F = [HasSME2p2, HasSVE2p2orSME2p2] in +let F = [HasSME2p2, HasSVE2p2orSME2p2, HasNonStreamingSVEorSME2p2, + HasNonStreamingSVE2p2orSME2p2] in def SME2p2Unsupported : AArch64Unsupported; def SME2p1Unsupported : AArch64Unsupported { diff --git a/llvm/lib/Target/AArch64/AArch64FMV.td b/llvm/lib/Target/AArch64/AArch64FMV.td index 7146b041fe5d150db43626d1b700f01c7f69d0c9..12d841445b80f750ce44de8f99062146a0540576 100644 --- a/llvm/lib/Target/AArch64/AArch64FMV.td +++ b/llvm/lib/Target/AArch64/AArch64FMV.td @@ -81,9 +81,6 @@ def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>; def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>; def : FMVExtension<"ssbs", "FEAT_SSBS2", "+ssbs", 490>; def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>; -def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>; -def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>; -def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>; def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>; def : FMVExtension<"sve2-aes", "FEAT_SVE_PMULL128", "+sve2,+sve,+aes,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>; def : FMVExtension<"sve2-bitperm", "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 32ba2866ac818075cda8af79dd1fe112b5c9ff8a..e8c02c09879747675cc29e83f13c9460d239f628 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -2536,6 +2536,11 @@ unsigned AArch64TargetLowering::ComputeNumSignBitsForTargetNode( case AArch64ISD::FCMLTz: // Compares return either 0 or all-ones return VTBits; + case AArch64ISD::VASHR: { + unsigned Tmp = + DAG.ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1); + return std::min(Tmp + Op.getConstantOperandVal(1), VTBits); + } } return 1; @@ -7922,10 +7927,8 @@ SDValue AArch64TargetLowering::LowerFormalArguments( APInt(Ptr.getValueSizeInBits().getFixedValue(), PartSize), DL, Ptr.getValueType()); } - SDNodeFlags Flags; - Flags.setNoUnsignedWrap(true); Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, - BytesIncrement, Flags); + BytesIncrement, SDNodeFlags::NoUnsignedWrap); ExtraArgLocs++; i++; } @@ -8981,12 +8984,9 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI, APInt(Ptr.getValueSizeInBits().getFixedValue(), PartSize), DL, Ptr.getValueType()); } - SDNodeFlags Flags; - Flags.setNoUnsignedWrap(true); - MPI = MachinePointerInfo(MPI.getAddrSpace()); Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, - BytesIncrement, Flags); + BytesIncrement, SDNodeFlags::NoUnsignedWrap); ExtraArgLocs++; i++; } @@ -11772,8 +11772,7 @@ SDValue AArch64TargetLowering::getSqrtEstimate(SDValue Operand, SDLoc DL(Operand); EVT VT = Operand.getValueType(); - SDNodeFlags Flags; - Flags.setAllowReassociation(true); + SDNodeFlags Flags = SDNodeFlags::AllowReassociation; // Newton reciprocal square root iteration: E * 0.5 * (3 - X * E^2) // AArch64 reciprocal square root iteration instruction: 0.5 * (3 - M * N) @@ -11802,8 +11801,7 @@ SDValue AArch64TargetLowering::getRecipEstimate(SDValue Operand, SDLoc DL(Operand); EVT VT = Operand.getValueType(); - SDNodeFlags Flags; - Flags.setAllowReassociation(true); + SDNodeFlags Flags = SDNodeFlags::AllowReassociation; // Newton reciprocal iteration: E * (2 - X * E) // AArch64 reciprocal iteration instruction: (2 - M * N) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 6194de2d56b63049ff42191b0279a980a51f87a9..457e918728ae27a1e2949e859c5719215ad85f25 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -244,7 +244,7 @@ def HasSVEorSME : Predicate<"Subtarget->hasSVE() || (Subtarget->isStreaming() && Subtarget->hasSME())">, AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME), "sve or sme">; -def HasSVEorSME2p2 +def HasNonStreamingSVEorSME2p2 : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||" "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">, AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2), @@ -281,6 +281,11 @@ def HasSMEF16F16orSMEF8F16 : Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">, AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16), "sme-f16f16 or sme-f8f16">; +def HasNonStreamingSVE2p2orSME2p2 + : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2p2()) ||" + "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">, + AssemblerPredicateWithAll<(any_of FeatureSVE2p2, FeatureSME2p2), + "sme2p2 or sve2p2">; // A subset of NEON instructions are legal in Streaming SVE execution mode, // so don't need the additional check for 'isNeonAvailable'. diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td index 8516ab2c7dd71ce6614068ce1639382c5ed8a5df..4117d74d10c1e7db10e9473d10896c612981e5a6 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -19,18 +19,24 @@ class AArch64Reg enc, string n, list subregs = [], } let Namespace = "AArch64" in { + // SubRegIndexes for GPR registers def sub_32 : SubRegIndex<32>; + def sube64 : SubRegIndex<64>; + def subo64 : SubRegIndex<64>; + def sube32 : SubRegIndex<32>; + def subo32 : SubRegIndex<32>; + // SubRegIndexes for FPR/Vector registers def bsub : SubRegIndex<8>; def hsub : SubRegIndex<16>; def ssub : SubRegIndex<32>; def dsub : SubRegIndex<64>; - def sube32 : SubRegIndex<32>; - def subo32 : SubRegIndex<32>; - def sube64 : SubRegIndex<64>; - def subo64 : SubRegIndex<64>; - // SVE - def zsub : SubRegIndex<128>; + def zsub : SubRegIndex<128>; + // Note: Code depends on these having consecutive numbers + def zsub0 : SubRegIndex<128, -1>; + def zsub1 : SubRegIndex<128, -1>; + def zsub2 : SubRegIndex<128, -1>; + def zsub3 : SubRegIndex<128, -1>; // Note: Code depends on these having consecutive numbers def dsub0 : SubRegIndex<64>; def dsub1 : SubRegIndex<64>; @@ -41,7 +47,8 @@ let Namespace = "AArch64" in { def qsub1 : SubRegIndex<128>; def qsub2 : SubRegIndex<128>; def qsub3 : SubRegIndex<128>; - // Note: Code depends on these having consecutive numbers + + // SubRegIndexes for SME Matrix tiles def zasubb : SubRegIndex<2048>; // (16 x 16)/1 bytes = 2048 bits def zasubh0 : SubRegIndex<1024>; // (16 x 16)/2 bytes = 1024 bits def zasubh1 : SubRegIndex<1024>; // (16 x 16)/2 bytes = 1024 bits @@ -52,7 +59,11 @@ let Namespace = "AArch64" in { def zasubq0 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits def zasubq1 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits - def psub : SubRegIndex<16>; + // SubRegIndexes for SVE Predicates + def psub : SubRegIndex<16>; + // Note: Code depends on these having consecutive numbers + def psub0 : SubRegIndex<16, -1>; + def psub1 : SubRegIndex<16, -1>; } let Namespace = "AArch64" in { @@ -1026,11 +1037,6 @@ def PNR16_p8to15 : PNRP8to15RegOp<"h", PNRAsmOp16_p8to15, 16, PNR_p8to15>; def PNR32_p8to15 : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PNR_p8to15>; def PNR64_p8to15 : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PNR_p8to15>; -let Namespace = "AArch64" in { - def psub0 : SubRegIndex<16, -1>; - def psub1 : SubRegIndex<16, -1>; -} - class PPRorPNRClass : RegisterClass< "AArch64", [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1, aarch64svcount ], 16, @@ -1123,8 +1129,7 @@ let EncoderMethod = "EncodeRegMul_MinMax<2, 0, 14>", } // end let EncoderMethod/DecoderMethod -//****************************************************************************** - +//===----------------------------------------------------------------------===// // SVE vector register classes class ZPRClass : RegisterClass<"AArch64", [nxv16i8, nxv8i16, nxv4i32, nxv2i64, @@ -1245,13 +1250,6 @@ def FPR32asZPR : FPRasZPROperand<32>; def FPR64asZPR : FPRasZPROperand<64>; def FPR128asZPR : FPRasZPROperand<128>; -let Namespace = "AArch64" in { - def zsub0 : SubRegIndex<128, -1>; - def zsub1 : SubRegIndex<128, -1>; - def zsub2 : SubRegIndex<128, -1>; - def zsub3 : SubRegIndex<128, -1>; -} - // Pairs, triples, and quads of SVE vector registers. def ZSeqPairs : RegisterTuples<[zsub0, zsub1], [(rotl ZPR, 0), (rotl ZPR, 1)]>; def ZSeqTriples : RegisterTuples<[zsub0, zsub1, zsub2], [(rotl ZPR, 0), (rotl ZPR, 1), (rotl ZPR, 2)]>; diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index ae40911cc62a8776cf514cef9b3f86458020347d..7357aa3c1f0d55652c99b131ccf8eb2748a77d5d 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -1017,6 +1017,12 @@ let Predicates = [HasSME2p2] in { defm FMUL_2Z2Z : sme2_multi2_fmul_mm< "fmul">; defm FMUL_4ZZ : sme2_multi4_fmul_sm<"fmul">; defm FMUL_4Z4Z : sme2_multi4_fmul_mm< "fmul">; + + defm FMOP4A : sme2_fmop4as_fp32_non_widening<0, "fmop4a">; + defm FMOP4S : sme2_fmop4as_fp32_non_widening<1, "fmop4s">; + + defm FMOP4A : sme2_fmop4as_fp16_fp32_widening<0, "fmop4a">; + defm FMOP4S : sme2_fmop4as_fp16_fp32_widening<1, "fmop4s">; } // [HasSME2p2] let Predicates = [HasSME2p2, HasSMEB16B16] in { @@ -1041,3 +1047,19 @@ let Predicates = [HasSME2, HasSVEBFSCALE] in { defm BFMUL : sme2_bfmul_single<"bfmul">; defm BFMUL : sme2_bfmul_multi<"bfmul">; } //[HasSME2, HasSVEBFSCALE] + +let Uses = [FPMR, FPCR] in { +let Predicates = [HasSME2p2, HasSMEF8F32] in { + defm FMOP4A : sme2_fmop4a_fp8_fp32_4way<"fmop4a">; +} +} + +let Predicates = [HasSME2p2, HasSMEB16B16] in { + defm BFMOP4A : sme2_bfmop4as_non_widening<0, "bfmop4a">; + defm BFMOP4S : sme2_bfmop4as_non_widening<1, "bfmop4s">; +} + +let Predicates = [HasSME2p2, HasSMEF64F64] in { + defm FMOP4A : sme2_fmop4as_fp64_non_widening<0, "fmop4a">; + defm FMOP4S : sme2_fmop4as_fp64_non_widening<1, "fmop4s">; +} diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 4f101d0d46b7afa039e525deddc4c0106a1b2075..d6662d15617fabf19cf13bec71d2794f059085d3 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -928,9 +928,10 @@ let Predicates = [HasSVEorSME] in { defm SPLICE_ZPZ : sve_int_perm_splice<"splice", AArch64splice>; } // End HasSVEorSME -let Predicates = [HasSVE] in { - defm COMPACT_ZPZ : sve_int_perm_compact<"compact", int_aarch64_sve_compact>; -} // End HasSVE +// COMPACT - word and doubleword +let Predicates = [HasNonStreamingSVEorSME2p2] in { + defm COMPACT_ZPZ : sve_int_perm_compact_sd<"compact", int_aarch64_sve_compact>; +} let Predicates = [HasSVEorSME] in { defm INSR_ZR : sve_int_perm_insrs<"insr", AArch64insr>; @@ -2128,7 +2129,7 @@ let Predicates = [HasSVEorSME] in { defm CNTH_XPiI : sve_int_count<0b010, "cnth", int_aarch64_sve_cnth>; defm CNTW_XPiI : sve_int_count<0b100, "cntw", int_aarch64_sve_cntw>; defm CNTD_XPiI : sve_int_count<0b110, "cntd", int_aarch64_sve_cntd>; - defm CNTP_XPP : sve_int_pcount_pred<0b0000, "cntp", int_aarch64_sve_cntp>; + defm CNTP_XPP : sve_int_pcount_pred<0b000, "cntp", int_aarch64_sve_cntp>; def : Pat<(i64 (AArch64CttzElts nxv16i1:$Op1)), (CNTP_XPP_B (BRKB_PPzP (PTRUE_B 31), PPR:$Op1), @@ -3850,7 +3851,7 @@ let Predicates = [HasSVE2] in { let Predicates = [HasSVE2orSME] in { // SVE2 vector splice (constructive) - defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">; + defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice", AArch64splice>; } // End HasSVE2orSME let Predicates = [HasSVE2] in { @@ -4225,15 +4226,22 @@ defm TBLQ_ZZZ : sve2p1_tblq<"tblq", int_aarch64_sve_tblq>; // SME2.2 or SVE2.2 instructions //===----------------------------------------------------------------------===// let Predicates = [HasSVE2p2orSME2p2] in { + // SVE Floating-point convert precision, zeroing predicate + defm FCVT_ZPzZ : sve_fp_z2op_p_zd_b_0<"fcvt">; + // SVE2p2 floating-point convert precision down (placing odd), zeroing predicate defm FCVTNT_ZPzZ : sve_fp_fcvtntz<"fcvtnt">; def FCVTXNT_ZPzZ_DtoS : sve_fp_fcvt2z<0b0010, "fcvtxnt", ZPR32, ZPR64>; + // Placing even + def FCVTX_ZPzZ_DtoS : sve_fp_z2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32>; // SVE2p2 floating-point convert precision up, zeroing predicate defm FCVTLT_ZPzZ : sve_fp_fcvtltz<"fcvtlt">; // SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate def BFCVTNT_ZPzZ : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>; + // Placing corresponding + def BFCVT_ZPzZ_StoH : sve_fp_z2op_p_zd<0b1001010, "bfcvt", ZPR32, ZPR16>; // Floating-point convert to integer, zeroing predicate defm FCVTZS_ZPzZ : sve_fp_z2op_p_zd_d<0b0, "fcvtzs">; @@ -4296,8 +4304,21 @@ let Predicates = [HasSVE2p2orSME2p2] in { def SXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1000, "sxtw", ZPR64>; def UXTW_ZPzZ_D : sve_int_un_pred_arit_z<0b11, 0b1010, "uxtw", ZPR64>; + // SVE predicate count + defm FIRSTP_XPP : sve_int_pcount_pred_tmp<0b001, "firstp">; + defm LASTP_XPP : sve_int_pcount_pred_tmp<0b010, "lastp">; } // End HasSME2p2orSVE2p2 +//===----------------------------------------------------------------------===// +// SME2.2 or SVE2.2 instructions - Legal in streaming mode iff target has SME2p2 +//===----------------------------------------------------------------------===// +let Predicates = [HasNonStreamingSVE2p2orSME2p2] in { + // SVE2 EXPAND + defm EXPAND_ZPZ : sve2_int_perm_expand<"expand">; + // SVE COMPACT - byte and halfword + defm COMPACT_ZPZ : sve_int_perm_compact_bh<"compact">; +} + //===----------------------------------------------------------------------===// // SVE2 FP8 instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 7fb2a961e0313d3c7f6ff071eab0c251ac6fe6b7..736d57e6ae2fd985ce434c5a135ef06e2ea98455 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -86,6 +86,13 @@ static cl::alias AArch64StreamingStackHazardSize( cl::desc("alias for -aarch64-streaming-hazard-size"), cl::aliasopt(AArch64StreamingHazardSize)); +// Subreg liveness tracking is disabled by default for now until all issues +// are ironed out. This option allows the feature to be used in tests. +static cl::opt + EnableSubregLivenessTracking("aarch64-enable-subreg-liveness-tracking", + cl::init(false), cl::Hidden, + cl::desc("Enable subreg liveness tracking")); + unsigned AArch64Subtarget::getVectorInsertExtractBaseCost() const { if (OverrideVectorInsertExtractBaseCost.getNumOccurrences() > 0) return OverrideVectorInsertExtractBaseCost; @@ -380,6 +387,8 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU, ReserveXRegisterForRA.set(29); AddressCheckPSV.reset(new AddressCheckPseudoSourceValue(TM)); + + EnableSubregLiveness = EnableSubregLivenessTracking.getValue(); } const CallLowering *AArch64Subtarget::getCallLowering() const { diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 50adb7cbf69a87269074694e5162069913299cf5..f3dcce3f3994ba4f4dadb99234004a4686c015e3 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -90,6 +90,8 @@ protected: unsigned VScaleForTuning = 2; TailFoldingOpts DefaultSVETFOpts = TailFoldingOpts::Disabled; + bool EnableSubregLiveness; + /// TargetTriple - What processor and OS we're targeting. Triple TargetTriple; @@ -153,6 +155,7 @@ public: const Triple &getTargetTriple() const { return TargetTriple; } bool enableMachineScheduler() const override { return true; } bool enablePostRAScheduler() const override { return usePostRAScheduler(); } + bool enableSubRegLiveness() const override { return EnableSubregLiveness; } bool enableMachinePipeliner() const override; bool useDFAforSMS() const override { return false; } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp index 762a7af8c3ddb3d02f7d4c23ed81e964a29035b6..2ee2ee5a6fa500f50262871c0072fdcd3a2fde57 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -59,12 +59,12 @@ bool AArch64InstPrinter::applyTargetSpecificCLOption(StringRef Opt) { return false; } -void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << getRegisterName(Reg); } void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg, - unsigned AltIdx) const { + unsigned AltIdx) { markup(OS, Markup::Register) << getRegisterName(Reg, AltIdx); } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h index e7b62b3203681bcb9e24137110e3ef28a3e2570b..9cf2674ae943aa7a2616588a4a9d8b30f5c625f2 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h @@ -29,8 +29,8 @@ public: void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &OS, MCRegister Reg) const override; - void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx) const; + void printRegName(raw_ostream &OS, MCRegister Reg) override; + void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx); // Autogenerated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 330c540ffde443288ec8d7ff6857da6e0d21567e..867901ac5d90358c7ea441ffa4b0a441404b2061 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -5382,3 +5382,186 @@ multiclass sme2_fmop4as_fp16_non_widening { // Multiple vectors def _M2Z2Z_H : sme2_fp16_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>; } + +class sme2_fp8_fp32_quarter_tile_outer_product + : I<(outs TileOp32:$ZAda), + (ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, Sched<[]> { + bits<2> ZAda; + bits<3> Zn; + bits<3> Zm; + + let Inst{31-21} = 0b10000000001; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5-2} = 0b0000; + let Inst{1-0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme2_fmop4a_fp8_fp32_4way { + // Single vectors + def _MZZ_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<0, 0, mnemonic, ZPR8Mul2_Lo, ZPR8Mul2_Hi>; + + // Multiple and single vectors + def _M2ZZ_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<0, 1, mnemonic, ZZ_b_mul_r_Lo, ZPR8Mul2_Hi>; + + // Single and multiple vectors + def _MZ2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 0, mnemonic, ZPR8Mul2_Lo, ZZ_b_mul_r_Hi>; + + // Multiple vectors + def _M2Z2Z_BtoS : sme2_fp8_fp32_quarter_tile_outer_product<1, 1, mnemonic, ZZ_b_mul_r_Lo, ZZ_b_mul_r_Hi>; +} + +class sme2_bf16_fp16_quarter_tile_outer_product + : I<(outs TileOp16:$ZAda), + (ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, Sched<[]> { + bit ZAda; + bits<3> Zn; + bits<3> Zm; + + let Inst{31-21} = 0b10000001001; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = S; + let Inst{3-1} = 0b100; + let Inst{0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme2_bfmop4as_non_widening { + // Single vectors + def _MZZ_H : sme2_bf16_fp16_quarter_tile_outer_product<0, 0, S, mnemonic, ZPR16Mul2_Lo, ZPR16Mul2_Hi>; + + // Multiple and single vectors + def _M2ZZ_H : sme2_bf16_fp16_quarter_tile_outer_product<0, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZPR16Mul2_Hi>; + + // Single and multiple vectors + def _MZ2Z_H : sme2_bf16_fp16_quarter_tile_outer_product<1, 0, S, mnemonic, ZPR16Mul2_Lo, ZZ_h_mul_r_Hi>; + + // Multiple vectors + def _M2Z2Z_H : sme2_bf16_fp16_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>; +} + +class sme2_fp32_quarter_tile_outer_product + : I<(outs TileOp32:$ZAda), + (ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, Sched<[]> { + bits<2> ZAda; + bits<3> Zn; + bits<3> Zm; + + let Inst{31-21} = 0b10000000000; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = S; + let Inst{3-2} = 0b00; + let Inst{1-0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme2_fmop4as_fp32_non_widening { + // Single vectors + def _MZZ_S : sme2_fp32_quarter_tile_outer_product<0, 0, S, mnemonic, ZPR32Mul2_Lo, ZPR32Mul2_Hi>; + + // Multiple and single vectors + def _M2ZZ_S : sme2_fp32_quarter_tile_outer_product<0, 1, S, mnemonic, ZZ_s_mul_r_Lo, ZPR32Mul2_Hi>; + + // Single and multiple vectors + def _MZ2Z_S : sme2_fp32_quarter_tile_outer_product<1, 0, S, mnemonic, ZPR32Mul2_Lo, ZZ_s_mul_r_Hi>; + + // Multiple vectors + def _M2Z2Z_S : sme2_fp32_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_s_mul_r_Lo, ZZ_s_mul_r_Hi>; +} + +class sme2_fp64_quarter_tile_outer_product + : I<(outs TileOp64:$ZAda), + (ins TileOp64:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, Sched<[]> { + bits<3> ZAda; + bits<3> Zn; + bits<3> Zm; + + let Inst{31-21} = 0b10000000110; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = S; + let Inst{3} = 0b1; + let Inst{2-0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme2_fmop4as_fp64_non_widening { + // Single vectors + def _MZZ_D : sme2_fp64_quarter_tile_outer_product<0, 0, S, mnemonic, ZPR64Mul2_Lo, ZPR64Mul2_Hi>; + + // Multiple and single vectors + def _M2ZZ_D : sme2_fp64_quarter_tile_outer_product<0, 1, S, mnemonic, ZZ_d_mul_r_Lo, ZPR64Mul2_Hi>; + + // Single and multiple vectors + def _MZ2Z_D : sme2_fp64_quarter_tile_outer_product<1, 0, S, mnemonic, ZPR64Mul2_Lo, ZZ_d_mul_r_Hi>; + + // Multiple vectors + def _M2Z2Z_D : sme2_fp64_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_d_mul_r_Lo, ZZ_d_mul_r_Hi>; +} + +class sme2_fp16_fp32_quarter_tile_outer_product + : I<(outs TileOp32:$ZAda), + (ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm), + mnemonic, "\t$ZAda, $Zn, $Zm", + "", []>, Sched<[]> { + bits<2> ZAda; + bits<3> Zn; + bits<3> Zm; + + let Inst{31-21} = 0b10000001001; + let Inst{20} = M; + let Inst{19-17} = Zm; + let Inst{16-10} = 0b0000000; + let Inst{9} = N; + let Inst{8-6} = Zn; + let Inst{5} = 0; + let Inst{4} = S; + let Inst{3-2} = 0b00; + let Inst{1-0} = ZAda; + + let Constraints = "$ZAda = $_ZAda"; +} + +multiclass sme2_fmop4as_fp16_fp32_widening { + // Single vectors + def _MZZ_HtoS : sme2_fp16_fp32_quarter_tile_outer_product<0, 0, S, mnemonic, ZPR16Mul2_Lo, ZPR16Mul2_Hi>; + + // Multiple and single vectors + def _M2ZZ_HtoS : sme2_fp16_fp32_quarter_tile_outer_product<0, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZPR16Mul2_Hi>; + + // Single and multiple vectors + def _MZ2Z_HtoS : sme2_fp16_fp32_quarter_tile_outer_product<1, 0, S, mnemonic, ZPR16Mul2_Lo, ZZ_h_mul_r_Hi>; + + // Multiple vectors + def _M2Z2Z_HtoS : sme2_fp16_fp32_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>; +} diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index d1ceb30f36dcdc9b2d6282325b3ff439c9cb0425..552d5b9b23a7e4c75a7ae5fce2242dd7fc059710 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1046,7 +1046,7 @@ multiclass sve_int_count_v opc, string asm, (!cast(NAME # "_D") ZPR64:$Zdn, PPRAny:$Pm), 0>; } -class sve_int_pcount_pred sz8_64, bits<4> opc, string asm, +class sve_int_pcount_pred sz8_64, bits<3> opc, string asm, PPRRegOp pprty> : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn), asm, "\t$Rd, $Pg, $Pn", @@ -1058,17 +1058,17 @@ class sve_int_pcount_pred sz8_64, bits<4> opc, string asm, let Inst{31-24} = 0b00100101; let Inst{23-22} = sz8_64; let Inst{21-19} = 0b100; - let Inst{18-16} = opc{3-1}; + let Inst{18-16} = opc{2-0}; let Inst{15-14} = 0b10; let Inst{13-10} = Pg; - let Inst{9} = opc{0}; + let Inst{9} = 0b0; let Inst{8-5} = Pn; let Inst{4-0} = Rd; let hasSideEffects = 0; } -multiclass sve_int_pcount_pred opc, string asm, +multiclass sve_int_pcount_pred opc, string asm, SDPatternOperator int_op> { def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>; def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>; @@ -1081,6 +1081,12 @@ multiclass sve_int_pcount_pred opc, string asm, def : SVE_2_Op_Pat(NAME # _D)>; } +multiclass sve_int_pcount_pred_tmp opc, string asm> { + def _B : sve_int_pcount_pred<0b00, opc, asm, PPR8>; + def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>; + def _S : sve_int_pcount_pred<0b10, opc, asm, PPR32>; + def _D : sve_int_pcount_pred<0b11, opc, asm, PPR64>; +} //===----------------------------------------------------------------------===// // SVE Element Count Group //===----------------------------------------------------------------------===// @@ -3207,6 +3213,15 @@ multiclass sve_fp_z2op_p_zd_d_flogb { def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>; } +multiclass sve_fp_z2op_p_zd_b_0 { + def _StoH : sve_fp_z2op_p_zd<0b1001000, asm, ZPR32, ZPR16>; + def _HtoS : sve_fp_z2op_p_zd<0b1001001, asm, ZPR16, ZPR32>; + def _DtoH : sve_fp_z2op_p_zd<0b1101000, asm, ZPR64, ZPR16>; + def _HtoD : sve_fp_z2op_p_zd<0b1101001, asm, ZPR16, ZPR64>; + def _DtoS : sve_fp_z2op_p_zd<0b1101010, asm, ZPR64, ZPR32>; + def _StoD : sve_fp_z2op_p_zd<0b1101011, asm, ZPR32, ZPR64>; +} + //===----------------------------------------------------------------------===// // SVE Integer Arithmetic - Binary Predicated Group //===----------------------------------------------------------------------===// @@ -7299,11 +7314,59 @@ class sve2_int_perm_splice_cons sz8_64, string asm, let hasSideEffects = 0; } -multiclass sve2_int_perm_splice_cons { +multiclass sve2_int_perm_splice_cons { def _B : sve2_int_perm_splice_cons<0b00, asm, ZPR8, ZZ_b>; def _H : sve2_int_perm_splice_cons<0b01, asm, ZPR16, ZZ_h>; def _S : sve2_int_perm_splice_cons<0b10, asm, ZPR32, ZZ_s>; def _D : sve2_int_perm_splice_cons<0b11, asm, ZPR64, ZZ_d>; + + let AddedComplexity = 2 in { + foreach VT = [nxv16i8] in + def : Pat<(VT (op nxv16i1:$pred, VT:$zn1, VT:$zn2)), + (!cast(NAME # _B) + nxv16i1:$pred, (REG_SEQUENCE ZPR2, VT:$zn1, zsub0, VT:$zn2, zsub1))>; + + foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in + def : Pat<(VT (op nxv8i1:$pred, VT:$zn1, VT:$zn2)), + (!cast(NAME # _H) + nxv8i1:$pred, (REG_SEQUENCE ZPR2, VT:$zn1, zsub0, VT:$zn2, zsub1))>; + + foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in + def : Pat<(VT (op nxv4i1:$pred, VT:$zn1, VT:$zn2)), + (!cast(NAME # _S) + nxv4i1:$pred, (REG_SEQUENCE ZPR2, VT:$zn1, zsub0, VT:$zn2, zsub1))>; + + foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in + def : Pat<(VT (op nxv2i1:$pred, VT:$zn1, VT:$zn2)), + (!cast(NAME # _D) + nxv2i1:$pred, (REG_SEQUENCE ZPR2, VT:$zn1, zsub0, VT:$zn2, zsub1))>; + } +} + +class sve2_int_perm_expand sz, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn), + asm, "\t$Zd, $Pg, $Zn", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zn; + bits<5> Zd; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz; + let Inst{21-13} = 0b110001100; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; + + let hasSideEffects = 0; +} + +multiclass sve2_int_perm_expand { + def _B : sve2_int_perm_expand<0b00, asm, ZPR8>; + def _H : sve2_int_perm_expand<0b01, asm, ZPR16>; + def _S : sve2_int_perm_expand<0b10, asm, ZPR32>; + def _D : sve2_int_perm_expand<0b11, asm, ZPR64>; } class sve_int_perm_rev sz8_64, bits<2> opc, string asm, @@ -7467,7 +7530,7 @@ multiclass sve_int_perm_cpy_v { (!cast(NAME # _H) $passthru, $pg, $splat)>; } -class sve_int_perm_compact +class sve_int_perm_compact sz, string asm, ZPRRegOp zprty> : I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn), asm, "\t$Zd, $Pg, $Zn", "", @@ -7475,8 +7538,8 @@ class sve_int_perm_compact bits<3> Pg; bits<5> Zd; bits<5> Zn; - let Inst{31-23} = 0b000001011; - let Inst{22} = sz; + let Inst{31-24} = 0b00000101; + let Inst{23-22} = sz; let Inst{21-13} = 0b100001100; let Inst{12-10} = Pg; let Inst{9-5} = Zn; @@ -7485,9 +7548,9 @@ class sve_int_perm_compact let hasSideEffects = 0; } -multiclass sve_int_perm_compact { - def _S : sve_int_perm_compact<0b0, asm, ZPR32>; - def _D : sve_int_perm_compact<0b1, asm, ZPR64>; +multiclass sve_int_perm_compact_sd { + def _S : sve_int_perm_compact<0b10, asm, ZPR32>; + def _D : sve_int_perm_compact<0b11, asm, ZPR64>; def : SVE_2_Op_Pat(NAME # _S)>; def : SVE_2_Op_Pat(NAME # _S)>; @@ -7495,6 +7558,11 @@ multiclass sve_int_perm_compact { def : SVE_2_Op_Pat(NAME # _D)>; } +multiclass sve_int_perm_compact_bh { + def _B : sve_int_perm_compact<0b00, asm, ZPR8>; + def _H : sve_int_perm_compact<0b01, asm, ZPR16>; +} + //===----------------------------------------------------------------------===// // SVE Memory - Contiguous Load Group //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp index 687a7339da379d5eef5d09c8015e8c9a64aef1ae..6a69b9d2bfc7161cfa8cb20da86dbbb216e7b53e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp @@ -358,7 +358,7 @@ struct AAUniformWorkGroupSizeFunction : public AAUniformWorkGroupSize { const auto *CallerInfo = A.getAAFor( *this, IRPosition::function(*Caller), DepClassTy::REQUIRED); - if (!CallerInfo) + if (!CallerInfo || !CallerInfo->isValidState()) return false; Change = Change | clampStateAndIndicateChange(this->getState(), @@ -449,7 +449,8 @@ struct AAAMDAttributesFunction : public AAAMDAttributes { // Check for Intrinsics and propagate attributes. const AACallEdges *AAEdges = A.getAAFor( *this, this->getIRPosition(), DepClassTy::REQUIRED); - if (!AAEdges || AAEdges->hasNonAsmUnknownCallee()) + if (!AAEdges || !AAEdges->isValidState() || + AAEdges->hasNonAsmUnknownCallee()) return indicatePessimisticFixpoint(); bool IsNonEntryFunc = !AMDGPU::isEntryFunctionCC(F->getCallingConv()); @@ -465,7 +466,7 @@ struct AAAMDAttributesFunction : public AAAMDAttributes { if (IID == Intrinsic::not_intrinsic) { const AAAMDAttributes *AAAMD = A.getAAFor( *this, IRPosition::function(*Callee), DepClassTy::REQUIRED); - if (!AAAMD) + if (!AAAMD || !AAAMD->isValidState()) return indicatePessimisticFixpoint(); *this &= *AAAMD; continue; @@ -660,7 +661,7 @@ private: const auto *PointerInfoAA = A.getAAFor( *this, IRPosition::callsite_returned(Call), DepClassTy::REQUIRED); - if (!PointerInfoAA) + if (!PointerInfoAA || !PointerInfoAA->getState().isValidState()) return false; return PointerInfoAA->forallInterferingAccesses( @@ -717,7 +718,7 @@ struct AAAMDSizeRangeAttribute const auto *CallerInfo = A.getAAFor( *this, IRPosition::function(*Caller), DepClassTy::REQUIRED); - if (!CallerInfo) + if (!CallerInfo || !CallerInfo->isValidState()) return false; Change |= @@ -835,7 +836,8 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute { auto &InfoCache = static_cast(A.getInfoCache()); if (const auto *AssumedGroupSize = A.getAAFor( - *this, IRPosition::function(*F), DepClassTy::REQUIRED)) { + *this, IRPosition::function(*F), DepClassTy::REQUIRED); + AssumedGroupSize->isValidState()) { unsigned Min, Max; std::tie(Min, Max) = InfoCache.getWavesPerEU( @@ -864,7 +866,8 @@ struct AAAMDWavesPerEU : public AAAMDSizeRangeAttribute { *this, IRPosition::function(*Caller), DepClassTy::REQUIRED); const auto *AssumedGroupSize = A.getAAFor( *this, IRPosition::function(*Func), DepClassTy::REQUIRED); - if (!CallerInfo || !AssumedGroupSize) + if (!CallerInfo || !AssumedGroupSize || !CallerInfo->isValidState() || + !AssumedGroupSize->isValidState()) return false; unsigned Min, Max; @@ -982,7 +985,8 @@ struct AAAMDGPUNoAGPR // TODO: Handle callsite attributes const auto *CalleeInfo = A.getAAFor( *this, IRPosition::function(*Callee), DepClassTy::REQUIRED); - return CalleeInfo && CalleeInfo->getAssumed(); + return CalleeInfo && CalleeInfo->isValidState() && + CalleeInfo->getAssumed(); }; bool UsedAssumedInformation = false; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp index 351e9f25e29cfc23a7b8c5974c19cddf36f98b8d..ab62e530a18d0cf3dffa983a8a50d91f6d52d086 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -230,13 +230,6 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler { return AddrReg.getReg(0); } - void assignValueToReg(Register ValVReg, Register PhysReg, - const CCValAssign &VA) override { - MIB.addUse(PhysReg, RegState::Implicit); - Register ExtReg = extendRegisterMin32(*this, ValVReg, VA); - MIRBuilder.buildCopy(PhysReg, ExtReg); - } - void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO, const CCValAssign &VA) override { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td index 21412044d5a0139a7ae8ecec7813114749fef044..80969fce3d77fb57d208322c32f26ffa7fda64e8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td @@ -22,19 +22,13 @@ def CC_SI_Gfx : CallingConv<[ // 32 is reserved for the stack pointer // 33 is reserved for the frame pointer // 34 is reserved for the base pointer - CCIfInReg>>, - - CCIfNotInReg>>, + CCIfInReg("SGPR"#i)) // SGPR4-29 + >>>, + + CCIfNotInReg("VGPR"#i)) // VGPR0-31 + >>>, CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>> ]>; @@ -43,93 +37,35 @@ def RetCC_SI_Gfx : CallingConv<[ CCIfType<[i1], CCPromoteToType>, CCIfType<[i1, i16], CCIfExtend>>, - CCIfNotInReg>>, + CCIfNotInReg("VGPR"#i)) // VGPR0-135 + >>>, ]>; def CC_SI_SHADER : CallingConv<[ CCIfType<[i1], CCPromoteToType>, - - CCIfInReg>>, + + CCIfInReg("SGPR"#i)) // SGPR0-43 + >>>, // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs. - CCIfNotInReg>> + CCIfNotInReg("VGPR"#i)) // VGPR0-135 + >>> ]>; def RetCC_SI_Shader : CallingConv<[ CCIfType<[i1, i16], CCIfExtend>>, - CCIfType<[i32, i16, v2i16] , CCAssignToReg<[ - SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, - SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, - SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, - SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, - SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39, - SGPR40, SGPR41, SGPR42, SGPR43 - ]>>, + CCIfType<[i32, i16, v2i16] , CCAssignToReg< + !foreach(i, !range(0, 44), !cast("SGPR"#i)) // SGPR0-43 + >>, // 32*4 + 4 is the minimum for a fetch shader with 32 outputs. - CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg<[ - VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, - VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, - VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, - VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, - VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39, - VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47, - VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55, - VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63, - VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71, - VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79, - VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87, - VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95, - VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103, - VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111, - VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119, - VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127, - VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135 - ]>> + CCIfType<[f32, f16, v2f16, bf16, v2bf16] , CCAssignToReg< + !foreach(i, !range(0, 136), !cast("VGPR"#i)) // VGPR0-135 + >> ]>; def CSR_AMDGPU_VGPRs : CalleeSavedRegs< @@ -194,11 +130,9 @@ def CC_AMDGPU_Func : CallingConv<[ !foreach(i, !range(0, 30), !cast("SGPR"#i)) // SGPR0-29 >>>, - CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg<[ - VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, - VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, - VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, - VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>, + CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1, bf16, v2bf16], CCAssignToReg< + !foreach(i, !range(0, 32), !cast("VGPR"#i)) // VGPR0-31 + >>, CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1, bf16, v2bf16], CCAssignToStack<4, 4>> ]>; @@ -206,11 +140,9 @@ def CC_AMDGPU_Func : CallingConv<[ def RetCC_AMDGPU_Func : CallingConv<[ CCIfType<[i1], CCPromoteToType>, CCIfType<[i1, i16], CCIfExtend>>, - CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg<[ - VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, - VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, - VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, - VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>, + CCIfType<[i32, f32, i16, f16, v2i16, v2f16, bf16, v2bf16], CCAssignToReg< + !foreach(i, !range(0, 32), !cast("VGPR"#i)) // VGPR0-31 + >>, ]>; def CC_AMDGPU : CallingConv<[ diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index f8744d6a483cffec269a2d96a78b1ea4be62c558..7dd7388376f47434e1f34cb8a9d390149a9c2e58 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -1159,7 +1159,6 @@ bool AMDGPUPromoteAllocaImpl::collectUsesWithPtrTypes( if (LoadInst *LI = dyn_cast(UseInst)) { if (LI->isVolatile()) return false; - continue; } @@ -1170,12 +1169,19 @@ bool AMDGPUPromoteAllocaImpl::collectUsesWithPtrTypes( // Reject if the stored value is not the pointer operand. if (SI->getPointerOperand() != Val) return false; - } else if (AtomicRMWInst *RMW = dyn_cast(UseInst)) { + continue; + } + + if (AtomicRMWInst *RMW = dyn_cast(UseInst)) { if (RMW->isVolatile()) return false; - } else if (AtomicCmpXchgInst *CAS = dyn_cast(UseInst)) { + continue; + } + + if (AtomicCmpXchgInst *CAS = dyn_cast(UseInst)) { if (CAS->isVolatile()) return false; + continue; } // Only promote a select if we know that the other select operand @@ -1186,6 +1192,7 @@ bool AMDGPUPromoteAllocaImpl::collectUsesWithPtrTypes( // May need to rewrite constant operands. WorkList.push_back(ICmp); + continue; } // TODO: If we know the address is only observed through flat pointers, we @@ -1198,8 +1205,9 @@ bool AMDGPUPromoteAllocaImpl::collectUsesWithPtrTypes( if (isa(User) || isa(User)) return false; + // TODO: Handle vectors of pointers. if (!User->getType()->isPointerTy()) - continue; + return false; if (GetElementPtrInst *GEP = dyn_cast(UseInst)) { // Be conservative if an address could be computed outside the bounds of @@ -1504,6 +1512,8 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToLDS(AllocaInst &I, PointerType *NewTy = PointerType::get(Context, AMDGPUAS::LOCAL_ADDRESS); + assert(isa(V->getType())); + // FIXME: It doesn't really make sense to try to do this for all // instructions. V->mutateType(NewTy); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index dd8d93c3f0b72a0c611beb55bf255cdb8f8417ca..88caf8196b3c90ae6d3e667470ba6335c6900745 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -24,7 +24,7 @@ using namespace llvm; using namespace llvm::AMDGPU; -void AMDGPUInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void AMDGPUInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { // FIXME: The current implementation of // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this // as an integer or we provide a name which represents a physical register. diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h index a72e0fe6ea769f51c69732f3b7967be814f6d60d..4729b8a6aa6f40188e36b0f634c277a8a7b8aae8 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -29,7 +29,7 @@ public: const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; static void printRegOperand(MCRegister Reg, raw_ostream &O, diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index c912a580854c1c48d35ae32e338485600884ee69..f0c7837e0bb75ac1faedc64076f76bbf3f6133fa 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -1793,6 +1793,9 @@ bool SIFoldOperandsImpl::tryFoldOMod(MachineInstr &MI) { DefOMod->setImm(OMod); MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg()); + // Kill flags can be wrong if we replaced a def inside a loop with a def + // outside the loop. + MRI->clearKillFlags(Def->getOperand(0).getReg()); MI.eraseFromParent(); // Use of output modifiers forces VOP3 encoding for a VOP2 mac/fmac diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 52ca38aca5c7711dab79305642de8f92f9e0a30b..bddb6e822b81b719fe9e647e6fa8beaf34183b30 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3855,10 +3855,14 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI, unsigned ArgIdx = 0; for (auto [Reg, Val] : RegsToPass) { - if (ArgIdx++ >= NumSpecialInputs && !Val->isDivergent() && - TRI->isSGPRPhysReg(Reg)) { - // Speculatively insert a readfirstlane in case this is a uniform value in - // a VGPR. + if (ArgIdx++ >= NumSpecialInputs && + (IsChainCallConv || !Val->isDivergent()) && TRI->isSGPRPhysReg(Reg)) { + // For chain calls, the inreg arguments are required to be + // uniform. Speculatively Insert a readfirstlane in case we cannot prove + // they are uniform. + // + // For other calls, if an inreg arguments is known to be uniform, + // speculatively insert a readfirstlane in case it is in a VGPR. // // FIXME: We need to execute this in a waterfall loop if it is a divergent // value, so let that continue to produce invalid code. @@ -3893,9 +3897,6 @@ SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI, Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64)); } else { if (IsTailCall) { - assert(!Callee->isDivergent() && - "cannot tail call a divergent call target"); - // isEligibleForTailCallOptimization considered whether the call target is // divergent, but we may still end up with a uniform value in a VGPR. // Insert a readfirstlane just in case. diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index faa0b6d6c3f506327558c46988b715ff55cd1a49..c8a46217190a1d1f81dd1c2b40a6346898c4429a 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3553,19 +3553,6 @@ def : AMDGPUPat < (V_BFE_U32_e64 $src, (i32 0), $width) >; -// x << (bitwidth - y) >> (bitwidth - y) -def : AMDGPUPat < - (DivergentBinFrag (shl_oneuse i32:$src, (sub 32, i32:$width)), - (sub 32, i32:$width)), - (V_BFE_U32_e64 $src, (i32 0), $width) ->; - -def : AMDGPUPat < - (DivergentBinFrag (shl_oneuse i32:$src, (sub 32, i32:$width)), - (sub 32, i32:$width)), - (V_BFE_I32_e64 $src, (i32 0), $width) ->; - // SHA-256 Ma patterns // ((x & z) | (y & (x | z))) -> BFI (XOR x, y), z, y diff --git a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp index d76c2810c39f8c675cc0c052cc0dcc1e6b5f6dc3..e669b9479369d635c107c3bc1c230ddc3ff6f0a7 100644 --- a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp +++ b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp @@ -93,7 +93,7 @@ static const char *ARCCondCodeToString(ARCCC::CondCode CC) { return BadConditionCode(CC); } -void ARCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void ARCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << StringRef(getRegisterName(Reg)).lower(); } diff --git a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h index baf4a6915b70657fc9d42ea57942e6fe693bfb15..c4bd73448ca71b71afee7aa968095c9aab1b70d5 100644 --- a/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h +++ b/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h @@ -30,7 +30,7 @@ public: void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; void printCCOperand(const MCInst *MI, int OpNum, raw_ostream &O); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index a98b7a8420927ea86fb421d509d08591c9ffdc5f..e0022190d87c18a15c77d6badccfd65a088dffbc 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -6051,7 +6051,7 @@ static SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG, DAG.getConstant((1 << BW) - 1, DL, VT)); if (IsSigned) Max = DAG.getNode(ISD::SMAX, DL, VT, Max, - DAG.getConstant(-(1 << BW), DL, VT)); + DAG.getSignedConstant(-(1 << BW), DL, VT)); return Max; } diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 61635bd1629eb84c59e1d00a48407d08ed099665..cb20aacb539ad9b840646d59464815273f074757 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -77,8 +77,8 @@ def t2_so_imm_not_XFORM : SDNodeXFormgetTargetConstant(-((int)N->getZExtValue()), SDLoc(N), - MVT::i32); + return CurDAG->getSignedConstant(-((int)N->getZExtValue()), SDLoc(N), + MVT::i32, /*isTarget=*/true); }]>; // so_imm_notSext_XFORM - Return a so_imm value packed into the format diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp index e4a2f8c8f2ea0ceb75b5f61ff458eba6ba3425c1..5a6895a4ab84ef3604ffb08cd951cdb39d7ca30c 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp @@ -50,7 +50,7 @@ static unsigned translateShiftImm(unsigned imm) { } static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, - unsigned ShImm, const ARMInstPrinter &printer) { + unsigned ShImm, ARMInstPrinter &printer) { if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) return; O << ", "; @@ -81,7 +81,7 @@ bool ARMInstPrinter::applyTargetSpecificCLOption(StringRef Opt) { return false; } -void ARMInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void ARMInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << getRegisterName(Reg, DefaultAltIdx); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h index 494a644cf545462099db5a60a0dd0c33b15551bf..cd1dddc5f331a331790a196eab230e286f32f970 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h @@ -27,7 +27,7 @@ public: void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; // Autogenerated by tblgen. std::pair getMnemonic(const MCInst *MI) override; diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td index 9809caa8bd8f65b31c61eab42756ba1204444071..f88daeed8d421545e4cb0c7c14de726c04341dad 100644 --- a/llvm/lib/Target/CSKY/CSKY.td +++ b/llvm/lib/Target/CSKY/CSKY.td @@ -97,28 +97,28 @@ def iHasFLOAT7E60 : Predicate<"Subtarget->hasFLOAT7E60()">, "Support CSKY float7e60 instructions">; def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", - "Enable divide instrutions">; + "Enable divide instructions">; def HasHWDiv : Predicate<"Subtarget->hasHardwareDivide()">, AssemblerPredicate<(all_of FeatureHWDiv), - "Enable divide instrutions">; + "Enable divide instructions">; def FeatureSTM : SubtargetFeature<"multiple_stld", "HasSTM", "true", - "Enable multiple load/store instrutions">; + "Enable multiple load/store instructions">; def HasSTM : Predicate<"Subtarget->hasSTM()">, AssemblerPredicate<(all_of FeatureSTM), - "Enable multiple load/store instrutions">; + "Enable multiple load/store instructions">; def FeaturePushPop : SubtargetFeature<"pushpop", "HasPushPop", "true", - "Enable push/pop instrutions">; + "Enable push/pop instructions">; def HasPushPop : Predicate<"Subtarget->hasPushPop()">, AssemblerPredicate<(all_of FeaturePushPop), - "Enable push/pop instrutions">; + "Enable push/pop instructions">; def FeatureDSP - : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instrutions">; + : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instructions">; def HasDSP : Predicate<"Subtarget->hasDSP()">, AssemblerPredicate<(all_of FeatureDSP), - "Enable DSP instrutions">; + "Enable DSP instructions">; def HasDSP1E2 : SubtargetFeature<"dsp1e2", "HasDSP1E2", "true", "Support CSKY dsp1e2 instructions">; @@ -133,16 +133,16 @@ def iHasDSPE60 : Predicate<"Subtarget->hasDSPE60()">, "Support CSKY dspe60 instructions">; def FeatureDSPV2 : SubtargetFeature<"dspv2", "HasDSPV2", "true", - "Enable DSP V2.0 instrutions">; + "Enable DSP V2.0 instructions">; def HasDSPV2 : Predicate<"Subtarget->hasDSPV2()">, AssemblerPredicate<(all_of FeatureDSPV2), - "Enable DSP V2.0 instrutions">; + "Enable DSP V2.0 instructions">; def FeatureDSP_Silan : SubtargetFeature<"dsp_silan", "HasDSP_Silan", "true", - "Enable DSP Silan instrutions">; + "Enable DSP Silan instructions">; def HasDSP_Silan : Predicate<"Subtarget->hasDSP_Silan()">, AssemblerPredicate<(all_of FeatureDSP_Silan), - "Enable DSP Silan instrutions">; + "Enable DSP Silan instructions">; // Atomic Support def FeatureBTST16 : SubtargetFeature<"btst16", "HasBTST16", "true", @@ -232,11 +232,11 @@ def FeatureSoftTP : SubtargetFeature<"soft-tp", "ReadTPHard", "false", "Disable TLS Pointer register">; def FeatureIstack : SubtargetFeature<"istack", "EnableInterruptAttribute", - "true", "Enable interrput attribute">; + "true", "Enable interrupt attribute">; def EnableInterruptAttribute : Predicate<"Subtarget->enableInterruptAttribute()">, AssemblerPredicate<(all_of FeatureIstack), - "Enable interrput attribute">; + "Enable interrupt attribute">; def FeatureConstPool : SubtargetFeature<"constpool", "DumpConstPool", "true", "Dump the constant pool by compiler">; diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp index 9af7958112fce30e8e58383095f841b4cbc7f4d9..a4b0d8488cf53b32a7a442af1139254b971b5195 100644 --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp @@ -82,7 +82,7 @@ void CSKYInstPrinter::printInst(const MCInst *MI, uint64_t Address, printAnnotation(O, Annot); } -void CSKYInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void CSKYInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { if (PrintBranchImmAsAddress) O << getRegisterName(Reg, ABIRegNames ? CSKY::ABIRegAltName : CSKY::NoRegAltName); diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h index 461d7f6f12b371bd918e8172d6e19e500a1827a6..16eccfdfb5ce5bceadf853049053698df1d808a3 100644 --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h @@ -31,7 +31,7 @@ public: void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier = nullptr); diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td index 68ae5de06423c2a6b2b584604707d670ad2f3779..1e8dc63ffa257e1422c5b47f9135a549bdb2f303 100644 --- a/llvm/lib/Target/DirectX/DXIL.td +++ b/llvm/lib/Target/DirectX/DXIL.td @@ -554,11 +554,10 @@ def Rbits : DXILOp<30, unary> { let attributes = [Attributes]; } -def CBits : DXILOp<31, unary> { +def CountBits : DXILOp<31, unaryBits> { let Doc = "Returns the number of 1 bits in the specified value."; - let LLVMIntrinsic = int_ctpop; let arguments = [OverloadTy]; - let result = OverloadTy; + let result = Int32Ty; let overloads = [Overloads]; let stages = [Stages]; diff --git a/llvm/lib/Target/DirectX/DXILOpLowering.cpp b/llvm/lib/Target/DirectX/DXILOpLowering.cpp index f7722d77074764d119aa9321247d20abaf9d2f52..8acc9c1efa08c081f2ee4c028c06f713c9c20ac2 100644 --- a/llvm/lib/Target/DirectX/DXILOpLowering.cpp +++ b/llvm/lib/Target/DirectX/DXILOpLowering.cpp @@ -505,6 +505,73 @@ public: }); } + [[nodiscard]] bool lowerCtpopToCountBits(Function &F) { + IRBuilder<> &IRB = OpBuilder.getIRB(); + Type *Int32Ty = IRB.getInt32Ty(); + + return replaceFunction(F, [&](CallInst *CI) -> Error { + IRB.SetInsertPoint(CI); + SmallVector Args; + Args.append(CI->arg_begin(), CI->arg_end()); + + Type *RetTy = Int32Ty; + Type *FRT = F.getReturnType(); + if (const auto *VT = dyn_cast(FRT)) + RetTy = VectorType::get(RetTy, VT); + + Expected OpCall = OpBuilder.tryCreateOp( + dxil::OpCode::CountBits, Args, CI->getName(), RetTy); + if (Error E = OpCall.takeError()) + return E; + + // If the result type is 32 bits we can do a direct replacement. + if (FRT->isIntOrIntVectorTy(32)) { + CI->replaceAllUsesWith(*OpCall); + CI->eraseFromParent(); + return Error::success(); + } + + unsigned CastOp; + unsigned CastOp2; + if (FRT->isIntOrIntVectorTy(16)) { + CastOp = Instruction::ZExt; + CastOp2 = Instruction::SExt; + } else { // must be 64 bits + assert(FRT->isIntOrIntVectorTy(64) && + "Currently only lowering 16, 32, or 64 bit ctpop to CountBits \ + is supported."); + CastOp = Instruction::Trunc; + CastOp2 = Instruction::Trunc; + } + + // It is correct to replace the ctpop with the dxil op and + // remove all casts to i32 + bool NeedsCast = false; + for (User *User : make_early_inc_range(CI->users())) { + Instruction *I = dyn_cast(User); + if (I && (I->getOpcode() == CastOp || I->getOpcode() == CastOp2) && + I->getType() == RetTy) { + I->replaceAllUsesWith(*OpCall); + I->eraseFromParent(); + } else + NeedsCast = true; + } + + // It is correct to replace a ctpop with the dxil op and + // a cast from i32 to the return type of the ctpop + // the cast is emitted here if there is a non-cast to i32 + // instr which uses the ctpop + if (NeedsCast) { + Value *Cast = + IRB.CreateZExtOrTrunc(*OpCall, F.getReturnType(), "ctpop.cast"); + CI->replaceAllUsesWith(Cast); + } + + CI->eraseFromParent(); + return Error::success(); + }); + } + bool lowerIntrinsics() { bool Updated = false; bool HasErrors = false; @@ -543,6 +610,9 @@ public: return replaceSplitDoubleCallUsages(CI, Op); }); break; + case Intrinsic::ctpop: + HasErrors |= lowerCtpopToCountBits(F); + break; } Updated = true; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp index de5c8b86978a827ccf940a4944ad3ac1a66ba630..e4e84a80b5d0bc76992a08406b0c65e6bab12c3b 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp @@ -26,7 +26,7 @@ using namespace llvm; #define GET_INSTRUCTION_NAME #include "HexagonGenAsmWriter.inc" -void HexagonInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void HexagonInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { O << getRegisterName(Reg); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h index 38a9081c93fe794b253476f7959ffce6c2e77a53..fe37cd91dabc6ad1b945d0cb98c870ef763cd74a 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h @@ -30,7 +30,7 @@ public: void printInst(MCInst const *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; static char const *getRegisterName(MCRegister Reg); diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp index 0265a75fb346c9fdb7ebef3b47d318b58d435e6b..4b5751eaedda052f37a1f8fc3836ced846e4348c 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp @@ -31,7 +31,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "LanaiGenAsmWriter.inc" -void LanaiInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void LanaiInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << StringRef(getRegisterName(Reg)).lower(); } diff --git a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h index 55a254036fee5b63146a7d9fdf3146faed6fff82..851613b27e3dd901906f5e91504706d864ab191b 100644 --- a/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h +++ b/llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h @@ -49,7 +49,7 @@ public: unsigned OpIdx, unsigned PrintMethodIdx, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; private: bool printAlias(const MCInst *MI, raw_ostream &Ostream); diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp index cb2521db5217e82c62940f6b8c012b75cf45175e..e3007cfe3d401b868cbe234335e8c9d3b753dfc6 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.cpp @@ -56,7 +56,7 @@ void LoongArchInstPrinter::printInst(const MCInst *MI, uint64_t Address, printAnnotation(O, Annot); } -void LoongArchInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void LoongArchInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { O << '$' << getRegisterName(Reg); } diff --git a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h index 4e6092bfcb12829d1b8cc038db4b67b62f691eb7..8cda3fdb4510e59e41c3ef6394b8f5d935fe262b 100644 --- a/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h +++ b/llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchInstPrinter.h @@ -28,7 +28,7 @@ public: void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printAtomicMemOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp index 84800fc762cbb81e47b45f00919ea025b119c0cf..68ac15b57508c18e70a2af61a1e23979bb2131f4 100644 --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.cpp @@ -41,7 +41,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "M68kGenAsmWriter.inc" -void M68kInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void M68kInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << "%" << getRegisterName(Reg); } diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h index 0963176304587c2c9d853cd917a6a6d1034394f7..d6d17ca9568e0244c0ef88d92c0b6110e786c025 100644 --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kInstPrinter.h @@ -34,7 +34,7 @@ public: void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp index 3726c600f4a7b82430579fc8a2c91113e7b84c59..d8a27f34c6fd13f88a2ba88d8f939596cd608ff1 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.cpp @@ -26,7 +26,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "MSP430GenAsmWriter.inc" -void MSP430InstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void MSP430InstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { O << getRegisterName(Reg); } diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h index 40605b92bcb01a6097b3257ace248652af8f7756..413492b8efeedaf0ff65c8133aebc4cdef2509d4 100644 --- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h +++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h @@ -22,7 +22,7 @@ namespace llvm { const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp index 1518a539782efb54adcd16c21523afe55f7ebdd3..2fd1b344eb687edd566d26c557a29e6015a5017a 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp @@ -72,7 +72,7 @@ const char* Mips::MipsFCCToString(Mips::CondCode CC) { llvm_unreachable("Impossible condition code!"); } -void MipsInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void MipsInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << '$' << StringRef(getRegisterName(Reg)).lower(); } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h index 0652b237509fe3fe809b20f348c8e7aff3bb39bf..8e3b4614a4aade64e8ab13e0cc57409bb1ea49ef 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h @@ -84,7 +84,7 @@ public: const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp index 9b589284463294cb48aca2b8c150693963242e58..4211ae5a2eebcdec2d3091b7773ee70785e25337 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp @@ -34,7 +34,7 @@ NVPTXInstPrinter::NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} -void NVPTXInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void NVPTXInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { // Decode the virtual register // Must be kept in sync with NVPTXAsmPrinter::encodeVirtualRegister unsigned RCId = (Reg.id() >> 28); diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h index e8a4a6dbdd5324b6394acfea0b207ee01e4a5f5f..63207e8a975ace29926b3ecaeec167a42839ad44 100644 --- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h +++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h @@ -24,7 +24,7 @@ public: NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index a95cba586b8fc391ea114c2671b36b74e431d57f..01abf9591e342f0705b7f06924b1728e573b807f 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -1335,8 +1335,6 @@ NVPTXTargetLowering::getPreferredVectorAction(MVT VT) const { if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1) return TypeSplitVector; - if (Isv2x16VT(VT)) - return TypeLegal; return TargetLoweringBase::getPreferredVectorAction(VT); } diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td index 5f6cba397c5352998a1f473e4c9fd9a5dc776917..1ca3aefb0b09344f17b7ecfadfe84e41c5cc9930 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td @@ -1922,7 +1922,7 @@ def imem : Operand { let PrintMethod = "printOperand"; } -def imemAny : Operand { +def imemAny : Operand { let PrintMethod = "printOperand"; } diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp index 1d6f39b290536af79950c70fef11986fb4b4c800..a5a147da8da1c5b5ef935efc91a54ddc24ffe214 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -332,7 +332,7 @@ void NVPTXPassConfig::addIRPasses() { disablePass(&PrologEpilogCodeInserterID); disablePass(&MachineLateInstrsCleanupID); disablePass(&MachineCopyPropagationID); - disablePass(&TailDuplicateID); + disablePass(&TailDuplicateLegacyID); disablePass(&StackMapLivenessID); disablePass(&PostRAMachineSinkingID); disablePass(&PostRASchedulerID); @@ -461,7 +461,7 @@ void NVPTXPassConfig::addOptimizedRegAlloc() { void NVPTXPassConfig::addMachineSSAOptimization() { // Pre-ra tail duplication. - if (addPass(&EarlyTailDuplicateID)) + if (addPass(&EarlyTailDuplicateLegacyID)) printAndVerify("After Pre-RegAlloc TailDuplicate"); // Optimize PHIs before DCE: removing dead PHI cycles may make more diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 9a4291c90408d60d32a96d46e68d8f82eddcaddc..7511e24f705c18ba12846ca18de90777b2c22bb5 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -47,7 +47,7 @@ FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, #define PRINT_ALIAS_INSTR #include "PPCGenAsmWriter.inc" -void PPCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void PPCInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { const char *RegName = getRegisterName(Reg); OS << RegName; } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h index 6ba3eb4c79dc990851497637d146fbd5d28b1489..1b9365fa04961c9991bf8dc68ac34e56a6d27371 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -31,7 +31,7 @@ public: const MCRegisterInfo &MRI, Triple T) : MCInstPrinter(MAI, MII, MRI), TT(T) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ab31898e262e7edc5a12758b0793cbd976e7733d..d8f3095ed7fb68ae4c5f0b6b34643b1713f50b1d 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -200,6 +200,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom); + // On P10, the default lowering generates better code using the + // setbc instruction. + if (!Subtarget.hasP10Vector() && isPPC64) + setOperationAction(ISD::SSUBO, MVT::i32, Custom); + // Match BITREVERSE to customized fast code sequence in the td file. setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); @@ -12016,6 +12021,36 @@ SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const { return Res; } +SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const { + + SDLoc dl(Op); + + SDValue LHS64 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Op.getOperand(0)); + SDValue RHS64 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, Op.getOperand(1)); + + SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i64, LHS64, RHS64); + + SDValue Extsw = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i64, Sub, + DAG.getValueType(MVT::i32)); + + SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i64, Extsw, Sub); + + SDValue Addic = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(MVT::i64, MVT::Glue), + Xor, DAG.getConstant(-1, dl, MVT::i64)); + + SDValue Overflow = + DAG.getNode(ISD::SUBE, dl, DAG.getVTList(MVT::i64, MVT::Glue), Xor, Addic, + Addic.getValue(1)); + + SDValue OverflowTrunc = + DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow); + SDValue SubTrunc = + (Sub->getValueType(0) != Op.getNode()->getValueType(0)) + ? DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(0), Sub) + : Sub; + return DAG.getMergeValues({SubTrunc, OverflowTrunc}, dl); +} + /// LowerOperation - Provide custom lowering hooks for some operations. /// SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { @@ -12038,6 +12073,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); + case ISD::SSUBO: + return LowerSSUBO(Op, DAG); case ISD::INLINEASM: case ISD::INLINEASM_BR: return LowerINLINEASM(Op, DAG); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 0adbad8684597313642ddffbfdd41575e5fb46c6..dde45e4cf6f4ae6d3c2af5879ca847cdf35bd0ec 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -1279,6 +1279,7 @@ namespace llvm { SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; SDValue LowerUaddo(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 2abe44ca26b4c4b8ae1bd78e6dafa752b6c27f2d..7fab807d05304630ba53b10e4d1b173940714be4 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -345,7 +345,20 @@ enum OperandType : unsigned { OPERAND_RVKRNUM_1_10, OPERAND_RVKRNUM_2_14, OPERAND_SPIMM, - OPERAND_LAST_RISCV_IMM = OPERAND_SPIMM, + // Operand is a 3-bit rounding mode, '111' indicates FRM register. + // Represents 'frm' argument passing to floating-point operations. + OPERAND_FRMARG, + // Operand is a 3-bit rounding mode where only RTZ is valid. + OPERAND_RTZARG, + // Condition code used by select and short forward branch pseudos. + OPERAND_COND_CODE, + // Vector policy operand. + OPERAND_VEC_POLICY, + // Vector SEW operand. + OPERAND_SEW, + // Vector rounding mode for VXRM or FRM. + OPERAND_VEC_RM, + OPERAND_LAST_RISCV_IMM = OPERAND_VEC_RM, // Operand is either a register or uimm5, this is used by V extension pseudo // instructions to represent a value that be passed as AVL to either vsetvli // or vsetivli. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index ef7f43b7e5d8092ca3779f534f841a0f48a4a857..00725c22adfcbece6ae1a30bf3d0c9134467ad99 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -75,7 +75,7 @@ void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address, printAnnotation(O, Annot); } -void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { markup(O, Markup::Register) << getRegisterName(Reg); } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h index 77cc7a67e88920d16a70732166a3c0841f34378a..c15fd591b9e9565e7d832f88c880430387b91fb0 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -28,7 +28,7 @@ public: void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier = nullptr); diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d18c812e6b9a22bba4a8b2ee8ee092e6b6e8e8bb..52e1fa50fdd1eccfeeb136537f00a5c6698b3539 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -741,7 +741,8 @@ def HasEPI : Predicate<"Subtarget->hasEPI()">, def FeatureStdExtZvkb : RISCVExtension<"zvkb", 1, 0, - "'Zvkb' (Vector Bit-manipulation used in Cryptography)">, + "'Zvkb' (Vector Bit-manipulation used in Cryptography)", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 52>; def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, AssemblerPredicate<(all_of FeatureStdExtZvkb), @@ -758,7 +759,8 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, def FeatureStdExtZvbc : RISCVExtension<"zvbc", 1, 0, - "'Zvbc' (Vector Carryless Multiplication)">, + "'Zvbc' (Vector Carryless Multiplication)", + [FeatureStdExtZve64x]>, RISCVExtensionBitmask<0, 49>; def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, AssemblerPredicate<(all_of FeatureStdExtZvbc), @@ -766,7 +768,8 @@ def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, def FeatureStdExtZvbc32e : RISCVExperimentalExtension<"zvbc32e", 0, 7, - "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)">; + "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)", + [FeatureStdExtZve32x]>; def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget->hasStdExtZvbc32e()">, AssemblerPredicate<(any_of FeatureStdExtZvbc, FeatureStdExtZvbc32e), @@ -774,7 +777,8 @@ def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget- def FeatureStdExtZvkg : RISCVExtension<"zvkg", 1, 0, - "'Zvkg' (Vector GCM instructions for Cryptography)">, + "'Zvkg' (Vector GCM instructions for Cryptography)", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 53>; def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, AssemblerPredicate<(all_of FeatureStdExtZvkg), @@ -790,7 +794,8 @@ def HasStdExtZvkgs : Predicate<"Subtarget->hasStdExtZvkgs()">, def FeatureStdExtZvkned : RISCVExtension<"zvkned", 1, 0, - "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">, + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 54>; def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, AssemblerPredicate<(all_of FeatureStdExtZvkned), @@ -798,7 +803,8 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : RISCVExtension<"zvknha", 1, 0, - "'Zvknha' (Vector SHA-2 (SHA-256 only))">, + "'Zvknha' (Vector SHA-2 (SHA-256 only))", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 55>; def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, AssemblerPredicate<(all_of FeatureStdExtZvknha), @@ -806,7 +812,8 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, def FeatureStdExtZvknhb : RISCVExtension<"zvknhb", 1, 0, - "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">, + "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", + [FeatureStdExtZve64x]>, RISCVExtensionBitmask<0, 56>; def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, AssemblerPredicate<(all_of FeatureStdExtZvknhb), @@ -818,7 +825,8 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg def FeatureStdExtZvksed : RISCVExtension<"zvksed", 1, 0, - "'Zvksed' (SM4 Block Cipher Instructions)">, + "'Zvksed' (SM4 Block Cipher Instructions)", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 57>; def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, AssemblerPredicate<(all_of FeatureStdExtZvksed), @@ -826,7 +834,8 @@ def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, def FeatureStdExtZvksh : RISCVExtension<"zvksh", 1, 0, - "'Zvksh' (SM3 Hash Function Instructions)">, + "'Zvksh' (SM3 Hash Function Instructions)", + [FeatureStdExtZve32x]>, RISCVExtensionBitmask<0, 58>; def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, AssemblerPredicate<(all_of FeatureStdExtZvksh), @@ -1039,7 +1048,7 @@ def FeatureStdExtSvpbmt def FeatureStdExtSvvptc : RISCVExtension<"svvptc", 1, 0, - "'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)">; + "'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)">; def FeatureStdExtSha : RISCVExtension<"sha", 1, 0, diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index 3d3a29c3e03530d99a813162e504469b631e2239..3a4cf399fd8c13c9c892e5b8e3d55dab3e769386 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -42,10 +42,19 @@ RISCVFrameLowering::RISCVFrameLowering(const RISCVSubtarget &STI) /*TransientStackAlignment=*/getABIStackAlignment(STI.getTargetABI())), STI(STI) {} +// The register used to hold the frame pointer. +static constexpr Register FPReg = RISCV::X8; + +// The register used to hold the stack pointer. +static constexpr Register SPReg = RISCV::X2; + +// The register used to hold the return address. +static constexpr Register RAReg = RISCV::X1; + // Offsets which need to be scale by XLen representing locations of CSRs which // are given a fixed location by save/restore libcalls or Zcmp Push/Pop. static const std::pair FixedCSRFIMap[] = { - {/*ra*/ RISCV::X1, -1}, {/*s0*/ RISCV::X8, -2}, + {/*ra*/ RAReg, -1}, {/*s0*/ FPReg, -2}, {/*s1*/ RISCV::X9, -3}, {/*s2*/ RISCV::X18, -4}, {/*s3*/ RISCV::X19, -5}, {/*s4*/ RISCV::X20, -6}, {/*s5*/ RISCV::X21, -7}, {/*s6*/ RISCV::X22, -8}, @@ -187,6 +196,7 @@ static int getLibCallID(const MachineFunction &MF, switch (MaxReg) { default: llvm_unreachable("Something has gone wrong!"); + // clang-format off case /*s11*/ RISCV::X27: return 12; case /*s10*/ RISCV::X26: return 11; case /*s9*/ RISCV::X25: return 10; @@ -198,8 +208,9 @@ static int getLibCallID(const MachineFunction &MF, case /*s3*/ RISCV::X19: return 4; case /*s2*/ RISCV::X18: return 3; case /*s1*/ RISCV::X9: return 2; - case /*s0*/ RISCV::X8: return 1; - case /*ra*/ RISCV::X1: return 0; + case /*s0*/ FPReg: return 1; + case /*ra*/ RAReg: return 0; + // clang-format on } } @@ -284,9 +295,9 @@ getPushPopEncodingAndNum(const Register MaxReg) { return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S2, 4); case RISCV::X9: /*s1*/ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S1, 3); - case RISCV::X8: /*s0*/ + case FPReg: /*s0*/ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0, 2); - case RISCV::X1: /*ra*/ + case RAReg: /*ra*/ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA, 1); } } @@ -372,12 +383,6 @@ uint64_t RISCVFrameLowering::getStackSizeWithRVVPadding( return alignTo(MFI.getStackSize() + RVFI->getRVVPadding(), getStackAlign()); } -// Returns the register used to hold the frame pointer. -static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; } - -// Returns the register used to hold the stack pointer. -static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; } - static SmallVector getUnmanagedCSI(const MachineFunction &MF, const std::vector &CSI) { @@ -415,8 +420,6 @@ void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF, MachineInstr::MIFlag Flag) const { assert(Amount != 0 && "Did not need to adjust stack pointer for RVV."); - const Register SPReg = getSPReg(STI); - // Optimize compile time offset case StackOffset Offset = StackOffset::getScalable(Amount); if (auto VLEN = STI.getRealVLen()) { @@ -479,7 +482,7 @@ static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true); Expr.push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg)); Expr.push_back(0); - if (Reg == RISCV::X2) + if (Reg == SPReg) Comment << "sp"; else Comment << printReg(Reg, &TRI); @@ -530,8 +533,6 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, const RISCVInstrInfo *TII = STI.getInstrInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); - Register FPReg = getFPReg(STI); - Register SPReg = getSPReg(STI); Register BPReg = RISCVABI::getBPReg(); // Debug location must be unknown since the first debug location is used @@ -784,8 +785,6 @@ void RISCVFrameLowering::deallocateStack(MachineFunction &MF, int64_t CFAOffset) const { const RISCVRegisterInfo *RI = STI.getRegisterInfo(); - Register SPReg = getSPReg(STI); - if (STI.hasEPI()) RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize), MachineInstr::FrameDestroy, getStackAlign(), RISCV::X7); @@ -799,8 +798,6 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF, const RISCVRegisterInfo *RI = STI.getRegisterInfo(); MachineFrameInfo &MFI = MF.getFrameInfo(); auto *RVFI = MF.getInfo(); - Register FPReg = getFPReg(STI); - Register SPReg = getSPReg(STI); // All calls are tail calls in GHC calling conv, and functions have no // prologue/epilogue. @@ -948,7 +945,7 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, } if (FI >= MinCSFI && FI <= MaxCSFI) { - FrameReg = RISCV::X2; + FrameReg = SPReg; if (FirstSPAdjustAmount) Offset += StackOffset::getFixed(FirstSPAdjustAmount); @@ -995,13 +992,13 @@ RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, } else { // VarSize objects must be empty in this case! assert(!MFI.hasVarSizedObjects()); - FrameReg = RISCV::X2; + FrameReg = SPReg; } } else { FrameReg = RI->getFrameRegister(MF); } - if (FrameReg == getFPReg(STI)) { + if (FrameReg == FPReg) { Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize()); // When using FP to access scalable vector objects, we need to minus // the frame size. @@ -1093,8 +1090,8 @@ void RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF, // Unconditionally spill RA and FP only if the function uses a frame // pointer. if (hasFP(MF)) { - SavedRegs.set(RISCV::X1); - SavedRegs.set(RISCV::X8); + SavedRegs.set(RAReg); + SavedRegs.set(FPReg); } // Mark BP as used if function has dedicated base pointer. if (hasBP(MF)) @@ -1159,23 +1156,23 @@ RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFunction &MF) const { uint64_t StackSize = Offset; - // Multiply by vscale. - if (ST.getRealMinVLen() >= RISCV::RVVBitsPerBlock) - StackSize *= ST.getRealMinVLen() / RISCV::RVVBitsPerBlock; - // Ensure the alignment of the RVV stack. Since we want the most-aligned // object right at the bottom (i.e., any padding at the top of the frame), // readjust all RVV objects down by the alignment padding. - if (auto AlignmentPadding = offsetToAlignment(StackSize, RVVStackAlign)) { - StackSize += AlignmentPadding; - for (int FI : ObjectsToAllocate) - MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding); + // Stack size and offsets are multiples of vscale, stack alignment is in + // bytes, we can divide stack alignment by minimum vscale to get a maximum + // stack alignment multiple of vscale. + auto VScale = + std::max(ST.getRealMinVLen() / RISCV::RVVBitsPerBlock, 1); + if (auto RVVStackAlignVScale = RVVStackAlign.value() / VScale) { + if (auto AlignmentPadding = + offsetToAlignment(StackSize, Align(RVVStackAlignVScale))) { + StackSize += AlignmentPadding; + for (int FI : ObjectsToAllocate) + MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding); + } } - // Remove vscale. - if (ST.getRealMinVLen() >= RISCV::RVVBitsPerBlock) - StackSize /= ST.getRealMinVLen() / RISCV::RVVBitsPerBlock; - return std::make_pair(StackSize, RVVStackAlign); } @@ -1363,7 +1360,6 @@ bool RISCVFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - Register SPReg = RISCV::X2; DebugLoc DL = MI->getDebugLoc(); if (!hasReservedCallFrame(MF)) { diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 7927d0d1623208b5074d4edf29731686fb05761b..26108e2a6a62bbe3e07bae10b58185cebdefb2a2 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -1068,7 +1068,7 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) { // The constants that can be encoded in the THeadMemIdx instructions // are of the form (sign_extend(imm5) << imm2). - int64_t Shift; + unsigned Shift; for (Shift = 0; Shift < 4; Shift++) if (isInt<5>(Offset >> Shift) && ((Offset % (1LL << Shift)) == 0)) break; @@ -3809,7 +3809,7 @@ bool RISCVDAGToDAGISel::selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2) { if (auto *C = dyn_cast(N)) { int64_t Offset = C->getSExtValue(); - int64_t Shift; + unsigned Shift; for (Shift = 0; Shift < 4; Shift++) if (isInt<5>(Offset >> Shift) && ((Offset % (1LL << Shift)) == 0)) break; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 972fee934bb0966d9273fca414f9786958ff9c3d..53a953f7a84f3b425483b92daa2a469d06ce810c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1482,7 +1482,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, } setOperationAction({ISD::BUILD_VECTOR, ISD::VECTOR_SHUFFLE, - ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT}, + ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, + ISD::SCALAR_TO_VECTOR}, VT, Custom); setOperationAction( @@ -3631,6 +3632,7 @@ static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) { case ISD::VP_FROUND: return RISCVFPRndMode::RMM; case ISD::FRINT: + case ISD::VP_FRINT: return RISCVFPRndMode::DYN; } @@ -3702,6 +3704,8 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG, switch (Op.getOpcode()) { default: llvm_unreachable("Unexpected opcode"); + case ISD::FRINT: + case ISD::VP_FRINT: case ISD::FCEIL: case ISD::VP_FCEIL: case ISD::FFLOOR: @@ -3721,10 +3725,6 @@ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(SDValue Op, SelectionDAG &DAG, Truncated = DAG.getNode(RISCVISD::VFCVT_RTZ_X_F_VL, DL, IntVT, Src, Mask, VL); break; - case ISD::FRINT: - case ISD::VP_FRINT: - Truncated = DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, IntVT, Src, Mask, VL); - break; case ISD::FNEARBYINT: case ISD::VP_FNEARBYINT: Truncated = DAG.getNode(RISCVISD::VFROUND_NOEXCEPT_VL, DL, ContainerVT, Src, @@ -3895,8 +3895,10 @@ static SDValue lowerVectorXRINT(SDValue Op, SelectionDAG &DAG, } auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); - SDValue Truncated = - DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, ContainerVT, Src, Mask, VL); + SDValue Truncated = DAG.getNode( + RISCVISD::VFCVT_RM_X_F_VL, DL, ContainerVT, Src, Mask, + DAG.getTargetConstant(RISCVFPRndMode::DYN, DL, Subtarget.getXLenVT()), + VL); if (!VT.isFixedLengthVector()) return Truncated; @@ -4594,10 +4596,9 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG, A = DAG.getNode(ISD::AND, SDLoc(A), XLenVT, A, Mask); B = DAG.getNode(ISD::AND, SDLoc(B), XLenVT, B, Mask); SDValue ShtAmt = DAG.getConstant(ElemSizeInBits, ElemDL, XLenVT); - SDNodeFlags Flags; - Flags.setDisjoint(true); return DAG.getNode(ISD::OR, ElemDL, XLenVT, A, - DAG.getNode(ISD::SHL, ElemDL, XLenVT, B, ShtAmt), Flags); + DAG.getNode(ISD::SHL, ElemDL, XLenVT, B, ShtAmt), + SDNodeFlags::Disjoint); }; SmallVector NewOperands; @@ -6626,11 +6627,8 @@ static SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG, SDValue ClearedSign = DAG.getNode(ISD::AND, DL, XLenVT, MagAsInt, ClearSignMask); - SDNodeFlags Flags; - Flags.setDisjoint(true); - - SDValue CopiedSign = - DAG.getNode(ISD::OR, DL, XLenVT, ClearedSign, SignBit, Flags); + SDValue CopiedSign = DAG.getNode(ISD::OR, DL, XLenVT, ClearedSign, SignBit, + SDNodeFlags::Disjoint); return DAG.getNode(RISCVISD::FMV_H_X, DL, VT, CopiedSign); } @@ -6774,7 +6772,7 @@ static unsigned getRISCVVLOp(SDValue Op) { case ISD::VP_LRINT: case ISD::LLRINT: case ISD::VP_LLRINT: - return RISCVISD::VFCVT_X_F_VL; + return RISCVISD::VFCVT_RM_X_F_VL; } // clang-format on #undef OP_CASE @@ -6787,7 +6785,7 @@ static bool hasPassthruOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == - 130 && + 128 && RISCVISD::LAST_RISCV_STRICTFP_OPCODE - ISD::FIRST_TARGET_STRICTFP_OPCODE == 21 && @@ -6813,7 +6811,7 @@ static bool hasMaskOp(unsigned Opcode) { Opcode <= RISCVISD::LAST_RISCV_STRICTFP_OPCODE && "not a RISC-V target specific op"); static_assert(RISCVISD::LAST_VL_VECTOR_OP - RISCVISD::FIRST_VL_VECTOR_OP == - 130 && + 128 && RISCVISD::LAST_RISCV_STRICTFP_OPCODE - ISD::FIRST_TARGET_STRICTFP_OPCODE == 21 && @@ -7185,9 +7183,16 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op, if (VT.isFixedLengthVector()) ContainerVT = getContainerForFixedLengthVector(VT); SDValue VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second; - Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), Scalar); - SDValue V = DAG.getNode(RISCVISD::VMV_S_X_VL, DL, ContainerVT, - DAG.getUNDEF(ContainerVT), Scalar, VL); + + SDValue V; + if (VT.isFloatingPoint()) { + V = DAG.getNode(RISCVISD::VFMV_S_F_VL, DL, ContainerVT, + DAG.getUNDEF(ContainerVT), Scalar, VL); + } else { + Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), Scalar); + V = DAG.getNode(RISCVISD::VMV_S_X_VL, DL, ContainerVT, + DAG.getUNDEF(ContainerVT), Scalar, VL); + } if (VT.isFixedLengthVector()) V = convertFromScalableVector(VT, V, DAG, Subtarget); return V; @@ -13042,6 +13047,11 @@ SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const { } } } + // VFCVT_RM_X_F_VL requires a rounding mode to be injected before the VL. + if (RISCVISDOpc == RISCVISD::VFCVT_RM_X_F_VL && + ISD::getVPExplicitVectorLengthIdx(Op.getOpcode()) == OpIdx.index()) + Ops.push_back(DAG.getTargetConstant(RISCVFPRndMode::DYN, DL, + Subtarget.getXLenVT())); // Pass through operands which aren't fixed-length vectors. if (!V.getValueType().isFixedLengthVector()) { Ops.push_back(V); @@ -15132,9 +15142,8 @@ combineBinOpOfExtractToReduceTree(SDNode *N, SelectionDAG &DAG, EVT ReduceVT = EVT::getVectorVT(*DAG.getContext(), VT, RHSIdx + 1); SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec, DAG.getVectorIdxConstant(0, DL)); - auto Flags = ReduceVec->getFlags(); - Flags.intersectWith(N->getFlags()); - return DAG.getNode(ReduceOpc, DL, VT, Vec, Flags); + return DAG.getNode(ReduceOpc, DL, VT, Vec, + ReduceVec->getFlags() & N->getFlags()); } return SDValue(); @@ -17572,10 +17581,6 @@ static SDValue performFP_TO_INTCombine(SDNode *N, unsigned Opc = IsSigned ? RISCVISD::VFCVT_RTZ_X_F_VL : RISCVISD::VFCVT_RTZ_XU_F_VL; FpToInt = DAG.getNode(Opc, DL, ContainerVT, XVal, Mask, VL); - } else if (FRM == RISCVFPRndMode::DYN) { - unsigned Opc = - IsSigned ? RISCVISD::VFCVT_X_F_VL : RISCVISD::VFCVT_XU_F_VL; - FpToInt = DAG.getNode(Opc, DL, ContainerVT, XVal, Mask, VL); } else { unsigned Opc = IsSigned ? RISCVISD::VFCVT_RM_X_F_VL : RISCVISD::VFCVT_RM_XU_F_VL; @@ -22553,8 +22558,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(VFCVT_RTZ_XU_F_VL) NODE_NAME_CASE(VFCVT_RM_X_F_VL) NODE_NAME_CASE(VFCVT_RM_XU_F_VL) - NODE_NAME_CASE(VFCVT_X_F_VL) - NODE_NAME_CASE(VFCVT_XU_F_VL) NODE_NAME_CASE(VFROUND_NOEXCEPT_VL) NODE_NAME_CASE(SINT_TO_FP_VL) NODE_NAME_CASE(UINT_TO_FP_VL) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 49d38f57121034e0cb9bfbe0479f12956087edbc..a2fbc8be6cdbb31ce12b8038f2a01a3b4b23ef0e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -357,8 +357,6 @@ enum NodeType : unsigned { FCOPYSIGN_VL, // Has a passthru operand VFCVT_RTZ_X_F_VL, VFCVT_RTZ_XU_F_VL, - VFCVT_X_F_VL, - VFCVT_XU_F_VL, VFROUND_NOEXCEPT_VL, VFCVT_RM_X_F_VL, // Has a rounding mode operand. VFCVT_RM_XU_F_VL, // Has a rounding mode operand. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index fed4b01090a170020c2907afa36a51df2750112a..5a9f2bc0eda2e47722c88e73dc2acd668decf3f5 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2624,6 +2624,28 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_SPIMM: Ok = (Imm & 0xf) == 0; break; + case RISCVOp::OPERAND_FRMARG: + Ok = RISCVFPRndMode::isValidRoundingMode(Imm); + break; + case RISCVOp::OPERAND_RTZARG: + Ok = Imm == RISCVFPRndMode::RTZ; + break; + case RISCVOp::OPERAND_COND_CODE: + Ok = Imm >= 0 && Imm < RISCVCC::COND_INVALID; + break; + case RISCVOp::OPERAND_VEC_POLICY: + Ok = (Imm & (RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC)) == Imm; + break; + case RISCVOp::OPERAND_SEW: + Ok = Imm == 0 || (Imm >= 3 && Imm <= 6); + break; + case RISCVOp::OPERAND_VEC_RM: + assert(RISCVII::hasRoundModeOp(Desc.TSFlags)); + if (RISCVII::usesVXRM(Desc.TSFlags)) + Ok = isUInt<2>(Imm); + else + Ok = RISCVFPRndMode::isValidRoundingMode(Imm); + break; } if (!Ok) { ErrInfo = "Invalid immediate"; @@ -2696,6 +2718,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, } } + if (int Idx = RISCVII::getFRMOpNum(Desc); + Idx >= 0 && MI.getOperand(Idx).getImm() == RISCVFPRndMode::DYN && + !MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { + ErrInfo = "dynamic rounding mode should read FRM"; + return false; + } + return true; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 0afdf00182f8bfaaa785b29b7d8d3cf2985784b8..5d81086b708223ba4ef36fe42605fa0c9d37e417 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -387,6 +387,11 @@ def csr_sysreg : RISCVOp, TImmLeaf(Imm);"> { // A parameterized register class alternative to i32imm/i64imm from Target.td. def ixlenimm : Operand; +// Condition code used by select and short forward branch pseudos. +def cond_code : RISCVOp { + let OperandType = "OPERAND_COND_CODE"; +} + def ixlenimm_li : Operand { let ParserMatchClass = ImmXLenAsmOperand<"", "LI">; } @@ -1450,7 +1455,7 @@ def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc, multiclass SelectCC_GPR_rrirr { let usesCustomInserter = 1 in def _Using_CC_GPR : Pseudo<(outs valty:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, valty:$truev, valty:$falsev), [(set valty:$dst, (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), GPR:$rhs, cond, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index 4c58af0b379add5ad550ad3d6eaeff1ff9c43763..e5fc2e41f58c435a6fb8b7757cddac5d5a9d7dd7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -134,6 +134,8 @@ def frmarg : Operand { let ParserMatchClass = FRMArg; let PrintMethod = "printFRMArg"; let DecoderMethod = "decodeFRMArg"; + let OperandType = "OPERAND_FRMARG"; + let OperandNamespace = "RISCVOp"; } // Variants of the rounding mode operand that default to 'rne'. This is used @@ -154,6 +156,8 @@ def frmarglegacy : Operand { let ParserMatchClass = FRMArgLegacy; let PrintMethod = "printFRMArgLegacy"; let DecoderMethod = "decodeFRMArg"; + let OperandType = "OPERAND_FRMARG"; + let OperandNamespace = "RISCVOp"; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td index f25dc7302608baf613c8b6eb9bcb1b86b0880b1a..16cc0e5a61f0bc347fb6ee2eb7f5df9c6c9421a9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td @@ -15,7 +15,7 @@ let Predicates = [HasShortForwardBranchOpt], isSelect = 1, // This instruction moves $truev to $dst when the condition is true. It will // be expanded to control flow in RISCVExpandPseudoInsts. def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$truev), [(set GPR:$dst, (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), @@ -34,7 +34,7 @@ let Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt], // be expanded to control flow in RISCVExpandPseudoInsts. // We use GPRNoX0 because c.mv cannot encode X0. def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPRNoX0:$falsev, GPRNoX0:$truev), [(set GPRNoX0:$dst, (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), @@ -51,143 +51,143 @@ def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst), let Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in { def PseudoCCADD : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSUB : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSLL : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRL : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRA : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCAND : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCXOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCADDI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSLLI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRLI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRAI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCANDI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCORI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCXORI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; // RV64I instructions def PseudoCCADDW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSUBW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSLLW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRLW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRAW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCADDIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSLLIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRLIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCSRAIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; // Zbb/Zbkb instructions def PseudoCCANDN : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCORN : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; def PseudoCCXNOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + (ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU, ReadSFBALU]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index e273ac160f6dd15cc2e9a7427f5296300d2178da..aec496534f5441425eb1df5fb49f7a4f2b5905db 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -104,13 +104,28 @@ class SchedCommon writes, list reads, string mx = "WorstCase", int sew = 0, bit forceMasked = 0, bit forcePassthruRead = 0> : Sched<[]> { defvar isMasked = !ne(!find(NAME, "_MASK"), -1); + defvar isTied = !ne(!find(NAME, "_TIED"), -1); defvar isMaskedOrForceMasked = !or(forceMasked, isMasked); + defvar isTiedMasked = !and(isMaskedOrForceMasked, isTied); defvar passthruRead = !if(!or(!eq(mx, "WorstCase"), !eq(sew, 0)), !cast("ReadVPassthru_" # mx), !cast("ReadVPassthru_" # mx # "_E" #sew)); - defvar needsPassthruRead = !or(isMaskedOrForceMasked, forcePassthruRead); + // We don't need passthru operand if it's already _TIED without mask. + defvar needsForcePassthruRead = !and(forcePassthruRead, !not(isTied)); + defvar needsPassthruRead = !or(isMaskedOrForceMasked, needsForcePassthruRead); + // If this is a _TIED + masked operation, $rs2 (i.e. the first operand) is + // merged with the mask. + // NOTE: the following if statement is written in such a weird way because + // should we want to write something like + // `!if(!and(!not(!empty(reads), isTiedMasked), !tail(reads), reads)` + // since `!if` doesn't have a proper short-circuit behavior, if the + // condition of this `!if` cannot be resolved right away, `!tail(reads)` will + // be immediately evaluated anyway even when `reads` is empty, which leads to + // an assertion failure. + defvar readsWithTiedMask = + !if(isTiedMasked, !if(!not(!empty(reads)), !tail(reads), reads), reads); defvar readsWithMask = - !if(isMaskedOrForceMasked, !listconcat(reads, [ReadVMask]), reads); + !if(isMaskedOrForceMasked, !listconcat(readsWithTiedMask, [ReadVMask]), reads); defvar allReads = !if(needsPassthruRead, !listconcat([passthruRead], readsWithMask), reads); let SchedRW = !listconcat(writes, allReads); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index af4f653f57afd5a280b6128ef1ad4761d70e2d63..57460425e338e908fa5b10fb88d8406cc867bfda 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -84,6 +84,18 @@ def AVL : RegisterOperand { let OperandType = "OPERAND_AVL"; } +def vec_policy : RISCVOp { + let OperandType = "OPERAND_VEC_POLICY"; +} + +def sew : RISCVOp { + let OperandType = "OPERAND_SEW"; +} + +def vec_rm : RISCVOp { + let OperandType = "OPERAND_VEC_RM"; +} + // X0 has special meaning for vsetvl/vsetvli. // rd | rs1 | AVL value | Effect on vl //-------------------------------------------------------------- @@ -764,8 +776,8 @@ class GetVTypePredicates { class VPseudoUSLoadNoMask : Pseudo<(outs RetClass:$rd), - (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -782,7 +794,7 @@ class VPseudoUSLoadMask.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -799,7 +811,7 @@ class VPseudoUSLoadFFNoMask : Pseudo<(outs RetClass:$rd, GPR:$vl), (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -816,7 +828,7 @@ class VPseudoUSLoadFFMask.R:$rd, GPR:$vl), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -833,7 +845,7 @@ class VPseudoSLoadNoMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -850,7 +862,7 @@ class VPseudoSLoadMask.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, GPR:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLE { let mayLoad = 1; @@ -869,10 +881,10 @@ class VPseudoILoadNoMask LMUL, bit Ordered, bit EarlyClobber, - int TargetConstraintType = 1> : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLX { let mayLoad = 1; @@ -891,11 +903,11 @@ class VPseudoILoadMask LMUL, bit Ordered, bit EarlyClobber, - int TargetConstraintType = 1> : + bits<2> TargetConstraintType = 1> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, IdxClass:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLX { let mayLoad = 1; @@ -912,7 +924,7 @@ class VPseudoILoadMask : Pseudo<(outs), - (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>, + (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSE { let mayLoad = 0; @@ -926,7 +938,7 @@ class VPseudoUSStoreMask : Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSE { let mayLoad = 0; @@ -940,7 +952,7 @@ class VPseudoSStoreNoMask : Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSE { let mayLoad = 0; @@ -954,7 +966,7 @@ class VPseudoSStoreMask : Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSE { let mayLoad = 0; @@ -967,7 +979,7 @@ class VPseudoSStoreMask : Pseudo<(outs RegClass:$rd), (ins RegClass:$passthru, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -981,7 +993,7 @@ class VPseudoNullaryNoMask : class VPseudoNullaryMask : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -996,7 +1008,7 @@ class VPseudoNullaryMask : // Nullary for pseudo instructions. They are expanded in // RISCVExpandPseudoInsts pass. class VPseudoNullaryPseudoM : - Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>, + Pseudo<(outs VR:$rd), (ins AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1013,10 +1025,10 @@ class VPseudoNullaryPseudoM : class VPseudoUnaryNoMask : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, OpClass:$rs2, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1031,9 +1043,9 @@ class VPseudoUnaryNoMask : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), - (ins OpClass:$rs2, AVL:$vl, ixlenimm:$sew), []>, + (ins OpClass:$rs2, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1047,10 +1059,10 @@ class VPseudoUnaryNoMaskNoPolicy : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1062,15 +1074,16 @@ class VPseudoUnaryNoMaskRoundingMode : + bits<2> TargetConstraintType = 1> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1086,11 +1099,11 @@ class VPseudoUnaryMask : + bits<2> TargetConstraintType = 1> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1103,6 +1116,7 @@ class VPseudoUnaryMaskRoundingMode : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> { + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1122,49 +1136,9 @@ class VPseudoUnaryMask_NoExcept : - Pseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, OpClass:$rs2, ixlenimm:$frm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, - RISCVVPseudo { - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; - let Constraints = !interleave([Constraint, "$rd = $passthru"], ","); - let TargetOverlapConstraintType = TargetConstraintType; - let HasVLOp = 1; - let HasSEWOp = 1; - let HasVecPolicyOp = 1; - let HasRoundModeOp = 1; -} - -class VPseudoUnaryMask_FRM : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, ixlenimm:$frm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, - RISCVVPseudo { - let mayLoad = 0; - let mayStore = 0; - let hasSideEffects = 0; - let Constraints = !interleave([Constraint, "$rd = $passthru"], ","); - let TargetOverlapConstraintType = TargetConstraintType; - let HasVLOp = 1; - let HasSEWOp = 1; - let HasVecPolicyOp = 1; - let UsesMaskPolicy = 1; - let HasRoundModeOp = 1; -} - class VPseudoUnaryNoMaskGPROut : Pseudo<(outs GPR:$rd), - (ins VR:$rs2, AVL:$vl, ixlenimm:$sew), []>, + (ins VR:$rs2, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1175,7 +1149,7 @@ class VPseudoUnaryNoMaskGPROut : class VPseudoUnaryMaskGPROut : Pseudo<(outs GPR:$rd), - (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1189,7 +1163,7 @@ class VPseudoUnaryAnyMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, - VR:$vm, AVL:$vl, ixlenimm:$sew), []>, + VR:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1203,9 +1177,9 @@ class VPseudoBinaryNoMask : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), - (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>, + (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1220,10 +1194,10 @@ class VPseudoBinaryNoMaskPolicy : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1239,11 +1213,11 @@ class VPseudoBinaryNoMaskRoundingMode : + bit UsesVXRM_ = 1, + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1254,19 +1228,20 @@ class VPseudoBinaryNoMaskRoundingMode : + bit UsesVXRM_, + bits<2> TargetConstraintType = 1> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, ixlenimm:$rm, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, vec_rm:$rm, AVL:$vl, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1278,6 +1253,7 @@ class VPseudoBinaryMaskPolicyRoundingMode : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), - (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1306,12 +1282,12 @@ class VPseudoTiedBinaryNoMask : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), (ins RetClass:$rs2, Op2Class:$rs1, - ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + vec_rm:$rm, + AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1325,13 +1301,14 @@ class VPseudoTiedBinaryNoMaskRoundingMode LMUL, bit Ordered>: Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, - ixlenimm:$sew),[]>, + sew:$sew),[]>, RISCVVPseudo, RISCVVSX { let mayLoad = 0; @@ -1345,7 +1322,7 @@ class VPseudoIStoreMask LMUL, bit Ordered>: Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, + VMaskOp:$vm, AVL:$vl, sew:$sew),[]>, RISCVVPseudo, RISCVVSX { let mayLoad = 0; @@ -1359,11 +1336,11 @@ class VPseudoBinaryMaskPolicy : + bits<2> TargetConstraintType = 1> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1382,7 +1359,7 @@ class VPseudoTernaryMaskPolicy.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1400,8 +1377,8 @@ class VPseudoTernaryMaskPolicyRoundingMode.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, VMaskOp:$vm, - ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1412,6 +1389,7 @@ class VPseudoTernaryMaskPolicyRoundingMode : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1441,11 +1419,11 @@ class VPseudoBinaryMOutMask : + bits<2> TargetConstraintType = 1> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1462,13 +1440,13 @@ class VPseudoTiedBinaryMask : + bits<2> TargetConstraintType = 1> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op2Class:$rs1, VMaskOp:$vm, - ixlenimm:$rm, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1482,6 +1460,7 @@ class VPseudoTiedBinaryMaskRoundingMode : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), !if(CarryIn, (ins Op1Class:$rs2, Op2Class:$rs1, - VMV0:$carry, AVL:$vl, ixlenimm:$sew), + VMV0:$carry, AVL:$vl, sew:$sew), (ins Op1Class:$rs2, Op2Class:$rs1, - AVL:$vl, ixlenimm:$sew)), []>, + AVL:$vl, sew:$sew)), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1512,10 +1491,10 @@ class VPseudoTiedBinaryCarryIn : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMV0:$carry, AVL:$vl, ixlenimm:$sew), []>, + VMV0:$carry, AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1534,7 +1513,7 @@ class VPseudoTernaryNoMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1548,10 +1527,10 @@ class VPseudoTernaryNoMaskWithPolicy : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1567,10 +1546,10 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode : + bits<2> TargetConstraintType = 1> : Pseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - ixlenimm:$rm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1582,6 +1561,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode NF> : Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1606,7 +1586,7 @@ class VPseudoUSSegLoadMask NF> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1624,7 +1604,7 @@ class VPseudoUSSegLoadFFNoMask NF> : Pseudo<(outs RetClass:$rd, GPR:$vl), (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1641,7 +1621,7 @@ class VPseudoUSSegLoadFFMask NF> : Pseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy), []>, + VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1659,7 +1639,7 @@ class VPseudoSSegLoadNoMask NF> : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, GPRMem:$rs1, GPR:$offset, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1676,8 +1656,8 @@ class VPseudoSSegLoadMask NF> : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; @@ -1698,7 +1678,7 @@ class VPseudoISegLoadNoMask : Pseudo<(outs RetClass:$rd), (ins RetClass:$passthru, GPRMem:$rs1, IdxClass:$offset, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), []>, + sew:$sew, vec_policy:$policy), []>, RISCVVPseudo, RISCVVLXSEG { let mayLoad = 1; @@ -1720,8 +1700,8 @@ class VPseudoISegLoadMask : Pseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMem:$rs1, - IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, - ixlenimm:$policy), []>, + IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVPseudo, RISCVVLXSEG { let mayLoad = 1; @@ -1740,7 +1720,7 @@ class VPseudoUSSegStoreNoMask NF> : Pseudo<(outs), - (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew), []>, + (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; @@ -1755,7 +1735,7 @@ class VPseudoUSSegStoreMask NF> : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; @@ -1770,7 +1750,7 @@ class VPseudoSSegStoreNoMask NF> : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, GPR:$offset, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; @@ -1785,7 +1765,7 @@ class VPseudoSSegStoreMask NF> : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, GPR: $offset, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; @@ -1803,7 +1783,7 @@ class VPseudoISegStoreNoMask : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSXSEG { let mayLoad = 0; @@ -1821,7 +1801,7 @@ class VPseudoISegStoreMask : Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index, - VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVPseudo, RISCVVSXSEG { let mayLoad = 0; @@ -2097,7 +2077,7 @@ multiclass VPseudoBinary TargetConstraintType = 1, bit Commutable = 0> { let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); @@ -2115,8 +2095,8 @@ multiclass VPseudoBinaryRoundingMode TargetConstraintType = 1, bit Commutable = 0> { let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); @@ -2139,7 +2119,7 @@ multiclass VPseudoBinaryM TargetConstraintType = 1, bit Commutable = 0> { let VLMul = MInfo.value, isCommutable = Commutable in { def "_" # MInfo.MX : VPseudoBinaryNoMask { + bits<2> TargetConstraintType = 1> { let VLMul = MInfo.value in { def "_" # MInfo.MX # "_TIED": VPseudoTiedBinaryNoMask; @@ -2187,7 +2167,7 @@ multiclass VPseudoTiedBinaryRoundingMode { + bits<2> TargetConstraintType = 1> { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); let VLMul = MInfo.value in { def suffix # "_TIED": @@ -2409,7 +2389,7 @@ multiclass VPseudoBinaryV_WI_RM { multiclass VPseudoBinaryV_VM { + bits<2> TargetConstraintType = 1> { let isCommutable = Commutable in def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX : VPseudoBinaryCarry { } multiclass VPseudoBinaryV_XM { + string Constraint = "", bits<2> TargetConstraintType = 1> { def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX : VPseudoBinaryCarry { + string Constraint = "", bits<2> TargetConstraintType = 1> { def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX : VPseudoBinaryCarry TargetConstraintType = 1, bit Commutable = 0> { defm _VV : VPseudoBinaryM; } -multiclass VPseudoBinaryM_VX { +multiclass VPseudoBinaryM_VX TargetConstraintType = 1> { defm "_VX" : VPseudoBinaryM; } -multiclass VPseudoBinaryM_VF { +multiclass VPseudoBinaryM_VF TargetConstraintType = 1> { defm "_V" # f.FX : VPseudoBinaryM; } -multiclass VPseudoBinaryM_VI { +multiclass VPseudoBinaryM_VI TargetConstraintType = 1> { defm _VI : VPseudoBinaryM; } @@ -3194,7 +3174,7 @@ multiclass VPseudoTernaryWithPolicy { + bits<2> TargetConstraintType = 1> { let VLMul = MInfo.value in { let isCommutable = Commutable in def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy; @@ -3210,7 +3190,7 @@ multiclass VPseudoTernaryWithPolicyRoundingMode { + bits<2> TargetConstraintType = 1> { let VLMul = MInfo.value in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); let isCommutable = Commutable in @@ -3540,7 +3520,7 @@ multiclass VPseudoConversion { + bits<2> TargetConstraintType = 1> { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); let VLMul = MInfo.value, SEW=sew in { def suffix : VPseudoUnaryNoMask; @@ -3555,7 +3535,7 @@ multiclass VPseudoConversionRoundingMode { + bits<2> TargetConstraintType = 1> { let VLMul = MInfo.value, SEW=sew in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); def suffix : VPseudoUnaryNoMaskRoundingMode; @@ -3566,23 +3546,6 @@ multiclass VPseudoConversionRoundingMode { - let VLMul = MInfo.value, SEW=sew in { - defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); - def suffix : VPseudoUnaryNoMask_FRM; - def suffix # "_MASK" : VPseudoUnaryMask_FRM, - RISCVMaskedPseudo; - } -} - multiclass VPseudoConversionNoExcept, - SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX, - forcePassthruRead=true>; - } -} - multiclass VPseudoVFROUND_NOEXCEPT_V { foreach m = MxListF in { defm _V : VPseudoConversionNoExcept, @@ -3633,15 +3588,6 @@ multiclass VPseudoVCVTF_V_RM { } } -multiclass VPseudoVCVTF_RM_V { - foreach m = MxListF in { - foreach e = SchedSEWSet.val in - defm _V : VPseudoConversionRM, - SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e, - forcePassthruRead=true>; - } -} - multiclass VPseudoVWCVTI_V { defvar constraint = "@earlyclobber $rd"; foreach m = MxListFW in { @@ -3660,15 +3606,6 @@ multiclass VPseudoVWCVTI_V_RM { } } -multiclass VPseudoVWCVTI_RM_V { - defvar constraint = "@earlyclobber $rd"; - foreach m = MxListFW in { - defm _V : VPseudoConversionRM, - SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX, - forcePassthruRead=true>; - } -} - multiclass VPseudoVWCVTF_V { defvar constraint = "@earlyclobber $rd"; foreach m = MxListW in { @@ -3709,15 +3646,6 @@ multiclass VPseudoVNCVTI_W_RM { } } -multiclass VPseudoVNCVTI_RM_W { - defvar constraint = "@earlyclobber $rd"; - foreach m = MxListW in { - defm _W : VPseudoConversionRM, - SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX, - forcePassthruRead=true>; - } -} - multiclass VPseudoVNCVTF_W_RM { defvar constraint = "@earlyclobber $rd"; foreach m = MxListFW in { @@ -3730,17 +3658,6 @@ multiclass VPseudoVNCVTF_W_RM { } } -multiclass VPseudoVNCVTF_RM_W { - defvar constraint = "@earlyclobber $rd"; - foreach m = MxListFW in { - foreach e = SchedSEWSet.val in - defm _W : VPseudoConversionRM, - SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e, - forcePassthruRead=true>; - } -} - multiclass VPseudoVNCVTD_W { defvar constraint = "@earlyclobber $rd"; foreach m = MxListFW in { @@ -6443,7 +6360,7 @@ let Predicates = [HasVInstructionsAnyF] in { //===----------------------------------------------------------------------===// // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasPostISelHook = 1 in { +let mayRaiseFPException = true in { defm PseudoVFADD : VPseudoVALU_VV_VF_RM; defm PseudoVFSUB : VPseudoVALU_VV_VF_RM; defm PseudoVFRSUB : VPseudoVALU_VF_RM; @@ -6452,7 +6369,7 @@ defm PseudoVFRSUB : VPseudoVALU_VF_RM; //===----------------------------------------------------------------------===// // 13.3. Vector Widening Floating-Point Add/Subtract Instructions //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { +let mayRaiseFPException = true, hasSideEffects = 0 in { defm PseudoVFWADD : VPseudoVFWALU_VV_VF_RM; defm PseudoVFWSUB : VPseudoVFWALU_VV_VF_RM; defm PseudoVFWADD : VPseudoVFWALU_WV_WF_RM; @@ -6462,7 +6379,7 @@ defm PseudoVFWSUB : VPseudoVFWALU_WV_WF_RM; //===----------------------------------------------------------------------===// // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { +let mayRaiseFPException = true, hasSideEffects = 0 in { defm PseudoVFMUL : VPseudoVFMUL_VV_VF_RM; defm PseudoVFDIV : VPseudoVFDIV_VV_VF_RM; defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM; @@ -6478,7 +6395,7 @@ defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM; //===----------------------------------------------------------------------===// // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { +let mayRaiseFPException = true, hasSideEffects = 0 in { defm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA_RM; defm PseudoVFNMACC : VPseudoVMAC_VV_VF_AAXA_RM; defm PseudoVFMSAC : VPseudoVMAC_VV_VF_AAXA_RM; @@ -6492,7 +6409,7 @@ defm PseudoVFNMSUB : VPseudoVMAC_VV_VF_AAXA_RM; //===----------------------------------------------------------------------===// // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { +let mayRaiseFPException = true, hasSideEffects = 0 in { defm PseudoVFWMACC : VPseudoVWMAC_VV_VF_RM; defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF_RM; defm PseudoVFWMSAC : VPseudoVWMAC_VV_VF_RM; @@ -6566,36 +6483,29 @@ defm PseudoVFMV_V : VPseudoVMV_F; // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// let mayRaiseFPException = true in { -let hasSideEffects = 0, hasPostISelHook = 1 in { +let hasSideEffects = 0 in { defm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM; defm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM; } -defm PseudoVFCVT_RM_XU_F : VPseudoVCVTI_RM_V; -defm PseudoVFCVT_RM_X_F : VPseudoVCVTI_RM_V; - defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V; defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V; defm PseudoVFROUND_NOEXCEPT : VPseudoVFROUND_NOEXCEPT_V; -let hasSideEffects = 0, hasPostISelHook = 1 in { +let hasSideEffects = 0 in { defm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM; defm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM; } -defm PseudoVFCVT_RM_F_XU : VPseudoVCVTF_RM_V; -defm PseudoVFCVT_RM_F_X : VPseudoVCVTF_RM_V; } // mayRaiseFPException = true //===----------------------------------------------------------------------===// // 13.18. Widening Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// let mayRaiseFPException = true in { -let hasSideEffects = 0, hasPostISelHook = 1 in { +let hasSideEffects = 0 in { defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM; defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM; } -defm PseudoVFWCVT_RM_XU_F : VPseudoVWCVTI_RM_V; -defm PseudoVFWCVT_RM_X_F : VPseudoVWCVTI_RM_V; defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V; defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V; @@ -6611,26 +6521,23 @@ defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V; // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions //===----------------------------------------------------------------------===// let mayRaiseFPException = true in { -let hasSideEffects = 0, hasPostISelHook = 1 in { +let hasSideEffects = 0 in { defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM; defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM; } -defm PseudoVFNCVT_RM_XU_F : VPseudoVNCVTI_RM_W; -defm PseudoVFNCVT_RM_X_F : VPseudoVNCVTI_RM_W; defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W; defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W; -let hasSideEffects = 0, hasPostISelHook = 1 in { +let hasSideEffects = 0 in { defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM; defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM; } -defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W; -defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W; -let hasSideEffects = 0, hasPostISelHook = 1 in +let hasSideEffects = 0 in { defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM; defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM; +} defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W; } // mayRaiseFPException = true @@ -6666,8 +6573,7 @@ let Predicates = [HasVInstructionsAnyF] in { //===----------------------------------------------------------------------===// // 14.3. Vector Single-Width Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, - hasSideEffects = 0 in { +let mayRaiseFPException = true, hasSideEffects = 0 in { defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM; defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM; } @@ -6679,9 +6585,7 @@ defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS; //===----------------------------------------------------------------------===// // 14.4. Vector Widening Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// -let IsRVVWideningReduction = 1, - hasSideEffects = 0, - mayRaiseFPException = true in { +let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true in { defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM; defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM; } @@ -6762,13 +6666,13 @@ let Predicates = [HasVInstructions] in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let HasSEWOp = 1, BaseInstr = VMV_X_S in def PseudoVMV_X_S: - Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>, + Pseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>, Sched<[WriteVMovXS, ReadVMovXS]>, RISCVVPseudo; let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1, Constraints = "$rd = $rs1" in def PseudoVMV_S_X: Pseudo<(outs VR:$rd), - (ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew), + (ins VR:$rs1, GPR:$rs2, AVL:$vl, sew:$sew), []>, Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>, RISCVVPseudo; @@ -6785,14 +6689,14 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let HasSEWOp = 1, BaseInstr = VFMV_F_S in def "PseudoVFMV_" # f.FX # "_S" : Pseudo<(outs f.fprclass:$rd), - (ins VR:$rs2, ixlenimm:$sew), []>, + (ins VR:$rs2, sew:$sew), []>, Sched<[WriteVMovFS, ReadVMovFS]>, RISCVVPseudo; let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1, Constraints = "$rd = $rs1" in def "PseudoVFMV_S_" # f.FX : Pseudo<(outs VR:$rd), - (ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, ixlenimm:$sew), + (ins VR:$rs1, f.fprclass:$rs2, AVL:$vl, sew:$sew), []>, Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>, RISCVVPseudo; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td index 18749f00a10a52ff108d81173ad8b07a4a95c1b9..9d434cef5a96f11ea39c7f2e79901a32346e247a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -270,8 +270,6 @@ def SDT_RISCVSETCCOP_VL : SDTypeProfile<1, 6, [ SDTCisSameAs<0, 5>, SDTCisVT<6, XLenVT>]>; // Float -> Int -def riscv_vfcvt_xu_f_vl : SDNode<"RISCVISD::VFCVT_XU_F_VL", SDT_RISCVFP2IOp_VL>; -def riscv_vfcvt_x_f_vl : SDNode<"RISCVISD::VFCVT_X_F_VL", SDT_RISCVFP2IOp_VL>; def riscv_vfcvt_rm_xu_f_vl : SDNode<"RISCVISD::VFCVT_RM_XU_F_VL", SDT_RISCVFP2IOp_RM_VL>; def riscv_vfcvt_rm_x_f_vl : SDNode<"RISCVISD::VFCVT_RM_X_F_VL", SDT_RISCVFP2IOp_RM_VL>; @@ -1206,24 +1204,6 @@ multiclass VPatConvertFP2IVL_V { } } -multiclass VPatConvertFP2IVL_V_RM { - foreach fvti = AllFloatVectors in { - defvar ivti = GetIntVTypeInfo.Vti; - let Predicates = !listconcat(GetVTypePredicates.Predicates, - GetVTypePredicates.Predicates) in - def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), - (fvti.Mask V0), - VLOpFrag)), - (!cast(instruction_name#"_"#ivti.LMul.MX#"_MASK") - (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, - (fvti.Mask V0), - // Value to indicate no rounding mode change in - // RISCVInsertReadWriteCSR - FRM_DYN, - GPR:$vl, ivti.Log2SEW, TA_MA)>; - } -} - multiclass VPatConvertFP2I_RM_VL_V { foreach fvti = AllFloatVectors in { @@ -1289,25 +1269,6 @@ multiclass VPatWConvertFP2IVL_V } } -multiclass VPatWConvertFP2IVL_V_RM { - foreach fvtiToFWti = AllWidenableFloatVectors in { - defvar fvti = fvtiToFWti.Vti; - defvar iwti = GetIntVTypeInfo.Vti; - let Predicates = !listconcat(GetVTypePredicates.Predicates, - GetVTypePredicates.Predicates) in - def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), - (fvti.Mask V0), - VLOpFrag)), - (!cast(instruction_name#"_"#fvti.LMul.MX#"_MASK") - (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, - (fvti.Mask V0), - // Value to indicate no rounding mode change in - // RISCVInsertReadWriteCSR - FRM_DYN, - GPR:$vl, fvti.Log2SEW, TA_MA)>; - } -} - multiclass VPatWConvertFP2I_RM_VL_V { foreach fvtiToFWti = AllWidenableFloatVectors in { @@ -1361,28 +1322,6 @@ multiclass VPatNConvertFP2IVL_W { - // Reuse the same list of types used in the widening nodes, but just swap the - // direction of types around so we're converting from Wti -> Vti - foreach vtiToWti = AllWidenableIntToFloatVectors in { - defvar vti = vtiToWti.Vti; - defvar fwti = vtiToWti.Wti; - let Predicates = !listconcat(GetVTypePredicates.Predicates, - GetVTypePredicates.Predicates) in - def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), - (fwti.Mask V0), - VLOpFrag)), - (!cast(instruction_name#"_"#vti.LMul.MX#"_MASK") - (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, - (fwti.Mask V0), - // Value to indicate no rounding mode change in - // RISCVInsertReadWriteCSR - FRM_DYN, - GPR:$vl, vti.Log2SEW, TA_MA)>; - } -} - multiclass VPatNConvertFP2I_RM_VL_W { foreach vtiToWti = AllWidenableIntToFloatVectors in { defvar vti = vtiToWti.Vti; @@ -2637,10 +2576,8 @@ foreach fvti = AllFloatVectors in { } // 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions -defm : VPatConvertFP2IVL_V_RM; -defm : VPatConvertFP2IVL_V_RM; -defm : VPatConvertFP2I_RM_VL_V; -defm : VPatConvertFP2I_RM_VL_V; +defm : VPatConvertFP2I_RM_VL_V; +defm : VPatConvertFP2I_RM_VL_V; defm : VPatConvertFP2IVL_V; defm : VPatConvertFP2IVL_V; @@ -2648,14 +2585,12 @@ defm : VPatConvertFP2IVL_V; defm : VPatConvertI2FPVL_V_RM; defm : VPatConvertI2FPVL_V_RM; -defm : VPatConvertI2FP_RM_VL_V; -defm : VPatConvertI2FP_RM_VL_V; +defm : VPatConvertI2FP_RM_VL_V; +defm : VPatConvertI2FP_RM_VL_V; // 13.18. Widening Floating-Point/Integer Type-Convert Instructions -defm : VPatWConvertFP2IVL_V_RM; -defm : VPatWConvertFP2IVL_V_RM; -defm : VPatWConvertFP2I_RM_VL_V; -defm : VPatWConvertFP2I_RM_VL_V; +defm : VPatWConvertFP2I_RM_VL_V; +defm : VPatWConvertFP2I_RM_VL_V; defm : VPatWConvertFP2IVL_V; defm : VPatWConvertFP2IVL_V; @@ -2694,10 +2629,8 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in { } // 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions -defm : VPatNConvertFP2IVL_W_RM; -defm : VPatNConvertFP2IVL_W_RM; -defm : VPatNConvertFP2I_RM_VL_W; -defm : VPatNConvertFP2I_RM_VL_W; +defm : VPatNConvertFP2I_RM_VL_W; +defm : VPatNConvertFP2I_RM_VL_W; defm : VPatNConvertFP2IVL_W; defm : VPatNConvertFP2IVL_W; @@ -2705,8 +2638,8 @@ defm : VPatNConvertFP2IVL_W; defm : VPatNConvertI2FPVL_W_RM; -defm : VPatNConvertI2FP_RM_VL_W; -defm : VPatNConvertI2FP_RM_VL_W; +defm : VPatNConvertI2FP_RM_VL_W; +defm : VPatNConvertI2FP_RM_VL_W; foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td index b54baa16d9286baa829ce67b1273d2ea76dcb799..4478e24611108063956b1dfdd431147adfd71718 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td @@ -818,7 +818,7 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in { let usesCustomInserter = 1 in def Select_GPR_Using_CC_Imm : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, simm5:$imm5, ixlenimm:$cc, + (ins GPR:$lhs, simm5:$imm5, cond_code:$cc, GPR:$truev, GPR:$falsev), []>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 5068d0be0fb49bd2df474a897d085e12d61f4ca5..1ad3e1b681466b608441250119df9e458b9397c7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -222,7 +222,8 @@ let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq", def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">; } -let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf" in { +let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf", + Uses = [FRM] in { def VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">; def VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">; } @@ -230,7 +231,7 @@ let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf class VPseudoVC_X : Pseudo<(outs), (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -243,7 +244,7 @@ class VPseudoVC_X : class VPseudoVC_XV : Pseudo<(outs), (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -257,7 +258,7 @@ class VPseudoVC_XVV : Pseudo<(outs), (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -270,7 +271,7 @@ class VPseudoVC_XVV : Pseudo<(outs RDClass:$rd), (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -284,7 +285,7 @@ class VPseudoVC_V_XV : Pseudo<(outs RDClass:$rd), (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -298,7 +299,7 @@ class VPseudoVC_V_XVV : Pseudo<(outs RDClass:$rd), (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, ixlenimm:$sew), []>, + AVL:$vl, sew:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -405,7 +406,7 @@ multiclass VPseudoSiFiveVFWMACC { multiclass VPseudoSiFiveVFNRCLIP { foreach i = 0-4 in - let hasSideEffects = 0 in + let hasSideEffects = 0, hasPostISelHook = 1 in defm "Pseudo" # NAME : VPseudoBinaryRoundingMode { let ParserMatchClass = LoadFPImmOperand; let PrintMethod = "printFPImmOperand"; + let OperandType = "OPERAND_UIMM5"; + let OperandNamespace = "RISCVOp"; } def RTZArg : AsmOperandClass { @@ -48,6 +50,8 @@ def rtzarg : Operand { let ParserMatchClass = RTZArg; let PrintMethod = "printFRMArg"; let DecoderMethod = "decodeRTZArg"; + let OperandType = "OPERAND_RTZARG"; + let OperandNamespace = "RISCVOp"; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index 7ec13e4eaafa7d3bbae0fe851470b8bdfb3d93c7..782651fd6d01975b20554d21dfe942e6e5dc63c2 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -231,7 +231,7 @@ class ZvkMxSet { class VPseudoBinaryNoMask_Zvk : Pseudo<(outs RetClass:$rd_wb), - (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -248,7 +248,7 @@ class VPseudoTernaryNoMask_Zvk : Pseudo<(outs RetClass:$rd_wb), (ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1, - AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index 79248feb6f35d15192478047205cf5afccddad44..1c337d1789ed52b3f2f5f8a40fd8d2608099e4a2 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -847,8 +847,7 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost( // The interleaved memory access pass will lower interleaved memory ops (i.e // a load and store followed by a specific shuffle) to vlseg/vsseg - // intrinsics. In those cases then we can treat it as if it's just one (legal) - // memory op + // intrinsics. if (!UseMaskForCond && !UseMaskForGaps && Factor <= TLI->getMaxSupportedInterleaveFactor()) { auto *VTy = cast(VecTy); @@ -858,19 +857,27 @@ InstructionCost RISCVTTIImpl::getInterleavedMemoryOpCost( auto *SubVecTy = VectorType::get(VTy->getElementType(), VTy->getElementCount().divideCoefficientBy(Factor)); - if (VTy->getElementCount().isKnownMultipleOf(Factor) && TLI->isLegalInterleavedAccessType(SubVecTy, Factor, Alignment, AddressSpace, DL)) { - // FIXME: We use the memory op cost of the *legalized* type here, - // because it's getMemoryOpCost returns a really expensive cost for - // types like <6 x i8>, which show up when doing interleaves of - // Factor=3 etc. Should the memory op cost of these be cheaper? - auto *LegalVTy = VectorType::get(VTy->getElementType(), - LT.second.getVectorElementCount()); - InstructionCost LegalMemCost = getMemoryOpCost( - Opcode, LegalVTy, Alignment, AddressSpace, CostKind); - return LT.first + LegalMemCost; + + // Most available hardware today optimizes NF=2 as as one wide memory op + // + Factor * LMUL shuffle ops. + if (Factor == 2) { + InstructionCost Cost = + getMemoryOpCost(Opcode, VTy, Alignment, AddressSpace, CostKind); + MVT SubVecVT = getTLI()->getValueType(DL, SubVecTy).getSimpleVT(); + Cost += Factor * TLI->getLMULCost(SubVecVT); + return LT.first * Cost; + } + + // Otherwise, the cost is proportional to the number of elements (VL * + // Factor ops). + InstructionCost MemOpCost = + getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, + CostKind, {TTI::OK_AnyValue, TTI::OP_None}); + unsigned NumLoads = getEstimatedVLFor(VTy); + return NumLoads * MemOpCost; } } } @@ -1076,12 +1083,17 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) { auto *RetTy = ICA.getReturnType(); switch (ICA.getID()) { + case Intrinsic::lrint: + case Intrinsic::llrint: + // We can't currently lower half or bfloat vector lrint/llrint. + if (auto *VecTy = dyn_cast(ICA.getArgTypes()[0]); + VecTy && VecTy->getElementType()->is16bitFPTy()) + return InstructionCost::getInvalid(); + [[fallthrough]]; case Intrinsic::ceil: case Intrinsic::floor: case Intrinsic::trunc: case Intrinsic::rint: - case Intrinsic::lrint: - case Intrinsic::llrint: case Intrinsic::round: case Intrinsic::roundeven: { // These all use the same code. @@ -1762,13 +1774,6 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, } // IR Reduction is composed by two vmv and one rvv reduction instruction. - if (TTI::requiresOrderedReduction(FMF)) { - Opcodes.push_back(RISCV::VFMV_S_F); - for (unsigned i = 0; i < LT.first.getValue(); i++) - Opcodes.push_back(RISCV::VFREDOSUM_VS); - Opcodes.push_back(RISCV::VFMV_F_S); - return getRISCVInstructionCost(Opcodes, LT.second, CostKind); - } unsigned SplitOp; switch (ISD) { case ISD::ADD: @@ -1788,6 +1793,13 @@ RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Opcodes = {RISCV::VMV_S_X, RISCV::VREDAND_VS, RISCV::VMV_X_S}; break; case ISD::FADD: + if (TTI::requiresOrderedReduction(FMF)) { + Opcodes.push_back(RISCV::VFMV_S_F); + for (unsigned i = 0; i < LT.first.getValue(); i++) + Opcodes.push_back(RISCV::VFREDOSUM_VS); + Opcodes.push_back(RISCV::VFMV_F_S); + return getRISCVInstructionCost(Opcodes, LT.second, CostKind); + } // We can't promote f16/bf16 fadd reductions. if ((LT.second.getVectorElementType() == MVT::f16 && !ST->hasVInstructionsF16()) || diff --git a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp index 64fde8bf67ab9100ed1c65edf4b913b237614b76..62bd8d1f9d2433fe5d45600dbe9aedfef148a591 100644 --- a/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp @@ -713,21 +713,36 @@ Register SPIRVGlobalRegistry::buildGlobalVariable( return Reg; } +static std::string GetSpirvImageTypeName(const SPIRVType *Type, + MachineIRBuilder &MIRBuilder, + const std::string &Prefix); + static std::string buildSpirvTypeName(const SPIRVType *Type, MachineIRBuilder &MIRBuilder) { switch (Type->getOpcode()) { + case SPIRV::OpTypeSampledImage: { + return GetSpirvImageTypeName(Type, MIRBuilder, "sampled_image_"); + } case SPIRV::OpTypeImage: { - Register SampledTypeReg = Type->getOperand(1).getReg(); - auto *SampledType = MIRBuilder.getMRI()->getUniqueVRegDef(SampledTypeReg); - std::string TypeName = - "image_" + buildSpirvTypeName(SampledType, MIRBuilder); - for (uint32_t I = 2; I < Type->getNumOperands(); ++I) { - TypeName = (TypeName + '_' + Twine(Type->getOperand(I).getImm())).str(); - } - return TypeName; + return GetSpirvImageTypeName(Type, MIRBuilder, "image_"); + } + case SPIRV::OpTypeArray: { + MachineRegisterInfo *MRI = MIRBuilder.getMRI(); + Register ElementTypeReg = Type->getOperand(1).getReg(); + auto *ElementType = MRI->getUniqueVRegDef(ElementTypeReg); + const SPIRVType *TypeInst = MRI->getVRegDef(Type->getOperand(2).getReg()); + assert(TypeInst->getOpcode() != SPIRV::OpConstantI); + MachineInstr *ImmInst = MRI->getVRegDef(TypeInst->getOperand(1).getReg()); + assert(ImmInst->getOpcode() == TargetOpcode::G_CONSTANT); + uint32_t ArraySize = ImmInst->getOperand(1).getCImm()->getZExtValue(); + return (buildSpirvTypeName(ElementType, MIRBuilder) + Twine("[") + + Twine(ArraySize) + Twine("]")) + .str(); } case SPIRV::OpTypeFloat: return ("f" + Twine(Type->getOperand(1).getImm())).str(); + case SPIRV::OpTypeSampler: + return ("sampler"); case SPIRV::OpTypeInt: if (Type->getOperand(2).getImm()) return ("i" + Twine(Type->getOperand(1).getImm())).str(); @@ -737,6 +752,18 @@ static std::string buildSpirvTypeName(const SPIRVType *Type, } } +static std::string GetSpirvImageTypeName(const SPIRVType *Type, + MachineIRBuilder &MIRBuilder, + const std::string &Prefix) { + Register SampledTypeReg = Type->getOperand(1).getReg(); + auto *SampledType = MIRBuilder.getMRI()->getUniqueVRegDef(SampledTypeReg); + std::string TypeName = Prefix + buildSpirvTypeName(SampledType, MIRBuilder); + for (uint32_t I = 2; I < Type->getNumOperands(); ++I) { + TypeName = (TypeName + '_' + Twine(Type->getOperand(I).getImm())).str(); + } + return TypeName; +} + Register SPIRVGlobalRegistry::getOrCreateGlobalVariableWithBinding( const SPIRVType *VarType, uint32_t Set, uint32_t Binding, MachineIRBuilder &MIRBuilder) { diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index d9377fe4b91a1adeffab941ac114fa7e98153c48..526305d7ed28ab579b08a2c75c15278368054c30 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -260,6 +260,7 @@ private: SPIRVType *SrcPtrTy) const; Register buildPointerToResource(const SPIRVType *ResType, uint32_t Set, uint32_t Binding, uint32_t ArraySize, + Register IndexReg, bool IsNonUniform, MachineIRBuilder MIRBuilder) const; }; @@ -2547,6 +2548,17 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectExtInst(ResVReg, ResType, I, CL::rsqrt, GL::InverseSqrt); case Intrinsic::spv_sign: return selectSign(ResVReg, ResType, I); + case Intrinsic::spv_group_memory_barrier_with_group_sync: { + Register MemSemReg = + buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I); + Register ScopeReg = buildI32Constant(SPIRV::Scope::Workgroup, I); + MachineBasicBlock &BB = *I.getParent(); + return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier)) + .addUse(ScopeReg) + .addUse(ScopeReg) + .addUse(MemSemReg) + .constrainAllUses(TII, TRI, RBI); + } break; case Intrinsic::spv_lifetime_start: case Intrinsic::spv_lifetime_end: { unsigned Op = IID == Intrinsic::spv_lifetime_start ? SPIRV::OpLifetimeStart @@ -2605,10 +2617,15 @@ void SPIRVInstructionSelector::selectHandleFromBinding(Register &ResVReg, uint32_t Set = foldImm(I.getOperand(2), MRI); uint32_t Binding = foldImm(I.getOperand(3), MRI); uint32_t ArraySize = foldImm(I.getOperand(4), MRI); + Register IndexReg = I.getOperand(5).getReg(); + bool IsNonUniform = ArraySize > 1 && foldImm(I.getOperand(6), MRI); MachineIRBuilder MIRBuilder(I); - Register VarReg = - buildPointerToResource(ResType, Set, Binding, ArraySize, MIRBuilder); + Register VarReg = buildPointerToResource(ResType, Set, Binding, ArraySize, + IndexReg, IsNonUniform, MIRBuilder); + + if (IsNonUniform) + buildOpDecorate(ResVReg, I, TII, SPIRV::Decoration::NonUniformEXT, {}); // TODO: For now we assume the resource is an image, which needs to be // loaded to get the handle. That will not be true for storage buffers. @@ -2620,10 +2637,35 @@ void SPIRVInstructionSelector::selectHandleFromBinding(Register &ResVReg, Register SPIRVInstructionSelector::buildPointerToResource( const SPIRVType *ResType, uint32_t Set, uint32_t Binding, - uint32_t ArraySize, MachineIRBuilder MIRBuilder) const { - assert(ArraySize == 1 && "Resource arrays are not implemented yet."); - return GR.getOrCreateGlobalVariableWithBinding(ResType, Set, Binding, - MIRBuilder); + uint32_t ArraySize, Register IndexReg, bool IsNonUniform, + MachineIRBuilder MIRBuilder) const { + if (ArraySize == 1) + return GR.getOrCreateGlobalVariableWithBinding(ResType, Set, Binding, + MIRBuilder); + + const SPIRVType *VarType = GR.getOrCreateSPIRVArrayType( + ResType, ArraySize, *MIRBuilder.getInsertPt(), TII); + Register VarReg = GR.getOrCreateGlobalVariableWithBinding( + VarType, Set, Binding, MIRBuilder); + + SPIRVType *ResPointerType = GR.getOrCreateSPIRVPointerType( + ResType, MIRBuilder, SPIRV::StorageClass::UniformConstant); + + Register AcReg = MRI->createVirtualRegister(&SPIRV::iIDRegClass); + if (IsNonUniform) { + // It is unclear which value needs to be marked an non-uniform, so both + // the index and the access changed are decorated as non-uniform. + buildOpDecorate(IndexReg, MIRBuilder, SPIRV::Decoration::NonUniformEXT, {}); + buildOpDecorate(AcReg, MIRBuilder, SPIRV::Decoration::NonUniformEXT, {}); + } + + MIRBuilder.buildInstr(SPIRV::OpAccessChain) + .addDef(AcReg) + .addUse(GR.getSPIRVTypeID(ResPointerType)) + .addUse(VarReg) + .addUse(IndexReg); + + return AcReg; } bool SPIRVInstructionSelector::selectAllocaArray(Register ResVReg, diff --git a/llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp b/llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp index 9930d067173df764c17272116c2f4f547f57d5a8..c22492ec43b095c334348806ec528b26c3102c21 100644 --- a/llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVMergeRegionExitTargets.cpp @@ -130,6 +130,13 @@ public: assert(false && "Unhandled terminator type."); } + AllocaInst *CreateVariable(Function &F, Type *Type, + BasicBlock::iterator Position) { + const DataLayout &DL = F.getDataLayout(); + return new AllocaInst(Type, DL.getAllocaAddrSpace(), nullptr, "reg", + Position); + } + // Run the pass on the given convergence region, ignoring the sub-regions. // Returns true if the CFG changed, false otherwise. bool runOnConvergenceRegionNoRecurse(LoopInfo &LI, @@ -152,6 +159,9 @@ public: auto NewExitTarget = BasicBlock::Create(F->getContext(), "new.exit", F); IRBuilder<> Builder(NewExitTarget); + AllocaInst *Variable = CreateVariable(*F, Builder.getInt32Ty(), + F->begin()->getFirstInsertionPt()); + // CodeGen output needs to be stable. Using the set as-is would order // the targets differently depending on the allocation pattern. // Sorting per basic-block ordering in the function. @@ -176,18 +186,16 @@ public: std::vector> ExitToVariable; for (auto Exit : SortedExits) { llvm::Value *Value = createExitVariable(Exit, TargetToValue); + IRBuilder<> B2(Exit); + B2.SetInsertPoint(Exit->getFirstInsertionPt()); + B2.CreateStore(Value, Variable); ExitToVariable.emplace_back(std::make_pair(Exit, Value)); } - // Gather the correct value depending on the exit we came from. - llvm::PHINode *node = - Builder.CreatePHI(Builder.getInt32Ty(), ExitToVariable.size()); - for (auto [BB, Value] : ExitToVariable) { - node->addIncoming(Value, BB); - } + llvm::Value *Load = Builder.CreateLoad(Builder.getInt32Ty(), Variable); // Creating the switch to jump to the correct exit target. - llvm::SwitchInst *Sw = Builder.CreateSwitch(node, SortedExitTargets[0], + llvm::SwitchInst *Sw = Builder.CreateSwitch(Load, SortedExitTargets[0], SortedExitTargets.size() - 1); for (size_t i = 1; i < SortedExitTargets.size(); i++) { BasicBlock *BB = SortedExitTargets[i]; diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index db5463f5c7abb0b3d877595460c63d493c8a290d..29ce60d9983e38c8ca6388f199d773f85e2d4288 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -689,11 +689,31 @@ void RequirementHandler::initAvailableCapabilitiesForVulkan( const SPIRVSubtarget &ST) { addAvailableCaps({Capability::Shader, Capability::Linkage}); - // Provided by all supported Vulkan versions. + // Core in Vulkan 1.1 and earlier. addAvailableCaps({Capability::Int16, Capability::Int64, Capability::Float16, Capability::Float64, Capability::GroupNonUniform, Capability::Image1D, Capability::SampledBuffer, - Capability::ImageBuffer}); + Capability::ImageBuffer, + Capability::UniformBufferArrayDynamicIndexing, + Capability::SampledImageArrayDynamicIndexing, + Capability::StorageBufferArrayDynamicIndexing, + Capability::StorageImageArrayDynamicIndexing}); + + // Became core in Vulkan 1.2 + if (ST.isAtLeastSPIRVVer(VersionTuple(1, 5))) { + addAvailableCaps( + {Capability::ShaderNonUniformEXT, Capability::RuntimeDescriptorArrayEXT, + Capability::InputAttachmentArrayDynamicIndexingEXT, + Capability::UniformTexelBufferArrayDynamicIndexingEXT, + Capability::StorageTexelBufferArrayDynamicIndexingEXT, + Capability::UniformBufferArrayNonUniformIndexingEXT, + Capability::SampledImageArrayNonUniformIndexingEXT, + Capability::StorageBufferArrayNonUniformIndexingEXT, + Capability::StorageImageArrayNonUniformIndexingEXT, + Capability::InputAttachmentArrayNonUniformIndexingEXT, + Capability::UniformTexelBufferArrayNonUniformIndexingEXT, + Capability::StorageTexelBufferArrayNonUniformIndexingEXT}); + } } } // namespace SPIRV @@ -729,6 +749,8 @@ static void addOpDecorateReqs(const MachineInstr &MI, unsigned DecIndex, Dec == SPIRV::Decoration::ImplementInRegisterMapINTEL) { Reqs.addExtension( SPIRV::Extension::SPV_INTEL_global_variable_fpga_decorations); + } else if (Dec == SPIRV::Decoration::NonUniformEXT) { + Reqs.addRequirements(SPIRV::Capability::ShaderNonUniformEXT); } } @@ -848,6 +870,136 @@ static void AddAtomicFloatRequirements(const MachineInstr &MI, } } +bool isUniformTexelBuffer(MachineInstr *ImageInst) { + if (ImageInst->getOpcode() != SPIRV::OpTypeImage) + return false; + uint32_t Dim = ImageInst->getOperand(2).getImm(); + uint32_t Sampled = ImageInst->getOperand(6).getImm(); + return Dim == SPIRV::Dim::DIM_Buffer && Sampled == 1; +} + +bool isStorageTexelBuffer(MachineInstr *ImageInst) { + if (ImageInst->getOpcode() != SPIRV::OpTypeImage) + return false; + uint32_t Dim = ImageInst->getOperand(2).getImm(); + uint32_t Sampled = ImageInst->getOperand(6).getImm(); + return Dim == SPIRV::Dim::DIM_Buffer && Sampled == 2; +} + +bool isSampledImage(MachineInstr *ImageInst) { + if (ImageInst->getOpcode() != SPIRV::OpTypeImage) + return false; + uint32_t Dim = ImageInst->getOperand(2).getImm(); + uint32_t Sampled = ImageInst->getOperand(6).getImm(); + return Dim != SPIRV::Dim::DIM_Buffer && Sampled == 1; +} + +bool isInputAttachment(MachineInstr *ImageInst) { + if (ImageInst->getOpcode() != SPIRV::OpTypeImage) + return false; + uint32_t Dim = ImageInst->getOperand(2).getImm(); + uint32_t Sampled = ImageInst->getOperand(6).getImm(); + return Dim == SPIRV::Dim::DIM_SubpassData && Sampled == 2; +} + +bool isStorageImage(MachineInstr *ImageInst) { + if (ImageInst->getOpcode() != SPIRV::OpTypeImage) + return false; + uint32_t Dim = ImageInst->getOperand(2).getImm(); + uint32_t Sampled = ImageInst->getOperand(6).getImm(); + return Dim != SPIRV::Dim::DIM_Buffer && Sampled == 2; +} + +bool isCombinedImageSampler(MachineInstr *SampledImageInst) { + if (SampledImageInst->getOpcode() != SPIRV::OpTypeSampledImage) + return false; + + const MachineRegisterInfo &MRI = SampledImageInst->getMF()->getRegInfo(); + Register ImageReg = SampledImageInst->getOperand(1).getReg(); + auto *ImageInst = MRI.getUniqueVRegDef(ImageReg); + return isSampledImage(ImageInst); +} + +bool hasNonUniformDecoration(Register Reg, const MachineRegisterInfo &MRI) { + for (const auto &MI : MRI.reg_instructions(Reg)) { + if (MI.getOpcode() != SPIRV::OpDecorate) + continue; + + uint32_t Dec = MI.getOperand(1).getImm(); + if (Dec == SPIRV::Decoration::NonUniformEXT) + return true; + } + return false; +} + +void addOpAccessChainReqs(const MachineInstr &Instr, + SPIRV::RequirementHandler &Handler, + const SPIRVSubtarget &Subtarget) { + const MachineRegisterInfo &MRI = Instr.getMF()->getRegInfo(); + // Get the result type. If it is an image type, then the shader uses + // descriptor indexing. The appropriate capabilities will be added based + // on the specifics of the image. + Register ResTypeReg = Instr.getOperand(1).getReg(); + MachineInstr *ResTypeInst = MRI.getUniqueVRegDef(ResTypeReg); + + assert(ResTypeInst->getOpcode() == SPIRV::OpTypePointer); + uint32_t StorageClass = ResTypeInst->getOperand(1).getImm(); + if (StorageClass != SPIRV::StorageClass::StorageClass::UniformConstant && + StorageClass != SPIRV::StorageClass::StorageClass::Uniform && + StorageClass != SPIRV::StorageClass::StorageClass::StorageBuffer) { + return; + } + + Register PointeeTypeReg = ResTypeInst->getOperand(2).getReg(); + MachineInstr *PointeeType = MRI.getUniqueVRegDef(PointeeTypeReg); + if (PointeeType->getOpcode() != SPIRV::OpTypeImage && + PointeeType->getOpcode() != SPIRV::OpTypeSampledImage && + PointeeType->getOpcode() != SPIRV::OpTypeSampler) { + return; + } + + bool IsNonUniform = + hasNonUniformDecoration(Instr.getOperand(0).getReg(), MRI); + if (isUniformTexelBuffer(PointeeType)) { + if (IsNonUniform) + Handler.addRequirements( + SPIRV::Capability::UniformTexelBufferArrayNonUniformIndexingEXT); + else + Handler.addRequirements( + SPIRV::Capability::UniformTexelBufferArrayDynamicIndexingEXT); + } else if (isInputAttachment(PointeeType)) { + if (IsNonUniform) + Handler.addRequirements( + SPIRV::Capability::InputAttachmentArrayNonUniformIndexingEXT); + else + Handler.addRequirements( + SPIRV::Capability::InputAttachmentArrayDynamicIndexingEXT); + } else if (isStorageTexelBuffer(PointeeType)) { + if (IsNonUniform) + Handler.addRequirements( + SPIRV::Capability::StorageTexelBufferArrayNonUniformIndexingEXT); + else + Handler.addRequirements( + SPIRV::Capability::StorageTexelBufferArrayDynamicIndexingEXT); + } else if (isSampledImage(PointeeType) || + isCombinedImageSampler(PointeeType) || + PointeeType->getOpcode() == SPIRV::OpTypeSampler) { + if (IsNonUniform) + Handler.addRequirements( + SPIRV::Capability::SampledImageArrayNonUniformIndexingEXT); + else + Handler.addRequirements( + SPIRV::Capability::SampledImageArrayDynamicIndexing); + } else if (isStorageImage(PointeeType)) { + if (IsNonUniform) + Handler.addRequirements( + SPIRV::Capability::StorageImageArrayNonUniformIndexingEXT); + else + Handler.addRequirements( + SPIRV::Capability::StorageImageArrayDynamicIndexing); + } +} + void addInstrRequirements(const MachineInstr &MI, SPIRV::RequirementHandler &Reqs, const SPIRVSubtarget &ST) { @@ -967,11 +1119,17 @@ void addInstrRequirements(const MachineInstr &MI, case SPIRV::OpConstantSampler: Reqs.addCapability(SPIRV::Capability::LiteralSampler); break; + case SPIRV::OpInBoundsAccessChain: + case SPIRV::OpAccessChain: + addOpAccessChainReqs(MI, Reqs, ST); + break; case SPIRV::OpTypeImage: addOpTypeImageReqs(MI, Reqs, ST); break; case SPIRV::OpTypeSampler: - Reqs.addCapability(SPIRV::Capability::ImageBasic); + if (!ST.isVulkanEnv()) { + Reqs.addCapability(SPIRV::Capability::ImageBasic); + } break; case SPIRV::OpTypeForwardPointer: // TODO: check if it's OpenCL's kernel. diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index 3c2af34dd55239a5a1a2d976443c51052f435ecb..cc34cf877dea97fe355e0dd18c2b72da3932a969 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -165,6 +165,57 @@ static MachineInstr *findAssignTypeInstr(Register Reg, return nullptr; } +static void buildOpBitcast(SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB, + Register ResVReg, Register OpReg) { + SPIRVType *ResType = GR->getSPIRVTypeForVReg(ResVReg); + SPIRVType *OpType = GR->getSPIRVTypeForVReg(OpReg); + assert(ResType && OpType && "Operand types are expected"); + if (!GR->isBitcastCompatible(ResType, OpType)) + report_fatal_error("incompatible result and operand types in a bitcast"); + MachineRegisterInfo *MRI = MIB.getMRI(); + if (!MRI->getRegClassOrNull(ResVReg)) + MRI->setRegClass(ResVReg, GR->getRegClass(ResType)); + MIB.buildInstr(SPIRV::OpBitcast) + .addDef(ResVReg) + .addUse(GR->getSPIRVTypeID(ResType)) + .addUse(OpReg); +} + +// We do instruction selections early instead of calling MIB.buildBitcast() +// generating the general op code G_BITCAST. When MachineVerifier validates +// G_BITCAST we see a check of a kind: if Source Type is equal to Destination +// Type then report error "bitcast must change the type". This doesn't take into +// account the notion of a typed pointer that is important for SPIR-V where a +// user may and should use bitcast between pointers with different pointee types +// (https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpBitcast). +// It's important for correct lowering in SPIR-V, because interpretation of the +// data type is not left to instructions that utilize the pointer, but encoded +// by the pointer declaration, and the SPIRV target can and must handle the +// declaration and use of pointers that specify the type of data they point to. +// It's not feasible to improve validation of G_BITCAST using just information +// provided by low level types of source and destination. Therefore we don't +// produce G_BITCAST as the general op code with semantics different from +// OpBitcast, but rather lower to OpBitcast immediately. As for now, the only +// difference would be that CombinerHelper couldn't transform known patterns +// around G_BUILD_VECTOR. See discussion +// in https://github.com/llvm/llvm-project/pull/110270 for even more context. +static void selectOpBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR, + MachineIRBuilder MIB) { + SmallVector ToErase; + for (MachineBasicBlock &MBB : MF) { + for (MachineInstr &MI : MBB) { + if (MI.getOpcode() != TargetOpcode::G_BITCAST) + continue; + MIB.setInsertPt(*MI.getParent(), MI); + buildOpBitcast(GR, MIB, MI.getOperand(0).getReg(), + MI.getOperand(1).getReg()); + ToErase.push_back(&MI); + } + } + for (MachineInstr *MI : ToErase) + MI->eraseFromParent(); +} + static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR, MachineIRBuilder MIB) { // Get access to information about available extensions @@ -202,15 +253,6 @@ static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR, } else { GR->assignSPIRVTypeToVReg(AssignedPtrType, Def, MF); MIB.buildBitcast(Def, Source); - // MachineVerifier requires that bitcast must change the type. - // Change AddressSpace if needed to hint that Def and Source points to - // different types: this doesn't change actual code generation. - LLT DefType = MRI->getType(Def); - if (DefType == MRI->getType(Source)) - MRI->setType(Def, - LLT::pointer((DefType.getAddressSpace() + 1) % - SPIRVSubtarget::MaxLegalAddressSpace, - GR->getPointerSize())); } } } @@ -1007,6 +1049,7 @@ bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) { removeImplicitFallthroughs(MF, MIB); insertSpirvDecorations(MF, MIB); insertInlineAsm(MF, GR, ST, MIB); + selectOpBitcasts(MF, GR, MIB); return true; } diff --git a/llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp b/llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp index 211a060ee103bca98d5b60e67b8ffff17a696251..13e05b679275185cd81d855c303cd6fae23a7626 100644 --- a/llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVStructurizer.cpp @@ -87,7 +87,7 @@ BasicBlock *getExitFor(const ConvergenceRegion *CR) { // Returns the merge block designated by I if I is a merge instruction, nullptr // otherwise. BasicBlock *getDesignatedMergeBlock(Instruction *I) { - IntrinsicInst *II = dyn_cast(I); + IntrinsicInst *II = dyn_cast_or_null(I); if (II == nullptr) return nullptr; @@ -102,7 +102,7 @@ BasicBlock *getDesignatedMergeBlock(Instruction *I) { // Returns the continue block designated by I if I is an OpLoopMerge, nullptr // otherwise. BasicBlock *getDesignatedContinueBlock(Instruction *I) { - IntrinsicInst *II = dyn_cast(I); + IntrinsicInst *II = dyn_cast_or_null(I); if (II == nullptr) return nullptr; @@ -284,18 +284,6 @@ void replaceBranchTargets(BasicBlock *BB, BasicBlock *OldTarget, assert(false && "Unhandled terminator type."); } -// Replaces basic bloc operands |OldSrc| or OpPhi instructions in |BB| by -// |NewSrc|. This function does not simplify the OpPhi instruction once -// transformed. -void replacePhiTargets(BasicBlock *BB, BasicBlock *OldSrc, BasicBlock *NewSrc) { - for (PHINode &Phi : BB->phis()) { - int index = Phi.getBasicBlockIndex(OldSrc); - if (index == -1) - continue; - Phi.setIncomingBlock(index, NewSrc); - } -} - } // anonymous namespace // Given a reducible CFG, produces a structurized CFG in the SPIR-V sense, @@ -423,7 +411,7 @@ class SPIRVStructurizer : public FunctionPass { } // Splits the given edges by recreating proxy nodes so that the destination - // OpPhi instruction can still be viable. + // has unique incoming edges from this region. // // clang-format off // @@ -436,66 +424,58 @@ class SPIRVStructurizer : public FunctionPass { // A -> D -> C // B -> D -> C // - // But if C had a phi node, adding such proxy-block breaks it. In such case, we must add 1 new block per - // exit, and patchup the phi node: + // This is fine (assuming C has no PHI nodes), but requires handling the merge instruction here. + // By adding a proxy node, we create a regular divergent shape which can easily be regularized later on. // A -> D -> D1 -> C // B -> D -> D2 -> C // - // A, B, D belongs to the construct. D is the exit. D1 and D2 are empty, just used as - // source operands for C's phi node. + // A, B, D belongs to the construct. D is the exit. D1 and D2 are empty. // // clang-format on std::vector createAliasBlocksForComplexEdges(std::vector Edges) { - std::unordered_map Seen; + std::unordered_set Seen; std::vector Output; Output.reserve(Edges.size()); for (auto &[Src, Dst] : Edges) { - auto [iterator, inserted] = Seen.insert({Src, Dst}); - if (inserted) { - Output.emplace_back(Src, Dst); - continue; + auto [Iterator, Inserted] = Seen.insert(Src); + if (!Inserted) { + // Src already a source node. Cannot have 2 edges from A to B. + // Creating alias source block. + BasicBlock *NewSrc = BasicBlock::Create( + F.getContext(), Src->getName() + ".new.src", &F); + replaceBranchTargets(Src, Dst, NewSrc); + IRBuilder<> Builder(NewSrc); + Builder.CreateBr(Dst); + Src = NewSrc; } - // The exact same edge was already seen. Ignoring. - if (iterator->second == Dst) - continue; - - // The same Src block branches to 2 distinct blocks. This will be an - // issue for the generated OpPhi. Creating alias block. - BasicBlock *NewSrc = - BasicBlock::Create(F.getContext(), "new.exit.src", &F); - replaceBranchTargets(Src, Dst, NewSrc); - replacePhiTargets(Dst, Src, NewSrc); - - IRBuilder<> Builder(NewSrc); - Builder.CreateBr(Dst); - - Seen.emplace(NewSrc, Dst); - Output.emplace_back(NewSrc, Dst); + Output.emplace_back(Src, Dst); } return Output; } + AllocaInst *CreateVariable(Function &F, Type *Type, + BasicBlock::iterator Position) { + const DataLayout &DL = F.getDataLayout(); + return new AllocaInst(Type, DL.getAllocaAddrSpace(), nullptr, "reg", + Position); + } + // Given a construct defined by |Header|, and a list of exiting edges // |Edges|, creates a new single exit node, fixing up those edges. BasicBlock *createSingleExitNode(BasicBlock *Header, std::vector &Edges) { - auto NewExit = BasicBlock::Create(F.getContext(), "new.exit", &F); - IRBuilder<> ExitBuilder(NewExit); - std::vector Dsts; - std::unordered_map DstToIndex; - - // Given 2 edges: Src1 -> Dst, Src2 -> Dst: - // If Dst has an PHI node, and Src1 and Src2 are both operands, both Src1 - // and Src2 cannot be hidden by NewExit. Create 2 new nodes: Alias1, - // Alias2 to which NewExit will branch before going to Dst. Then, patchup - // Dst PHI node to look for Alias1 and Alias2. std::vector FixedEdges = createAliasBlocksForComplexEdges(Edges); + std::vector Dsts; + std::unordered_map DstToIndex; + auto NewExit = BasicBlock::Create(F.getContext(), + Header->getName() + ".new.exit", &F); + IRBuilder<> ExitBuilder(NewExit); for (auto &[Src, Dst] : FixedEdges) { if (DstToIndex.count(Dst) != 0) continue; @@ -506,33 +486,34 @@ class SPIRVStructurizer : public FunctionPass { if (Dsts.size() == 1) { for (auto &[Src, Dst] : FixedEdges) { replaceBranchTargets(Src, Dst, NewExit); - replacePhiTargets(Dst, Src, NewExit); } ExitBuilder.CreateBr(Dsts[0]); return NewExit; } - PHINode *PhiNode = - ExitBuilder.CreatePHI(ExitBuilder.getInt32Ty(), FixedEdges.size()); - + AllocaInst *Variable = CreateVariable(F, ExitBuilder.getInt32Ty(), + F.begin()->getFirstInsertionPt()); for (auto &[Src, Dst] : FixedEdges) { - PhiNode->addIncoming(DstToIndex[Dst], Src); + IRBuilder<> B2(Src); + B2.SetInsertPoint(Src->getFirstInsertionPt()); + B2.CreateStore(DstToIndex[Dst], Variable); replaceBranchTargets(Src, Dst, NewExit); - replacePhiTargets(Dst, Src, NewExit); } + llvm::Value *Load = + ExitBuilder.CreateLoad(ExitBuilder.getInt32Ty(), Variable); + // If we can avoid an OpSwitch, generate an OpBranch. Reason is some // OpBranch are allowed to exist without a new OpSelectionMerge if one of // the branch is the parent's merge node, while OpSwitches are not. if (Dsts.size() == 2) { - Value *Condition = ExitBuilder.CreateCmp(CmpInst::ICMP_EQ, - DstToIndex[Dsts[0]], PhiNode); + Value *Condition = + ExitBuilder.CreateCmp(CmpInst::ICMP_EQ, DstToIndex[Dsts[0]], Load); ExitBuilder.CreateCondBr(Condition, Dsts[0], Dsts[1]); return NewExit; } - SwitchInst *Sw = - ExitBuilder.CreateSwitch(PhiNode, Dsts[0], Dsts.size() - 1); + SwitchInst *Sw = ExitBuilder.CreateSwitch(Load, Dsts[0], Dsts.size() - 1); for (auto It = Dsts.begin() + 1; It != Dsts.end(); ++It) { Sw->addCase(DstToIndex[*It], *It); } @@ -576,7 +557,7 @@ class SPIRVStructurizer : public FunctionPass { // Creates a new basic block in F with a single OpUnreachable instruction. BasicBlock *CreateUnreachable(Function &F) { - BasicBlock *BB = BasicBlock::Create(F.getContext(), "new.exit", &F); + BasicBlock *BB = BasicBlock::Create(F.getContext(), "unreachable", &F); IRBuilder<> Builder(BB); Builder.CreateUnreachable(); return BB; @@ -1027,17 +1008,8 @@ class SPIRVStructurizer : public FunctionPass { return Modified; } - bool IsRequiredForPhiNode(BasicBlock *BB) { - for (BasicBlock *Successor : successors(BB)) { - for (PHINode &Phi : Successor->phis()) { - if (Phi.getBasicBlockIndex(BB) != -1) - return true; - } - } - - return false; - } - + // Removes blocks not contributing to any structured CFG. This assumes there + // is no PHI nodes. bool removeUselessBlocks(Function &F) { std::vector ToRemove; @@ -1054,9 +1026,6 @@ class SPIRVStructurizer : public FunctionPass { if (MergeBlocks.count(&BB) != 0 || ContinueBlocks.count(&BB) != 0) continue; - if (IsRequiredForPhiNode(&BB)) - continue; - if (BB.getUniqueSuccessor() == nullptr) continue; @@ -1127,6 +1096,18 @@ class SPIRVStructurizer : public FunctionPass { continue; Modified = true; + + if (Merge == nullptr) { + Merge = *successors(Header).begin(); + IRBuilder<> Builder(Header); + Builder.SetInsertPoint(Header->getTerminator()); + + auto MergeAddress = BlockAddress::get(Merge->getParent(), Merge); + SmallVector Args = {MergeAddress}; + Builder.CreateIntrinsic(Intrinsic::spv_selection_merge, {}, {Args}); + continue; + } + Instruction *SplitInstruction = Merge->getTerminator(); if (isMergeInstruction(SplitInstruction->getPrevNode())) SplitInstruction = SplitInstruction->getPrevNode(); diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td index 13ad1eb8e8b33793ae7ed37d568b73d035038e4d..d63438baca7e7692779417232f12eb6a4fc96143 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td +++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td @@ -355,7 +355,9 @@ defm GeometryPointSize : CapabilityOperand<24, 0, 0, [], [Geometry]>; defm ImageGatherExtended : CapabilityOperand<25, 0, 0, [], [Shader]>; defm StorageImageMultisample : CapabilityOperand<27, 0, 0, [], [Shader]>; defm UniformBufferArrayDynamicIndexing : CapabilityOperand<28, 0, 0, [], [Shader]>; -defm SampledImageArrayDymnamicIndexing : CapabilityOperand<29, 0, 0, [], [Shader]>; +defm SampledImageArrayDynamicIndexing : CapabilityOperand<29, 0, 0, [], [Shader]>; +defm StorageBufferArrayDynamicIndexing : CapabilityOperand<30, 0, 0, [], [Shader]>; +defm StorageImageArrayDynamicIndexing : CapabilityOperand<31, 0, 0, [], [Shader]>; defm ClipDistance : CapabilityOperand<32, 0, 0, [], [Shader]>; defm CullDistance : CapabilityOperand<33, 0, 0, [], [Shader]>; defm SampleRateShading : CapabilityOperand<35, 0, 0, [], [Shader]>; diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index e5384b2eb2c2c140057512a52d452d9f44cb4829..34854f31b3e387f7e5c0ae19faa3bb1184be9f53 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -29,6 +29,7 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Pass.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Transforms/Scalar/Reg2Mem.h" #include "llvm/Transforms/Utils.h" #include @@ -169,13 +170,21 @@ void SPIRVPassConfig::addIRPasses() { // - loops have a single back-edge. addPass(createLoopSimplifyPass()); - // 2. Merge the convergence region exit nodes into one. After this step, + // 2. Removes registers whose lifetime spans across basic blocks. Also + // removes phi nodes. This will greatly simplify the next steps. + addPass(createRegToMemWrapperPass()); + + // 3. Merge the convergence region exit nodes into one. After this step, // regions are single-entry, single-exit. This will help determine the // correct merge block. addPass(createSPIRVMergeRegionExitTargetsPass()); - // 3. Structurize. + // 4. Structurize. addPass(createSPIRVStructurizerPass()); + + // 5. Reduce the amount of variables required by pushing some operations + // back to virtual registers. + addPass(createPromoteMemoryToRegisterPass()); } addPass(createSPIRVRegularizerPass()); diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp index dff33b16b9cfcf387ba1e0b22883f0f31d77c497..f9b361e163c9090847200e44a26339cfca78b4ce 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.cpp @@ -460,53 +460,98 @@ PartialOrderingVisitor::getReachableFrom(BasicBlock *Start) { return Output; } -size_t PartialOrderingVisitor::visit(BasicBlock *BB, size_t Rank) { - if (Visited.count(BB) != 0) - return Rank; +bool PartialOrderingVisitor::CanBeVisited(BasicBlock *BB) const { + for (BasicBlock *P : predecessors(BB)) { + // Ignore back-edges. + if (DT.dominates(BB, P)) + continue; - Loop *L = LI.getLoopFor(BB); - const bool isLoopHeader = LI.isLoopHeader(BB); + // One of the predecessor hasn't been visited. Not ready yet. + if (BlockToOrder.count(P) == 0) + return false; - if (BlockToOrder.count(BB) == 0) { - OrderInfo Info = {Rank, Visited.size()}; - BlockToOrder.emplace(BB, Info); - } else { - BlockToOrder[BB].Rank = std::max(BlockToOrder[BB].Rank, Rank); + // If the block is a loop exit, the loop must be finished before + // we can continue. + Loop *L = LI.getLoopFor(P); + if (L == nullptr || L->contains(BB)) + continue; + + // SPIR-V requires a single back-edge. And the backend first + // step transforms loops into the simplified format. If we have + // more than 1 back-edge, something is wrong. + assert(L->getNumBackEdges() <= 1); + + // If the loop has no latch, loop's rank won't matter, so we can + // proceed. + BasicBlock *Latch = L->getLoopLatch(); + assert(Latch); + if (Latch == nullptr) + continue; + + // The latch is not ready yet, let's wait. + if (BlockToOrder.count(Latch) == 0) + return false; } - for (BasicBlock *Predecessor : predecessors(BB)) { - if (isLoopHeader && L->contains(Predecessor)) { + return true; +} + +size_t PartialOrderingVisitor::GetNodeRank(BasicBlock *BB) const { + size_t result = 0; + + for (BasicBlock *P : predecessors(BB)) { + // Ignore back-edges. + if (DT.dominates(BB, P)) continue; - } - if (BlockToOrder.count(Predecessor) == 0) { - return Rank; + auto Iterator = BlockToOrder.end(); + Loop *L = LI.getLoopFor(P); + BasicBlock *Latch = L ? L->getLoopLatch() : nullptr; + + // If the predecessor is either outside a loop, or part of + // the same loop, simply take its rank + 1. + if (L == nullptr || L->contains(BB) || Latch == nullptr) { + Iterator = BlockToOrder.find(P); + } else { + // Otherwise, take the loop's rank (highest rank in the loop) as base. + // Since loops have a single latch, highest rank is easy to find. + // If the loop has no latch, then it doesn't matter. + Iterator = BlockToOrder.find(Latch); } + + assert(Iterator != BlockToOrder.end()); + result = std::max(result, Iterator->second.Rank + 1); } - Visited.insert(BB); + return result; +} + +size_t PartialOrderingVisitor::visit(BasicBlock *BB, size_t Unused) { + ToVisit.push(BB); + Queued.insert(BB); - SmallVector OtherSuccessors; - SmallVector LoopSuccessors; + while (ToVisit.size() != 0) { + BasicBlock *BB = ToVisit.front(); + ToVisit.pop(); - for (BasicBlock *Successor : successors(BB)) { - // Ignoring back-edges. - if (DT.dominates(Successor, BB)) + if (!CanBeVisited(BB)) { + ToVisit.push(BB); continue; + } - if (isLoopHeader && L->contains(Successor)) { - LoopSuccessors.push_back(Successor); - } else - OtherSuccessors.push_back(Successor); - } + size_t Rank = GetNodeRank(BB); + OrderInfo Info = {Rank, BlockToOrder.size()}; + BlockToOrder.emplace(BB, Info); - for (BasicBlock *BB : LoopSuccessors) - Rank = std::max(Rank, visit(BB, Rank + 1)); + for (BasicBlock *S : successors(BB)) { + if (Queued.count(S) != 0) + continue; + ToVisit.push(S); + Queued.insert(S); + } + } - size_t OutputRank = Rank; - for (BasicBlock *Item : OtherSuccessors) - OutputRank = std::max(OutputRank, visit(Item, Rank + 1)); - return OutputRank; + return 0; } PartialOrderingVisitor::PartialOrderingVisitor(Function &F) { diff --git a/llvm/lib/Target/SPIRV/SPIRVUtils.h b/llvm/lib/Target/SPIRV/SPIRVUtils.h index 83e717e6ea58fd993f9044cb8f3968e1892ac560..11fd3a5c61dcae03ef99038ce339bf24d7465221 100644 --- a/llvm/lib/Target/SPIRV/SPIRVUtils.h +++ b/llvm/lib/Target/SPIRV/SPIRVUtils.h @@ -18,6 +18,7 @@ #include "llvm/IR/Dominators.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/TypedPointerType.h" +#include #include #include @@ -62,7 +63,9 @@ class SPIRVSubtarget; class PartialOrderingVisitor { DomTreeBuilder::BBDomTree DT; LoopInfo LI; - std::unordered_set Visited = {}; + + std::unordered_set Queued = {}; + std::queue ToVisit = {}; struct OrderInfo { size_t Rank; @@ -80,6 +83,9 @@ class PartialOrderingVisitor { // Visits |BB| with the current rank being |Rank|. size_t visit(BasicBlock *BB, size_t Rank); + size_t GetNodeRank(BasicBlock *BB) const; + bool CanBeVisited(BasicBlock *BB) const; + public: // Build the visitor to operate on the function F. PartialOrderingVisitor(Function &F); diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp index 5b407a8b6f54a0fc7cba0a3a9515953ca184096a..4bba54463103bcb0ceeafb7afd21a02ae478f1af 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp @@ -38,7 +38,7 @@ bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { return (STI.hasFeature(Sparc::FeatureV9)) != 0; } -void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << '%' << getRegisterName(Reg); } diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h index 207a970228058daeca30725cd1f508bd13fde5e9..52321d5621185835a7c45b993e1dbc1031a15beb 100644 --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h @@ -24,7 +24,7 @@ public: const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printRegName(raw_ostream &OS, MCRegister Reg, unsigned AltIdx) const; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.cpp index 05113010794e0b695a089bedbdde0d052cfd1acc..72b7bd60276a7a8f4814fb286d655ea5550c4568 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.cpp @@ -19,7 +19,7 @@ using namespace llvm; void SystemZGNUInstPrinter::printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const { + raw_ostream &O) { const char *RegName = getRegisterName(Reg); markup(O, Markup::Register) << '%' << RegName; } diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.h index 8f62ae0e16c006d7497e839f0ef2676ad536ae4e..7095e325c70bc00047d5e9298f7224059fffa699 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZGNUInstPrinter.h @@ -38,7 +38,7 @@ public: private: void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const override; + raw_ostream &O) override; }; } // end namespace llvm diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp index 9abd408324c0672a3666bc4e9d133165dba6051f..ef9881932f7c0854b6394ab0b5177491686e97d4 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.cpp @@ -19,7 +19,7 @@ using namespace llvm; void SystemZHLASMInstPrinter::printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const { + raw_ostream &O) { const char *RegName = getRegisterName(Reg); // Skip register prefix so that only register number is left assert(isalpha(RegName[0]) && isdigit(RegName[1])); diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.h index 9a69e012c72942db855461053b361377b29dfe82..ffccbec36c7491afdd4314bfd02043c6f82c63d0 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMInstPrinter.h @@ -37,7 +37,7 @@ public: private: void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const override; + raw_ostream &O) override; }; } // end namespace llvm diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp index 00560ab1f4b18d978ac9477e003000fd8c412dcb..fe0f3874765614d6823c61aa3aeebc9dce5d0fdf 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.cpp @@ -57,8 +57,7 @@ void SystemZInstPrinterCommon::printOperand(const MCOperand &MO, llvm_unreachable("Invalid operand"); } -void SystemZInstPrinterCommon::printRegName(raw_ostream &O, - MCRegister Reg) const { +void SystemZInstPrinterCommon::printRegName(raw_ostream &O, MCRegister Reg) { printFormattedRegName(&MAI, Reg, O); } diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h index 9a972824f7ffb51ae09f8c5acc433ef6fff3db35..1a11e421691ae38f0fe2e8a99badb807cc3445ef 100644 --- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h +++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinterCommon.h @@ -36,10 +36,10 @@ public: void printOperand(const MCOperand &MO, const MCAsmInfo *MAI, raw_ostream &O); virtual void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, - raw_ostream &O) const {} + raw_ostream &O) {} // Override MCInstPrinter. - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; protected: template diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 1fa2dbfb26fc25a9dde7b45300dd4dcd38a9cc0e..3999b54de81b657a2a4dfb8f1ae69e59e5b9b214 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -2676,10 +2676,7 @@ static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL, (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) { // Disable the nsw and nuw flags: the backend needs to handle // overflow as well during comparison elimination. - SDNodeFlags Flags = N->getFlags(); - Flags.setNoSignedWrap(false); - Flags.setNoUnsignedWrap(false); - N->setFlags(Flags); + N->dropFlags(SDNodeFlags::NoWrap); C.Op0 = SDValue(N, 0); C.Op1 = DAG.getConstant(0, DL, N->getValueType(0)); return; diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp index 8261b5aa7b4e13abbb9272a20294c75e259b61bd..47455a9a0274c2e0fc3f4ed16879d491659e2376 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp +++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp @@ -27,7 +27,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "VEGenAsmWriter.inc" -void VEInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void VEInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { // Generic registers have identical register name among register classes. unsigned AltIdx = VE::AsmName; // Misc registers have each own name, so no use alt-names. diff --git a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h index 65660a49c5e4dd3977e92f6663a8fff1b253f106..d5e0ebd3596ca86d8ec2683dcd164b5889c400ef 100644 --- a/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h +++ b/llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h @@ -24,7 +24,7 @@ public: const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp index 4c29b59b3302e4746b13421a6323cddc419bcc50..026f859b15d71521dc7627c5feed0151aaae9492 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp @@ -38,8 +38,7 @@ WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} -void WebAssemblyInstPrinter::printRegName(raw_ostream &OS, - MCRegister Reg) const { +void WebAssemblyInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { assert(Reg.id() != WebAssembly::UnusedReg); // Note that there's an implicit local.get/local.set here! OS << "$" << Reg.id(); diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h index b499926ab82965b520857d9801d3b2d7a841f321..e7c5e14973b630abfd1588cf2bd894109ad1e9a6 100644 --- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h +++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h @@ -35,7 +35,7 @@ public: WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp index 58b4527af6557b27e46ce6620e4cf2ab190cffca..c811d621e60eb7b31e3aa699412e7c6581739dfd 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp @@ -35,7 +35,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "X86GenAsmWriter.inc" -void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << '%' << getRegisterName(Reg); } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h index 83040c112b68850f8333833ea1e7ff1a52bcde3a..7e525e232362299d00854de45ec88df39df5d868 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h @@ -23,7 +23,7 @@ public: const MCRegisterInfo &MRI) : X86InstPrinterCommon(MAI, MII, MRI), HasCustomInstComment(false) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS); diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp index 587f923e789f02f497a0ed6b982c709e3d2998db..49e8bab4c0363dae395014ba2b3a2c6a905c3ec3 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp @@ -40,6 +40,20 @@ using namespace llvm; CASE_MASK_INS_COMMON(Inst, Suffix, src) \ CASE_MASKZ_INS_COMMON(Inst, Suffix, src) +#define CASE_FPCLASS_PACKED(Inst, src) \ + CASE_AVX_INS_COMMON(Inst, Z, r##src) \ + CASE_AVX_INS_COMMON(Inst, Z256, r##src) \ + CASE_AVX_INS_COMMON(Inst, Z128, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z, r##src) + +#define CASE_FPCLASS_PACKED_MEM(Inst) \ + CASE_FPCLASS_PACKED(Inst, m) \ + CASE_FPCLASS_PACKED(Inst, mb) + +#define CASE_FPCLASS_SCALAR(Inst, src) \ + CASE_AVX_INS_COMMON(Inst, Z, r##src) \ + CASE_MASK_INS_COMMON(Inst, Z, r##src) + #define CASE_PTERNLOG(Inst, src) \ CASE_AVX512_INS_COMMON(Inst, Z, r##src##i) \ CASE_AVX512_INS_COMMON(Inst, Z256, r##src##i) \ @@ -949,6 +963,70 @@ static bool printPTERNLOGComments(const MCInst *MI, raw_ostream &OS, return true; } +static bool printFPCLASSComments(const MCInst *MI, raw_ostream &OS, + const MCInstrInfo &MCII) { + unsigned NumOperands = MI->getNumOperands(); + int SrcIdx; + switch (MI->getOpcode()) { + CASE_FPCLASS_PACKED(FPCLASSPBF16, r) + CASE_FPCLASS_PACKED(FPCLASSPH, r) + CASE_FPCLASS_PACKED(FPCLASSPS, r) + CASE_FPCLASS_PACKED(FPCLASSPD, r) + CASE_FPCLASS_SCALAR(FPCLASSSH, r) + CASE_FPCLASS_SCALAR(FPCLASSSS, r) + CASE_FPCLASS_SCALAR(FPCLASSSD, r) { + SrcIdx = NumOperands - 2; + break; + } + CASE_FPCLASS_PACKED_MEM(FPCLASSPBF16) + CASE_FPCLASS_PACKED_MEM(FPCLASSPH) + CASE_FPCLASS_PACKED_MEM(FPCLASSPS) + CASE_FPCLASS_PACKED_MEM(FPCLASSPD) + CASE_FPCLASS_SCALAR(FPCLASSSH, m) + CASE_FPCLASS_SCALAR(FPCLASSSS, m) + CASE_FPCLASS_SCALAR(FPCLASSSD, m) { + SrcIdx = -1; + break; + } + default: + return false; + } + StringRef DestName = getRegName(MI->getOperand(0).getReg()); + StringRef SrcName = + SrcIdx != -1 ? getRegName(MI->getOperand(SrcIdx).getReg()) : "mem"; + + OS << DestName; + printMasking(OS, MI, MCII); + OS << " = "; + + uint8_t Categories = MI->getOperand(NumOperands - 1).getImm(); + if (Categories == 0) { + OS << "false"; + } else { + static constexpr StringLiteral CategoryNames[] = { + "QuietNaN", + "PositiveZero", + "NegativeZero", + "PositiveInfinity", + "NegativeInfinity", + "Subnormal", + "Negative", + "SignalingNaN", + }; + bool Conjoin = false; + for (size_t I = 0, E = std::size(CategoryNames); I != E; ++I) { + if (Categories & (1 << I)) { + if (Conjoin) + OS << " | "; + Conjoin = true; + OS << "is" << CategoryNames[I] << '(' << SrcName << ')'; + } + } + } + OS << '\n'; + return true; +} + //===----------------------------------------------------------------------===// // Top Level Entrypoint //===----------------------------------------------------------------------===// @@ -970,6 +1048,9 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, if (printPTERNLOGComments(MI, OS, MCII)) return true; + if (printFPCLASSComments(MI, OS, MCII)) + return true; + switch (MI->getOpcode()) { default: // Not an instruction for which we can decode comments. diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp index cd8b9aa62573001663686bbb296c14eb46a246f2..8e7dae229275bbb429fc028ab0005b51aa9fd89b 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp @@ -33,7 +33,7 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "X86GenAsmWriter1.inc" -void X86IntelInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void X86IntelInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { markup(OS, Markup::Register) << getRegisterName(Reg); } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h index a34c06782f404223d275452d6a2a169d5bc16fdb..988ab9626c3fd7e98203b8970451d3ee1c18e624 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h @@ -24,7 +24,7 @@ public: const MCRegisterInfo &MRI) : X86InstPrinterCommon(MAI, MII, MRI) {} - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) override; bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS); diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 6bedf9e1d13ac359de2c0d67392bba63f3bf2099..c7882acc044e04b484c93194b1f51b49173e1fb9 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -270,6 +270,9 @@ def FeatureAMXFP16 : SubtargetFeature<"amx-fp16", "HasAMXFP16", "true", def FeatureAMXCOMPLEX : SubtargetFeature<"amx-complex", "HasAMXCOMPLEX", "true", "Support AMX-COMPLEX instructions", [FeatureAMXTILE]>; +def FeatureAMXFP8 : SubtargetFeature<"amx-fp8", "HasAMXFP8", "true", + "Support AMX-FP8 instructions", + [FeatureAMXTILE]>; def FeatureCMPCCXADD : SubtargetFeature<"cmpccxadd", "HasCMPCCXADD", "true", "Support CMPCCXADD instructions">; def FeatureRAOINT : SubtargetFeature<"raoint", "HasRAOINT", "true", diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1c790f3813b7a477f80ca0f84adff182f0b0af30..58598fefe0e796b9840c57f1dd506eed87a180f3 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2440,6 +2440,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::FMA, MVT::v32bf16, Legal); setOperationAction(ISD::SETCC, MVT::v32bf16, Custom); } + for (auto VT : {MVT::f16, MVT::f32, MVT::f64}) { + setCondCodeAction(ISD::SETOEQ, VT, Custom); + setCondCodeAction(ISD::SETUNE, VT, Custom); + } } if (!Subtarget.useSoftFloat() && Subtarget.hasVLX()) { @@ -24072,6 +24076,13 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { return IsStrict ? DAG.getMergeValues({Res, Chain}, dl) : Res; } + if (Subtarget.hasAVX10_2()) { + if (CC == ISD::SETOEQ || CC == ISD::SETUNE) { + auto NewCC = (CC == ISD::SETOEQ) ? X86::COND_E : (X86::COND_NE); + return getSETCC(NewCC, DAG.getNode(X86ISD::UCOMX, dl, MVT::i32, Op0, Op1), + dl, DAG); + } + } // Handle floating point. X86::CondCode CondCode = TranslateX86CC(CC, dl, /*IsFP*/ true, Op0, Op1, DAG); if (CondCode == X86::COND_INVALID) @@ -37409,7 +37420,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, case X86::PTDPBUSD: case X86::PTDPBUUD: case X86::PTDPBF16PS: - case X86::PTDPFP16PS: { + case X86::PTDPFP16PS: + case X86::PTDPBF8PS: + case X86::PTDPBHF8PS: + case X86::PTDPHBF8PS: + case X86::PTDPHF8PS: { unsigned Opc; switch (MI.getOpcode()) { // clang-format off @@ -37420,6 +37435,10 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, case X86::PTDPBUUD: Opc = X86::TDPBUUD; break; case X86::PTDPBF16PS: Opc = X86::TDPBF16PS; break; case X86::PTDPFP16PS: Opc = X86::TDPFP16PS; break; + case X86::PTDPBF8PS: Opc = X86::TDPBF8PS; break; + case X86::PTDPBHF8PS: Opc = X86::TDPBHF8PS; break; + case X86::PTDPHBF8PS: Opc = X86::TDPHBF8PS; break; + case X86::PTDPHF8PS: Opc = X86::TDPHF8PS; break; // clang-format on } @@ -49310,7 +49329,7 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG, if (!LogicalShift && ISD::isBuildVectorAllOnes(N0.getNode())) // N0 is all ones or undef. We guarantee that the bits shifted into the // result are all ones, not undef. - return DAG.getConstant(-1, SDLoc(N), VT); + return DAG.getAllOnesConstant(SDLoc(N), VT); auto MergeShifts = [&](SDValue X, uint64_t Amt0, uint64_t Amt1) { unsigned NewShiftVal = Amt0 + Amt1; diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td index 99deacc811a170b87d6c7c783c4d231814bec0d7..202232ccb8bc7286473123e58e3f6312b8879e3c 100644 --- a/llvm/lib/Target/X86/X86InstrAMX.td +++ b/llvm/lib/Target/X86/X86InstrAMX.td @@ -267,3 +267,42 @@ let Predicates = [HasAMXCOMPLEX, In64BitMode] in { } } // SchedRW = [WriteSystem] } + +// AMX-FP8 +let Predicates = [HasAMXFP8, In64BitMode] in { + let SchedRW = [WriteSystem] in { + let Constraints = "$src1 = $dst" in { + class AMX_FP8_BASE Opcode, string Opstr> : + I, VEX, VVVV; + } + + def TDPBF8PS : AMX_FP8_BASE<0xfd, "tdpbf8ps">, T_MAP5, PS; + def TDPBHF8PS : AMX_FP8_BASE<0xfd, "tdpbhf8ps">, T_MAP5, XD; + def TDPHBF8PS : AMX_FP8_BASE<0xfd, "tdphbf8ps">, T_MAP5, XS; + def TDPHF8PS : AMX_FP8_BASE<0xfd, "tdphf8ps">, T_MAP5, PD; + + let usesCustomInserter = 1 in { + // Pseudo instructions, using immediates instead of tile registers. + // To be translated to the actual instructions in X86ISelLowering.cpp + def PTDPBF8PS : PseudoI<(outs), + (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), + [(int_x86_tdpbf8ps timm:$src1, timm:$src2, + timm:$src3)]>; + def PTDPBHF8PS : PseudoI<(outs), + (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), + [(int_x86_tdpbhf8ps timm:$src1, timm:$src2, + timm:$src3)]>; + def PTDPHBF8PS : PseudoI<(outs), + (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), + [(int_x86_tdphbf8ps timm:$src1, timm:$src2, + timm:$src3)]>; + def PTDPHF8PS : PseudoI<(outs), + (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), + [(int_x86_tdphf8ps timm:$src1, timm:$src2, + timm:$src3)]>; + } + } +} diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td index 4d64eb776e09ceff098d73c3880f124db29f0bc3..0301c07dfb540b707280383657fe9bc94acb5aa6 100644 --- a/llvm/lib/Target/X86/X86InstrAVX10.td +++ b/llvm/lib/Target/X86/X86InstrAVX10.td @@ -1541,6 +1541,24 @@ defm VFNMSUB132NEPBF16 : avx10_fma3p_132_bf16<0x9E, "vfnmsub132nepbf16", X86any_ //------------------------------------------------- // AVX10 COMEF instructions //------------------------------------------------- +multiclass avx10_com_ef Opc, RegisterClass RC, ValueType VT, + SDPatternOperator OpNode, string OpcodeStr, + X86MemOperand x86memop, PatFrag ld_frag, + Domain d, X86FoldableSchedWrite sched = WriteFComX>{ + let ExeDomain = d, mayRaiseFPException = 1, isCodeGenOnly = 1 in { + def rr : AVX512, + EVEX, EVEX_V128, Sched<[sched]>, SIMD_EXC; + let mayLoad = 1 in { + def rm : AVX512, + EVEX, EVEX_V128, Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC; + } + } +} + multiclass avx10_com_ef_int Opc, X86VectorVTInfo _, SDNode OpNode, string OpcodeStr, Domain d, @@ -1564,6 +1582,15 @@ multiclass avx10_com_ef_int Opc, X86VectorVTInfo _, SDNode OpNode, } let Defs = [EFLAGS], Uses = [MXCSR], Predicates = [HasAVX10_2] in { + defm VUCOMXSDZ : avx10_com_ef<0x2e, FR64X, f64, X86ucomi512, + "vucomxsd", f64mem, loadf64, SSEPackedDouble>, + TB, XS, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>; + defm VUCOMXSHZ : avx10_com_ef<0x2e, FR16X, f16, X86ucomi512, + "vucomxsh", f16mem, loadf16, SSEPackedSingle>, + T_MAP5, XD, EVEX_CD8<16, CD8VT1>; + defm VUCOMXSSZ : avx10_com_ef<0x2e, FR32X, f32, X86ucomi512, + "vucomxss", f32mem, loadf32, SSEPackedSingle>, + TB, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCOMXSDZ : avx10_com_ef_int<0x2f, v2f64x_info, X86comi512, "vcomxsd", SSEPackedDouble>, TB, XS, VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>; diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td index 7fb566fba51818fed96d5d76058b4d5c35a77575..5b659d3b072dca3663e4df404d9ccc9717ab992c 100644 --- a/llvm/lib/Target/X86/X86InstrPredicates.td +++ b/llvm/lib/Target/X86/X86InstrPredicates.td @@ -183,6 +183,7 @@ def HasAMXTILE : Predicate<"Subtarget->hasAMXTILE()">; def HasAMXBF16 : Predicate<"Subtarget->hasAMXBF16()">; def HasAMXINT8 : Predicate<"Subtarget->hasAMXINT8()">; def HasAMXCOMPLEX : Predicate<"Subtarget->hasAMXCOMPLEX()">; +def HasAMXFP8 : Predicate<"Subtarget->hasAMXFP8()">; def HasUINTR : Predicate<"Subtarget->hasUINTR()">; def HasUSERMSR : Predicate<"Subtarget->hasUSERMSR()">; def HasCRC32 : Predicate<"Subtarget->hasCRC32()">; diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index bae223243b3dc98a65c3c6c9a834860c580eaf45..520284d1d7a4887620d51cac96ed1c8cce5a9e49 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -3068,6 +3068,13 @@ InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, if (auto KindCost = Entry->Cost[CostKind]) return *KindCost; } + + if ((ISD == ISD::FP_ROUND && SimpleDstTy == MVT::f16) || + (ISD == ISD::FP_EXTEND && SimpleSrcTy == MVT::f16)) { + // fp16 conversions not covered by any table entries require a libcall. + // Return a large (arbitrary) number to model this. + return InstructionCost(64); + } } // Fall back to legalized types. @@ -3174,11 +3181,6 @@ InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, TTI::CastContextHint::None, CostKind); } - if (ISD == ISD::FP_ROUND && LTDest.second.getScalarType() == MVT::f16) { - // Conversion requires a libcall. - return InstructionCost::getInvalid(); - } - // TODO: Allow non-throughput costs that aren't binary. auto AdjustCost = [&CostKind](InstructionCost Cost, InstructionCost N = 1) -> InstructionCost { diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp index eda90d3101ab4817329963fbcf7cffa6edbb4694..707c4a790872805d4c6a88c704a49338ef0fb500 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.cpp @@ -27,7 +27,7 @@ using namespace llvm; #include "XCoreGenAsmWriter.inc" -void XCoreInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { +void XCoreInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { OS << StringRef(getRegisterName(Reg)).lower(); } diff --git a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h index 916ca99968fbb0c5d880b9e01580c50351605818..2b47de457322ee27e90b2c036e6b58a78b5d36eb 100644 --- a/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h +++ b/llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h @@ -31,7 +31,7 @@ public: void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(MCRegister Reg); - void printRegName(raw_ostream &OS, MCRegister Reg) const override; + void printRegName(raw_ostream &OS, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp index fe1dc0e2e483e726ac10d7a6d50c1b964c917b1e..e04d7bd211216f2cf019631e8cae137813a4df57 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp @@ -74,7 +74,7 @@ void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address, printAnnotation(O, Annot); } -void XtensaInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const { +void XtensaInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) { O << getRegisterName(Reg); } diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h index 46a35ae6f4e3fad3c80b91172178a5f017e03591..4122b1ff2310b711aff0a03d61392123cd0c7d7b 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h @@ -36,7 +36,7 @@ public: static void printOperand(const MCOperand &MO, raw_ostream &O); // Override MCInstPrinter. - void printRegName(raw_ostream &O, MCRegister Reg) const override; + void printRegName(raw_ostream &O, MCRegister Reg) override; void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index de6c4edebba39a68ebbb6f9a452c5aaa41f497ee..fd34a276cf3ce5c94e7da01252e41204af162e76 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -68,15 +68,11 @@ using namespace llvm; static std::unique_ptr LLVM_ATTRIBUTE_UNUSED getProcCpuinfoContent() { - const char *CPUInfoFile = "/proc/cpuinfo"; - if (const char *CpuinfoIntercept = std::getenv("LLVM_CPUINFO")) - CPUInfoFile = CpuinfoIntercept; llvm::ErrorOr> Text = - llvm::MemoryBuffer::getFileAsStream(CPUInfoFile); - + llvm::MemoryBuffer::getFileAsStream("/proc/cpuinfo"); if (std::error_code EC = Text.getError()) { - llvm::errs() << "Can't read " << CPUInfoFile << ": " << EC.message() - << "\n"; + llvm::errs() << "Can't read " + << "/proc/cpuinfo: " << EC.message() << "\n"; return nullptr; } return std::move(*Text); @@ -1880,6 +1876,10 @@ const StringMap sys::getHostCPUFeatures() { MaxLevel >= 0x19 && !getX86CpuIDAndInfo(0x19, &EAX, &EBX, &ECX, &EDX); Features["widekl"] = HasLeaf7 && HasLeaf19 && ((EBX >> 2) & 1); + bool HasLeaf1E = MaxLevel >= 0x1e && + !getX86CpuIDAndInfoEx(0x1e, 0x1, &EAX, &EBX, &ECX, &EDX); + Features["amx-fp8"] = HasLeaf1E && ((EAX >> 4) & 1) && HasAMXSave; + bool HasLeaf24 = MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX); diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index bd6061fc28ccb715029da5a06d8162f3c141f27d..54acda82221f651b723ce0abf25df40039e169ea 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -751,17 +751,6 @@ Error RISCVISAInfo::checkDependency() { if (HasZvl && !HasVector) return getExtensionRequiresError("zvl*b", "v' or 'zve*"); - if (!HasVector) - for (auto Ext : - {"zvbb", "zvbc32e", "zvkb", "zvkg", "zvkgs", "zvkned", "zvknha", "zvksed", "zvksh"}) - if (Exts.count(Ext)) - return getExtensionRequiresError(Ext, "v' or 'zve*"); - - if (!Exts.count("zve64x")) - for (auto Ext : {"zvknhb", "zvbc"}) - if (Exts.count(Ext)) - return getExtensionRequiresError(Ext, "v' or 'zve64*"); - if ((HasZcmt || Exts.count("zcmp")) && HasD && (HasC || Exts.count("zcd"))) return getError(Twine("'") + (HasZcmt ? "zcmt" : "zcmp") + "' extension is incompatible with '" + diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp index 586df5748aa8229d473250498189cc2b76dc9f97..7d60b81d4bb1c3183e0585fcba1180817707ee8c 100644 --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -598,6 +598,7 @@ constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE; +constexpr FeatureBitset ImpliedFeaturesAMX_FP8 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesHRESET = {}; constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {}; diff --git a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp index 0395ee62ae988bef77ed0a07c04af2bd4491a71b..070df429bfc265594c134602d786dd514e249554 100644 --- a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp @@ -60,6 +60,7 @@ #include "llvm/Support/Casting.h" #include "llvm/Support/Debug.h" #include "llvm/Support/PrettyStackTrace.h" +#include "llvm/Support/TimeProfiler.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Transforms/Coroutines/ABI.h" #include "llvm/Transforms/Coroutines/CoroInstr.h" @@ -118,7 +119,6 @@ private: TargetTransformInfo &TTI; -public: /// Create a cloner for a switch lowering. CoroCloner(Function &OrigF, const Twine &Suffix, coro::Shape &Shape, Kind FKind, TargetTransformInfo &TTI) @@ -140,6 +140,30 @@ public: assert(ActiveSuspend && "need active suspend point for continuation"); } +public: + /// Create a clone for a switch lowering. + static Function *createClone(Function &OrigF, const Twine &Suffix, + coro::Shape &Shape, Kind FKind, + TargetTransformInfo &TTI) { + TimeTraceScope FunctionScope("CoroCloner"); + + CoroCloner Cloner(OrigF, Suffix, Shape, FKind, TTI); + Cloner.create(); + return Cloner.getFunction(); + } + + /// Create a clone for a continuation lowering. + static Function *createClone(Function &OrigF, const Twine &Suffix, + coro::Shape &Shape, Function *NewF, + AnyCoroSuspendInst *ActiveSuspend, + TargetTransformInfo &TTI) { + TimeTraceScope FunctionScope("CoroCloner"); + + CoroCloner Cloner(OrigF, Suffix, Shape, NewF, ActiveSuspend, TTI); + Cloner.create(); + return Cloner.getFunction(); + } + Function *getFunction() const { assert(NewF != nullptr && "declaration not yet set"); return NewF; @@ -1466,13 +1490,16 @@ struct SwitchCoroutineSplitter { TargetTransformInfo &TTI) { assert(Shape.ABI == coro::ABI::Switch); + // Create a resume clone by cloning the body of the original function, + // setting new entry block and replacing coro.suspend an appropriate value + // to force resume or cleanup pass for every suspend point. createResumeEntryBlock(F, Shape); - auto *ResumeClone = - createClone(F, ".resume", Shape, CoroCloner::Kind::SwitchResume, TTI); - auto *DestroyClone = - createClone(F, ".destroy", Shape, CoroCloner::Kind::SwitchUnwind, TTI); - auto *CleanupClone = - createClone(F, ".cleanup", Shape, CoroCloner::Kind::SwitchCleanup, TTI); + auto *ResumeClone = CoroCloner::createClone( + F, ".resume", Shape, CoroCloner::Kind::SwitchResume, TTI); + auto *DestroyClone = CoroCloner::createClone( + F, ".destroy", Shape, CoroCloner::Kind::SwitchUnwind, TTI); + auto *CleanupClone = CoroCloner::createClone( + F, ".cleanup", Shape, CoroCloner::Kind::SwitchCleanup, TTI); postSplitCleanup(*ResumeClone); postSplitCleanup(*DestroyClone); @@ -1562,17 +1589,6 @@ struct SwitchCoroutineSplitter { } private: - // Create a resume clone by cloning the body of the original function, setting - // new entry block and replacing coro.suspend an appropriate value to force - // resume or cleanup pass for every suspend point. - static Function *createClone(Function &F, const Twine &Suffix, - coro::Shape &Shape, CoroCloner::Kind FKind, - TargetTransformInfo &TTI) { - CoroCloner Cloner(F, Suffix, Shape, FKind, TTI); - Cloner.create(); - return Cloner.getFunction(); - } - // Create an entry block for a resume function with a switch that will jump to // suspend points. static void createResumeEntryBlock(Function &F, coro::Shape &Shape) { @@ -1872,7 +1888,8 @@ void coro::AsyncABI::splitCoroutine(Function &F, coro::Shape &Shape, auto *Suspend = Shape.CoroSuspends[Idx]; auto *Clone = Clones[Idx]; - CoroCloner(F, "resume." + Twine(Idx), Shape, Clone, Suspend, TTI).create(); + CoroCloner::createClone(F, "resume." + Twine(Idx), Shape, Clone, Suspend, + TTI); } } @@ -2001,7 +2018,8 @@ void coro::AnyRetconABI::splitCoroutine(Function &F, coro::Shape &Shape, auto Suspend = Shape.CoroSuspends[i]; auto Clone = Clones[i]; - CoroCloner(F, "resume." + Twine(i), Shape, Clone, Suspend, TTI).create(); + CoroCloner::createClone(F, "resume." + Twine(i), Shape, Clone, Suspend, + TTI); } } diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp index 3fcfc6a876776d9c09b96aad2ece782f18910b85..9369b91d9c7f1896619c2ea0c38681824634c7e5 100644 --- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp +++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp @@ -118,10 +118,16 @@ static cl::opt ClWriteSummary( cl::desc("Write summary to given YAML file after running pass"), cl::Hidden); -static cl::opt +static cl::opt ClDropTypeTests("lowertypetests-drop-type-tests", - cl::desc("Simply drop type test assume sequences"), - cl::Hidden, cl::init(false)); + cl::desc("Simply drop type test sequences"), + cl::values(clEnumValN(DropTestKind::None, "none", + "Do not drop any type tests"), + clEnumValN(DropTestKind::Assume, "assume", + "Drop type test assume sequences"), + clEnumValN(DropTestKind::All, "all", + "Drop all type test sequences")), + cl::Hidden, cl::init(DropTestKind::None)); bool BitSetInfo::containsGlobalOffset(uint64_t Offset) const { if (Offset < ByteOffset) @@ -399,7 +405,7 @@ class LowerTypeTestsModule { const ModuleSummaryIndex *ImportSummary; // Set when the client has invoked this to simply drop all type test assume // sequences. - bool DropTypeTests; + DropTestKind DropTypeTests; Triple::ArchType Arch; Triple::OSType OS; @@ -542,7 +548,7 @@ public: LowerTypeTestsModule(Module &M, ModuleAnalysisManager &AM, ModuleSummaryIndex *ExportSummary, const ModuleSummaryIndex *ImportSummary, - bool DropTypeTests); + DropTestKind DropTypeTests); bool lower(); @@ -1828,9 +1834,10 @@ void LowerTypeTestsModule::buildBitSetsFromDisjointSet( /// Lower all type tests in this module. LowerTypeTestsModule::LowerTypeTestsModule( Module &M, ModuleAnalysisManager &AM, ModuleSummaryIndex *ExportSummary, - const ModuleSummaryIndex *ImportSummary, bool DropTypeTests) + const ModuleSummaryIndex *ImportSummary, DropTestKind DropTypeTests) : M(M), ExportSummary(ExportSummary), ImportSummary(ImportSummary), - DropTypeTests(DropTypeTests || ClDropTypeTests) { + DropTypeTests(ClDropTypeTests > DropTypeTests ? ClDropTypeTests + : DropTypeTests) { assert(!(ExportSummary && ImportSummary)); Triple TargetTriple(M.getTargetTriple()); Arch = TargetTriple.getArch(); @@ -1882,7 +1889,7 @@ bool LowerTypeTestsModule::runForTesting(Module &M, ModuleAnalysisManager &AM) { M, AM, ClSummaryAction == PassSummaryAction::Export ? &Summary : nullptr, ClSummaryAction == PassSummaryAction::Import ? &Summary : nullptr, - /*DropTypeTests*/ false) + /*DropTypeTests=*/DropTestKind::None) .lower(); if (!ClWriteSummary.empty()) { @@ -1949,7 +1956,8 @@ void LowerTypeTestsModule::replaceDirectCalls(Value *Old, Value *New) { Old->replaceUsesWithIf(New, isDirectCall); } -static void dropTypeTests(Module &M, Function &TypeTestFunc) { +static void dropTypeTests(Module &M, Function &TypeTestFunc, + bool ShouldDropAll) { for (Use &U : llvm::make_early_inc_range(TypeTestFunc.uses())) { auto *CI = cast(U.getUser()); // Find and erase llvm.assume intrinsics for this llvm.type.test call. @@ -1959,9 +1967,13 @@ static void dropTypeTests(Module &M, Function &TypeTestFunc) { // If the assume was merged with another assume, we might have a use on a // phi (which will feed the assume). Simply replace the use on the phi // with "true" and leave the merged assume. + // + // If ShouldDropAll is set, then we we need to update any remaining uses, + // regardless of the instruction type. if (!CI->use_empty()) { - assert( - all_of(CI->users(), [](User *U) -> bool { return isa(U); })); + assert(ShouldDropAll || all_of(CI->users(), [](User *U) -> bool { + return isa(U); + })); CI->replaceAllUsesWith(ConstantInt::getTrue(M.getContext())); } CI->eraseFromParent(); @@ -1972,16 +1984,17 @@ bool LowerTypeTestsModule::lower() { Function *TypeTestFunc = Intrinsic::getDeclarationIfExists(&M, Intrinsic::type_test); - if (DropTypeTests) { + if (DropTypeTests != DropTestKind::None) { + bool ShouldDropAll = DropTypeTests == DropTestKind::All; if (TypeTestFunc) - dropTypeTests(M, *TypeTestFunc); + dropTypeTests(M, *TypeTestFunc, ShouldDropAll); // Normally we'd have already removed all @llvm.public.type.test calls, // except for in the case where we originally were performing ThinLTO but // decided not to in the backend. Function *PublicTypeTestFunc = Intrinsic::getDeclarationIfExists(&M, Intrinsic::public_type_test); if (PublicTypeTestFunc) - dropTypeTests(M, *PublicTypeTestFunc); + dropTypeTests(M, *PublicTypeTestFunc, ShouldDropAll); if (TypeTestFunc || PublicTypeTestFunc) { // We have deleted the type intrinsics, so we no longer have enough // information to reason about the liveness of virtual function pointers diff --git a/llvm/lib/Transforms/Utils/CloneFunction.cpp b/llvm/lib/Transforms/Utils/CloneFunction.cpp index 5dc82a8dfb2dbed92f11f09140dbc2e13e9997b8..a2d38717f38d14de59cb5e8e763d506814342e77 100644 --- a/llvm/lib/Transforms/Utils/CloneFunction.cpp +++ b/llvm/lib/Transforms/Utils/CloneFunction.cpp @@ -87,28 +87,14 @@ BasicBlock *llvm::CloneBasicBlock(const BasicBlock *BB, ValueToValueMapTy &VMap, return NewBB; } -// Clone OldFunc into NewFunc, transforming the old arguments into references to -// VMap values. -// -void llvm::CloneFunctionInto(Function *NewFunc, const Function *OldFunc, - ValueToValueMapTy &VMap, - CloneFunctionChangeType Changes, - SmallVectorImpl &Returns, - const char *NameSuffix, ClonedCodeInfo *CodeInfo, - ValueMapTypeRemapper *TypeMapper, - ValueMaterializer *Materializer) { - NewFunc->setIsNewDbgInfoFormat(OldFunc->IsNewDbgInfoFormat); - assert(NameSuffix && "NameSuffix cannot be null!"); - -#ifndef NDEBUG - for (const Argument &I : OldFunc->args()) - assert(VMap.count(&I) && "No mapping from source argument specified!"); -#endif - - bool ModuleLevelChanges = Changes > CloneFunctionChangeType::LocalChangesOnly; - - // Copy all attributes other than those stored in the AttributeList. We need - // to remap the parameter indices of the AttributeList. +void llvm::CloneFunctionAttributesInto(Function *NewFunc, + const Function *OldFunc, + ValueToValueMapTy &VMap, + bool ModuleLevelChanges, + ValueMapTypeRemapper *TypeMapper, + ValueMaterializer *Materializer) { + // Copy all attributes other than those stored in Function's AttributeList + // which holds e.g. parameters and return value attributes. AttributeList NewAttrs = NewFunc->getAttributes(); NewFunc->copyAttributesFrom(OldFunc); NewFunc->setAttributes(NewAttrs); @@ -140,6 +126,7 @@ void llvm::CloneFunctionInto(Function *NewFunc, const Function *OldFunc, // Clone any argument attributes that are present in the VMap. for (const Argument &OldArg : OldFunc->args()) { if (Argument *NewArg = dyn_cast(VMap[&OldArg])) { + // Remap the parameter indices. NewArgAttrs[NewArg->getArgNo()] = OldAttrs.getParamAttrs(OldArg.getArgNo()); } @@ -148,6 +135,29 @@ void llvm::CloneFunctionInto(Function *NewFunc, const Function *OldFunc, NewFunc->setAttributes( AttributeList::get(NewFunc->getContext(), OldAttrs.getFnAttrs(), OldAttrs.getRetAttrs(), NewArgAttrs)); +} + +// Clone OldFunc into NewFunc, transforming the old arguments into references to +// VMap values. +void llvm::CloneFunctionInto(Function *NewFunc, const Function *OldFunc, + ValueToValueMapTy &VMap, + CloneFunctionChangeType Changes, + SmallVectorImpl &Returns, + const char *NameSuffix, ClonedCodeInfo *CodeInfo, + ValueMapTypeRemapper *TypeMapper, + ValueMaterializer *Materializer) { + NewFunc->setIsNewDbgInfoFormat(OldFunc->IsNewDbgInfoFormat); + assert(NameSuffix && "NameSuffix cannot be null!"); + +#ifndef NDEBUG + for (const Argument &I : OldFunc->args()) + assert(VMap.count(&I) && "No mapping from source argument specified!"); +#endif + + bool ModuleLevelChanges = Changes > CloneFunctionChangeType::LocalChangesOnly; + + CloneFunctionAttributesInto(NewFunc, OldFunc, VMap, ModuleLevelChanges, + TypeMapper, Materializer); // Everything else beyond this point deals with function instructions, // so if we are dealing with a function declaration, we're done. diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp index 4ad426285ce2f016dd0d7a27a676c0e9c2c3c815..a27cb4dd219c306fe2596c6c242251c93903addf 100644 --- a/llvm/lib/Transforms/Utils/InlineFunction.cpp +++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp @@ -181,9 +181,21 @@ namespace { } } }; - } // end anonymous namespace +static IntrinsicInst *getConvergenceEntry(BasicBlock &BB) { + auto *I = BB.getFirstNonPHI(); + while (I) { + if (auto *IntrinsicCall = dyn_cast(I)) { + if (IntrinsicCall->isEntry()) { + return IntrinsicCall; + } + } + I = I->getNextNode(); + } + return nullptr; +} + /// Get or create a target for the branch from ResumeInsts. BasicBlock *LandingPadInliningInfo::getInnerResumeDest() { if (InnerResumeDest) return InnerResumeDest; @@ -2496,15 +2508,10 @@ llvm::InlineResult llvm::InlineFunction(CallBase &CB, InlineFunctionInfo &IFI, // fully implements convergence control tokens, there is no mixing of // controlled and uncontrolled convergent operations in the whole program. if (CB.isConvergent()) { - auto *I = CalledFunc->getEntryBlock().getFirstNonPHI(); - if (auto *IntrinsicCall = dyn_cast(I)) { - if (IntrinsicCall->getIntrinsicID() == - Intrinsic::experimental_convergence_entry) { - if (!ConvergenceControlToken) { - return InlineResult::failure( - "convergent call needs convergencectrl operand"); - } - } + if (!ConvergenceControlToken && + getConvergenceEntry(CalledFunc->getEntryBlock())) { + return InlineResult::failure( + "convergent call needs convergencectrl operand"); } } @@ -2795,13 +2802,10 @@ llvm::InlineResult llvm::InlineFunction(CallBase &CB, InlineFunctionInfo &IFI, } if (ConvergenceControlToken) { - auto *I = FirstNewBlock->getFirstNonPHI(); - if (auto *IntrinsicCall = dyn_cast(I)) { - if (IntrinsicCall->getIntrinsicID() == - Intrinsic::experimental_convergence_entry) { - IntrinsicCall->replaceAllUsesWith(ConvergenceControlToken); - IntrinsicCall->eraseFromParent(); - } + IntrinsicInst *IntrinsicCall = getConvergenceEntry(*FirstNewBlock); + if (IntrinsicCall) { + IntrinsicCall->replaceAllUsesWith(ConvergenceControlToken); + IntrinsicCall->eraseFromParent(); } } diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 02583a6022e6d6a3c4d91a0577257ac726d3b819..8e7e2942d97b1a05e56f7e7f6b4b4c470a8c1b05 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -491,11 +491,12 @@ public: ElementCount MinProfitableTripCount, unsigned UnrollFactor, LoopVectorizationLegality *LVL, LoopVectorizationCostModel *CM, BlockFrequencyInfo *BFI, - ProfileSummaryInfo *PSI, GeneratedRTChecks &RTChecks) + ProfileSummaryInfo *PSI, GeneratedRTChecks &RTChecks, + VPlan &Plan) : OrigLoop(OrigLoop), PSE(PSE), LI(LI), DT(DT), TLI(TLI), TTI(TTI), AC(AC), ORE(ORE), VF(VecWidth), UF(UnrollFactor), Builder(PSE.getSE()->getContext()), Legal(LVL), Cost(CM), BFI(BFI), - PSI(PSI), RTChecks(RTChecks) { + PSI(PSI), RTChecks(RTChecks), Plan(Plan) { // Query this against the original loop and save it here because the profile // of the original loop header may change as the transformation happens. OptForSizeBasedOnProfile = llvm::shouldOptimizeForSize( @@ -528,7 +529,7 @@ public: VPValue *BlockInMask, VPValue *EVL); /// Fix the vectorized code, taking care of header phi's, live-outs, and more. - void fixVectorizedLoop(VPTransformState &State, VPlan &Plan); + void fixVectorizedLoop(VPTransformState &State); // Return true if any runtime check is added. bool areSafetyChecksAdded() { return AddedSafetyChecks; } @@ -543,7 +544,7 @@ public: VPTransformState &State); /// Fix the non-induction PHIs in \p Plan. - void fixNonInductionPHIs(VPlan &Plan, VPTransformState &State); + void fixNonInductionPHIs(VPTransformState &State); /// Create a new phi node for the induction variable \p OrigPhi to resume /// iteration count in the scalar epilogue, from where the vectorized loop @@ -578,8 +579,7 @@ protected: /// Set up the values of the IVs correctly when exiting the vector loop. virtual void fixupIVUsers(PHINode *OrigPhi, const InductionDescriptor &II, Value *VectorTripCount, Value *EndValue, - BasicBlock *MiddleBlock, VPlan &Plan, - VPTransformState &State); + BasicBlock *MiddleBlock, VPTransformState &State); /// Iteratively sink the scalarized operands of a predicated instruction into /// the block that was created for it. @@ -618,8 +618,8 @@ protected: /// Allow subclasses to override and print debug traces before/after vplan /// execution, when trace information is requested. - virtual void printDebugTracesAtStart(){}; - virtual void printDebugTracesAtEnd(){}; + virtual void printDebugTracesAtStart() {} + virtual void printDebugTracesAtEnd() {} /// The original loop. Loop *OrigLoop; @@ -716,6 +716,8 @@ protected: // correct start value of reduction PHIs when vectorizing the epilogue. SmallMapVector ReductionResumeValues; + + VPlan &Plan; }; /// Encapsulate information regarding vectorization of a loop and its epilogue. @@ -757,10 +759,10 @@ public: OptimizationRemarkEmitter *ORE, EpilogueLoopVectorizationInfo &EPI, LoopVectorizationLegality *LVL, llvm::LoopVectorizationCostModel *CM, BlockFrequencyInfo *BFI, ProfileSummaryInfo *PSI, - GeneratedRTChecks &Checks) + GeneratedRTChecks &Checks, VPlan &Plan) : InnerLoopVectorizer(OrigLoop, PSE, LI, DT, TLI, TTI, AC, ORE, EPI.MainLoopVF, EPI.MainLoopVF, EPI.MainLoopUF, LVL, - CM, BFI, PSI, Checks), + CM, BFI, PSI, Checks, Plan), EPI(EPI) {} // Override this function to handle the more complex control flow around the @@ -797,9 +799,9 @@ public: OptimizationRemarkEmitter *ORE, EpilogueLoopVectorizationInfo &EPI, LoopVectorizationLegality *LVL, llvm::LoopVectorizationCostModel *CM, BlockFrequencyInfo *BFI, ProfileSummaryInfo *PSI, - GeneratedRTChecks &Check) + GeneratedRTChecks &Check, VPlan &Plan) : InnerLoopAndEpilogueVectorizer(OrigLoop, PSE, LI, DT, TLI, TTI, AC, ORE, - EPI, LVL, CM, BFI, PSI, Check) {} + EPI, LVL, CM, BFI, PSI, Check, Plan) {} /// Implements the interface for creating a vectorized skeleton using the /// *main loop* strategy (ie the first pass of vplan execution). std::pair @@ -815,7 +817,7 @@ protected: void fixupIVUsers(PHINode *OrigPhi, const InductionDescriptor &II, Value *VectorTripCount, Value *EndValue, - BasicBlock *MiddleBlock, VPlan &Plan, + BasicBlock *MiddleBlock, VPTransformState &State) override {}; }; @@ -831,9 +833,9 @@ public: OptimizationRemarkEmitter *ORE, EpilogueLoopVectorizationInfo &EPI, LoopVectorizationLegality *LVL, llvm::LoopVectorizationCostModel *CM, BlockFrequencyInfo *BFI, ProfileSummaryInfo *PSI, - GeneratedRTChecks &Checks) + GeneratedRTChecks &Checks, VPlan &Plan) : InnerLoopAndEpilogueVectorizer(OrigLoop, PSE, LI, DT, TLI, TTI, AC, ORE, - EPI, LVL, CM, BFI, PSI, Checks) { + EPI, LVL, CM, BFI, PSI, Checks, Plan) { TripCount = EPI.TripCount; } /// Implements the interface for creating a vectorized skeleton using the @@ -1378,7 +1380,7 @@ public: return false; case cl::BOU_FALSE: return true; - }; + } llvm_unreachable("impossible case value"); } @@ -2899,7 +2901,7 @@ InnerLoopVectorizer::createVectorizedLoopSkeleton( void InnerLoopVectorizer::fixupIVUsers(PHINode *OrigPhi, const InductionDescriptor &II, Value *VectorTripCount, Value *EndValue, - BasicBlock *MiddleBlock, VPlan &Plan, + BasicBlock *MiddleBlock, VPTransformState &State) { // There are two kinds of external IV usages - those that use the value // computed in the last iteration (the PHI) and those that use the penultimate @@ -3147,11 +3149,10 @@ InstructionCost LoopVectorizationCostModel::getVectorIntrinsicCost( TargetTransformInfo::TCK_RecipThroughput); } -void InnerLoopVectorizer::fixVectorizedLoop(VPTransformState &State, - VPlan &Plan) { +void InnerLoopVectorizer::fixVectorizedLoop(VPTransformState &State) { // Fix widened non-induction PHIs by setting up the PHI operands. if (EnableVPlanNativePath || EPIVPlanNativePath) - fixNonInductionPHIs(Plan, State); + fixNonInductionPHIs(State); // Forget the original basic block. PSE.getSE()->forgetLoop(OrigLoop); @@ -3182,7 +3183,7 @@ void InnerLoopVectorizer::fixVectorizedLoop(VPTransformState &State, for (const auto &Entry : Legal->getInductionVars()) fixupIVUsers(Entry.first, Entry.second, getOrCreateVectorTripCount(nullptr), - IVEndValues[Entry.first], LoopMiddleBlock, Plan, State); + IVEndValues[Entry.first], LoopMiddleBlock, State); } // Fix live-out phis not already fixed earlier. @@ -3293,8 +3294,7 @@ void InnerLoopVectorizer::sinkScalarOperands(Instruction *PredInst) { } while (Changed); } -void InnerLoopVectorizer::fixNonInductionPHIs(VPlan &Plan, - VPTransformState &State) { +void InnerLoopVectorizer::fixNonInductionPHIs(VPTransformState &State) { auto Iter = vp_depth_first_deep(Plan.getEntry()); for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly(Iter)) { for (VPRecipeBase &P : VPBB->phis()) { @@ -8538,7 +8538,7 @@ DenseMap LoopVectorizationPlanner::executePlan( // 3. Fix the vectorized code: take care of header phi's, live-outs, // predication, updating analyses. - ILV.fixVectorizedLoop(State, BestVPlan); + ILV.fixVectorizedLoop(State); ILV.printDebugTracesAtEnd(); @@ -10216,7 +10216,7 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) { if (!getDecisionAndClampRange(ApplyIG, Range)) continue; InterleaveGroups.insert(IG); - }; + } // --------------------------------------------------------------------------- // Construct recipes for the instructions in the loop @@ -11125,7 +11125,7 @@ static bool processLoopInVPlanNativePath( GeneratedRTChecks Checks(PSE, DT, LI, TTI, F->getParent()->getDataLayout(), AddBranchWeights); InnerLoopVectorizer LB(L, PSE, LI, DT, TLI, TTI, AC, ORE, VF.Width, - VF.Width, 1, LVL, &CM, BFI, PSI, Checks); + VF.Width, 1, LVL, &CM, BFI, PSI, Checks, BestPlan); LLVM_DEBUG(dbgs() << "Vectorizing outer loop in \"" << L->getHeader()->getParent()->getName() << "\"\n"); LVP.executePlan(VF.Width, 1, BestPlan, LB, DT, false); @@ -11308,13 +11308,14 @@ static bool processLoopInEPIVPlanNativePath( return false; } } + VPlan &BestPlan = LVP.getBestPlan(); InnerLoopVectorizer LB(L, PSE, LI, DT, TLI, TTI, AC, ORE, VF.Width, VF.MinProfitableTripCount, UserIC, LVL, &CM, BFI, - PSI, Checks); + PSI, Checks, BestPlan); LLVM_DEBUG(dbgs() << "Select vectorization factor " << VF.Width << ".\n"); LLVM_DEBUG(dbgs() << "Vectorizing loop in \"" << L->getHeader()->getParent()->getName() << "\"\n"); - LVP.executePlan(VF.Width, UserIC, LVP.getBestPlan(), LB, DT, false); + LVP.executePlan(VF.Width, UserIC, BestPlan, LB, DT, false); } reportVectorization(ORE, L, VF, 1); @@ -11840,11 +11841,11 @@ bool LoopVectorizePass::processLoop(Loop *L) { assert(IC > 1 && "interleave count should not be 1 or 0"); // If we decided that it is not legal to vectorize the loop, then // interleave it. + VPlan &BestPlan = LVP.getPlanFor(VF.Width); InnerLoopVectorizer Unroller( L, PSE, LI, DT, TLI, TTI, AC, ORE, ElementCount::getFixed(1), - ElementCount::getFixed(1), IC, &LVL, &CM, BFI, PSI, Checks); + ElementCount::getFixed(1), IC, &LVL, &CM, BFI, PSI, Checks, BestPlan); - VPlan &BestPlan = LVP.getPlanFor(VF.Width); LVP.executePlan(VF.Width, IC, BestPlan, Unroller, DT, false); ORE->emit([&]() { @@ -11862,15 +11863,16 @@ bool LoopVectorizePass::processLoop(Loop *L) { LVP.selectEpilogueVectorizationFactor(VF.Width, IC); if (EpilogueVF != VectorizationFactor::Disabled() && EpilogueVF.Width.isVector()) { + std::unique_ptr BestMainPlan(BestPlan.duplicate()); // The first pass vectorizes the main loop and creates a scalar epilogue // to be vectorized by executing the plan (potentially with a different // factor) again shortly afterwards. EpilogueLoopVectorizationInfo EPI(VF.Width, IC, EpilogueVF.Width, 1); EpilogueVectorizerMainLoop MainILV(L, PSE, LI, DT, TLI, TTI, AC, ORE, - EPI, &LVL, &CM, BFI, PSI, Checks); + EPI, &LVL, &CM, BFI, PSI, Checks, + *BestMainPlan); - std::unique_ptr BestMainPlan(BestPlan.duplicate()); auto ExpandedSCEVs = LVP.executePlan(EPI.MainLoopVF, EPI.MainLoopUF, *BestMainPlan, MainILV, DT, false); ++LoopsVectorized; @@ -11879,11 +11881,11 @@ bool LoopVectorizePass::processLoop(Loop *L) { // edges from the first pass. EPI.MainLoopVF = EPI.EpilogueVF; EPI.MainLoopUF = EPI.EpilogueUF; + VPlan &BestEpiPlan = LVP.getPlanFor(EPI.EpilogueVF); EpilogueVectorizerEpilogueLoop EpilogILV(L, PSE, LI, DT, TLI, TTI, AC, ORE, EPI, &LVL, &CM, BFI, PSI, - Checks); + Checks, BestEpiPlan); - VPlan &BestEpiPlan = LVP.getPlanFor(EPI.EpilogueVF); VPRegionBlock *VectorLoop = BestEpiPlan.getVectorLoopRegion(); VPBasicBlock *Header = VectorLoop->getEntryBasicBlock(); Header->setName("vec.epilog.vector.body"); @@ -11972,7 +11974,7 @@ bool LoopVectorizePass::processLoop(Loop *L) { } else { InnerLoopVectorizer LB(L, PSE, LI, DT, TLI, TTI, AC, ORE, VF.Width, VF.MinProfitableTripCount, IC, &LVL, &CM, BFI, - PSI, Checks); + PSI, Checks, BestPlan); LVP.executePlan(VF.Width, IC, BestPlan, LB, DT, false); ++LoopsVectorized; diff --git a/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp b/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp index 346d8a90589f55504b01d809dcd53c670239b6e6..1cc6356300e492bd2a0a29ed3c46ebf485737e10 100644 --- a/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp +++ b/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Legality.cpp @@ -55,6 +55,21 @@ LegalityAnalysis::notVectorizableBasedOnOpcodesAndTypes( return ResultReason::DiffMathFlags; } + // TODO: Allow vectorization by using common flags. + // For now Pack if they don't have the same wrap flags. + bool CanHaveWrapFlags = + isa(I0) || isa(I0); + if (CanHaveWrapFlags) { + bool NUW0 = I0->hasNoUnsignedWrap(); + bool NSW0 = I0->hasNoSignedWrap(); + if (any_of(drop_begin(Bndl), [NUW0, NSW0](auto *V) { + return cast(V)->hasNoUnsignedWrap() != NUW0 || + cast(V)->hasNoSignedWrap() != NSW0; + })) { + return ResultReason::DiffWrapFlags; + } + } + // TODO: Missing checks return std::nullopt; diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 20e52d4ecd1670f724dd86db37ad3b7988fe755a..f577c74c4ed17ef8c4e9c58c6f7ab07d0a913c1c 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -1840,13 +1840,18 @@ public: VPWidenIntrinsicRecipe(Intrinsic::ID VectorIntrinsicID, ArrayRef CallArguments, Type *Ty, - bool MayReadFromMemory, bool MayWriteToMemory, - bool MayHaveSideEffects, DebugLoc DL = {}) + DebugLoc DL = {}) : VPRecipeWithIRFlags(VPDef::VPWidenIntrinsicSC, CallArguments), - VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty), - MayReadFromMemory(MayReadFromMemory), - MayWriteToMemory(MayWriteToMemory), - MayHaveSideEffects(MayHaveSideEffects) {} + VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty) { + LLVMContext &Ctx = Ty->getContext(); + AttributeList Attrs = Intrinsic::getAttributes(Ctx, VectorIntrinsicID); + MemoryEffects ME = Attrs.getMemoryEffects(); + MayReadFromMemory = ME.onlyWritesMemory(); + MayWriteToMemory = ME.onlyReadsMemory(); + MayHaveSideEffects = MayWriteToMemory || + !Attrs.hasFnAttr(Attribute::NoUnwind) || + !Attrs.hasFnAttr(Attribute::WillReturn); + } ~VPWidenIntrinsicRecipe() override = default; @@ -2446,6 +2451,10 @@ public: /// Generate the phi nodes. void execute(VPTransformState &State) override = 0; + /// Return the cost of this header phi recipe. + InstructionCost computeCost(ElementCount VF, + VPCostContext &Ctx) const override; + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) /// Print the recipe. void print(raw_ostream &O, const Twine &Indent, @@ -2873,6 +2882,11 @@ struct VPFirstOrderRecurrencePHIRecipe : public VPHeaderPHIRecipe { void execute(VPTransformState &State) override; + /// Return the cost of this first-order recurrence phi recipe. + InstructionCost computeCost(ElementCount VF, + VPCostContext &Ctx) const override; + + // This might be redundant now? InstructionCost cost(VPlanContext &VPCtx, ElementCount VF, TargetTransformInfo::TargetCostKind CostKind) override; @@ -4174,6 +4188,13 @@ public: /// canonical, i.e. has the same start and step (of 1) as the canonical IV. bool isCanonical(InductionDescriptor::InductionKind Kind, VPValue *Start, VPValue *Step) const; + + /// Return the cost of this VPCanonicalIVPHIRecipe. + InstructionCost computeCost(ElementCount VF, + VPCostContext &Ctx) const override { + // For now, match the behavior of the legacy cost model. + return 0; + } }; /// A recipe for generating the active lane mask for the vector loop that is @@ -4271,6 +4292,13 @@ public: /// TODO: investigate if it can share the code with VPCanonicalIVPHIRecipe. void execute(VPTransformState &State) override; + /// Return the cost of this VPEVLBasedIVPHIRecipe. + InstructionCost computeCost(ElementCount VF, + VPCostContext &Ctx) const override { + // For now, match the behavior of the legacy cost model. + return 0; + } + /// Returns true if the recipe only uses the first lane of operand \p Op. bool onlyFirstLaneUsed(const VPValue *Op) const override { assert(is_contained(operands(), Op) && diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index 58d2103eb9a1c60a100f5e231bb3f9079a699bfa..bdb4344b8743b3b2f955f3a889d0b0d7c2e09e02 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -2610,6 +2610,11 @@ void EPIVPWidenRecipe::print(raw_ostream &O, const Twine &Indent, } #endif +InstructionCost VPHeaderPHIRecipe::computeCost(ElementCount VF, + VPCostContext &Ctx) const { + return Ctx.TTI.getCFInstrCost(Instruction::PHI, TTI::TCK_RecipThroughput); +} + /// This function adds /// (StartIdx * Step, (StartIdx + 1) * Step, (StartIdx + 2) * Step, ...) /// to each vector element of Val. The sequence starts at StartIndex. @@ -5543,6 +5548,23 @@ VPFirstOrderRecurrencePHIRecipe::cost(VPlanContext &VPCtx, ElementCount VF, return VPCtx.TTI.getCFInstrCost(Instruction::PHI, CostKind); } +InstructionCost +VPFirstOrderRecurrencePHIRecipe::computeCost(ElementCount VF, + VPCostContext &Ctx) const { + if (VF.isScalable() && VF.getKnownMinValue() == 1) + return InstructionCost::getInvalid(); + + SmallVector Mask(VF.getKnownMinValue()); + std::iota(Mask.begin(), Mask.end(), VF.getKnownMinValue() - 1); + Type *VectorTy = + ToVectorTy(Ctx.Types.inferScalarType(this->getVPSingleValue()), VF); + + TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; + return Ctx.TTI.getShuffleCost(TargetTransformInfo::SK_Splice, + cast(VectorTy), Mask, CostKind, + VF.getKnownMinValue() - 1); +} + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) void VPFirstOrderRecurrencePHIRecipe::print(raw_ostream &O, const Twine &Indent, VPSlotTracker &SlotTracker) const { diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index 566177ebf54c7ffb910ec9771477f737c99f2e4a..5d188f5beac01a3cba205f5fd69f3a3aea5fbb41 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -2065,7 +2065,7 @@ static void transformRecipestoEVLRecipes(VPlan &Plan, VPValue &EVL) { Ops.push_back(&EVL); return new VPWidenIntrinsicRecipe(Intrinsic::vp_select, Ops, TypeInfo.inferScalarType(Sel), - false, false, false); + Sel->getDebugLoc()); }) .Default([&](VPRecipeBase *R) { return nullptr; }); diff --git a/llvm/test/Analysis/CostModel/RISCV/fround.ll b/llvm/test/Analysis/CostModel/RISCV/fround.ll index c6826760a45bee69773aab2dd774aa3e1ebab05c..b0964983550814cb6f59d201a0cd20479cfc07a4 100644 --- a/llvm/test/Analysis/CostModel/RISCV/fround.ll +++ b/llvm/test/Analysis/CostModel/RISCV/fround.ll @@ -425,15 +425,15 @@ define void @rint_fp16() { define void @lrint() { ; CHECK-LABEL: 'lrint' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i64 @llvm.lrint.i64.bf16(bfloat undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i64> @llvm.lrint.v2i64.v2bf16(<2 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i64> @llvm.lrint.v4i64.v4bf16(<4 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i64> @llvm.lrint.v8i64.v8bf16(<8 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = call <16 x i64> @llvm.lrint.v16i64.v16bf16(<16 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = call @llvm.lrint.nxv1i64.nxv1bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call @llvm.lrint.nxv2i64.nxv2bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call @llvm.lrint.nxv4i64.nxv4bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call @llvm.lrint.nxv8i64.nxv8bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call @llvm.lrint.nxv16i64.nxv16bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %2 = call <2 x i64> @llvm.lrint.v2i64.v2bf16(<2 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %3 = call <4 x i64> @llvm.lrint.v4i64.v4bf16(<4 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %4 = call <8 x i64> @llvm.lrint.v8i64.v8bf16(<8 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %5 = call <16 x i64> @llvm.lrint.v16i64.v16bf16(<16 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.lrint.nxv1i64.nxv1bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.lrint.nxv2i64.nxv2bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.lrint.nxv4i64.nxv4bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.lrint.nxv8i64.nxv8bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.lrint.nxv16i64.nxv16bf16( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %11 = call i64 @llvm.lrint.i64.f32(float undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %12 = call <2 x i64> @llvm.lrint.v2i64.v2f32(<2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = call <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float> undef) @@ -490,15 +490,15 @@ define void @lrint() { define void @lrint_fp16() { ; CHECK-LABEL: 'lrint_fp16' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i64 @llvm.lrint.i64.f16(half undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = call <16 x i64> @llvm.lrint.v16i64.v16f16(<16 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = call @llvm.lrint.nxv1i64.nxv1f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call @llvm.lrint.nxv2i64.nxv2f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call @llvm.lrint.nxv4i64.nxv4f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call @llvm.lrint.nxv8i64.nxv8f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call @llvm.lrint.nxv16i64.nxv16f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %2 = call <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %3 = call <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %4 = call <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %5 = call <16 x i64> @llvm.lrint.v16i64.v16f16(<16 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.lrint.nxv1i64.nxv1f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.lrint.nxv2i64.nxv2f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.lrint.nxv4i64.nxv4f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.lrint.nxv8i64.nxv8f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.lrint.nxv16i64.nxv16f16( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; call i64 @llvm.lrint.f16(half undef) @@ -517,15 +517,15 @@ define void @lrint_fp16() { define void @llrint() { ; CHECK-LABEL: 'llrint' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i64 @llvm.llrint.i64.bf16(bfloat undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i64> @llvm.llrint.v2i64.v2bf16(<2 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i64> @llvm.llrint.v4i64.v4bf16(<4 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i64> @llvm.llrint.v8i64.v8bf16(<8 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = call <16 x i64> @llvm.llrint.v16i64.v16bf16(<16 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = call @llvm.llrint.nxv1i64.nxv1bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call @llvm.llrint.nxv2i64.nxv2bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call @llvm.llrint.nxv4i64.nxv4bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call @llvm.llrint.nxv8i64.nxv8bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call @llvm.llrint.nxv16i64.nxv16bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %2 = call <2 x i64> @llvm.llrint.v2i64.v2bf16(<2 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %3 = call <4 x i64> @llvm.llrint.v4i64.v4bf16(<4 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %4 = call <8 x i64> @llvm.llrint.v8i64.v8bf16(<8 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %5 = call <16 x i64> @llvm.llrint.v16i64.v16bf16(<16 x bfloat> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.llrint.nxv1i64.nxv1bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.llrint.nxv2i64.nxv2bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.llrint.nxv4i64.nxv4bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.llrint.nxv8i64.nxv8bf16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.llrint.nxv16i64.nxv16bf16( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %11 = call i64 @llvm.llrint.i64.f32(float undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %12 = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> undef) @@ -582,15 +582,15 @@ define void @llrint() { define void @llrint_fp16() { ; CHECK-LABEL: 'llrint_fp16' ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %1 = call i64 @llvm.llrint.i64.f16(half undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %5 = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %6 = call @llvm.llrint.nxv1i64.nxv1f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call @llvm.llrint.nxv2i64.nxv2f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call @llvm.llrint.nxv4i64.nxv4f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call @llvm.llrint.nxv8i64.nxv8f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call @llvm.llrint.nxv16i64.nxv16f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %2 = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %3 = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %4 = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %5 = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %6 = call @llvm.llrint.nxv1i64.nxv1f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %7 = call @llvm.llrint.nxv2i64.nxv2f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %8 = call @llvm.llrint.nxv4i64.nxv4f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %9 = call @llvm.llrint.nxv8i64.nxv8f16( undef) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %10 = call @llvm.llrint.nxv16i64.nxv16f16( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; call i64 @llvm.llrint.f16(half undef) diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll index 588d852d7f26e20c7bdc2d3e455b357963e296c8..0486f383aa553dd2c1f7b0566252ccf983767161 100644 --- a/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll +++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll @@ -13,6 +13,12 @@ define void @reduce_fadd_bfloat() { ; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fadd_bfloat' @@ -24,6 +30,12 @@ define void @reduce_fadd_bfloat() { ; SIZE-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; SIZE-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; SIZE-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.0, <1 x bfloat> undef) @@ -34,6 +46,12 @@ define void @reduce_fadd_bfloat() { %v32 = call fast bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.0, <32 x bfloat> undef) %V64 = call fast bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.0, <64 x bfloat> undef) %V128 = call fast bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.0, <128 x bfloat> undef) + %NXV1 = call fast bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.0, undef) + %NXV2 = call fast bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.0, undef) + %NXV4 = call fast bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.0, undef) + %NXV8 = call fast bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.0, undef) + %NXV16 = call fast bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.0, undef) + %NXV32 = call fast bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.0, undef) ret void } @@ -47,6 +65,12 @@ define void @reduce_fadd_half() { ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_fadd_half' @@ -58,6 +82,12 @@ define void @reduce_fadd_half() { ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fadd_half' @@ -69,6 +99,12 @@ define void @reduce_fadd_half() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast half @llvm.vector.reduce.fadd.v1f16(half 0.0, <1 x half> undef) @@ -79,6 +115,12 @@ define void @reduce_fadd_half() { %v32 = call fast half @llvm.vector.reduce.fadd.v32f16(half 0.0, <32 x half> undef) %V64 = call fast half @llvm.vector.reduce.fadd.v64f16(half 0.0, <64 x half> undef) %V128 = call fast half @llvm.vector.reduce.fadd.v128f16(half 0.0, <128 x half> undef) + %NXV1 = call fast half @llvm.vector.reduce.fadd.nxv1f16(half 0.0, undef) + %NXV2 = call fast half @llvm.vector.reduce.fadd.nxv2f16(half 0.0, undef) + %NXV4 = call fast half @llvm.vector.reduce.fadd.nxv4f16(half 0.0, undef) + %NXV8 = call fast half @llvm.vector.reduce.fadd.nxv8f16(half 0.0, undef) + %NXV16 = call fast half @llvm.vector.reduce.fadd.nxv16f16(half 0.0, undef) + %NXV32 = call fast half @llvm.vector.reduce.fadd.nxv32f16(half 0.0, undef) ret void } @@ -92,6 +134,11 @@ define void @reduce_fadd_float() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %v32 = call fast float @llvm.vector.reduce.fadd.v32f32(float 0.000000e+00, <32 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64 = call fast float @llvm.vector.reduce.fadd.v64f32(float 0.000000e+00, <64 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V128 = call fast float @llvm.vector.reduce.fadd.v128f32(float 0.000000e+00, <128 x float> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast float @llvm.vector.reduce.fadd.nxv1f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast float @llvm.vector.reduce.fadd.nxv2f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast float @llvm.vector.reduce.fadd.nxv4f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast float @llvm.vector.reduce.fadd.nxv8f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call fast float @llvm.vector.reduce.fadd.nxv16f32(float 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fadd_float' @@ -103,6 +150,11 @@ define void @reduce_fadd_float() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call fast float @llvm.vector.reduce.fadd.v32f32(float 0.000000e+00, <32 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64 = call fast float @llvm.vector.reduce.fadd.v64f32(float 0.000000e+00, <64 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V128 = call fast float @llvm.vector.reduce.fadd.v128f32(float 0.000000e+00, <128 x float> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast float @llvm.vector.reduce.fadd.nxv1f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast float @llvm.vector.reduce.fadd.nxv2f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast float @llvm.vector.reduce.fadd.nxv4f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast float @llvm.vector.reduce.fadd.nxv8f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call fast float @llvm.vector.reduce.fadd.nxv16f32(float 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast float @llvm.vector.reduce.fadd.v1f32(float 0.0, <1 x float> undef) @@ -113,6 +165,11 @@ define void @reduce_fadd_float() { %v32 = call fast float @llvm.vector.reduce.fadd.v32f32(float 0.0, <32 x float> undef) %V64 = call fast float @llvm.vector.reduce.fadd.v64f32(float 0.0, <64 x float> undef) %V128 = call fast float @llvm.vector.reduce.fadd.v128f32(float 0.0, <128 x float> undef) + %NXV1 = call fast float @llvm.vector.reduce.fadd.nxv1f32(float 0.0, undef) + %NXV2 = call fast float @llvm.vector.reduce.fadd.nxv2f32(float 0.0, undef) + %NXV4 = call fast float @llvm.vector.reduce.fadd.nxv4f32(float 0.0, undef) + %NXV8 = call fast float @llvm.vector.reduce.fadd.nxv8f32(float 0.0, undef) + %NXV16 = call fast float @llvm.vector.reduce.fadd.nxv16f32(float 0.0, undef) ret void } @@ -126,6 +183,10 @@ define void @reduce_fadd_double() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %v32 = call fast double @llvm.vector.reduce.fadd.v32f64(double 0.000000e+00, <32 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 30 for instruction: %V64 = call fast double @llvm.vector.reduce.fadd.v64f64(double 0.000000e+00, <64 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 62 for instruction: %V128 = call fast double @llvm.vector.reduce.fadd.v128f64(double 0.000000e+00, <128 x double> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast double @llvm.vector.reduce.fadd.nxv1f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast double @llvm.vector.reduce.fadd.nxv2f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast double @llvm.vector.reduce.fadd.nxv4f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast double @llvm.vector.reduce.fadd.nxv8f64(double 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fadd_double' @@ -137,6 +198,10 @@ define void @reduce_fadd_double() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32 = call fast double @llvm.vector.reduce.fadd.v32f64(double 0.000000e+00, <32 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64 = call fast double @llvm.vector.reduce.fadd.v64f64(double 0.000000e+00, <64 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call fast double @llvm.vector.reduce.fadd.v128f64(double 0.000000e+00, <128 x double> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call fast double @llvm.vector.reduce.fadd.nxv1f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call fast double @llvm.vector.reduce.fadd.nxv2f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call fast double @llvm.vector.reduce.fadd.nxv4f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call fast double @llvm.vector.reduce.fadd.nxv8f64(double 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast double @llvm.vector.reduce.fadd.v1f64(double 0.0, <1 x double> undef) @@ -147,11 +212,15 @@ define void @reduce_fadd_double() { %v32 = call fast double @llvm.vector.reduce.fadd.v32f64(double 0.0, <32 x double> undef) %V64 = call fast double @llvm.vector.reduce.fadd.v64f64(double 0.0, <64 x double> undef) %V128 = call fast double @llvm.vector.reduce.fadd.v128f64(double 0.0, <128 x double> undef) + %NXV1 = call fast double @llvm.vector.reduce.fadd.nxv1f64(double 0.0, undef) + %NXV2 = call fast double @llvm.vector.reduce.fadd.nxv2f64(double 0.0, undef) + %NXV4 = call fast double @llvm.vector.reduce.fadd.nxv4f64(double 0.0, undef) + %NXV8 = call fast double @llvm.vector.reduce.fadd.nxv8f64(double 0.0, undef) ret void } -define void @reduce_oredered_fadd_bfloat() { -; FP-REDUCE-LABEL: 'reduce_oredered_fadd_bfloat' +define void @reduce_ordered_fadd_bfloat() { +; FP-REDUCE-LABEL: 'reduce_ordered_fadd_bfloat' ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef) @@ -160,9 +229,15 @@ define void @reduce_oredered_fadd_bfloat() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; SIZE-LABEL: 'reduce_oredered_fadd_bfloat' +; SIZE-LABEL: 'reduce_ordered_fadd_bfloat' ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0xR0000, <1 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call bfloat @llvm.vector.reduce.fadd.v2bf16(bfloat 0xR0000, <2 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call bfloat @llvm.vector.reduce.fadd.v4bf16(bfloat 0xR0000, <4 x bfloat> undef) @@ -171,6 +246,12 @@ define void @reduce_oredered_fadd_bfloat() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0xR0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call bfloat @llvm.vector.reduce.fadd.v1bf16(bfloat 0.0, <1 x bfloat> undef) @@ -181,11 +262,17 @@ define void @reduce_oredered_fadd_bfloat() { %v32 = call bfloat @llvm.vector.reduce.fadd.v32bf16(bfloat 0.0, <32 x bfloat> undef) %V64 = call bfloat @llvm.vector.reduce.fadd.v64bf16(bfloat 0.0, <64 x bfloat> undef) %V128 = call bfloat @llvm.vector.reduce.fadd.v128bf16(bfloat 0.0, <128 x bfloat> undef) + %NXV1 = call bfloat @llvm.vector.reduce.fadd.nxv1bf16(bfloat 0.0, undef) + %NXV2 = call bfloat @llvm.vector.reduce.fadd.nxv2bf16(bfloat 0.0, undef) + %NXV4 = call bfloat @llvm.vector.reduce.fadd.nxv4bf16(bfloat 0.0, undef) + %NXV8 = call bfloat @llvm.vector.reduce.fadd.nxv8bf16(bfloat 0.0, undef) + %NXV16 = call bfloat @llvm.vector.reduce.fadd.nxv16bf16(bfloat 0.0, undef) + %NXV32 = call bfloat @llvm.vector.reduce.fadd.nxv32bf16(bfloat 0.0, undef) ret void } -define void @reduce_oredered_fadd_half() { -; FP-REDUCE-LABEL: 'reduce_oredered_fadd_half' +define void @reduce_ordered_fadd_half() { +; FP-REDUCE-LABEL: 'reduce_ordered_fadd_half' ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef) @@ -194,9 +281,15 @@ define void @reduce_oredered_fadd_half() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; SIZE-LABEL: 'reduce_oredered_fadd_half' +; SIZE-LABEL: 'reduce_ordered_fadd_half' ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0xH0000, <1 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call half @llvm.vector.reduce.fadd.v2f16(half 0xH0000, <2 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call half @llvm.vector.reduce.fadd.v4f16(half 0xH0000, <4 x half> undef) @@ -205,6 +298,12 @@ define void @reduce_oredered_fadd_half() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0xH0000, <32 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0xH0000, <64 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0xH0000, <128 x half> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0xH0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call half @llvm.vector.reduce.fadd.v1f16(half 0.0, <1 x half> undef) @@ -215,11 +314,17 @@ define void @reduce_oredered_fadd_half() { %v32 = call half @llvm.vector.reduce.fadd.v32f16(half 0.0, <32 x half> undef) %V64 = call half @llvm.vector.reduce.fadd.v64f16(half 0.0, <64 x half> undef) %V128 = call half @llvm.vector.reduce.fadd.v128f16(half 0.0, <128 x half> undef) + %NXV1 = call half @llvm.vector.reduce.fadd.nxv1f16(half 0.0, undef) + %NXV2 = call half @llvm.vector.reduce.fadd.nxv2f16(half 0.0, undef) + %NXV4 = call half @llvm.vector.reduce.fadd.nxv4f16(half 0.0, undef) + %NXV8 = call half @llvm.vector.reduce.fadd.nxv8f16(half 0.0, undef) + %NXV16 = call half @llvm.vector.reduce.fadd.nxv16f16(half 0.0, undef) + %NXV32 = call half @llvm.vector.reduce.fadd.nxv32f16(half 0.0, undef) ret void } -define void @reduce_oredered_fadd_float() { -; FP-REDUCE-LABEL: 'reduce_oredered_fadd_float' +define void @reduce_ordered_fadd_float() { +; FP-REDUCE-LABEL: 'reduce_ordered_fadd_float' ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call float @llvm.vector.reduce.fadd.v1f32(float 0.000000e+00, <1 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef) @@ -228,9 +333,14 @@ define void @reduce_oredered_fadd_float() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call float @llvm.vector.reduce.fadd.v32f32(float 0.000000e+00, <32 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call float @llvm.vector.reduce.fadd.v64f32(float 0.000000e+00, <64 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call float @llvm.vector.reduce.fadd.v128f32(float 0.000000e+00, <128 x float> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call float @llvm.vector.reduce.fadd.nxv1f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call float @llvm.vector.reduce.fadd.nxv2f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call float @llvm.vector.reduce.fadd.nxv4f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call float @llvm.vector.reduce.fadd.nxv8f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call float @llvm.vector.reduce.fadd.nxv16f32(float 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; SIZE-LABEL: 'reduce_oredered_fadd_float' +; SIZE-LABEL: 'reduce_ordered_fadd_float' ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call float @llvm.vector.reduce.fadd.v1f32(float 0.000000e+00, <1 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call float @llvm.vector.reduce.fadd.v2f32(float 0.000000e+00, <2 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call float @llvm.vector.reduce.fadd.v4f32(float 0.000000e+00, <4 x float> undef) @@ -239,6 +349,11 @@ define void @reduce_oredered_fadd_float() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %v32 = call float @llvm.vector.reduce.fadd.v32f32(float 0.000000e+00, <32 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V64 = call float @llvm.vector.reduce.fadd.v64f32(float 0.000000e+00, <64 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V128 = call float @llvm.vector.reduce.fadd.v128f32(float 0.000000e+00, <128 x float> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call float @llvm.vector.reduce.fadd.nxv1f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call float @llvm.vector.reduce.fadd.nxv2f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call float @llvm.vector.reduce.fadd.nxv4f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call float @llvm.vector.reduce.fadd.nxv8f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16 = call float @llvm.vector.reduce.fadd.nxv16f32(float 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call float @llvm.vector.reduce.fadd.v1f32(float 0.0, <1 x float> undef) @@ -249,11 +364,16 @@ define void @reduce_oredered_fadd_float() { %v32 = call float @llvm.vector.reduce.fadd.v32f32(float 0.0, <32 x float> undef) %V64 = call float @llvm.vector.reduce.fadd.v64f32(float 0.0, <64 x float> undef) %V128 = call float @llvm.vector.reduce.fadd.v128f32(float 0.0, <128 x float> undef) + %NXV1 = call float @llvm.vector.reduce.fadd.nxv1f32(float 0.0, undef) + %NXV2 = call float @llvm.vector.reduce.fadd.nxv2f32(float 0.0, undef) + %NXV4 = call float @llvm.vector.reduce.fadd.nxv4f32(float 0.0, undef) + %NXV8 = call float @llvm.vector.reduce.fadd.nxv8f32(float 0.0, undef) + %NXV16 = call float @llvm.vector.reduce.fadd.nxv16f32(float 0.0, undef) ret void } -define void @reduce_oredered_fadd_double() { -; FP-REDUCE-LABEL: 'reduce_oredered_fadd_double' +define void @reduce_ordered_fadd_double() { +; FP-REDUCE-LABEL: 'reduce_ordered_fadd_double' ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double 0.000000e+00, <1 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2 = call double @llvm.vector.reduce.fadd.v2f64(double 0.000000e+00, <2 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V4 = call double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> undef) @@ -262,9 +382,13 @@ define void @reduce_oredered_fadd_double() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %v32 = call double @llvm.vector.reduce.fadd.v32f64(double 0.000000e+00, <32 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %V64 = call double @llvm.vector.reduce.fadd.v64f64(double 0.000000e+00, <64 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 130 for instruction: %V128 = call double @llvm.vector.reduce.fadd.v128f64(double 0.000000e+00, <128 x double> undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call double @llvm.vector.reduce.fadd.nxv1f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call double @llvm.vector.reduce.fadd.nxv2f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call double @llvm.vector.reduce.fadd.nxv4f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call double @llvm.vector.reduce.fadd.nxv8f64(double 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; -; SIZE-LABEL: 'reduce_oredered_fadd_double' +; SIZE-LABEL: 'reduce_ordered_fadd_double' ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1 = call double @llvm.vector.reduce.fadd.v1f64(double 0.000000e+00, <1 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call double @llvm.vector.reduce.fadd.v2f64(double 0.000000e+00, <2 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4 = call double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> undef) @@ -273,6 +397,10 @@ define void @reduce_oredered_fadd_double() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v32 = call double @llvm.vector.reduce.fadd.v32f64(double 0.000000e+00, <32 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V64 = call double @llvm.vector.reduce.fadd.v64f64(double 0.000000e+00, <64 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call double @llvm.vector.reduce.fadd.v128f64(double 0.000000e+00, <128 x double> undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1 = call double @llvm.vector.reduce.fadd.nxv1f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2 = call double @llvm.vector.reduce.fadd.nxv2f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4 = call double @llvm.vector.reduce.fadd.nxv4f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV8 = call double @llvm.vector.reduce.fadd.nxv8f64(double 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call double @llvm.vector.reduce.fadd.v1f64(double 0.0, <1 x double> undef) @@ -283,30 +411,9 @@ define void @reduce_oredered_fadd_double() { %v32 = call double @llvm.vector.reduce.fadd.v32f64(double 0.0, <32 x double> undef) %V64 = call double @llvm.vector.reduce.fadd.v64f64(double 0.0, <64 x double> undef) %V128 = call double @llvm.vector.reduce.fadd.v128f64(double 0.0, <128 x double> undef) + %NXV1 = call double @llvm.vector.reduce.fadd.nxv1f64(double 0.0, undef) + %NXV2 = call double @llvm.vector.reduce.fadd.nxv2f64(double 0.0, undef) + %NXV4 = call double @llvm.vector.reduce.fadd.nxv4f64(double 0.0, undef) + %NXV8 = call double @llvm.vector.reduce.fadd.nxv8f64(double 0.0, undef) ret void } - -declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>) -declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>) -declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>) -declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>) -declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>) -declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>) -declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>) -declare half @llvm.vector.reduce.fadd.v128f16(half, <128 x half>) -declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>) -declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>) -declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>) -declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>) -declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>) -declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>) -declare float @llvm.vector.reduce.fadd.v64f32(float, <64 x float>) -declare float @llvm.vector.reduce.fadd.v128f32(float, <128 x float>) -declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>) -declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>) -declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>) -declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>) -declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>) -declare double @llvm.vector.reduce.fadd.v32f64(double, <32 x double>) -declare double @llvm.vector.reduce.fadd.v64f64(double, <64 x double>) -declare double @llvm.vector.reduce.fadd.v128f64(double, <128 x double>) diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll index a50b3bfed62072505f8edb7c8ca3fd093b16fc5f..e485995aad36e5d5ca2da07df1a4efb0ce59ed70 100644 --- a/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll +++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fmul.ll @@ -13,6 +13,12 @@ define void @reduce_fmul_bfloat() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 351 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fmul_bfloat' @@ -24,6 +30,12 @@ define void @reduce_fmul_bfloat() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.0, <1 x bfloat> undef) @@ -34,6 +46,12 @@ define void @reduce_fmul_bfloat() { %v32 = call fast bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0.0, <32 x bfloat> undef) %V64 = call fast bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0.0, <64 x bfloat> undef) %V128 = call fast bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0.0, <128 x bfloat> undef) + %NXV1 = call fast bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0.0, undef) + %NXV2 = call fast bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0.0, undef) + %NXV4 = call fast bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0.0, undef) + %NXV8 = call fast bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0.0, undef) + %NXV16 = call fast bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0.0, undef) + %NXV32 = call fast bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0.0, undef) ret void } @@ -47,6 +65,12 @@ define void @reduce_fmul_half() { ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 151 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-ZVFH-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-ZVFH-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; FP-REDUCE-ZVFHMIN-LABEL: 'reduce_fmul_half' @@ -58,6 +82,12 @@ define void @reduce_fmul_half() { ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 351 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 541 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 573 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fmul_half' @@ -69,6 +99,12 @@ define void @reduce_fmul_half() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast half @llvm.vector.reduce.fmul.v1f16(half 0.0, <1 x half> undef) @@ -79,6 +115,12 @@ define void @reduce_fmul_half() { %v32 = call fast half @llvm.vector.reduce.fmul.v32f16(half 0.0, <32 x half> undef) %V64 = call fast half @llvm.vector.reduce.fmul.v64f16(half 0.0, <64 x half> undef) %V128 = call fast half @llvm.vector.reduce.fmul.v128f16(half 0.0, <128 x half> undef) + %NXV1 = call fast half @llvm.vector.reduce.fmul.nxv1f16(half 0.0, undef) + %NXV2 = call fast half @llvm.vector.reduce.fmul.nxv2f16(half 0.0, undef) + %NXV4 = call fast half @llvm.vector.reduce.fmul.nxv4f16(half 0.0, undef) + %NXV8 = call fast half @llvm.vector.reduce.fmul.nxv8f16(half 0.0, undef) + %NXV16 = call fast half @llvm.vector.reduce.fmul.nxv16f16(half 0.0, undef) + %NXV32 = call fast half @llvm.vector.reduce.fmul.nxv32f16(half 0.0, undef) ret void } @@ -92,6 +134,11 @@ define void @reduce_fmul_float() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 451 for instruction: %v32 = call fast float @llvm.vector.reduce.fmul.v32f32(float 0.000000e+00, <32 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 483 for instruction: %V64 = call fast float @llvm.vector.reduce.fmul.v64f32(float 0.000000e+00, <64 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 547 for instruction: %V128 = call fast float @llvm.vector.reduce.fmul.v128f32(float 0.000000e+00, <128 x float> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast float @llvm.vector.reduce.fmul.nxv1f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast float @llvm.vector.reduce.fmul.nxv2f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast float @llvm.vector.reduce.fmul.nxv8f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast float @llvm.vector.reduce.fmul.nxv16f32(float 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fmul_float' @@ -103,6 +150,11 @@ define void @reduce_fmul_float() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 26 for instruction: %v32 = call fast float @llvm.vector.reduce.fmul.v32f32(float 0.000000e+00, <32 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V64 = call fast float @llvm.vector.reduce.fmul.v64f32(float 0.000000e+00, <64 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 34 for instruction: %V128 = call fast float @llvm.vector.reduce.fmul.v128f32(float 0.000000e+00, <128 x float> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast float @llvm.vector.reduce.fmul.nxv1f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast float @llvm.vector.reduce.fmul.nxv2f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast float @llvm.vector.reduce.fmul.nxv8f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call fast float @llvm.vector.reduce.fmul.nxv16f32(float 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast float @llvm.vector.reduce.fmul.v1f32(float 0.0, <1 x float> undef) @@ -113,6 +165,11 @@ define void @reduce_fmul_float() { %v32 = call fast float @llvm.vector.reduce.fmul.v32f32(float 0.0, <32 x float> undef) %V64 = call fast float @llvm.vector.reduce.fmul.v64f32(float 0.0, <64 x float> undef) %V128 = call fast float @llvm.vector.reduce.fmul.v128f32(float 0.0, <128 x float> undef) + %NXV1 = call fast float @llvm.vector.reduce.fmul.nxv1f32(float 0.0, undef) + %NXV2 = call fast float @llvm.vector.reduce.fmul.nxv2f32(float 0.0, undef) + %NXV4 = call fast float @llvm.vector.reduce.fmul.nxv4f32(float 0.0, undef) + %NXV8 = call fast float @llvm.vector.reduce.fmul.nxv8f32(float 0.0, undef) + %NXV16 = call fast float @llvm.vector.reduce.fmul.nxv16f32(float 0.0, undef) ret void } @@ -126,6 +183,10 @@ define void @reduce_fmul_double() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 393 for instruction: %v32 = call fast double @llvm.vector.reduce.fmul.v32f64(double 0.000000e+00, <32 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 457 for instruction: %V64 = call fast double @llvm.vector.reduce.fmul.v64f64(double 0.000000e+00, <64 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 585 for instruction: %V128 = call fast double @llvm.vector.reduce.fmul.v128f64(double 0.000000e+00, <128 x double> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast double @llvm.vector.reduce.fmul.nxv1f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast double @llvm.vector.reduce.fmul.nxv2f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast double @llvm.vector.reduce.fmul.nxv4f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast double @llvm.vector.reduce.fmul.nxv8f64(double 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_fmul_double' @@ -137,6 +198,10 @@ define void @reduce_fmul_double() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %v32 = call fast double @llvm.vector.reduce.fmul.v32f64(double 0.000000e+00, <32 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 29 for instruction: %V64 = call fast double @llvm.vector.reduce.fmul.v64f64(double 0.000000e+00, <64 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 38 for instruction: %V128 = call fast double @llvm.vector.reduce.fmul.v128f64(double 0.000000e+00, <128 x double> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call fast double @llvm.vector.reduce.fmul.nxv1f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call fast double @llvm.vector.reduce.fmul.nxv2f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call fast double @llvm.vector.reduce.fmul.nxv4f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call fast double @llvm.vector.reduce.fmul.nxv8f64(double 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call fast double @llvm.vector.reduce.fmul.v1f64(double 0.0, <1 x double> undef) @@ -147,6 +212,10 @@ define void @reduce_fmul_double() { %v32 = call fast double @llvm.vector.reduce.fmul.v32f64(double 0.0, <32 x double> undef) %V64 = call fast double @llvm.vector.reduce.fmul.v64f64(double 0.0, <64 x double> undef) %V128 = call fast double @llvm.vector.reduce.fmul.v128f64(double 0.0, <128 x double> undef) + %NXV1 = call fast double @llvm.vector.reduce.fmul.nxv1f64(double 0.0, undef) + %NXV2 = call fast double @llvm.vector.reduce.fmul.nxv2f64(double 0.0, undef) + %NXV4 = call fast double @llvm.vector.reduce.fmul.nxv4f64(double 0.0, undef) + %NXV8 = call fast double @llvm.vector.reduce.fmul.nxv8f64(double 0.0, undef) ret void } @@ -160,6 +229,12 @@ define void @reduce_ordered_fmul_bfloat() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_ordered_fmul_bfloat' @@ -171,6 +246,12 @@ define void @reduce_ordered_fmul_bfloat() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0xR0000, <32 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0xR0000, <64 x bfloat> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0xR0000, <128 x bfloat> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0xR0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0xR0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call bfloat @llvm.vector.reduce.fmul.v1bf16(bfloat 0.0, <1 x bfloat> undef) @@ -181,6 +262,12 @@ define void @reduce_ordered_fmul_bfloat() { %v32 = call bfloat @llvm.vector.reduce.fmul.v32bf16(bfloat 0.0, <32 x bfloat> undef) %V64 = call bfloat @llvm.vector.reduce.fmul.v64bf16(bfloat 0.0, <64 x bfloat> undef) %V128 = call bfloat @llvm.vector.reduce.fmul.v128bf16(bfloat 0.0, <128 x bfloat> undef) + %NXV1 = call bfloat @llvm.vector.reduce.fmul.nxv1bf16(bfloat 0.0, undef) + %NXV2 = call bfloat @llvm.vector.reduce.fmul.nxv2bf16(bfloat 0.0, undef) + %NXV4 = call bfloat @llvm.vector.reduce.fmul.nxv4bf16(bfloat 0.0, undef) + %NXV8 = call bfloat @llvm.vector.reduce.fmul.nxv8bf16(bfloat 0.0, undef) + %NXV16 = call bfloat @llvm.vector.reduce.fmul.nxv16bf16(bfloat 0.0, undef) + %NXV32 = call bfloat @llvm.vector.reduce.fmul.nxv32bf16(bfloat 0.0, undef) ret void } @@ -194,6 +281,12 @@ define void @reduce_ordered_fmul_half() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 255 for instruction: %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 510 for instruction: %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_ordered_fmul_half' @@ -205,6 +298,12 @@ define void @reduce_ordered_fmul_half() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0xH0000, <32 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 191 for instruction: %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0xH0000, <64 x half> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 382 for instruction: %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0xH0000, <128 x half> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0xH0000, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0xH0000, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call half @llvm.vector.reduce.fmul.v1f16(half 0.0, <1 x half> undef) @@ -215,6 +314,12 @@ define void @reduce_ordered_fmul_half() { %v32 = call half @llvm.vector.reduce.fmul.v32f16(half 0.0, <32 x half> undef) %V64 = call half @llvm.vector.reduce.fmul.v64f16(half 0.0, <64 x half> undef) %V128 = call half @llvm.vector.reduce.fmul.v128f16(half 0.0, <128 x half> undef) + %NXV1 = call half @llvm.vector.reduce.fmul.nxv1f16(half 0.0, undef) + %NXV2 = call half @llvm.vector.reduce.fmul.nxv2f16(half 0.0, undef) + %NXV4 = call half @llvm.vector.reduce.fmul.nxv4f16(half 0.0, undef) + %NXV8 = call half @llvm.vector.reduce.fmul.nxv8f16(half 0.0, undef) + %NXV16 = call half @llvm.vector.reduce.fmul.nxv16f16(half 0.0, undef) + %NXV32 = call half @llvm.vector.reduce.fmul.nxv32f16(half 0.0, undef) ret void } @@ -228,6 +333,11 @@ define void @reduce_ordered_fmul_float() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %v32 = call float @llvm.vector.reduce.fmul.v32f32(float 0.000000e+00, <32 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 254 for instruction: %V64 = call float @llvm.vector.reduce.fmul.v64f32(float 0.000000e+00, <64 x float> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 508 for instruction: %V128 = call float @llvm.vector.reduce.fmul.v128f32(float 0.000000e+00, <128 x float> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call float @llvm.vector.reduce.fmul.nxv1f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call float @llvm.vector.reduce.fmul.nxv2f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call float @llvm.vector.reduce.fmul.nxv8f32(float 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call float @llvm.vector.reduce.fmul.nxv16f32(float 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_ordered_fmul_float' @@ -239,6 +349,11 @@ define void @reduce_ordered_fmul_float() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 95 for instruction: %v32 = call float @llvm.vector.reduce.fmul.v32f32(float 0.000000e+00, <32 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 190 for instruction: %V64 = call float @llvm.vector.reduce.fmul.v64f32(float 0.000000e+00, <64 x float> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 380 for instruction: %V128 = call float @llvm.vector.reduce.fmul.v128f32(float 0.000000e+00, <128 x float> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call float @llvm.vector.reduce.fmul.nxv1f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call float @llvm.vector.reduce.fmul.nxv2f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call float @llvm.vector.reduce.fmul.nxv4f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call float @llvm.vector.reduce.fmul.nxv8f32(float 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV16 = call float @llvm.vector.reduce.fmul.nxv16f32(float 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call float @llvm.vector.reduce.fmul.v1f32(float 0.0, <1 x float> undef) @@ -249,6 +364,11 @@ define void @reduce_ordered_fmul_float() { %v32 = call float @llvm.vector.reduce.fmul.v32f32(float 0.0, <32 x float> undef) %V64 = call float @llvm.vector.reduce.fmul.v64f32(float 0.0, <64 x float> undef) %V128 = call float @llvm.vector.reduce.fmul.v128f32(float 0.0, <128 x float> undef) + %NXV1 = call float @llvm.vector.reduce.fmul.nxv1f32(float 0.0, undef) + %NXV2 = call float @llvm.vector.reduce.fmul.nxv2f32(float 0.0, undef) + %NXV4 = call float @llvm.vector.reduce.fmul.nxv4f32(float 0.0, undef) + %NXV8 = call float @llvm.vector.reduce.fmul.nxv8f32(float 0.0, undef) + %NXV16 = call float @llvm.vector.reduce.fmul.nxv16f32(float 0.0, undef) ret void } @@ -262,6 +382,10 @@ define void @reduce_ordered_fmul_double() { ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 126 for instruction: %v32 = call double @llvm.vector.reduce.fmul.v32f64(double 0.000000e+00, <32 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 252 for instruction: %V64 = call double @llvm.vector.reduce.fmul.v64f64(double 0.000000e+00, <64 x double> undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 504 for instruction: %V128 = call double @llvm.vector.reduce.fmul.v128f64(double 0.000000e+00, <128 x double> undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call double @llvm.vector.reduce.fmul.nxv1f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call double @llvm.vector.reduce.fmul.nxv2f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call double @llvm.vector.reduce.fmul.nxv4f64(double 0.000000e+00, undef) +; FP-REDUCE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call double @llvm.vector.reduce.fmul.nxv8f64(double 0.000000e+00, undef) ; FP-REDUCE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'reduce_ordered_fmul_double' @@ -273,6 +397,10 @@ define void @reduce_ordered_fmul_double() { ; SIZE-NEXT: Cost Model: Found an estimated cost of 94 for instruction: %v32 = call double @llvm.vector.reduce.fmul.v32f64(double 0.000000e+00, <32 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 188 for instruction: %V64 = call double @llvm.vector.reduce.fmul.v64f64(double 0.000000e+00, <64 x double> undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 376 for instruction: %V128 = call double @llvm.vector.reduce.fmul.v128f64(double 0.000000e+00, <128 x double> undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV1 = call double @llvm.vector.reduce.fmul.nxv1f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV2 = call double @llvm.vector.reduce.fmul.nxv2f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV4 = call double @llvm.vector.reduce.fmul.nxv4f64(double 0.000000e+00, undef) +; SIZE-NEXT: Cost Model: Invalid cost for instruction: %NXV8 = call double @llvm.vector.reduce.fmul.nxv8f64(double 0.000000e+00, undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; %V1 = call double @llvm.vector.reduce.fmul.v1f64(double 0.0, <1 x double> undef) @@ -283,5 +411,9 @@ define void @reduce_ordered_fmul_double() { %v32 = call double @llvm.vector.reduce.fmul.v32f64(double 0.0, <32 x double> undef) %V64 = call double @llvm.vector.reduce.fmul.v64f64(double 0.0, <64 x double> undef) %V128 = call double @llvm.vector.reduce.fmul.v128f64(double 0.0, <128 x double> undef) + %NXV1 = call double @llvm.vector.reduce.fmul.nxv1f64(double 0.0, undef) + %NXV2 = call double @llvm.vector.reduce.fmul.nxv2f64(double 0.0, undef) + %NXV4 = call double @llvm.vector.reduce.fmul.nxv4f64(double 0.0, undef) + %NXV8 = call double @llvm.vector.reduce.fmul.nxv8f64(double 0.0, undef) ret void } diff --git a/llvm/test/Analysis/StackSafetyAnalysis/local.ll b/llvm/test/Analysis/StackSafetyAnalysis/local.ll index 4a833611c78916eaefe8f6ffa9b923670a081957..02d46c8449bae531e45409d3c4af4e0b10d7db47 100644 --- a/llvm/test/Analysis/StackSafetyAnalysis/local.ll +++ b/llvm/test/Analysis/StackSafetyAnalysis/local.ll @@ -1120,5 +1120,21 @@ define void @NonPointer(ptr %p) { ret void } +@ifunc = dso_local ifunc i64 (ptr), ptr @ifunc_resolver + +define dso_local void @CallIfunc(ptr noundef %uaddr) local_unnamed_addr { +; CHECK-LABEL: @CallIfunc +; CHECK-NEXT: args uses: +; CHECK-NEXT: uaddr[]: full-set +entry: + tail call i64 @ifunc(ptr noundef %uaddr) + ret void +} + +define dso_local ptr @ifunc_resolver() { +entry: + ret ptr null +} + declare void @llvm.lifetime.start.p0(i64, ptr nocapture) declare void @llvm.lifetime.end.p0(i64, ptr nocapture) diff --git a/llvm/test/Assembler/invalid-inttype.ll b/llvm/test/Assembler/invalid-inttype.ll index c8aa7c66b79e4ddfbbd27f23ee21612a90bfe81b..9e3c31148af2d6a625705a0d6bb297c30de6c849 100644 --- a/llvm/test/Assembler/invalid-inttype.ll +++ b/llvm/test/Assembler/invalid-inttype.ll @@ -1,5 +1,5 @@ ; RUN: not llvm-as --disable-output %s 2>&1 | FileCheck -DFILE=%s %s ; i8388609 is the smallest integer type that can't be represented in LLVM IR -; CHECK: [[FILE]]:[[@LINE+1]]:21: error: bitwidth for integer type out of range! +; CHECK: [[FILE]]:[[@LINE+1]]:21: error: bitwidth for integer type out of range @i2 = common global i8388609 0, align 4 diff --git a/llvm/test/Assembler/invalid-name.ll b/llvm/test/Assembler/invalid-name.ll index 74133e60df54d595c68c50aea282cd90899f334f..52e2bda3adbabde32ffd154cf1cd8256e0f6ab81 100644 Binary files a/llvm/test/Assembler/invalid-name.ll and b/llvm/test/Assembler/invalid-name.ll differ diff --git a/llvm/test/Assembler/invalid-name2.ll b/llvm/test/Assembler/invalid-name2.ll index 8a848798a54cafef9c3c151b08f70955e59fa62f..78da4dc3d1b8d04c34b049c222d581088f506e7b 100644 Binary files a/llvm/test/Assembler/invalid-name2.ll and b/llvm/test/Assembler/invalid-name2.ll differ diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/icmp-flags.mir b/llvm/test/CodeGen/AArch64/GlobalISel/icmp-flags.mir new file mode 100644 index 0000000000000000000000000000000000000000..59e4de9440416f67b544df4087d15f997fa570f6 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/icmp-flags.mir @@ -0,0 +1,45 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple aarch64 -run-pass=none -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: icmp_samesign +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: icmp_samesign + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:_(s32) = COPY $w0 + ; CHECK-NEXT: %y:_(s32) = COPY $w1 + ; CHECK-NEXT: %cmp:_(s1) = samesign G_ICMP intpred(eq), %y(s32), %y + ; CHECK-NEXT: %zext:_(s32) = G_ZEXT %cmp(s1) + ; CHECK-NEXT: $w0 = COPY %zext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + %x:_(s32) = COPY $w0 + %y:_(s32) = COPY $w1 + %cmp:_(s1) = samesign G_ICMP intpred(eq), %y:_(s32), %y:_ + %zext:_(s32) = G_ZEXT %cmp:_(s1) + $w0 = COPY %zext + RET_ReallyLR implicit $w0 +... +--- +name: icmp_differentsign +body: | + bb.0: + liveins: $w0, $w1 + ; CHECK-LABEL: name: icmp_differentsign + ; CHECK: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: %x:_(s32) = COPY $w0 + ; CHECK-NEXT: %y:_(s32) = COPY $w1 + ; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), %y + ; CHECK-NEXT: %zext:_(s32) = G_ZEXT %cmp(s1) + ; CHECK-NEXT: $w0 = COPY %zext(s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 + %x:_(s32) = COPY $w0 + %y:_(s32) = COPY $w1 + %cmp:_(s1) = G_ICMP intpred(eq), %y:_(s32), %y:_ + %zext:_(s32) = G_ZEXT %cmp:_(s1) + $w0 = COPY %zext + RET_ReallyLR implicit $w0 +--- diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll new file mode 100644 index 0000000000000000000000000000000000000000..0173f92c9822037507438444a08d94d059306de6 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslater-samesign.ll @@ -0,0 +1,69 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -global-isel -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator < %s | FileCheck %s + + +define <2 x i1> @call_icmp_samesign_vector(<2 x i32> %a, <2 x i32> %b) { + ; CHECK-LABEL: name: call_icmp_samesign_vector + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 + ; CHECK-NEXT: %2:_(<2 x s1>) = samesign G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) + ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 +entry: + %result = icmp samesign ult <2 x i32> %a, %b + ret <2 x i1> %result +} + +define <2 x i1> @call_icmp_vector(<2 x i32> %a, <2 x i32> %b) { + ; CHECK-LABEL: name: call_icmp_vector + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $d0, $d1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s1>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s32>) = G_ANYEXT [[ICMP]](<2 x s1>) + ; CHECK-NEXT: $d0 = COPY [[ANYEXT]](<2 x s32>) + ; CHECK-NEXT: RET_ReallyLR implicit $d0 +entry: + %result = icmp ult <2 x i32> %a, %b + ret <2 x i1> %result +} + +define i1 @call_icmp(i32 %a) { + ; CHECK-LABEL: name: call_icmp + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[C]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8) + ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %result = icmp ult i32 %a, 3 + ret i1 %result +} + +define i1 @call_icmp_samesign(i32 %a) { + ; CHECK-LABEL: name: call_icmp_samesign + ; CHECK: bb.1.entry: + ; CHECK-NEXT: liveins: $w0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK-NEXT: %2:_(s1) = samesign G_ICMP intpred(ult), [[COPY]](s32), [[C]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT %2(s1) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8) + ; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: RET_ReallyLR implicit $w0 +entry: + %result = icmp samesign ult i32 %a, 3 + ret i1 %result +} diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll index 1dfd977186b0e7346ded214c72f5cc501112cb8c..7af7c235f9ac16bd1cdfa3213f9ebf15c9b37c77 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll @@ -3560,4 +3560,16 @@ entry: ret <4 x i16> %vrshrn_n1 } +define <8 x i16> @signbits_vashr(<8 x i16> %a) { +; CHECK-LABEL: signbits_vashr: +; CHECK: // %bb.0: +; CHECK-NEXT: sshr.8h v0, v0, #8 +; CHECK-NEXT: sshr.8h v0, v0, #9 +; CHECK-NEXT: ret + %b = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %a, <8 x i16> ) + %c = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %b, <8 x i16> ) + %d = ashr <8 x i16> %c, + ret <8 x i16> %d +} + declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>) diff --git a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir index 0963ecbb123115d861e6f7022ddbd47ec4662425..a2532a854923f53313063fd8b428322ef955c4a9 100644 --- a/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir +++ b/llvm/test/CodeGen/AArch64/jump-table-duplicate.mir @@ -1,4 +1,5 @@ # RUN: llc -run-pass=tailduplication -tail-dup-size=4 %s -o - | FileCheck %s +# RUN: llc -passes=tailduplication -tail-dup-size=4 %s -o - | FileCheck %s # JumpTableDest32 uses an `adr` to a temporary label (itself). If duplicated we # cannot guarantee reachability for any uses after the first. diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll index c1810c678ea52296942dd1f7af1400e82f1e050a..6e2ecfca9e963e8a2ccdbad6f57932aa08367b6f 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s -; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE2 +; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SME ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -61,10 +61,10 @@ define <8 x i8> @concat_v8i8(<4 x i8> %op1, <4 x i8> %op2) { define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-LABEL: concat_v16i8: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.b, p0, { z0.b, z1.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -172,10 +172,10 @@ define <4 x i16> @concat_v4i16(<2 x i16> %op1, <2 x i16> %op2) { define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-LABEL: concat_v8i16: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -270,10 +270,10 @@ define <2 x i32> @concat_v2i32(<1 x i32> %op1, <1 x i32> %op2) { define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-LABEL: concat_v4i32: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -340,10 +340,10 @@ define void @concat_v16i32(ptr %a, ptr %b, ptr %c) { define <2 x i64> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-LABEL: concat_v2i64: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.d, vl1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.d, p0, { z0.d, z1.d } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -406,17 +406,33 @@ define void @concat_v8i64(ptr %a, ptr %b, ptr %c) { ; define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2) { -; CHECK-LABEL: concat_v4f16: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: mov z2.h, z1.h[1] -; CHECK-NEXT: mov z3.h, z0.h[1] -; CHECK-NEXT: zip1 z1.h, z1.h, z2.h -; CHECK-NEXT: zip1 z0.h, z0.h, z3.h -; CHECK-NEXT: zip1 z0.s, z0.s, z1.s -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 -; CHECK-NEXT: ret +; SVE2-LABEL: concat_v4f16: +; SVE2: // %bb.0: +; SVE2-NEXT: cnth x8 +; SVE2-NEXT: adrp x9, .LCPI15_0 +; SVE2-NEXT: adrp x10, .LCPI15_1 +; SVE2-NEXT: mov z2.h, w8 +; SVE2-NEXT: ldr q3, [x9, :lo12:.LCPI15_0] +; SVE2-NEXT: ldr q4, [x10, :lo12:.LCPI15_1] +; SVE2-NEXT: ptrue p0.h, vl8 +; SVE2-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 +; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; SVE2-NEXT: mad z2.h, p0/m, z3.h, z4.h +; SVE2-NEXT: tbl z0.h, { z0.h, z1.h }, z2.h +; SVE2-NEXT: // kill: def $d0 killed $d0 killed $z0 +; SVE2-NEXT: ret +; +; SME-LABEL: concat_v4f16: +; SME: // %bb.0: +; SME-NEXT: // kill: def $d1 killed $d1 def $z1 +; SME-NEXT: // kill: def $d0 killed $d0 def $z0 +; SME-NEXT: mov z2.h, z1.h[1] +; SME-NEXT: mov z3.h, z0.h[1] +; SME-NEXT: zip1 z1.h, z1.h, z2.h +; SME-NEXT: zip1 z0.h, z0.h, z3.h +; SME-NEXT: zip1 z0.s, z0.s, z1.s +; SME-NEXT: // kill: def $d0 killed $d0 killed $z0 +; SME-NEXT: ret ; ; NONEON-NOSVE-LABEL: concat_v4f16: ; NONEON-NOSVE: // %bb.0: @@ -436,10 +452,10 @@ define <4 x half> @concat_v4f16(<2 x half> %op1, <2 x half> %op2) { define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2) { ; CHECK-LABEL: concat_v8f16: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -534,10 +550,10 @@ define <2 x float> @concat_v2f32(<1 x float> %op1, <1 x float> %op2) { define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2) { ; CHECK-LABEL: concat_v4f32: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -604,10 +620,10 @@ define void @concat_v16f32(ptr %a, ptr %b, ptr %c) { define <2 x double> @concat_v2f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-LABEL: concat_v2f64: ; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 killed $z0_z1 def $z0_z1 ; CHECK-NEXT: ptrue p0.d, vl1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0_z1 def $z0_z1 +; CHECK-NEXT: splice z0.d, p0, { z0.d, z1.d } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll index f1771a753826cc06b74bf8fd3fb8b415a43f8e0e..2282e74af5d006c03d8ba437402a02302acd7cfc 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE -; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SVE2 +; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s --check-prefixes=SVE +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=SVE2 +; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=SVE2 ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" @@ -842,16 +842,16 @@ define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) { ; ; SVE2-LABEL: test_copysign_v4f32_v4f64: ; SVE2: // %bb.0: -; SVE2-NEXT: ldp q0, q1, [x1] +; SVE2-NEXT: ldp q1, q0, [x1] ; SVE2-NEXT: ptrue p0.d -; SVE2-NEXT: ldr q2, [x0] -; SVE2-NEXT: fcvt z1.s, p0/m, z1.d ; SVE2-NEXT: fcvt z0.s, p0/m, z0.d +; SVE2-NEXT: fcvt z1.s, p0/m, z1.d ; SVE2-NEXT: ptrue p0.s, vl2 -; SVE2-NEXT: uzp1 z1.s, z1.s, z1.s -; SVE2-NEXT: uzp1 z0.s, z0.s, z0.s -; SVE2-NEXT: splice z0.s, p0, z0.s, z1.s +; SVE2-NEXT: uzp1 z3.s, z0.s, z0.s +; SVE2-NEXT: uzp1 z2.s, z1.s, z1.s ; SVE2-NEXT: mov z1.s, #0x7fffffff +; SVE2-NEXT: splice z0.s, p0, { z2.s, z3.s } +; SVE2-NEXT: ldr q2, [x0] ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str q2, [x0] ; SVE2-NEXT: ret @@ -1237,16 +1237,16 @@ define void @test_copysign_v8f16_v8f32(ptr %ap, ptr %bp) { ; ; SVE2-LABEL: test_copysign_v8f16_v8f32: ; SVE2: // %bb.0: -; SVE2-NEXT: ldp q0, q1, [x1] +; SVE2-NEXT: ldp q1, q0, [x1] ; SVE2-NEXT: ptrue p0.s -; SVE2-NEXT: ldr q2, [x0] -; SVE2-NEXT: fcvt z1.h, p0/m, z1.s ; SVE2-NEXT: fcvt z0.h, p0/m, z0.s +; SVE2-NEXT: fcvt z1.h, p0/m, z1.s ; SVE2-NEXT: ptrue p0.h, vl4 -; SVE2-NEXT: uzp1 z1.h, z1.h, z1.h -; SVE2-NEXT: uzp1 z0.h, z0.h, z0.h -; SVE2-NEXT: splice z0.h, p0, z0.h, z1.h +; SVE2-NEXT: uzp1 z3.h, z0.h, z0.h +; SVE2-NEXT: uzp1 z2.h, z1.h, z1.h ; SVE2-NEXT: mov z1.h, #32767 // =0x7fff +; SVE2-NEXT: splice z0.h, p0, { z2.h, z3.h } +; SVE2-NEXT: ldr q2, [x0] ; SVE2-NEXT: bsl z2.d, z2.d, z0.d, z1.d ; SVE2-NEXT: str q2, [x0] ; SVE2-NEXT: ret @@ -1349,5 +1349,3 @@ declare <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b) #0 declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0 declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0 -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK: {{.*}} diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll index 516772b8ca664043cdf169a255c24cddc2924ecf..1fdcd4f82687084f3c857d0e0e9a77b7da11f6ca 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll @@ -1,7 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE -; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK,SVE2 -; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SVE2 +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE target triple = "aarch64-unknown-linux-gnu" @@ -26,19 +25,6 @@ define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v4i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8 -; NEON-NOSVE-NEXT: shl v1.4h, v1.4h, #8 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8 -; NEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #8 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v4i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -85,27 +71,12 @@ define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } +; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v8i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sshll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: xtn v0.8b, v0.8h -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v8i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -177,45 +148,21 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8 ; CHECK-NEXT: sunpklo z1.s, z1.h ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z4.h, z4.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z1.h, p0, { z1.h, z2.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z2.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z3.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v16i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: sshll2 v2.8h, v1.16b, #0 -; NEON-NOSVE-NEXT: sshll2 v3.8h, v0.16b, #0 -; NEON-NOSVE-NEXT: sshll v1.8h, v1.8b, #0 -; NEON-NOSVE-NEXT: sshll v0.8h, v0.8b, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sshll2 v4.4s, v2.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v5.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: sdivr z4.s, p0/m, z4.s, z5.s -; NEON-NOSVE-NEXT: sshll2 v5.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: sshll2 v3.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sdivr z3.s, p0/m, z3.s, z5.s -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v4.8h -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v3.8h -; NEON-NOSVE-NEXT: uzp1 v0.16b, v0.16b, v1.16b -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v16i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -319,7 +266,6 @@ define void @sdiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: sunpklo z4.h, z2.b ; CHECK-NEXT: sunpklo z2.s, z3.h ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: sunpklo z5.s, z4.h ; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8 ; CHECK-NEXT: sunpklo z3.s, z3.h @@ -328,7 +274,6 @@ define void @sdiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q5, [x0] ; CHECK-NEXT: sunpklo z16.h, z5.b ; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h ; CHECK-NEXT: sunpklo z5.h, z5.b ; CHECK-NEXT: sunpklo z18.s, z16.h ; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8 @@ -337,81 +282,36 @@ define void @sdiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: sunpklo z18.s, z5.h ; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8 ; CHECK-NEXT: sunpklo z5.s, z5.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z16.s ; CHECK-NEXT: sunpklo z16.s, z6.h ; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8 ; CHECK-NEXT: sunpklo z6.s, z6.h +; CHECK-NEXT: uzp1 z20.h, z17.h, z17.h ; CHECK-NEXT: sdivr z16.s, p0/m, z16.s, z18.s +; CHECK-NEXT: uzp1 z18.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z21.h, z7.h, z7.h ; CHECK-NEXT: sdiv z5.s, p0/m, z5.s, z6.s -; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h -; CHECK-NEXT: uzp1 z7.h, z16.h, z16.h +; CHECK-NEXT: uzp1 z0.h, z16.h, z16.h ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s -; CHECK-NEXT: uzp1 z4.h, z17.h, z17.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z6.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z1.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z1.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z20.h, z21.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z1.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z4.b, z2.b, z2.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: splice z1.b, p0, z1.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z2.b -; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: uzp1 z2.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z3.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z4.b, z5.b } +; CHECK-NEXT: splice z1.b, p0, { z2.b, z3.b } +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v32i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q6, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NEON-NOSVE-NEXT: sshll2 v1.8h, v3.16b, #0 -; NEON-NOSVE-NEXT: sshll2 v4.8h, v2.16b, #0 -; NEON-NOSVE-NEXT: sshll v3.8h, v3.8b, #0 -; NEON-NOSVE-NEXT: sshll v2.8h, v2.8b, #0 -; NEON-NOSVE-NEXT: sshll2 v7.8h, v6.16b, #0 -; NEON-NOSVE-NEXT: sshll v6.8h, v6.8b, #0 -; NEON-NOSVE-NEXT: sshll2 v0.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v5.4s, v4.8h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v4.4s, v4.4h, #0 -; NEON-NOSVE-NEXT: sshll2 v17.4s, v7.8h, #0 -; NEON-NOSVE-NEXT: sshll v7.4s, v7.4h, #0 -; NEON-NOSVE-NEXT: sdivr z0.s, p0/m, z0.s, z5.s -; NEON-NOSVE-NEXT: sshll2 v5.4s, v2.8h, #0 -; NEON-NOSVE-NEXT: sshll v2.4s, v2.4h, #0 -; NEON-NOSVE-NEXT: sdivr z1.s, p0/m, z1.s, z4.s -; NEON-NOSVE-NEXT: sshll2 v4.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: sdivr z4.s, p0/m, z4.s, z5.s -; NEON-NOSVE-NEXT: ldr q5, [x0] -; NEON-NOSVE-NEXT: sshll2 v16.8h, v5.16b, #0 -; NEON-NOSVE-NEXT: sshll v5.8h, v5.8b, #0 -; NEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NEON-NOSVE-NEXT: sshll2 v18.4s, v16.8h, #0 -; NEON-NOSVE-NEXT: sshll v16.4s, v16.4h, #0 -; NEON-NOSVE-NEXT: sdivr z17.s, p0/m, z17.s, z18.s -; NEON-NOSVE-NEXT: sshll2 v18.4s, v5.8h, #0 -; NEON-NOSVE-NEXT: sshll v5.4s, v5.4h, #0 -; NEON-NOSVE-NEXT: sdivr z7.s, p0/m, z7.s, z16.s -; NEON-NOSVE-NEXT: sshll2 v16.4s, v6.8h, #0 -; NEON-NOSVE-NEXT: sshll v6.4s, v6.4h, #0 -; NEON-NOSVE-NEXT: sdivr z16.s, p0/m, z16.s, z18.s -; NEON-NOSVE-NEXT: sdiv z5.s, p0/m, z5.s, z6.s -; NEON-NOSVE-NEXT: sdiv z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: uzp1 v3.8h, v7.8h, v17.8h -; NEON-NOSVE-NEXT: uzp1 v5.8h, v5.8h, v16.8h -; NEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v4.8h -; NEON-NOSVE-NEXT: uzp1 v2.16b, v5.16b, v3.16b -; NEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NEON-NOSVE-NEXT: stp q2, q0, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v32i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -571,17 +471,6 @@ define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v2i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: shl v1.2s, v1.2s, #16 -; NEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16 -; NEON-NOSVE-NEXT: ptrue p0.s, vl2 -; NEON-NOSVE-NEXT: sshr v1.2s, v1.2s, #16 -; NEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v2i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -614,15 +503,6 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v4i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v4i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -664,26 +544,14 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: sunpklo z1.s, z1.h ; CHECK-NEXT: sunpklo z0.s, z0.h ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; CHECK-NEXT: sdivr z1.s, p0/m, z1.s, z0.s +; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v8i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: sshll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v8i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -748,41 +616,18 @@ define void @sdiv_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 ; CHECK-NEXT: sunpklo z3.s, z3.h ; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sdiv z3.s, p0/m, z3.s, z4.s +; CHECK-NEXT: uzp1 z4.h, z5.h, z5.h ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z0.h -; CHECK-NEXT: stp q1, q2, [x0] +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z1.h, p0, { z1.h, z2.h } +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v16i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q4, q1, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NEON-NOSVE-NEXT: sshll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: sshll2 v5.4s, v4.8h, #0 -; NEON-NOSVE-NEXT: sshll v4.4s, v4.4h, #0 -; NEON-NOSVE-NEXT: sshll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: sshll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: sdivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: ldr q3, [x0] -; NEON-NOSVE-NEXT: sshll2 v6.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: sshll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: sdivr z5.s, p0/m, z5.s, z6.s -; NEON-NOSVE-NEXT: sdiv z3.s, p0/m, z3.s, z4.s -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v5.8h -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: stp q1, q0, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v16i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -876,15 +721,6 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v2i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.s, vl2 -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $z1 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v2i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -913,15 +749,6 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v4i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $q1 killed $q1 def $z1 -; NEON-NOSVE-NEXT: sdiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v4i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -957,17 +784,6 @@ define void @sdiv_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v8i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: sdivr z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: movprfx z1, z2 -; NEON-NOSVE-NEXT: sdiv z1.s, p0/m, z1.s, z3.s -; NEON-NOSVE-NEXT: stp q0, q1, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v8i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -1021,15 +837,6 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v1i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.d, vl1 -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $z1 -; NEON-NOSVE-NEXT: sdiv z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v1i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #16 @@ -1055,15 +862,6 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v2i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $q1 killed $q1 def $z1 -; NEON-NOSVE-NEXT: sdiv z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v2i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -1093,17 +891,6 @@ define void @sdiv_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: sdiv_v4i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: sdivr z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: movprfx z1, z2 -; NEON-NOSVE-NEXT: sdiv z1.d, p0/m, z1.d, z3.d -; NEON-NOSVE-NEXT: stp q0, q1, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: sdiv_v4i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -1135,9 +922,7 @@ define void @sdiv_v4i64(ptr %a, ptr %b) { ret void } -; ; UDIV -; define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-LABEL: udiv_v4i8: @@ -1154,17 +939,6 @@ define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v4i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: bic v0.4h, #255, lsl #8 -; NEON-NOSVE-NEXT: bic v1.4h, #255, lsl #8 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v4i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -1211,27 +985,12 @@ define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } +; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v8i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ushll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: xtn v0.8b, v0.8h -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v8i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -1303,45 +1062,21 @@ define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8 ; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z4.h, z4.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z1.h, p0, { z1.h, z2.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z2.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z3.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v16i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ushll2 v2.8h, v1.16b, #0 -; NEON-NOSVE-NEXT: ushll2 v3.8h, v0.16b, #0 -; NEON-NOSVE-NEXT: ushll v1.8h, v1.8b, #0 -; NEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ushll2 v4.4s, v2.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v5.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: udivr z4.s, p0/m, z4.s, z5.s -; NEON-NOSVE-NEXT: ushll2 v5.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: ushll2 v3.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: udivr z3.s, p0/m, z3.s, z5.s -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v4.8h -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v3.8h -; NEON-NOSVE-NEXT: uzp1 v0.16b, v0.16b, v1.16b -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v16i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -1445,7 +1180,6 @@ define void @udiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: uunpklo z4.h, z2.b ; CHECK-NEXT: uunpklo z2.s, z3.h ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: uunpklo z5.s, z4.h ; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8 ; CHECK-NEXT: uunpklo z3.s, z3.h @@ -1454,7 +1188,6 @@ define void @udiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ldr q5, [x0] ; CHECK-NEXT: uunpklo z16.h, z5.b ; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h ; CHECK-NEXT: uunpklo z5.h, z5.b ; CHECK-NEXT: uunpklo z18.s, z16.h ; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8 @@ -1463,81 +1196,36 @@ define void @udiv_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: uunpklo z18.s, z5.h ; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8 ; CHECK-NEXT: uunpklo z5.s, z5.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z16.s ; CHECK-NEXT: uunpklo z16.s, z6.h ; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8 ; CHECK-NEXT: uunpklo z6.s, z6.h +; CHECK-NEXT: uzp1 z20.h, z17.h, z17.h ; CHECK-NEXT: udivr z16.s, p0/m, z16.s, z18.s +; CHECK-NEXT: uzp1 z18.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z21.h, z7.h, z7.h ; CHECK-NEXT: udiv z5.s, p0/m, z5.s, z6.s -; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h -; CHECK-NEXT: uzp1 z7.h, z16.h, z16.h +; CHECK-NEXT: uzp1 z0.h, z16.h, z16.h ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s -; CHECK-NEXT: uzp1 z4.h, z17.h, z17.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z6.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z1.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z1.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z20.h, z21.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z1.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z4.b, z2.b, z2.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: splice z1.b, p0, z1.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z2.b -; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: uzp1 z2.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z3.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z4.b, z5.b } +; CHECK-NEXT: splice z1.b, p0, { z2.b, z3.b } +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v32i8: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q6, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldr q2, [x0, #16] -; NEON-NOSVE-NEXT: ushll2 v1.8h, v3.16b, #0 -; NEON-NOSVE-NEXT: ushll2 v4.8h, v2.16b, #0 -; NEON-NOSVE-NEXT: ushll v3.8h, v3.8b, #0 -; NEON-NOSVE-NEXT: ushll v2.8h, v2.8b, #0 -; NEON-NOSVE-NEXT: ushll2 v7.8h, v6.16b, #0 -; NEON-NOSVE-NEXT: ushll v6.8h, v6.8b, #0 -; NEON-NOSVE-NEXT: ushll2 v0.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v5.4s, v4.8h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v4.4s, v4.4h, #0 -; NEON-NOSVE-NEXT: ushll2 v17.4s, v7.8h, #0 -; NEON-NOSVE-NEXT: ushll v7.4s, v7.4h, #0 -; NEON-NOSVE-NEXT: udivr z0.s, p0/m, z0.s, z5.s -; NEON-NOSVE-NEXT: ushll2 v5.4s, v2.8h, #0 -; NEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0 -; NEON-NOSVE-NEXT: udivr z1.s, p0/m, z1.s, z4.s -; NEON-NOSVE-NEXT: ushll2 v4.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: udivr z4.s, p0/m, z4.s, z5.s -; NEON-NOSVE-NEXT: ldr q5, [x0] -; NEON-NOSVE-NEXT: ushll2 v16.8h, v5.16b, #0 -; NEON-NOSVE-NEXT: ushll v5.8h, v5.8b, #0 -; NEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h -; NEON-NOSVE-NEXT: ushll2 v18.4s, v16.8h, #0 -; NEON-NOSVE-NEXT: ushll v16.4s, v16.4h, #0 -; NEON-NOSVE-NEXT: udivr z17.s, p0/m, z17.s, z18.s -; NEON-NOSVE-NEXT: ushll2 v18.4s, v5.8h, #0 -; NEON-NOSVE-NEXT: ushll v5.4s, v5.4h, #0 -; NEON-NOSVE-NEXT: udivr z7.s, p0/m, z7.s, z16.s -; NEON-NOSVE-NEXT: ushll2 v16.4s, v6.8h, #0 -; NEON-NOSVE-NEXT: ushll v6.4s, v6.4h, #0 -; NEON-NOSVE-NEXT: udivr z16.s, p0/m, z16.s, z18.s -; NEON-NOSVE-NEXT: udiv z5.s, p0/m, z5.s, z6.s -; NEON-NOSVE-NEXT: udiv z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: uzp1 v3.8h, v7.8h, v17.8h -; NEON-NOSVE-NEXT: uzp1 v5.8h, v5.8h, v16.8h -; NEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v4.8h -; NEON-NOSVE-NEXT: uzp1 v2.16b, v5.16b, v3.16b -; NEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b -; NEON-NOSVE-NEXT: stp q2, q0, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v32i8: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -1697,16 +1385,6 @@ define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v2i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: movi d2, #0x00ffff0000ffff -; NEON-NOSVE-NEXT: ptrue p0.s, vl2 -; NEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b -; NEON-NOSVE-NEXT: and v0.8b, v0.8b, v2.8b -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v2i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -1739,15 +1417,6 @@ define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v4i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: xtn v0.4h, v0.4s -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v4i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -1789,26 +1458,14 @@ define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: uunpklo z1.s, z1.h ; CHECK-NEXT: uunpklo z0.s, z0.h ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; CHECK-NEXT: udivr z1.s, p0/m, z1.s, z0.s +; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v8i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ushll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v8i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -1873,41 +1530,18 @@ define void @udiv_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 ; CHECK-NEXT: uunpklo z3.s, z3.h ; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: udiv z3.s, p0/m, z3.s, z4.s +; CHECK-NEXT: uzp1 z4.h, z5.h, z5.h ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z3.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z0.h -; CHECK-NEXT: stp q1, q2, [x0] +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z2.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z1.h, p0, { z1.h, z2.h } +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v16i16: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q4, q1, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldr q0, [x0, #16] -; NEON-NOSVE-NEXT: ushll2 v2.4s, v1.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v3.4s, v0.8h, #0 -; NEON-NOSVE-NEXT: ushll2 v5.4s, v4.8h, #0 -; NEON-NOSVE-NEXT: ushll v4.4s, v4.4h, #0 -; NEON-NOSVE-NEXT: ushll v1.4s, v1.4h, #0 -; NEON-NOSVE-NEXT: ushll v0.4s, v0.4h, #0 -; NEON-NOSVE-NEXT: udivr z2.s, p0/m, z2.s, z3.s -; NEON-NOSVE-NEXT: ldr q3, [x0] -; NEON-NOSVE-NEXT: ushll2 v6.4s, v3.8h, #0 -; NEON-NOSVE-NEXT: ushll v3.4s, v3.4h, #0 -; NEON-NOSVE-NEXT: udivr z5.s, p0/m, z5.s, z6.s -; NEON-NOSVE-NEXT: udiv z3.s, p0/m, z3.s, z4.s -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: uzp1 v1.8h, v3.8h, v5.8h -; NEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v2.8h -; NEON-NOSVE-NEXT: stp q1, q0, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v16i16: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -2001,15 +1635,6 @@ define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v2i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.s, vl2 -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $z1 -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v2i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #32 @@ -2038,15 +1663,6 @@ define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v4i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $q1 killed $q1 def $z1 -; NEON-NOSVE-NEXT: udiv z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v4i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -2082,17 +1698,6 @@ define void @udiv_v8i32(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v8i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.s, vl4 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: udivr z0.s, p0/m, z0.s, z1.s -; NEON-NOSVE-NEXT: movprfx z1, z2 -; NEON-NOSVE-NEXT: udiv z1.s, p0/m, z1.s, z3.s -; NEON-NOSVE-NEXT: stp q0, q1, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v8i32: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -2146,15 +1751,6 @@ define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) { ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v1i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.d, vl1 -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $d1 killed $d1 def $z1 -; NEON-NOSVE-NEXT: udiv z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v1i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #16 @@ -2180,15 +1776,6 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) { ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v2i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 def $z0 -; NEON-NOSVE-NEXT: // kill: def $q1 killed $q1 def $z1 -; NEON-NOSVE-NEXT: udiv z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: // kill: def $q0 killed $q0 killed $z0 -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v2i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-48]! @@ -2218,17 +1805,6 @@ define void @udiv_v4i64(ptr %a, ptr %b) { ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret ; -; NEON-NOSVE-LABEL: udiv_v4i64: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: ldp q0, q3, [x1] -; NEON-NOSVE-NEXT: ptrue p0.d, vl2 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: udivr z0.d, p0/m, z0.d, z1.d -; NEON-NOSVE-NEXT: movprfx z1, z2 -; NEON-NOSVE-NEXT: udiv z1.d, p0/m, z1.d, z3.d -; NEON-NOSVE-NEXT: stp q0, q1, [x0] -; NEON-NOSVE-NEXT: ret -; ; NONEON-NOSVE-LABEL: udiv_v4i64: ; NONEON-NOSVE: // %bb.0: ; NONEON-NOSVE-NEXT: sub sp, sp, #96 @@ -2261,64 +1837,22 @@ define void @udiv_v4i64(ptr %a, ptr %b) { } define void @udiv_constantsplat_v8i32(ptr %a) { -; SVE-LABEL: udiv_constantsplat_v8i32: -; SVE: // %bb.0: -; SVE-NEXT: mov w8, #8969 // =0x2309 -; SVE-NEXT: ldp q1, q2, [x0] -; SVE-NEXT: movk w8, #22765, lsl #16 -; SVE-NEXT: ptrue p0.s, vl4 -; SVE-NEXT: mov z0.s, w8 -; SVE-NEXT: movprfx z3, z1 -; SVE-NEXT: umulh z3.s, p0/m, z3.s, z0.s -; SVE-NEXT: umulh z0.s, p0/m, z0.s, z2.s -; SVE-NEXT: sub z1.s, z1.s, z3.s -; SVE-NEXT: sub z2.s, z2.s, z0.s -; SVE-NEXT: lsr z1.s, z1.s, #1 -; SVE-NEXT: lsr z2.s, z2.s, #1 -; SVE-NEXT: add z1.s, z1.s, z3.s -; SVE-NEXT: add z0.s, z2.s, z0.s -; SVE-NEXT: lsr z1.s, z1.s, #6 -; SVE-NEXT: lsr z0.s, z0.s, #6 -; SVE-NEXT: stp q1, q0, [x0] -; SVE-NEXT: ret -; -; SVE2-LABEL: udiv_constantsplat_v8i32: -; SVE2: // %bb.0: -; SVE2-NEXT: mov w8, #8969 // =0x2309 -; SVE2-NEXT: ldp q1, q2, [x0] -; SVE2-NEXT: movk w8, #22765, lsl #16 -; SVE2-NEXT: mov z0.s, w8 -; SVE2-NEXT: umulh z3.s, z1.s, z0.s -; SVE2-NEXT: umulh z0.s, z2.s, z0.s -; SVE2-NEXT: sub z1.s, z1.s, z3.s -; SVE2-NEXT: sub z2.s, z2.s, z0.s -; SVE2-NEXT: usra z3.s, z1.s, #1 -; SVE2-NEXT: usra z0.s, z2.s, #1 -; SVE2-NEXT: lsr z1.s, z3.s, #6 -; SVE2-NEXT: lsr z0.s, z0.s, #6 -; SVE2-NEXT: stp q1, q0, [x0] -; SVE2-NEXT: ret -; -; NEON-NOSVE-LABEL: udiv_constantsplat_v8i32: -; NEON-NOSVE: // %bb.0: -; NEON-NOSVE-NEXT: mov w8, #8969 // =0x2309 -; NEON-NOSVE-NEXT: ldp q1, q2, [x0] -; NEON-NOSVE-NEXT: movk w8, #22765, lsl #16 -; NEON-NOSVE-NEXT: dup v0.4s, w8 -; NEON-NOSVE-NEXT: umull2 v3.2d, v1.4s, v0.4s -; NEON-NOSVE-NEXT: umull v4.2d, v1.2s, v0.2s -; NEON-NOSVE-NEXT: umull2 v5.2d, v2.4s, v0.4s -; NEON-NOSVE-NEXT: umull v0.2d, v2.2s, v0.2s -; NEON-NOSVE-NEXT: uzp2 v3.4s, v4.4s, v3.4s -; NEON-NOSVE-NEXT: uzp2 v0.4s, v0.4s, v5.4s -; NEON-NOSVE-NEXT: sub v1.4s, v1.4s, v3.4s -; NEON-NOSVE-NEXT: sub v2.4s, v2.4s, v0.4s -; NEON-NOSVE-NEXT: usra v3.4s, v1.4s, #1 -; NEON-NOSVE-NEXT: usra v0.4s, v2.4s, #1 -; NEON-NOSVE-NEXT: ushr v1.4s, v3.4s, #6 -; NEON-NOSVE-NEXT: ushr v0.4s, v0.4s, #6 -; NEON-NOSVE-NEXT: stp q1, q0, [x0] -; NEON-NOSVE-NEXT: ret +; CHECK-LABEL: udiv_constantsplat_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov w8, #8969 // =0x2309 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: movk w8, #22765, lsl #16 +; CHECK-NEXT: mov z0.s, w8 +; CHECK-NEXT: umulh z3.s, z1.s, z0.s +; CHECK-NEXT: umulh z0.s, z2.s, z0.s +; CHECK-NEXT: sub z1.s, z1.s, z3.s +; CHECK-NEXT: sub z2.s, z2.s, z0.s +; CHECK-NEXT: usra z3.s, z1.s, #1 +; CHECK-NEXT: usra z0.s, z2.s, #1 +; CHECK-NEXT: lsr z1.s, z3.s, #6 +; CHECK-NEXT: lsr z0.s, z0.s, #6 +; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: udiv_constantsplat_v8i32: ; NONEON-NOSVE: // %bb.0: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll index b4641172f8b06d870929a1af717dd02929555bbc..9497ec88e57b4da90f8a047fc9811c13b78a43aa 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -76,10 +76,10 @@ define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: uzp1 z3.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z3.h, z4.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z2.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -160,23 +160,23 @@ define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: mov z3.d, z1.d ; CHECK-NEXT: sunpklo z5.s, z5.h ; CHECK-NEXT: ext z3.b, z3.b, z1.b, #8 -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h ; CHECK-NEXT: sunpklo z3.h, z3.b ; CHECK-NEXT: sunpklo z6.s, z3.h ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 ; CHECK-NEXT: sunpklo z3.s, z3.h ; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z4.h, p0, z4.h, z2.h -; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z4.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z7.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z6.h, z7.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b +; CHECK-NEXT: uzp1 z5.b, z3.b, z3.b +; CHECK-NEXT: splice z2.b, p0, { z4.b, z5.b } ; CHECK-NEXT: ptrue p0.b, vl16 ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 @@ -300,14 +300,12 @@ define void @srem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: sunpklo z4.s, z16.h ; CHECK-NEXT: ext z7.b, z7.b, z7.b, #8 ; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sunpklo z7.s, z7.h ; CHECK-NEXT: movprfx z6, z4 ; CHECK-NEXT: sdiv z6.s, p0/m, z6.s, z3.s ; CHECK-NEXT: ldr q3, [x0] ; CHECK-NEXT: ldr q4, [x1] ; CHECK-NEXT: sunpklo z16.s, z16.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h ; CHECK-NEXT: sunpklo z17.h, z4.b ; CHECK-NEXT: sunpklo z18.h, z3.b ; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z16.s @@ -317,11 +315,9 @@ define void @srem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ext z18.b, z18.b, z18.b, #8 ; CHECK-NEXT: sunpklo z17.s, z17.h ; CHECK-NEXT: sunpklo z18.s, z18.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h ; CHECK-NEXT: sdivr z19.s, p0/m, z19.s, z20.s ; CHECK-NEXT: mov z20.d, z3.d ; CHECK-NEXT: ext z20.b, z20.b, z3.b, #8 -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h ; CHECK-NEXT: sunpklo z20.h, z20.b ; CHECK-NEXT: sunpklo z22.s, z20.h ; CHECK-NEXT: ext z20.b, z20.b, z20.b, #8 @@ -329,32 +325,36 @@ define void @srem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: mov z18.d, z4.d ; CHECK-NEXT: sunpklo z20.s, z20.h ; CHECK-NEXT: ext z18.b, z18.b, z4.b, #8 -; CHECK-NEXT: uzp1 z16.h, z19.h, z19.h ; CHECK-NEXT: sunpklo z18.h, z18.b ; CHECK-NEXT: sunpklo z21.s, z18.h ; CHECK-NEXT: ext z18.b, z18.b, z18.b, #8 ; CHECK-NEXT: sunpklo z18.s, z18.h ; CHECK-NEXT: sdivr z21.s, p0/m, z21.s, z22.s -; CHECK-NEXT: uzp1 z17.h, z17.h, z17.h +; CHECK-NEXT: uzp1 z22.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z23.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h ; CHECK-NEXT: sdivr z18.s, p0/m, z18.s, z20.s +; CHECK-NEXT: uzp1 z19.h, z19.h, z19.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z16.h, p0, z16.h, z17.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: uzp1 z19.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z5.b, z16.b, z16.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b -; CHECK-NEXT: uzp1 z18.h, z18.h, z18.h -; CHECK-NEXT: splice z19.h, p0, z19.h, z18.h +; CHECK-NEXT: uzp1 z20.h, z17.h, z17.h +; CHECK-NEXT: splice z7.h, p0, { z22.h, z23.h } +; CHECK-NEXT: splice z5.h, p0, { z5.h, z6.h } +; CHECK-NEXT: uzp1 z16.h, z21.h, z21.h +; CHECK-NEXT: splice z2.h, p0, { z19.h, z20.h } +; CHECK-NEXT: uzp1 z6.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z7.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z17.h, z18.h, z18.h +; CHECK-NEXT: splice z16.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z17.b, z2.b, z2.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: splice z2.b, p0, z2.b, z6.b -; CHECK-NEXT: uzp1 z7.b, z19.b, z19.b -; CHECK-NEXT: splice z5.b, p0, z5.b, z7.b +; CHECK-NEXT: splice z5.b, p0, { z6.b, z7.b } +; CHECK-NEXT: uzp1 z18.b, z16.b, z16.b +; CHECK-NEXT: splice z2.b, p0, { z17.b, z18.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b -; CHECK-NEXT: mls z3.b, p0/m, z5.b, z4.b -; CHECK-NEXT: stp q3, q0, [x0] +; CHECK-NEXT: mls z0.b, p0/m, z5.b, z1.b +; CHECK-NEXT: msb z2.b, p0/m, z4.b, z3.b +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: srem_v32i8: @@ -600,9 +600,9 @@ define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: sunpklo z3.s, z3.h ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } ; CHECK-NEXT: ptrue p0.h, vl8 ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 @@ -680,23 +680,23 @@ define void @srem_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: sdivr z5.s, p0/m, z5.s, z6.s ; CHECK-NEXT: mov z6.d, z4.d ; CHECK-NEXT: ext z6.b, z6.b, z4.b, #8 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: sunpklo z6.s, z6.h ; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s ; CHECK-NEXT: mov z7.d, z1.d ; CHECK-NEXT: ext z7.b, z7.b, z1.b, #8 -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h ; CHECK-NEXT: sunpklo z7.s, z7.h ; CHECK-NEXT: sdivr z7.s, p0/m, z7.s, z16.s +; CHECK-NEXT: uzp1 z16.h, z5.h, z5.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z6.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z7.h +; CHECK-NEXT: uzp1 z17.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h +; CHECK-NEXT: splice z5.h, p0, { z5.h, z6.h } ; CHECK-NEXT: ptrue p0.h, vl8 -; CHECK-NEXT: mls z3.h, p0/m, z5.h, z4.h -; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h -; CHECK-NEXT: stp q3, q0, [x0] +; CHECK-NEXT: msb z2.h, p0/m, z4.h, z3.h +; CHECK-NEXT: mls z0.h, p0/m, z5.h, z1.h +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: srem_v16i16: @@ -1126,10 +1126,10 @@ define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) { ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: uzp1 z3.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z3.h, z4.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z2.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -1210,23 +1210,23 @@ define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) { ; CHECK-NEXT: mov z3.d, z1.d ; CHECK-NEXT: uunpklo z5.s, z5.h ; CHECK-NEXT: ext z3.b, z3.b, z1.b, #8 -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h ; CHECK-NEXT: uunpklo z3.h, z3.b ; CHECK-NEXT: uunpklo z6.s, z3.h ; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8 ; CHECK-NEXT: uunpklo z3.s, z3.h ; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z4.h, p0, z4.h, z2.h -; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z4.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z7.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z6.h, z7.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b +; CHECK-NEXT: uzp1 z5.b, z3.b, z3.b +; CHECK-NEXT: splice z2.b, p0, { z4.b, z5.b } ; CHECK-NEXT: ptrue p0.b, vl16 ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 @@ -1350,14 +1350,12 @@ define void @urem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: uunpklo z4.s, z16.h ; CHECK-NEXT: ext z7.b, z7.b, z7.b, #8 ; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: uunpklo z7.s, z7.h ; CHECK-NEXT: movprfx z6, z4 ; CHECK-NEXT: udiv z6.s, p0/m, z6.s, z3.s ; CHECK-NEXT: ldr q3, [x0] ; CHECK-NEXT: ldr q4, [x1] ; CHECK-NEXT: uunpklo z16.s, z16.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h ; CHECK-NEXT: uunpklo z17.h, z4.b ; CHECK-NEXT: uunpklo z18.h, z3.b ; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z16.s @@ -1367,11 +1365,9 @@ define void @urem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: ext z18.b, z18.b, z18.b, #8 ; CHECK-NEXT: uunpklo z17.s, z17.h ; CHECK-NEXT: uunpklo z18.s, z18.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h ; CHECK-NEXT: udivr z19.s, p0/m, z19.s, z20.s ; CHECK-NEXT: mov z20.d, z3.d ; CHECK-NEXT: ext z20.b, z20.b, z3.b, #8 -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h ; CHECK-NEXT: uunpklo z20.h, z20.b ; CHECK-NEXT: uunpklo z22.s, z20.h ; CHECK-NEXT: ext z20.b, z20.b, z20.b, #8 @@ -1379,32 +1375,36 @@ define void @urem_v32i8(ptr %a, ptr %b) { ; CHECK-NEXT: mov z18.d, z4.d ; CHECK-NEXT: uunpklo z20.s, z20.h ; CHECK-NEXT: ext z18.b, z18.b, z4.b, #8 -; CHECK-NEXT: uzp1 z16.h, z19.h, z19.h ; CHECK-NEXT: uunpklo z18.h, z18.b ; CHECK-NEXT: uunpklo z21.s, z18.h ; CHECK-NEXT: ext z18.b, z18.b, z18.b, #8 ; CHECK-NEXT: uunpklo z18.s, z18.h ; CHECK-NEXT: udivr z21.s, p0/m, z21.s, z22.s -; CHECK-NEXT: uzp1 z17.h, z17.h, z17.h +; CHECK-NEXT: uzp1 z22.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z23.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h ; CHECK-NEXT: udivr z18.s, p0/m, z18.s, z20.s +; CHECK-NEXT: uzp1 z19.h, z19.h, z19.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: splice z16.h, p0, z16.h, z17.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: uzp1 z19.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z5.b, z16.b, z16.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b -; CHECK-NEXT: uzp1 z18.h, z18.h, z18.h -; CHECK-NEXT: splice z19.h, p0, z19.h, z18.h +; CHECK-NEXT: uzp1 z20.h, z17.h, z17.h +; CHECK-NEXT: splice z7.h, p0, { z22.h, z23.h } +; CHECK-NEXT: splice z5.h, p0, { z5.h, z6.h } +; CHECK-NEXT: uzp1 z16.h, z21.h, z21.h +; CHECK-NEXT: splice z2.h, p0, { z19.h, z20.h } +; CHECK-NEXT: uzp1 z6.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z7.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z17.h, z18.h, z18.h +; CHECK-NEXT: splice z16.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z17.b, z2.b, z2.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: splice z2.b, p0, z2.b, z6.b -; CHECK-NEXT: uzp1 z7.b, z19.b, z19.b -; CHECK-NEXT: splice z5.b, p0, z5.b, z7.b +; CHECK-NEXT: splice z5.b, p0, { z6.b, z7.b } +; CHECK-NEXT: uzp1 z18.b, z16.b, z16.b +; CHECK-NEXT: splice z2.b, p0, { z17.b, z18.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b -; CHECK-NEXT: mls z3.b, p0/m, z5.b, z4.b -; CHECK-NEXT: stp q3, q0, [x0] +; CHECK-NEXT: mls z0.b, p0/m, z5.b, z1.b +; CHECK-NEXT: msb z2.b, p0/m, z4.b, z3.b +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: urem_v32i8: @@ -1650,9 +1650,9 @@ define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) { ; CHECK-NEXT: uunpklo z3.s, z3.h ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h +; CHECK-NEXT: uzp1 z4.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z5.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } ; CHECK-NEXT: ptrue p0.h, vl8 ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 @@ -1730,23 +1730,23 @@ define void @urem_v16i16(ptr %a, ptr %b) { ; CHECK-NEXT: udivr z5.s, p0/m, z5.s, z6.s ; CHECK-NEXT: mov z6.d, z4.d ; CHECK-NEXT: ext z6.b, z6.b, z4.b, #8 -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h ; CHECK-NEXT: uunpklo z6.s, z6.h ; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s ; CHECK-NEXT: mov z7.d, z1.d ; CHECK-NEXT: ext z7.b, z7.b, z1.b, #8 -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h ; CHECK-NEXT: uunpklo z7.s, z7.h ; CHECK-NEXT: udivr z7.s, p0/m, z7.s, z16.s +; CHECK-NEXT: uzp1 z16.h, z5.h, z5.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z6.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z7.h +; CHECK-NEXT: uzp1 z17.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z5.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z6.h, z7.h, z7.h +; CHECK-NEXT: splice z5.h, p0, { z5.h, z6.h } ; CHECK-NEXT: ptrue p0.h, vl8 -; CHECK-NEXT: mls z3.h, p0/m, z5.h, z4.h -; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h -; CHECK-NEXT: stp q3, q0, [x0] +; CHECK-NEXT: msb z2.h, p0/m, z4.h, z3.h +; CHECK-NEXT: mls z0.h, p0/m, z5.h, z1.h +; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: urem_v16i16: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll index 5235423c00d9a1178c64fb6fd8db42853d8d4466..e07036f2a1acfc14d5caeef349268d8ee57633bb 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -11,28 +11,28 @@ define i1 @ptest_v16i1(ptr %a, ptr %b) { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] +; CHECK-NEXT: ldp q3, q2, [x0] ; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.0 ; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: fcmne p3.s, p0/z, z3.s, #0.0 -; CHECK-NEXT: fcmne p0.s, p0/z, z2.s, #0.0 +; CHECK-NEXT: fcmne p3.s, p0/z, z2.s, #0.0 +; CHECK-NEXT: fcmne p0.s, p0/z, z3.s, #0.0 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z0.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b +; CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: umaxv b0, p0, z1.b +; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret @@ -120,49 +120,49 @@ define i1 @ptest_v16i1(ptr %a, ptr %b) { define i1 @ptest_or_v16i1(ptr %a, ptr %b) { ; CHECK-LABEL: ptest_or_v16i1: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x1, #32] -; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.0 -; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: ldp q2, q3, [x1, #32] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, #0.0 +; CHECK-NEXT: ldp q1, q6, [x1] ; CHECK-NEXT: fcmne p3.s, p0/z, z3.s, #0.0 -; CHECK-NEXT: fcmne p4.s, p0/z, z2.s, #0.0 -; CHECK-NEXT: fcmne p5.s, p0/z, z5.s, #0.0 -; CHECK-NEXT: fcmne p6.s, p0/z, z4.s, #0.0 -; CHECK-NEXT: fcmne p7.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmne p2.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmne p5.s, p0/z, z2.s, #0.0 +; CHECK-NEXT: fcmne p4.s, p0/z, z5.s, #0.0 +; CHECK-NEXT: fcmne p7.s, p0/z, z4.s, #0.0 +; CHECK-NEXT: fcmne p6.s, p0/z, z6.s, #0.0 +; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, #0.0 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z4.s, p5/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h +; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z6.s, p7/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z7.s, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z17.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z16.h, z1.h, z1.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z4.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z6.h +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z18.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z0.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z2.h, z7.h, z7.h +; CHECK-NEXT: splice z4.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z5.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b -; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b -; CHECK-NEXT: splice z3.b, p0, z3.b, z2.b +; CHECK-NEXT: uzp1 z3.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z5.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z2.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } +; CHECK-NEXT: splice z1.b, p0, { z4.b, z5.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: orr z0.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d ; CHECK-NEXT: umaxv b0, p0, z0.b ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 @@ -329,49 +329,49 @@ declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>) define i1 @ptest_and_v16i1(ptr %a, ptr %b) { ; CHECK-LABEL: ptest_and_v16i1: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x1, #32] -; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.0 -; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: ldp q2, q3, [x1, #32] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: fcmne p1.s, p0/z, z1.s, #0.0 +; CHECK-NEXT: ldp q1, q6, [x1] ; CHECK-NEXT: fcmne p3.s, p0/z, z3.s, #0.0 -; CHECK-NEXT: fcmne p4.s, p0/z, z2.s, #0.0 -; CHECK-NEXT: fcmne p5.s, p0/z, z5.s, #0.0 -; CHECK-NEXT: fcmne p6.s, p0/z, z4.s, #0.0 -; CHECK-NEXT: fcmne p7.s, p0/z, z1.s, #0.0 -; CHECK-NEXT: fcmne p0.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmne p2.s, p0/z, z0.s, #0.0 +; CHECK-NEXT: fcmne p5.s, p0/z, z2.s, #0.0 +; CHECK-NEXT: fcmne p4.s, p0/z, z5.s, #0.0 +; CHECK-NEXT: fcmne p7.s, p0/z, z4.s, #0.0 +; CHECK-NEXT: fcmne p6.s, p0/z, z6.s, #0.0 +; CHECK-NEXT: fcmne p0.s, p0/z, z1.s, #0.0 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z4.s, p5/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h +; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z6.s, p7/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: mov z7.s, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z17.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z16.h, z1.h, z1.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z4.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z6.h +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z18.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z0.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z2.h, z7.h, z7.h +; CHECK-NEXT: splice z4.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z5.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b -; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b -; CHECK-NEXT: splice z3.b, p0, z3.b, z2.b +; CHECK-NEXT: uzp1 z3.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z5.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z2.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } +; CHECK-NEXT: splice z1.b, p0, { z4.b, z5.b } ; CHECK-NEXT: ptrue p0.b, vl16 -; CHECK-NEXT: and z0.d, z1.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z1.d ; CHECK-NEXT: uminv b0, p0, z0.b ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll index c0aa162b19b77df11c5c803fbba7702cc35b8384..13fcd94ea8a2606f722d92d1d16bb48c4f91e129 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc-stores.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -129,11 +129,11 @@ define void @store_trunc_v2i64i8(ptr %ap, ptr %dest) { define void @store_trunc_v2i256i64(ptr %ap, ptr %dest) { ; CHECK-LABEL: store_trunc_v2i256i64: ; CHECK: // %bb.0: +; CHECK-NEXT: ldr d1, [x0, #32] ; CHECK-NEXT: ptrue p0.d, vl1 -; CHECK-NEXT: ldr d0, [x0, #32] -; CHECK-NEXT: ldr d1, [x0] -; CHECK-NEXT: splice z1.d, p0, z1.d, z0.d -; CHECK-NEXT: str q1, [x1] +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: splice z0.d, p0, { z0.d, z1.d } +; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: store_trunc_v2i256i64: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll index 77aaeeadcfc2f0b918093a76a3142c6502c2890d..9d241f6f927e1174c5c0ba1a69c357a624c9f52d 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-trunc.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s +; RUN: llc -mattr=+sve2 -force-streaming-compatible < %s | FileCheck %s ; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s ; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE @@ -13,11 +13,11 @@ target triple = "aarch64-unknown-linux-gnu" define <16 x i8> @trunc_v16i16_v16i8(ptr %in) nounwind { ; CHECK-LABEL: trunc_v16i16_v16i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z3.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z2.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -69,18 +69,18 @@ define <16 x i8> @trunc_v16i16_v16i8(ptr %in) nounwind { define void @trunc_v32i16_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v32i16_v32i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b -; CHECK-NEXT: add z0.b, z0.b, z0.b +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z0.b, z3.b, z3.b +; CHECK-NEXT: splice z2.b, p0, { z4.b, z5.b } +; CHECK-NEXT: splice z0.b, p0, { z0.b, z1.b } ; CHECK-NEXT: add z1.b, z2.b, z2.b -; CHECK-NEXT: stp q1, q0, [x1] +; CHECK-NEXT: add z0.b, z0.b, z0.b +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v32i16_v32i8: @@ -216,27 +216,27 @@ define void @trunc_v32i16_v32i8(ptr %in, ptr %out) nounwind { define void @trunc_v64i16_v64i8(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v64i16_v64i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #64] +; CHECK-NEXT: ldp q1, q0, [x0, #64] ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: ldp q6, q7, [x0, #32] -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z5.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z4.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z7.b, z7.b, z7.b -; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b -; CHECK-NEXT: splice z4.b, p0, z4.b, z5.b -; CHECK-NEXT: splice z6.b, p0, z6.b, z7.b +; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: uzp1 z7.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z6.b, z1.b, z1.b +; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: uzp1 z17.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z16.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: splice z0.b, p0, { z6.b, z7.b } +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: splice z1.b, p0, { z16.b, z17.b } +; CHECK-NEXT: splice z2.b, p0, { z2.b, z3.b } +; CHECK-NEXT: splice z3.b, p0, { z4.b, z5.b } ; CHECK-NEXT: add z0.b, z0.b, z0.b +; CHECK-NEXT: add z1.b, z1.b, z1.b ; CHECK-NEXT: add z2.b, z2.b, z2.b -; CHECK-NEXT: add z1.b, z4.b, z4.b -; CHECK-NEXT: add z3.b, z6.b, z6.b +; CHECK-NEXT: add z3.b, z3.b, z3.b ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret @@ -527,49 +527,49 @@ define void @trunc_v128i16_v128i8(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #192] ; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: ldp q4, q5, [x0] ; CHECK-NEXT: ldp q6, q7, [x0, #64] -; CHECK-NEXT: ldp q16, q17, [x0, #224] -; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b -; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b -; CHECK-NEXT: ldp q20, q21, [x0, #160] -; CHECK-NEXT: uzp1 z7.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z17.b, z3.b, z3.b +; CHECK-NEXT: ldp q3, q18, [x0, #224] +; CHECK-NEXT: uzp1 z16.b, z2.b, z2.b +; CHECK-NEXT: ldp q2, q19, [x0, #128] ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: uzp1 z17.b, z17.b, z17.b -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: uzp1 z16.b, z16.b, z16.b -; CHECK-NEXT: ldp q18, q19, [x0, #128] -; CHECK-NEXT: splice z2.b, p0, z2.b, z3.b -; CHECK-NEXT: uzp1 z3.b, z21.b, z21.b -; CHECK-NEXT: uzp1 z20.b, z20.b, z20.b -; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b -; CHECK-NEXT: ldp q21, q22, [x0] -; CHECK-NEXT: splice z16.b, p0, z16.b, z17.b +; CHECK-NEXT: uzp1 z21.b, z18.b, z18.b +; CHECK-NEXT: ldp q18, q22, [x0, #160] +; CHECK-NEXT: uzp1 z20.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z24.b, z19.b, z19.b +; CHECK-NEXT: ldp q3, q19, [x0, #96] +; CHECK-NEXT: uzp1 z23.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z26.b, z22.b, z22.b +; CHECK-NEXT: splice z2.b, p0, { z16.b, z17.b } +; CHECK-NEXT: uzp1 z17.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z25.b, z18.b, z18.b +; CHECK-NEXT: splice z7.b, p0, { z20.b, z21.b } +; CHECK-NEXT: uzp1 z21.b, z5.b, z5.b ; CHECK-NEXT: uzp1 z19.b, z19.b, z19.b -; CHECK-NEXT: uzp1 z18.b, z18.b, z18.b -; CHECK-NEXT: uzp1 z4.b, z4.b, z4.b -; CHECK-NEXT: splice z20.b, p0, z20.b, z3.b -; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b -; CHECK-NEXT: splice z6.b, p0, z6.b, z7.b -; CHECK-NEXT: uzp1 z5.b, z22.b, z22.b -; CHECK-NEXT: uzp1 z7.b, z21.b, z21.b -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: splice z18.b, p0, z18.b, z19.b -; CHECK-NEXT: add z2.b, z2.b, z2.b -; CHECK-NEXT: splice z4.b, p0, z4.b, z3.b -; CHECK-NEXT: add z3.b, z16.b, z16.b -; CHECK-NEXT: splice z7.b, p0, z7.b, z5.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b -; CHECK-NEXT: add z1.b, z20.b, z20.b -; CHECK-NEXT: add z5.b, z18.b, z18.b -; CHECK-NEXT: stp q2, q3, [x1, #96] -; CHECK-NEXT: add z2.b, z6.b, z6.b +; CHECK-NEXT: uzp1 z20.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z5.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z16.b, z6.b, z6.b +; CHECK-NEXT: splice z6.b, p0, { z23.b, z24.b } +; CHECK-NEXT: uzp1 z18.b, z3.b, z3.b +; CHECK-NEXT: splice z3.b, p0, { z25.b, z26.b } +; CHECK-NEXT: uzp1 z4.b, z0.b, z0.b +; CHECK-NEXT: add z0.b, z2.b, z2.b +; CHECK-NEXT: add z7.b, z7.b, z7.b +; CHECK-NEXT: splice z1.b, p0, { z16.b, z17.b } +; CHECK-NEXT: splice z2.b, p0, { z18.b, z19.b } +; CHECK-NEXT: splice z16.b, p0, { z20.b, z21.b } +; CHECK-NEXT: splice z4.b, p0, { z4.b, z5.b } +; CHECK-NEXT: add z6.b, z6.b, z6.b +; CHECK-NEXT: add z3.b, z3.b, z3.b +; CHECK-NEXT: stp q0, q7, [x1, #96] +; CHECK-NEXT: add z0.b, z1.b, z1.b +; CHECK-NEXT: add z1.b, z2.b, z2.b +; CHECK-NEXT: add z2.b, z16.b, z16.b +; CHECK-NEXT: stp q6, q3, [x1, #64] ; CHECK-NEXT: add z3.b, z4.b, z4.b -; CHECK-NEXT: add z4.b, z7.b, z7.b -; CHECK-NEXT: add z0.b, z0.b, z0.b -; CHECK-NEXT: stp q5, q1, [x1, #64] -; CHECK-NEXT: stp q2, q3, [x1, #32] -; CHECK-NEXT: stp q4, q0, [x1] +; CHECK-NEXT: stp q0, q1, [x1, #32] +; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v128i16_v128i8: @@ -1181,11 +1181,11 @@ define void @trunc_v128i16_v128i8(ptr %in, ptr %out) nounwind { define <8 x i8> @trunc_v8i32_v8i8(ptr %in) nounwind { ; CHECK-LABEL: trunc_v8i32_v8i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z3.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z1.h, z1.h +; CHECK-NEXT: splice z0.h, p0, { z2.h, z3.h } ; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -1219,17 +1219,17 @@ define <16 x i8> @trunc_v16i32_v16i8(ptr %in) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z0.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b -; CHECK-NEXT: uzp1 z0.b, z2.b, z2.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b +; CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -1277,32 +1277,32 @@ define <16 x i8> @trunc_v16i32_v16i8(ptr %in) nounwind { define void @trunc_v32i32_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v32i32_v32i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #96] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q2, q3, [x0, #32] ; CHECK-NEXT: ldp q4, q5, [x0, #64] ; CHECK-NEXT: ldp q6, q7, [x0] -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h +; CHECK-NEXT: uzp1 z17.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z16.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z19.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z3.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z18.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z2.h, z6.h, z6.h +; CHECK-NEXT: splice z4.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: splice z5.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b -; CHECK-NEXT: uzp1 z3.b, z6.b, z6.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z1.b -; CHECK-NEXT: splice z3.b, p0, z3.b, z0.b -; CHECK-NEXT: add z0.b, z2.b, z2.b -; CHECK-NEXT: add z1.b, z3.b, z3.b +; CHECK-NEXT: uzp1 z3.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z7.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z6.b, z1.b, z1.b +; CHECK-NEXT: splice z0.b, p0, { z2.b, z3.b } +; CHECK-NEXT: splice z1.b, p0, { z6.b, z7.b } +; CHECK-NEXT: add z0.b, z0.b, z0.b +; CHECK-NEXT: add z1.b, z1.b, z1.b ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret ; @@ -1429,56 +1429,56 @@ define void @trunc_v64i32_v64i8(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #160] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q4, q5, [x0, #128] +; CHECK-NEXT: ldp q4, q5, [x0, #96] +; CHECK-NEXT: ldp q6, q7, [x0] +; CHECK-NEXT: uzp1 z17.h, z3.h, z3.h +; CHECK-NEXT: ldp q3, q18, [x0, #128] +; CHECK-NEXT: uzp1 z16.h, z2.h, z2.h +; CHECK-NEXT: ldp q2, q19, [x0, #192] ; CHECK-NEXT: ldp q0, q1, [x0, #64] -; CHECK-NEXT: ldp q6, q7, [x0, #96] -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: ldp q16, q17, [x0] -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: ldp q18, q19, [x0, #192] -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: ldp q20, q21, [x0, #224] -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: ldp q22, q23, [x0, #32] -; CHECK-NEXT: splice z4.h, p0, z4.h, z5.h -; CHECK-NEXT: uzp1 z19.h, z19.h, z19.h -; CHECK-NEXT: uzp1 z18.h, z18.h, z18.h -; CHECK-NEXT: uzp1 z17.h, z17.h, z17.h -; CHECK-NEXT: uzp1 z3.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z5.h, z20.h, z20.h -; CHECK-NEXT: uzp1 z16.h, z16.h, z16.h -; CHECK-NEXT: uzp1 z20.h, z23.h, z23.h -; CHECK-NEXT: uzp1 z21.h, z22.h, z22.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z18.h, p0, z18.h, z19.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h -; CHECK-NEXT: splice z16.h, p0, z16.h, z17.h -; CHECK-NEXT: splice z21.h, p0, z21.h, z20.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b +; CHECK-NEXT: uzp1 z21.h, z18.h, z18.h +; CHECK-NEXT: ldp q18, q22, [x0, #224] +; CHECK-NEXT: uzp1 z20.h, z3.h, z3.h +; CHECK-NEXT: ldp q3, q23, [x0, #32] +; CHECK-NEXT: splice z16.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z27.h, z19.h, z19.h +; CHECK-NEXT: uzp1 z25.h, z22.h, z22.h +; CHECK-NEXT: uzp1 z26.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z24.h, z18.h, z18.h +; CHECK-NEXT: uzp1 z18.h, z23.h, z23.h +; CHECK-NEXT: uzp1 z23.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z17.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z3.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z22.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z2.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z5.h, z1.h, z1.h +; CHECK-NEXT: splice z1.h, p0, { z20.h, z21.h } +; CHECK-NEXT: splice z6.h, p0, { z24.h, z25.h } +; CHECK-NEXT: uzp1 z4.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z26.h, z27.h } +; CHECK-NEXT: splice z7.h, p0, { z17.h, z18.h } +; CHECK-NEXT: uzp1 z17.b, z16.b, z16.b +; CHECK-NEXT: splice z2.h, p0, { z2.h, z3.h } +; CHECK-NEXT: splice z3.h, p0, { z22.h, z23.h } +; CHECK-NEXT: splice z4.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z16.b, z1.b, z1.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z4.b, z18.b, z18.b -; CHECK-NEXT: uzp1 z3.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z7.b, z16.b, z16.b -; CHECK-NEXT: uzp1 z5.b, z21.b, z21.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z1.b -; CHECK-NEXT: uzp1 z1.b, z6.b, z6.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: splice z4.b, p0, z4.b, z3.b -; CHECK-NEXT: splice z7.b, p0, z7.b, z5.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b -; CHECK-NEXT: add z1.b, z2.b, z2.b -; CHECK-NEXT: add z2.b, z4.b, z4.b -; CHECK-NEXT: add z3.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z6.b, z6.b, z6.b +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b +; CHECK-NEXT: uzp1 z1.b, z7.b, z7.b +; CHECK-NEXT: uzp1 z0.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b +; CHECK-NEXT: splice z7.b, p0, { z16.b, z17.b } +; CHECK-NEXT: uzp1 z2.b, z4.b, z4.b +; CHECK-NEXT: splice z4.b, p0, { z5.b, z6.b } +; CHECK-NEXT: splice z0.b, p0, { z0.b, z1.b } +; CHECK-NEXT: splice z1.b, p0, { z2.b, z3.b } +; CHECK-NEXT: add z2.b, z7.b, z7.b +; CHECK-NEXT: add z3.b, z4.b, z4.b ; CHECK-NEXT: add z0.b, z0.b, z0.b -; CHECK-NEXT: stp q1, q2, [x1, #32] -; CHECK-NEXT: stp q3, q0, [x1] +; CHECK-NEXT: add z1.b, z1.b, z1.b +; CHECK-NEXT: stp q2, q3, [x1, #32] +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v64i32_v64i8: @@ -1765,11 +1765,11 @@ define void @trunc_v64i32_v64i8(ptr %in, ptr %out) nounwind { define <8 x i16> @trunc_v8i32_v8i16(ptr %in) nounwind { ; CHECK-LABEL: trunc_v8i32_v8i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z3.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z1.h, z1.h +; CHECK-NEXT: splice z0.h, p0, { z2.h, z3.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -1801,18 +1801,18 @@ define <8 x i16> @trunc_v8i32_v8i16(ptr %in) nounwind { define void @trunc_v16i32_v16i16(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v16i32_v16i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: add z0.h, z0.h, z0.h +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z0.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p0, { z4.h, z5.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: add z1.h, z2.h, z2.h -; CHECK-NEXT: stp q1, q0, [x1] +; CHECK-NEXT: add z0.h, z0.h, z0.h +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v16i32_v16i16: @@ -1877,27 +1877,27 @@ define void @trunc_v16i32_v16i16(ptr %in, ptr %out) nounwind { define void @trunc_v32i32_v32i16(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v32i32_v32i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #64] +; CHECK-NEXT: ldp q1, q0, [x0, #64] ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: ldp q6, q7, [x0, #32] -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h +; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: uzp1 z7.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z6.h, z1.h, z1.h +; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: uzp1 z17.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z16.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z6.h, z7.h } +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: splice z1.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z2.h, p0, { z2.h, z3.h } +; CHECK-NEXT: splice z3.h, p0, { z4.h, z5.h } ; CHECK-NEXT: add z0.h, z0.h, z0.h +; CHECK-NEXT: add z1.h, z1.h, z1.h ; CHECK-NEXT: add z2.h, z2.h, z2.h -; CHECK-NEXT: add z1.h, z4.h, z4.h -; CHECK-NEXT: add z3.h, z6.h, z6.h +; CHECK-NEXT: add z3.h, z3.h, z3.h ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret @@ -2027,49 +2027,49 @@ define void @trunc_v64i32_v64i16(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #192] ; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: ldp q4, q5, [x0] ; CHECK-NEXT: ldp q6, q7, [x0, #64] -; CHECK-NEXT: ldp q16, q17, [x0, #224] -; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h -; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h -; CHECK-NEXT: ldp q20, q21, [x0, #160] -; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z17.h, z3.h, z3.h +; CHECK-NEXT: ldp q3, q18, [x0, #224] +; CHECK-NEXT: uzp1 z16.h, z2.h, z2.h +; CHECK-NEXT: ldp q2, q19, [x0, #128] ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: uzp1 z17.h, z17.h, z17.h -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: uzp1 z16.h, z16.h, z16.h -; CHECK-NEXT: ldp q18, q19, [x0, #128] -; CHECK-NEXT: splice z2.h, p0, z2.h, z3.h -; CHECK-NEXT: uzp1 z3.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z20.h, z20.h, z20.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: ldp q21, q22, [x0] -; CHECK-NEXT: splice z16.h, p0, z16.h, z17.h +; CHECK-NEXT: uzp1 z21.h, z18.h, z18.h +; CHECK-NEXT: ldp q18, q22, [x0, #160] +; CHECK-NEXT: uzp1 z20.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z24.h, z19.h, z19.h +; CHECK-NEXT: ldp q3, q19, [x0, #96] +; CHECK-NEXT: uzp1 z23.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z26.h, z22.h, z22.h +; CHECK-NEXT: splice z2.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z17.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z25.h, z18.h, z18.h +; CHECK-NEXT: splice z7.h, p0, { z20.h, z21.h } +; CHECK-NEXT: uzp1 z21.h, z5.h, z5.h ; CHECK-NEXT: uzp1 z19.h, z19.h, z19.h -; CHECK-NEXT: uzp1 z18.h, z18.h, z18.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: splice z20.h, p0, z20.h, z3.h -; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: uzp1 z5.h, z22.h, z22.h -; CHECK-NEXT: uzp1 z7.h, z21.h, z21.h -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z18.h, p0, z18.h, z19.h -; CHECK-NEXT: add z2.h, z2.h, z2.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z3.h -; CHECK-NEXT: add z3.h, z16.h, z16.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: add z1.h, z20.h, z20.h -; CHECK-NEXT: add z5.h, z18.h, z18.h -; CHECK-NEXT: stp q2, q3, [x1, #96] -; CHECK-NEXT: add z2.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z20.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z5.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z16.h, z6.h, z6.h +; CHECK-NEXT: splice z6.h, p0, { z23.h, z24.h } +; CHECK-NEXT: uzp1 z18.h, z3.h, z3.h +; CHECK-NEXT: splice z3.h, p0, { z25.h, z26.h } +; CHECK-NEXT: uzp1 z4.h, z0.h, z0.h +; CHECK-NEXT: add z0.h, z2.h, z2.h +; CHECK-NEXT: add z7.h, z7.h, z7.h +; CHECK-NEXT: splice z1.h, p0, { z16.h, z17.h } +; CHECK-NEXT: splice z2.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z16.h, p0, { z20.h, z21.h } +; CHECK-NEXT: splice z4.h, p0, { z4.h, z5.h } +; CHECK-NEXT: add z6.h, z6.h, z6.h +; CHECK-NEXT: add z3.h, z3.h, z3.h +; CHECK-NEXT: stp q0, q7, [x1, #96] +; CHECK-NEXT: add z0.h, z1.h, z1.h +; CHECK-NEXT: add z1.h, z2.h, z2.h +; CHECK-NEXT: add z2.h, z16.h, z16.h +; CHECK-NEXT: stp q6, q3, [x1, #64] ; CHECK-NEXT: add z3.h, z4.h, z4.h -; CHECK-NEXT: add z4.h, z7.h, z7.h -; CHECK-NEXT: add z0.h, z0.h, z0.h -; CHECK-NEXT: stp q5, q1, [x1, #64] -; CHECK-NEXT: stp q2, q3, [x1, #32] -; CHECK-NEXT: stp q4, q0, [x1] +; CHECK-NEXT: stp q0, q1, [x1, #32] +; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v64i32_v64i16: @@ -2360,11 +2360,11 @@ define void @trunc_v64i32_v64i16(ptr %in, ptr %out) nounwind { define <4 x i8> @trunc_v4i64_v4i8(ptr %in) nounwind { ; CHECK-LABEL: trunc_v4i64_v4i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: uzp1 z3.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z2.s, z1.s, z1.s +; CHECK-NEXT: splice z0.s, p0, { z2.s, z3.s } ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -2392,18 +2392,18 @@ define <8 x i8> @trunc_v8i64_v8i8(ptr %in) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: splice z1.s, p0, z1.s, z0.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z4.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z1.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z0.s, z3.s, z3.s +; CHECK-NEXT: splice z2.s, p0, { z4.s, z5.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z0.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h -; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z1.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } +; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; @@ -2439,34 +2439,34 @@ define <8 x i8> @trunc_v8i64_v8i8(ptr %in) nounwind { define <16 x i8> @trunc_v16i64_v16i8(ptr %in) nounwind { ; CHECK-LABEL: trunc_v16i64_v16i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #96] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q2, q3, [x0, #32] ; CHECK-NEXT: ldp q4, q5, [x0, #64] ; CHECK-NEXT: ldp q6, q7, [x0] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s +; CHECK-NEXT: uzp1 z17.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z16.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z19.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z1.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z18.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z0.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z3.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z2.s, z6.s, z6.s +; CHECK-NEXT: splice z4.s, p0, { z16.s, z17.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } +; CHECK-NEXT: splice z1.s, p0, { z18.s, z19.s } +; CHECK-NEXT: splice z2.s, p0, { z2.s, z3.s } ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z3.h, z6.h, z6.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z1.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z0.h +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p0, { z3.h, z4.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z0.b, z3.b, z3.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z1.b, z0.b, z0.b +; CHECK-NEXT: splice z0.b, p0, { z1.b, z2.b } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -2523,62 +2523,62 @@ define <16 x i8> @trunc_v16i64_v16i8(ptr %in) nounwind { define void @trunc_v32i64_v32i8(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v32i64_v32i8: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q5, q6, [x0, #224] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0, #224] -; CHECK-NEXT: ldp q4, q5, [x0, #32] -; CHECK-NEXT: ldp q6, q7, [x0, #64] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: ldp q16, q17, [x0, #192] -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: ldp q18, q19, [x0, #128] -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: ldp q20, q21, [x0, #160] -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: ldp q22, q23, [x0, #96] -; CHECK-NEXT: uzp1 z17.s, z17.s, z17.s -; CHECK-NEXT: uzp1 z16.s, z16.s, z16.s -; CHECK-NEXT: uzp1 z19.s, z19.s, z19.s -; CHECK-NEXT: uzp1 z18.s, z18.s, z18.s -; CHECK-NEXT: uzp1 z21.s, z21.s, z21.s -; CHECK-NEXT: uzp1 z20.s, z20.s, z20.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: uzp1 z23.s, z23.s, z23.s -; CHECK-NEXT: uzp1 z22.s, z22.s, z22.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: splice z16.s, p0, z16.s, z17.s -; CHECK-NEXT: splice z20.s, p0, z20.s, z21.s -; CHECK-NEXT: splice z18.s, p0, z18.s, z19.s -; CHECK-NEXT: splice z22.s, p0, z22.s, z23.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: ldp q2, q3, [x0, #32] +; CHECK-NEXT: ldp q4, q7, [x0, #64] +; CHECK-NEXT: uzp1 z17.s, z6.s, z6.s +; CHECK-NEXT: ldp q6, q18, [x0, #192] +; CHECK-NEXT: uzp1 z16.s, z5.s, z5.s +; CHECK-NEXT: ldp q5, q19, [x0, #128] +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: uzp1 z21.s, z18.s, z18.s +; CHECK-NEXT: ldp q18, q22, [x0, #160] +; CHECK-NEXT: uzp1 z20.s, z6.s, z6.s +; CHECK-NEXT: ldp q6, q23, [x0, #96] +; CHECK-NEXT: splice z16.s, p0, { z16.s, z17.s } +; CHECK-NEXT: uzp1 z27.s, z19.s, z19.s +; CHECK-NEXT: uzp1 z25.s, z22.s, z22.s +; CHECK-NEXT: uzp1 z26.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z24.s, z18.s, z18.s +; CHECK-NEXT: uzp1 z18.s, z23.s, z23.s +; CHECK-NEXT: uzp1 z23.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z17.s, z6.s, z6.s +; CHECK-NEXT: uzp1 z6.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z22.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z5.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z2.s, z1.s, z1.s +; CHECK-NEXT: splice z3.s, p0, { z20.s, z21.s } +; CHECK-NEXT: uzp1 z1.s, z0.s, z0.s +; CHECK-NEXT: splice z0.s, p0, { z24.s, z25.s } +; CHECK-NEXT: splice z7.s, p0, { z26.s, z27.s } +; CHECK-NEXT: splice z4.s, p0, { z17.s, z18.s } +; CHECK-NEXT: uzp1 z17.h, z16.h, z16.h +; CHECK-NEXT: splice z5.s, p0, { z5.s, z6.s } +; CHECK-NEXT: splice z6.s, p0, { z22.s, z23.s } +; CHECK-NEXT: splice z1.s, p0, { z1.s, z2.s } +; CHECK-NEXT: uzp1 z16.h, z3.h, z3.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z2.h, z16.h, z16.h -; CHECK-NEXT: uzp1 z3.h, z20.h, z20.h -; CHECK-NEXT: uzp1 z5.h, z18.h, z18.h -; CHECK-NEXT: uzp1 z7.h, z22.h, z22.h -; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z1.h -; CHECK-NEXT: splice z5.h, p0, z5.h, z3.h -; CHECK-NEXT: splice z6.h, p0, z6.h, z7.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z19.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z2.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z18.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z5.h, z6.h, z6.h +; CHECK-NEXT: splice z0.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z4.h, z1.h, z1.h +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } +; CHECK-NEXT: splice z2.h, p0, { z18.h, z19.h } +; CHECK-NEXT: splice z3.h, p0, { z4.h, z5.h } +; CHECK-NEXT: uzp1 z5.b, z0.b, z0.b ; CHECK-NEXT: ptrue p0.b, vl8 -; CHECK-NEXT: uzp1 z1.b, z2.b, z2.b -; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b -; CHECK-NEXT: uzp1 z3.b, z6.b, z6.b -; CHECK-NEXT: uzp1 z0.b, z0.b, z0.b -; CHECK-NEXT: splice z2.b, p0, z2.b, z1.b -; CHECK-NEXT: splice z0.b, p0, z0.b, z3.b -; CHECK-NEXT: add z1.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z4.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z7.b, z2.b, z2.b +; CHECK-NEXT: uzp1 z6.b, z3.b, z3.b +; CHECK-NEXT: splice z0.b, p0, { z4.b, z5.b } +; CHECK-NEXT: splice z1.b, p0, { z6.b, z7.b } ; CHECK-NEXT: add z0.b, z0.b, z0.b -; CHECK-NEXT: stp q0, q1, [x1] +; CHECK-NEXT: add z1.b, z1.b, z1.b +; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v32i64_v32i8: @@ -2731,11 +2731,11 @@ define void @trunc_v32i64_v32i8(ptr %in, ptr %out) nounwind { define <4 x i16> @trunc_v4i64_v4i16(ptr %in) nounwind { ; CHECK-LABEL: trunc_v4i64_v4i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: uzp1 z3.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z2.s, z1.s, z1.s +; CHECK-NEXT: splice z0.s, p0, { z2.s, z3.s } ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret @@ -2763,17 +2763,17 @@ define <8 x i16> @trunc_v8i64_v8i16(ptr %in) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: splice z1.s, p0, z1.s, z0.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z4.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z1.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z0.s, z3.s, z3.s +; CHECK-NEXT: splice z2.s, p0, { z4.s, z5.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h -; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h +; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z1.h, z0.h, z0.h +; CHECK-NEXT: splice z0.h, p0, { z1.h, z2.h } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -2810,32 +2810,32 @@ define <8 x i16> @trunc_v8i64_v8i16(ptr %in) nounwind { define void @trunc_v16i64_v16i16(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v16i64_v16i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q0, q1, [x0, #96] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q2, q3, [x0, #32] ; CHECK-NEXT: ldp q4, q5, [x0, #64] ; CHECK-NEXT: ldp q6, q7, [x0] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s +; CHECK-NEXT: uzp1 z17.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z16.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z1.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z19.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z0.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z3.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z18.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z2.s, z6.s, z6.s +; CHECK-NEXT: splice z4.s, p0, { z16.s, z17.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } +; CHECK-NEXT: splice z5.s, p0, { z18.s, z19.s } +; CHECK-NEXT: splice z1.s, p0, { z2.s, z3.s } ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h -; CHECK-NEXT: uzp1 z3.h, z6.h, z6.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z1.h -; CHECK-NEXT: splice z3.h, p0, z3.h, z0.h -; CHECK-NEXT: add z0.h, z2.h, z2.h -; CHECK-NEXT: add z1.h, z3.h, z3.h +; CHECK-NEXT: uzp1 z3.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z7.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z6.h, z1.h, z1.h +; CHECK-NEXT: splice z0.h, p0, { z2.h, z3.h } +; CHECK-NEXT: splice z1.h, p0, { z6.h, z7.h } +; CHECK-NEXT: add z0.h, z0.h, z0.h +; CHECK-NEXT: add z1.h, z1.h, z1.h ; CHECK-NEXT: stp q1, q0, [x1] ; CHECK-NEXT: ret ; @@ -2915,56 +2915,56 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #160] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q4, q5, [x0, #128] +; CHECK-NEXT: ldp q4, q5, [x0, #96] +; CHECK-NEXT: ldp q6, q7, [x0] +; CHECK-NEXT: uzp1 z17.s, z3.s, z3.s +; CHECK-NEXT: ldp q3, q18, [x0, #128] +; CHECK-NEXT: uzp1 z16.s, z2.s, z2.s +; CHECK-NEXT: ldp q2, q19, [x0, #192] ; CHECK-NEXT: ldp q0, q1, [x0, #64] -; CHECK-NEXT: ldp q6, q7, [x0, #96] -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: ldp q16, q17, [x0] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: ldp q18, q19, [x0, #192] -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: ldp q20, q21, [x0, #224] -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: ldp q22, q23, [x0, #32] -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: uzp1 z19.s, z19.s, z19.s -; CHECK-NEXT: uzp1 z18.s, z18.s, z18.s -; CHECK-NEXT: uzp1 z17.s, z17.s, z17.s -; CHECK-NEXT: uzp1 z3.s, z21.s, z21.s -; CHECK-NEXT: uzp1 z5.s, z20.s, z20.s -; CHECK-NEXT: uzp1 z16.s, z16.s, z16.s -; CHECK-NEXT: uzp1 z20.s, z23.s, z23.s -; CHECK-NEXT: uzp1 z21.s, z22.s, z22.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z18.s, p0, z18.s, z19.s -; CHECK-NEXT: splice z5.s, p0, z5.s, z3.s -; CHECK-NEXT: splice z16.s, p0, z16.s, z17.s -; CHECK-NEXT: splice z21.s, p0, z21.s, z20.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: uzp1 z1.h, z2.h, z2.h -; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z21.s, z18.s, z18.s +; CHECK-NEXT: ldp q18, q22, [x0, #224] +; CHECK-NEXT: uzp1 z20.s, z3.s, z3.s +; CHECK-NEXT: ldp q3, q23, [x0, #32] +; CHECK-NEXT: splice z16.s, p0, { z16.s, z17.s } +; CHECK-NEXT: uzp1 z27.s, z19.s, z19.s +; CHECK-NEXT: uzp1 z25.s, z22.s, z22.s +; CHECK-NEXT: uzp1 z26.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z24.s, z18.s, z18.s +; CHECK-NEXT: uzp1 z18.s, z23.s, z23.s +; CHECK-NEXT: uzp1 z23.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z17.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z3.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z22.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z2.s, z6.s, z6.s +; CHECK-NEXT: uzp1 z5.s, z1.s, z1.s +; CHECK-NEXT: splice z1.s, p0, { z20.s, z21.s } +; CHECK-NEXT: splice z6.s, p0, { z24.s, z25.s } +; CHECK-NEXT: uzp1 z4.s, z0.s, z0.s +; CHECK-NEXT: splice z0.s, p0, { z26.s, z27.s } +; CHECK-NEXT: splice z7.s, p0, { z17.s, z18.s } +; CHECK-NEXT: uzp1 z17.h, z16.h, z16.h +; CHECK-NEXT: splice z2.s, p0, { z2.s, z3.s } +; CHECK-NEXT: splice z3.s, p0, { z22.s, z23.s } +; CHECK-NEXT: splice z4.s, p0, { z4.s, z5.s } +; CHECK-NEXT: uzp1 z16.h, z1.h, z1.h ; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: uzp1 z4.h, z18.h, z18.h -; CHECK-NEXT: uzp1 z3.h, z5.h, z5.h -; CHECK-NEXT: uzp1 z7.h, z16.h, z16.h -; CHECK-NEXT: uzp1 z5.h, z21.h, z21.h -; CHECK-NEXT: splice z2.h, p0, z2.h, z1.h -; CHECK-NEXT: uzp1 z1.h, z6.h, z6.h -; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h -; CHECK-NEXT: splice z4.h, p0, z4.h, z3.h -; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h -; CHECK-NEXT: splice z0.h, p0, z0.h, z1.h -; CHECK-NEXT: add z1.h, z2.h, z2.h -; CHECK-NEXT: add z2.h, z4.h, z4.h -; CHECK-NEXT: add z3.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h +; CHECK-NEXT: uzp1 z5.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z1.h, z7.h, z7.h +; CHECK-NEXT: uzp1 z0.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h +; CHECK-NEXT: splice z7.h, p0, { z16.h, z17.h } +; CHECK-NEXT: uzp1 z2.h, z4.h, z4.h +; CHECK-NEXT: splice z4.h, p0, { z5.h, z6.h } +; CHECK-NEXT: splice z0.h, p0, { z0.h, z1.h } +; CHECK-NEXT: splice z1.h, p0, { z2.h, z3.h } +; CHECK-NEXT: add z2.h, z7.h, z7.h +; CHECK-NEXT: add z3.h, z4.h, z4.h ; CHECK-NEXT: add z0.h, z0.h, z0.h -; CHECK-NEXT: stp q1, q2, [x1, #32] -; CHECK-NEXT: stp q3, q0, [x1] +; CHECK-NEXT: add z1.h, z1.h, z1.h +; CHECK-NEXT: stp q2, q3, [x1, #32] +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v32i64_v32i16: @@ -3118,11 +3118,11 @@ define void @trunc_v32i64_v32i16(ptr %in, ptr %out) nounwind { define <4 x i32> @trunc_v4i64_v4i32(ptr %in) nounwind { ; CHECK-LABEL: trunc_v4i64_v4i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ldp q1, q0, [x0] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: uzp1 z3.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z2.s, z1.s, z1.s +; CHECK-NEXT: splice z0.s, p0, { z2.s, z3.s } ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; @@ -3146,18 +3146,18 @@ define <4 x i32> @trunc_v4i64_v4i32(ptr %in) nounwind { define void @trunc_v8i64_v8i32(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v8i64_v8i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: ldp q1, q0, [x0, #32] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: add z0.s, z0.s, z0.s +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: uzp1 z5.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z4.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z1.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z0.s, z3.s, z3.s +; CHECK-NEXT: splice z2.s, p0, { z4.s, z5.s } +; CHECK-NEXT: splice z0.s, p0, { z0.s, z1.s } ; CHECK-NEXT: add z1.s, z2.s, z2.s -; CHECK-NEXT: stp q1, q0, [x1] +; CHECK-NEXT: add z0.s, z0.s, z0.s +; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v8i64_v8i32: @@ -3202,27 +3202,27 @@ define void @trunc_v8i64_v8i32(ptr %in, ptr %out) nounwind { define void @trunc_v16i64_v16i32(ptr %in, ptr %out) nounwind { ; CHECK-LABEL: trunc_v16i64_v16i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ldp q0, q1, [x0, #64] +; CHECK-NEXT: ldp q1, q0, [x0, #64] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: ldp q2, q3, [x0] -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: ldp q6, q7, [x0, #32] -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z5.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s +; CHECK-NEXT: ldp q2, q3, [x0, #96] +; CHECK-NEXT: ldp q4, q5, [x0] +; CHECK-NEXT: uzp1 z7.s, z0.s, z0.s +; CHECK-NEXT: uzp1 z6.s, z1.s, z1.s +; CHECK-NEXT: ldp q1, q0, [x0, #32] +; CHECK-NEXT: uzp1 z17.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z16.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z3.s, z5.s, z5.s +; CHECK-NEXT: uzp1 z2.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z5.s, z0.s, z0.s +; CHECK-NEXT: splice z0.s, p0, { z6.s, z7.s } +; CHECK-NEXT: uzp1 z4.s, z1.s, z1.s +; CHECK-NEXT: splice z1.s, p0, { z16.s, z17.s } +; CHECK-NEXT: splice z2.s, p0, { z2.s, z3.s } +; CHECK-NEXT: splice z3.s, p0, { z4.s, z5.s } ; CHECK-NEXT: add z0.s, z0.s, z0.s +; CHECK-NEXT: add z1.s, z1.s, z1.s ; CHECK-NEXT: add z2.s, z2.s, z2.s -; CHECK-NEXT: add z1.s, z4.s, z4.s -; CHECK-NEXT: add z3.s, z6.s, z6.s +; CHECK-NEXT: add z3.s, z3.s, z3.s ; CHECK-NEXT: stp q0, q1, [x1, #32] ; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret @@ -3297,49 +3297,49 @@ define void @trunc_v32i64_v32i32(ptr %in, ptr %out) nounwind { ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q2, q3, [x0, #192] ; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: ldp q4, q5, [x0] ; CHECK-NEXT: ldp q6, q7, [x0, #64] -; CHECK-NEXT: ldp q16, q17, [x0, #224] -; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s -; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s -; CHECK-NEXT: ldp q20, q21, [x0, #160] -; CHECK-NEXT: uzp1 z7.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z17.s, z3.s, z3.s +; CHECK-NEXT: ldp q3, q18, [x0, #224] +; CHECK-NEXT: uzp1 z16.s, z2.s, z2.s +; CHECK-NEXT: ldp q2, q19, [x0, #128] ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: uzp1 z17.s, z17.s, z17.s -; CHECK-NEXT: ldp q4, q5, [x0, #96] -; CHECK-NEXT: uzp1 z16.s, z16.s, z16.s -; CHECK-NEXT: ldp q18, q19, [x0, #128] -; CHECK-NEXT: splice z2.s, p0, z2.s, z3.s -; CHECK-NEXT: uzp1 z3.s, z21.s, z21.s -; CHECK-NEXT: uzp1 z20.s, z20.s, z20.s -; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s -; CHECK-NEXT: ldp q21, q22, [x0] -; CHECK-NEXT: splice z16.s, p0, z16.s, z17.s +; CHECK-NEXT: uzp1 z21.s, z18.s, z18.s +; CHECK-NEXT: ldp q18, q22, [x0, #160] +; CHECK-NEXT: uzp1 z20.s, z3.s, z3.s +; CHECK-NEXT: uzp1 z24.s, z19.s, z19.s +; CHECK-NEXT: ldp q3, q19, [x0, #96] +; CHECK-NEXT: uzp1 z23.s, z2.s, z2.s +; CHECK-NEXT: uzp1 z26.s, z22.s, z22.s +; CHECK-NEXT: splice z2.s, p0, { z16.s, z17.s } +; CHECK-NEXT: uzp1 z17.s, z7.s, z7.s +; CHECK-NEXT: uzp1 z25.s, z18.s, z18.s +; CHECK-NEXT: splice z7.s, p0, { z20.s, z21.s } +; CHECK-NEXT: uzp1 z21.s, z5.s, z5.s ; CHECK-NEXT: uzp1 z19.s, z19.s, z19.s -; CHECK-NEXT: uzp1 z18.s, z18.s, z18.s -; CHECK-NEXT: uzp1 z4.s, z4.s, z4.s -; CHECK-NEXT: splice z20.s, p0, z20.s, z3.s -; CHECK-NEXT: uzp1 z3.s, z5.s, z5.s -; CHECK-NEXT: splice z6.s, p0, z6.s, z7.s -; CHECK-NEXT: uzp1 z5.s, z22.s, z22.s -; CHECK-NEXT: uzp1 z7.s, z21.s, z21.s -; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s -; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s -; CHECK-NEXT: splice z18.s, p0, z18.s, z19.s -; CHECK-NEXT: add z2.s, z2.s, z2.s -; CHECK-NEXT: splice z4.s, p0, z4.s, z3.s -; CHECK-NEXT: add z3.s, z16.s, z16.s -; CHECK-NEXT: splice z7.s, p0, z7.s, z5.s -; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s -; CHECK-NEXT: add z1.s, z20.s, z20.s -; CHECK-NEXT: add z5.s, z18.s, z18.s -; CHECK-NEXT: stp q2, q3, [x1, #96] -; CHECK-NEXT: add z2.s, z6.s, z6.s +; CHECK-NEXT: uzp1 z20.s, z4.s, z4.s +; CHECK-NEXT: uzp1 z5.s, z1.s, z1.s +; CHECK-NEXT: uzp1 z16.s, z6.s, z6.s +; CHECK-NEXT: splice z6.s, p0, { z23.s, z24.s } +; CHECK-NEXT: uzp1 z18.s, z3.s, z3.s +; CHECK-NEXT: splice z3.s, p0, { z25.s, z26.s } +; CHECK-NEXT: uzp1 z4.s, z0.s, z0.s +; CHECK-NEXT: add z0.s, z2.s, z2.s +; CHECK-NEXT: add z7.s, z7.s, z7.s +; CHECK-NEXT: splice z1.s, p0, { z16.s, z17.s } +; CHECK-NEXT: splice z2.s, p0, { z18.s, z19.s } +; CHECK-NEXT: splice z16.s, p0, { z20.s, z21.s } +; CHECK-NEXT: splice z4.s, p0, { z4.s, z5.s } +; CHECK-NEXT: add z6.s, z6.s, z6.s +; CHECK-NEXT: add z3.s, z3.s, z3.s +; CHECK-NEXT: stp q0, q7, [x1, #96] +; CHECK-NEXT: add z0.s, z1.s, z1.s +; CHECK-NEXT: add z1.s, z2.s, z2.s +; CHECK-NEXT: add z2.s, z16.s, z16.s +; CHECK-NEXT: stp q6, q3, [x1, #64] ; CHECK-NEXT: add z3.s, z4.s, z4.s -; CHECK-NEXT: add z4.s, z7.s, z7.s -; CHECK-NEXT: add z0.s, z0.s, z0.s -; CHECK-NEXT: stp q5, q1, [x1, #64] -; CHECK-NEXT: stp q2, q3, [x1, #32] -; CHECK-NEXT: stp q4, q0, [x1] +; CHECK-NEXT: stp q0, q1, [x1, #32] +; CHECK-NEXT: stp q2, q3, [x1] ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: trunc_v32i64_v32i32: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll index 3438cbdd476d85976b45f153d2b55300f981d706..4b0ff1b2eb470468b4078b3acb4a3ad58164dae8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-cs-chain.ll @@ -24,9 +24,12 @@ define amdgpu_cs_chain void @chain_call(<3 x i32> inreg %sgpr, { i32, ptr addrsp ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX11-NEXT: [[GV1:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @callee ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>) - ; GFX11-NEXT: $sgpr0 = COPY [[UV]](s32) - ; GFX11-NEXT: $sgpr1 = COPY [[UV1]](s32) - ; GFX11-NEXT: $sgpr2 = COPY [[UV2]](s32) + ; GFX11-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; GFX11-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; GFX11-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; GFX11-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) + ; GFX11-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32) + ; GFX11-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32) ; GFX11-NEXT: $vgpr8 = COPY [[COPY3]](s32) ; GFX11-NEXT: $vgpr9 = COPY [[COPY4]](p5) ; GFX11-NEXT: $vgpr10 = COPY [[COPY5]](s32) @@ -50,9 +53,12 @@ define amdgpu_cs_chain void @chain_call(<3 x i32> inreg %sgpr, { i32, ptr addrsp ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX10-NEXT: [[GV1:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @callee ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>) - ; GFX10-NEXT: $sgpr0 = COPY [[UV]](s32) - ; GFX10-NEXT: $sgpr1 = COPY [[UV1]](s32) - ; GFX10-NEXT: $sgpr2 = COPY [[UV2]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; GFX10-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; GFX10-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32) + ; GFX10-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32) ; GFX10-NEXT: $vgpr8 = COPY [[COPY3]](s32) ; GFX10-NEXT: $vgpr9 = COPY [[COPY4]](p5) ; GFX10-NEXT: $vgpr10 = COPY [[COPY5]](s32) @@ -82,9 +88,12 @@ define amdgpu_cs_chain void @chain_preserve_call(<3 x i32> inreg %sgpr, { i32, p ; GFX11-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX11-NEXT: [[GV1:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @callee_preserve ; GFX11-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>) - ; GFX11-NEXT: $sgpr0 = COPY [[UV]](s32) - ; GFX11-NEXT: $sgpr1 = COPY [[UV1]](s32) - ; GFX11-NEXT: $sgpr2 = COPY [[UV2]](s32) + ; GFX11-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; GFX11-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; GFX11-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; GFX11-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) + ; GFX11-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32) + ; GFX11-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32) ; GFX11-NEXT: $vgpr8 = COPY [[COPY3]](s32) ; GFX11-NEXT: $vgpr9 = COPY [[COPY4]](p5) ; GFX11-NEXT: $vgpr10 = COPY [[COPY5]](s32) @@ -108,9 +117,12 @@ define amdgpu_cs_chain void @chain_preserve_call(<3 x i32> inreg %sgpr, { i32, p ; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX10-NEXT: [[GV1:%[0-9]+]]:ccr_sgpr_64(p0) = G_GLOBAL_VALUE @callee_preserve ; GFX10-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<3 x s32>) - ; GFX10-NEXT: $sgpr0 = COPY [[UV]](s32) - ; GFX10-NEXT: $sgpr1 = COPY [[UV1]](s32) - ; GFX10-NEXT: $sgpr2 = COPY [[UV2]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; GFX10-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; GFX10-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) + ; GFX10-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32) + ; GFX10-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32) ; GFX10-NEXT: $vgpr8 = COPY [[COPY3]](s32) ; GFX10-NEXT: $vgpr9 = COPY [[COPY4]](p5) ; GFX10-NEXT: $vgpr10 = COPY [[COPY5]](s32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll index 5effd24a752088d696d4849ea90e6847419b05c0..adad38de380d7d10a132459e624152fd3014556c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-non-fixed.ll @@ -50,7 +50,8 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_i32_imm_inreg(i32 inreg ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_i32_inreg - ; CHECK-NEXT: $sgpr4 = COPY [[C]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[C]](s32) + ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>) ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_i32_inreg, csr_amdgpu_si_gfx, implicit $sgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3 @@ -99,8 +100,10 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() # ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8) ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16) - ; CHECK-NEXT: $sgpr4 = COPY [[ANYEXT1]](s32) - ; CHECK-NEXT: $sgpr5 = COPY [[LOAD2]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT1]](s32) + ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[LOAD2]](s32) + ; CHECK-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>) ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32_inreg, csr_amdgpu_si_gfx, implicit $sgpr4, implicit $sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll index c3694158e7b971e04e410374bc80d4258a6cdc7d..96c3575e3190c03fd73180b3ce128f5b111209af 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll @@ -942,7 +942,8 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_i32_imm_inreg(i32 inreg ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_i32_inreg - ; CHECK-NEXT: $sgpr4 = COPY [[C]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[C]](s32) + ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY1]](<4 x s32>) ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_i32_inreg, csr_amdgpu_si_gfx, implicit $sgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3 @@ -3984,8 +3985,10 @@ define amdgpu_gfx void @test_gfx_call_external_void_func_struct_i8_i32_inreg() # ; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @external_gfx_void_func_struct_i8_i32_inreg ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[LOAD1]](s8) ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[ANYEXT]](s16) - ; CHECK-NEXT: $sgpr4 = COPY [[ANYEXT1]](s32) - ; CHECK-NEXT: $sgpr5 = COPY [[LOAD2]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT1]](s32) + ; CHECK-NEXT: $sgpr4 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[LOAD2]](s32) + ; CHECK-NEXT: $sgpr5 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY]](<4 x s32>) ; CHECK-NEXT: $sgpr30_sgpr31 = noconvergent G_SI_CALL [[GV]](p0), @external_gfx_void_func_struct_i8_i32_inreg, csr_amdgpu_si_gfx, implicit $sgpr4, implicit $sgpr5, implicit $sgpr0_sgpr1_sgpr2_sgpr3 @@ -5309,7 +5312,8 @@ define void @test_call_external_void_func_i16_inreg(i16 inreg %arg) #0 { ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) - ; CHECK-NEXT: $sgpr0 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4) @@ -5354,7 +5358,8 @@ define void @test_call_external_void_func_i32_inreg(i32 inreg %arg) #0 { ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]] ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK-NEXT: $sgpr0 = COPY [[COPY9]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4) @@ -5402,8 +5407,10 @@ define void @test_call_external_void_func_i64_inreg(i64 inreg %arg) #0 { ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) - ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32) - ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4) @@ -5451,8 +5458,10 @@ define void @test_call_external_void_func_v2i32_inreg(<2 x i32> inreg %arg) #0 { ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x s32>) - ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32) - ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4) @@ -5499,7 +5508,8 @@ define void @test_call_external_void_func_f16_inreg(half inreg %arg) #0 { ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) - ; CHECK-NEXT: $sgpr0 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4) @@ -5546,7 +5556,8 @@ define void @test_call_external_void_func_bf16_inreg(bfloat inreg %arg) #0 { ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16) - ; CHECK-NEXT: $sgpr0 = COPY [[ANYEXT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[ANYEXT]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4) @@ -5591,7 +5602,8 @@ define void @test_call_external_void_func_f32_inreg(float inreg %arg) #0 { ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]] ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK-NEXT: $sgpr0 = COPY [[COPY9]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY9]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4) @@ -5639,8 +5651,10 @@ define void @test_call_external_void_func_f64_inreg(double inreg %arg) #0 { ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64) - ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32) - ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4) @@ -5685,7 +5699,9 @@ define void @test_call_external_void_func_v2f16_inreg(<2 x half> inreg %arg) #0 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]] ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK-NEXT: $sgpr0 = COPY [[COPY9]](<2 x s16>) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY9]](<2 x s16>) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4) @@ -5738,8 +5754,12 @@ define void @test_call_external_void_func_v3f16_inreg(<3 x half> inreg %arg) #0 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV4]](s16), [[UV5]](s16), [[UV6]](s16), [[DEF]](s16) ; CHECK-NEXT: [[UV7:%[0-9]+]]:_(<2 x s16>), [[UV8:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s16>) - ; CHECK-NEXT: $sgpr0 = COPY [[UV7]](<2 x s16>) - ; CHECK-NEXT: $sgpr1 = COPY [[UV8]](<2 x s16>) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV7]](<2 x s16>) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV8]](<2 x s16>) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4) @@ -5787,8 +5807,12 @@ define void @test_call_external_void_func_v4f16_inreg(<4 x half> inreg %arg) #0 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS]](<4 x s16>) - ; CHECK-NEXT: $sgpr0 = COPY [[UV]](<2 x s16>) - ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](<2 x s16>) + ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[BITCAST1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4) @@ -5836,8 +5860,10 @@ define void @test_call_external_void_func_p0_inreg(ptr inreg %arg) #0 { ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p0) - ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32) - ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4) @@ -5885,8 +5911,10 @@ define void @test_call_external_void_func_p1_inreg(ptr addrspace(1) inreg %arg) ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](p1) - ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32) - ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4) @@ -5931,7 +5959,9 @@ define void @test_call_external_void_func_p3_inreg(ptr addrspace(3) inreg %arg) ; CHECK-NEXT: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY2]] ; CHECK-NEXT: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) - ; CHECK-NEXT: $sgpr0 = COPY [[COPY9]](p3) + ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY9]](p3) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY10]](p4) @@ -5983,10 +6013,14 @@ define void @test_call_external_void_func_v2p1_inreg(<2 x ptr addrspace(1)> inre ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x p1>) - ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32) - ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32) - ; CHECK-NEXT: $sgpr2 = COPY [[UV2]](s32) - ; CHECK-NEXT: $sgpr3 = COPY [[UV3]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT2:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV2]](s32) + ; CHECK-NEXT: $sgpr2 = COPY [[INTRINSIC_CONVERGENT2]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT3:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV3]](s32) + ; CHECK-NEXT: $sgpr3 = COPY [[INTRINSIC_CONVERGENT3]](s32) ; CHECK-NEXT: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY13]](p4) @@ -6034,8 +6068,10 @@ define void @test_call_external_void_func_v2p5_inreg(<2 x ptr addrspace(5)> inre ; CHECK-NEXT: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY1]] ; CHECK-NEXT: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR]](<2 x p5>) - ; CHECK-NEXT: $sgpr0 = COPY [[UV]](s32) - ; CHECK-NEXT: $sgpr1 = COPY [[UV1]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV]](s32) + ; CHECK-NEXT: $sgpr0 = COPY [[INTRINSIC_CONVERGENT]](s32) + ; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32) + ; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32) ; CHECK-NEXT: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3 ; CHECK-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>) ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY11]](p4) diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll index 06f66e05d6747e5f433b48929d2e68a05c72112c..8ca3e8255b63402eb2b91d19d174371b7afa4981 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll @@ -501,6 +501,79 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %a, <3 x i32> %b) { unreachable } +; Chain call with SGPR arguments that we cannot prove are uniform. +define amdgpu_cs void @cs_to_chain_nonuniform(<3 x i32> %a, <3 x i32> %b) { +; GISEL-GFX11-LABEL: cs_to_chain_nonuniform: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: v_readfirstlane_b32 s0, v0 +; GISEL-GFX11-NEXT: v_readfirstlane_b32 s1, v1 +; GISEL-GFX11-NEXT: v_readfirstlane_b32 s2, v2 +; GISEL-GFX11-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v10, v5 +; GISEL-GFX11-NEXT: s_mov_b32 s4, chain_callee@abs32@lo +; GISEL-GFX11-NEXT: s_mov_b32 s5, chain_callee@abs32@hi +; GISEL-GFX11-NEXT: s_mov_b32 exec_lo, -1 +; GISEL-GFX11-NEXT: s_setpc_b64 s[4:5] +; +; GISEL-GFX10-LABEL: cs_to_chain_nonuniform: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_getpc_b64 s[100:101] +; GISEL-GFX10-NEXT: s_mov_b32 s100, s0 +; GISEL-GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; GISEL-GFX10-NEXT: s_load_dwordx4 s[100:103], s[100:101], 0x10 +; GISEL-GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v8, v3 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v9, v4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v10, v5 +; GISEL-GFX10-NEXT: s_mov_b32 s4, chain_callee@abs32@lo +; GISEL-GFX10-NEXT: s_mov_b32 s5, chain_callee@abs32@hi +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: s_bitset0_b32 s103, 21 +; GISEL-GFX10-NEXT: s_add_u32 s100, s100, s0 +; GISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0 +; GISEL-GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; GISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101] +; GISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103] +; GISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1 +; GISEL-GFX10-NEXT: s_setpc_b64 s[4:5] +; +; DAGISEL-GFX11-LABEL: cs_to_chain_nonuniform: +; DAGISEL-GFX11: ; %bb.0: +; DAGISEL-GFX11-NEXT: v_readfirstlane_b32 s0, v0 +; DAGISEL-GFX11-NEXT: v_readfirstlane_b32 s1, v1 +; DAGISEL-GFX11-NEXT: v_readfirstlane_b32 s2, v2 +; DAGISEL-GFX11-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 +; DAGISEL-GFX11-NEXT: v_mov_b32_e32 v10, v5 +; DAGISEL-GFX11-NEXT: s_mov_b32 s5, chain_callee@abs32@hi +; DAGISEL-GFX11-NEXT: s_mov_b32 s4, chain_callee@abs32@lo +; DAGISEL-GFX11-NEXT: s_mov_b32 exec_lo, -1 +; DAGISEL-GFX11-NEXT: s_setpc_b64 s[4:5] +; +; DAGISEL-GFX10-LABEL: cs_to_chain_nonuniform: +; DAGISEL-GFX10: ; %bb.0: +; DAGISEL-GFX10-NEXT: s_getpc_b64 s[100:101] +; DAGISEL-GFX10-NEXT: s_mov_b32 s100, s0 +; DAGISEL-GFX10-NEXT: v_readfirstlane_b32 s1, v1 +; DAGISEL-GFX10-NEXT: s_load_dwordx4 s[100:103], s[100:101], 0x10 +; DAGISEL-GFX10-NEXT: v_readfirstlane_b32 s2, v2 +; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v8, v3 +; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v9, v4 +; DAGISEL-GFX10-NEXT: v_mov_b32_e32 v10, v5 +; DAGISEL-GFX10-NEXT: s_mov_b32 s5, chain_callee@abs32@hi +; DAGISEL-GFX10-NEXT: s_mov_b32 s4, chain_callee@abs32@lo +; DAGISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; DAGISEL-GFX10-NEXT: s_bitset0_b32 s103, 21 +; DAGISEL-GFX10-NEXT: s_add_u32 s100, s100, s0 +; DAGISEL-GFX10-NEXT: s_addc_u32 s101, s101, 0 +; DAGISEL-GFX10-NEXT: v_readfirstlane_b32 s0, v0 +; DAGISEL-GFX10-NEXT: s_mov_b64 s[48:49], s[100:101] +; DAGISEL-GFX10-NEXT: s_mov_b64 s[50:51], s[102:103] +; DAGISEL-GFX10-NEXT: s_mov_b32 exec_lo, -1 +; DAGISEL-GFX10-NEXT: s_setpc_b64 s[4:5] + call void(ptr, i32, <3 x i32>, <3 x i32>, i32, ...) @llvm.amdgcn.cs.chain.v3i32(ptr @chain_callee, i32 -1, <3 x i32> inreg %a, <3 x i32> %b, i32 0) + unreachable +} + define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %a, <3 x i32> %b) { ; GISEL-GFX11-LABEL: chain_to_chain: ; GISEL-GFX11: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/bfe-patterns.ll b/llvm/test/CodeGen/AMDGPU/bfe-patterns.ll index f54ea615ca664564b8210def7707c3593d71a695..c57a35aa1880db0df2fe846c34b0d9ff1f1ac9b8 100644 --- a/llvm/test/CodeGen/AMDGPU/bfe-patterns.ll +++ b/llvm/test/CodeGen/AMDGPU/bfe-patterns.ll @@ -17,7 +17,9 @@ define amdgpu_kernel void @v_ubfe_sub_i32(ptr addrspace(1) %out, ptr addrspace(1 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_mov_b64 s[2:3], s[6:7] -; SI-NEXT: v_bfe_u32 v2, v2, 0, v3 +; SI-NEXT: v_sub_i32_e32 v3, vcc, 32, v3 +; SI-NEXT: v_lshlrev_b32_e32 v2, v3, v2 +; SI-NEXT: v_lshrrev_b32_e32 v2, v3, v2 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: s_endpgm ; @@ -36,7 +38,9 @@ define amdgpu_kernel void @v_ubfe_sub_i32(ptr addrspace(1) %out, ptr addrspace(1 ; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_bfe_u32 v2, v3, 0, v4 +; VI-NEXT: v_sub_u32_e32 v2, vcc, 32, v4 +; VI-NEXT: v_lshlrev_b32_e32 v3, v2, v3 +; VI-NEXT: v_lshrrev_b32_e32 v2, v2, v3 ; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: s_endpgm %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() @@ -215,7 +219,9 @@ define amdgpu_kernel void @v_sbfe_sub_i32(ptr addrspace(1) %out, ptr addrspace(1 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc ; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_mov_b64 s[2:3], s[6:7] -; SI-NEXT: v_bfe_i32 v2, v2, 0, v3 +; SI-NEXT: v_sub_i32_e32 v3, vcc, 32, v3 +; SI-NEXT: v_lshlrev_b32_e32 v2, v3, v2 +; SI-NEXT: v_ashrrev_i32_e32 v2, v3, v2 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: s_endpgm ; @@ -234,7 +240,9 @@ define amdgpu_kernel void @v_sbfe_sub_i32(ptr addrspace(1) %out, ptr addrspace(1 ; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc -; VI-NEXT: v_bfe_i32 v2, v3, 0, v4 +; VI-NEXT: v_sub_u32_e32 v2, vcc, 32, v4 +; VI-NEXT: v_lshlrev_b32_e32 v3, v2, v3 +; VI-NEXT: v_ashrrev_i32_e32 v2, v2, v3 ; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: s_endpgm %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() diff --git a/llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir b/llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir index 2cb84c7ef4637d57f9a3ffd6c5af2de3bce6d085..072cc3a60a60caeb4e19642b01506684e1ef56b2 100644 --- a/llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir +++ b/llvm/test/CodeGen/AMDGPU/early-tailduplicator-nophis.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=early-tailduplication -o - %s | FileCheck %s # There are no phis in this testcase. Early tail duplication introduces them, # so the NoPHIs property needs to be cleared to avoid verifier errors diff --git a/llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir b/llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir index 41c6906b3c85ad288f03074b3d881e84ffe0a02d..8132fa4df89eee4d63cca069c598676167256834 100644 --- a/llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir +++ b/llvm/test/CodeGen/AMDGPU/early-tailduplicator-terminator.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=early-tailduplication -o - %s | FileCheck %s # Early tail duplication should not merge bb.6 into bb.5, adding a # non-terminator (S_SLEEP) after the terminator S_MOV_B32_term. diff --git a/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll b/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll index 9677ec41ce268a5999a87dfd04dc3c6a9d9fdf05..3d9616f02d52d16bcd245f1a71709eee8202c481 100644 --- a/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll +++ b/llvm/test/CodeGen/AMDGPU/extract-lowbits.ll @@ -150,11 +150,21 @@ define i32 @bzhi32_c4_commutative(i32 %val, i32 %numlowbits) nounwind { ; ---------------------------------------------------------------------------- ; define i32 @bzhi32_d0(i32 %val, i32 %numlowbits) nounwind { -; GCN-LABEL: bzhi32_d0: -; GCN: ; %bb.0: -; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_bfe_u32 v0, v0, 0, v1 -; GCN-NEXT: s_setpc_b64 s[30:31] +; SI-LABEL: bzhi32_d0: +; SI: ; %bb.0: +; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; SI-NEXT: v_sub_i32_e32 v1, vcc, 32, v1 +; SI-NEXT: v_lshlrev_b32_e32 v0, v1, v0 +; SI-NEXT: v_lshrrev_b32_e32 v0, v1, v0 +; SI-NEXT: s_setpc_b64 s[30:31] +; +; VI-LABEL: bzhi32_d0: +; VI: ; %bb.0: +; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; VI-NEXT: v_sub_u32_e32 v1, vcc, 32, v1 +; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0 +; VI-NEXT: v_lshrrev_b32_e32 v0, v1, v0 +; VI-NEXT: s_setpc_b64 s[30:31] %numhighbits = sub i32 32, %numlowbits %highbitscleared = shl i32 %val, %numhighbits %masked = lshr i32 %highbitscleared, %numhighbits diff --git a/llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir b/llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir new file mode 100644 index 0000000000000000000000000000000000000000..8065e2cfc0043224a3f99b44f85ef0f2fd316c93 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fold-omod-crash.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fold-operands %s -verify-machineinstrs -o - | FileCheck %s -check-prefix=GFX9 + +# When V_ADD_F32 is replaced with an output modifier on V_RSQ_F32, check that +# the kill flag is cleared on the use of %4 in V_MUL_F32. +--- +name: main +tracksRegLiveness: true +machineFunctionInfo: + mode: + ieee: false + fp32-input-denormals: false + fp32-output-denormals: false +body: | + ; GFX9-LABEL: name: main + ; GFX9: bb.0: + ; GFX9-NEXT: successors: %bb.1(0x80000000) + ; GFX9-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 + ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX9-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; GFX9-NEXT: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, undef [[DEF]], 0, 1, implicit $mode, implicit $exec + ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: bb.1: + ; GFX9-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GFX9-NEXT: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, killed undef [[DEF2]], 0, [[V_RSQ_F32_e64_]], 0, 0, implicit $mode, implicit $exec + ; GFX9-NEXT: SI_LOOP undef [[DEF1]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + ; GFX9-NEXT: S_BRANCH %bb.2 + ; GFX9-NEXT: {{ $}} + ; GFX9-NEXT: bb.2: + ; GFX9-NEXT: S_ENDPGM 0 + bb.0: + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 + + %0:vgpr_32 = IMPLICIT_DEF + %1:sreg_64 = IMPLICIT_DEF + %2:vgpr_32 = nofpexcept V_RSQ_F32_e64 0, undef %0, 0, 0, implicit $mode, implicit $exec + + bb.1: + %3:vgpr_32 = IMPLICIT_DEF + %4:vgpr_32 = nsz reassoc nofpexcept V_ADD_F32_e64 0, undef %2, 0, undef %2, 0, 0, implicit $mode, implicit $exec + %5:vgpr_32 = V_MUL_F32_e64 0, killed undef %3, 0, killed %4, 0, 0, implicit $mode, implicit $exec + SI_LOOP undef %1, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + S_BRANCH %bb.2 + + bb.2: + S_ENDPGM 0 +... diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll index 469d0453b9dfb1cde3a3891927233d54e139ee1e..ae309f3a614d50b4aba87fe30405ac6919479c2d 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w32.ll @@ -6,7 +6,6 @@ declare amdgpu_cs_chain void @callee(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) declare amdgpu_cs_chain_preserve void @callee_preserve(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) -declare void @llvm.amdgcn.cs.chain(ptr, i32, <3 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) noreturn define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr) { ; GISEL-GFX11-LABEL: name: chain_to_chain @@ -20,9 +19,15 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY5]] @@ -30,8 +35,8 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY7]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: chain_to_chain ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -44,20 +49,26 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY6]] - ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY8]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: chain_to_chain ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -136,9 +147,15 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5 ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY5]] @@ -146,8 +163,8 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5 ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY7]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: cs_to_chain ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -160,20 +177,26 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5 ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY6]] - ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY8]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: cs_to_chain ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -252,9 +275,15 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3 ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY5]] @@ -262,8 +291,8 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3 ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY7]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: chain_to_chain_preserve ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -276,20 +305,26 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3 ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY6]] - ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY8]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: chain_to_chain_preserve ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -368,9 +403,15 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY5]] @@ -378,8 +419,8 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY7]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY10]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: cs_to_chain_preserve ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -392,20 +433,26 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY6]] - ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY8]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: cs_to_chain_preserve ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -487,9 +534,15 @@ define amdgpu_cs_chain void @indirect(ptr inreg %callee, <3 x i32> inreg %sgpr, ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY2]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY3]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY5]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY6]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY7]] @@ -510,15 +563,21 @@ define amdgpu_cs_chain void @indirect(ptr inreg %callee, <3 x i32> inreg %sgpr, ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY2]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY3]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY6]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY7]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY8]] - ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY9]] + ; GISEL-GFX10-NEXT: [[COPY12:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY12]] ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], 0, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: indirect @@ -600,6 +659,93 @@ define amdgpu_cs_chain void @indirect(ptr inreg %callee, <3 x i32> inreg %sgpr, unreachable } +; Indirect with callee that we cannot prove is uniform. +define amdgpu_cs_chain void @nonuniform_callee(ptr %callee, i32 inreg %sgpr, i32 %vgpr) { + ; GISEL-GFX11-LABEL: name: nonuniform_callee + ; GISEL-GFX11: bb.1 (%ir-block.0): + ; GISEL-GFX11-NEXT: liveins: $sgpr0, $vgpr8, $vgpr9, $vgpr10 + ; GISEL-GFX11-NEXT: {{ $}} + ; GISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; GISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; GISEL-GFX11-NEXT: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY2]], 0, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8 + ; + ; GISEL-GFX10-LABEL: name: nonuniform_callee + ; GISEL-GFX10: bb.1 (%ir-block.0): + ; GISEL-GFX10-NEXT: liveins: $sgpr0, $vgpr8, $vgpr9, $vgpr10 + ; GISEL-GFX10-NEXT: {{ $}} + ; GISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; GISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; GISEL-GFX10-NEXT: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY6]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY2]], 0, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; + ; DAGISEL-GFX11-LABEL: name: nonuniform_callee + ; DAGISEL-GFX11: bb.0 (%ir-block.0): + ; DAGISEL-GFX11-NEXT: liveins: $vgpr8, $vgpr9, $sgpr0, $vgpr10 + ; DAGISEL-GFX11-NEXT: {{ $}} + ; DAGISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; DAGISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0 + ; DAGISEL-GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; DAGISEL-GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; DAGISEL-GFX11-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; DAGISEL-GFX11-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; DAGISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 + ; DAGISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1 + ; DAGISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY4]], implicit $exec + ; DAGISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0 + ; DAGISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY5]], implicit $exec + ; DAGISEL-GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:ccr_sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_1]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_]], %subreg.sub1 + ; DAGISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; DAGISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; DAGISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; DAGISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_2]] + ; DAGISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY]] + ; DAGISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 killed [[REG_SEQUENCE1]], 0, 0, killed [[S_MOV_B32_]], amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8 + ; + ; DAGISEL-GFX10-LABEL: name: nonuniform_callee + ; DAGISEL-GFX10: bb.0 (%ir-block.0): + ; DAGISEL-GFX10-NEXT: liveins: $vgpr8, $vgpr9, $sgpr0, $vgpr10 + ; DAGISEL-GFX10-NEXT: {{ $}} + ; DAGISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; DAGISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0 + ; DAGISEL-GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; DAGISEL-GFX10-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; DAGISEL-GFX10-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; DAGISEL-GFX10-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; DAGISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 + ; DAGISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1 + ; DAGISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY4]], implicit $exec + ; DAGISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0 + ; DAGISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY5]], implicit $exec + ; DAGISEL-GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:ccr_sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_1]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_]], %subreg.sub1 + ; DAGISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; DAGISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; DAGISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; DAGISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 + ; DAGISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; DAGISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_2]] + ; DAGISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY]] + ; DAGISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 killed [[REG_SEQUENCE1]], 0, 0, killed [[S_MOV_B32_]], amdgpu_allvgprs, implicit $sgpr48_sgpr49_sgpr50_sgpr51, implicit $sgpr0, implicit $vgpr8 + call void(ptr, i32, i32, i32, i32, ...) @llvm.amdgcn.cs.chain(ptr %callee, i32 -1, i32 inreg %sgpr, i32 %vgpr, i32 0) + unreachable +} + define amdgpu_cs_chain void @non_imm_exec(i32 inreg %exec, <3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr) { ; GISEL-GFX11-LABEL: name: non_imm_exec ; GISEL-GFX11: bb.1 (%ir-block.0): @@ -613,9 +759,15 @@ define amdgpu_cs_chain void @non_imm_exec(i32 inreg %exec, <3 x i32> inreg %sgpr ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY2]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY5]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY6]] @@ -623,8 +775,8 @@ define amdgpu_cs_chain void @non_imm_exec(i32 inreg %exec, <3 x i32> inreg %sgpr ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY8]], @callee, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W32 [[COPY11]], @callee, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: non_imm_exec ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -638,20 +790,26 @@ define amdgpu_cs_chain void @non_imm_exec(i32 inreg %exec, <3 x i32> inreg %sgpr ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY2]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY3]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY6]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY7]] - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY8]] + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY11]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY9]], @callee, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY12:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[COPY12]], @callee, 0, [[COPY]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: non_imm_exec ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -734,9 +892,15 @@ define amdgpu_cs_chain void @indirect_with_non_imm_exec(ptr inreg %callee, i32 i ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY3]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY4]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY5]] + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY6]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY7]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY8]] @@ -758,15 +922,21 @@ define amdgpu_cs_chain void @indirect_with_non_imm_exec(ptr inreg %callee, i32 i ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY3]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY4]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY5]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY6]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY7]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY8]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY9]] - ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] + ; GISEL-GFX10-NEXT: [[COPY13:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY13]] ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W32 [[REG_SEQUENCE]], 0, 0, [[COPY2]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: indirect_with_non_imm_exec diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll index 51c28a02b7f8214a1befd7bdedee9ee8dfb2316e..90707e823c14781dd4333d3a96e7128cd13ee04b 100644 --- a/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll +++ b/llvm/test/CodeGen/AMDGPU/isel-amdgcn-cs-chain-intrinsic-w64.ll @@ -6,7 +6,6 @@ declare amdgpu_cs_chain void @callee(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) declare amdgpu_cs_chain_preserve void @callee_preserve(<3 x i32> inreg, { i32, ptr addrspace(5), i32, i32 }) -declare void @llvm.amdgcn.cs.chain(ptr, i64, <3 x i32>, { i32, ptr addrspace(5), i32, i32 }, i32, ...) noreturn define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr) { ; GISEL-GFX11-LABEL: name: chain_to_chain @@ -20,9 +19,15 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY5]] @@ -30,8 +35,8 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY7]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: chain_to_chain ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -44,20 +49,26 @@ define amdgpu_cs_chain void @chain_to_chain(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY6]] - ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY8]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: chain_to_chain ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -136,9 +147,15 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5 ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY5]] @@ -146,8 +163,8 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5 ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY7]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: cs_to_chain ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -160,20 +177,26 @@ define amdgpu_cs void @cs_to_chain(<3 x i32> inreg %sgpr, { i32, ptr addrspace(5 ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY6]] - ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY8]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY11]], @callee, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: cs_to_chain ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -252,9 +275,15 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3 ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY5]] @@ -262,8 +291,8 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3 ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY7]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: chain_to_chain_preserve ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -276,20 +305,26 @@ define amdgpu_cs_chain void @chain_to_chain_preserve(<3 x i32> inreg %sgpr, { i3 ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY6]] - ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY8]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY11]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: chain_to_chain_preserve ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -368,9 +403,15 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY5]] @@ -378,8 +419,8 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY7]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: cs_to_chain_preserve ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -392,20 +433,26 @@ define amdgpu_cs void @cs_to_chain_preserve(<3 x i32> inreg %sgpr, { i32, ptr ad ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY1]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY3]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY4]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY6]] - ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:sgpr_128 = COPY $sgpr100_sgpr101_sgpr102_sgpr103 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY10]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee_preserve ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee_preserve ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY8]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY11]], @callee_preserve, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: cs_to_chain_preserve ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -487,9 +534,15 @@ define amdgpu_cs_chain void @indirect(ptr inreg %callee, <3 x i32> inreg %sgpr, ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY2]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY3]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY5]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY6]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY7]] @@ -510,15 +563,21 @@ define amdgpu_cs_chain void @indirect(ptr inreg %callee, <3 x i32> inreg %sgpr, ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY2]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY3]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY6]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY7]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY8]] - ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY9]] + ; GISEL-GFX10-NEXT: [[COPY12:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY12]] ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], 0, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: indirect @@ -600,6 +659,92 @@ define amdgpu_cs_chain void @indirect(ptr inreg %callee, <3 x i32> inreg %sgpr, unreachable } +; Indirect with callee that we cannot prove is uniform. +define amdgpu_cs_chain void @nonuniform_callee(ptr %callee, i32 inreg %sgpr, i32 %vgpr) { + ; GISEL-GFX11-LABEL: name: nonuniform_callee + ; GISEL-GFX11: bb.1 (%ir-block.0): + ; GISEL-GFX11-NEXT: liveins: $sgpr0, $vgpr8, $vgpr9, $vgpr10 + ; GISEL-GFX11-NEXT: {{ $}} + ; GISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; GISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; GISEL-GFX11-NEXT: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; GISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY2]], 0, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8 + ; + ; GISEL-GFX10-LABEL: name: nonuniform_callee + ; GISEL-GFX10: bb.1 (%ir-block.0): + ; GISEL-GFX10-NEXT: liveins: $sgpr0, $vgpr8, $vgpr9, $vgpr10 + ; GISEL-GFX10-NEXT: {{ $}} + ; GISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; GISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; GISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; GISEL-GFX10-NEXT: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE]] + ; GISEL-GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; GISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY6]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY2]], 0, 0, -1, amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; + ; DAGISEL-GFX11-LABEL: name: nonuniform_callee + ; DAGISEL-GFX11: bb.0 (%ir-block.0): + ; DAGISEL-GFX11-NEXT: liveins: $vgpr8, $vgpr9, $sgpr0, $vgpr10 + ; DAGISEL-GFX11-NEXT: {{ $}} + ; DAGISEL-GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; DAGISEL-GFX11-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0 + ; DAGISEL-GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; DAGISEL-GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; DAGISEL-GFX11-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; DAGISEL-GFX11-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; DAGISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 + ; DAGISEL-GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1 + ; DAGISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY4]], implicit $exec + ; DAGISEL-GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0 + ; DAGISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY5]], implicit $exec + ; DAGISEL-GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:ccr_sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_1]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_]], %subreg.sub1 + ; DAGISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; DAGISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; DAGISEL-GFX11-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 + ; DAGISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_2]] + ; DAGISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY]] + ; DAGISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 killed [[REG_SEQUENCE1]], 0, 0, killed [[S_MOV_B64_]], amdgpu_allvgprs, implicit $sgpr0, implicit $vgpr8 + ; + ; DAGISEL-GFX10-LABEL: name: nonuniform_callee + ; DAGISEL-GFX10: bb.0 (%ir-block.0): + ; DAGISEL-GFX10-NEXT: liveins: $vgpr8, $vgpr9, $sgpr0, $vgpr10 + ; DAGISEL-GFX10-NEXT: {{ $}} + ; DAGISEL-GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; DAGISEL-GFX10-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr0 + ; DAGISEL-GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; DAGISEL-GFX10-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; DAGISEL-GFX10-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; DAGISEL-GFX10-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; DAGISEL-GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY2]], %subreg.sub1 + ; DAGISEL-GFX10-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1 + ; DAGISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY4]], implicit $exec + ; DAGISEL-GFX10-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0 + ; DAGISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY5]], implicit $exec + ; DAGISEL-GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:ccr_sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_1]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_]], %subreg.sub1 + ; DAGISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] + ; DAGISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; DAGISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; DAGISEL-GFX10-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 + ; DAGISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY7]] + ; DAGISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_2]] + ; DAGISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY]] + ; DAGISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 killed [[REG_SEQUENCE1]], 0, 0, killed [[S_MOV_B64_]], amdgpu_allvgprs, implicit $sgpr48_sgpr49_sgpr50_sgpr51, implicit $sgpr0, implicit $vgpr8 + call void(ptr, i64, i32, i32, i32, ...) @llvm.amdgcn.cs.chain(ptr %callee, i64 -1, i32 inreg %sgpr, i32 %vgpr, i32 0) + unreachable +} define amdgpu_cs_chain void @non_imm_exec(i64 inreg %exec, <3 x i32> inreg %sgpr, { i32, ptr addrspace(5), i32, i32 } %vgpr) { ; GISEL-GFX11-LABEL: name: non_imm_exec ; GISEL-GFX11: bb.1 (%ir-block.0): @@ -615,9 +760,15 @@ define amdgpu_cs_chain void @non_imm_exec(i64 inreg %exec, <3 x i32> inreg %sgpr ; GISEL-GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY2]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY3]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY5]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY6]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY7]] @@ -625,8 +776,8 @@ define amdgpu_cs_chain void @non_imm_exec(i64 inreg %exec, <3 x i32> inreg %sgpr ; GISEL-GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE1]] - ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY9]], @callee, 0, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 + ; GISEL-GFX11-NEXT: [[COPY12:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE1]] + ; GISEL-GFX11-NEXT: SI_CS_CHAIN_TC_W64 [[COPY12]], @callee, 0, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11 ; ; GISEL-GFX10-LABEL: name: non_imm_exec ; GISEL-GFX10: bb.1 (%ir-block.0): @@ -642,20 +793,26 @@ define amdgpu_cs_chain void @non_imm_exec(i64 inreg %exec, <3 x i32> inreg %sgpr ; GISEL-GFX10-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY2]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY3]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY2]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY3]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY10]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY5]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY6]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY7]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY8]] - ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY9]] + ; GISEL-GFX10-NEXT: [[COPY12:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY12]] ; GISEL-GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @callee ; GISEL-GFX10-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-hi) @callee ; GISEL-GFX10-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1 - ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE1]] - ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY10]], @callee, 0, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: [[COPY13:%[0-9]+]]:ccr_sgpr_64 = COPY [[REG_SEQUENCE1]] + ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[COPY13]], @callee, 0, [[REG_SEQUENCE]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: non_imm_exec ; DAGISEL-GFX11: bb.0 (%ir-block.0): @@ -744,9 +901,15 @@ define amdgpu_cs_chain void @indirect_with_non_imm_exec(ptr inreg %callee, i64 i ; GISEL-GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[COPY4]] - ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[COPY5]] - ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[COPY6]] + ; GISEL-GFX11-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX11-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX11-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GISEL-GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec + ; GISEL-GFX11-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX11-NEXT: $vgpr8 = COPY [[COPY7]] ; GISEL-GFX11-NEXT: $vgpr9 = COPY [[COPY8]] ; GISEL-GFX11-NEXT: $vgpr10 = COPY [[COPY9]] @@ -770,15 +933,21 @@ define amdgpu_cs_chain void @indirect_with_non_imm_exec(ptr inreg %callee, i64 i ; GISEL-GFX10-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr9 ; GISEL-GFX10-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr10 ; GISEL-GFX10-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr11 - ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[COPY4]] - ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[COPY5]] - ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[COPY6]] + ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY11]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]] + ; GISEL-GFX10-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY12]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]] + ; GISEL-GFX10-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[COPY6]] + ; GISEL-GFX10-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[COPY13]], implicit $exec + ; GISEL-GFX10-NEXT: $sgpr2 = COPY [[V_READFIRSTLANE_B32_2]] ; GISEL-GFX10-NEXT: $vgpr8 = COPY [[COPY7]] ; GISEL-GFX10-NEXT: $vgpr9 = COPY [[COPY8]] ; GISEL-GFX10-NEXT: $vgpr10 = COPY [[COPY9]] ; GISEL-GFX10-NEXT: $vgpr11 = COPY [[COPY10]] - ; GISEL-GFX10-NEXT: [[COPY11:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 - ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY11]] + ; GISEL-GFX10-NEXT: [[COPY14:%[0-9]+]]:sgpr_128 = COPY $sgpr48_sgpr49_sgpr50_sgpr51 + ; GISEL-GFX10-NEXT: $sgpr48_sgpr49_sgpr50_sgpr51 = COPY [[COPY14]] ; GISEL-GFX10-NEXT: SI_CS_CHAIN_TC_W64 [[REG_SEQUENCE]], 0, 0, [[REG_SEQUENCE1]], amdgpu_allvgprs, implicit $sgpr0, implicit $sgpr1, implicit $sgpr2, implicit $vgpr8, implicit $vgpr9, implicit $vgpr10, implicit $vgpr11, implicit $sgpr48_sgpr49_sgpr50_sgpr51 ; ; DAGISEL-GFX11-LABEL: name: indirect_with_non_imm_exec diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll new file mode 100644 index 0000000000000000000000000000000000000000..b0d578e421e280ce320b2700b77e86ebd4f99714 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-invalid-vector-gep.ll @@ -0,0 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s + +; Check that invalid IR is not produced on a vector typed +; getelementptr with a scalar alloca pointer base. + +define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset() { +; CHECK-LABEL: define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset() { +; CHECK-NEXT: [[BB:.*:]] +; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) +; CHECK-NEXT: [[GETELEMENTPTR:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ALLOCA]], <4 x i64> +; CHECK-NEXT: [[EXTRACTELEMENT:%.*]] = extractelement <4 x ptr addrspace(5)> [[GETELEMENTPTR]], i64 0 +; CHECK-NEXT: store i32 0, ptr addrspace(5) [[EXTRACTELEMENT]], align 4 +; CHECK-NEXT: ret void +; +bb: + %alloca = alloca i32, align 4, addrspace(5) + %getelementptr = getelementptr inbounds i8, ptr addrspace(5) %alloca, <4 x i64> + %extractelement = extractelement <4 x ptr addrspace(5)> %getelementptr, i64 0 + store i32 0, ptr addrspace(5) %extractelement + ret void +} + +define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset_select(i1 %cond) { +; CHECK-LABEL: define amdgpu_kernel void @scalar_alloca_ptr_with_vector_gep_offset_select( +; CHECK-SAME: i1 [[COND:%.*]]) { +; CHECK-NEXT: [[BB:.*:]] +; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i32, align 4, addrspace(5) +; CHECK-NEXT: [[GETELEMENTPTR0:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ALLOCA]], <4 x i64> +; CHECK-NEXT: [[GETELEMENTPTR1:%.*]] = getelementptr inbounds i8, ptr addrspace(5) [[ALLOCA]], <4 x i64> +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], <4 x ptr addrspace(5)> [[GETELEMENTPTR0]], <4 x ptr addrspace(5)> [[GETELEMENTPTR1]] +; CHECK-NEXT: [[EXTRACTELEMENT:%.*]] = extractelement <4 x ptr addrspace(5)> [[SELECT]], i64 1 +; CHECK-NEXT: store i32 0, ptr addrspace(5) [[EXTRACTELEMENT]], align 4 +; CHECK-NEXT: ret void +; +bb: + %alloca = alloca i32, align 4, addrspace(5) + %getelementptr0 = getelementptr inbounds i8, ptr addrspace(5) %alloca, <4 x i64> + %getelementptr1 = getelementptr inbounds i8, ptr addrspace(5) %alloca, <4 x i64> + %select = select i1 %cond, <4 x ptr addrspace(5)> %getelementptr0, <4 x ptr addrspace(5)> %getelementptr1 + %extractelement = extractelement <4 x ptr addrspace(5)> %select, i64 1 + store i32 0, ptr addrspace(5) %extractelement + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir b/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir index c23c8900096fba1c7b344f51360335b85d460960..be1a8aceb8c9032e95b7b3158dfc03e1fe00128c 100644 --- a/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir +++ b/llvm/test/CodeGen/AMDGPU/stop-tail-duplicate-cfg-intrinsic.mir @@ -1,5 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=early-tailduplication -verify-machineinstrs -o - %s | FileCheck %s +# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes=early-tailduplication -o - %s | FileCheck %s --- name: stop_duplicate_cfg_intrinsic diff --git a/llvm/test/CodeGen/DirectX/countbits.ll b/llvm/test/CodeGen/DirectX/countbits.ll index c6bc2b6790948ee0aa843c7f73908eff5ab4cc4a..f03ab9c5e79c35458001c57bb474c9f727e36273 100644 --- a/llvm/test/CodeGen/DirectX/countbits.ll +++ b/llvm/test/CodeGen/DirectX/countbits.ll @@ -4,35 +4,67 @@ define noundef i16 @test_countbits_short(i16 noundef %a) { entry: -; CHECK: call i16 @dx.op.unary.i16(i32 31, i16 %{{.*}}) +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i16(i32 31, i16 %{{.*}}) +; CHECK-NEXT: [[B:%.*]] = trunc i32 [[A]] to i16 +; CHECK-NEXT ret i16 [[B]] %elt.ctpop = call i16 @llvm.ctpop.i16(i16 %a) ret i16 %elt.ctpop } +define noundef i32 @test_countbits_short2(i16 noundef %a) { +entry: +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i16(i32 31, i16 %{{.*}}) +; CHECK-NEXT: ret i32 [[A]] + %elt.ctpop = call i16 @llvm.ctpop.i16(i16 %a) + %elt.zext = zext i16 %elt.ctpop to i32 + ret i32 %elt.zext +} + +define noundef i32 @test_countbits_short3(i16 noundef %a) { +entry: +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i16(i32 31, i16 %{{.*}}) +; CHECK-NEXT: ret i32 [[A]] + %elt.ctpop = call i16 @llvm.ctpop.i16(i16 %a) + %elt.sext = sext i16 %elt.ctpop to i32 + ret i32 %elt.sext +} + define noundef i32 @test_countbits_int(i32 noundef %a) { entry: -; CHECK: call i32 @dx.op.unary.i32(i32 31, i32 %{{.*}}) +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 %{{.*}}) +; CHECK-NEXT: ret i32 [[A]] %elt.ctpop = call i32 @llvm.ctpop.i32(i32 %a) ret i32 %elt.ctpop } define noundef i64 @test_countbits_long(i64 noundef %a) { entry: -; CHECK: call i64 @dx.op.unary.i64(i32 31, i64 %{{.*}}) +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i64(i32 31, i64 %{{.*}}) +; CHECK-NEXT: [[B:%.*]] = zext i32 [[A]] to i64 +; CHECK-NEXT ret i64 [[B]] %elt.ctpop = call i64 @llvm.ctpop.i64(i64 %a) ret i64 %elt.ctpop } +define noundef i32 @test_countbits_long2(i64 noundef %a) { +entry: +; CHECK: [[A:%.*]] = call i32 @dx.op.unaryBits.i64(i32 31, i64 %{{.*}}) +; CHECK-NEXT: ret i32 [[A]] + %elt.ctpop = call i64 @llvm.ctpop.i64(i64 %a) + %elt.trunc = trunc i64 %elt.ctpop to i32 + ret i32 %elt.trunc +} + define noundef <4 x i32> @countbits_vec4_i32(<4 x i32> noundef %a) { entry: ; CHECK: [[ee0:%.*]] = extractelement <4 x i32> %a, i64 0 - ; CHECK: [[ie0:%.*]] = call i32 @dx.op.unary.i32(i32 31, i32 [[ee0]]) + ; CHECK: [[ie0:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 [[ee0]]) ; CHECK: [[ee1:%.*]] = extractelement <4 x i32> %a, i64 1 - ; CHECK: [[ie1:%.*]] = call i32 @dx.op.unary.i32(i32 31, i32 [[ee1]]) + ; CHECK: [[ie1:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 [[ee1]]) ; CHECK: [[ee2:%.*]] = extractelement <4 x i32> %a, i64 2 - ; CHECK: [[ie2:%.*]] = call i32 @dx.op.unary.i32(i32 31, i32 [[ee2]]) + ; CHECK: [[ie2:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 [[ee2]]) ; CHECK: [[ee3:%.*]] = extractelement <4 x i32> %a, i64 3 - ; CHECK: [[ie3:%.*]] = call i32 @dx.op.unary.i32(i32 31, i32 [[ee3]]) + ; CHECK: [[ie3:%.*]] = call i32 @dx.op.unaryBits.i32(i32 31, i32 [[ee3]]) ; CHECK: insertelement <4 x i32> poison, i32 [[ie0]], i64 0 ; CHECK: insertelement <4 x i32> %{{.*}}, i32 [[ie1]], i64 1 ; CHECK: insertelement <4 x i32> %{{.*}}, i32 [[ie2]], i64 2 diff --git a/llvm/test/CodeGen/Generic/MIRStripDebug/bundles.mir b/llvm/test/CodeGen/Generic/MIRStripDebug/bundles.mir new file mode 100644 index 0000000000000000000000000000000000000000..111c886f585cf65a1c68b042f3f9af701b12dd96 --- /dev/null +++ b/llvm/test/CodeGen/Generic/MIRStripDebug/bundles.mir @@ -0,0 +1,63 @@ +# RUN: llc -run-pass=mir-strip-debug -o - %s | FileCheck %s +# RUN: llc -run-pass=mir-strip-debug,mir-debugify,mir-strip-debug -o - %s | FileCheck %s + +--- | + source_filename = "loc-only.ll" + + define i32 @test(i32 %a, i32 %b) !dbg !6 { + %add = add i32 %a, 2, !dbg !12 + call void @llvm.dbg.value(metadata i32 %add, metadata !9, metadata !DIExpression()), !dbg !12 + %sub = sub i32 %add, %b, !dbg !13 + call void @llvm.dbg.value(metadata i32 %sub, metadata !11, metadata !DIExpression()), !dbg !13 + ret i32 %sub, !dbg !14 + } + + declare void @llvm.dbg.value(metadata, metadata, metadata) + + !llvm.dbg.cu = !{!0} + ; CHECK-NOT: !llvm.dbg.cu + !llvm.debugify = !{!3, !4} + ; CHECK-NOT: !llvm.debugify + !llvm.module.flags = !{!5} + ; CHECK-NOT: !llvm.module.flags + + ; CHECK-NOT: !DI + !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) + !1 = !DIFile(filename: "", directory: "/") + !2 = !{} + !3 = !{i32 3} + !4 = !{i32 2} + !5 = !{i32 2, !"Debug Info Version", i32 3} + !6 = distinct !DISubprogram(name: "test", linkageName: "test", scope: null, file: !1, line: 1, type: !7, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !8) + !7 = !DISubroutineType(types: !2) + !8 = !{!9, !11} + !9 = !DILocalVariable(name: "1", scope: !6, file: !1, line: 1, type: !10) + !10 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned) + !11 = !DILocalVariable(name: "2", scope: !6, file: !1, line: 2, type: !10) + !12 = !DILocation(line: 1, column: 1, scope: !6) + !13 = !DILocation(line: 2, column: 1, scope: !6) + !14 = !DILocation(line: 3, column: 1, scope: !6) + +... +--- +name: test +body: | + bb.1 (%ir-block.0): + %0:_(s32) = G_IMPLICIT_DEF + %1:_(s32) = G_IMPLICIT_DEF + BUNDLE { + %2:_(s32) = G_CONSTANT i32 2, debug-location !DILocation(line: 0, scope: !6) + %3:_(s32) = G_ADD %0, %1, debug-location !12 + } + + ; CHECK-LABEL: body: + ; CHECK-NOT: debug-location + ; CHECK-NOT: !DI + ; CHECK-NEXT: bb + ; CHECK-NEXT: %0:_(s32) = G_IMPLICIT_DEF{{$}} + ; CHECK-NEXT: %1:_(s32) = G_IMPLICIT_DEF{{$}} + ; CHECK-NEXT: BUNDLE { + ; CHECK-NEXT: %2:_(s32) = G_CONSTANT i32 2{{$}} + ; CHECK-NEXT: %3:_(s32) = G_ADD %0, %1{{$}} + ; CHECK-NEXT: } +... diff --git a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll index fd5f26ba35742f3c11a74a29899ecb263dde8e49..7147257d27c4b8bf005b13c210ebebca94ad09ce 100644 --- a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll +++ b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll @@ -129,12 +129,11 @@ entry: define i1 @test_ssubo_i32(i32 %a, i32 %b) nounwind { ; CHECK-LABEL: test_ssubo_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: sub 5, 3, 4 -; CHECK-NEXT: cmpwi 1, 4, 0 -; CHECK-NEXT: cmpw 5, 3 -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: creqv 20, 5, 0 -; CHECK-NEXT: isel 3, 0, 3, 20 +; CHECK-NEXT: sub 3, 3, 4 +; CHECK-NEXT: extsw 4, 3 +; CHECK-NEXT: xor 3, 4, 3 +; CHECK-NEXT: addic 4, 3, -1 +; CHECK-NEXT: subfe 3, 4, 3 ; CHECK-NEXT: blr entry: %res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind diff --git a/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll b/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll index 5ced89c17c42087f9c805435d55d2508eca53fb3..da477aa2043cf12a742f5272d6132e249d1566be 100644 --- a/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll +++ b/llvm/test/CodeGen/RISCV/rvv/65704-illegal-instruction.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+m,+zfh,+zvfh \ +; RUN: llc -mtriple=riscv64 -mattr=+v,+f,+m,+zvfh \ ; RUN: < %s | FileCheck %s declare <16 x i8> @llvm.vector.extract.v16i8.nxv8i8(, i64 immarg) diff --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll index 35e269b91190257c94a17329fd5c60aa72f3090e..43be8feece23c1b10d922b2de78695f2f0b2daa7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll +++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll @@ -756,3 +756,104 @@ define void @lmul_8_x9() nounwind { %v9 = alloca ret void } + +define void @lmul_16_align() nounwind { +; NOZBA-LABEL: lmul_16_align: +; NOZBA: # %bb.0: +; NOZBA-NEXT: addi sp, sp, -144 +; NOZBA-NEXT: sd ra, 136(sp) # 8-byte Folded Spill +; NOZBA-NEXT: sd s0, 128(sp) # 8-byte Folded Spill +; NOZBA-NEXT: addi s0, sp, 144 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: li a1, 24 +; NOZBA-NEXT: mul a0, a0, a1 +; NOZBA-NEXT: sub sp, sp, a0 +; NOZBA-NEXT: andi sp, sp, -128 +; NOZBA-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; NOZBA-NEXT: vmv.v.i v8, 0 +; NOZBA-NEXT: csrr a0, vlenb +; NOZBA-NEXT: add a0, sp, a0 +; NOZBA-NEXT: addi a0, a0, 128 +; NOZBA-NEXT: vs8r.v v8, (a0) +; NOZBA-NEXT: csrr a1, vlenb +; NOZBA-NEXT: slli a1, a1, 3 +; NOZBA-NEXT: add a0, a0, a1 +; NOZBA-NEXT: vs8r.v v8, (a0) +; NOZBA-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; NOZBA-NEXT: vmv.v.i v8, 0 +; NOZBA-NEXT: addi a0, sp, 128 +; NOZBA-NEXT: vs1r.v v8, (a0) +; NOZBA-NEXT: addi sp, s0, -144 +; NOZBA-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; NOZBA-NEXT: ld s0, 128(sp) # 8-byte Folded Reload +; NOZBA-NEXT: addi sp, sp, 144 +; NOZBA-NEXT: ret +; +; ZBA-LABEL: lmul_16_align: +; ZBA: # %bb.0: +; ZBA-NEXT: addi sp, sp, -144 +; ZBA-NEXT: sd ra, 136(sp) # 8-byte Folded Spill +; ZBA-NEXT: sd s0, 128(sp) # 8-byte Folded Spill +; ZBA-NEXT: addi s0, sp, 144 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: slli a0, a0, 3 +; ZBA-NEXT: sh1add a0, a0, a0 +; ZBA-NEXT: sub sp, sp, a0 +; ZBA-NEXT: andi sp, sp, -128 +; ZBA-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; ZBA-NEXT: vmv.v.i v8, 0 +; ZBA-NEXT: csrr a0, vlenb +; ZBA-NEXT: add a0, sp, a0 +; ZBA-NEXT: addi a0, a0, 128 +; ZBA-NEXT: vs8r.v v8, (a0) +; ZBA-NEXT: csrr a1, vlenb +; ZBA-NEXT: sh3add a0, a1, a0 +; ZBA-NEXT: vs8r.v v8, (a0) +; ZBA-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; ZBA-NEXT: vmv.v.i v8, 0 +; ZBA-NEXT: addi a0, sp, 128 +; ZBA-NEXT: vs1r.v v8, (a0) +; ZBA-NEXT: addi sp, s0, -144 +; ZBA-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; ZBA-NEXT: ld s0, 128(sp) # 8-byte Folded Reload +; ZBA-NEXT: addi sp, sp, 144 +; ZBA-NEXT: ret +; +; NOMUL-LABEL: lmul_16_align: +; NOMUL: # %bb.0: +; NOMUL-NEXT: addi sp, sp, -144 +; NOMUL-NEXT: sd ra, 136(sp) # 8-byte Folded Spill +; NOMUL-NEXT: sd s0, 128(sp) # 8-byte Folded Spill +; NOMUL-NEXT: addi s0, sp, 144 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: slli a0, a0, 3 +; NOMUL-NEXT: mv a1, a0 +; NOMUL-NEXT: slli a0, a0, 1 +; NOMUL-NEXT: add a0, a0, a1 +; NOMUL-NEXT: sub sp, sp, a0 +; NOMUL-NEXT: andi sp, sp, -128 +; NOMUL-NEXT: vsetvli a0, zero, e64, m8, ta, ma +; NOMUL-NEXT: vmv.v.i v8, 0 +; NOMUL-NEXT: csrr a0, vlenb +; NOMUL-NEXT: add a0, sp, a0 +; NOMUL-NEXT: addi a0, a0, 128 +; NOMUL-NEXT: vs8r.v v8, (a0) +; NOMUL-NEXT: csrr a1, vlenb +; NOMUL-NEXT: slli a1, a1, 3 +; NOMUL-NEXT: add a0, a0, a1 +; NOMUL-NEXT: vs8r.v v8, (a0) +; NOMUL-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; NOMUL-NEXT: vmv.v.i v8, 0 +; NOMUL-NEXT: addi a0, sp, 128 +; NOMUL-NEXT: vs1r.v v8, (a0) +; NOMUL-NEXT: addi sp, s0, -144 +; NOMUL-NEXT: ld ra, 136(sp) # 8-byte Folded Reload +; NOMUL-NEXT: ld s0, 128(sp) # 8-byte Folded Reload +; NOMUL-NEXT: addi sp, sp, 144 +; NOMUL-NEXT: ret + %v1 = alloca + %v2 = alloca + store zeroinitializer, ptr %v1 + store zeroinitializer, ptr %v2 + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll index 15cff650765efaf9e2b2d3bab13bc68adb039a88..f9588ffb5da52778c555050f5a7446bbe0593bbd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll b/llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll index 4c40b7c74451d3e5b89cacdbb99aef929f5d45aa..7a995a8d29f9e05f619c37486b978abf2e4d7322 100644 --- a/llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll +++ b/llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s define @not_icmp_sle_nxv8i16( %a, %b) { ; CHECK-LABEL: not_icmp_sle_nxv8i16: diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll index 9ea1394a1dd2c4b432dda5bb7f36b1962de0c281..2c9f633b890143accb765fe11c8e222f06c57d2f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll index 77b2fd4729674155fb97ead1704e890a1b40f3d8..83396b8e59241a396613a5f905042f4d032da108 100644 --- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB diff --git a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll index dfc70299d015bd87ab7b896c625c60c0cb7445b1..63fd13d98c7adf44bf8af075b1b8851279994652 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s define @sextload_nxv1i1_nxv1i8(ptr %x) { ; CHECK-LABEL: sextload_nxv1i1_nxv1i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll index 63fa87852b646a7517ef0f1f349613b0428aaf4e..8e9751502460ecbde1843c65e1e1f0198c574d28 100644 --- a/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s define @extract_nxv8i32_nxv4i32_0( %vec) { ; CHECK-LABEL: extract_nxv8i32_nxv4i32_0: diff --git a/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll index d8781495abd75cda3c55dd847ffaf11eda3149a2..4e549a5aa7c3a5fcc07c8c16cbd624decb98d681 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @ceil_nxv1f16( %x) strictfp { diff --git a/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll index ee16b476dc84efccb5368ab3b9180f8d1922dbe4..35936574e8fe21be4625c0141537be6aa41690cf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll index 1df452d8641c589fb1c4ec143a618ee2bf845c49..f6b47743d1154ce4913d525e4a36fb74a48457c3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @floor_nxv1f16( %x) strictfp { diff --git a/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll index 00e21ce8992b0c7fb9b50476e24b24bef2c07aca..d26b74c7c139ec288a29ba80ee36c5ce18ec08ed 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll index 29489be4dcb569a833f30c9e1aeec5e3af23b4eb..327b168ffe6b5463713dc9c9c0fb2952f9761164 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,RV32 -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,RV64 +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,RV32 +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,RV64 define <1 x i1> @v1i1(i1 %x, i1 %y) { ; CHECK-LABEL: v1i1: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll index f124d550df16dabc6558a49761660ddfcf3c9836..9ad1d7167c6a03328151df8b4aeef8fe274f11d7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+zvfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfh -verify-machineinstrs \ ; RUN: -target-abi=ilp32d < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+zvfh -verify-machineinstrs \ +; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfh -verify-machineinstrs \ ; RUN: -target-abi=lp64d < %s | FileCheck %s --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+zve32f,+zvl128b,+d,+zfh,+zvfh \ +; RUN: llc -mtriple=riscv32 -mattr=+zve32f,+zvl128b,+d,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d < %s | FileCheck %s \ ; RUN: --check-prefixes=ELEN32,RV32ELEN32 -; RUN: llc -mtriple=riscv64 -mattr=+zve32f,+zvl128b,+d,+zfh,+zvfh \ +; RUN: llc -mtriple=riscv64 -mattr=+zve32f,+zvl128b,+d,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d < %s | FileCheck %s \ ; RUN: --check-prefixes=ELEN32,RV64ELEN32 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll index befbfb88550bade7cc725a8f40bdc131cd9447ef..f7840be8f0c65ba924a2578c60271c81de1a0e9a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.ceil.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll index 36fbdd8e0664fd9734acd2bbebb80c77080b2790..9d42f2b6adeedc64643d00568bc03cad4918ef92 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-compressstore-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare void @llvm.masked.compressstore.v1f16(<1 x half>, ptr, <1 x i1>) define void @compressstore_v1f16(ptr %base, <1 x half> %v, <1 x i1> %mask) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll index 9f8de22b25c2dfc01b7aa43a5bb58a2926a03710..1d7496397670f9dad74b3eb4e3e63db38fcc3930 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck %s ; Integers diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll index 8b31166e313debc6a40f5f26c486e828ed9b47bc..707e0797a11426c1d78d78f453a69e9ad30714a0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-expandload-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare <1 x half> @llvm.masked.expandload.v1f16(ptr, <1 x i1>, <1 x half>) define <1 x half> @expandload_v1f16(ptr %base, <1 x half> %src0, <1 x i1> %mask) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll index d309da6df7dc70cc13d5144e2186c03e5c7afaf4..f2052ccc462793b962dd8439dd4dc99bd63d5901 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32NOM -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32M -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64NOM -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64M +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32NOM +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32M +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64NOM +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64M define i8 @extractelt_v16i8(ptr %x) nounwind { ; CHECK-LABEL: extractelt_v16i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll index 404fb72b8abe91cb2862ba52a8c7d3cb6ceded28..84895715e814f9f9d4b49dfa064fea908728d815 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <1 x half> @ceil_v1f16(<1 x half> %x) strictfp { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll index 2319aab370d2de68e68b3d125640ff7bbff5bbad..3c99870dba950c87318da6b25a0bda0757c49815 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <1 x half> @floor_v1f16(<1 x half> %x) strictfp { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll index c1b4c5fda6c6400c64d40ed0aacb2dcd12793786..87061581af7398f8fa68e7b27bb7b0d6bf512054 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.floor.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll index 619104df9ca94fdf755446068fc178f7669e1496..c4ee860439f497187f5157f94da9f055df8a4e46 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.maximum.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll index 02c2fafc89785fa6218db99e8b8d2bd0b7fd6e18..ae592119cf88152ae09a45d5918a9b8d52bfedd9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.maximum.v2f16(<2 x half>, <2 x half>) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll index 7a5d7cbd244040f92312a085d502c1dc5b780660..7ea8d5dfeb7573a03160e1e18b6b2513d4413ab9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.minimum.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll index b15d697f0754ed462971ac9c4f8c01ddc8073bc6..8e042fc0785e1927fb7bf2427e71fb5495cac33c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.minimum.v2f16(<2 x half>, <2 x half>) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll index 719dd52494284604c9b7112495842e4a425e9353..0b9fabb832e29600bd79b7e2b4368c190e52eb9e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.experimental.constrained.nearbyint.v2f16(<2 x half>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll index 5f5015c9ad16903e59e305378ac1f4f81f33f1b7..5b35c0083ca0cdfd4f085b6adf5220762c938374 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV32-FP -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV64-FP diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll index 96b9b2bac2993ca1760e098e0ad603cfdb5aa5ef..924732e554f0ef98f0e5fa18fa19b70a9e06e4f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RV64V -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RVA22U64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zba,+zbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFH +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RV64V +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFH,RVA22U64 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFHMIN,RV32-NO-ZFHMIN ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVFHMIN,RV64-NO-ZFHMIN ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfhmin,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVFHMIN,RV32-ZFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll index d0dc70fd81151d0f7577ed311b2967773b80a396..ff52f5d2039e1e69cd2e961fa0139b23a05a3042 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s define void @fpext_v2f16_v2f32(ptr %x, ptr %y) { ; CHECK-LABEL: fpext_v2f16_v2f32: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll index f3b124aa34dcb5277d53e339cf63ba73867412d3..a138b02b6139d61c4459ded0d9bc019e79425e3a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+m,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V128,RV32-V128 -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+m,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V128,RV64-V128 -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV32-V512 -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV64-V512 +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+m,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V128,RV32-V128 +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+m,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V128,RV64-V128 +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV32-V512 +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+m,+zvl512b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V512,RV64-V512 ; Test optimizing interleaves to widening arithmetic. diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll index 250b3e90cbbb65af839cc7410a4a937889990b28..0d0ef9c87946ce727795de6b1a7de7700c1dc64f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFH +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFH ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFHMIN,RV64-ZVFHMIN-NOZFHMIN ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfhmin,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,RV64-ZVFHMIN,RV64_ZVFHMIN-ZFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll index d92dc3edecb0b947192f1a5d5cfd45ba81408b33..f0e6df629847140d5c369feffd33c350ffc84b94 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @fp2si_v2f32_v2i32(ptr %x, ptr %y) { ; CHECK-LABEL: fp2si_v2f32_v2i32: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll index 9d92018db2e88ea273058b4530905045a9cbaebb..da0bc5983a125143ad53f0edcc4a94feedd7dced 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64 define void @fp2si_v2f32_v2i32(ptr %x, ptr %y) { ; CHECK-LABEL: fp2si_v2f32_v2i32: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll index 31d7844251a77c5a4430bb9a54fe30a73e5ee870..a1466d46f1ba71f8659bc4ae8b9aead8f3ddc273 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s declare <2 x float> @llvm.vp.fpext.v2f32.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll index 602662b184290a97bcc2386e3fa4883b96ebc7ee..bc86be6f62fd1d455cd06bd1e276e504f918efc7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half>, <4 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll index a4050b716e78777bd0352dc7df30d17ba7fae7ff..f6c992280c6e3c307d94ebfaac0ea3aa4f35c029 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <4 x i7> @llvm.vp.fptosi.v4i7.v4f16(<4 x half>, <4 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll index c5bfd41ec9510db768506c0d72f92496503d8e2d..c41f14076db3173de774b7160a5a313df7b6932d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <4 x i1> @llvm.vp.fptoui.v4i1.v4f16(<4 x half>, <4 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll index b652cdd88c7c2c0ef31a2f30114a4ac0850e9369..af225f4d95aa2e833d23c5167a9a4f223926224c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <4 x i7> @llvm.vp.fptoui.v4i7.v4f16(<4 x half>, <4 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll index cd123cdf33a8f0a6cd5a2f48295b73d2d2fe69e3..e64c7c87132eee9091464b0052e265bbea9356e5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fptrunc.v2f16.v2f32(<2 x float>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll index e855d9504ff4048f7bb4dc15d7a9d206e04c4f65..131fa53b359998eea3994d16cb7db109af5c4e25 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This file tests the code generation for `llvm.experimental.constrained.round.*` on scalable vector type. diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll index 3f1bc03435840bedba6979a3a03685272e18c072..b21be367f8ef5e0d2afd089fd4fc398cfe802d80 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN ; This file tests the code generation for `llvm.round.*` on fixed vector type. diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll index 9976cd2a8ab29aedac1bcb17e0485db52f2186dd..37f2e59ad7516d035092c00980c9d4b927b5fadd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This file tests the code generation for `llvm.experimental.constrained.roundeven.*` on scalable vector type. diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll index 9607aa09d89d68051d77e5902334f850f8afefc6..13d62bb24441c9f3f0a86019fb3e45eba3e33c7a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN ; This file tests the code generation for `llvm.roundeven.*` on fixed vector type. diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll index eac26451d5a8cc3342d904d005300f63fbaae13c..b911722368ce3ae973da840f0cf472ab29232f76 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <1 x half> @trunc_v1f16(<1 x half> %x) strictfp { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll index 9cdc9b81c9530a66afd21028ce21c2b227e65b4a..29f8730021ce45b91bb8db8202c455e59454d278 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64 -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64 define void @si2fp_v2i32_v2f32(ptr %x, ptr %y) { ; CHECK-LABEL: si2fp_v2i32_v2f32: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll index 7853e91ca53a391c2e89c93d2e81503af0f0deb4..87f9bfbd1aaff7aafea867aa736da45b1324c562 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define <4 x i32> @insertelt_v4i32_0(<4 x i32> %a, i32 %y) { ; CHECK-LABEL: insertelt_v4i32_0: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll index 8de9cc25ae09aa0b4acc0964d123e7cb8eead885..7de9b59c6853f641e48d2df9ef3fbdedcab3187e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck %s ; Integers diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll index 3bf8d10654acd5450bede4ef6323a427d510397b..2fab2b76ee27a223bfc9d4097430004c71102f8d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load-store.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s define void @v2i8(ptr %p, ptr %q) { ; CHECK-LABEL: v2i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll index 22cde3c36ef619a9b6516afc79e3bdcb10fb75b0..8f1e026d09c0a2d64eac3ac2d3e58ceb8c941103 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s define <5 x i8> @load_v5i8(ptr %p) { ; CHECK-LABEL: load_v5i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll index 9c6ec6aef6034764b1a2d964dff7feaffce9e1f9..5802f45d311b37fde23b61a7fee7b8e92431b704 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+zve32f,+zvl128b -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zve32f,+zvl128b -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVE32F -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+zve32f,+zvl128b -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zve32f,+zvl128b -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE32F declare <1 x i8> @llvm.masked.gather.v1i8.v1p0(<1 x ptr>, i32, <1 x i1>, <1 x i8>) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll index 79b05334cb1f929901e35827eb909b2b0f792bb2..f1d300b300a64646c7eea9f89371ef7b8e98e233 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @masked_load_v1f16(ptr %a, ptr %m_ptr, ptr %res_ptr) nounwind { ; CHECK-LABEL: masked_load_v1f16: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll index 323f08acac28e36feb557c5f81ddbe7fe3691b63..a445c8fe081725b554408d697f3cfebbfbddabc9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+zve32f,+zvl128b -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zve32f,+zvl128b -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVE32F -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+zve32f,+zvl128b -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zve32f,+zvl128b -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64ZVE32F declare void @llvm.masked.scatter.v1i8.v1p0(<1 x i8>, <1 x ptr>, i32, <1 x i1>) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll index a1e81ea41c249b1982a5de6bc2efedf55a9a948e..80110b3eef4dd8a0056b3f5b27bd2d1165b0bbe3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half>* %m_ptr) nounwind { ; CHECK-LABEL: masked_store_v1f16: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll index 93b4f7d2a9c9fd644e50149d1a0bda66129412a6..3fab9ce63678687caa93d2152b8e347a5c4a4f8a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.nearbyint.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll index 6d5be7f14bf70b20751430510bb927c1c462611d..6684e6d223eac14a07885908f4d5146ae06f285d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare half @llvm.vp.reduce.fadd.v2f16(half, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll index 1f856d04ca89fd1d5388d1feba0c81c45af2718f..79dc2db8b16914d7bebb96f501e816338462b42a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.rint.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll index 0f587232680df670ada0a3c97625c09533774627..2228147176de52f9fd7105ae133b45fea3f5d856 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.round.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll index 0fb7e6a7de5696b0ab27012b9633a88297ba708b..336ffc8603fafa836c937b2ca398892fd3b2c4e4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.roundeven.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll index 927f96b6442274b8a0b8ffda10e5f1a70d05c3ad..9f7124f1e4d9f8beb00f4ca946344dae97e54c54 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.roundtozero.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll new file mode 100644 index 0000000000000000000000000000000000000000..4621f339ca88284509417889f468d4013fc14131 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-scalarized.ll @@ -0,0 +1,92 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s + +define <8 x float> @fpext_v8bf16(<8 x bfloat> %x) { +; CHECK-LABEL: fpext_v8bf16: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.x.w a0, fa0 +; CHECK-NEXT: fmv.x.w a1, fa1 +; CHECK-NEXT: fmv.x.w a2, fa2 +; CHECK-NEXT: fmv.x.w a3, fa3 +; CHECK-NEXT: fmv.x.w a4, fa4 +; CHECK-NEXT: fmv.x.w a5, fa5 +; CHECK-NEXT: fmv.x.w a6, fa6 +; CHECK-NEXT: fmv.x.w a7, fa7 +; CHECK-NEXT: slli a7, a7, 16 +; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-NEXT: vmv.s.x v8, a7 +; CHECK-NEXT: slli a6, a6, 16 +; CHECK-NEXT: vmv.s.x v9, a6 +; CHECK-NEXT: vslideup.vi v9, v8, 1 +; CHECK-NEXT: slli a5, a5, 16 +; CHECK-NEXT: vmv.s.x v8, a5 +; CHECK-NEXT: slli a4, a4, 16 +; CHECK-NEXT: vmv.s.x v10, a4 +; CHECK-NEXT: vslideup.vi v10, v8, 1 +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vslideup.vi v10, v9, 2 +; CHECK-NEXT: slli a3, a3, 16 +; CHECK-NEXT: vmv.s.x v8, a3 +; CHECK-NEXT: slli a2, a2, 16 +; CHECK-NEXT: vmv.s.x v9, a2 +; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-NEXT: vslideup.vi v9, v8, 1 +; CHECK-NEXT: slli a1, a1, 16 +; CHECK-NEXT: vmv.s.x v11, a1 +; CHECK-NEXT: slli a0, a0, 16 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vslideup.vi v8, v11, 1 +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vslideup.vi v8, v9, 2 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-NEXT: vslideup.vi v8, v10, 4 +; CHECK-NEXT: ret + %y = fpext <8 x bfloat> %x to <8 x float> + ret <8 x float> %y +} + +define <8 x float> @fpext_v8f16(<8 x bfloat> %x) { +; CHECK-LABEL: fpext_v8f16: +; CHECK: # %bb.0: +; CHECK-NEXT: fmv.x.w a0, fa0 +; CHECK-NEXT: fmv.x.w a1, fa1 +; CHECK-NEXT: fmv.x.w a2, fa2 +; CHECK-NEXT: fmv.x.w a3, fa3 +; CHECK-NEXT: fmv.x.w a4, fa4 +; CHECK-NEXT: fmv.x.w a5, fa5 +; CHECK-NEXT: fmv.x.w a6, fa6 +; CHECK-NEXT: fmv.x.w a7, fa7 +; CHECK-NEXT: slli a7, a7, 16 +; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-NEXT: vmv.s.x v8, a7 +; CHECK-NEXT: slli a6, a6, 16 +; CHECK-NEXT: vmv.s.x v9, a6 +; CHECK-NEXT: vslideup.vi v9, v8, 1 +; CHECK-NEXT: slli a5, a5, 16 +; CHECK-NEXT: vmv.s.x v8, a5 +; CHECK-NEXT: slli a4, a4, 16 +; CHECK-NEXT: vmv.s.x v10, a4 +; CHECK-NEXT: vslideup.vi v10, v8, 1 +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vslideup.vi v10, v9, 2 +; CHECK-NEXT: slli a3, a3, 16 +; CHECK-NEXT: vmv.s.x v8, a3 +; CHECK-NEXT: slli a2, a2, 16 +; CHECK-NEXT: vmv.s.x v9, a2 +; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-NEXT: vslideup.vi v9, v8, 1 +; CHECK-NEXT: slli a1, a1, 16 +; CHECK-NEXT: vmv.s.x v11, a1 +; CHECK-NEXT: slli a0, a0, 16 +; CHECK-NEXT: vmv.s.x v8, a0 +; CHECK-NEXT: vslideup.vi v8, v11, 1 +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma +; CHECK-NEXT: vslideup.vi v8, v9, 2 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma +; CHECK-NEXT: vslideup.vi v8, v10, 4 +; CHECK-NEXT: ret + %y = fpext <8 x bfloat> %x to <8 x float> + ret <8 x float> %y +} + diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll index cbf9829826fb61db5d9f9b8e722d7bbfc70ae68a..f5c45ba9ea58177bb4392aede834248ae00cf9cc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,NO-ZVBB,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV32-ZVBB +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVBB,RV64-ZVBB define <2 x i1> @reverse_v2i1(<2 x i1> %a) { ; NO-ZVBB-LABEL: reverse_v2i1: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll index dffe0e0646ecc463efa2cf02c3c38a5612d2b495..814e35f201dca6910e8923dcfd0279f2afe83fe7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll index ff5f6960ed4e4d6ddeeb307d3bacc9e1ce6277ff..f531ff3a835e459583c26ba977b995485dc923b8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1down.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll index e0b2dd1af918357221bf18cd54ea71080997b6c9..b3390b6eeeccdbfe4faaf63c05b3c5226ea69f47 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll index 4ef65032469e418ebe37bb02239ea5a1bf58a989..a3e50685889d18a2ed3b24ef0e18f9392488a870 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+zvl256b \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvl256b \ ; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \ ; RUN: | FileCheck %s --check-prefixes=CHECK,V -; RUN: llc < %s -mtriple=riscv64 -mattr=+f,+zve32f,+zfh,+zvfh,+zvl256b \ +; RUN: llc < %s -mtriple=riscv64 -mattr=+f,+zve32f,+zvfh,+zvl256b \ ; RUN: -lower-interleaved-accesses=false -verify-machineinstrs \ ; RUN: | FileCheck %s --check-prefixes=CHECK,ZVE32F diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll index 67c045cc2b1899457230efe2a3122f4b26e844ce..a1390a8b1c0ded03baa73be292ac7e031a84328c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp-mask.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s declare <4 x half> @llvm.vp.sitofp.v4f16.v4i1(<4 x i1>, <4 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll index bf0eab77d0ac833b726f4910fc136edde649645f..a2d41de5d1853376c779ac2f572d4d0cbc403fd8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin < %s | FileCheck %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN declare <4 x half> @llvm.vp.sitofp.v4f16.v4i7(<4 x i7>, <4 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll index 169d99abb13c226f615cf13bde314d2eb7265604..5232d0d69fad08377297e00553077e4557eeb6dc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s define void @store_v5i8(ptr %p, <5 x i8> %v) { ; CHECK-LABEL: store_v5i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll index b49e323478e8ca13a823b4158b33632b77332302..ed72883e9d0523d4fa29b2b3da023f950d038449 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,RV64 -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+unaligned-vector-mem -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64,RV64-MISALIGN +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,RV64 +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+unaligned-vector-mem -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64,RV64-MISALIGN ; RUN: llc -mtriple=riscv64 -mattr=+f,+zfh,+zve64f,+zvl128b,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,CHECK-NO-MISALIGN,ZVE64F diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll index adfb26cd31060c21fbe07f40da645d733ae18be2..e625c46a57145643942659af66f0aec4be1c9f6d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp-mask.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s | FileCheck %s declare <4 x half> @llvm.vp.uitofp.v4f16.v4i1(<4 x i1>, <4 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll index e28d55f46abcbb1216ea0b940daa80757cffff59..a0d5d2ccc848d77c3ea342c03dc03b7132f406a5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <4 x half> @llvm.vp.uitofp.v4f16.v4i7(<4 x i7>, <4 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll index 77a095303675f595a0162b3258627ad85a62c922..f1dc476e5a4309a7b68d10937486ab2cb22c622c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.copysign.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll index 90a856605c70d8fe836779a9a5182a78619f09fc..08f486b601328fa857e50409d156912ef97af196 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.fabs.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll index 441cbebf5675729f5abea7a4074e53050ffb8c01..599f505808ab4789545e54d6574a88afd574e2c0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half>, <2 x half>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll index 09b9e7ce4c53dbf37372c1162503c93c9d9cbc6c..690c8af7fc8e7b1609c179aeef6b31985c3403f8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <2 x i1> @isnan_v2f16(<2 x half> %x, <2 x i1> %m, i32 zeroext %evl) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll index a1c36db5cfc318e9d799b9b1f8f845e3eb12aaf7..85e8638301ded8e84af3ea469ac1d11df41175b5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <2 x i1> @isnan_v2f16(<2 x half> %x) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll index 1a75c50f2b646f1f3f2cb536b32cf6038fca7bf7..4e9862b05f408987da07333d63ee55a6870655ae 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmp-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <1 x i1> @llvm.experimental.constrained.fcmp.v1f16(<1 x half>, <1 x half>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll index 83037baf3fabcfd7f1e7c51f6c1761e5e3ff9af5..97641ff6d92d7046219c084e4dbd5888d845c77d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <1 x i1> @llvm.experimental.constrained.fcmps.v1f16(<1 x half>, <1 x half>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll index fb9612d09504019faa326f26ff535953578e3eb6..1bc880d93af1a6a6244c8124e5cce2c5064f3eba 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.experimental.constrained.fdiv.v2f16(<2 x half>, <2 x half>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll index 2d6e1fd02dee5724ce0ebbf8192086f805ce623a..bc13e1d217a9b01171ca615990294ddd104a7683 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmacc-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll index 52d96fc63fadfcc49b01fa975908332329cf3a16..b8f3f0fef04198f1781963275f19ac89ba5f8ee9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmadd-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfmacc and vfmadd by using different operand orders to diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll index c83a298cb501eed1ddbec225ab17b9b4ddb3efbe..1f3c7a915d8484d3353196023b037a8245be1289 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.maxnum.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll index 60dbededb90a5c3a03f4bb7c54b08a4ca724a32f..a3dbd33451374fdc6591e6ac1a611d5f118bb237 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.minnum.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll index fc6578225aa647a2c4d9dd4be3a3cab59e97ce75..99fc0352356713fdb09e159b0f506b092a8fb634 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsac-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll index 652198b0d4469b6c592ce1fa70d2380c6166a05e..268494bf337e1f58b037c5d56c87516da2d54e0a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmsub-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfmsac and vfmsub by using different operand orders to diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll index d5e96c88f9388771f31a919d49aaf8df33bb9b2f..c8148a5e8d49cb1300cc20946cb0ac9b52c2e7d9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <1 x half> @llvm.experimental.constrained.fmul.v1f16(<1 x half>, <1 x half>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll index 6af0147300bda6eeb3a8c192c6077159fb88d4c9..699788abfa86c996212094d51de67844ad6660a0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fmuladd.v2f16(<2 x half>, <2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll index 019923ffdfdedf73ed28d1001d020eab811e92f6..968fd9f9bab80694ad7f0af283e00fb31c4a27e2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.fneg.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll index 6d65ab4083f7ced816c31cbe8f48610e361e8892..4ab94444b1b89cd3b010335436685267af410155 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmacc-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll index b7f5dd49b3508c437412a373407f2bcb4ee7100f..afc89717596b2da61ca21958e344e5f195dbb471 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmadd-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfnmacc and vfnmadd by using different operand orders to diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll index df705270664bc573b0293f18707ac95179154a44..4d9b002cc785c9c44dd65eeefaa9e883d9b26fbd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsac-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll index ace96c1a571d1de1bb2cddc2e6a8b56af0ffe942..d9863bb36c739e0b34d8f91fad5597283c92bfc0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfnmsub-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfnmsac and vfnmsub by using different operand orders to diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll index 5321f731441e3eee8a26d952243c37868c58bf40..59fd8bbd179535fa0cfa3adb46b798bcad993a09 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfpext-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x float> @llvm.experimental.constrained.fpext.v2f32.v2f16(<2 x half>, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll index 4ac72bf0a3b00cd6e4f2e1096d6cf5160b0019f6..1f74691437ad27469e72c6b8d2728c4c9793036c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptrunc-constrained-sdnode.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x float> @llvm.experimental.constrained.fptrunc.v2f32.v2f64(<2 x double>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll index bd354b7dae80378e504973d751f4abbf18c5f73a..fb813d4381a7d97f82d935b908a2dd682f74b654 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fdiv.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll index 0903ef8c8ec3fe2d014540e420327185597e2173..63c2d1f2e7db3ba0fd3b1c2782b2161d2de3d724 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.vp.fsub.v2f16(<2 x half>, <2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll index 9f29d14050de7845a4642cba6bb0e634c8dc773e..62d03e1ab588a433f6f53dc8c383004dc70bb729 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.experimental.constrained.sqrt.v2f16(<2 x half>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll index 988b200ae53656ed86a37fb658fc3123c59afaff..c1e63cbf0b138ff2504166eca38459a1f1ccad29 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare <2 x half> @llvm.vp.sqrt.v2f16(<2 x half>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll index f9d40d7a117b5e959bd4a97bf04ffda0379dc2e5..e6001352a237b80596fe179620140d4bb85923b0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half>, <2 x half>, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll index cb50ca4a721207a4b8cb7c335ca7003d6632749f..1144f776e7fbfc935e03c3fc4e74c7d34fe28ee8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfw-web-simplification.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=1 | FileCheck %s --check-prefixes=NO_FOLDING -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=2 | FileCheck %s --check-prefixes=NO_FOLDING -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=3 | FileCheck %s --check-prefixes=FOLDING,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=3 | FileCheck %s --check-prefixes=FOLDING,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=1 | FileCheck %s --check-prefixes=NO_FOLDING +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=2 | FileCheck %s --check-prefixes=NO_FOLDING +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=3 | FileCheck %s --check-prefixes=FOLDING,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+f,+d -verify-machineinstrs %s -o - --riscv-lower-ext-max-web-size=3 | FileCheck %s --check-prefixes=FOLDING,ZVFHMIN ; Check that the default value enables the web folding and ; that it is bigger than 3. -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=FOLDING +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=FOLDING define void @vfwmul_v2f116_multiple_users(ptr %x, ptr %y, ptr %z, <2 x half> %a, <2 x half> %b, <2 x half> %b2) { ; NO_FOLDING-LABEL: vfwmul_v2f116_multiple_users: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll index afea1dc6d3c2a3429d1928de531073de671e4b1e..4bd521725f488ae906b1c49cfbacb853a4f2d176 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwadd.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+f,+d -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+f,+d -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+f,+d -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <2 x float> @vfwadd_v2f16(ptr %x, ptr %y) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll index 5140d89b78307a752ec33f221b7b66e9a787cecc..a48be7687106e493bc80038fd40879125b791d9c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <1 x float> @llvm.fma.v1f32(<1 x float>, <1 x float>, <1 x float>) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll index 319994d2655651fda419c1cd3595a018df805e26..84c126217789136fd085f16f16e1eea884fcb9b2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmul.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+f,+d -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+f,+d -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+f,+d -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <2 x float> @vfwmul_v2f16(ptr %x, ptr %y) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll index 2c706cad9742ff8e95aa0dbe1233cd98952a407c..b8b26a4d5adf0f22a05682b796eb9c9df0cc5038 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwsub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+f,+d -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+f,+d -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+f,+d -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+f,+d -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define <2 x float> @vfwsub_v2f16(ptr %x, ptr %y) { diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll index 3dec7daf66ac9c8e15b8b09030fad01db2b1549b..5eb54fc7e299a8582626a8dd665ae3c9226a78ce 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vitofp-constrained-sdnode.ll @@ -412,30 +412,20 @@ declare <1 x half> @llvm.experimental.constrained.sitofp.v1f16.v1i7(<1 x i7>, me define <1 x half> @vsitofp_v1i7_v1f16(<1 x i7> %va) strictfp { ; RV32-LABEL: vsitofp_v1i7_v1f16: ; RV32: # %bb.0: -; RV32-NEXT: addi sp, sp, -16 -; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: slli a0, a0, 25 ; RV32-NEXT: srai a0, a0, 25 ; RV32-NEXT: fcvt.h.w fa5, a0 -; RV32-NEXT: fsh fa5, 14(sp) -; RV32-NEXT: addi a0, sp, 14 -; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; RV32-NEXT: vle16.v v8, (a0) -; RV32-NEXT: addi sp, sp, 16 +; RV32-NEXT: vsetivli zero, 1, e16, m1, ta, ma +; RV32-NEXT: vfmv.s.f v8, fa5 ; RV32-NEXT: ret ; ; RV64-LABEL: vsitofp_v1i7_v1f16: ; RV64: # %bb.0: -; RV64-NEXT: addi sp, sp, -16 -; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: slli a0, a0, 57 ; RV64-NEXT: srai a0, a0, 57 ; RV64-NEXT: fcvt.h.w fa5, a0 -; RV64-NEXT: fsh fa5, 14(sp) -; RV64-NEXT: addi a0, sp, 14 -; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; RV64-NEXT: vle16.v v8, (a0) -; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: vsetivli zero, 1, e16, m1, ta, ma +; RV64-NEXT: vfmv.s.f v8, fa5 ; RV64-NEXT: ret %evec = call <1 x half> @llvm.experimental.constrained.sitofp.v1f16.v1i7(<1 x i7> %va, metadata !"round.dynamic", metadata !"fpexcept.strict") ret <1 x half> %evec @@ -445,15 +435,10 @@ declare <1 x half> @llvm.experimental.constrained.uitofp.v1f16.v1i7(<1 x i7>, me define <1 x half> @vuitofp_v1i7_v1f16(<1 x i7> %va) strictfp { ; CHECK-LABEL: vuitofp_v1i7_v1f16: ; CHECK: # %bb.0: -; CHECK-NEXT: addi sp, sp, -16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: andi a0, a0, 127 ; CHECK-NEXT: fcvt.h.wu fa5, a0 -; CHECK-NEXT: fsh fa5, 14(sp) -; CHECK-NEXT: addi a0, sp, 14 -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma -; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: addi sp, sp, 16 +; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma +; CHECK-NEXT: vfmv.s.f v8, fa5 ; CHECK-NEXT: ret %evec = call <1 x half> @llvm.experimental.constrained.uitofp.v1f16.v1i7(<1 x i7> %va, metadata !"round.dynamic", metadata !"fpexcept.strict") ret <1 x half> %evec diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll index a31405f75e8a4e685c9f46bdbfd7f3df7ffaa426..2e3e36e45d5714a14070903e551a1658cc111c18 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splat.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 define <1 x i8> @vp_splat_v1i8(i8 %val, <1 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_splat_v1i8: diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll index 028fb9a626f02d018c10172cffed7330696af0fd..f66974e511406766db4bdf8cbacf90af1233841d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare <2 x i8> @llvm.vp.gather.v2i8.v2p0(<2 x ptr>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll index f204d812c14f6850c7411f58f9bf314744d293be..351d7d4cd9b09bf4d0f74ec12097ad450f1e545f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <2 x i8> @llvm.vp.load.v2i8.p0(ptr, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll index c0550398761915edadd45e008af17196cd66e22c..0a61bc42326f48901909548d0eb9189fa6c2b10c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare void @llvm.vp.scatter.v2i8.v2p0(<2 x i8>, <2 x ptr>, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll index f396790f4f1783af43af1a9788d4308309e52103..d34292abdce0d5306246e7064cbcd14a94b11e83 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.vp.store.v2i8.p0(<2 x i8>, ptr, <2 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll index 0a2ed3eb1ffbf7b46e414d0e29239aab35999e24..99aafdbcde127fc8f2b15895fb069af6a63ee87a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare <1 x i1> @llvm.vp.select.v1i1(<1 x i1>, <1 x i1>, <1 x i1>, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll index 2194651a95e54f8fb0a8bb12716c6e2500a3072f..a3bba2dd8265c03f78dc6ac586da04a1fe1ed846 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 +; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV32 +; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK,RV64 define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) { ; RV32-LABEL: vselect_vv_v6i32: diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll index 03d1fb6c8d297fc219ff0aed4314447b42503fc5..40c855b5d04516b9318ecab17acf131a77cdb5f8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll index a8995fca23cb7ba8b35463658dcfe838f96225cc..ecc36340a282ccd9945c1737d0a2b87dfd19accd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll @@ -1,19 +1,19 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare @llvm.maximum.nxv1bf16(, ) diff --git a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll index dd01e1c1ee66d07b1e7979a1e1255267d46d3d12..7b70a0daf11c87166006d202fc1210f3ec78bc37 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 \ -; RUN: -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \ +; RUN: -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN ; RUN: llc -mtriple=riscv64 \ -; RUN: -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \ +; RUN: -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll index 1c6a29f16a9fee243347c310af1f39c436989b0b..fad3eab97f468d43a8c7f7141c6320931af74f59 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll @@ -1,19 +1,19 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN declare @llvm.minimum.nxv1bf16(, ) diff --git a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll index 85cac8d187059460b44e89469e462994df96c340..2526b87651779e955745c5d4171cfea03947adfc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v,+m \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 \ -; RUN: -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \ +; RUN: -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN ; RUN: llc -mtriple=riscv64 \ -; RUN: -mattr=+d,+zfh,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \ +; RUN: -mattr=+d,+zvfhmin,+zfbfmin,+zvfbfmin,+v,+m \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll index 372937bb5ca5df624c57ec5c90bbfba122754aa3..f22cd77db7a40b4e16f1814a374d233c33dc46c0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.experimental.constrained.nearbyint.nxv1f16(, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll index 9498c65ba9a1764df415110dfe0f5cf8ff771d0d..89769615365cacb340f46136bdeb546ccbb2422c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll index adfae5ede7bb59a480d7b9ee1e5757c98aaaa21f..5bc1ab9820d6cc517909f0e6e6ee4f179d2a5392 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zbb -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zbb -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s define i64 @reduce_add(i64 %x, <4 x i64> %v) { ; CHECK-LABEL: reduce_add: diff --git a/llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll b/llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll index 393cd5c7f52e2fe0c69f22be131c06fa668d3806..52e5ecf9cb8a1130275a022e97f5d4cbc24d8917 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; Float diff --git a/llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll b/llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll index a7efa4b3de940109cfb92591e70641b05dcea1b7..02b43c2d95295156574632f5496743ebb1a46bae 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK64 ; Float diff --git a/llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll index ee1d1b8e29e7abef24a31a20b1825acf8af1975f..262e59bb8081d252cbd6c21f9ddcd4f2c9255757 100644 --- a/llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll b/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll index ccfe94ecad286b7fe684ddfded703bfffadd7338..54f56eadf0034262de70eff1c32c1a9f998957d5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/frm-insert.ll @@ -559,7 +559,7 @@ define @after_fsrm3( %0, @after_fsrm3( %0, undef, %0, %1, - i64 5, i64 %2) + i64 3, i64 %2) ret %a } diff --git a/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll index aaa7a538e70fb706f7f5b1db28e3088cf534ebf7..095f44cfb63e40e6fc03d2dc78e679d09cd01929 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fround-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This file tests the code generation for `llvm.experimental.constrained.round.*` on scalable vector type. diff --git a/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll index 193773b0c89c9a540cd6efc0fa74f6970c90c998..fd834e9eb5275c3dc64427738543dc2d2f15e44a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll index cdc01d658778bc4d599dcc221e21e601ef8d069d..051939d988f85786b4f3a6cc804eacaf47fc5ce9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This file tests the code generation for `llvm.experimental.constrained.roundeven.*` on scalable vector type. diff --git a/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll index 052ee2d3a43cf23474db81fa437910b29dd17bf2..85146588246780c6dc420d74706c01caf16afa99 100644 --- a/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll index 21615b516da898601fb5d94fce71a6521b56f9e9..d07bc2c6bf74d7098f557e2bc1ff4e17c5e267f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @trunc_nxv1f16( %x) strictfp { diff --git a/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll index b29b24a9ce7b2503d65ac89927fa47397f2c270b..2b3c952679eac66a2cd38782a1890d6265897d1b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll index 5cd9996c7ba3bd951d17d6c3fb4c2a4a5e5d5250..4d47c265a97471917c571d8965662abb8d685a35 100644 --- a/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zfh,+zvfh,+v -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=riscv32 -mattr=+zvfh,+v -verify-machineinstrs < %s | \ ; RUN: FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+zfh,+zvfh,+v -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=riscv64 -mattr=+zvfh,+v -verify-machineinstrs < %s | \ ; RUN: FileCheck %s ; ================================================================================ diff --git a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll index 71f90153b2124a34c528f44a37fc573d5fe2ae51..e2298774a9b8d49e3a9fd8f888c9482aa00e840f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s define @insert_nxv8i32_nxv4i32_0( %vec, %subvec) { ; CHECK-LABEL: insert_nxv8i32_nxv4i32_0: diff --git a/llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll index eada90e055df9692867ff86745cebd84bca76118..e9e1303d10768b103d7f16ad6a7a6171f1b2e901 100644 --- a/llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s ; Check that we are able to legalize scalable-vector loads that require widening. diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll b/llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll index 9c7ad239bcade3f312debeee58c5e7033a15275b..c301d4975e7139f317b10a90867d86f4d43b2ec1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s define @masked_load_nxv1bf16(ptr %a, %mask) nounwind { ; CHECK-LABEL: masked_load_nxv1bf16: diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll b/llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll index ddb56e0d979a1c633bf67bd7ae77bade5077e45e..586af50266f9454efe30be11fb223ccfedfab5f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s define void @masked_store_nxv1bf16( %val, ptr %a, %mask) nounwind { ; CHECK-LABEL: masked_store_nxv1bf16: diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll index 5c14ed1e813c0ed01ea018c05dd00a52b549fa06..420597b009f33fb481cc677be446212a926439cd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.riscv.vle.mask.nxv1i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll index 4098270d365a9c6696b89f41f4ebfebf54452a2b..0e771eb7c43156bdb742973ae9fe00e06c6b74a7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.riscv.vle.mask.nxv1i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll index 4cd7e143be66cda0eea243d95f072652ec4ac8e8..c4c2fc88913bbd897b6f696da99831b53410a673 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.riscv.vle.mask.nxv1i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll index c8719e6a2e7c36de402619d803662f3595b2bd1a..ec0ebb10e8f7a681c082d311750a60fc5938b6eb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh\ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh\ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.riscv.vle.mask.nxv1i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll index 189ba08dddc7aa1c282454132e5216e24d2f5335..9f6fc3b5d7d1090f37e6122411f88437a4e43c05 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV64 diff --git a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll index 29db67b4b0a41f4175f2e9416907f385bc181bf0..f75f8dfedc5436ba6440fe892801719c06790450 100644 --- a/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV32 -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,RV64 diff --git a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll index a6c6db345032ec66418f77c5bbb06c3b53ba1373..20296c09998b8159e2c1b6f0224a3429d208c354 100644 --- a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll @@ -1,16 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-UNKNOWN -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-256 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-512 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-UNKNOWN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-256 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-512 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-UNKNOWN -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-256 -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zfh,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-512 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-UNKNOWN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-256 -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zfh,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-512 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-UNKNOWN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-256 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-512 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-UNKNOWN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-256 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfh,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-512 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-UNKNOWN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-256 +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-BITS-512 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-UNKNOWN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=256 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-256 +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+f,+d,+zvfhmin,+zvfbfmin -riscv-v-vector-bits-max=512 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-BITS-512 ; ; VECTOR_REVERSE - masks diff --git a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll index 5aa773b01e6926ccb3c016e5c27d4b2f619dceef..12c7b9cf13e1159618dcd78dbf8077421bef8382 100644 --- a/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/pr63596.ll b/llvm/test/CodeGen/RISCV/rvv/pr63596.ll index 8bb62eaa8e9e9403fbb7981b0392837d7801fb48..dbd4224c7ef084611a7274cf93c406513b6c7089 100644 --- a/llvm/test/CodeGen/RISCV/rvv/pr63596.ll +++ b/llvm/test/CodeGen/RISCV/rvv/pr63596.ll @@ -9,36 +9,54 @@ define <4 x float> @foo(ptr %0) nounwind { ; CHECK-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 16(sp) # 8-byte Folded Spill +; CHECK-NEXT: csrr a1, vlenb +; CHECK-NEXT: slli a1, a1, 1 +; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: lhu s0, 0(a0) ; CHECK-NEXT: lhu s1, 2(a0) ; CHECK-NEXT: lhu s2, 4(a0) ; CHECK-NEXT: lhu a0, 6(a0) ; CHECK-NEXT: fmv.w.x fa0, a0 ; CHECK-NEXT: call __extendhfsf2 -; CHECK-NEXT: fsw fa0, 4(sp) -; CHECK-NEXT: fmv.w.x fa0, s2 +; CHECK-NEXT: fmv.w.x fa5, s2 +; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; CHECK-NEXT: vfmv.s.f v8, fa0 +; CHECK-NEXT: addi a0, sp, 16 +; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: fmv.s fa0, fa5 ; CHECK-NEXT: call __extendhfsf2 -; CHECK-NEXT: fsw fa0, 12(sp) +; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-NEXT: vfmv.s.f v8, fa0 +; CHECK-NEXT: addi a0, sp, 16 +; CHECK-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload +; CHECK-NEXT: vslideup.vi v8, v9, 1 +; CHECK-NEXT: csrr a0, vlenb +; CHECK-NEXT: add a0, sp, a0 +; CHECK-NEXT: addi a0, a0, 16 +; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: fmv.w.x fa0, s1 ; CHECK-NEXT: call __extendhfsf2 -; CHECK-NEXT: fsw fa0, 8(sp) -; CHECK-NEXT: fmv.w.x fa0, s0 +; CHECK-NEXT: fmv.w.x fa5, s0 +; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma +; CHECK-NEXT: vfmv.s.f v8, fa0 +; CHECK-NEXT: addi a0, sp, 16 +; CHECK-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill +; CHECK-NEXT: fmv.s fa0, fa5 ; CHECK-NEXT: call __extendhfsf2 -; CHECK-NEXT: fsw fa0, 0(sp) -; CHECK-NEXT: addi a0, sp, 4 -; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-NEXT: vle32.v v9, (a0) -; CHECK-NEXT: addi a0, sp, 12 -; CHECK-NEXT: vle32.v v10, (a0) -; CHECK-NEXT: addi a0, sp, 8 -; CHECK-NEXT: vle32.v v11, (a0) -; CHECK-NEXT: mv a0, sp -; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-NEXT: vslideup.vi v10, v9, 1 -; CHECK-NEXT: vslideup.vi v8, v11, 1 +; CHECK-NEXT: vfmv.s.f v8, fa0 +; CHECK-NEXT: addi a0, sp, 16 +; CHECK-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload +; CHECK-NEXT: vslideup.vi v8, v9, 1 +; CHECK-NEXT: csrr a0, vlenb +; CHECK-NEXT: add a0, sp, a0 +; CHECK-NEXT: addi a0, a0, 16 +; CHECK-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; CHECK-NEXT: vslideup.vi v8, v10, 2 +; CHECK-NEXT: vslideup.vi v8, v9, 2 +; CHECK-NEXT: csrr a0, vlenb +; CHECK-NEXT: slli a0, a0, 1 +; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 24(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll index a454f9dd97cebf91659871ff8e752e63b443bba8..7b6027991c3206ce7540f9afe90d3dc2ae13214d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rint-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll index a4936483e8a1525b56bad151c69a66b5264f6a4b..6f5c1eab7f07a64952c69e5a3d009f2c5c517f41 100644 --- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll index 9857009002eb90489e2b9a3d71ada40d9f189e19..447962a7542f1dccd3c77edca6bfde54431d5000 100644 --- a/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll index 11830c924867b46f71af3aa6c16ff1ebf8f230b7..7249069294c46403065096f3c38b70e838651bc6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll index 5ba4efa8458c79f367de53f1f21fef77a2f43b7c..3e6f8953a515f9f530464aaa3d1890bb8853fb0e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll index 3c19616576f55dbf1ec575cc6eb8af7f447bb654..fbe1a97c201cf38bd5a2a8919a37ddbafed82b13 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll @@ -13,10 +13,8 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: sf.vfnrclip.x.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -24,7 +22,7 @@ entry: undef, %0, float %1, - iXLen 0, iXLen %2) + iXLen 7, iXLen %2) ret %a } diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll index dbcee311c6e35fb098853ed10fc094137dd6e6d5..dfb0ccd982e845e19069b89a8de49f85d15de86c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll @@ -13,10 +13,8 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -24,7 +22,7 @@ entry: undef, %0, float %1, - iXLen 0, iXLen %2) + iXLen 7, iXLen %2) ret %a } diff --git a/llvm/test/CodeGen/RISCV/rvv/splat-vectors.ll b/llvm/test/CodeGen/RISCV/rvv/splat-vectors.ll index 8e422fa6f76b37ae6fe1e7c323ab9cc07db59160..2e6df118401792f71c9482b6af28b0f5f9484bb2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/splat-vectors.ll +++ b/llvm/test/CodeGen/RISCV/rvv/splat-vectors.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+zvfh -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zvfh -verify-machineinstrs < %s | FileCheck %s define @splat_c3_nxv4i32( %v) { ; CHECK-LABEL: splat_c3_nxv4i32: diff --git a/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll b/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll index 1491bb6c337a029df69607e8da1ae31cfdbc43a5..b5613a4a635883e42115885f1b64c9be388cb005 100644 --- a/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll +++ b/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple riscv32 -mattr=+d,+zfh,+zvfh,+v < %s \ +; RUN: llc -mtriple riscv32 -mattr=+d,+zvfh,+v < %s \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: llc -mtriple riscv64 -mattr=+d,+zfh,+zvfh,+v < %s \ +; RUN: llc -mtriple riscv64 -mattr=+d,+zvfh,+v < %s \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: llc -mtriple riscv32 -mattr=+d,+zfh,+zvfh,+v,+unaligned-vector-mem < %s \ +; RUN: llc -mtriple riscv32 -mattr=+d,+zvfh,+v,+unaligned-vector-mem < %s \ ; RUN: -verify-machineinstrs | FileCheck --check-prefix=FAST %s -; RUN: llc -mtriple riscv64 -mattr=+d,+zfh,+zvfh,+v,+unaligned-vector-mem < %s \ +; RUN: llc -mtriple riscv64 -mattr=+d,+zvfh,+v,+unaligned-vector-mem < %s \ ; RUN: -verify-machineinstrs | FileCheck --check-prefix=FAST %s diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll b/llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll index 1bfc0f432eb55e64c1b9b352da6f988c585cba7f..6b0abeef657ebb5468548233e310ae306c5aa365 100644 --- a/llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; Test that we can remove trivially-undef VP operations of various kinds. diff --git a/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll b/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll index bcc7bb9f072f6d28bb539792853671c28d8a18d7..8640b61e6462893e82efbbba8deb3e0c71c439dc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll +++ b/llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.riscv.vfmacc.nxv1f32.nxv1f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll b/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll index aeb3f6c174859c4ec874279ecfb248afb8bf43ed..3052108a12e3e981c1570330258405fabf4f9184 100644 --- a/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.riscv.vle.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vcompress.ll b/llvm/test/CodeGen/RISCV/rvv/vcompress.ll index b763e116a9f62e5dfab376f6f2446f001a12342b..5ee82e6d95d4dc5f7a85a98b205c7dc8854b4009 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vcompress.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vcompress.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin,+zvfbfmin \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin,+zvfbfmin \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vcompress.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll index e8a7d79075859698974fbce107ea46f3d1f31a94..ccf82b93d6b753dcee15b9b4e36fed5d1dc65b48 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll index eb02fd895f18d7ceeaec72c1ec61590212d7f164..4fed94401f0acda5aa3f02e85d9522b21d882bd1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck %s ; Integers diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll index 54373d94f8f5f3a9e5e45a2184884db40e463c67..2521e4d707b1fda2d3ce07141c959b7681f5ca23 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+m | FileCheck --check-prefixes=CHECK,RV32 %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+m | FileCheck --check-prefixes=CHECK,RV64 %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+m | FileCheck --check-prefixes=CHECK,RV32 %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+m | FileCheck --check-prefixes=CHECK,RV64 %s ; Integers diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll index 28f7eb4329e3b90ff0b9f74468932390863356e5..14fe477f537cf6d929fc69b0f7d0f2018a561a76 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin | FileCheck %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin | FileCheck %s -; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin | FileCheck %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin | FileCheck %s ; Integers diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll index 99872c199a1e0d7bc60e243a10d8c5d6f5e7f251..e730ae230d5a0d615cd60668681bd8e95da5823f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV32 %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV64 %s -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zfh,+zvfh | FileCheck %s --check-prefix=ZVBB +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck -check-prefixes=CHECK,RV32 %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck -check-prefixes=CHECK,RV64 %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh | FileCheck %s --check-prefix=ZVBB ; Integers diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll index a06aa2d02b11b58007542ff1506d8b0ec027e5c8..8fc6bb6e2b7ac3fdf718bdad976effff582a4e42 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck --check-prefixes=CHECK,RV32 %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck --check-prefixes=CHECK,RV64 %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh | FileCheck --check-prefixes=CHECK,RV32 %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh | FileCheck --check-prefixes=CHECK,RV64 %s ; Integers diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll index 83c235d8e87ab717934c6591010e2c9060450737..362d8a8f372d8612450d4d459118a85cbbd319ff 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll @@ -1,10 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+zvfbfmin | FileCheck %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+zvfbfmin | FileCheck %s -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin,+zvfbfmin | FileCheck %s -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin,+zvfbfmin | FileCheck %s -; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zfh,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB -; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zfh,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfh,+zvfbfmin | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin | FileCheck %s +; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB +; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zvbb,+zvfh,+zvfbfmin | FileCheck %s --check-prefix=ZVBB ; Integers diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll index c8313c902697bc0e52a87658f01fa6e5f47f0f96..1d8638844af7f990a39addd1fb82c848d125c04c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll index b9be6eb1fa3737b20cab428128c4b5f0f9b74324..42b71d412fde4df0c404c18e225c83814c7da2bc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll index 53be153f8ff2dac14cfc343c5fe2288a3cecae5b..c6c92db62bf694f006d6cec38265c738fb5b1bf0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-constrained-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll index c3c0958f7096d91555755de960a080cff3f8b7a8..53a13b511a799e60904a01f8decd7342064ab24e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll index 4c298ab2b5e6dbca2e5769606de3946961d62f5f..00ff3456a8e2d86798cee90dd88d2c54b713560a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfadd.ll index ae7d7d5d19627facf1106e781270ef65c3e97ad7..e5f7545eea6faf3a0df036473c566f442ab8e114 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfadd.ll @@ -1,15 +1,15 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfhmin,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfhmin,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s -; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \ +; RUN: sed 's/iXLen/i32/g' %s | not --crash llc -mtriple=riscv32 -mattr=+v,+zvfhmin \ ; RUN: -target-abi=ilp32d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN -; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \ +; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 -mattr=+v,+zvfhmin \ ; RUN: -target-abi=lp64d 2>&1 | FileCheck %s --check-prefixes=ZVFMIN ; ZVFMIN: LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vfadd diff --git a/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll index c97278480f1a81f3e684f03435f2852ee7815d6d..862a8355d43218c2086864017e7a78713700b9d6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll index be2d576597da232dd7d070aadddffdabcef6aae1..36e1bea1f999468a771fbc70bca08038552c22dd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfclass-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @isnan_nxv2f16( %x, %m, i32 zeroext %evl) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vfclass.ll b/llvm/test/CodeGen/RISCV/rvv/vfclass.ll index 7c7cdab19aaead15781c625c3d8d1e631189cbb4..293300bd8dd69801f22e47482ea23bff9798a4e0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfclass.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfclass.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfclass.nxv1i16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll index 1cc9ea029d45748d7722391bd2dd12683d4de203..21c5f757e4558d0b56d79853c0f8de01dfa61d88 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcmp-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.experimental.constrained.fcmp.nxv1f16(, , metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll index 9a10359228e55da0588f6c05029a672e420ae791..56284d90a146b3429fe5f0ee4c0573aa038b4478 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcmps-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.experimental.constrained.fcmps.nxv1f16(, , metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll index c1e1450d0b0a2a9571f2470e2c841f77f98e98c7..b28981ff196ad7024349c022b813da0656385017 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll index bc8440920cd860f2c4919b00659efd8996696fb3..87d7885d4410320a02a7ae46deb9f4dbd54359f6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll index 9cf47f993ee46667f5d58b47511bbb4f85883145..1557e33dd7737920c6db8d6b25ec97fc80d8e5ed 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll index 1caddaf3feeca829258c018507cf4b08c896b642..3b641ea5bdf455b06ac4e5336b126dfd9357c6f5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfcvt.rtz.x.f.v.nxv1i16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll index 42e55a5f170e26c2e2cfb3951eae0302088a5bcf..2fdb4b13acc98830c037738328459819d3da6c93 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfcvt.rtz.xu.f.v.nxv1i16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll index 582c302dd2a156e7008973b4c39aab8516350a48..2ea0f668dc211bc518a9936dc18d6624d5252afa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll index 708b38b8ed1161d996a1e08ac63dbe9b2f73565a..a7a742d12dc678ec0d1f24e6711195732d52aa8c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll index aa59732e1e1e52cd308ffe8bc3ebaef6858f86f4..ab517de846b0f4bf1e95daf59d31be50fff4d950 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-constrained-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll index f7db2be35d720be0d8c6487351ea141445e6cc14..8d0c3bcf16756105e865374de9f447d18302f6dc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll index 0fe6c5dec42649ec64399196aabc596d3c0b1457..cdc0dc0dbca3efe4da6e6b85b89642f86d14dad5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll index 3f67c433bcbf1fd5cd77766548f19f8178138c98..03094db580596b62de734e6dcf412e6d557a5e18 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll index ab8a595dde5d7bdcca140ba9581e3164b91e73e5..35bed86d61176784f4f7543c7980afe346fb36c6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp-combine.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fma.nxv1f64(, , , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll index f0c74d064016a85a33405ec0cd81aa575833932d..a65c2fba81acb1265a7b52bb02c8439fbd330d06 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll index 54855e6152b95e6e615b42206aa312124a0fd696..ef583b748b9c2477253c240785c4f180c8d363f8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fma.nxv1f16(, , , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll index 5586b52b64ec4d5443ff668ecd0ad0bf7ebcee22..1f0db104df7aa91fe475c00376b5839d5ccdd9d7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll index dea411348ce54219cd7bc23a02dc4477261949ff..50bf6eb78044f5b301b3404d71ab01b1aa1a41c4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-constrained-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll index 2df2212c43db099b797f7d5b87f91b3aa4010134..1de8ce51bfe323574f72e703aa10524efae8f2ec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll index c44690d23f082bb7b7b99c2285c170ed77400103..fb04888a84dea5779fa500c4c67e56e06a4a0a40 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll index b5604add6d25bd77977876a998edb5e4ba4d2703..8ff7453a0e9a7b7a7ec1384c9539b3f9ffb8d795 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll index 6e38881b4d60fb1deba1b36923eb622c1aca16de..345a05d98f77b6c23f54c8a07454b96cfa25941d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax.ll index 458815c98b258f21b2387dfaa9e40c50aef61e40..52067e00a54bdde394b6ece5c1eb1b5811dc9411 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmax.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmax.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmax.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmerge.ll b/llvm/test/CodeGen/RISCV/rvv/vfmerge.ll index e47c2a47d6c6421cc7bd4d03e87a60022dfc655a..e227cff7054fa72ddec198f27f62ce11d501df05 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmerge.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmerge.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vmerge.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll index 9212ddab5b1ebf917453cb4e654b3ff540d9b51b..de49aed6e52b26062ffd4292ee6d072db155c26b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll index f1d6b2100ae980865465f939cf6eca636b2f914c..6f153acda01e202a12abca725669b0ebab92d5c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin.ll index 842c78dce02f8cf965a51a9248f503b55c7783fa..a69bb9e3d6c0225328c0e76b35b7e8f0c14c9b71 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmin.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmin.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmin.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll index f1d5562131b8e894f62ef25e37566576e7267ed8..31369b69bee15e48d93bf5f45264a757a4b8f80e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fma.nxv1f16(, , , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll index 4eac7b63fd881b624fc5b824db180a5bc6661dfa..319c9454354023416f2c03acfbe1f0521e7c36b9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll index 7ec241bf74247a0391226f75c3617c2f026e8d28..8bd82336de5622c7274c6a9c9cec638027e3c0fc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll index 433b0d1cbdd853148363ef2b98fe55a9ecd86e82..1f99d0e3a5b4b6069aebb7c922d238276be66edc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s ; This tests a mix of vfmsac and vfmsub by using different operand orders to diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll index 626b40e132c73bc060e923f54d6b84642eeb0c5c..23b4479fa8c9451c5c55d62e20a20622013cb4aa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll index 999b06ba5a5791ec2bcae629c2451c4c3834a700..9a68da58096d66c7226c08b76a3a9a2cbe668bf0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-constrained-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll index 2ab04a45c8183d9f6235e9415fceae4f1f1a231f..bbacbaa8e5e491b076b3f3c4de589a7b84c5d315 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll index 3114fb5d3bfa3e4918feefbd864acb3da09fb5fc..7112cf3b76835e3f0ad86f233cee5757206aacd4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul.ll index b73d03fe36c730c317ccf5a236742f3aac9a0a72..03084ebc3ae301071004a9a42ffba44057d2d184 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmul.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll index abda6750e5a8a5a864c440379014935458c632c5..ceefe709fe2a3fb04f0b963e8c9f9146cbbac3bf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fmuladd.nxv1f16(, , , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll index af1c378c56812f12e7f0dc05861c6ad03cabe88f..3779b0ab18d8a9ce6e65ff453da39957ad04f7ae 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+zfh,+zvfh -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+zfh,+zvfh -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+zvfh -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+zvfh -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s declare half @llvm.riscv.vfmv.f.s.nxv1f16() diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll index 1e863a4adbc21aada8a6b3c6db1205b03c08a300..912dfe499016f77dea92d6b13007242400836d4d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32 -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64 declare @llvm.riscv.vfmv.s.f.nxv1f16(, half, iXLen) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll index 237ef11d154bad73a0261ec48ac37a3ece51cb99..a3d3443e48c6da825b5af3f128a21fdf64505ff5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfmv.v.f.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll index 183ffa8a668a0249c1119eefd403ec2e914a2052..83250a0f90eaf4f47c048c8361af4cc861106432 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( , diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll index aef119faf5f7fe0d7848cb5d411c1c35e4eafef1..81b684978bafc2f25cc9ca54dfabdcb7392f6401 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll index bc287e4bdef163f45067f4a0aed336d15d9bbfef..697c062c7a71f22aac441437633e46ab8fd5e6a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll index f5a019d3152dd45282b3fdfbcc13275b495a7b74..c0e5c6991aec28e5363f658b0439d5c290937219 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfncvt.rod.f.f.w.nxv1f16.nxv1f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll index 65373bfbdb44c4cc21f1204bd1e18dccf57310b1..4079e1c055c5ef75947f1650a9bc01404531044d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfncvt.rtz.x.f.w.nxv1i8.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll index cafffa0d51f56ac6ec969be7852dcdd4de85d68b..9ce9fbfa8f19c58d71c9f26e7d9b12e568e48194 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfncvt.rtz.xu.f.w.nxv1i8.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll index 334d5eba03001211f6fe96123ebf82794d6c6eb2..5831bb33ff90ef738957eb28f73f78e092254dfa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll index bea99a0e81a348da2410d5d7712eb2362b3ffe56..3ef0a95197198c30c168723a3abb6dfb6813a75b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll index b4ec691796a71edc42805fe75c8b4baf291bd408..9f456e97be11d6287e5933722c5be1770419e919 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll index af2668a9b0c54522eab6e3bec9600d4c236497a3..6fa6c26890c3e0a830571adef157b1b3068d0e80 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll index ee3ed603ff6d792e820b861e308159e1ef7390a8..3b5cbb685a424b2be0deb5980879a57ecc9a8019 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fma.nxv1f16(, , , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll index 01f4715274b6c5a3c0478ca429c91d7d0370990c..31df27853cb3c97eb01f8736fc5e0f47b4706454 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll index 5ec089a2dcac865f31a66fe8c52483fed13d289c..332ab89b25856b756c269a45513fb2cb3d2ce805 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll index 61acb88b17bd729b1e3626f51ba5e49bf50a473d..07c85bc67339b1ac51d6e0b8c9d224d707bc2615 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfnmacc and vfnmadd by using different operand orders to diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll index ae4cfef35e61d45b5e5069c307a44e13bffca2a8..6f41ed177beacfffed1a04aafee08da8cfefccf9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll index 14dba24daf5ffaf17427841761c113a3f218b4d1..edeb554bc6d35f21c662bf193176aa6aaccdaf2c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fma.nxv1f16(, , , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll index 071f546b4f6096a4f60a42ed9a57786256a924de..50497d92764a52bab42c74536d6b439cc9cdae28 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll index 286492bce2960caf85eb45a6cb35ba906f2afae5..8b968017841f8d7420bfaa913e2499772b8ddc56 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll index 72f64b23f7584c42466bb6e97115fc3552c2f84f..a356da80e16394d56efa9c7a18447e2ef0fbca41 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ; This tests a mix of vfnmsac and vfnmsub by using different operand orders to diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll index 4922cf40e503831c92d30329d2cdc8979ea7d072..c5d5bb1fe0b3e4888f2675a01523e76c61402e74 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll index 2375f5def3dab086d62fd74e4b436965cfd80288..3999b97d6e256d0c56387ca0f9b67555f76ce2a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.experimental.constrained.fpext.nxv1f32.nxv1f16(, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll index 2f8b1d501f003bcfa0a59da9ed0e73adcec61bd2..3b2de0185f90c4a46c96e649092460c81f6f5dc9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfpext_nxv1f16_nxv1f32( %va) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll index 9d10b0209cbe740d35cac550ee0e2e40c822eb60..5962d38b1baa72bced598745cb558a4f0bc0af22 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfpext-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fpext.nxv2f32.nxv2f16(, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll index 47f68837cd578c3989e9e006b679b1c059e3abe3..6ebdcec4a403c4e70feb08225289cf603f64b8a5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.experimental.constrained.fptosi.nxv1i1.nxv1f16(, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll index 4edaa3825e5879e8dff14918d5e371956e98b3e0..37e14783d18733e15a0b35c224271f824f095eeb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll index 2e9ceadb96592e835563825ef3af441ed45f8fcd..b7f2133144e7143318afa737760512834f4a51a2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN define @vfptosi_nxv2i1_nxv2bf16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfptosi_nxv2i1_nxv2bf16: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll index f42b603509c22af6192561cd0d05176880ef49bc..a8ea062211337f564ff58a6d903126ea377c4b93 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN define @vfptosi_v4i7_v4bf16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfptosi_v4i7_v4bf16: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll index 2cf158ddbd50d6a6dafcea603ca98eae77b57787..8ac5992bd5eb9c4fddd525cce0f0dca5be554b39 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN define @vfptoui_nxv2i1_nxv2bf16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfptoui_nxv2i1_nxv2bf16: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll index 403bc595b9bbd1efee8947250f69c3283038b975..9062d8a6f2024f79a4ba306eaa028e92387d0286 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN define @vfptoui_v4i7_v4bf16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vfptoui_v4i7_v4bf16: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll index 65e753445aceb03528c22a3e635e785ff261a4a6..566920d577ce1dae2b4d800b112527499dcefa1e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-constrained-sdnode.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.experimental.constrained.fptrunc.nxv1f32.nxv1f64(, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll index e930e1fe42f0ecfa550714bed48ff3e0b59a8880..dcec2200b1308280664c521294b7ca7c27f5dc66 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfptrunc_nxv1f32_nxv1f16( %va) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll index da16feeddecd7110a0a2db41cb1fca0e0730c0bd..16c8fa728500e94637688d1fde05bd6f90c01553 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+m,+zvfbfmin -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fptrunc.nxv2f16.nxv2f32(, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll index 876f8d945638698f38fd481b96a5176be0a3dd1a..e8688abc63a5ddf80b2f6ff05830bfee4536a5dd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fdiv.nxv1f16(, , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll index f73e7dce92120f7a31b3097f0d79d3bbe529596b..9d29db4b1868ecb64337ad85c8c83999dbfbbe97 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfrdiv.nxv1f16.f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll b/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll index 914b3b33fbe5e3064a943a711b62edfb8307f585..98d82144a33349611eb0c67f43feb2c6896292cb 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfrec7.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmax.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmax.ll index 4219abbbaa1d825414ab66c6f98fc07a73917449..f1ed95512741c5f418505a32390ef3805b72336d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredmax.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredmax.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfredmax.nxv4f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmin.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmin.ll index 9fcd233fdc142810a6c1c9fd6a7f75e64d27d4fc..5dfa5a1f2b20eb0143034e4283a6a932e88ae490 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredmin.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredmin.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfredmin.nxv4f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll b/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll index bb489e0f380ca932a1b201822c2a1a8e8101ca34..a85850b0c4504bbeb98f4b3d0c233d9e51da5986 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll b/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll index c1463102c8e682caaae7aafacf236acee2c13f11..b3101450493e84627d767bcf76a5c48efecd4cfd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll b/llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll index f13fae2614eb6c4e667d329cf2f852674e7f6791..97d6e2924178fbc4ffb9de7259111b8ede757679 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfrsqrt7.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll index bd941dc1a77724dd93936d94d476ea9f62d3371f..e2864ea30ec7b6e021b41976728cc98ea4072a16 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.fsub.nxv1f16(, , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfrsub.ll index 1104753419883aebe468931632fb0df66178c65f..c3406c2730516951a67c58e332f9108caebf3768 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrsub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfrsub.nxv1f16.f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll index e7f0b7ab8a892adcc6d5ef97557f125af5a3bf76..73aaf32471db88e785aa8c7c509584fc2358ea1c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfsgnj.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll index 2ac48e0b9f9dc4ec3f047228d444f1e74bfeb0b1..06dc5656bb6c84c9d635b4354506c06f672eadc6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll index b9bbd8982d743010f2a0f6485d6bfc1cdcd031a3..891cda277a444d5acbeba0f0bcf3a20c679e8a50 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll index 9317a8a21f494c34940b563145e02f1cfea25cc4..dd036d1e1724dbf9c2150c30b7d15a18f14b827a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfslide1down.nxv1f16.f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll index c71cc13566f6d13b4a2337317f9a8d158c025fc5..6eead91c17873b95a2c895a514649f1e668701bd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfslide1up.nxv1f16.f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll index 9da1e0a576d5b7e13313d64b066db49ca76acff2..d92db0b5a3a7bc4e85b55b8528a5b8d25c886341 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-constrained-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll index de31a02cd154529071102a5914b77e6ce92bb23d..a51b0e4efecf23b042e554d0c6953b89558638dd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll index 574c2e05263015229e5e00a2b4a15458209e6597..00542284ebaee2e0f4e3632afed6c858069bac65 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll index 3e3eea9f353c81e63490ddbde3d4d25a2f5227e3..500a07ad87edf62ff92ae7f53006e63e80699e1a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfsqrt.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll index e40427a305f61c3df4e5aa76c980c76fcfc74f74..9b24b1df0f064b81fcc058f9b3b7cf80f807362e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-constrained-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll index e56cfd9ee4eb1a4c2e3905c3ac3e9d8a5fa14fbf..a2137eaa7a9585ee9eeee49529a785b9029ddc9c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll index dd57b65b50f4f19661bead153a83854f38b3738a..02647c1927c25bdf1ce3a8fd671f64412bf18049 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \ diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfsub.ll index 04590a52236655484a2e06e5e318d3180c498db6..96c915c6dbf1ef28cd7d8f64a29a9ec97c96a8d5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfsub.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll index d7f5b109aa7cb5b12f90491a33ef1e281a576075..68014ff4206f8ad7dbbe323059cdf9bbc75c4c97 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfwadd_vv_nxv1f64( %va, %vb) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll index b42a1fe46e670b4f59fbed0fe974bd44951d6da6..d980803cb38973f277b456dc35df4d9dcb6cabf3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll index 76246eba9480d7c914bef068f447a7a79b0dd9f6..8eb2a2c0391b553a01ed1233eb257adff81dc1ba 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll index 89c5d5a9a68f14d7cc5ce75be3b77f5614b3491e..4f03188cf3806d6d3ef9366ddad978a10ece20df 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfhmin \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfhmin \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwcvt.f.f.v.nxv1f32.nxv1f16( , diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll index cc8eeaaba256dfbe195f707adc9a99a0d77ef928..3c1e07b4a5ef4808220f87750afd425026f43832 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwcvt.f.x.v.nxv1f16.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll index 841278924d0f63ccb6c9545df1c5602a52d5551c..17ea8f50a6943e98e7741949327972cbe490a29d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwcvt.f.xu.v.nxv1f16.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll index f3a73e4fa3639bb39731159b62338ebcf3650128..f9f426cd3c9b61a0382e2d9c65e954cf41b15be7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.x.f.v.nxv1i32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll index d1d70aeee45e87defc784a9536a1c3aa9b39cd37..61d2ad5bf892a6855430faf46da2b29dec5a2e8e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwcvt.rtz.xu.f.v.nxv1i32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll index 9a80e02bbbbb44d1f085c5532725e8d3dfbc761b..8b545585c56d0a29872e6ad2bc7be9a783833cc2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll index 98caaf91ab3c01707cf2b59e9b6b69f76f5896c5..476e2398c479d03c32aa77874c96355f6e287bdd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll index 225ba1c14031f6eb10e5e20a7aa47e3aa48230a9..354f169561735df9239abaf3b0bb053ad7bca0e9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll index 5e3f63b95b2f9bbc69f9ad779726494200f7dec0..bd0d616fa6176e652d43f9d983cb4f15463ecb2b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll index 6b16171721f1dea276653eca99c5fe6856ad4f53..f00ff4b6d2cec2a57cdd1dc416ebbcc498652d58 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfwmul_vv_nxv1f64( %va, %vb) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll index bc5759f469ad0024f2a1d8bf0b516ff4782a579f..dae29efc75bf80ab419bc65550a312c9f463c6d6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll index fc8e15273f08503e884b95de7e613341fe4e5fcc..e1db8cb722760be17293d45e57f9dbd9028389b1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll index b51faf9082c8fcdbd101efab48e6a4fd4aacfabd..5c62112aa9e3d854db070ef1153e52f6f8f893af 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll index dbf7e27d318e55ec11e71ddda1410869f4453e70..bbb019f2f5892b27b5a58ea6be3c27010094ea5b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll index 9710051186c8d66238cbaa21e0c84bc1f659a6af..05044ef689a92b06b66b80f202c533f2d6a08875 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll index 787de48be7f0de7d200658688394d73ea45b7759..b9f66d5d30825d48c2a9371743b81c88f95a22e0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s define @vfwsub_vv_nxv1f64( %va, %vb) { diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll index 0e3e5f8aabfd376f6a3295450b65c3e669432aee..4f263c63e545b59486fb585e8f478d088f46809e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll index 90f92226dcdd9b42d73270b8e1f555dd1e96de7f..fdb48a6f10d3a5325542459ecdfb42474cd3bd15 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll index 90e5f58a603a59172dfd56cb61ac55a1a54f259f..f25a27ca2b905a753749f9fca2b3f7409d0c3127 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-constrained-sdnode.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.experimental.constrained.sitofp.nxv1f16.nxv1i1(, metadata, metadata) diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll index f5f8ee91c31c478af5e12d3621aa405c84c6f658..0f76968485fb4396d1c3f889a2c1f930739aa9c9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll @@ -1,14 +1,14 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+v,+zvfbfmin \ ; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+v,+zvfbfmin \ ; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \ ; RUN: --check-prefixes=CHECK,ZVFHMIN diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll index 481505a2095cb41bcb35b3f18f8f78ea1c525073..4f7286aeeda1e71e61b9c0a9a8dadfd56a24b2d9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", , 2), ptr, , i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll index c308512753f2df3aa58a4aed5bdd1f9da913c226..7b1d545ff9e9e51a1bf76c2a06c11d69a96a2333 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare target("riscv.vector.tuple", , 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", , 2), ptr, , i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll index b96874fe9098291b7f4d208e4af47670452ec62a..e6a98c90037d631e9abcb4957e010af3d4d9f725 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll index d6cbf362e7ece028cc4c2e2a5df7d1030fa7490a..809ae2d2bebfe3a63824a7893bbb70176c79bc6c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll index 0e4915895ef348b4ad766fc19403ddde3f24b49f..b89097b8ff97440f61add61962ac9022acf89b29 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {target("riscv.vector.tuple", , 2), i32} @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll index 632fbc1e4431dc4c9d0b499bc9dfd63cefabe70a..68acb3beb0686759758f05e7c8739db49747a884 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare {target("riscv.vector.tuple", , 2), i64} @llvm.riscv.vlseg2ff.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll index 4b475dd96e00e3b39eab9b9742e1466132b67541..a87d51692227f9edbbb974ae23167148b1cb5675 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i32, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll index 6cc95979eb13e0450f7faca8d87fcfbe1fab9baf..7b5421fba3dcc51bcfe57844192daa5cd8405be3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare target("riscv.vector.tuple", , 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i64, i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll index 10bfdec0e2c99d136ea4188a8e125348bcd7646a..d1ca40bcc0db3973b37c8c00999ba5c962f5f682 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", , 2), ptr, , i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll index 28f70ce08bfe10048f57f29d78a43763aee77f18..3b9db2655e03386364d48bcdf4902b44c2bbc31b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare target("riscv.vector.tuple", , 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", , 2), ptr, , i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq.ll index 2e5b67c93fce1aa262d1f4256b04a2cfb40df822..9ca78c872befd3b8e208ed37dd1a2e89fe6bc2e8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfeq.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vmfeq.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge.ll index b5ca47707c8a820661875245cecbd82ed983f5b6..7cf18a70158124c014739ac11d02aaf7fc20ac72 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfge.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfge.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vmfge.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll index 971249d38d1b26193312eb4ec4d0ec5862a8ed55..b78f2da4ae25409ad06af6169b6f1f7f41ab7757 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vmfgt.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle.ll index f19a181a365afc8feec462a67c23bcdf2a0b48b0..940e4d043f63f650ee97c3d86db6aef7d8ed4938 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfle.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfle.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vmfle.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt.ll index 0a046422193342d0082f2dfe0188159864a251bc..10ddfb8f014ed75e8c95f918d36ed03b201aa87b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmflt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmflt.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vmflt.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne.ll index 520099247e0f3d47d30e9a7d98ec30c518f08a05..4d8a95de1d3de72eb1cb644db72d8ba8c5554dbd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfne.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfne.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \ ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s declare @llvm.riscv.vmfne.nxv1f16( diff --git a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll index 84c8321b5b93429bb2fd5d3157376ef38722021a..34f8f35ee98c0c5d05068fe865fb16f7e47f3e0c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare @llvm.vp.gather.nxv1i8.nxv1p0(, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vpload.ll b/llvm/test/CodeGen/RISCV/rvv/vpload.ll index 0a98b672fb19c9a821e0ddcbcc2541e5237ba790..5683a7b7588546cc50bf9e4adb1b95c72dbeaed8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpload.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpload.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.load.nxv1i8.p0(ptr, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll index 0028f3035c27343be77e66136ef8a33e74a218d8..329f97da64ea8c1e56c3ec7ad855547807e22ffc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v,+m \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v,+m \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v,+m \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v,+m \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v,+m \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v,+m \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32 -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v,+m \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v,+m \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64 declare void @llvm.vp.scatter.nxv1i8.nxv1p0(, , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll index d935e52149d2075edfd080a3758042e0ed9ee8e5..7168b07e81971ef93872cf80f90aaf91eadc7548 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+zvfbfmin,+v \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfhmin,+zvfbfmin,+v \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.vp.store.nxv1i8.p0(, ptr, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll index f3ccf74019bb580d74f71ce5905f2cb3e28a656c..13d1ac5088479fdf26d2628163401ea50918caf3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare half @llvm.vp.reduce.fadd.nxv1f16(half, , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll index d1e947e2f33671ccb506c222f0b4b4d7741a1aeb..f386fd9cd3aeb1f724c6dd0bf8b51f86b80adcad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vrgatherei16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfh \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfh \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vrgatherei16.vv.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll index ee0617c9314801d9917bd22d0362819c7cc9ec82..b7e2c92350a2f66c1ffaa0921e90e8820d7383b4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zfh,+zvfh,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zvfh,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zfh,+zvfh,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zvfh,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zfh,+zvfhmin,+v -target-abi=ilp32d \ +; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zvfhmin,+v -target-abi=ilp32d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zfh,+zvfhmin,+v -target-abi=lp64d \ +; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zvfhmin,+v -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare @llvm.vp.select.nxv1i1(, , , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll index d1c2cf325bec49dd72f5b574ec3e8a94f9a6481c..ec16e58f6e57d2e22f795351543ac27c7efd5cda 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s define @vsitofp_nxv2bf16_nxv2i1( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i1: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll index d163988b3d41cdba3de4e3825111b1886477badf..8b6e437fbc0a3fee9c344bc9c5984a8979946fec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN define @vsitofp_nxv2bf16_nxv2i7( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i7: diff --git a/llvm/test/CodeGen/RISCV/rvv/vslidedown.ll b/llvm/test/CodeGen/RISCV/rvv/vslidedown.ll index fc26ac25fe0811323db58594278f20f9d2819358..2be187c50af26f62dfad61cab4e316416932f08f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vslidedown.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslidedown.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfh \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfh \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vslidedown.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vslideup.ll b/llvm/test/CodeGen/RISCV/rvv/vslideup.ll index 4880bf2bc66ddb2a404742c99bdf8daf655e1d8f..1e3ede7fee9cbda51ab7510b4d4998e1104a533f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vslideup.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vslideup.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfh \ ; RUN: -verify-machineinstrs | FileCheck %s -; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zfh,+zvfh \ +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfh \ ; RUN: -verify-machineinstrs | FileCheck %s declare @llvm.riscv.vslideup.nxv1i8( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll index c24895a0e6380b32d3870e51621eb1af40f01713..6b54ce4974f34b00531da6c124abacbc1fdf6064 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", , 2), ptr, , i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll index c8e7c437540581da026f838f61b6accccc7e2412..70fb9c2b348d36732b54789e559afd26eec901bc 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", , 2), ptr, , i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll index 330ec59d3459cd0adf1a9a45a6a9f7b35e316294..7b80d45a924d36f997d38fddf1a47ee1db4c8b9d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll index 877eeeaf10039f9153b6e1a3cb41f7ee81b68535..6ce326be23ee3760fe049ea3ff357f106e767ec4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll index df443d6f4d93af6a57a62b3733256b45ac83f627..a0a583c046c490da55c2d561a9d518ea6d183b28 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i32, i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll index dd6faad09f49a9c0db7c10801dcdf172a698a4ab..bdd809841d2d6cb811d35f572295b924a922c2f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", , 2), ptr, i64, i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll index 9119d42ba0aeee1b799a498b92600b41a64690b2..316c7ccb7e415561328854faed0d913e42e4f6a1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv32 -mattr=+zve64d,+f,+d,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", , 2), ptr, , i32, i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll index 82698e6da2abfa228b8274dc87104b06bba6be72..22be2ebca8fdeb84a8e5ce1e2ffa7ac8665fce70 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zfh,+zvfh,+zvfbfmin \ +; RUN: llc -mtriple=riscv64 -mattr=+zve64d,+f,+d,+zvfh,+zvfbfmin \ ; RUN: -verify-machineinstrs < %s | FileCheck %s declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv1i8_2t.nxv1i8(target("riscv.vector.tuple", , 2), ptr, , i64, i64) diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll index 5426102efc73e3460012271eab3b2289899d2edb..616dc697b2847659f91c8f589967da4dd489e018 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s define @vuitofp_nxv2bf16_nxv2i1( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vuitofp_nxv2bf16_nxv2i1: diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll index 7c96a9e9e10f65c01af0aef5dc3a3300c1e850c4..499bd4aa667c38493f5ab6f3e1ed63c992dca5be 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH -; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN -; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfh,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFH +; RUN: llc -mtriple=riscv32 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN +; RUN: llc -mtriple=riscv64 -mattr=+m,+v,+zvfhmin,+zvfbfmin < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN define @vuitofp_nxv2bf16_nxv2i7( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vuitofp_nxv2bf16_nxv2i7: diff --git a/llvm/test/CodeGen/SPIRV/OpVariable_order.ll b/llvm/test/CodeGen/SPIRV/OpVariable_order.ll index 6057bf38d4c4c40614a66b6f1ca995bc79e21b48..c68250697c4a7b75e8dc862d0e5d703c28d96fd9 100644 --- a/llvm/test/CodeGen/SPIRV/OpVariable_order.ll +++ b/llvm/test/CodeGen/SPIRV/OpVariable_order.ll @@ -1,7 +1,7 @@ ; All OpVariable instructions in a function must be the first instructions in the first block -; RUN: llc -O0 -mtriple=spirv-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-linux %s -o - -filetype=obj | spirv-val %} +; RUN: llc -O0 -mtriple=spirv32-unknown-linux %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-linux %s -o - -filetype=obj | spirv-val %} ; CHECK-SPIRV: OpFunction ; CHECK-SPIRV-NEXT: OpLabel diff --git a/llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll b/llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll index 3c002e1849b8dd2ca11317fbf477638afc059a30..1f203043e6a164f1553abea9e2da2b343af40c2d 100644 --- a/llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll +++ b/llvm/test/CodeGen/SPIRV/ShaderBufferImage.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-library %s -o - -filetype=obj | spirv-val %} ; CHECK-NOT: OpCapability ImageBasic diff --git a/llvm/test/CodeGen/SPIRV/ShaderImage.ll b/llvm/test/CodeGen/SPIRV/ShaderImage.ll index 6ac58ce42f950f35225d00fd3aafdd1b02fac10d..9cd5fb338080560bc76384ee8f4b8f70d211be5c 100644 --- a/llvm/test/CodeGen/SPIRV/ShaderImage.ll +++ b/llvm/test/CodeGen/SPIRV/ShaderImage.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-library %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: [[Float:%[0-9]+]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/basic_float_types.ll b/llvm/test/CodeGen/SPIRV/basic_float_types.ll index 1c7a8a851f59c69793854d04a93849cbc6e15241..dfee1ace2205dded6df76d06eeb3b550f2b05470 100644 --- a/llvm/test/CodeGen/SPIRV/basic_float_types.ll +++ b/llvm/test/CodeGen/SPIRV/basic_float_types.ll @@ -1,4 +1,3 @@ -; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types.ll b/llvm/test/CodeGen/SPIRV/basic_int_types.ll index bb664568ed842f97ef34e64260e4343b1e7f1b75..e85e0919d1793426f9906eff142fdc11e50269f4 100644 --- a/llvm/test/CodeGen/SPIRV/basic_int_types.ll +++ b/llvm/test/CodeGen/SPIRV/basic_int_types.ll @@ -1,6 +1,4 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} - +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll b/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll index 3778d897929188b9dc343e83714925d3ae9c3231..0d7b2b99f64eac247a129a780d936d7bed56fc55 100644 --- a/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll +++ b/llvm/test/CodeGen/SPIRV/basic_int_types_spirvdis.ll @@ -1,5 +1,5 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; REQUIRES: spirv-tools -; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - --filetype=obj | spirv-dis | FileCheck %s diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll index c84b1c4b06c1993ae13597e88f424cfe8870a28d..2d8692adf12a2a046238724f38bc3eb45df8ae21 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/SV_DispatchThreadID.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} ; This file generated from the following command: diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll index 89a8575fa15991cb90c21262e72d357cba2b6d88..d0a56854c32f8ae0239ba415bc4152cf88c339af 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveGetLaneIndex.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} ; This file generated from the following command: diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll index 8f1092c2206ed83e405244a327322cfacd6debfe..c3e894afd710b62d1b506226aa937a1f4e1213a4 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/abs.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll index 7c9450267cbe89be4a5116d52706bc69cac108f2..1936f6d27207379d9e0ab6fda5ecf7acf52361b0 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/acos.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll index 7c40eed8465a1d4eebd84beca4501986b3cf39a2..1edd69e2b0d5b0bb8024c2af8c29d875a6931d1b 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/all.ll @@ -1,5 +1,6 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; Make sure spirv operation function calls for all are generated. diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll index 54f5b7774b579e8b1c4847eab784f70acb56b799..dc6e9dc2033055268d41fbc86def6948b4b91134 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/any.ll @@ -1,5 +1,6 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-HLSL +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-OCL ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; Make sure spirv operation function calls for any are generated. diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll index 4d57c6fce77f70e4480c2374e6b07b2eac7c85b7..be338f22bf12555e3eebfd564dd10b82b47607ef 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/asin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll index 65e198d0e71a3503728ed08ecca36b96f852a0d7..5d352eb80af2d3aac55dd7b9a5696b25d6ac73b9 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll index bdbfc133efa29b07c2ae8453a89dc6549ca4c50f..aba6f7583b68338357635132717c89978e6e05e2 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/atan2.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll index 93677aadffa5e9ea03d4d3c29e930184eaa140fd..2c36459bdac95ddf3028c0d5d35db957d27cbeec 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/ceil.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll index e9e9642354f5a55f78917c244a49a44671b12168..937a545cc563cbd5fffa8ff17d0bd8ebaead0567 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cos.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll index 1560f9b9bd76059ca3bfe0ec0b7aae0532cc6a74..2d7a4caada7d5496a2080d655742810936a9526c 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/cosh.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll index 57ec0bda2e18903d6691b7e7611637953063ea77..d47ec3ec27aa1b3506c5d92ac9f5dd3f920f228e 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/countbits.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpMemoryModel Logical GLSL450 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll index 533bcca6f62169a740e36a8c5bc36ca3e66a29eb..6915362001288b23446521719b0fea89c482f46c 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/degrees.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll index c1734a264ea04231f41eb814c47ec22c08033f15..43bb8e217a67056ee0775f244cdef87b61d9ac96 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll index 4753b7bd9fe5bddf3572fdbea60603ed1da480c1..ae6c33cb0c7ef2a2bf4bba88b26cba621aa2806d 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/exp2.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll index ea19fa94ea32658487fdfb468008e9f041a52401..1ecaafc22e6fad9dd661786fd64017f2d56da3ee 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/floor.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll index b1ca34dc504c033f9ab231843e505e7c1f0d6ff5..add94601bd1687ebab7b94119b9aea0d40bc4d77 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmad.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll index ca0fcfe8d646b6388f407ad3c6c15bee0b728bf7..b202025f5dc83d724efcfd4bde2427a65375ddc1 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmax.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll index adc563bcea5c6c6f18dc2feb0d6f92d908bc6363..77e2ed1748e6ee644144d279e759b4413718107a 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/fmin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll index 4c088b6b38103c1c60c12b3f4f5fef93813678bd..41c18b693574f74d17bf644b9b65226727730627 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/frac.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll new file mode 100644 index 0000000000000000000000000000000000000000..e314361fe418128826d343b15e0b4a5cd0939d35 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier_with_group_sync.ll @@ -0,0 +1,15 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpMemoryModel Logical GLSL450 + +define void @test_group_memory_barrier_with_group_sync() { +entry: + ; CHECK: %[[#TY:]] = OpTypeInt 32 0 + ; CHECK-DAG: %[[#MEM_SEM:]] = OpConstant %[[#TY]] 16 + ; CHECK-DAG: %[[#EXEC_AND_MEM_SCOPE:]] = OpConstant %[[#TY]] 2 + ; CHECK: OpControlBarrier %[[#EXEC_AND_MEM_SCOPE]] %[[#EXEC_AND_MEM_SCOPE]] %[[#MEM_SEM]] + call void @llvm.spv.group.memory.barrier.with.group.sync() + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll index 1be8eb7e6516612f0fe5f80a05086c85d24fe73d..a161147c8b9647e289f5ea812f8d981ba9a381bd 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/imad.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16 0 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll index aa7ad8c74d336cc9c484b51f463473b55fd7dceb..94272a84bd639247e235ac9b93b33a950ec1aaaa 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/lerp.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; Make sure SPIRV operation function calls for lerp are generated as FMix diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll index f85b20324da515444d4cd414548f403ce293f720..d5dd92042537a16009791ccc4d55b9b3f89a7937 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll index 32d63a0c0f1d21987afba3820a79ae9d99b1c1f1..a829422d84ebfa5478e797e862c1f065b25e6685 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log10.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#extinst:]] = OpExtInstImport "GLSL.std.450" @@ -6,35 +7,22 @@ ; CHECK: %[[#float:]] = OpTypeFloat 32 ; CHECK: %[[#v4float:]] = OpTypeVector %[[#float]] 4 ; CHECK: %[[#float_0_30103001:]] = OpConstant %[[#float]] 0.30103000998497009 -; CHECK: %[[#_ptr_Function_v4float:]] = OpTypePointer Function %[[#v4float]] -; CHECK: %[[#_ptr_Function_float:]] = OpTypePointer Function %[[#float]] -define void @main() { +define void @main(float %f, <4 x float> %f4) { entry: -; CHECK: %[[#f:]] = OpVariable %[[#_ptr_Function_float]] Function -; CHECK: %[[#logf:]] = OpVariable %[[#_ptr_Function_float]] Function -; CHECK: %[[#f4:]] = OpVariable %[[#_ptr_Function_v4float]] Function -; CHECK: %[[#logf4:]] = OpVariable %[[#_ptr_Function_v4float]] Function - %f = alloca float, align 4 +; CHECK-DAG: %[[#f:]] = OpFunctionParameter %[[#float]] +; CHECK-DAG: %[[#f4:]] = OpFunctionParameter %[[#v4float]] %logf = alloca float, align 4 - %f4 = alloca <4 x float>, align 16 %logf4 = alloca <4 x float>, align 16 -; CHECK: %[[#load:]] = OpLoad %[[#float]] %[[#f]] Aligned 4 -; CHECK: %[[#log2:]] = OpExtInst %[[#float]] %[[#extinst]] Log2 %[[#load]] + +; CHECK: %[[#log2:]] = OpExtInst %[[#float]] %[[#extinst]] Log2 %[[#f]] ; CHECK: %[[#res:]] = OpFMul %[[#float]] %[[#log2]] %[[#float_0_30103001]] -; CHECK: OpStore %[[#logf]] %[[#res]] Aligned 4 - %0 = load float, ptr %f, align 4 - %elt.log10 = call float @llvm.log10.f32(float %0) - store float %elt.log10, ptr %logf, align 4 + %elt.log10 = call float @llvm.log10.f32(float %f) -; CHECK: %[[#load:]] = OpLoad %[[#v4float]] %[[#f4]] Aligned 16 -; CHECK: %[[#log2:]] = OpExtInst %[[#v4float]] %[[#extinst]] Log2 %[[#load]] +; CHECK: %[[#log2:]] = OpExtInst %[[#v4float]] %[[#extinst]] Log2 %[[#f4]] ; CHECK: %[[#res:]] = OpVectorTimesScalar %[[#v4float]] %[[#log2]] %[[#float_0_30103001]] -; CHECK: OpStore %[[#logf4]] %[[#res]] Aligned 16 - %1 = load <4 x float>, ptr %f4, align 16 - %elt.log101 = call <4 x float> @llvm.log10.v4f32(<4 x float> %1) - store <4 x float> %elt.log101, ptr %logf4, align 16 + %elt.log101 = call <4 x float> @llvm.log10.v4f32(<4 x float> %f4) ret void } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll index add7f77897f790540aa9cb77c7de5e0e1c362abb..c71ca125c172a77b95278d745b5b77a22f46fde9 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/log2.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll index fa73b9c2a4d3abfaca82f0aab595c513d0ea1020..ddf89221be2ae4233a819c46f00fcba56f0635a3 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/normalize.ll @@ -1,3 +1,4 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll index 3ac98853b92fbce454ef6febd8a5a8840e9f5e58..38c51ca47d86c93d00264214a983704f7701b04d 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/pow.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll index 1fe8ab30ed9538e84f326b3ad41e6338cdbfec20..7aad4df76e3185851560c053ffc269a5ef33f2f5 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/radians.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll index 6f91162a378c8ad1970691bd657b5d49d293e8e9..9c8c14c2a7220a0370290b121a97adbb2d62733c 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rcp.ll @@ -1,4 +1,5 @@ - ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" + ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64 ; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll index a23b15ab075d6007ba63f91656cdd04b3bd231ab..ce8175fdceb202d52d203afa39f5f6aa3e2ee4d0 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/reversebits.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpMemoryModel Logical GLSL450 diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll index 1c7e78261ffefdbeccf28eac983661752ebb48d6..0c88c55cbd395f650f15cdfd4aa67d255d202840 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/round.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll index 91023a1e401e1607f8aad2905d28d6f59289eedf..33d3edc080fd78e96c94442c18b117ad91f53ed4 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/rsqrt.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll index a6ae70a48e5db457cfeffc4bd03e0c2790989d4b..7474b759945138352c182a9b3e347df41e132f7b 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll index 3b8bdbed0041bb1a15eb40daa2eefbb2fef33057..6a31b702187733ea1a80e679457518521b276500 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sinh.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll index 901e4764e15f67ecaa9bb8ff209ddcc67f6f3f20..cbf0b243ab2b3f90a36369b436e55591a5289d0a 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smax.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll index c39c39f0455fadaafe928d04979c668a3393cfe9..960de853f3afdfef89c3e963f956af6885587937 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/smin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll index d18b16b843c37bcb65f332312beefa8a53a63e30..a05a31c18a754f1d2759c63c35f7359e2e41d5e8 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/splitdouble.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; Make sure lowering is correctly generating spirv code. diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll index bb1f0346047e220a2b04ec316b7bff1aed2ea2eb..55d8a286a0e7fd83743c3faa65e36d9cc7924420 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/sqrt.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll index bb50d8c790f8adc23609173699b0df7a597c109f..eac0b858955545a331f987281cf4e8ec78cfd39e 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/step.ll @@ -1,3 +1,4 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll index b4a6e1574f732bb76124e54fdf20f5ad864a4111..6e2f0698b7b6d5618c7e07e4ec25a8c47b01aeeb 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tan.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll index 94fc3f0ec7abf56335cf91f83e7b48835454f69b..1dfdf83fee31e72b694f9583441b9b54d10ea3da 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/tanh.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: %[[#op_ext_glsl:]] = OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll index 2a308028a9b48203d6e5d72380c79e8b6c0a617a..bae614ee59676c00a3a93b984b3eae40ed3b6237 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/trunc.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll index 01606a38732772323ee13861d830476ec22d5b38..e2b14b089bc13928d6e07adfa98eb8e500595efd 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umax.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll index 34185ad7143e32de3bc90048d7b26854d6d93ead..708b76a93e661333da6b07e339bc76775b35397a 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/umin.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: OpExtInstImport "GLSL.std.450" diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..d5e95c7824144f7cb05fe9a8aa0ef316275f7633 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageDynIdx.ll @@ -0,0 +1,41 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK-NEXT: OpCapability SampledImageArrayDynamicIndexing +; CHECK-NEXT: OpCapability Sampled1D +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] 1D 2 0 0 1 R32i {{$}} +; CHECK-DAG: [[CombindedType:%[0-9]+]] = OpTypeSampledImage [[BufferType]] +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[CombindedType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One:%[0-9]+]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero:%[0-9]+]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[CombindedType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[CombindedType]] [[ac]] + %buffer0 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 0, i1 false) + +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[CombindedType]] [[ac]] + %buffer1 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 1, i1 false) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..68bf3478fa9af09260d2baaf210b0ac5dc6c39e9 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/CombinedSamplerImageNonUniformIdx.ll @@ -0,0 +1,48 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK: OpCapability ShaderNonUniform +; CHECK-NEXT: OpCapability SampledImageArrayNonUniformIndexing +; CHECK-NEXT: OpCapability Sampled1D +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 +; CHECK: OpDecorate [[Zero:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[One:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac1:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld1:%[0-9]+]] NonUniform + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] 1D 2 0 0 1 R32i {{$}} +; CHECK-DAG: [[CombindedType:%[0-9]+]] = OpTypeSampledImage [[BufferType]] +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[CombindedType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[CombindedType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[ld0:%[0-9]+]] = OpLoad [[CombindedType]] [[ac0]] + %buffer0 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 0, i1 true) + +; CHECK: [[ac1]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[ld1]] = OpLoad [[CombindedType]] [[ac1]] + %buffer1 = call target("spirv.SampledImage", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 1, i1 true) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/HlslBufferLoad.ll similarity index 85% rename from llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll rename to llvm/test/CodeGen/SPIRV/hlsl-resources/HlslBufferLoad.ll index fe960f0d6f2f9aaaba5d123829bae4134c63ce98..66d5f0f4b05fe6580c45243952b608545e270af0 100644 --- a/llvm/test/CodeGen/SPIRV/HlslBufferLoad.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/HlslBufferLoad.ll @@ -1,4 +1,5 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv-vulkan-library %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-library %s -o - -filetype=obj | spirv-val %} ; CHECK-DAG: OpDecorate [[IntBufferVar:%[0-9]+]] DescriptorSet 16 @@ -18,13 +19,13 @@ ; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} ; CHECK-NEXT: OpLabel define void @RWBufferLoad() #0 { -; CHECK-NEXT: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) ; Make sure we use the same variable with multiple loads. -; CHECK-NEXT: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) @@ -36,7 +37,7 @@ define void @RWBufferLoad() #0 { define void @UseDifferentGlobalVar() #0 { ; Make sure we use a different variable from the first function. They have ; different types. -; CHECK-NEXT: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeFloat]] [[FloatBufferVar]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeFloat]] [[FloatBufferVar]] %buffer0 = call target("spirv.Image", float, 5, 2, 0, 0, 2, 3) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_3( i32 16, i32 7, i32 1, i32 0, i1 false) @@ -48,7 +49,7 @@ define void @UseDifferentGlobalVar() #0 { define void @ReuseGlobalVarFromFirstFunction() #0 { ; Make sure we use the same variable as the first function. They should be the ; same in case one function calls the other. -; CHECK-NEXT: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[RWBufferTypeInt]] [[IntBufferVar]] %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( i32 16, i32 7, i32 1, i32 0, i1 false) diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..39fdc866af7ff25e907ebf104de68fe6444272a1 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageDynIdx.ll @@ -0,0 +1,40 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK-NEXT: OpCapability InputAttachmentArrayDynamicIndexing +; SCHECK-NEXT: OpCapability InputAttachment +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] SubpassData 2 0 0 2 Unknown {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One:%[0-9]+]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero:%[0-9]+]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer0 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + i32 3, i32 4, i32 3, i32 0, i1 false) + +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer1 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + i32 3, i32 4, i32 3, i32 1, i1 false) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..b05b7eb885b426c09877f8d6412b53b5f52d207b --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/InputAttachmentImageNonUniformIdx.ll @@ -0,0 +1,47 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK-NEXT: OpCapability ShaderNonUniformEXT +; CHECK-NEXT: OpCapability InputAttachmentArrayNonUniformIndexing +; SCHECK-NEXT: OpCapability InputAttachment +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 +; CHECK: OpDecorate [[Zero:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[One:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac1:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld1:%[0-9]+]] NonUniform + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] SubpassData 2 0 0 2 Unknown {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] + %buffer0 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + i32 3, i32 4, i32 3, i32 0, i1 true) + +; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] + %buffer1 = call target("spirv.Image", i32, 6, 2, 0, 0, 2, 0) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_6_2_0_0_2_0( + i32 3, i32 4, i32 3, i32 1, i1 true) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..0c47eeb606e802ee20e115285eda11694e0e54da --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageDynIdx.ll @@ -0,0 +1,66 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK-NEXT: OpCapability SampledImageArrayDynamicIndexing +; CHECK-NEXT: OpCapability Sampled1D +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 +; CHECK-DAG: OpDecorate [[OtherVar:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[OtherVar]] Binding 4 + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] 1D 2 0 0 1 R32i {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One:%[0-9]+]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero:%[0-9]+]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK-DAG: [[OtherArraySize:%[0-9]+]] = OpConstant [[int]] 5 +; CHECK-DAG: [[OtherBufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[OtherArraySize]] +; CHECK-DAG: [[OtherArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[OtherBufferArrayType]] +; CHECK-DAG: [[OtherVar]] = OpVariable [[OtherArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 0, i1 false) + +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 1, i1 false) + ret void +} + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @DifferentArraySizesAreDifferentVariables() #0 { +; Make sure we use different variables when the array sizes are different +; same in case one function calls the other. +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 0, i1 false) + +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[OtherVar]] [[One]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 5, i32 1, i1 false) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..ec94a8eeac2e42324ca66b4326a065e2fc9e5ba2 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SampledImageNonUniformIdx.ll @@ -0,0 +1,47 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK-NEXT: OpCapability ShaderNonUniformEXT +; CHECK-NEXT: OpCapability SampledImageArrayNonUniformIndexing +; CHECK-NEXT: OpCapability Sampled1D +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 +; CHECK: OpDecorate [[Zero:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[One:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac1:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld1:%[0-9]+]] NonUniform + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] 1D 2 0 0 1 R32i {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] + %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 0, i1 true) + +; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] + %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 1, i1 true) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..9371a792f84b2ab10ba98638016c20d7441b6532 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayDynIdx.ll @@ -0,0 +1,39 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK-NEXT: OpCapability SampledImageArrayDynamicIndexing +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[SamplerType:%[0-9]+]] = OpTypeSampler +; CHECK-DAG: [[SamplerPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[SamplerType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One:%[0-9]+]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero:%[0-9]+]] = OpConstant [[int]] 0 +; CHECK-DAG: [[SamplerArrayType:%[0-9]+]] = OpTypeArray [[SamplerType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[SamplerArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[Zero]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[SamplerType]] [[ac]] + %buffer0 = call target("spirv.Sampler") + @llvm.spv.handle.fromBinding.tspirv.Image( + i32 3, i32 4, i32 3, i32 0, i1 false) + +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[One]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[SamplerType]] [[ac]] + %buffer1 = call target("spirv.Sampler") + @llvm.spv.handle.fromBinding.tspirv.Image( + i32 3, i32 4, i32 3, i32 1, i1 false) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..151c4aa6d4365c99196296035b98dcdb4c24d90b --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/SamplerArrayNonUniformIdx.ll @@ -0,0 +1,46 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK-NEXT: ShaderNonUniform +; CHECK-NEXT: OpCapability SampledImageArrayNonUniformIndexing +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 +; CHECK: OpDecorate [[Zero:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[One:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac1:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld1:%[0-9]+]] NonUniform + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[SamplerType:%[0-9]+]] = OpTypeSampler +; CHECK-DAG: [[SamplerPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[SamplerType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero]] = OpConstant [[int]] 0 +; CHECK-DAG: [[SamplerArrayType:%[0-9]+]] = OpTypeArray [[SamplerType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[SamplerArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac0]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[Zero]] +; CHECK: [[ld0]] = OpLoad [[SamplerType]] [[ac0]] + %buffer0 = call target("spirv.Sampler") + @llvm.spv.handle.fromBinding.tspirv.Image( + i32 3, i32 4, i32 3, i32 0, i1 true) + +; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[SamplerPtrType]] [[Var]] [[One]] +; CHECK: [[ld1]] = OpLoad [[SamplerType]] [[ac1]] + %buffer1 = call target("spirv.Sampler") + @llvm.spv.handle.fromBinding.tspirv.Image( + i32 3, i32 4, i32 3, i32 1, i1 true) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..908a81777a04a08014c41f0f914e81ab01a9a85c --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageDynIdx.ll @@ -0,0 +1,40 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK-NEXT: OpCapability StorageImageArrayDynamicIndexing +; CHECK-NEXT: OpCapability Image1D +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] 1D 2 0 0 2 R32i {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One:%[0-9]+]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero:%[0-9]+]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + i32 3, i32 4, i32 3, i32 0, i1 false) + +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + i32 3, i32 4, i32 3, i32 1, i1 false) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..4a582b31d60f1d36eb8a240f897aa9e06b766fa9 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageImageNonUniformIdx.ll @@ -0,0 +1,47 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; CHECK: OpCapability ShaderNonUniformEXT +; CHECK-NEXT: OpCapability StorageImageArrayNonUniformIndexing +; CHECK-NEXT: OpCapability Image1D +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 +; CHECK: OpDecorate [[Zero:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[One:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac1:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld1:%[0-9]+]] NonUniform + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] 1D 2 0 0 2 R32i {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] + %buffer0 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + i32 3, i32 4, i32 3, i32 0, i1 true) + +; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] + %buffer1 = call target("spirv.Image", i32, 0, 2, 0, 0, 2, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_0_2_0_0_2_24( + i32 3, i32 4, i32 3, i32 1, i1 true) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..d144dcf505fa18abaface7114cbf7212b8777dd0 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferDynIdx.ll @@ -0,0 +1,40 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; SCHECK-NEXT: OpCapability ImageBuffer +; CHECK-NEXT: OpCapability StorageTexelBufferArrayDynamicIndexing +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] Buffer 2 0 0 2 R32i {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One:%[0-9]+]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero:%[0-9]+]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @void() #0 { +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + i32 3, i32 4, i32 3, i32 0, i1 false) + +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + i32 3, i32 4, i32 3, i32 1, i1 false) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..2f96eda4518f06012a44ba1910ea5d06164d26d1 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StorageTexelBufferNonUniformIdx.ll @@ -0,0 +1,47 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; SCHECK-NEXT: OpCapability ImageBuffer +; CHECK-NEXT: OpCapability ShaderNonUniformEXT +; CHECK-NEXT: OpCapability StorageTexelBufferArrayNonUniformIndexingEXT +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 +; CHECK: OpDecorate [[Zero:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[One:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac1:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld1:%[0-9]+]] NonUniform + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] Buffer 2 0 0 2 R32i {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] + %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + i32 3, i32 4, i32 3, i32 0, i1 true) + +; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] + %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 2, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_2_24( + i32 3, i32 4, i32 3, i32 1, i1 true) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..117363241bd966d09ada87caae02937c5d1a12b8 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferDynIdx.ll @@ -0,0 +1,40 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; SCHECK-NEXT: OpCapability SampledBuffer +; CHECK-NEXT: OpCapability UniformTexelBufferArrayDynamicIndexing +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] Buffer 2 0 0 1 R32i {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One:%[0-9]+]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero:%[0-9]+]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 0, i1 false) + +; CHECK: [[ac:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[buffer:%[0-9]+]] = OpLoad [[BufferType]] [[ac]] + %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 1, i1 false) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll new file mode 100644 index 0000000000000000000000000000000000000000..cec16a8e7c8b4763d3312fd9b8239b7c1688d1dd --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/UniformTexelBufferNonUniformIdx.ll @@ -0,0 +1,47 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" +; RUN: llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-library %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Shader +; SCHECK-NEXT: OpCapability SampledBuffer +; CHECK-NEXT: OpCapability ShaderNonUniformEXT +; CHECK-NEXT: OpCapability UniformTexelBufferArrayNonUniformIndexing +; CHECK-NOT: OpCapability + +; CHECK-DAG: OpDecorate [[Var:%[0-9]+]] DescriptorSet 3 +; CHECK-DAG: OpDecorate [[Var]] Binding 4 +; CHECK: OpDecorate [[Zero:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld0:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[One:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ac1:%[0-9]+]] NonUniform +; CHECK: OpDecorate [[ld1:%[0-9]+]] NonUniform + +; CHECK-DAG: [[int:%[0-9]+]] = OpTypeInt 32 0 +; CHECK-DAG: [[BufferType:%[0-9]+]] = OpTypeImage [[int]] Buffer 2 0 0 1 R32i {{$}} +; CHECK-DAG: [[BufferPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferType]] +; CHECK-DAG: [[ArraySize:%[0-9]+]] = OpConstant [[int]] 3 +; CHECK-DAG: [[One]] = OpConstant [[int]] 1 +; CHECK-DAG: [[Zero]] = OpConstant [[int]] 0 +; CHECK-DAG: [[BufferArrayType:%[0-9]+]] = OpTypeArray [[BufferType]] [[ArraySize]] +; CHECK-DAG: [[ArrayPtrType:%[0-9]+]] = OpTypePointer UniformConstant [[BufferArrayType]] +; CHECK-DAG: [[Var]] = OpVariable [[ArrayPtrType]] UniformConstant + +; CHECK: {{%[0-9]+}} = OpFunction {{%[0-9]+}} DontInline {{%[0-9]+}} +; CHECK-NEXT: OpLabel +define void @main() #0 { +; CHECK: [[ac0]] = OpAccessChain [[BufferPtrType]] [[Var]] [[Zero]] +; CHECK: [[ld0]] = OpLoad [[BufferType]] [[ac0]] + %buffer0 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 0, i1 true) + +; CHECK: [[ac1:%[0-9]+]] = OpAccessChain [[BufferPtrType]] [[Var]] [[One]] +; CHECK: [[ld1]] = OpLoad [[BufferType]] [[ac1]] + %buffer1 = call target("spirv.Image", i32, 5, 2, 0, 0, 1, 24) + @llvm.spv.handle.fromBinding.tspirv.Image_f32_5_2_0_0_1_24( + i32 3, i32 4, i32 3, i32 1, i1 true) + ret void +} + +attributes #0 = { convergent noinline norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } diff --git a/llvm/test/CodeGen/SPIRV/literals.ll b/llvm/test/CodeGen/SPIRV/literals.ll index 4109bb6de56110a66ba5396b6592316b093464e6..86a366976a6e26b559c5ca02160f506a063b10e1 100644 --- a/llvm/test/CodeGen/SPIRV/literals.ll +++ b/llvm/test/CodeGen/SPIRV/literals.ll @@ -1,12 +1,10 @@ +; TODO(pull/110270): verifier, fix G_BITCAST error "bitcast must change type" ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-unknown-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-unknown %s -o - -filetype=obj | spirv-val %} - ; CHECK: %[[#F32:]] = OpTypeFloat 32 ; CHECK: %[[#F64:]] = OpTypeFloat 64 diff --git a/llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-rev.ll b/llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-rev.ll index 6fa3f4e53cc598f46e938ae0dbe7955dc35931cf..8d14c3a359963f4765a1a5bd48418d52f562cd80 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-rev.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types-rev.ll @@ -1,7 +1,4 @@ -; The goal of the test case is to ensure that OpPhi is consistent with respect to operand types. -; -verify-machineinstrs is not available due to mutually exclusive requirements for G_BITCAST and G_PHI. - -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#Char:]] = OpTypeInt 8 0 diff --git a/llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types.ll b/llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types.ll index 4fbaae2556730010568813ba52cad302772ac2b6..07824d4ed6cd850593251856b6d9e5d73a1ca877 100644 --- a/llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types.ll +++ b/llvm/test/CodeGen/SPIRV/pointers/phi-valid-operand-types.ll @@ -1,7 +1,4 @@ -; The goal of the test case is to ensure that OpPhi is consistent with respect to operand types. -; -verify-machineinstrs is not available due to mutually exclusive requirements for G_BITCAST and G_PHI. - -; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} ; CHECK: %[[#Char:]] = OpTypeInt 8 0 diff --git a/llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll b/llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll new file mode 100644 index 0000000000000000000000000000000000000000..5585e4a07590a38dc71332dfd5643005bc7d45c5 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/basic-if.ll @@ -0,0 +1,52 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target triple = "spirv-unknown-vulkan1.3-compute" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK: %[[#entry:]] = OpLabel +; CHECK: OpSelectionMerge %[[#merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#right:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %1 = alloca i32, align 4 + br i1 true, label %left, label %right + +; CHECK: %[[#left]] = OpLabel +; CHECK: OpBranch %[[#merge]] +left: + store i32 0, ptr %1 + br label %end + +; CHECK: %[[#right]] = OpLabel +; CHECK: OpBranch %[[#merge]] +right: + store i32 0, ptr %1 + br label %end + +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturnValue %[[#]] +end: + ret i32 0 +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.entry() #1 + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.loop() #1 + + +attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { convergent } + +!llvm.module.flags = !{!0, !1, !2} + + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{i32 7, !"frame-pointer", i32 2} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/basic-imbalanced-if.ll b/llvm/test/CodeGen/SPIRV/structurizer/basic-imbalanced-if.ll new file mode 100644 index 0000000000000000000000000000000000000000..810b5785e4b1a48fbcf400f3d65fb72463c0a25e --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/basic-imbalanced-if.ll @@ -0,0 +1,47 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK: %[[#entry:]] = OpLabel +; CHECK: OpSelectionMerge %[[#merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#merge]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %1 = alloca i32, align 4 + br i1 true, label %left, label %end + +; CHECK: %[[#left]] = OpLabel +; CHECK: OpBranch %[[#merge]] +left: + store i32 0, ptr %1 + br label %end + +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturnValue %[[#]] +end: + ret i32 0 +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.entry() #1 + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.loop() #1 + + +attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { convergent } + +!llvm.module.flags = !{!0, !1, !2} + + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{i32 7, !"frame-pointer", i32 2} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll b/llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll new file mode 100644 index 0000000000000000000000000000000000000000..ded9c335c5a25fda50fe86ab4a782a1802a4ee6b --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/basic-loop.ll @@ -0,0 +1,59 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK: %[[#entry:]] = OpLabel +; CHECK: OpBranch %[[#header:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %1 = alloca i32, align 4 + br label %header + +; CHECK: %[[#header]] = OpLabel +; CHECK: OpLoopMerge %[[#merge:]] %[[#continue:]] None +; CHECK: OpBranchConditional %[[#]] %[[#body:]] %[[#merge]] +header: + %2 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] + br i1 true, label %body, label %merge + +; CHECK: %[[#body]] = OpLabel +; CHECK: OpBranch %[[#continue]] +body: + store i32 0, ptr %1 + br label %continue + +continue: + br label %header +; CHECK: %[[#continue]] = OpLabel +; CHECK: OpBranch %[[#header]] + +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturnValue %[[#]] +merge: + ret i32 0 +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.entry() #1 + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.loop() #1 + + +attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { convergent } + +!llvm.module.flags = !{!0, !1, !2} + + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{i32 7, !"frame-pointer", i32 2} + diff --git a/llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll b/llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll new file mode 100644 index 0000000000000000000000000000000000000000..a43d25e9b06d5dae1265423b93c601aa66f3ec52 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/basic-phi.ll @@ -0,0 +1,58 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +; Function Attrs: convergent noinline norecurse nounwind optnone +define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0 +; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1 + +; CHECK: %[[#entry:]] = OpLabel +; CHECK: %[[#var:]] = OpVariable %[[#]] Function +; CHECK: OpSelectionMerge %[[#merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#right:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + br i1 true, label %left, label %right + +; CHECK: %[[#left]] = OpLabel +; CHECK-NEXT: OpStore %[[#var]] %[[#int_0]] +; CHECK-NEXT: OpBranch %[[#merge]] +left: + br label %end + +; CHECK: %[[#right]] = OpLabel +; CHECK-NEXT: OpStore %[[#var]] %[[#int_1]] +; CHECK-NEXT: OpBranch %[[#merge]] +right: + br label %end + +; CHECK: %[[#merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#var]] +; CHECK: OpReturnValue %[[#tmp]] +end: + %1 = phi i32 [ 0, %left ], [ 1, %right ] + ret i32 %1 +} + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.entry() #1 + +; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none) +declare token @llvm.experimental.convergence.loop() #1 + + +attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } +attributes #3 = { convergent } + +!llvm.module.flags = !{!0, !1, !2} + + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} +!2 = !{i32 7, !"frame-pointer", i32 2} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll index 4934b17c8c002e3b1373131bceca8470e8604101..86033608deb6e292c49ad8fff4d6bf30a1ccfb24 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.cond-op.ll @@ -8,16 +8,17 @@ target triple = "spirv-unknown-vulkan1.3-compute" ; CHECK-DAG: OpName %[[#fn:]] "_Z2fnv" ; CHECK-DAG: OpName %[[#fn1:]] "_Z3fn1v" ; CHECK-DAG: OpName %[[#fn2:]] "_Z3fn2v" -; CHECK-DAG: OpName %[[#val:]] "val" -; CHECK-DAG: OpName %[[#a:]] "a" -; CHECK-DAG: OpName %[[#b:]] "b" -; CHECK-DAG: OpName %[[#c:]] "c" + +; CHECK-DAG: OpName %[[#r2m_a:]] ".reg2mem3" +; CHECK-DAG: OpName %[[#r2m_b:]] ".reg2mem1" +; CHECK-DAG: OpName %[[#r2m_c:]] ".reg2mem" ; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool -; CHECK-DAG: %[[#int_pfty:]] = OpTypePointer Function %[[#int_ty]] -; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0 +; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1 +; CHECK-DAG: %[[#true:]] = OpConstantTrue +; CHECK-DAG: %[[#false:]] = OpConstantFalse declare token @llvm.experimental.convergence.entry() #1 @@ -44,100 +45,86 @@ entry: ; CHECK: %[[#process]] = OpFunction %[[#int_ty]] define spir_func noundef i32 @_Z7processv() #0 { + +; CHECK: %[[#entry:]] = OpLabel +; CHECK-DAG: %[[#r2m_a]] = OpVariable %[[#]] Function +; CHECK: OpSelectionMerge %[[#a_merge:]] +; CHECK: OpBranchConditional %[[#]] %[[#a_true:]] %[[#a_false:]] entry: - ; CHECK: %[[#entry:]] = OpLabel %0 = call token @llvm.experimental.convergence.entry() - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - %val = alloca i32, align 4 - store i32 0, ptr %a, align 4 - store i32 1, ptr %b, align 4 - store i32 2, ptr %c, align 4 - store i32 0, ptr %val, align 4 - ; CHECK-DAG: %[[#a]] = OpVariable %[[#int_pfty]] Function - ; CHECK-DAG: %[[#b]] = OpVariable %[[#int_pfty]] Function - ; CHECK-DAG: %[[#c]] = OpVariable %[[#int_pfty]] Function - ; CHECK-DAG: %[[#val]] = OpVariable %[[#int_pfty]] Function - %1 = load i32, ptr %a, align 4 - %tobool = icmp ne i32 %1, 0 - br i1 %tobool, label %cond.true, label %cond.false - ; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#a]] - ; CHECK: %[[#cond:]] = OpINotEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] - ; CHECK: OpSelectionMerge %[[#cond_end:]] - ; CHECK: OpBranchConditional %[[#cond]] %[[#cond_true:]] %[[#cond_false:]] - -cond.true: ; preds = %entry - %2 = load i32, ptr %b, align 4 - br label %cond.end - ; CHECK: %[[#cond_true]] = OpLabel - ; CHECK: OpBranch %[[#cond_end]] - -cond.false: ; preds = %entry - %3 = load i32, ptr %c, align 4 - br label %cond.end - ; CHECK: %[[#cond_false]] = OpLabel - ; CHECK: %[[#load_c:]] = OpLoad %[[#]] %[[#c]] - ; CHECK: OpBranch %[[#cond_end]] - -cond.end: ; preds = %cond.false, %cond.true - %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] - %tobool1 = icmp ne i32 %cond, 0 - br i1 %tobool1, label %if.then, label %if.end - ; CHECK: %[[#cond_end]] = OpLabel - ; CHECK: %[[#tmp:]] = OpPhi %[[#int_ty]] %[[#load_b:]] %[[#cond_true]] %[[#load_c]] %[[#cond_false]] - ; CHECK: OpSelectionMerge %[[#if_end:]] - ; CHECK: OpBranchConditional %[[#]] %[[#if_then:]] %[[#if_end]] - -if.then: ; preds = %cond.end - %4 = load i32, ptr %val, align 4 - %inc = add nsw i32 %4, 1 - store i32 %inc, ptr %val, align 4 - br label %if.end - ; CHECK: %[[#if_then]] = OpLabel - ; CHECK: OpBranch %[[#if_end]] - -if.end: ; preds = %if.then, %cond.end - %call2 = call spir_func noundef i32 @_Z2fnv() #4 [ "convergencectrl"(token %0) ] - %tobool3 = icmp ne i32 %call2, 0 - br i1 %tobool3, label %cond.true4, label %cond.false6 - ; CHECK: %[[#if_end]] = OpLabel - ; CHECK: OpSelectionMerge %[[#cond_end8:]] - ; CHECK: OpBranchConditional %[[#]] %[[#cond_true4:]] %[[#cond_false6:]] - -cond.true4: ; preds = %if.end - %call5 = call spir_func noundef i32 @_Z3fn1v() #4 [ "convergencectrl"(token %0) ] - br label %cond.end8 - ; CHECK: %[[#cond_true4]] = OpLabel - ; CHECK: OpBranch %[[#cond_end8]] - -cond.false6: ; preds = %if.end - %call7 = call spir_func noundef i32 @_Z3fn2v() #4 [ "convergencectrl"(token %0) ] - br label %cond.end8 - ; CHECK: %[[#cond_false6]] = OpLabel - ; CHECK: OpBranch %[[#cond_end8]] - -cond.end8: ; preds = %cond.false6, %cond.true4 - %cond9 = phi i32 [ %call5, %cond.true4 ], [ %call7, %cond.false6 ] - %tobool10 = icmp ne i32 %cond9, 0 - br i1 %tobool10, label %if.then11, label %if.end13 - ; CHECK: %[[#cond_end8]] = OpLabel - ; CHECK: OpSelectionMerge %[[#if_end13:]] - ; CHECK: OpBranchConditional %[[#]] %[[#if_then11:]] %[[#if_end13]] - -if.then11: ; preds = %cond.end8 - %5 = load i32, ptr %val, align 4 - %inc12 = add nsw i32 %5, 1 - store i32 %inc12, ptr %val, align 4 - br label %if.end13 - ; CHECK: %[[#if_then11]] = OpLabel - ; CHECK: OpBranch %[[#if_end13]] - -if.end13: ; preds = %if.then11, %cond.end8 - %6 = load i32, ptr %val, align 4 - ret i32 %6 - ; CHECK: %[[#if_end13]] = OpLabel - ; CHECK: OpReturnValue + %var = alloca i32 + br i1 true, label %a_true, label %a_false + +; CHECK: %[[#a_true]] = OpLabel +; CHECK: OpStore %[[#r2m_a]] %[[#true]] +; CHECK: OpBranch %[[#a_merge]] +a_true: + br label %a_merge + +; CHECK: %[[#a_false]] = OpLabel +; CHECK: OpStore %[[#r2m_a]] %[[#false]] +; CHECK: OpBranch %[[#a_merge]] +a_false: + br label %a_merge + +; CHECK: %[[#a_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#r2m_a]] +; CHECK: OpSelectionMerge %[[#b_merge:]] +; CHECK: OpBranchConditional %[[#]] %[[#b_true:]] %[[#b_merge]] +a_merge: + %1 = phi i1 [ true, %a_true ], [ false, %a_false ] + br i1 %1, label %b_true, label %b_merge + +; CHECK: %[[#b_true]] = OpLabel +; CHECK: OpBranch %[[#b_merge]] +b_true: + store i32 0, ptr %var ; Prevents whole branch optimization. + br label %b_merge + +; CHECK: %[[#b_merge]] = OpLabel +; CHECK: OpFunctionCall +; CHECK: OpSelectionMerge %[[#c_merge:]] +; CHECK: OpBranchConditional %[[#]] %[[#c_true:]] %[[#c_false:]] +b_merge: + %f1 = call spir_func noundef i32 @_Z2fnv() #4 [ "convergencectrl"(token %0) ] + br i1 true, label %c_true, label %c_false + +; CHECK: %[[#c_true]] = OpLabel +; CHECK: %[[#]] = OpFunctionCall +; CHECK: OpStore %[[#r2m_b]] %[[#]] +; CHECK: OpBranch %[[#c_merge]] +c_true: + %f2 = call spir_func noundef i32 @_Z3fn1v() #4 [ "convergencectrl"(token %0) ] + br label %c_merge + +; CHECK: %[[#c_false]] = OpLabel +; CHECK: %[[#]] = OpFunctionCall +; CHECK: OpStore %[[#r2m_b]] %[[#]] +; CHECK: OpBranch %[[#c_merge]] +c_false: + %f3 = call spir_func noundef i32 @_Z3fn2v() #4 [ "convergencectrl"(token %0) ] + br label %c_merge + +; CHECK: %[[#c_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#r2m_b]] +; CHECK: OpStore %[[#r2m_c]] %[[#tmp:]] +; CHECK: OpSelectionMerge %[[#d_merge:]] +; CHECK: OpBranchConditional %[[#]] %[[#d_true:]] %[[#d_merge]] +c_merge: + %5 = phi i32 [ %f2, %c_true ], [ %f3, %c_false ] + br i1 true, label %d_true, label %d_merge + +; CHECK: %[[#d_true]] = OpLabel +; CHECK: OpBranch %[[#d_merge]] +d_true: + store i32 0, ptr %var ; Prevents whole branch optimization. + br label %d_merge + +; CHECK: %[[#d_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#r2m_c]] +; CHECK: OpReturnValue %[[#tmp]] +d_merge: + ret i32 %5 } ; Function Attrs: convergent noinline norecurse nounwind optnone diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll index 3fc440dc445e149714f46b0efa8aca8457941b9c..8e05bf1ebdaa7c8818562d8386d808812848d6a6 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.break.ll @@ -1,5 +1,4 @@ ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=2 ; int foo() { return true; } ; diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll index 051f0685a40426f9a4a4d8baa7eb2e99e724d10e..36b61745fa55afe05cf4e06d39e8809b69d6f977 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.continue.ll @@ -1,4 +1,3 @@ -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=10 ; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %} ; ; Source HLSL: diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll index a28e1c7b942de0984772a1c8ce43da9fd53ae9fc..d8e17c2291a7c648e27fa26811cf34e987e3b64c 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.do.nested.ll @@ -1,5 +1,4 @@ ; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=142 ; ; Source HLSL: ; diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll index f2e60f916c795be814cdc733efad3cdb0b758570..9d8cab44c0cbb5dcfa4de5c725bf01e4d7a944af 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.break.ll @@ -1,5 +1,4 @@ ; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=4 ; ; Source HLSL: ; diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll index 31a3433cae4c0732ace7be65918644d10e45bc3e..12e6473c15c7570e2433d192d717254934e6d287 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.continue.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=19 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll index 1619a519273b376605aef4701ce78a14329bd85b..ddd4c5222301a3d483752d450cca9b68e6062116 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.nested.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=2563170 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll index 1b5e868317fba5a0a59eb5abe7e3bcc38c10d8f9..07c20ebadd159e5dc1c6a4517dcad73583552a87 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.for.short-circuited-cond.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=9 ; ; int process() { @@ -139,10 +138,10 @@ ; CHECK: OpBranchConditional %[[#]] %[[#bb130:]] %[[#bb125:]] ; CHECK: %[[#bb130:]] = OpLabel ; CHECK: OpBranch %[[#bb126:]] -; CHECK: %[[#bb125:]] = OpLabel -; CHECK: OpReturnValue %[[#]] ; CHECK: %[[#bb126:]] = OpLabel ; CHECK: OpBranch %[[#bb124:]] +; CHECK: %[[#bb125:]] = OpLabel +; CHECK: OpReturnValue %[[#]] ; CHECK: OpFunctionEnd ; CHECK: %[[#func_83:]] = OpFunction %[[#void:]] DontInline %[[#]] ; CHECK: %[[#bb131:]] = OpLabel diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll index f3a9109b06ee2e74b1fc30ae51b3c7f7326fbcbd..df406917fdff971021efe9ac7adf7eb381dbcd00 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.const-cond.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=3 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll index 42c885070453ac724034e8fe8f43ec2d00f72b0b..93effc141fc812a996f80f004a887f7fa505d428 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.for.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=6 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll index 1fea1ebd888f5cbb9b5fd0ddf2eaa4e68c2da049..a69475a59db6f45010f3e2a2f180283f6ca77970 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.nested.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=3 ; diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll index c3b0caa4e269477eeec2d0ea727e98cda2b58e80..8fa8c2c14878bf051fabaf820df6a8b2e97d0f05 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.if.plain.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=2 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll index a5f00071ca27127cfe526e4876bddec5a7056a70..9d35fb3c82b0779e8f34a2fa6c075e6bc9b76834 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-and.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=1 ; ; int fn() { return true; } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll index 73db1c897711fad90476768074fb503b979d7e8d..0a986661e50d5b26c97c8dab4c4ca756f66ef45a 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.logical-or.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=3 ; ; int fn() { return true; } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll index 62d18cdf538c374b6cacc5ca691ad122436ec3db..dfaca85be2280c5c7d0f3401c3d609dd032d4676 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.return.early.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=0 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll index d2447fe4562435fb6303f94aa8f59f0afb90e365..8e2a0506d286d6c7fae6c486f6d03f97d5ccdc55 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=308 ; ; int foo() { return 200; } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll index 74c5a2edf7c2fb7831c9ea01aa48877c20e9a206..125e3f751315eb35c0b0146a9f74d0fa70726d18 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=5 ; ; int process() { diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll index bfe3b45779afb69f6d19c9b86b46d14c899b262a..cf50b982b23dc8bec8d258540b60630133fd8834 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.switch.ifstmt.simple2.ll @@ -1,6 +1,5 @@ ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-sim --function=_Z7processv --wave=1 --expects=5 ; ; int foo() { return 200; } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll b/llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll index 8f3981a2449682e8a5b68233aaf73577994c945a..769be32c9fc41e76ba144fa0e775b69f5543ea65 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/cf.while.break.ll @@ -41,47 +41,45 @@ ; } ; CHECK: %[[#func_16:]] = OpFunction %[[#uint:]] DontInline %[[#]] -; CHECK: %[[#bb37:]] = OpLabel +; CHECK: %[[#bb44:]] = OpLabel ; CHECK: OpReturnValue %[[#]] ; CHECK: OpFunctionEnd -; CHECK: %[[#func_17:]] = OpFunction %[[#void:]] DontInline %[[#]] -; CHECK: %[[#bb38:]] = OpLabel -; CHECK: OpBranch %[[#bb39:]] -; CHECK: %[[#bb39:]] = OpLabel -; CHECK: OpLoopMerge %[[#bb40:]] %[[#bb41:]] None -; CHECK: OpBranchConditional %[[#]] %[[#bb42:]] %[[#bb40:]] -; CHECK: %[[#bb42:]] = OpLabel -; CHECK: OpBranchConditional %[[#]] %[[#bb40:]] %[[#bb43:]] -; CHECK: %[[#bb43:]] = OpLabel -; CHECK: OpBranchConditional %[[#]] %[[#bb40:]] %[[#bb41:]] -; CHECK: %[[#bb40:]] = OpLabel -; CHECK: OpSelectionMerge %[[#bb44:]] None -; CHECK: OpSwitch %[[#]] %[[#bb44:]] 1 %[[#bb44:]] 2 %[[#bb44:]] -; CHECK: %[[#bb41:]] = OpLabel -; CHECK: OpBranch %[[#bb39:]] -; CHECK: %[[#bb44:]] = OpLabel -; CHECK: OpBranch %[[#bb45:]] +; CHECK: %[[#func_19:]] = OpFunction %[[#void:]] DontInline %[[#]] ; CHECK: %[[#bb45:]] = OpLabel ; CHECK: OpBranch %[[#bb46:]] ; CHECK: %[[#bb46:]] = OpLabel -; CHECK: OpBranch %[[#bb47:]] -; CHECK: %[[#bb47:]] = OpLabel -; CHECK: OpSelectionMerge %[[#bb48:]] None -; CHECK: OpBranchConditional %[[#]] %[[#bb49:]] %[[#bb48:]] +; CHECK: OpLoopMerge %[[#bb47:]] %[[#bb48:]] None +; CHECK: OpBranchConditional %[[#]] %[[#bb49:]] %[[#bb47:]] ; CHECK: %[[#bb49:]] = OpLabel -; CHECK: OpBranch %[[#bb48:]] -; CHECK: %[[#bb48:]] = OpLabel -; CHECK: OpBranch %[[#bb50:]] +; CHECK: OpBranchConditional %[[#]] %[[#bb47:]] %[[#bb50:]] ; CHECK: %[[#bb50:]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#bb47:]] %[[#bb48:]] +; CHECK: %[[#bb48:]] = OpLabel +; CHECK: OpBranch %[[#bb46:]] +; CHECK: %[[#bb47:]] = OpLabel +; CHECK: OpSelectionMerge %[[#bb51:]] None +; CHECK: OpSwitch %[[#]] %[[#bb51:]] 1 %[[#bb51:]] 2 %[[#bb51:]] +; CHECK: %[[#bb51:]] = OpLabel +; CHECK: OpBranch %[[#bb52:]] +; CHECK: %[[#bb52:]] = OpLabel +; CHECK: OpBranch %[[#bb53:]] +; CHECK: %[[#bb53:]] = OpLabel +; CHECK: OpBranch %[[#bb54:]] +; CHECK: %[[#bb54:]] = OpLabel +; CHECK: OpSelectionMerge %[[#bb55:]] None +; CHECK: OpBranchConditional %[[#]] %[[#bb56:]] %[[#bb55:]] +; CHECK: %[[#bb56:]] = OpLabel +; CHECK: OpBranch %[[#bb55:]] +; CHECK: %[[#bb55:]] = OpLabel +; CHECK: OpBranch %[[#bb57:]] +; CHECK: %[[#bb57:]] = OpLabel ; CHECK: OpReturn ; CHECK: OpFunctionEnd -; CHECK: %[[#func_35:]] = OpFunction %[[#void:]] None %[[#]] -; CHECK: %[[#bb51:]] = OpLabel +; CHECK: %[[#func_40:]] = OpFunction %[[#void:]] None %[[#]] +; CHECK: %[[#bb58:]] = OpLabel ; CHECK: OpReturn ; CHECK: OpFunctionEnd - - target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" diff --git a/llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll b/llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll index faab2553ae6f511de64c93fd4ea1aa91b0539898..71f3ce9263da5610aac7f2fb134038eb234505c7 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/condition-linear.ll @@ -1,5 +1,5 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan-compute" @@ -25,90 +25,92 @@ entry: ret i32 1 } + +; CHECK-DAG: OpName %[[#reg_0:]] "cond.reg2mem" +; CHECK-DAG: OpName %[[#reg_1:]] "cond9.reg2mem" + define internal spir_func void @main() #0 { -; CHECK: %[[#cond:]] = OpINotEqual %[[#bool_ty:]] %[[#a:]] %[[#b:]] -; CHECK: OpSelectionMerge %[[#cond_end:]] None -; CHECK: OpBranchConditional %[[#cond]] %[[#cond_true:]] %[[#cond_false:]] +; CHECK: OpSelectionMerge %[[#cond1_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#cond1_true:]] %[[#cond1_false:]] entry: %0 = call token @llvm.experimental.convergence.entry() %a = alloca i32, align 4 %b = alloca i32, align 4 - %c = alloca i32, align 4 - %val = alloca i32, align 4 - store i32 0, ptr %val, align 4 - %1 = load i32, ptr %a, align 4 - %tobool = icmp ne i32 %1, 0 - br i1 %tobool, label %cond.true, label %cond.false - -; CHECK: %[[#cond_true]] = OpLabel -; CHECK: OpBranch %[[#cond_end]] -cond.true: - %2 = load i32, ptr %b, align 4 - br label %cond.end - -; CHECK: %[[#cond_false]] = OpLabel -; CHECK: OpBranch %[[#cond_end]] -cond.false: - %3 = load i32, ptr %c, align 4 - br label %cond.end - -; CHECK: %[[#cond_end]] = OpLabel -; CHECK: %[[#tmp:]] = OpPhi %[[#int_ty:]] %[[#load_cond_true:]] %[[#cond_true]] %[[#load_cond_false:]] %[[#cond_false:]] -; CHECK: %[[#cond:]] = OpINotEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0:]] -; CHECK: OpSelectionMerge %[[#if_end:]] None -; CHECK: OpBranchConditional %[[#cond]] %[[#if_then:]] %[[#if_end]] -cond.end: - %cond = phi i32 [ %2, %cond.true ], [ %3, %cond.false ] + br i1 true, label %cond1_true, label %cond1_false + +; CHECK: %[[#cond1_true]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] +; CHECK: OpBranch %[[#cond1_merge]] +cond1_true: + %2 = load i32, ptr %a, align 4 + br label %cond1_merge + +; CHECK: %[[#cond1_false]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] +; CHECK: OpBranch %[[#cond1_merge]] +cond1_false: + %3 = load i32, ptr %b, align 4 + br label %cond1_merge + +; CHECK: %[[#cond1_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#reg_0]] +; CHECK: %[[#cond:]] = OpINotEqual %[[#]] %[[#tmp]] %[[#]] +; CHECK: OpSelectionMerge %[[#cond2_merge:]] None +; CHECK: OpBranchConditional %[[#cond]] %[[#cond2_true:]] %[[#cond2_merge]] +cond1_merge: + %cond = phi i32 [ %2, %cond1_true ], [ %3, %cond1_false ] %tobool1 = icmp ne i32 %cond, 0 - br i1 %tobool1, label %if.then, label %if.end - -; CHECK: %[[#if_then]] = OpLabel -; CHECK: OpBranch %[[#if_end]] -if.then: - %4 = load i32, ptr %val, align 4 - %inc = add nsw i32 %4, 1 - store i32 %inc, ptr %val, align 4 - br label %if.end - -; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpSelectionMerge %[[#cond_end8:]] None -; CHECK: OpBranchConditional %[[#tmp:]] %[[#cond4_true:]] %[[#cond_false6:]] -if.end: + br i1 %tobool1, label %cond2_true, label %cond2_merge + +; CHECK: %[[#cond2_true]] = OpLabel +; CHECK: OpBranch %[[#cond2_merge]] +cond2_true: + store i32 0, ptr %a + br label %cond2_merge + +; CHECK: %[[#cond2_merge]] = OpLabel +; CHECK: OpFunctionCall +; CHECK: OpSelectionMerge %[[#cond3_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#cond3_true:]] %[[#cond3_false:]] +cond2_merge: %call2 = call spir_func noundef i32 @fn() #4 [ "convergencectrl"(token %0) ] - %tobool3 = icmp ne i32 %call2, 0 - br i1 %tobool3, label %cond.true4, label %cond.false6 + br i1 true, label %cond3_true, label %cond3_false -; CHECK: %[[#cond4_true]] = OpLabel -; CHECK: OpBranch %[[#cond_end8]] -cond.true4: +; CHECK: %[[#cond3_true]] = OpLabel +; CHECK: OpFunctionCall +; CHECK: OpStore %[[#reg_1]] %[[#]] +; CHECK: OpBranch %[[#cond3_merge]] +cond3_true: %call5 = call spir_func noundef i32 @fn1() #4 [ "convergencectrl"(token %0) ] - br label %cond.end8 + br label %cond3_merge -; CHECK: %[[#cond_false6]] = OpLabel -; CHECK: OpBranch %[[#cond_end8]] -cond.false6: +; CHECK: %[[#cond3_false]] = OpLabel +; CHECK: OpFunctionCall +; CHECK: OpStore %[[#reg_1]] %[[#]] +; CHECK: OpBranch %[[#cond3_merge]] +cond3_false: %call7 = call spir_func noundef i32 @fn2() #4 [ "convergencectrl"(token %0) ] - br label %cond.end8 - -; CHECK: %[[#cond_end8]] = OpLabel -; CHECK: OpSelectionMerge %[[#if_end13:]] None -; CHECK: OpBranchConditional %[[#tmp:]] %[[#if_then11:]] %[[#if_end13]] -cond.end8: - %cond9 = phi i32 [ %call5, %cond.true4 ], [ %call7, %cond.false6 ] + br label %cond3_merge + +; CHECK: %[[#cond3_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#reg_1]] +; CHECK: %[[#cond:]] = OpINotEqual %[[#]] %[[#tmp]] %[[#]] +; CHECK: OpSelectionMerge %[[#cond4_merge:]] None +; CHECK: OpBranchConditional %[[#cond]] %[[#cond4_true:]] %[[#cond4_merge]] +cond3_merge: + %cond9 = phi i32 [ %call5, %cond3_true ], [ %call7, %cond3_false ] %tobool10 = icmp ne i32 %cond9, 0 - br i1 %tobool10, label %if.then11, label %if.end13 + br i1 %tobool10, label %cond4_true, label %cond4_merge -; CHECK: %[[#if_then11]] = OpLabel -; CHECK: OpBranch %[[#if_end13]] -if.then11: - %5 = load i32, ptr %val, align 4 - %inc12 = add nsw i32 %5, 1 - store i32 %inc12, ptr %val, align 4 - br label %if.end13 +; CHECK: %[[#cond4_true]] = OpLabel +; CHECK: OpBranch %[[#cond4_merge]] +cond4_true: + store i32 0, ptr %a + br label %cond4_merge -; CHECK: %[[#if_end13]] = OpLabel +; CHECK: %[[#cond4_merge]] = OpLabel ; CHECK: OpReturn -if.end13: +cond4_merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll b/llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll index d547ad8eded9761a4658220cc8d257625263224b..05071d03164d5f36c10724d7d97555d3d3cc7b5f 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/do-continue.ll @@ -1,5 +1,5 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" @@ -12,100 +12,98 @@ entry: define internal spir_func void @main() #2 { ; CHECK: %[[#entry:]] = OpLabel -; CHECK: OpBranch %[[#do_body:]] +; CHECK: OpBranch %[[#do_header:]] entry: %0 = call token @llvm.experimental.convergence.entry() - %val = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 0, ptr %val, align 4 - store i32 0, ptr %i, align 4 - br label %do.body + %var = alloca i32, align 4 + br label %do_header +; Here a the loop header had to be split in two: +; - 1 header for the loop +; - 1 header for the condition. +; In SPIR-V, a loop header cannot directly ; CHECK: %[[#do_header:]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end:]] %[[#do_cond:]] None -; CHECK: OpBranch %[[#do_body:]] +; CHECK: OpLoopMerge %[[#do_merge:]] %[[#do_latch:]] None +; CHECK: OpBranch %[[#new_header:]] -; CHECK: %[[#do_body]] = OpLabel -; CHECK: OpSelectionMerge %[[#if_then:]] None -; CHECK: OpBranchConditional %[[#cond:]] %[[#if_then]] %[[#if_end:]] -do.body: +; CHECK: %[[#new_header]] = OpLabel +; CHECK: OpSelectionMerge %[[#if_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#if_then:]] %[[#if_end:]] +do_header: %1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - %2 = load i32, ptr %i, align 4 - %inc = add nsw i32 %2, 1 - store i32 %inc, ptr %i, align 4 - %3 = load i32, ptr %i, align 4 - %cmp = icmp sgt i32 %3, 5 - br i1 %cmp, label %if.then, label %if.end + store i32 0, ptr %var + br i1 true, label %if.then, label %if.end + +; CHECK: %[[#if_then]] = OpLabel +; CHECK: OpBranch %[[#if_merge]] +if.then: + store i32 0, ptr %var + br label %do_latch ; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpBranch %[[#if_then]] +; CHECK: OpBranch %[[#if_merge]] if.end: - %4 = load i32, ptr %i, align 4 - store i32 %4, ptr %val, align 4 - br label %do.cond + store i32 0, ptr %var + br label %do_latch -; CHECK: %[[#if_then]] = OpLabel -; CHECK: OpBranch %[[#do_cond]] -if.then: - br label %do.cond +; CHECK: %[[#if_merge]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do_latch]] %[[#do_merge]] -; CHECK: %[[#do_cond]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_header]] %[[#do_end]] -do.cond: - %5 = load i32, ptr %i, align 4 - %cmp1 = icmp slt i32 %5, 10 - br i1 %cmp1, label %do.body, label %do.end +; CHECK: %[[#do_latch]] = OpLabel +; CHECK: OpBranch %[[#do_header]] +do_latch: + store i32 0, ptr %var + br i1 true, label %do_header, label %do.end -; CHECK: %[[#do_end]] = OpLabel -; CHECK: OpBranch %[[#do_body2:]] +; CHECK: %[[#do_merge]] = OpLabel +; CHECK: OpBranch %[[#do2_header:]] do.end: - br label %do.body2 + store i32 0, ptr %var + br label %do2_header -; CHECK: %[[#do_body2]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end11:]] %[[#do_cond9:]] None -; CHECK: OpBranch %[[#do_body4:]] -do.body2: +; CHECK: %[[#do2_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do2_merge:]] %[[#do2_continue:]] None +; CHECK: OpBranch %[[#do3_header:]] +do2_header: %6 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - %7 = load i32, ptr %i, align 4 - %inc3 = add nsw i32 %7, 1 - store i32 %inc3, ptr %i, align 4 - br label %do.body4 - -; CHECK: %[[#do_body4]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end8:]] %[[#do_cond6:]] None -; CHECK: OpBranch %[[#do_cond6]] -do.body4: + store i32 0, ptr %var + br label %do3_header + +; CHECK: %[[#do3_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do3_merge:]] %[[#do3_continue:]] None +; CHECK: OpBranch %[[#do3_body:]] +do3_header: %8 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %6) ] - %9 = load i32, ptr %val, align 4 - %inc5 = add nsw i32 %9, 1 - store i32 %inc5, ptr %val, align 4 - br label %do.cond6 - -; CHECK: %[[#do_cond6]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body4]] %[[#do_end8]] -do.cond6: - %10 = load i32, ptr %i, align 4 - %cmp7 = icmp slt i32 %10, 10 - br i1 %cmp7, label %do.body4, label %do.end8 - -; CHECK: %[[#do_end8]] = OpLabel -; CHECK: OpBranch %[[#do_cond9]] -do.end8: - %11 = load i32, ptr %i, align 4 - %dec = add nsw i32 %11, -1 - store i32 %dec, ptr %i, align 4 - br label %do.cond9 - -; CHECK: %[[#do_cond9]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body2]] %[[#do_end11]] -do.cond9: - %12 = load i32, ptr %val, align 4 - %cmp10 = icmp slt i32 %12, 10 - br i1 %cmp10, label %do.body2, label %do.end11 - -; CHECK: %[[#do_end11]] = OpLabel -; CHECK: OpReturn -do.end11: + store i32 0, ptr %var + br label %do3_continue + +; CHECK: %[[#do3_body]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do3_continue]] %[[#do3_merge]] + +; CHECK: %[[#do3_continue]] = OpLabel +; CHECK: OpBranch %[[#do3_header]] +do3_continue: + store i32 0, ptr %var + br i1 true, label %do3_header, label %do3_merge + +; CHECK: %[[#do3_merge]] = OpLabel +; CHECK: OpBranch %[[#do2_new_latch:]] +do3_merge: + store i32 0, ptr %var + br label %do2_continue + +; CHECK: %[[#do2_new_latch]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do2_continue]] %[[#do2_merge]] + +; CHECK: %[[#do2_continue]] = OpLabel +; CHECK: OpBranch %[[#do2_header]] +do2_continue: + store i32 0, ptr %var + br i1 true, label %do2_header, label %do2_merge + +; CHECK: %[[#do2_merge]] = OpLabel +; CHECK: OpReturn +do2_merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll b/llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll index a16eed5cdfb4ce8f0232af6e834009e81fc143f8..bef95f5f63bf7bfe8f449fb6f1453ba03d8ea3ff 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/do-nested.ll @@ -1,5 +1,5 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" @@ -8,84 +8,72 @@ define internal spir_func void @main() #0 { ; CHECK: %[[#entry:]] = OpLabel entry: %0 = call token @llvm.experimental.convergence.entry() - %val = alloca i32, align 4 - %i = alloca i32, align 4 - %j = alloca i32, align 4 - %k = alloca i32, align 4 - store i32 0, ptr %val, align 4 - store i32 0, ptr %i, align 4 - store i32 0, ptr %j, align 4 - store i32 0, ptr %k, align 4 - br label %do.body + %var = alloca i32, align 4 + br label %do1_header -; CHECK: %[[#do_1_header:]] = OpLabel -; CHECK: OpLoopMerge %[[#end:]] %[[#do_1_latch:]] None -; CHECK: OpBranch %[[#do_2_header:]] -do.body: +; CHECK: %[[#do1_header:]] = OpLabel +; CHECK: OpLoopMerge %[[#do1_merge:]] %[[#do1_continue:]] None +; CHECK: OpBranch %[[#do2_header:]] +do1_header: %1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - %2 = load i32, ptr %val, align 4 - %3 = load i32, ptr %i, align 4 - %add = add nsw i32 %2, %3 - store i32 %add, ptr %val, align 4 - br label %do.body1 + store i32 0, ptr %var + br label %do2_header -; CHECK: %[[#do_2_header]] = OpLabel -; CHECK: OpLoopMerge %[[#do_2_end:]] %[[#do_2_latch:]] None -; CHECK: OpBranch %[[#do_2_body:]] -do.body1: +; CHECK: %[[#do2_header:]] = OpLabel +; CHECK: OpLoopMerge %[[#do2_merge:]] %[[#do2_continue:]] None +; CHECK: OpBranch %[[#do3_header:]] +do2_header: %4 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %1) ] - br label %do.body2 + store i32 0, ptr %var + br label %do3_header -; CHECK: %[[#do_2_body]] = OpLabel -; CHECK: OpLoopMerge %[[#do_3_end:]] %[[#do_3_header:]] None -; CHECK: OpBranch %[[#do_3_header]] -do.body2: +; CHECK: %[[#do3_header:]] = OpLabel +; CHECK: OpLoopMerge %[[#do3_merge:]] %[[#do3_continue:]] None +; CHECK: OpBranch %[[#do3_cond:]] +do3_header: %5 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %4) ] - %6 = load i32, ptr %k, align 4 - %inc = add nsw i32 %6, 1 - store i32 %inc, ptr %k, align 4 - br label %do.cond + store i32 0, ptr %var + br label %do3_continue -; CHECK: %[[#do_3_header]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_2_body]] %[[#do_3_end]] -do.cond: - %7 = load i32, ptr %k, align 4 - %cmp = icmp slt i32 %7, 30 - br i1 %cmp, label %do.body2, label %do.end +; CHECK: %[[#do3_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do3_continue]] %[[#do3_merge]] +; CHECK: %[[#do3_continue]] = OpLabel +; CHECK: OpBranch %[[#do3_header]] +do3_continue: + store i32 0, ptr %var + br i1 true, label %do3_header, label %do3_merge -; CHECK: %[[#do_3_end]] = OpLabel -; CHECK: OpBranch %[[#do_2_latch]] -do.end: - %8 = load i32, ptr %j, align 4 - %inc3 = add nsw i32 %8, 1 - store i32 %inc3, ptr %j, align 4 - br label %do.cond4 +; CHECK: %[[#do3_merge]] = OpLabel +; CHECK: OpBranch %[[#do2_cond:]] +do3_merge: + store i32 0, ptr %var + br label %do2_continue -; CHECK: %[[#do_2_latch]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_2_header]] %[[#do_2_end]] -do.cond4: - %9 = load i32, ptr %j, align 4 - %cmp5 = icmp slt i32 %9, 20 - br i1 %cmp5, label %do.body1, label %do.end6 +; CHECK: %[[#do2_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do2_continue]] %[[#do2_merge]] +; CHECK: %[[#do2_continue]] = OpLabel +; CHECK: OpBranch %[[#do2_header]] +do2_continue: + store i32 0, ptr %var + br i1 true, label %do2_header, label %do2_merge -; CHECK: %[[#do_2_end]] = OpLabel -; CHECK: OpBranch %[[#do_1_latch]] -do.end6: - %10 = load i32, ptr %i, align 4 - %inc7 = add nsw i32 %10, 1 - store i32 %inc7, ptr %i, align 4 - br label %do.cond8 +; CHECK: %[[#do2_merge]] = OpLabel +; CHECK: OpBranch %[[#do1_cond:]] +do2_merge: + store i32 0, ptr %var + br label %do1_continue -; CHECK: %[[#do_1_latch]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_1_header]] %[[#end]] -do.cond8: - %11 = load i32, ptr %i, align 4 - %cmp9 = icmp slt i32 %11, 10 - br i1 %cmp9, label %do.body, label %do.end10 +; CHECK: %[[#do1_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do1_continue]] %[[#do1_merge]] +; CHECK: %[[#do1_continue]] = OpLabel +; CHECK: OpBranch %[[#do1_header]] +do1_continue: + store i32 0, ptr %var + br i1 true, label %do1_header, label %do1_merge -; CHECK: %[[#end]] = OpLabel -; CHECK: OpReturn -do.end10: +; CHECK: %[[#do1_merge]] = OpLabel +; CHECK: OpReturn +do1_merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll b/llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll index 6d4a0e591cf512f36f8b0db9663987f0a07e14bf..9f84fc317021f09df55c645873f22bd96e020453 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/do-plain.ll @@ -15,71 +15,75 @@ entry: define internal spir_func void @main() #2 { ; CHECK: %[[#entry:]] = OpLabel -; CHECK: OpBranch %[[#do_body:]] +; CHECK: OpBranch %[[#do1_header:]] entry: %0 = call token @llvm.experimental.convergence.entry() - %val = alloca i32, align 4 - %i = alloca i32, align 4 - store i32 0, ptr %val, align 4 - store i32 0, ptr %i, align 4 - br label %do.body - -; CHECK: %[[#do_body]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end:]] %[[#do_cond:]] None -; CHECK: OpBranch %[[#do_cond]] -do.body: + %var = alloca i32, align 4 + br label %do1_header + +; CHECK: %[[#do1_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do1_merge:]] %[[#do1_continue:]] None +; CHECK: OpBranch %[[#do1_cond:]] +do1_header: %1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - %2 = load i32, ptr %i, align 4 - store i32 %2, ptr %val, align 4 - br label %do.cond - -; CHECK: %[[#do_cond]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body]] %[[#do_end]] -do.cond: - %3 = load i32, ptr %i, align 4 - %cmp = icmp slt i32 %3, 10 - br i1 %cmp, label %do.body, label %do.end - -; CHECK: %[[#do_end]] = OpLabel -; CHECK: OpBranch %[[#do_body1:]] -do.end: - br label %do.body1 - -; CHECK: %[[#do_body1]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end3:]] %[[#do_cond2:]] None -; CHECK: OpBranch %[[#do_cond2]] -do.body1: + store i32 0, ptr %var + br label %do1_continue + +; CHECK: %[[#do1_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do1_continue]] %[[#do1_merge]] +; CHECK: %[[#do1_continue]] = OpLabel +; CHECK: OpBranch %[[#do1_header]] +do1_continue: + store i32 0, ptr %var + br i1 true, label %do1_header, label %do1_merge + +; CHECK: %[[#do1_merge]] = OpLabel +; CHECK: OpBranch %[[#do2_header:]] +do1_merge: + store i32 0, ptr %var + br label %do2_header + +; CHECK: %[[#do2_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do2_merge:]] %[[#do2_continue:]] None +; CHECK: OpBranch %[[#do2_cond:]] +do2_header: %4 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - store i32 0, ptr %val, align 4 - br label %do.cond2 - -; CHECK: %[[#do_cond2]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body1]] %[[#do_end3]] -do.cond2: - br i1 true, label %do.body1, label %do.end3 - -; CHECK: %[[#do_end3]] = OpLabel -; CHECK: OpBranch %[[#do_body4:]] -do.end3: - br label %do.body4 - -; CHECK: %[[#do_body4]] = OpLabel -; CHECK: OpLoopMerge %[[#do_end7:]] %[[#do_cond5:]] None -; CHECK: OpBranch %[[#do_cond5]] -do.body4: + store i32 0, ptr %var + br label %do2_continue + +; CHECK: %[[#do2_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do2_continue]] %[[#do2_merge]] +; CHECK: %[[#do2_continue]] = OpLabel +; CHECK: OpBranch %[[#do2_header]] +do2_continue: + store i32 0, ptr %var + br i1 true, label %do2_header, label %do2_merge + +; CHECK: %[[#do2_merge]] = OpLabel +; CHECK: OpBranch %[[#do3_header:]] +do2_merge: + store i32 0, ptr %var + br label %do3_header + +; CHECK: %[[#do3_header]] = OpLabel +; CHECK: OpLoopMerge %[[#do3_merge:]] %[[#do3_continue:]] None +; CHECK: OpBranch %[[#do3_cond:]] +do3_header: %5 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] - br label %do.cond5 - -; CHECK: %[[#do_cond5]] = OpLabel -; CHECK: OpBranchConditional %[[#cond:]] %[[#do_body4]] %[[#do_end7]] -do.cond5: - %6 = load i32, ptr %val, align 4 - %cmp6 = icmp slt i32 %6, 20 - br i1 %cmp6, label %do.body4, label %do.end7 - -; CHECK: %[[#do_end7]] = OpLabel -; CHECK: OpReturn -do.end7: + store i32 0, ptr %var + br label %do3_continue + +; CHECK: %[[#do3_cond]] = OpLabel +; CHECK: OpBranchConditional %[[#]] %[[#do3_continue]] %[[#do3_merge]] +; CHECK: %[[#do3_continue]] = OpLabel +; CHECK: OpBranch %[[#do3_header]] +do3_continue: + store i32 0, ptr %var + br i1 true, label %do3_header, label %do3_merge + +; CHECK: %[[#do3_merge]] = OpLabel +; CHECK: OpReturn +do3_merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll b/llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll index 26b12a1e14f0e21da7338f9130beeb2191809650..235f15b0644704a07af2774fdbeb17509cbe0a8a 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/logical-or.ll @@ -1,84 +1,77 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - --asm-verbose=0 | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - --asm-verbose=0 | FileCheck %s --match-full-lines target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" -; CHECK-DAG: OpName %[[#fn:]] "fn" -; CHECK-DAG: OpName %[[#main:]] "main" -; CHECK-DAG: OpName %[[#var_a:]] "a" -; CHECK-DAG: OpName %[[#var_b:]] "b" +define internal spir_func void @main() #3 { +; CHECK-DAG: OpName %[[#switch_0:]] "reg1" +; CHECK-DAG: OpName %[[#switch_1:]] "reg" -; CHECK-DAG: %[[#bool:]] = OpTypeBool -; CHECK-DAG: %[[#true:]] = OpConstantTrue %[[#bool]] +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0 +; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1 -; CHECK: %[[#fn]] = OpFunction %[[#param:]] DontInline %[[#ftype:]] -define spir_func noundef i32 @fn() #0 { -entry: - %0 = call token @llvm.experimental.convergence.entry() - ret i32 1 -} +; CHECK: %[[#entry:]] = OpLabel +; CHECK-DAG: %[[#switch_0]] = OpVariable %[[#]] Function +; CHECK-DAG: %[[#switch_1]] = OpVariable %[[#]] Function +; CHECK: OpSelectionMerge %[[#merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#new_header:]] %[[#unreachable:]] -; CHECK: %[[#main]] = OpFunction %[[#param:]] DontInline %[[#ftype:]] +; CHECK: %[[#new_header]] = OpLabel +; CHECK: OpSelectionMerge %[[#new_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#taint_true_merge:]] %[[#br_false:]] -define internal spir_func void @main() #3 { +; CHECK: %[[#unreachable]] = OpLabel +; CHECK-NEXT: OpUnreachable -; CHECK: %[[#entry:]] = OpLabel -; CHECK-DAG: %[[#var_a]] = OpVariable %[[#type:]] Function -; CHECK-DAG: %[[#var_b]] = OpVariable %[[#type:]] Function -; CHECK: %[[#tmp:]] = OpLoad %[[#type:]] %[[#var_a]] Aligned 4 -; CHECK: %[[#cond:]] = OpINotEqual %[[#bool]] %[[#tmp]] %[[#const:]] -; CHECK: OpSelectionMerge %[[#if_end:]] None -; CHECK: OpBranchConditional %[[#true]] %[[#cond1:]] %[[#dead:]] +; CHECK: %[[#taint_true_merge]] = OpLabel +; CHECK: OpStore %[[#switch_0]] %[[#int_1]] +; CHECK: OpBranch %[[#new_merge]] -; CHECK: %[[#cond1]] = OpLabel -; CHECK: OpSelectionMerge %[[#new_exit:]] None -; CHECK: OpBranchConditional %[[#cond]] %[[#new_exit]] %[[#lor_lhs_false:]] +; CHECK: %[[#br_false]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_1]] %[[#int_0]] +; CHECK: OpSelectionMerge %[[#taint_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#taint_merge]] %[[#taint_false:]] -; CHECK: %[[#dead]] = OpLabel -; CHECK-NEXT: OpUnreachable +; CHECK: %[[#taint_false]] = OpLabel +; CHECK: OpStore %[[#switch_1]] %[[#int_1]] +; CHECK: OpBranch %[[#taint_merge]] -; CHECK: %[[#lor_lhs_false]] = OpLabel -; CHECK: %[[#tmp:]] = OpLoad %[[#type:]] %[[#var_b]] Aligned 4 -; CHECK: %[[#cond:]] = OpINotEqual %[[#bool]] %[[#tmp]] %[[#value:]] -; CHECK: OpBranchConditional %[[#cond]] %[[#new_exit]] %[[#alias_exit:]] +; CHECK: %[[#taint_merge]] = OpLabel +; CHECK: OpStore %[[#switch_0]] %[[#int_0]] +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_1]] +; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]] +; CHECK: OpBranchConditional %[[#cond]] %[[#taint_false_true:]] %[[#new_merge]] -; CHECK: %[[#alias_exit]] = OpLabel -; CHECK: OpBranch %[[#new_exit]] +; CHECK: %[[#taint_false_true]] = OpLabel +; CHECK: OpStore %[[#switch_0]] %[[#int_1]] +; CHECK: OpBranch %[[#new_merge]] -; CHECK: %[[#new_exit]] = OpLabel -; CHECK: %[[#tmp:]] = OpPhi %[[#type:]] %[[#A:]] %[[#cond1]] %[[#A:]] %[[#lor_lhs_false]] %[[#B:]] %[[#alias_exit]] -; CHECK: %[[#cond:]] = OpIEqual %[[#bool]] %[[#A]] %[[#tmp]] -; CHECK: OpBranchConditional %[[#cond]] %[[#if_then:]] %[[#if_end]] +; CHECK: %[[#new_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_0]] +; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]] +; CHECK: OpBranchConditional %[[#cond]] %[[#merge]] %[[#br_true:]] -; CHECK: %[[#if_then]] = OpLabel -; CHECK: OpBranch %[[#if_end]] +; CHECK: %[[#br_true]] = OpLabel +; CHECK: OpBranch %[[#merge]] -; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpReturn +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturn entry: %0 = call token @llvm.experimental.convergence.entry() - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %val = alloca i32, align 4 - store i32 0, ptr %val, align 4 - %1 = load i32, ptr %a, align 4 - %tobool = icmp ne i32 %1, 0 - br i1 %tobool, label %if.then, label %lor.lhs.false - -lor.lhs.false: - %2 = load i32, ptr %b, align 4 - %tobool1 = icmp ne i32 %2, 0 - br i1 %tobool1, label %if.then, label %if.end - -if.then: - %8 = load i32, ptr %val, align 4 - %inc = add nsw i32 %8, 1 - store i32 %inc, ptr %val, align 4 - br label %if.end - -if.end: + %var = alloca i32, align 4 + br i1 true, label %br_true, label %br_false + +br_false: + store i32 0, ptr %var, align 4 + br i1 true, label %br_true, label %merge + +br_true: + store i32 0, ptr %var, align 4 + br label %merge + +merge: ret void } diff --git a/llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll b/llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll new file mode 100644 index 0000000000000000000000000000000000000000..5a5ea002e0942f35bba743dee8ec923f4d7dbb33 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/loop-continue-split.ll @@ -0,0 +1,104 @@ +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s + +; The goal of this test is to voluntarily create 2 overlapping convergence +; structures: the loop, and the inner condition. +; Here, the condition header also branches to 2 internal nodes, which are not +; directly a merge/exits. +; This will require a proper header-split. +; In addition, splitting the header makes the continue the merge of the inner +; condition, so we need to properly split the continue block to create a +; valid inner merge, in the correct order. + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +; CHECK-DAG: OpName %[[#switch_0:]] "reg1" +; CHECK-DAG: OpName %[[#variable:]] "var" + +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#]] 0 +; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#]] 1 +; CHECK-DAG: %[[#int_2:]] = OpConstant %[[#]] 2 +; CHECK-DAG: %[[#int_3:]] = OpConstant %[[#]] 3 +; CHECK-DAG: %[[#int_4:]] = OpConstant %[[#]] 4 + +define internal spir_func void @main() #1 { +; CHECK: %[[#entry:]] = OpLabel +; CHECK: %[[#switch_0]] = OpVariable %[[#]] Function +; CHECK: %[[#variable]] = OpVariable %[[#]] Function +; CHECK: OpBranch %[[#header:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %var = alloca i32, align 4 + br label %header + +; CHECK: %[[#header]] = OpLabel +; CHECK: OpLoopMerge %[[#merge:]] %[[#continue:]] None +; CHECK: OpBranch %[[#split_header:]] + +; CHECK: %[[#split_header]] = OpLabel +; CHECK: OpSelectionMerge %[[#inner_merge:]] None +; CHECK: OpBranchConditional %[[#]] %[[#left:]] %[[#right:]] +header: + %2 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ] + br i1 true, label %left, label %right + +; CHECK: %[[#left]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_0]] +; CHECK-DAG: OpStore %[[#variable]] %[[#int_1]] +; CHECK: OpBranchConditional %[[#]] %[[#inner_merge]] %[[#left_next:]] +left: + store i32 1, ptr %var + br i1 true, label %merge, label %left_next + +; CHECK: %[[#right]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_0]] +; CHECK-DAG: OpStore %[[#variable]] %[[#int_2]] +; CHECK: OpBranchConditional %[[#]] %[[#inner_merge]] %[[#right_next:]] +right: + store i32 2, ptr %var + br i1 true, label %merge, label %right_next + +; CHECK: %[[#left_next]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_1]] +; CHECK-DAG: OpStore %[[#variable]] %[[#int_3]] +; CHECK: OpBranch %[[#inner_merge]] +left_next: + store i32 3, ptr %var + br label %continue + +; CHECK: %[[#right_next]] = OpLabel +; CHECK-DAG: OpStore %[[#switch_0]] %[[#int_1]] +; CHECK-DAG: OpStore %[[#variable]] %[[#int_4]] +; CHECK: OpBranch %[[#inner_merge]] +right_next: + store i32 4, ptr %var + br label %continue + +; CHECK: %[[#inner_merge]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#switch_0]] +; CHECK: %[[#cond:]] = OpIEqual %[[#]] %[[#int_0]] %[[#tmp]] +; CHECK: OpBranchConditional %[[#cond]] %[[#merge]] %[[#continue]] + +; CHECK: %[[#continue]] = OpLabel +; CHECK: OpBranch %[[#header]] +continue: + br label %header + +; CHECK: %[[#merge]] = OpLabel +; CHECK: OpReturn +merge: + ret void +} + + +declare token @llvm.experimental.convergence.entry() #0 +declare token @llvm.experimental.convergence.loop() #0 + +attributes #0 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #1 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} diff --git a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll index a9a0397718e1f5d6d5b520db6a5a9606612227f4..b421ae7990c67a5c33191fee303bac6f82bc7b59 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-break.ll @@ -1,23 +1,23 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan-compute" define internal spir_func void @main() #0 { -; CHECK: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId -; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#int_fpty:]] = OpTypePointer Function %[[#int_ty]] +; CHECK-DAG: OpName %[[#idx:]] "idx" +; CHECK-DAG: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId +; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#int_ipty:]] = OpTypePointer Input %[[#int_ty]] -; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool -; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 -; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10 -; CHECK-DAG: %[[#builtin]] = OpVariable %[[#int_ipty]] Input +; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool +; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 +; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10 +; CHECK-DAG: %[[#builtin]] = OpVariable %[[#int_ipty]] Input ; CHECK: %[[#entry:]] = OpLabel -; CHECK: %[[#idx:]] = OpVariable %[[#int_fpty]] Function -; CHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4 +; CHECK: %[[#idx]] = OpVariable %[[#]] Function +; ACHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4 ; CHECK: OpBranch %[[#while_cond:]] entry: %0 = call token @llvm.experimental.convergence.entry() @@ -37,12 +37,12 @@ while.cond: %cmp = icmp ne i32 %2, 10 br i1 %cmp, label %while.body, label %while.end -; CHECK: %[[#while_body]] = OpLabel -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 -; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4 -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 -; CHECK-NEXT: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] -; CHECK: OpBranchConditional %[[#cmp1]] %[[#new_end]] %[[#if_end]] +; CHECK: %[[#while_body]] = OpLabel +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#builtin]] Aligned 1 +; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 +; CHECK: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] +; CHECK: OpBranchConditional %[[#cmp1]] %[[#new_end]] %[[#if_end]] while.body: %3 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ] store i32 %3, ptr %idx, align 4 @@ -50,14 +50,14 @@ while.body: %cmp1 = icmp eq i32 %4, 0 br i1 %cmp1, label %if.then, label %if.end +; CHECK: %[[#if_end]] = OpLabel +; CHECK: OpBranch %[[#while_cond]] + ; CHECK: %[[#new_end]] = OpLabel ; CHECK: OpBranch %[[#while_end:]] - if.then: br label %while.end -; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpBranch %[[#while_cond]] if.end: br label %while.cond diff --git a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll index 3db7545b81780c5e9d0d9929737707b298d9a8e3..ac330a96444b82ee440c9f8a647a639e1286c25e 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-convergence-in-break.ll @@ -1,21 +1,20 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan-compute" define internal spir_func void @main() #0 { -; CHECK: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId - +; CHECK-DAG: OpName %[[#idx:]] "idx" +; CHECK-DAG: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId ; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#pint_ty:]] = OpTypePointer Function %[[#int_ty]] ; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool ; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 ; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10 ; CHECK: %[[#entry:]] = OpLabel -; CHECK: %[[#idx:]] = OpVariable %[[#pint_ty]] Function +; CHECK: %[[#idx]] = OpVariable %[[#]] Function ; CHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4 ; CHECK: OpBranch %[[#while_cond:]] entry: @@ -48,17 +47,18 @@ while.body: %cmp1 = icmp eq i32 %4, 0 br i1 %cmp1, label %if.then, label %if.end +; CHECK: %[[#if_end]] = OpLabel +; CHECK: OpBranch %[[#while_cond]] + ; CHECK: %[[#if_then]] = OpLabel -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 -; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 +; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4 ; CHECK: OpBranch %[[#new_end]] if.then: %5 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ] store i32 %5, ptr %idx, align 4 br label %while.end -; CHECK: %[[#if_end]] = OpLabel -; CHECK: OpBranch %[[#while_cond]] if.end: br label %while.cond diff --git a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll index d25b30df45ae045d202931876c08b6c30c3e947b..784bd38a6fbaedffd144b1a4b6192d57305a1d24 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/merge-exit-multiple-break.ll @@ -1,14 +1,15 @@ -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} ; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan-compute" define internal spir_func void @main() #0 { -; CHECK: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId +; CHECK-DAG: OpName %[[#idx:]] "idx" +; CHECK-DAG: OpName %[[#reg_0:]] "reg" +; CHECK-DAG: OpDecorate %[[#builtin:]] BuiltIn SubgroupLocalInvocationId ; CHECK-DAG: %[[#int_ty:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#pint_ty:]] = OpTypePointer Function %[[#int_ty]] ; CHECK-DAG: %[[#bool_ty:]] = OpTypeBool ; CHECK-DAG: %[[#int_0:]] = OpConstant %[[#int_ty]] 0 ; CHECK-DAG: %[[#int_1:]] = OpConstant %[[#int_ty]] 1 @@ -16,7 +17,7 @@ define internal spir_func void @main() #0 { ; CHECK-DAG: %[[#int_10:]] = OpConstant %[[#int_ty]] 10 ; CHECK: %[[#entry:]] = OpLabel -; CHECK: %[[#idx:]] = OpVariable %[[#pint_ty]] Function +; CHECK: %[[#idx]] = OpVariable %[[#]] Function ; CHECK: OpStore %[[#idx]] %[[#int_0]] Aligned 4 ; CHECK: OpBranch %[[#while_cond:]] entry: @@ -26,6 +27,7 @@ entry: br label %while.cond ; CHECK: %[[#while_cond]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] Aligned 4 ; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 ; CHECK: %[[#cmp:]] = OpINotEqual %[[#bool_ty]] %[[#tmp]] %[[#int_10]] ; CHECK: OpLoopMerge %[[#new_end:]] %[[#if_end2:]] None @@ -37,10 +39,11 @@ while.cond: br i1 %cmp, label %while.body, label %while.end ; CHECK: %[[#while_body]] = OpLabel -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 -; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4 -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 -; CHECK-NEXT: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] +; CHECK: OpStore %[[#reg_0]] %[[#]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#]] %[[#builtin]] Aligned 1 +; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 +; CHECK: %[[#cmp1:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] ; CHECK: OpBranchConditional %[[#cmp1]] %[[#new_end]] %[[#if_end:]] while.body: %3 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ] @@ -50,10 +53,11 @@ while.body: br i1 %cmp1, label %if.then, label %if.end ; CHECK: %[[#if_end]] = OpLabel -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 -; CHECK-NEXT: OpStore %[[#idx]] %[[#tmp]] Aligned 4 -; CHECK-NEXT: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 -; CHECK-NEXT: %[[#cmp2:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] +; CHECK: OpStore %[[#reg_0]] %[[#]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#builtin]] Aligned 1 +; CHECK: OpStore %[[#idx]] %[[#tmp]] Aligned 4 +; CHECK: %[[#tmp:]] = OpLoad %[[#int_ty]] %[[#idx]] Aligned 4 +; CHECK: %[[#cmp2:]] = OpIEqual %[[#bool_ty]] %[[#tmp]] %[[#int_0]] ; CHECK: OpBranchConditional %[[#cmp2]] %[[#new_end]] %[[#if_end2]] if.end: %5 = call i32 @__hlsl_wave_get_lane_index() [ "convergencectrl"(token %1) ] @@ -62,14 +66,15 @@ if.end: %cmp2 = icmp eq i32 %6, 0 br i1 %cmp2, label %if.then2, label %if.end2 +; CHECK: %[[#if_end2]] = OpLabel +; CHECK: OpBranch %[[#while_cond]] + ; TODO: this OpSwitch is useless. Improve the "remove useless branches" step of the structurizer to ; cleanup those. ; CHECK: %[[#new_end]] = OpLabel -; CHECK: %[[#route:]] = OpPhi %[[#int_ty]] %[[#int_0]] %[[#while_cond]] %[[#int_1]] %[[#while_body]] %[[#int_2]] %[[#if_end]] +; CHECK: %[[#route:]] = OpLoad %[[#]] %[[#reg_0]] Aligned 4 ; CHECK: OpSwitch %[[#route]] %[[#while_end:]] 1 %[[#while_end:]] 2 %[[#while_end:]] -; CHECK: %[[#if_end2]] = OpLabel -; CHECK: OpBranch %[[#while_cond]] if.end2: br label %while.cond diff --git a/llvm/test/CodeGen/SPIRV/structurizer/phi-exit.ll b/llvm/test/CodeGen/SPIRV/structurizer/phi-exit.ll new file mode 100644 index 0000000000000000000000000000000000000000..541b23a6495c9a8e10b57a9e6ae4fa3ba8d399a8 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/structurizer/phi-exit.ll @@ -0,0 +1,45 @@ +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} + +target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" +target triple = "spirv-unknown-vulkan1.3-compute" + +define internal spir_func void @main() #1 { +; CHECK: %[[#entry:]] = OpLabel +; CHECK: OpBranch %[[#do_body:]] +entry: + %0 = call token @llvm.experimental.convergence.entry() + %a = alloca i32, align 4 + br label %loop_body + +loop_body: + br i1 true, label %left, label %right + +left: + br i1 true, label %loop_exit, label %loop_continue + +right: + br i1 true, label %loop_exit, label %loop_continue + +loop_continue: + br label %loop_body + +loop_exit: + %r = phi i32 [ 0, %left ], [ 1, %right ] + store i32 %r, ptr %a, align 4 + ret void + +} + + +declare token @llvm.experimental.convergence.entry() #0 +declare token @llvm.experimental.convergence.loop() #0 + +attributes #0 = { convergent nocallback nofree nosync nounwind willreturn memory(none) } +attributes #1 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 4, !"dx.disable_optimizations", i32 1} + diff --git a/llvm/test/CodeGen/SPIRV/structurizer/return-early.ll b/llvm/test/CodeGen/SPIRV/structurizer/return-early.ll index 6f60538153dfc9e04b14605d97b9d4cc597701ea..e27aca8784286cfe35e8ec5db009a2926fb1e942 100644 --- a/llvm/test/CodeGen/SPIRV/structurizer/return-early.ll +++ b/llvm/test/CodeGen/SPIRV/structurizer/return-early.ll @@ -1,6 +1,9 @@ -; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s --match-full-lines +; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %} +; CHECK-DAG: OpName %[[#reg_0:]] "reg2" +; CHECK-DAG: OpName %[[#reg_1:]] "reg1" + target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1" target triple = "spirv-unknown-vulkan1.3-compute" @@ -37,36 +40,40 @@ while.body: ] ; CHECK: %[[#case_1]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] ; CHECK: OpBranch %[[#switch_end]] sw.bb: store i32 1, ptr %a, align 4 br label %while.end ; CHECK: %[[#case_2]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] ; CHECK: OpBranch %[[#switch_end]] sw.bb1: store i32 3, ptr %a, align 4 br label %while.end ; CHECK: %[[#case_5]] = OpLabel +; CHECK: OpStore %[[#reg_0]] %[[#]] ; CHECK: OpBranch %[[#switch_end]] sw.bb2: store i32 5, ptr %a, align 4 br label %while.end ; CHECK: %[[#switch_end]] = OpLabel -; CHECK: %[[#phi:]] = OpPhi %[[#type:]] %[[#A:]] %[[#while_body]] %[[#B:]] %[[#case_5]] %[[#B:]] %[[#case_2]] %[[#B:]] %[[#case_1]] -; CHECK: %[[#tmp:]] = OpIEqual %[[#type:]] %[[#A]] %[[#phi]] +; CHECK: %[[#val:]] = OpLoad %[[#]] %[[#reg_0]] +; CHECK: %[[#tmp:]] = OpIEqual %[[#type:]] %[[#]] %[[#val]] ; CHECK: OpBranchConditional %[[#tmp]] %[[#sw_default:]] %[[#while_end]] ; CHECK: %[[#sw_default]] = OpLabel -; CHECK: OpStore %[[#A:]] %[[#B:]] Aligned 4 +; CHECK: OpStore %[[#]] %[[#B:]] Aligned 4 ; CHECK: OpBranch %[[#for_cond:]] sw.default: store i32 0, ptr %i, align 4 br label %for.cond ; CHECK: %[[#for_cond]] = OpLabel +; CHECK: OpStore %[[#reg_1]] %[[#]] ; CHECK: OpSelectionMerge %[[#for_merge:]] None ; CHECK-NEXT: OpBranchConditional %[[#cond:]] %[[#for_merge]] %[[#for_end:]] for.cond: @@ -76,13 +83,14 @@ for.cond: br i1 %cmp, label %for.body, label %for.end ; CHECK: %[[#for_end]] = OpLabel +; CHECK: OpStore %[[#reg_1]] %[[#]] ; CHECK: OpBranch %[[#for_merge]] for.end: br label %while.end ; CHECK: %[[#for_merge]] = OpLabel -; CHECK: %[[#phi:]] = OpPhi %[[#type:]] %[[#A:]] %[[#for_cond]] %[[#B:]] %[[#for_end]] -; CHECK: %[[#tmp:]] = OpIEqual %[[#type:]] %[[#A]] %[[#phi]] +; CHECK: %[[#val:]] = OpLoad %[[#]] %[[#reg_1]] +; CHECK: %[[#tmp:]] = OpIEqual %[[#type:]] %[[#]] %[[#val]] ; CHECK: OpBranchConditional %[[#tmp]] %[[#for_body:]] %[[#while_end]] ; CHECK: %[[#for_body]] = OpLabel diff --git a/llvm/test/CodeGen/X86/amx_fp8_intrinsics.ll b/llvm/test/CodeGen/X86/amx_fp8_intrinsics.ll new file mode 100644 index 0000000000000000000000000000000000000000..f5d3f6ec9ec29885e8ce50486d509bbfb006983b --- /dev/null +++ b/llvm/test/CodeGen/X86/amx_fp8_intrinsics.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-fp8 | FileCheck %s + +; CHECK-LABEL: test_amx: +; CHECK: # %bb.0: +; CHECK: tdpbf8ps %tmm3, %tmm2, %tmm1 +; CHECK: tdpbhf8ps %tmm3, %tmm2, %tmm1 +; CHECK: tdphbf8ps %tmm3, %tmm2, %tmm1 +; CHECK: tdphf8ps %tmm3, %tmm2, %tmm1 + +define void @test_amx(){ +call void @llvm.x86.tdpbf8ps(i8 1, i8 2, i8 3) +call void @llvm.x86.tdpbhf8ps(i8 1, i8 2, i8 3) +call void @llvm.x86.tdphbf8ps(i8 1, i8 2, i8 3) +call void @llvm.x86.tdphf8ps(i8 1, i8 2, i8 3) +ret void +} +declare void @llvm.x86.tdpbf8ps(i8 %tile0, i8 %tile1, i8 %tile2) +declare void @llvm.x86.tdpbhf8ps(i8 %tile0, i8 %tile1, i8 %tile2) +declare void @llvm.x86.tdphbf8ps(i8 %tile0, i8 %tile1, i8 %tile2) +declare void @llvm.x86.tdphf8ps(i8 %tile0, i8 %tile1, i8 %tile2) diff --git a/llvm/test/CodeGen/X86/andnot-patterns.ll b/llvm/test/CodeGen/X86/andnot-patterns.ll index 1df29f0b12d1b6101de55ee93ad2b5331af98cd5..fc573fbd4fc99d3d7ed48c342f92fc8c2ade2b80 100644 --- a/llvm/test/CodeGen/X86/andnot-patterns.ll +++ b/llvm/test/CodeGen/X86/andnot-patterns.ll @@ -14,41 +14,73 @@ declare void @use_i32(i32) ; define i64 @andnot_rotl_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { -; X86-LABEL: andnot_rotl_i64: -; X86: # %bb.0: -; X86-NEXT: pushl %esi -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: movl {{[0-9]+}}(%esp), %esi -; X86-NEXT: notl %esi -; X86-NEXT: notl %edx -; X86-NEXT: testb $32, %cl -; X86-NEXT: jne .LBB0_1 -; X86-NEXT: # %bb.2: -; X86-NEXT: movl %edx, %eax -; X86-NEXT: jmp .LBB0_3 -; X86-NEXT: .LBB0_1: -; X86-NEXT: movl %esi, %eax -; X86-NEXT: movl %edx, %esi -; X86-NEXT: .LBB0_3: -; X86-NEXT: movl %esi, %edx -; X86-NEXT: shldl %cl, %eax, %edx -; X86-NEXT: # kill: def $cl killed $cl killed $ecx -; X86-NEXT: shldl %cl, %esi, %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %edx -; X86-NEXT: popl %esi -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotl_i64: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: pushl %esi +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: testb $32, %cl +; X86-NOBMI-NEXT: jne .LBB0_1 +; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: movl %eax, %edx +; X86-NOBMI-NEXT: jmp .LBB0_3 +; X86-NOBMI-NEXT: .LBB0_1: +; X86-NOBMI-NEXT: movl %esi, %edx +; X86-NOBMI-NEXT: movl %eax, %esi +; X86-NOBMI-NEXT: .LBB0_3: +; X86-NOBMI-NEXT: movl %esi, %eax +; X86-NOBMI-NEXT: shldl %cl, %edx, %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X86-NOBMI-NEXT: shldl %cl, %esi, %edx +; X86-NOBMI-NEXT: notl %edx +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %edx +; X86-NOBMI-NEXT: popl %esi +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotl_i64: -; X64: # %bb.0: -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: notq %rax -; X64-NEXT: # kill: def $cl killed $cl killed $rcx -; X64-NEXT: rolq %cl, %rax -; X64-NEXT: andq %rdi, %rax -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotl_i64: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: pushl %esi +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: testb $32, %cl +; X86-BMI-NEXT: jne .LBB0_1 +; X86-BMI-NEXT: # %bb.2: +; X86-BMI-NEXT: movl %eax, %esi +; X86-BMI-NEXT: jmp .LBB0_3 +; X86-BMI-NEXT: .LBB0_1: +; X86-BMI-NEXT: movl %edx, %esi +; X86-BMI-NEXT: movl %eax, %edx +; X86-BMI-NEXT: .LBB0_3: +; X86-BMI-NEXT: movl %edx, %eax +; X86-BMI-NEXT: shldl %cl, %esi, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax +; X86-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X86-BMI-NEXT: shldl %cl, %edx, %esi +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %esi, %edx +; X86-BMI-NEXT: popl %esi +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotl_i64: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rdx, %rcx +; X64-NOBMI-NEXT: movq %rsi, %rax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx +; X64-NOBMI-NEXT: rolq %cl, %rax +; X64-NOBMI-NEXT: notq %rax +; X64-NOBMI-NEXT: andq %rdi, %rax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotl_i64: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movq %rdx, %rcx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $rcx +; X64-BMI-NEXT: rolq %cl, %rsi +; X64-BMI-NEXT: andnq %rdi, %rsi, %rax +; X64-BMI-NEXT: retq %not = xor i64 %a1, -1 %rot = tail call i64 @llvm.fshl.i64(i64 %not, i64 %not, i64 %a2) %and = and i64 %rot, %a0 @@ -56,24 +88,40 @@ define i64 @andnot_rotl_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { } define i32 @andnot_rotl_i32(i32 %a0, i32 %a1, i32 %a2) nounwind { -; X86-LABEL: andnot_rotl_i32: -; X86: # %bb.0: -; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax -; X86-NEXT: roll %cl, %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %eax -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotl_i32: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: roll %cl, %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotl_i32: -; X64: # %bb.0: -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: movl %esi, %eax -; X64-NEXT: notl %eax -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %eax -; X64-NEXT: andl %edi, %eax -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotl_i32: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: roll %cl, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotl_i32: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: roll %cl, %eax +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotl_i32: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: roll %cl, %esi +; X64-BMI-NEXT: andnl %edi, %esi, %eax +; X64-BMI-NEXT: retq %not = xor i32 %a1, -1 %rot = tail call i32 @llvm.fshl.i32(i32 %not, i32 %not, i32 %a2) %and = and i32 %rot, %a0 @@ -84,23 +132,32 @@ define i16 @andnot_rotl_i16(i16 %a0, i16 %a1, i16 %a2) nounwind { ; X86-LABEL: andnot_rotl_i16: ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: rolw %cl, %ax +; X86-NEXT: notl %eax ; X86-NEXT: andw {{[0-9]+}}(%esp), %ax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; -; X64-LABEL: andnot_rotl_i16: -; X64: # %bb.0: -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: movl %esi, %eax -; X64-NEXT: notl %eax -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rolw %cl, %ax -; X64-NEXT: andl %edi, %eax -; X64-NEXT: # kill: def $ax killed $ax killed $eax -; X64-NEXT: retq +; X64-NOBMI-LABEL: andnot_rotl_i16: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: rolw %cl, %ax +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotl_i16: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: rolw %cl, %si +; X64-BMI-NEXT: andnl %edi, %esi, %eax +; X64-BMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-BMI-NEXT: retq %not = xor i16 %a1, -1 %rot = tail call i16 @llvm.fshl.i16(i16 %not, i16 %not, i16 %a2) %and = and i16 %rot, %a0 @@ -112,8 +169,8 @@ define i8 @andnot_rotl_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notb %al ; X86-NEXT: rolb %cl, %al +; X86-NEXT: notb %al ; X86-NEXT: andb {{[0-9]+}}(%esp), %al ; X86-NEXT: retl ; @@ -121,9 +178,9 @@ define i8 @andnot_rotl_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { ; X64: # %bb.0: ; X64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %esi, %eax -; X64-NEXT: notb %al ; X64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: rolb %cl, %al +; X64-NEXT: notb %al ; X64-NEXT: andb %dil, %al ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -198,41 +255,73 @@ define i64 @andnot_rotl_i64_multiuse_rot(i64 %a0, i64 %a1, i64 %a2) nounwind { ; define i64 @andnot_rotr_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { -; X86-LABEL: andnot_rotr_i64: -; X86: # %bb.0: -; X86-NEXT: pushl %esi -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %esi -; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: notl %esi -; X86-NEXT: notl %edx -; X86-NEXT: testb $32, %cl -; X86-NEXT: je .LBB5_1 -; X86-NEXT: # %bb.2: -; X86-NEXT: movl %edx, %eax -; X86-NEXT: jmp .LBB5_3 -; X86-NEXT: .LBB5_1: -; X86-NEXT: movl %esi, %eax -; X86-NEXT: movl %edx, %esi -; X86-NEXT: .LBB5_3: -; X86-NEXT: movl %esi, %edx -; X86-NEXT: shrdl %cl, %eax, %edx -; X86-NEXT: # kill: def $cl killed $cl killed $ecx -; X86-NEXT: shrdl %cl, %esi, %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %edx -; X86-NEXT: popl %esi -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotr_i64: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: pushl %esi +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: testb $32, %cl +; X86-NOBMI-NEXT: je .LBB5_1 +; X86-NOBMI-NEXT: # %bb.2: +; X86-NOBMI-NEXT: movl %eax, %edx +; X86-NOBMI-NEXT: jmp .LBB5_3 +; X86-NOBMI-NEXT: .LBB5_1: +; X86-NOBMI-NEXT: movl %esi, %edx +; X86-NOBMI-NEXT: movl %eax, %esi +; X86-NOBMI-NEXT: .LBB5_3: +; X86-NOBMI-NEXT: movl %esi, %eax +; X86-NOBMI-NEXT: shrdl %cl, %edx, %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X86-NOBMI-NEXT: shrdl %cl, %esi, %edx +; X86-NOBMI-NEXT: notl %edx +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %edx +; X86-NOBMI-NEXT: popl %esi +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotr_i64: -; X64: # %bb.0: -; X64-NEXT: movq %rdx, %rcx -; X64-NEXT: movq %rsi, %rax -; X64-NEXT: notq %rax -; X64-NEXT: # kill: def $cl killed $cl killed $rcx -; X64-NEXT: rorq %cl, %rax -; X64-NEXT: andq %rdi, %rax -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotr_i64: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: pushl %esi +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: testb $32, %cl +; X86-BMI-NEXT: je .LBB5_1 +; X86-BMI-NEXT: # %bb.2: +; X86-BMI-NEXT: movl %eax, %esi +; X86-BMI-NEXT: jmp .LBB5_3 +; X86-BMI-NEXT: .LBB5_1: +; X86-BMI-NEXT: movl %edx, %esi +; X86-BMI-NEXT: movl %eax, %edx +; X86-BMI-NEXT: .LBB5_3: +; X86-BMI-NEXT: movl %edx, %eax +; X86-BMI-NEXT: shrdl %cl, %esi, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax +; X86-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X86-BMI-NEXT: shrdl %cl, %edx, %esi +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %esi, %edx +; X86-BMI-NEXT: popl %esi +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotr_i64: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movq %rdx, %rcx +; X64-NOBMI-NEXT: movq %rsi, %rax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $rcx +; X64-NOBMI-NEXT: rorq %cl, %rax +; X64-NOBMI-NEXT: notq %rax +; X64-NOBMI-NEXT: andq %rdi, %rax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotr_i64: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movq %rdx, %rcx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $rcx +; X64-BMI-NEXT: rorq %cl, %rsi +; X64-BMI-NEXT: andnq %rdi, %rsi, %rax +; X64-BMI-NEXT: retq %not = xor i64 %a1, -1 %rot = tail call i64 @llvm.fshr.i64(i64 %not, i64 %not, i64 %a2) %and = and i64 %rot, %a0 @@ -240,24 +329,40 @@ define i64 @andnot_rotr_i64(i64 %a0, i64 %a1, i64 %a2) nounwind { } define i32 @andnot_rotr_i32(i32 %a0, i32 %a1, i32 %a2) nounwind { -; X86-LABEL: andnot_rotr_i32: -; X86: # %bb.0: -; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax -; X86-NEXT: rorl %cl, %eax -; X86-NEXT: andl {{[0-9]+}}(%esp), %eax -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotr_i32: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: rorl %cl, %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotr_i32: -; X64: # %bb.0: -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: movl %esi, %eax -; X64-NEXT: notl %eax -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %eax -; X64-NEXT: andl %edi, %eax -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotr_i32: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: rorl %cl, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %eax +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotr_i32: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: rorl %cl, %eax +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotr_i32: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: rorl %cl, %esi +; X64-BMI-NEXT: andnl %edi, %esi, %eax +; X64-BMI-NEXT: retq %not = xor i32 %a1, -1 %rot = tail call i32 @llvm.fshr.i32(i32 %not, i32 %not, i32 %a2) %and = and i32 %rot, %a0 @@ -268,23 +373,32 @@ define i16 @andnot_rotr_i16(i16 %a0, i16 %a1, i16 %a2) nounwind { ; X86-LABEL: andnot_rotr_i16: ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax +; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: rorw %cl, %ax +; X86-NEXT: notl %eax ; X86-NEXT: andw {{[0-9]+}}(%esp), %ax ; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; -; X64-LABEL: andnot_rotr_i16: -; X64: # %bb.0: -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: movl %esi, %eax -; X64-NEXT: notl %eax -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorw %cl, %ax -; X64-NEXT: andl %edi, %eax -; X64-NEXT: # kill: def $ax killed $ax killed $eax -; X64-NEXT: retq +; X64-NOBMI-LABEL: andnot_rotr_i16: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: movl %esi, %eax +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: rorw %cl, %ax +; X64-NOBMI-NEXT: notl %eax +; X64-NOBMI-NEXT: andl %edi, %eax +; X64-NOBMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotr_i16: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: rorw %cl, %si +; X64-BMI-NEXT: andnl %edi, %esi, %eax +; X64-BMI-NEXT: # kill: def $ax killed $ax killed $eax +; X64-BMI-NEXT: retq %not = xor i16 %a1, -1 %rot = tail call i16 @llvm.fshr.i16(i16 %not, i16 %not, i16 %a2) %and = and i16 %rot, %a0 @@ -296,8 +410,8 @@ define i8 @andnot_rotr_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { ; X86: # %bb.0: ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notb %al ; X86-NEXT: rorb %cl, %al +; X86-NEXT: notb %al ; X86-NEXT: andb {{[0-9]+}}(%esp), %al ; X86-NEXT: retl ; @@ -305,9 +419,9 @@ define i8 @andnot_rotr_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { ; X64: # %bb.0: ; X64-NEXT: movl %edx, %ecx ; X64-NEXT: movl %esi, %eax -; X64-NEXT: notb %al ; X64-NEXT: # kill: def $cl killed $cl killed $ecx ; X64-NEXT: rorb %cl, %al +; X64-NEXT: notb %al ; X64-NEXT: andb %dil, %al ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -318,36 +432,67 @@ define i8 @andnot_rotr_i8(i8 %a0, i8 %a1, i8 %a2) nounwind { } define i32 @andnot_rotr_i32_multiuse_not(i32 %a0, i32 %a1, i32 %a2) nounwind { -; X86-LABEL: andnot_rotr_i32_multiuse_not: -; X86: # %bb.0: -; X86-NEXT: pushl %esi -; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: notl %eax -; X86-NEXT: movl %eax, %esi -; X86-NEXT: rorl %cl, %esi -; X86-NEXT: andl {{[0-9]+}}(%esp), %esi -; X86-NEXT: pushl %eax -; X86-NEXT: calll use_i32@PLT -; X86-NEXT: addl $4, %esp -; X86-NEXT: movl %esi, %eax -; X86-NEXT: popl %esi -; X86-NEXT: retl +; X86-NOBMI-LABEL: andnot_rotr_i32_multiuse_not: +; X86-NOBMI: # %bb.0: +; X86-NOBMI-NEXT: pushl %esi +; X86-NOBMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NOBMI-NEXT: notl %eax +; X86-NOBMI-NEXT: movl %eax, %esi +; X86-NOBMI-NEXT: rorl %cl, %esi +; X86-NOBMI-NEXT: andl {{[0-9]+}}(%esp), %esi +; X86-NOBMI-NEXT: pushl %eax +; X86-NOBMI-NEXT: calll use_i32@PLT +; X86-NOBMI-NEXT: addl $4, %esp +; X86-NOBMI-NEXT: movl %esi, %eax +; X86-NOBMI-NEXT: popl %esi +; X86-NOBMI-NEXT: retl ; -; X64-LABEL: andnot_rotr_i32_multiuse_not: -; X64: # %bb.0: -; X64-NEXT: pushq %rbx -; X64-NEXT: movl %edx, %ecx -; X64-NEXT: notl %esi -; X64-NEXT: movl %esi, %ebx -; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %ebx -; X64-NEXT: andl %edi, %ebx -; X64-NEXT: movl %esi, %edi -; X64-NEXT: callq use_i32@PLT -; X64-NEXT: movl %ebx, %eax -; X64-NEXT: popq %rbx -; X64-NEXT: retq +; X86-BMI-LABEL: andnot_rotr_i32_multiuse_not: +; X86-BMI: # %bb.0: +; X86-BMI-NEXT: pushl %esi +; X86-BMI-NEXT: movzbl {{[0-9]+}}(%esp), %ecx +; X86-BMI-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-BMI-NEXT: movl %eax, %edx +; X86-BMI-NEXT: notl %edx +; X86-BMI-NEXT: rorl %cl, %eax +; X86-BMI-NEXT: andnl {{[0-9]+}}(%esp), %eax, %esi +; X86-BMI-NEXT: pushl %edx +; X86-BMI-NEXT: calll use_i32@PLT +; X86-BMI-NEXT: addl $4, %esp +; X86-BMI-NEXT: movl %esi, %eax +; X86-BMI-NEXT: popl %esi +; X86-BMI-NEXT: retl +; +; X64-NOBMI-LABEL: andnot_rotr_i32_multiuse_not: +; X64-NOBMI: # %bb.0: +; X64-NOBMI-NEXT: pushq %rbx +; X64-NOBMI-NEXT: movl %edx, %ecx +; X64-NOBMI-NEXT: notl %esi +; X64-NOBMI-NEXT: movl %esi, %ebx +; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-NOBMI-NEXT: rorl %cl, %ebx +; X64-NOBMI-NEXT: andl %edi, %ebx +; X64-NOBMI-NEXT: movl %esi, %edi +; X64-NOBMI-NEXT: callq use_i32@PLT +; X64-NOBMI-NEXT: movl %ebx, %eax +; X64-NOBMI-NEXT: popq %rbx +; X64-NOBMI-NEXT: retq +; +; X64-BMI-LABEL: andnot_rotr_i32_multiuse_not: +; X64-BMI: # %bb.0: +; X64-BMI-NEXT: pushq %rbx +; X64-BMI-NEXT: movl %edx, %ecx +; X64-BMI-NEXT: movl %esi, %eax +; X64-BMI-NEXT: notl %eax +; X64-BMI-NEXT: # kill: def $cl killed $cl killed $ecx +; X64-BMI-NEXT: rorl %cl, %esi +; X64-BMI-NEXT: andnl %edi, %esi, %ebx +; X64-BMI-NEXT: movl %eax, %edi +; X64-BMI-NEXT: callq use_i32@PLT +; X64-BMI-NEXT: movl %ebx, %eax +; X64-BMI-NEXT: popq %rbx +; X64-BMI-NEXT: retq %not = xor i32 %a1, -1 %rot = tail call i32 @llvm.fshr.i32(i32 %not, i32 %not, i32 %a2) %and = and i32 %rot, %a0 diff --git a/llvm/test/CodeGen/X86/avx10_2-cmp.ll b/llvm/test/CodeGen/X86/avx10_2-cmp.ll new file mode 100644 index 0000000000000000000000000000000000000000..de0bec7ea2695a8ebad30995b5c1221122fc9f0c --- /dev/null +++ b/llvm/test/CodeGen/X86/avx10_2-cmp.ll @@ -0,0 +1,237 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefix=X86 + +define i1 @hoeq(half %x, half %y) { +; X64-LABEL: hoeq: +; X64: # %bb.0: +; X64-NEXT: vucomxsh %xmm1, %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: hoeq: +; X86: # %bb.0: +; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X86-NEXT: vucomxsh {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %1 = fcmp oeq half %x, %y + ret i1 %1 +} + +define i1 @hune(half %x, half %y) { +; X64-LABEL: hune: +; X64: # %bb.0: +; X64-NEXT: vucomxsh %xmm1, %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: hune: +; X86: # %bb.0: +; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X86-NEXT: vucomxsh {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %1 = fcmp une half %x, %y + ret i1 %1 +} + +define i1 @hoeq_mem(ptr %xp, ptr %yp) { +; X64-LABEL: hoeq_mem: +; X64: # %bb.0: +; X64-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X64-NEXT: vucomxsh (%rsi), %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: hoeq_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X86-NEXT: vucomxsh (%eax), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %x = load half, ptr %xp + %y = load half, ptr %yp + %1 = fcmp oeq half %x, %y + ret i1 %1 +} + +define i1 @hune_mem(ptr %xp, ptr %yp) { +; X64-LABEL: hune_mem: +; X64: # %bb.0: +; X64-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X64-NEXT: vucomxsh (%rsi), %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: hune_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero +; X86-NEXT: vucomxsh (%eax), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %x = load half, ptr %xp + %y = load half, ptr %yp + %1 = fcmp une half %x, %y + ret i1 %1 +} + +define i1 @foeq(float %x, float %y) { +; X64-LABEL: foeq: +; X64: # %bb.0: +; X64-NEXT: vucomxss %xmm1, %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: foeq: +; X86: # %bb.0: +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vucomxss {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %1 = fcmp oeq float %x, %y + ret i1 %1 +} + +define i1 @fune(float %x, float %y) { +; X64-LABEL: fune: +; X64: # %bb.0: +; X64-NEXT: vucomxss %xmm1, %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: fune: +; X86: # %bb.0: +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vucomxss {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %1 = fcmp une float %x, %y + ret i1 %1 +} + +define i1 @foeq_mem(ptr %xp, ptr %yp) { +; X64-LABEL: foeq_mem: +; X64: # %bb.0: +; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X64-NEXT: vucomxss (%rsi), %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: foeq_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vucomxss (%eax), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %x = load float, ptr %xp + %y = load float, ptr %yp + %1 = fcmp oeq float %x, %y + ret i1 %1 +} + +define i1 @fune_mem(ptr %xp, ptr %yp) { +; X64-LABEL: fune_mem: +; X64: # %bb.0: +; X64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X64-NEXT: vucomxss (%rsi), %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: fune_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; X86-NEXT: vucomxss (%eax), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %x = load float, ptr %xp + %y = load float, ptr %yp + %1 = fcmp une float %x, %y + ret i1 %1 +} + +define i1 @doeq(double %x, double %y) { +; X64-LABEL: doeq: +; X64: # %bb.0: +; X64-NEXT: vucomxsd %xmm1, %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: doeq: +; X86: # %bb.0: +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vucomxsd {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %1 = fcmp oeq double %x, %y + ret i1 %1 +} + +define i1 @dune(double %x, double %y) { +; X64-LABEL: dune: +; X64: # %bb.0: +; X64-NEXT: vucomxsd %xmm1, %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: dune: +; X86: # %bb.0: +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vucomxsd {{[0-9]+}}(%esp), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %1 = fcmp une double %x, %y + ret i1 %1 +} + +define i1 @doeq_mem(ptr %xp, ptr %yp) { +; X64-LABEL: doeq_mem: +; X64: # %bb.0: +; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X64-NEXT: vucomxsd (%rsi), %xmm0 +; X64-NEXT: sete %al +; X64-NEXT: retq +; +; X86-LABEL: doeq_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vucomxsd (%eax), %xmm0 +; X86-NEXT: sete %al +; X86-NEXT: retl + %x = load double, ptr %xp + %y = load double, ptr %yp + %1 = fcmp oeq double %x, %y + ret i1 %1 +} + +define i1 @dune_mem(ptr %xp, ptr %yp) { +; X64-LABEL: dune_mem: +; X64: # %bb.0: +; X64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X64-NEXT: vucomxsd (%rsi), %xmm0 +; X64-NEXT: setne %al +; X64-NEXT: retq +; +; X86-LABEL: dune_mem: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; X86-NEXT: vucomxsd (%eax), %xmm0 +; X86-NEXT: setne %al +; X86-NEXT: retl + %x = load double, ptr %xp + %y = load double, ptr %yp + %1 = fcmp une double %x, %y + ret i1 %1 +} diff --git a/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll index 7b81d547db085c5e7a6ef2f20b8d2676cb08f788..5f2bcf0556b021e26da2db8a3ab29a6d6f00fa9a 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll @@ -76,13 +76,15 @@ declare <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat>, i32) define i32 @test_int_x86_avx512_fpclass_nepbf16_512(<32 x bfloat> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_nepbf16_512: ; CHECK: # %bb.0: -; CHECK-NEXT: vfpclasspbf16 $2, %zmm0, %k1 # encoding: [0x62,0xf3,0x7f,0x48,0x66,0xc8,0x02] -; CHECK-NEXT: vfpclasspbf16 $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7f,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: vfpclasspbf16 $6, %zmm0, %k1 # encoding: [0x62,0xf3,0x7f,0x48,0x66,0xc8,0x06] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) | isNegativeZero(zmm0) +; CHECK-NEXT: vfpclasspbf16 $0, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7f,0x49,0x66,0xc0,0x00] +; CHECK-NEXT: # k0 {%k1} = false ; CHECK-NEXT: kmovd %k0, %eax # encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] - %res = call <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat> %x0, i32 4) - %res1 = call <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat> %x0, i32 2) + %res = call <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat> %x0, i32 0) + %res1 = call <32 x i1> @llvm.x86.avx10.fpclass.nepbf16.512(<32 x bfloat> %x0, i32 6) %1 = and <32 x i1> %res1, %res %2 = bitcast <32 x i1> %1 to i32 ret i32 %2 diff --git a/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll index 559d866b55cc7b637f2bd20d14d27919d5bda0ba..59151d4dd96099e657fec2e564376269dddb6043 100644 --- a/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll @@ -298,6 +298,7 @@ define i8 @test_int_x86_avx512_fpclass_nepbf16_128(<8 x bfloat> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_nepbf16_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspbf16 $2, %xmm0, %k1 # encoding: [0x62,0xf3,0x7f,0x08,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(xmm0) ; CHECK-NEXT: vfpclasspbf16 $4, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7f,0x09,0x66,0xc0,0x04] ; CHECK-NEXT: kmovd %k0, %eax # encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -313,6 +314,7 @@ define i16 @test_int_x86_avx512_fpclass_nepbf16_256(<16 x bfloat> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_nepbf16_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspbf16 $2, %ymm0, %k1 # encoding: [0x62,0xf3,0x7f,0x28,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(ymm0) ; CHECK-NEXT: vfpclasspbf16 $4, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7f,0x29,0x66,0xc0,0x04] ; CHECK-NEXT: kmovd %k0, %eax # encoding: [0xc5,0xfb,0x93,0xc0] ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax diff --git a/llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll index 64063bdf8333eb5cf603cc6a560cb6298b809c7f..53193597d62f08ff07be0ddaa250d2b87f9ded27 100644 --- a/llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512dq-intrinsics-fast-isel.ll @@ -7,7 +7,7 @@ define zeroext i8 @test_mm512_mask_fpclass_pd_mask(i8 zeroext %__U, <8 x double> %__A) { ; X86-LABEL: test_mm512_mask_fpclass_pd_mask: ; X86: # %bb.0: # %entry -; X86-NEXT: vfpclasspd $4, %zmm0, %k0 +; X86-NEXT: vfpclasspd $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: andb {{[0-9]+}}(%esp), %al ; X86-NEXT: # kill: def $al killed $al killed $eax @@ -16,7 +16,7 @@ define zeroext i8 @test_mm512_mask_fpclass_pd_mask(i8 zeroext %__U, <8 x double> ; ; X64-LABEL: test_mm512_mask_fpclass_pd_mask: ; X64: # %bb.0: # %entry -; X64-NEXT: vfpclasspd $4, %zmm0, %k0 +; X64-NEXT: vfpclasspd $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: andb %dil, %al ; X64-NEXT: # kill: def $al killed $al killed $eax @@ -35,7 +35,7 @@ declare <8 x i1> @llvm.x86.avx512.fpclass.pd.512(<8 x double>, i32) define zeroext i8 @test_mm512_fpclass_pd_mask(<8 x double> %__A) { ; CHECK-LABEL: test_mm512_fpclass_pd_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 +; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper @@ -49,7 +49,7 @@ entry: define zeroext i16 @test_mm512_mask_fpclass_ps_mask(i16 zeroext %__U, <16 x float> %__A) { ; X86-LABEL: test_mm512_mask_fpclass_ps_mask: ; X86: # %bb.0: # %entry -; X86-NEXT: vfpclassps $4, %zmm0, %k0 +; X86-NEXT: vfpclassps $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: andw {{[0-9]+}}(%esp), %ax ; X86-NEXT: # kill: def $ax killed $ax killed $eax @@ -58,7 +58,7 @@ define zeroext i16 @test_mm512_mask_fpclass_ps_mask(i16 zeroext %__U, <16 x floa ; ; X64-LABEL: test_mm512_mask_fpclass_ps_mask: ; X64: # %bb.0: # %entry -; X64-NEXT: vfpclassps $4, %zmm0, %k0 +; X64-NEXT: vfpclassps $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: andl %edi, %eax ; X64-NEXT: # kill: def $ax killed $ax killed $eax @@ -77,7 +77,7 @@ declare <16 x i1> @llvm.x86.avx512.fpclass.ps.512(<16 x float>, i32) define zeroext i16 @test_mm512_fpclass_ps_mask(<16 x float> %__A) { ; CHECK-LABEL: test_mm512_fpclass_ps_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 +; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 # k0 = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper @@ -91,7 +91,7 @@ entry: define zeroext i8 @test_mm_fpclass_sd_mask(<4 x float> %__A) { ; CHECK-LABEL: test_mm_fpclass_sd_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 +; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 # k0 = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} @@ -107,7 +107,7 @@ define zeroext i8 @test_mm_mask_fpclass_sd_mask(i8 zeroext %__U, <4 x float> %__ ; X86-LABEL: test_mm_mask_fpclass_sd_mask: ; X86: # %bb.0: # %entry ; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 -; X86-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} +; X86-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} # k0 {%k1} = isPositiveZero(xmm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl @@ -115,7 +115,7 @@ define zeroext i8 @test_mm_mask_fpclass_sd_mask(i8 zeroext %__U, <4 x float> %__ ; X64-LABEL: test_mm_mask_fpclass_sd_mask: ; X64: # %bb.0: # %entry ; X64-NEXT: kmovw %edi, %k1 -; X64-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} +; X64-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} # k0 {%k1} = isPositiveZero(xmm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq @@ -128,7 +128,7 @@ entry: define zeroext i8 @test_mm_fpclass_ss_mask(<4 x float> %__A) { ; CHECK-LABEL: test_mm_fpclass_ss_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclassss $2, %xmm0, %k0 +; CHECK-NEXT: vfpclassss $2, %xmm0, %k0 # k0 = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} @@ -143,7 +143,7 @@ define zeroext i8 @test_mm_mask_fpclass_ss_mask(i8 zeroext %__U, <4 x float> %__ ; X86-LABEL: test_mm_mask_fpclass_ss_mask: ; X86: # %bb.0: # %entry ; X86-NEXT: kmovb {{[0-9]+}}(%esp), %k1 -; X86-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} +; X86-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} # k0 {%k1} = isPositiveZero(xmm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl @@ -151,7 +151,7 @@ define zeroext i8 @test_mm_mask_fpclass_ss_mask(i8 zeroext %__U, <4 x float> %__ ; X64-LABEL: test_mm_mask_fpclass_ss_mask: ; X64: # %bb.0: # %entry ; X64-NEXT: kmovw %edi, %k1 -; X64-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} +; X64-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} # k0 {%k1} = isPositiveZero(xmm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq diff --git a/llvm/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll index 23e929aa9d89b1cb69e1aa860a3684eb49088a1a..8a0428d022b6d7f686178906b53611a388425fc9 100644 --- a/llvm/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll +++ b/llvm/test/CodeGen/X86/avx512dq-intrinsics-upgrade.ll @@ -654,7 +654,9 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_512: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $2, %zmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x48,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) ; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] @@ -669,7 +671,9 @@ define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_512: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $2, %zmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x48,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) ; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] diff --git a/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll b/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll index 027bca9c8badf9cba3c1f1a33f0c49de37172681..70f60c802a2d5216982b19116aa4d8a405bd8e54 100644 --- a/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll @@ -726,7 +726,9 @@ define i8 @test_int_x86_avx512_fpclass_pd_512(<8 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_pd_512: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $2, %zmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x48,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) ; CHECK-NEXT: vfpclasspd $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] @@ -743,7 +745,9 @@ define i16@test_int_x86_avx512_fpclass_ps_512(<16 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_ps_512: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $2, %zmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x48,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(zmm0) ; CHECK-NEXT: vfpclassps $4, %zmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x49,0x66,0xc0,0x04] +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(zmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] @@ -761,7 +765,9 @@ define i8 @test_int_x86_avx512_mask_fpclass_sd(<2 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_sd: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasssd $4, %xmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x08,0x67,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(xmm0) ; CHECK-NEXT: vfpclasssd $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x67,0xc0,0x02] +; CHECK-NEXT: # k0 {%k1} = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] @@ -775,6 +781,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_sd_load(ptr %x0ptr) { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; X86-NEXT: vfpclasssd $4, (%eax), %k0 # encoding: [0x62,0xf3,0xfd,0x08,0x67,0x00,0x04] +; X86-NEXT: # k0 = isNegativeZero(mem) ; X86-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl # encoding: [0xc3] @@ -782,6 +789,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_sd_load(ptr %x0ptr) { ; X64-LABEL: test_int_x86_avx512_mask_fpclass_sd_load: ; X64: # %bb.0: ; X64-NEXT: vfpclasssd $4, (%rdi), %k0 # encoding: [0x62,0xf3,0xfd,0x08,0x67,0x07,0x04] +; X64-NEXT: # k0 = isNegativeZero(mem) ; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq # encoding: [0xc3] @@ -796,7 +804,9 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss(<4 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ss: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassss $4, %xmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x08,0x67,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(xmm0) ; CHECK-NEXT: vfpclassss $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x67,0xc0,0x02] +; CHECK-NEXT: # k0 {%k1} = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] @@ -810,6 +820,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss_load(ptr %x0ptr, i8 %x1) { ; X86: # %bb.0: ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; X86-NEXT: vfpclassss $4, (%eax), %k0 # encoding: [0x62,0xf3,0x7d,0x08,0x67,0x00,0x04] +; X86-NEXT: # k0 = isNegativeZero(mem) ; X86-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl # encoding: [0xc3] @@ -817,6 +828,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ss_load(ptr %x0ptr, i8 %x1) { ; X64-LABEL: test_int_x86_avx512_mask_fpclass_ss_load: ; X64: # %bb.0: ; X64-NEXT: vfpclassss $4, (%rdi), %k0 # encoding: [0x62,0xf3,0x7d,0x08,0x67,0x07,0x04] +; X64-NEXT: # k0 = isNegativeZero(mem) ; X64-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq # encoding: [0xc3] diff --git a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll index 703591acef572072a2fc384557c222f1a04dd17e..a8a38d9c48113315bf3a0465a4e6303b00904f8a 100644 --- a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-fast-isel.ll @@ -235,7 +235,7 @@ declare <2 x i1> @llvm.x86.avx512.fpclass.pd.128(<2 x double>, i32) define zeroext i8 @test_mm_fpclass_pd_mask(<2 x double> %__A) { ; CHECK-LABEL: test_mm_fpclass_pd_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclasspd $2, %xmm0, %k0 +; CHECK-NEXT: vfpclasspd $2, %xmm0, %k0 # k0 = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} @@ -279,7 +279,7 @@ declare <4 x i1> @llvm.x86.avx512.fpclass.pd.256(<4 x double>, i32) define zeroext i8 @test_mm256_fpclass_pd_mask(<4 x double> %__A) { ; CHECK-LABEL: test_mm256_fpclass_pd_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 +; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 # k0 = isPositiveZero(ymm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper @@ -322,7 +322,7 @@ declare <4 x i1> @llvm.x86.avx512.fpclass.ps.128(<4 x float>, i32) define zeroext i8 @test_mm_fpclass_ps_mask(<4 x float> %__A) { ; CHECK-LABEL: test_mm_fpclass_ps_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 +; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 # k0 = isPositiveZero(xmm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} @@ -336,7 +336,7 @@ entry: define zeroext i8 @test_mm256_mask_fpclass_ps_mask(i8 zeroext %__U, <8 x float> %__A) { ; X86-LABEL: test_mm256_mask_fpclass_ps_mask: ; X86: # %bb.0: # %entry -; X86-NEXT: vfpclassps $2, %ymm0, %k0 +; X86-NEXT: vfpclassps $2, %ymm0, %k0 # k0 = isPositiveZero(ymm0) ; X86-NEXT: kmovw %k0, %eax ; X86-NEXT: andb {{[0-9]+}}(%esp), %al ; X86-NEXT: # kill: def $al killed $al killed $eax @@ -345,7 +345,7 @@ define zeroext i8 @test_mm256_mask_fpclass_ps_mask(i8 zeroext %__U, <8 x float> ; ; X64-LABEL: test_mm256_mask_fpclass_ps_mask: ; X64: # %bb.0: # %entry -; X64-NEXT: vfpclassps $2, %ymm0, %k0 +; X64-NEXT: vfpclassps $2, %ymm0, %k0 # k0 = isPositiveZero(ymm0) ; X64-NEXT: kmovw %k0, %eax ; X64-NEXT: andb %dil, %al ; X64-NEXT: # kill: def $al killed $al killed $eax @@ -364,7 +364,7 @@ declare <8 x i1> @llvm.x86.avx512.fpclass.ps.256(<8 x float>, i32) define zeroext i8 @test_mm256_fpclass_ps_mask(<8 x float> %__A) { ; CHECK-LABEL: test_mm256_fpclass_ps_mask: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 +; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 # k0 = isPositiveZero(ymm0) ; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper diff --git a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll index 8d609eb7fdd00928240e4abc9327a961b25fc688..f31dafcd68626952b714a8153bcb5a750594a5e2 100644 --- a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll +++ b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics-upgrade.ll @@ -2921,6 +2921,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ps_128(<4 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $4, %xmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x08,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(xmm0) ; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -2936,6 +2937,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_ps_256(<8 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $4, %ymm0, %k1 # encoding: [0x62,0xf3,0x7d,0x28,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(ymm0) ; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -2952,6 +2954,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_128(<2 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $2, %xmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x08,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(xmm0) ; CHECK-NEXT: vfpclasspd $4, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x66,0xc0,0x04] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -2967,6 +2970,7 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_256(<4 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $4, %ymm0, %k1 # encoding: [0x62,0xf3,0xfd,0x28,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(ymm0) ; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x29,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax diff --git a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll index 3b9f96ef452c3234a0c915a89a3362ab231902c5..ec94b593148dfac630e41efbf659090a9cb69cad 100644 --- a/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll @@ -1500,6 +1500,7 @@ define i8 @test_int_x86_avx512_fpclass_ps_128(<4 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_ps_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $4, %xmm0, %k1 # encoding: [0x62,0xf3,0x7d,0x08,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(xmm0) ; CHECK-NEXT: vfpclassps $2, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -1518,6 +1519,7 @@ define i8 @test_int_x86_avx512_fpclass_ps_256(<8 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_ps_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclassps $4, %ymm0, %k1 # encoding: [0x62,0xf3,0x7d,0x28,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(ymm0) ; CHECK-NEXT: vfpclassps $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -1536,6 +1538,7 @@ define i8 @test_int_x86_avx512_fpclass_pd_128(<2 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_pd_128: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $2, %xmm0, %k1 # encoding: [0x62,0xf3,0xfd,0x08,0x66,0xc8,0x02] +; CHECK-NEXT: # k1 = isPositiveZero(xmm0) ; CHECK-NEXT: vfpclasspd $4, %xmm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x09,0x66,0xc0,0x04] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax @@ -1554,6 +1557,7 @@ define i8 @test_int_x86_avx512_fpclass_pd_256(<4 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_fpclass_pd_256: ; CHECK: # %bb.0: ; CHECK-NEXT: vfpclasspd $4, %ymm0, %k1 # encoding: [0x62,0xf3,0xfd,0x28,0x66,0xc8,0x04] +; CHECK-NEXT: # k1 = isNegativeZero(ymm0) ; CHECK-NEXT: vfpclasspd $2, %ymm0, %k0 {%k1} # encoding: [0x62,0xf3,0xfd,0x29,0x66,0xc0,0x02] ; CHECK-NEXT: kmovw %k0, %eax # encoding: [0xc5,0xf8,0x93,0xc0] ; CHECK-NEXT: # kill: def $al killed $al killed $eax diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll index ed7109c416e7fda1c999c92716acf78c5e963c9f..9382ba31ab649d60463503d397237db3fa100a7e 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll @@ -234,6 +234,7 @@ define i32 @stack_fold_fpclassph(<32 x half> %a0) { ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vfpclassphz $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 64-byte Folded Reload +; CHECK-NEXT: # k0 = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -253,6 +254,7 @@ define i32 @stack_fold_fpclassph_mask(<32 x half> %a0, ptr %p) { ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: kmovd (%rdi), %k1 ; CHECK-NEXT: vfpclassphz $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 {%k1} # 64-byte Folded Reload +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -272,6 +274,7 @@ define i8 @stack_fold_fpclasssh(<8 x half> %a0) { ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vfpclasssh $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 16-byte Folded Reload +; CHECK-NEXT: # k0 = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq @@ -290,6 +293,7 @@ define i8 @stack_fold_fpclasssh_mask(<8 x half> %a0, ptr %p) { ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: kmovb (%rdi), %k1 ; CHECK-NEXT: vfpclasssh $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 {%k1} # 16-byte Folded Reload +; CHECK-NEXT: # k0 {%k1} = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll index e2ed997783f59b8a64467c64bdc9ab48940a12cc..3386f4a9b519813178877d5d429e717cc25158e4 100644 --- a/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll +++ b/llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl.ll @@ -110,6 +110,7 @@ define i8 @stack_fold_fpclassph(<8 x half> %a0) { ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vfpclassphx $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 16-byte Folded Reload +; CHECK-NEXT: # k0 = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq @@ -148,6 +149,7 @@ define i16 @stack_fold_fpclassph_ymm(<16 x half> %a0) { ; CHECK-NEXT: nop ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vfpclassphy $4, {{[-0-9]+}}(%r{{[sb]}}p), %k0 # 32-byte Folded Reload +; CHECK-NEXT: # k0 = isNegativeZero(mem) ; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper diff --git a/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..231d4cd9967a497aabaacf5fe2c3a9c3cb256846 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening-diagnostics.s @@ -0,0 +1,220 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 < %s 2>&1 | FileCheck %s + +// BFMOP4A + +// Single vectors + +bfmop4a za0.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4a za4.h, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z15.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z0.h, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, z12.h, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, z12.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, z12.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Single and multiple vectors + +bfmop4a za0.d, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4a za4.h, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, z0.s, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z1.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z16.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4a za0.h, z0.h, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, z0.h, {z17.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, z0.h, {z12.h-z13.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +bfmop4a za0.d, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4a za4.h, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, {z0.s-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +bfmop4a za0.h, {z1.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z0.h-z1.h}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, {z0.h-z1.h}, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4a za0.h, {z0.h-z1.h}, z12.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Multiple vectors + +bfmop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4a za4.h, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, {z0.s-z1.s}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, {z1.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z18.h-z19.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z0.h-z1.h}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4a za0.h, {z0.h-z1.h}, {z19.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +bfmop4a za0.h, {z0.h-z1.h}, {z10.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + + +// BFMOP4S + +// Single vectors + +bfmop4s za0.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4s za4.h, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, z0.s, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z15.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z0.h, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, z12.h, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, z12.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, z12.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Single and multiple vectors + +bfmop4s za0.d, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4s za4.h, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, z0.s, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z1.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z16.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.h..z14.h + +bfmop4s za0.h, z0.h, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, z0.h, {z17.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, z0.h, {z12.h-z13.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +bfmop4s za0.d, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4s za4.h, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, {z0.s-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +bfmop4s za0.h, {z1.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z0.h-z1.h}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, {z0.h-z1.h}, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +bfmop4s za0.h, {z0.h-z1.h}, z12.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Multiple vectors + +bfmop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s + +bfmop4s za4.h, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, {z0.s-z1.s}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, {z1.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z18.h-z19.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z0.h-z1.h}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +bfmop4s za0.h, {z0.h-z1.h}, {z19.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +bfmop4s za0.h, {z0.h-z1.h}, {z10.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types diff --git a/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening.s b/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening.s new file mode 100644 index 0000000000000000000000000000000000000000..b98bb99def056949b66a56f6daf7577647a8cbbc --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/bfmop4as-non-widening.s @@ -0,0 +1,178 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-b16b16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-b16b16 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-b16b16 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-b16b16 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// BFMOP4A + +// Single vectors + +bfmop4a za0.h, z0.h, z16.h // 10000001-00100000-00000000-00001000 +// CHECK-INST: bfmop4a za0.h, z0.h, z16.h +// CHECK-ENCODING: [0x08,0x00,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81200008 + +bfmop4a za1.h, z12.h, z24.h // 10000001-00101000-00000001-10001001 +// CHECK-INST: bfmop4a za1.h, z12.h, z24.h +// CHECK-ENCODING: [0x89,0x01,0x28,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81280189 + +bfmop4a za1.h, z14.h, z30.h // 10000001-00101110-00000001-11001001 +// CHECK-INST: bfmop4a za1.h, z14.h, z30.h +// CHECK-ENCODING: [0xc9,0x01,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 812e01c9 + +// Single and multiple vectors + +bfmop4a za0.h, z0.h, {z16.h-z17.h} // 10000001-00110000-00000000-00001000 +// CHECK-INST: bfmop4a za0.h, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x00,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81300008 + +bfmop4a za1.h, z12.h, {z24.h-z25.h} // 10000001-00111000-00000001-10001001 +// CHECK-INST: bfmop4a za1.h, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x89,0x01,0x38,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81380189 + +bfmop4a za1.h, z14.h, {z30.h-z31.h} // 10000001-00111110-00000001-11001001 +// CHECK-INST: bfmop4a za1.h, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xc9,0x01,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 813e01c9 + +// Multiple and single vectors + +bfmop4a za0.h, {z0.h-z1.h}, z16.h // 10000001-00100000-00000010-00001000 +// CHECK-INST: bfmop4a za0.h, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x08,0x02,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81200208 + +bfmop4a za1.h, {z12.h-z13.h}, z24.h // 10000001-00101000-00000011-10001001 +// CHECK-INST: bfmop4a za1.h, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x89,0x03,0x28,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81280389 + +bfmop4a za1.h, {z14.h-z15.h}, z30.h // 10000001-00101110-00000011-11001001 +// CHECK-INST: bfmop4a za1.h, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xc9,0x03,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 812e03c9 + +// Multiple vectors + +bfmop4a za0.h, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00110000-00000010-00001000 +// CHECK-INST: bfmop4a za0.h, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x08,0x02,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81300208 + +bfmop4a za1.h, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00111000-00000011-10001001 +// CHECK-INST: bfmop4a za1.h, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x89,0x03,0x38,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81380389 + +bfmop4a za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11001001 +// CHECK-INST: bfmop4a za1.h, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xc9,0x03,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 813e03c9 + + +// BFMOP4S + +// Single vectors + +bfmop4s za0.h, z0.h, z16.h // 10000001-00100000-00000000-00011000 +// CHECK-INST: bfmop4s za0.h, z0.h, z16.h +// CHECK-ENCODING: [0x18,0x00,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81200018 + +bfmop4s za1.h, z12.h, z24.h // 10000001-00101000-00000001-10011001 +// CHECK-INST: bfmop4s za1.h, z12.h, z24.h +// CHECK-ENCODING: [0x99,0x01,0x28,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81280199 + +bfmop4s za1.h, z14.h, z30.h // 10000001-00101110-00000001-11011001 +// CHECK-INST: bfmop4s za1.h, z14.h, z30.h +// CHECK-ENCODING: [0xd9,0x01,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 812e01d9 + +// Single and multiple vectors + +bfmop4s za0.h, z0.h, {z16.h-z17.h} // 10000001-00110000-00000000-00011000 +// CHECK-INST: bfmop4s za0.h, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x00,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81300018 + +bfmop4s za1.h, z12.h, {z24.h-z25.h} // 10000001-00111000-00000001-10011001 +// CHECK-INST: bfmop4s za1.h, z12.h, { z24.h, z25.h } +// CHECK-ENCODING: [0x99,0x01,0x38,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81380199 + +bfmop4s za1.h, z14.h, {z30.h-z31.h} // 10000001-00111110-00000001-11011001 +// CHECK-INST: bfmop4s za1.h, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xd9,0x01,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 813e01d9 + +// Multiple and single vectors + +bfmop4s za0.h, {z0.h-z1.h}, z16.h // 10000001-00100000-00000010-00011000 +// CHECK-INST: bfmop4s za0.h, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x18,0x02,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81200218 + +bfmop4s za1.h, {z12.h-z13.h}, z24.h // 10000001-00101000-00000011-10011001 +// CHECK-INST: bfmop4s za1.h, { z12.h, z13.h }, z24.h +// CHECK-ENCODING: [0x99,0x03,0x28,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81280399 + +bfmop4s za1.h, {z14.h-z15.h}, z30.h // 10000001-00101110-00000011-11011001 +// CHECK-INST: bfmop4s za1.h, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xd9,0x03,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 812e03d9 + +// Multiple vectors + +bfmop4s za0.h, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00110000-00000010-00011000 +// CHECK-INST: bfmop4s za0.h, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x18,0x02,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81300218 + +bfmop4s za1.h, {z12.h-z13.h}, {z24.h-z25.h} // 10000001-00111000-00000011-10011001 +// CHECK-INST: bfmop4s za1.h, { z12.h, z13.h }, { z24.h, z25.h } +// CHECK-ENCODING: [0x99,0x03,0x38,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 81380399 + +bfmop4s za1.h, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11011001 +// CHECK-INST: bfmop4s za1.h, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xd9,0x03,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 sme-b16b16 +// CHECK-UNKNOWN: 813e03d9 diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..9a06192c0b30af43e8bc3372059549932b75c5b4 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening-diagnostics.s @@ -0,0 +1,120 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f8f32 < %s 2>&1 | FileCheck %s + +// Single vectors + +fmop4a za0.d, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, z0.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.d, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z15.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z16.b, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z0.b, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, z12.b, z17.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, z12.b, z14.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, z12.b, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +// Single and multiple vectors + +fmop4a za0.d, z0.b, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, z0.b, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.d, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z1.b, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z16.b, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.b..z14.b + +fmop4a za0.s, z0.b, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.b, {z17.b-z18.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, z0.b, {z16.b-z18.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.b, {z12.b-z13.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4a za0.d, {z0.b-z1.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, {z0.b-z1.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.s-z1.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +fmop4a za0.s, {z1.b-z2.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z2.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z16.b-z17.b}, z16.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z1.b}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, {z0.b-z1.b}, z17.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +fmop4a za0.s, {z0.b-z1.b}, z12.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.b..z30.b + +// Multiple vectors + +fmop4a za0.d, {z0.b-z1.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, {z0.b-z1.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.s-z1.s}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z1.b-z2.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z2.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z18.b-z19.b}, {z16.b-z17.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z1.b}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.b-z1.b}, {z19.b-z20.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.b-z1.b}, {z18.b-z20.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.b-z1.b}, {z10.b-z11.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening.s b/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening.s new file mode 100644 index 0000000000000000000000000000000000000000..9e378bcf3d7533584dde8100476ae3f1e8c32ee3 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4a-fp8-fp32-widening.s @@ -0,0 +1,93 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f8f32 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f8f32 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-f8f32 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f8f32 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f8f32 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f8f32 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// Single vectors + +fmop4a za0.s, z0.b, z16.b // 10000000-00100000-00000000-00000000 +// CHECK-INST: fmop4a za0.s, z0.b, z16.b +// CHECK-ENCODING: [0x00,0x00,0x20,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80200000 + +fmop4a za1.s, z10.b, z20.b // 10000000-00100100-00000001-01000001 +// CHECK-INST: fmop4a za1.s, z10.b, z20.b +// CHECK-ENCODING: [0x41,0x01,0x24,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80240141 + +fmop4a za3.s, z14.b, z30.b // 10000000-00101110-00000001-11000011 +// CHECK-INST: fmop4a za3.s, z14.b, z30.b +// CHECK-ENCODING: [0xc3,0x01,0x2e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 802e01c3 + +// Single and multiple vectors + +fmop4a za0.s, z0.b, {z16.b-z17.b} // 10000000-00110000-00000000-00000000 +// CHECK-INST: fmop4a za0.s, z0.b, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x00,0x30,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80300000 + +fmop4a za1.s, z10.b, {z20.b-z21.b} // 10000000-00110100-00000001-01000001 +// CHECK-INST: fmop4a za1.s, z10.b, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x01,0x34,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80340141 + +fmop4a za3.s, z14.b, {z30.b-z31.b} // 10000000-00111110-00000001-11000011 +// CHECK-INST: fmop4a za3.s, z14.b, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x01,0x3e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 803e01c3 + +// Multiple and single vectors + +fmop4a za0.s, {z0.b-z1.b}, z16.b // 10000000-00100000-00000010-00000000 +// CHECK-INST: fmop4a za0.s, { z0.b, z1.b }, z16.b +// CHECK-ENCODING: [0x00,0x02,0x20,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80200200 + +fmop4a za1.s, {z10.b-z11.b}, z20.b // 10000000-00100100-00000011-01000001 +// CHECK-INST: fmop4a za1.s, { z10.b, z11.b }, z20.b +// CHECK-ENCODING: [0x41,0x03,0x24,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80240341 + +fmop4a za3.s, {z14.b-z15.b}, z30.b // 10000000-00101110-00000011-11000011 +// CHECK-INST: fmop4a za3.s, { z14.b, z15.b }, z30.b +// CHECK-ENCODING: [0xc3,0x03,0x2e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 802e03c3 + +// Multiple vectors + +fmop4a za0.s, {z0.b-z1.b}, {z16.b-z17.b} // 10000000-00110000-00000010-00000000 +// CHECK-INST: fmop4a za0.s, { z0.b, z1.b }, { z16.b, z17.b } +// CHECK-ENCODING: [0x00,0x02,0x30,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80300200 + +fmop4a za1.s, {z10.b-z11.b}, {z20.b-z21.b} // 10000000-00110100-00000011-01000001 +// CHECK-INST: fmop4a za1.s, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x41,0x03,0x34,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 80340341 + +fmop4a za3.s, {z14.b-z15.b}, {z30.b-z31.b} // 10000000-00111110-00000011-11000011 +// CHECK-INST: fmop4a za3.s, { z14.b, z15.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xc3,0x03,0x3e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f8f32 +// CHECK-UNKNOWN: 803e03c3 diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..457add20355e894411dbe3abea8f66c55f7186fc --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening-diagnostics.s @@ -0,0 +1,243 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2 < %s 2>&1 | FileCheck %s + +// FMOP4A + +// Single vectors + +fmop4a za0.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.d, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4a za0.s, z15.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4a za0.s, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4a za0.s, z0.h, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.s, z12.h, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.s, z12.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.s, z12.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Single and multiple vectors + +fmop4a za0.d, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.d, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4a za0.s, z1.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4a za0.s, z16.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4a za0.s, z0.h, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.h, {z17.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, z0.h, {z16.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.h, {z12.h-z13.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4a za0.d, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.d-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +fmop4a za0.s, {z1.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za4.s, {z0.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.h-z1.h}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.s, {z0.h-z1.h}, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4a za0.s, {z0.h-z1.h}, z12.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Multiple vectors + +fmop4a za0.d, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.d-z1.d}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z1.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z18.h-z19.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.h-z1.h}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.h-z1.h}, {z19.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.h-z1.h}, {z18.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.h-z1.h}, {z10.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// FMOP4S + +// Single vectors + +fmop4a za0.d, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za4.s, z0.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, z0.d, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4s za0.s, z15.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4s za0.s, z16.h, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4s za0.s, z0.h, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.s, z12.h, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.s, z12.h, z14.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.s, z12.h, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Single and multiple vectors + +fmop4s za0.d, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za4.s, z0.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, z0.d, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4s za0.s, z1.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4s za0.s, z16.h, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register + +fmop4s za0.s, z0.h, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, z0.h, {z17.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, z0.h, {z16.h-z18.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, z0.h, {z12.h-z13.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4s za0.d, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za4.s, {z0.h-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z0.d-z1.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +fmop4s za0.s, {z1.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z0.h-z2.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z16.h-z17.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z0.h-z1.h}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.s, {z0.h-z1.h}, z17.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +fmop4s za0.s, {z0.h-z1.h}, z12.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.h..z30.h + +// Multiple vectors + +fmop4s za0.d, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za4.s, {z0.h-z1.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z0.d-z1.d}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z1.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z0.h-z2.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z18.h-z19.h}, {z16.h-z17.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z0.h-z1.h}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z0.h-z1.h}, {z19.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z0.h-z1.h}, {z18.h-z20.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z0.h-z1.h}, {z10.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening.s b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening.s new file mode 100644 index 0000000000000000000000000000000000000000..d615fb85b4fd7e5c001982b38bd54dfa2f99515b --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp16-fp32-widening.s @@ -0,0 +1,177 @@ + +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +// FMOP4A + +// Single vectors +fmop4a za0.s, z0.h, z16.h // 10000001-00100000-00000000-00000000 +// CHECK-INST: fmop4a za0.s, z0.h, z16.h +// CHECK-ENCODING: [0x00,0x00,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81200000 + +fmop4a za1.s, z10.h, z20.h // 10000001-00100100-00000001-01000001 +// CHECK-INST: fmop4a za1.s, z10.h, z20.h +// CHECK-ENCODING: [0x41,0x01,0x24,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81240141 + +fmop4a za3.s, z14.h, z30.h // 10000001-00101110-00000001-11000011 +// CHECK-INST: fmop4a za3.s, z14.h, z30.h +// CHECK-ENCODING: [0xc3,0x01,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 812e01c3 + +// Single and multiple vectors + +fmop4a za0.s, z0.h, {z16.h-z17.h} // 10000001-00110000-00000000-00000000 +// CHECK-INST: fmop4a za0.s, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x00,0x00,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81300000 + +fmop4a za1.s, z10.h, {z20.h-z21.h} // 10000001-00110100-00000001-01000001 +// CHECK-INST: fmop4a za1.s, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x41,0x01,0x34,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81340141 + +fmop4a za3.s, z14.h, {z30.h-z31.h} // 10000001-00111110-00000001-11000011 +// CHECK-INST: fmop4a za3.s, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xc3,0x01,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 813e01c3 + +// Multiple and single vectors + +fmop4a za0.s, {z0.h-z1.h}, z16.h // 10000001-00100000-00000010-00000000 +// CHECK-INST: fmop4a za0.s, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x00,0x02,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81200200 + +fmop4a za1.s, {z10.h-z11.h}, z20.h // 10000001-00100100-00000011-01000001 +// CHECK-INST: fmop4a za1.s, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x41,0x03,0x24,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81240341 + +fmop4a za3.s, {z14.h-z15.h}, z30.h // 10000001-00101110-00000011-11000011 +// CHECK-INST: fmop4a za3.s, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xc3,0x03,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 812e03c3 + +// Multiple vectors + +fmop4a za0.s, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00110000-00000010-00000000 +// CHECK-INST: fmop4a za0.s, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x00,0x02,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81300200 + +fmop4a za1.s, {z10.h-z11.h}, {z20.h-z21.h} // 10000001-00110100-00000011-01000001 +// CHECK-INST: fmop4a za1.s, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x41,0x03,0x34,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81340341 + +fmop4a za3.s, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11000011 +// CHECK-INST: fmop4a za3.s, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xc3,0x03,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 813e03c3 + +// FMOP4S + +// Single vectors +fmop4s za0.s, z0.h, z16.h // 10000001-00100000-00000000-00010000 +// CHECK-INST: fmop4s za0.s, z0.h, z16.h +// CHECK-ENCODING: [0x10,0x00,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81200010 + +fmop4s za1.s, z10.h, z20.h // 10000001-00100100-00000001-01010001 +// CHECK-INST: fmop4s za1.s, z10.h, z20.h +// CHECK-ENCODING: [0x51,0x01,0x24,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81240151 + +fmop4s za3.s, z14.h, z30.h // 10000001-00101110-00000001-11010011 +// CHECK-INST: fmop4s za3.s, z14.h, z30.h +// CHECK-ENCODING: [0xd3,0x01,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 812e01d3 + +// Single and multiple vectors + +fmop4s za0.s, z0.h, {z16.h-z17.h} // 10000001-00110000-00000000-00010000 +// CHECK-INST: fmop4s za0.s, z0.h, { z16.h, z17.h } +// CHECK-ENCODING: [0x10,0x00,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81300010 + +fmop4s za1.s, z10.h, {z20.h-z21.h} // 10000001-00110100-00000001-01010001 +// CHECK-INST: fmop4s za1.s, z10.h, { z20.h, z21.h } +// CHECK-ENCODING: [0x51,0x01,0x34,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81340151 + +fmop4s za3.s, z14.h, {z30.h-z31.h} // 10000001-00111110-00000001-11010011 +// CHECK-INST: fmop4s za3.s, z14.h, { z30.h, z31.h } +// CHECK-ENCODING: [0xd3,0x01,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 813e01d3 + +// Multiple and single vectors + +fmop4s za0.s, {z0.h-z1.h}, z16.h // 10000001-00100000-00000010-00010000 +// CHECK-INST: fmop4s za0.s, { z0.h, z1.h }, z16.h +// CHECK-ENCODING: [0x10,0x02,0x20,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81200210 + +fmop4s za1.s, {z10.h-z11.h}, z20.h // 10000001-00100100-00000011-01010001 +// CHECK-INST: fmop4s za1.s, { z10.h, z11.h }, z20.h +// CHECK-ENCODING: [0x51,0x03,0x24,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81240351 + +fmop4s za3.s, {z14.h-z15.h}, z30.h // 10000001-00101110-00000011-11010011 +// CHECK-INST: fmop4s za3.s, { z14.h, z15.h }, z30.h +// CHECK-ENCODING: [0xd3,0x03,0x2e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 812e03d3 + +// Multiple vectors + +fmop4s za0.s, {z0.h-z1.h}, {z16.h-z17.h} // 10000001-00110000-00000010-00010000 +// CHECK-INST: fmop4s za0.s, { z0.h, z1.h }, { z16.h, z17.h } +// CHECK-ENCODING: [0x10,0x02,0x30,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81300210 + +fmop4s za1.s, {z10.h-z11.h}, {z20.h-z21.h} // 10000001-00110100-00000011-01010001 +// CHECK-INST: fmop4s za1.s, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x51,0x03,0x34,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 81340351 + +fmop4s za3.s, {z14.h-z15.h}, {z30.h-z31.h} // 10000001-00111110-00000011-11010011 +// CHECK-INST: fmop4s za3.s, { z14.h, z15.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xd3,0x03,0x3e,0x81] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 813e03d3 diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..c9c59128f42060fedf95270ef4cdb40ce6d40996 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening-diagnostics.s @@ -0,0 +1,245 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2 < %s 2>&1 | FileCheck %s + +// FMOP4A + +// Single vectors + +fmop4a za0.d, z0.s, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, z0.s, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.d, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4a za0.s, z15.s, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4a za0.s, z16.s, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4a za0.s, z0.s, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4a za0.s, z12.s, z17.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4a za0.s, z12.s, z14.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4a za0.s, z12.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +// Single and multiple vectors + +fmop4a za0.d, z0.s, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, z0.s, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.d, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4a za0.s, z1.s, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4a za0.s, z16.s, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4a za0.s, z0.s, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.s, {z17.s-z18.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, z0.s, {z16.s-z18.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, z0.s, {z12.s-z13.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4a za0.d, {z0.s-z1.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, {z0.s-z1.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.d-z1.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +fmop4a za0.s, {z1.s-z2.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z2.s-z4.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z16.s-z17.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.s-z1.s}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4a za0.s, {z0.s-z1.s}, z17.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4a za0.s, {z0.s-z1.s}, z12.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +// Multiple vectors + +fmop4a za0.d, {z0.s-z1.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4a za4.s, {z0.s-z1.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.d-z1.d}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z1.s-z2.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z2.s-z4.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z18.s-z19.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.s-z1.s}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.s-z1.s}, {z19.s-z20.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.s, {z0.s-z1.s}, {z16.s-z18.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.s, {z0.s-z1.s}, {z10.s-z11.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + + +// FMOP4S + +// Single vectors + +fmop4s za0.d, z0.s, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za4.s, z0.s, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, z0.d, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4s za0.s, z15.s, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4s za0.s, z16.s, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4s za0.s, z0.s, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4s za0.s, z12.s, z17.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4s za0.s, z12.s, z14.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4s za0.s, z12.s, z31.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +// Single and multiple vectors + +fmop4s za0.d, z0.s, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za4.s, z0.s, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, z0.d, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4s za0.s, z1.s, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4s za0.s, z16.s, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4s za0.s, z0.s, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, z0.s, {z17.s-z18.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, z0.s, {z16.s-z18.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, z0.s, {z12.s-z13.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4s za0.d, {z0.s-z1.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za4.s, {z0.s-z1.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z0.d-z1.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix + +fmop4s za0.s, {z1.s-z2.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z2.s-z4.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z16.s-z17.s}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z0.s-z1.s}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4s za0.s, {z0.s-z1.s}, z17.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +fmop4s za0.s, {z0.s-z1.s}, z12.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.s..z30.s + +// Multiple vectors + +fmop4s za0.d, {z0.s-z1.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand + +fmop4s za4.s, {z0.s-z1.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z0.d-z1.d}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z1.s-z2.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z2.s-z4.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z18.s-z19.s}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z0.s-z1.s}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z0.s-z1.s}, {z19.s-z20.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.s, {z0.s-z1.s}, {z16.s-z18.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.s, {z0.s-z1.s}, {z10.s-z11.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening.s b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening.s new file mode 100644 index 0000000000000000000000000000000000000000..e65def17cd1b3d524f52ce3ae3a9aa7f38ad5bc2 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp32-non-widening.s @@ -0,0 +1,179 @@ + +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +// FMOP4A + +// Single vectors + +fmop4a za0.s, z0.s, z16.s // 10000000-00000000-00000000-00000000 +// CHECK-INST: fmop4a za0.s, z0.s, z16.s +// CHECK-ENCODING: [0x00,0x00,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80000000 + +fmop4a za3.s, z12.s, z24.s // 10000000-00001000-00000001-10000011 +// CHECK-INST: fmop4a za3.s, z12.s, z24.s +// CHECK-ENCODING: [0x83,0x01,0x08,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80080183 + +fmop4a za3.s, z14.s, z30.s // 10000000-00001110-00000001-11000011 +// CHECK-INST: fmop4a za3.s, z14.s, z30.s +// CHECK-ENCODING: [0xc3,0x01,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e01c3 + +// Single and multiple vectors + +fmop4a za0.s, z0.s, {z16.s-z17.s} // 10000000-00010000-00000000-00000000 +// CHECK-INST: fmop4a za0.s, z0.s, { z16.s, z17.s } +// CHECK-ENCODING: [0x00,0x00,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80100000 + +fmop4a za1.s, z10.s, {z20.s-z21.s} // 10000000-00010100-00000001-01000001 +// CHECK-INST: fmop4a za1.s, z10.s, { z20.s, z21.s } +// CHECK-ENCODING: [0x41,0x01,0x14,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80140141 + +fmop4a za3.s, z14.s, {z30.s-z31.s} // 10000000-00011110-00000001-11000011 +// CHECK-INST: fmop4a za3.s, z14.s, { z30.s, z31.s } +// CHECK-ENCODING: [0xc3,0x01,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e01c3 + +// Multiple and single vectors + +fmop4a za0.s, {z0.s-z1.s}, z16.s // 10000000-00000000-00000010-00000000 +// CHECK-INST: fmop4a za0.s, { z0.s, z1.s }, z16.s +// CHECK-ENCODING: [0x00,0x02,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80000200 + +fmop4a za1.s, {z10.s-z11.s}, z20.s // 10000000-00000100-00000011-01000001 +// CHECK-INST: fmop4a za1.s, { z10.s, z11.s }, z20.s +// CHECK-ENCODING: [0x41,0x03,0x04,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80040341 + +fmop4a za3.s, {z14.s-z15.s}, z30.s // 10000000-00001110-00000011-11000011 +// CHECK-INST: fmop4a za3.s, { z14.s, z15.s }, z30.s +// CHECK-ENCODING: [0xc3,0x03,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e03c3 + +// Multiple vectors + +fmop4a za0.s, {z0.s-z1.s}, {z16.s-z17.s} // 10000000-00010000-00000010-00000000 +// CHECK-INST: fmop4a za0.s, { z0.s, z1.s }, { z16.s, z17.s } +// CHECK-ENCODING: [0x00,0x02,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80100200 + +fmop4a za1.s, {z10.s-z11.s}, {z20.s-z21.s} // 10000000-00010100-00000011-01000001 +// CHECK-INST: fmop4a za1.s, { z10.s, z11.s }, { z20.s, z21.s } +// CHECK-ENCODING: [0x41,0x03,0x14,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80140341 + +fmop4a za3.s, {z14.s-z15.s}, {z30.s-z31.s} // 10000000-00011110-00000011-11000011 +// CHECK-INST: fmop4a za3.s, { z14.s, z15.s }, { z30.s, z31.s } +// CHECK-ENCODING: [0xc3,0x03,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e03c3 + +// FMOP4S + +// Single vectors + +fmop4s za0.s, z0.s, z16.s // 10000000-00000000-00000000-00010000 +// CHECK-INST: fmop4s za0.s, z0.s, z16.s +// CHECK-ENCODING: [0x10,0x00,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80000010 + +fmop4s za3.s, z12.s, z24.s // 10000000-00001000-00000001-10010011 +// CHECK-INST: fmop4s za3.s, z12.s, z24.s +// CHECK-ENCODING: [0x93,0x01,0x08,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80080193 + +fmop4s za3.s, z14.s, z30.s // 10000000-00001110-00000001-11010011 +// CHECK-INST: fmop4s za3.s, z14.s, z30.s +// CHECK-ENCODING: [0xd3,0x01,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e01d3 + +// Single and multiple vectors + +fmop4s za0.s, z0.s, {z16.s-z17.s} // 10000000-00010000-00000000-00010000 +// CHECK-INST: fmop4s za0.s, z0.s, { z16.s, z17.s } +// CHECK-ENCODING: [0x10,0x00,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80100010 + +fmop4s za1.s, z10.s, {z20.s-z21.s} // 10000000-00010100-00000001-01010001 +// CHECK-INST: fmop4s za1.s, z10.s, { z20.s, z21.s } +// CHECK-ENCODING: [0x51,0x01,0x14,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80140151 + +fmop4s za3.s, z14.s, {z30.s-z31.s} // 10000000-00011110-00000001-11010011 +// CHECK-INST: fmop4s za3.s, z14.s, { z30.s, z31.s } +// CHECK-ENCODING: [0xd3,0x01,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e01d3 + +// Multiple and single vectors + +fmop4s za0.s, {z0.s-z1.s}, z16.s // 10000000-00000000-00000010-00010000 +// CHECK-INST: fmop4s za0.s, { z0.s, z1.s }, z16.s +// CHECK-ENCODING: [0x10,0x02,0x00,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80000210 + +fmop4s za1.s, {z10.s-z11.s}, z20.s // 10000000-00000100-00000011-01010001 +// CHECK-INST: fmop4s za1.s, { z10.s, z11.s }, z20.s +// CHECK-ENCODING: [0x51,0x03,0x04,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80040351 + +fmop4s za3.s, {z14.s-z15.s}, z30.s // 10000000-00001110-00000011-11010011 +// CHECK-INST: fmop4s za3.s, { z14.s, z15.s }, z30.s +// CHECK-ENCODING: [0xd3,0x03,0x0e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 800e03d3 + +// Multiple vectors + +fmop4s za0.s, {z0.s-z1.s}, {z16.s-z17.s} // 10000000-00010000-00000010-00010000 +// CHECK-INST: fmop4s za0.s, { z0.s, z1.s }, { z16.s, z17.s } +// CHECK-ENCODING: [0x10,0x02,0x10,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80100210 + +fmop4s za1.s, {z10.s-z11.s}, {z20.s-z21.s} // 10000000-00010100-00000011-01010001 +// CHECK-INST: fmop4s za1.s, { z10.s, z11.s }, { z20.s, z21.s } +// CHECK-ENCODING: [0x51,0x03,0x14,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 80140351 + +fmop4s za3.s, {z14.s-z15.s}, {z30.s-z31.s} // 10000000-00011110-00000011-11010011 +// CHECK-INST: fmop4s za3.s, { z14.s, z15.s }, { z30.s, z31.s } +// CHECK-ENCODING: [0xd3,0x03,0x1e,0x80] +// CHECK-ERROR: instruction requires: sme2p2 +// CHECK-UNKNOWN: 801e03d3 diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening-diagnostics.s b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..ff9602bc12afc2d368586ef61f6c5f6ee048ace6 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening-diagnostics.s @@ -0,0 +1,243 @@ +// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f64f64 < %s 2>&1 | FileCheck %s + +// FMOP4A + +// Single vectors + +fmop4a za0.s, z0.d, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4a za8.d, z0.d, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, z0.s, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4a za0.d, z15.d, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4a za0.d, z16.d, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4a za0.d, z0.d, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4a za0.d, z12.d, z17.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4a za0.d, z12.d, z14.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4a za0.d, z12.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +// Single and multiple vectors + +fmop4a za0.s, z0.d, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4a za8.d, z0.d, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, z0.s, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4a za0.d, z1.d, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4a za0.d, z16.d, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4a za0.d, z0.d, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, z0.d, {z17.d-z18.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.d, z0.d, {z16.d-z18.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, z0.d, {z12.d-z13.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4a za0.s, {z0.d-z1.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za8.d, {z0.d-z1.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, {z0.s-z1.s}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, {z1.d-z2.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.d, {z0.d-z2.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, {z16.d-z17.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.d, {z0.d-z1.d}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4a za0.d, {z0.d-z1.d}, z17.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4a za0.d, {z0.d-z1.d}, z12.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +// Multiple vectors + +fmop4a za0.s, {z0.d-z1.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za8.d, {z0.d-z1.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, {z0.s-z1.s}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, {z1.d-z2.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.d, {z0.d-z2.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, {z18.d-z19.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.d, {z0.d-z1.d}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, {z0.d-z1.d}, {z19.d-z20.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4a za0.d, {z0.d-z1.d}, {z16.d-z18.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4a za0.d, {z0.d-z1.d}, {z10.d-z11.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// FMOP4S + +// Single vectors + +fmop4s za0.s, z0.d, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4s za8.d, z0.d, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, z0.s, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4s za0.d, z15.d, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4s za0.d, z16.d, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4s za0.d, z0.d, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4s za0.d, z12.d, z17.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4s za0.d, z12.d, z14.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4s za0.d, z12.d, z31.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +// Single and multiple vectors + +fmop4s za0.s, z0.d, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.s..z14.s + +fmop4s za8.d, z0.d, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, z0.s, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4s za0.d, z1.d, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4s za0.d, z16.d, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z0.d..z14.d + +fmop4s za0.d, z0.d, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, z0.d, {z17.d-z18.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.d, z0.d, {z16.d-z18.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, z0.d, {z12.d-z13.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +// Multiple and single vectors + +fmop4s za0.s, {z0.d-z1.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za8.d, {z0.d-z1.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, {z0.s-z1.s}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, {z1.d-z2.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.d, {z0.d-z2.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, {z16.d-z17.d}, z16.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.d, {z0.d-z1.d}, z16.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4s za0.d, {z0.d-z1.d}, z17.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +fmop4s za0.d, {z0.d-z1.d}, z12.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected even register in z16.d..z30.d + +// Multiple vectors + +fmop4s za0.s, {z0.d-z1.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za8.d, {z0.d-z1.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, {z0.s-z1.s}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, {z1.d-z2.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.d, {z0.d-z2.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, {z18.d-z19.d}, {z16.d-z17.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z0-z14, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.d, {z0.d-z1.d}, {z16.s-z17.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, {z0.d-z1.d}, {z19.d-z20.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types + +fmop4s za0.d, {z0.d-z1.d}, {z16.d-z18.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction + +fmop4s za0.d, {z0.d-z1.d}, {z10.d-z11.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors in the range z16-z30, where the first vector is a multiple of 2 and with matching element types diff --git a/llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening.s b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening.s new file mode 100644 index 0000000000000000000000000000000000000000..b0ad2984ad5acd10f4044bdb77515d6a2814501c --- /dev/null +++ b/llvm/test/MC/AArch64/SME2p2/fmop4as-fp64-non-widening.s @@ -0,0 +1,180 @@ + +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f64f64 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f64f64 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p2,+sme-f64f64 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2,+sme-f64f64 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2,+sme-f64f64 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2,+sme-f64f64 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +// FMOP4A + +// Single vectors + +fmop4a za0.d, z0.d, z16.d // 10000000-11000000-00000000-00001000 +// CHECK-INST: fmop4a za0.d, z0.d, z16.d +// CHECK-ENCODING: [0x08,0x00,0xc0,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80c00008 + +fmop4a za5.d, z10.d, z20.d // 10000000-11000100-00000001-01001101 +// CHECK-INST: fmop4a za5.d, z10.d, z20.d +// CHECK-ENCODING: [0x4d,0x01,0xc4,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80c4014d + +fmop4a za7.d, z14.d, z30.d // 10000000-11001110-00000001-11001111 +// CHECK-INST: fmop4a za7.d, z14.d, z30.d +// CHECK-ENCODING: [0xcf,0x01,0xce,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80ce01cf + +// Single and multiple vectors + +fmop4a za0.d, z0.d, {z16.d-z17.d} // 10000000-11010000-00000000-00001000 +// CHECK-INST: fmop4a za0.d, z0.d, { z16.d, z17.d } +// CHECK-ENCODING: [0x08,0x00,0xd0,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80d00008 + +fmop4a za5.d, z10.d, {z20.d-z21.d} // 10000000-11010100-00000001-01001101 +// CHECK-INST: fmop4a za5.d, z10.d, { z20.d, z21.d } +// CHECK-ENCODING: [0x4d,0x01,0xd4,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80d4014d + +fmop4a za7.d, z14.d, {z30.d-z31.d} // 10000000-11011110-00000001-11001111 +// CHECK-INST: fmop4a za7.d, z14.d, { z30.d, z31.d } +// CHECK-ENCODING: [0xcf,0x01,0xde,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80de01cf + +// Multiple and single vectors + +fmop4a za0.d, {z0.d-z1.d}, z16.d // 10000000-11000000-00000010-00001000 +// CHECK-INST: fmop4a za0.d, { z0.d, z1.d }, z16.d +// CHECK-ENCODING: [0x08,0x02,0xc0,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80c00208 + +fmop4a za5.d, {z10.d-z11.d}, z20.d // 10000000-11000100-00000011-01001101 +// CHECK-INST: fmop4a za5.d, { z10.d, z11.d }, z20.d +// CHECK-ENCODING: [0x4d,0x03,0xc4,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80c4034d + +fmop4a za7.d, {z14.d-z15.d}, z30.d // 10000000-11001110-00000011-11001111 +// CHECK-INST: fmop4a za7.d, { z14.d, z15.d }, z30.d +// CHECK-ENCODING: [0xcf,0x03,0xce,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80ce03cf + +// Multiple vectors + +fmop4a za0.d, {z0.d-z1.d}, {z16.d-z17.d} // 10000000-11010000-00000010-00001000 +// CHECK-INST: fmop4a za0.d, { z0.d, z1.d }, { z16.d, z17.d } +// CHECK-ENCODING: [0x08,0x02,0xd0,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80d00208 + +fmop4a za5.d, {z10.d-z11.d}, {z20.d-z21.d} // 10000000-11010100-00000011-01001101 +// CHECK-INST: fmop4a za5.d, { z10.d, z11.d }, { z20.d, z21.d } +// CHECK-ENCODING: [0x4d,0x03,0xd4,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80d4034d + +fmop4a za7.d, {z14.d-z15.d}, {z30.d-z31.d} // 10000000-11011110-00000011-11001111 +// CHECK-INST: fmop4a za7.d, { z14.d, z15.d }, { z30.d, z31.d } +// CHECK-ENCODING: [0xcf,0x03,0xde,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80de03cf + + +// FMOP4S + +// Single vectors + +fmop4s za0.d, z0.d, z16.d // 10000000-11000000-00000000-00011000 +// CHECK-INST: fmop4s za0.d, z0.d, z16.d +// CHECK-ENCODING: [0x18,0x00,0xc0,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80c00018 + +fmop4s za5.d, z10.d, z20.d // 10000000-11000100-00000001-01011101 +// CHECK-INST: fmop4s za5.d, z10.d, z20.d +// CHECK-ENCODING: [0x5d,0x01,0xc4,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80c4015d + +fmop4s za7.d, z14.d, z30.d // 10000000-11001110-00000001-11011111 +// CHECK-INST: fmop4s za7.d, z14.d, z30.d +// CHECK-ENCODING: [0xdf,0x01,0xce,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80ce01df + +// Single and multiple vectors + +fmop4s za0.d, z0.d, {z16.d-z17.d} // 10000000-11010000-00000000-00011000 +// CHECK-INST: fmop4s za0.d, z0.d, { z16.d, z17.d } +// CHECK-ENCODING: [0x18,0x00,0xd0,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80d00018 + +fmop4s za5.d, z10.d, {z20.d-z21.d} // 10000000-11010100-00000001-01011101 +// CHECK-INST: fmop4s za5.d, z10.d, { z20.d, z21.d } +// CHECK-ENCODING: [0x5d,0x01,0xd4,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80d4015d + +fmop4s za7.d, z14.d, {z30.d-z31.d} // 10000000-11011110-00000001-11011111 +// CHECK-INST: fmop4s za7.d, z14.d, { z30.d, z31.d } +// CHECK-ENCODING: [0xdf,0x01,0xde,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80de01df + +// Multiple and single vectors + +fmop4s za0.d, {z0.d-z1.d}, z16.d // 10000000-11000000-00000010-00011000 +// CHECK-INST: fmop4s za0.d, { z0.d, z1.d }, z16.d +// CHECK-ENCODING: [0x18,0x02,0xc0,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80c00218 + +fmop4s za5.d, {z10.d-z11.d}, z20.d // 10000000-11000100-00000011-01011101 +// CHECK-INST: fmop4s za5.d, { z10.d, z11.d }, z20.d +// CHECK-ENCODING: [0x5d,0x03,0xc4,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80c4035d + +fmop4s za7.d, {z14.d-z15.d}, z30.d // 10000000-11001110-00000011-11011111 +// CHECK-INST: fmop4s za7.d, { z14.d, z15.d }, z30.d +// CHECK-ENCODING: [0xdf,0x03,0xce,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80ce03df + +// Multiple vectors + +fmop4s za0.d, {z0.d-z1.d}, {z16.d-z17.d} // 10000000-11010000-00000010-00011000 +// CHECK-INST: fmop4s za0.d, { z0.d, z1.d }, { z16.d, z17.d } +// CHECK-ENCODING: [0x18,0x02,0xd0,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80d00218 + +fmop4s za5.d, {z10.d-z11.d}, {z20.d-z21.d} // 10000000-11010100-00000011-01011101 +// CHECK-INST: fmop4s za5.d, { z10.d, z11.d }, { z20.d, z21.d } +// CHECK-ENCODING: [0x5d,0x03,0xd4,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80d4035d + +fmop4s za7.d, {z14.d-z15.d}, {z30.d-z31.d} // 10000000-11011110-00000011-11011111 +// CHECK-INST: fmop4s za7.d, { z14.d, z15.d }, { z30.d, z31.d } +// CHECK-ENCODING: [0xdf,0x03,0xde,0x80] +// CHECK-ERROR: instruction requires: sme2p2 sme-f64f64 +// CHECK-UNKNOWN: 80de03df diff --git a/llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s b/llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s index 013f15f8b6e005020331116252ce720b31016f74..6c55ebe4088ff11a7a1a536e0072e5f64332877b 100644 --- a/llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s @@ -11,7 +11,7 @@ bfcvt z0.h, p0/m, z1.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: bfcvt z0.h, p0/z, z1.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: bfcvt z0.h, p0/z, z1.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/compact-diagnostics.s b/llvm/test/MC/AArch64/SVE/compact-diagnostics.s index a3d86267d917b53623707b72bd17935f9098fcfc..b8ff8cc46201f287a0490bcf378c4573a741f22f 100644 --- a/llvm/test/MC/AArch64/SVE/compact-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/compact-diagnostics.s @@ -28,12 +28,12 @@ compact z31.s, p7, z31.d // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: compact z31.b, p7, z31.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: compact z31.b, p7, z31.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: compact z31.h, p7, z31.h -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: compact z31.h, p7, z31.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/compact.s b/llvm/test/MC/AArch64/SVE/compact.s index ff815980781d79eb0084cf1a348c930300137330..a9b47dea246bee94cce10127ad26a2af63daebf4 100644 --- a/llvm/test/MC/AArch64/SVE/compact.s +++ b/llvm/test/MC/AArch64/SVE/compact.s @@ -12,11 +12,11 @@ compact z31.s, p7, z31.s // CHECK-INST: compact z31.s, p7, z31.s // CHECK-ENCODING: [0xff,0x9f,0xa1,0x05] -// CHECK-ERROR: instruction requires: sve +// CHECK-ERROR: instruction requires: sve or sme2p2 // CHECK-UNKNOWN: 05a19fff compact z31.d, p7, z31.d // CHECK-INST: compact z31.d, p7, z31.d // CHECK-ENCODING: [0xff,0x9f,0xe1,0x05] -// CHECK-ERROR: instruction requires: sve +// CHECK-ERROR: instruction requires: sve or sme2p2 // CHECK-UNKNOWN: 05e19fff diff --git a/llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s b/llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s index 5f365496033633a40c6ebf0af5826dc9b2548011..36c5d5fe9cbea6ac3cc672f8eeb0cf68d1b3686d 100644 --- a/llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s @@ -29,7 +29,7 @@ fcvtx z0.d, p0/m, z0.d // Invalid predicate operation fcvtx z0.s, p0/z, z0.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2 // CHECK-NEXT: fcvtx z0.s, p0/z, z0.d // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/bfcvt_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/bfcvt_z-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..30be5d19c4aae76d5a9aefbf2e5d367bafec3fef --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/bfcvt_z-diagnostics.s @@ -0,0 +1,60 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand + +bfcvt z0.b, p0/z, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: bfcvt z0.b, p0/z, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +bfcvt z0.h, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.h, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfcvt z0.h, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.h, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfcvt z0.s, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.s, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfcvt z0.s, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.s, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +bfcvt z0.d, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: bfcvt z0.d, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +bfcvt z0.h, p8/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: bfcvt z0.h, p8/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +bfcvt z0.h, p7/z, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bfcvt z0.h, p7/z, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +bfcvt z0.h, p7/z, z1.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: bfcvt z0.h, p7/z, z1.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/bfcvt_z.s b/llvm/test/MC/AArch64/SVE2p2/bfcvt_z.s new file mode 100644 index 0000000000000000000000000000000000000000..9d63ebf1e8309857dd2a37c1efaf64c15eb86696 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/bfcvt_z.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +bfcvt z0.h, p0/z, z0.s // 01100100-10011010-11000000-00000000 +// CHECK-INST: bfcvt z0.h, p0/z, z0.s +// CHECK-ENCODING: [0x00,0xc0,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649ac000 + +bfcvt z21.h, p5/z, z10.s // 01100100-10011010-11010101-01010101 +// CHECK-INST: bfcvt z21.h, p5/z, z10.s +// CHECK-ENCODING: [0x55,0xd5,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649ad555 + +bfcvt z31.h, p7/z, z31.s // 01100100-10011010-11011111-11111111 +// CHECK-INST: bfcvt z31.h, p7/z, z31.s +// CHECK-ENCODING: [0xff,0xdf,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649adfff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/compact-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/compact-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..acf00e7f7a600fb4276da5f4a412f7f3fc3d011a --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/compact-diagnostics.s @@ -0,0 +1,65 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element widths + +compact z31.h, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: compact z31.h, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z31.b, p7, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: compact z31.b, p7, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +compact z23.b, p7/m, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: compact z23.b, p7/m, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z23.b, p7.b, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: compact z23.b, p7.b, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z23.h, p7/z, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: compact z23.h, p7/z, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z23.h, p7.h, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: compact z23.h, p7.h, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +compact z23.b, p8, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: compact z23.b, p8, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +compact z23.h, p8, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: compact z23.h, p8, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31.b, p7/z, z6.b +compact z31.b, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: compact z31.b, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31, z6 +compact z31.h, p7, z31.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: compact z31.h, p7, z31.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/compact.s b/llvm/test/MC/AArch64/SVE2p2/compact.s new file mode 100644 index 0000000000000000000000000000000000000000..0170b3832bea674b09a2f545142ee720eedead27 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/compact.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +compact z0.b, p0, z0.b // 00000101-00100001-10000000-00000000 +// CHECK-INST: compact z0.b, p0, z0.b +// CHECK-ENCODING: [0x00,0x80,0x21,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05218000 + +compact z21.b, p5, z10.b // 00000101-00100001-10010101-01010101 +// CHECK-INST: compact z21.b, p5, z10.b +// CHECK-ENCODING: [0x55,0x95,0x21,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05219555 + +compact z31.h, p7, z31.h // 00000101-01100001-10011111-11111111 +// CHECK-INST: compact z31.h, p7, z31.h +// CHECK-ENCODING: [0xff,0x9f,0x61,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05619fff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/expand-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/expand-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..b9a95f399a168a7b766c9dfd1cd70b073d67636c --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/expand-diagnostics.s @@ -0,0 +1,120 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid element widths. + +expand z23.b, p3, z13.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.b, p3, z13.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p3, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.h, p3, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.s, p3, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.s, p3, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.d, p3, z13.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.d, p3, z13.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.q, p3, z13.q +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: expand z23.q, p3, z13.q +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate operation + +expand z23.b, p3/z, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: expand z23.b, p3/z, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.b, p3.b, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.b, p3.b, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p3/m, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: expand z23.h, p3/m, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p3.h, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.h, p3.h, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.s, p3/z, z13.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: expand z23.s, p3/z, z13.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.s, p3.s, z13.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.s, p3.s, z13.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.d, p3/m, z13.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: expand z23.d, p3/m, z13.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.d, p3.d, z13.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.d, p3.d, z13.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +expand z23.b, p8, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.b, p8, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.b, p3.b, z13.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.b, p3.b, z13.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p8, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.h, p8, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.h, p3.h, z13.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.h, p3.h, z13.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}} + +expand z23.s, p8, z13.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.s, p8, z13.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +expand z23.d, p8, z13.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: expand z23.d, p8, z13.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z31, z6 +expand z31.b, p7, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: expand z31.b, p7, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z31.b, p0/z, z6.b +expand z31.b, p0, z31.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: expand z31.b, p0, z31.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/expand.s b/llvm/test/MC/AArch64/SVE2p2/expand.s new file mode 100644 index 0000000000000000000000000000000000000000..7523978380fbd7e71aa8b40b8bccc10f87f2b483 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/expand.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +expand z0.b, p0, z0.b // 00000101-00110001-10000000-00000000 +// CHECK-INST: expand z0.b, p0, z0.b +// CHECK-ENCODING: [0x00,0x80,0x31,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05318000 + +expand z21.h, p5, z10.h // 00000101-01110001-10010101-01010101 +// CHECK-INST: expand z21.h, p5, z10.h +// CHECK-ENCODING: [0x55,0x95,0x71,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05719555 + +expand z23.s, p3, z13.s // 00000101-10110001-10001101-10110111 +// CHECK-INST: expand z23.s, p3, z13.s +// CHECK-ENCODING: [0xb7,0x8d,0xb1,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05b18db7 + +expand z31.d, p7, z31.d // 00000101-11110001-10011111-11111111 +// CHECK-INST: expand z31.d, p7, z31.d +// CHECK-ENCODING: [0xff,0x9f,0xf1,0x05] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 05f19fff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvt_z-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/fcvt_z-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..37f4a0ffbe6a2af04ac463559bcfff27795e67ff --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/fcvt_z-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand + +fcvt z0.b, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: fcvt z0.b, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvt z0.h, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvt z0.h, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvt z0.s, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvt z0.s, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvt z0.d, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvt z0.d, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvt z0.s, p8/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: fcvt z0.s, p8/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvt z0.s, p7/z, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvt z0.s, p7/z, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvt z0.s, p7/z, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvt z0.s, p7/z, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvt_z.s b/llvm/test/MC/AArch64/SVE2p2/fcvt_z.s new file mode 100644 index 0000000000000000000000000000000000000000..6cd9f1ba503210e691d9438d1986f8a9419ff8f1 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/fcvt_z.s @@ -0,0 +1,57 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +// convert to half + +fcvt z0.h, p0/z, z0.s // 01100100-10011010-10000000-00000000 +// CHECK-INST: fcvt z0.h, p0/z, z0.s +// CHECK-ENCODING: [0x00,0x80,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649a8000 + +fcvt z23.h, p3/z, z13.d // 01100100-11011010-10001101-10110111 +// CHECK-INST: fcvt z23.h, p3/z, z13.d +// CHECK-ENCODING: [0xb7,0x8d,0xda,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 64da8db7 + +// convert to single + +fcvt z0.s, p0/z, z0.h // 01100100-10011010-10100000-00000000 +// CHECK-INST: fcvt z0.s, p0/z, z0.h +// CHECK-ENCODING: [0x00,0xa0,0x9a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 649aa000 + +fcvt z31.s, p7/z, z31.d // 01100100-11011010-11011111-11111111 +// CHECK-INST: fcvt z31.s, p7/z, z31.d +// CHECK-ENCODING: [0xff,0xdf,0xda,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 64dadfff + +// convert to double + +fcvt z21.d, p5/z, z10.h // 01100100-11011010-10110101-01010101 +// CHECK-INST: fcvt z21.d, p5/z, z10.h +// CHECK-ENCODING: [0x55,0xb5,0xda,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 64dab555 + +fcvt z31.d, p7/z, z31.s // 01100100-11011010-11111111-11111111 +// CHECK-INST: fcvt z31.d, p7/z, z31.s +// CHECK-ENCODING: [0xff,0xff,0xda,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 64daffff &1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid element width + +fcvtx z0.b, p0/z, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.b, p0/z, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.h, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.h, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.s, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.s, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.d, p0/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.d, p0/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.h, p0/z, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.h, p0/z, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +fcvtx z0.b, p0/z, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: fcvtx z0.b, p0/z, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +fcvtx z0.s, p8/z, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: fcvtx z0.s, p8/z, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Negative tests for instructions that are incompatible with movprfx + +movprfx z0.s, p0/m, z7.s +fcvtx z0.s, p7/z, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtx z0.s, p7/z, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +movprfx z0, z7 +fcvtx z0.s, p7/z, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov +// CHECK-NEXT: fcvtx z0.s, p7/z, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/fcvtx_z.s b/llvm/test/MC/AArch64/SVE2p2/fcvtx_z.s new file mode 100644 index 0000000000000000000000000000000000000000..e5e2155ea5d8785a96cd972ad92278660e0ae5c0 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/fcvtx_z.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +fcvtx z0.s, p0/z, z0.d // 01100100-00011010-11000000-00000000 +// CHECK-INST: fcvtx z0.s, p0/z, z0.d +// CHECK-ENCODING: [0x00,0xc0,0x1a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 641ac000 + +fcvtx z23.s, p3/z, z13.d // 01100100-00011010-11001101-10110111 +// CHECK-INST: fcvtx z23.s, p3/z, z13.d +// CHECK-ENCODING: [0xb7,0xcd,0x1a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 641acdb7 + +fcvtx z31.s, p7/z, z31.d // 01100100-00011010-11011111-11111111 +// CHECK-INST: fcvtx z31.s, p7/z, z31.d +// CHECK-ENCODING: [0xff,0xdf,0x1a,0x64] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 641adfff diff --git a/llvm/test/MC/AArch64/SVE2p2/firstp-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/firstp-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..4309fd49ecf79f1500f1166bef35c4fa6803b4d8 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/firstp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid predicate operand + +firstp x0, p15, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: firstp x0, p15, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +firstp x0, p15.b, p0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: firstp x0, p15.b, p0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +firstp x0, p15.q, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: firstp x0, p15.q, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid register types + +firstp sp, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: firstp sp, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +firstp w0, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: firstp w0, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p2/firstp.s b/llvm/test/MC/AArch64/SVE2p2/firstp.s new file mode 100644 index 0000000000000000000000000000000000000000..629bee5576fc7d7c795ca18fbd918cfecc050675 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/firstp.s @@ -0,0 +1,87 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +firstp x0, p0, p0.b // 00100101-00100001-10000000-00000000 +// CHECK-INST: firstp x0, p0, p0.b +// CHECK-ENCODING: [0x00,0x80,0x21,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25218000 + +firstp x23, p11, p13.b // 00100101-00100001-10101101-10110111 +// CHECK-INST: firstp x23, p11, p13.b +// CHECK-ENCODING: [0xb7,0xad,0x21,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2521adb7 + +firstp xzr, p15, p15.b // 00100101-00100001-10111101-11111111 +// CHECK-INST: firstp xzr, p15, p15.b +// CHECK-ENCODING: [0xff,0xbd,0x21,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2521bdff + +firstp x0, p0, p0.h // 00100101-01100001-10000000-00000000 +// CHECK-INST: firstp x0, p0, p0.h +// CHECK-ENCODING: [0x00,0x80,0x61,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25618000 + +firstp x23, p11, p13.h // 00100101-01100001-10101101-10110111 +// CHECK-INST: firstp x23, p11, p13.h +// CHECK-ENCODING: [0xb7,0xad,0x61,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2561adb7 + +firstp xzr, p15, p15.h // 00100101-01100001-10111101-11111111 +// CHECK-INST: firstp xzr, p15, p15.h +// CHECK-ENCODING: [0xff,0xbd,0x61,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2561bdff + +firstp x0, p0, p0.s // 00100101-10100001-10000000-00000000 +// CHECK-INST: firstp x0, p0, p0.s +// CHECK-ENCODING: [0x00,0x80,0xa1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a18000 + +firstp x23, p11, p13.s // 00100101-10100001-10101101-10110111 +// CHECK-INST: firstp x23, p11, p13.s +// CHECK-ENCODING: [0xb7,0xad,0xa1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a1adb7 + +firstp xzr, p15, p15.s // 00100101-10100001-10111101-11111111 +// CHECK-INST: firstp xzr, p15, p15.s +// CHECK-ENCODING: [0xff,0xbd,0xa1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a1bdff + +firstp x0, p0, p0.d // 00100101-11100001-10000000-00000000 +// CHECK-INST: firstp x0, p0, p0.d +// CHECK-ENCODING: [0x00,0x80,0xe1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e18000 + +firstp x23, p11, p13.d // 00100101-11100001-10101101-10110111 +// CHECK-INST: firstp x23, p11, p13.d +// CHECK-ENCODING: [0xb7,0xad,0xe1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e1adb7 + +firstp xzr, p15, p15.d // 00100101-11100001-10111101-11111111 +// CHECK-INST: firstp xzr, p15, p15.d +// CHECK-ENCODING: [0xff,0xbd,0xe1,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e1bdff \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/lastp-diagnostics.s b/llvm/test/MC/AArch64/SVE2p2/lastp-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..e277bdbc6aa8b3514fb241682016a1df0ba4710c --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/lastp-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid predicate operand + +lastp x0, p15, p0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: lastp x0, p15, p0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastp x0, p15.b, p0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: lastp x0, p15.b, p0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastp x0, p15.q, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register. +// CHECK-NEXT: lastp x0, p15.q, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// ------------------------------------------------------------------------- // +// Invalid register types + +lastp sp, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: lastp sp, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lastp w0, p15, p0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: lastp w0, p15, p0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: \ No newline at end of file diff --git a/llvm/test/MC/AArch64/SVE2p2/lastp.s b/llvm/test/MC/AArch64/SVE2p2/lastp.s new file mode 100644 index 0000000000000000000000000000000000000000..1ffa0a7d1fcc1982f7a97b45c999510e23a501e7 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2p2/lastp.s @@ -0,0 +1,87 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// Disassemble encoding and check the re-encoding (-show-encoding) matches. +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +lastp x0, p0, p0.b // 00100101-00100010-10000000-00000000 +// CHECK-INST: lastp x0, p0, p0.b +// CHECK-ENCODING: [0x00,0x80,0x22,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25228000 + +lastp x23, p11, p13.b // 00100101-00100010-10101101-10110111 +// CHECK-INST: lastp x23, p11, p13.b +// CHECK-ENCODING: [0xb7,0xad,0x22,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2522adb7 + +lastp xzr, p15, p15.b // 00100101-00100010-10111101-11111111 +// CHECK-INST: lastp xzr, p15, p15.b +// CHECK-ENCODING: [0xff,0xbd,0x22,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2522bdff + +lastp x0, p0, p0.h // 00100101-01100010-10000000-00000000 +// CHECK-INST: lastp x0, p0, p0.h +// CHECK-ENCODING: [0x00,0x80,0x62,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25628000 + +lastp x23, p11, p13.h // 00100101-01100010-10101101-10110111 +// CHECK-INST: lastp x23, p11, p13.h +// CHECK-ENCODING: [0xb7,0xad,0x62,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2562adb7 + +lastp xzr, p15, p15.h // 00100101-01100010-10111101-11111111 +// CHECK-INST: lastp xzr, p15, p15.h +// CHECK-ENCODING: [0xff,0xbd,0x62,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 2562bdff + +lastp x0, p0, p0.s // 00100101-10100010-10000000-00000000 +// CHECK-INST: lastp x0, p0, p0.s +// CHECK-ENCODING: [0x00,0x80,0xa2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a28000 + +lastp x23, p11, p13.s // 00100101-10100010-10101101-10110111 +// CHECK-INST: lastp x23, p11, p13.s +// CHECK-ENCODING: [0xb7,0xad,0xa2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a2adb7 + +lastp xzr, p15, p15.s // 00100101-10100010-10111101-11111111 +// CHECK-INST: lastp xzr, p15, p15.s +// CHECK-ENCODING: [0xff,0xbd,0xa2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25a2bdff + +lastp x0, p0, p0.d // 00100101-11100010-10000000-00000000 +// CHECK-INST: lastp x0, p0, p0.d +// CHECK-ENCODING: [0x00,0x80,0xe2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e28000 + +lastp x23, p11, p13.d // 00100101-11100010-10101101-10110111 +// CHECK-INST: lastp x23, p11, p13.d +// CHECK-ENCODING: [0xb7,0xad,0xe2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e2adb7 + +lastp xzr, p15, p15.d // 00100101-11100010-10111101-11111111 +// CHECK-INST: lastp xzr, p15, p15.d +// CHECK-ENCODING: [0xff,0xbd,0xe2,0x25] +// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 +// CHECK-UNKNOWN: 25e2bdff \ No newline at end of file diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2-fake16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2-fake16.s new file mode 100644 index 0000000000000000000000000000000000000000..96dd57208943615a3b075ca5be6a5d17180c6357 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2-fake16.s @@ -0,0 +1,2554 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s + +v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo +// W32: encoding: [0x01,0x05,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo +// W32: encoding: [0xff,0x05,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo +// W32: encoding: [0x01,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo +// W32: encoding: [0x69,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo +// W32: encoding: [0x6a,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo +// W32: encoding: [0x6b,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo +// W32: encoding: [0x7b,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo +// W32: encoding: [0x7d,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo +// W32: encoding: [0x7e,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo +// W32: encoding: [0x7f,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo +// W32: encoding: [0x7c,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo +// W32: encoding: [0xc1,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo +// W32: encoding: [0xf0,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo +// W32: encoding: [0xfd,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo +// W32: encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc +// W64: encoding: [0x01,0x05,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v255, v2, vcc +// W64: encoding: [0xff,0x05,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, s1, v2, vcc +// W64: encoding: [0x01,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, s105, v2, vcc +// W64: encoding: [0x69,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, vcc_lo, v2, vcc +// W64: encoding: [0x6a,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, vcc_hi, v2, vcc +// W64: encoding: [0x6b,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, ttmp15, v2, vcc +// W64: encoding: [0x7b,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, m0, v2, vcc +// W64: encoding: [0x7d,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, exec_lo, v2, vcc +// W64: encoding: [0x7e,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, exec_hi, v2, vcc +// W64: encoding: [0x7f,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, null, v2, vcc +// W64: encoding: [0x7c,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, -1, v2, vcc +// W64: encoding: [0xc1,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, 0.5, v2, vcc +// W64: encoding: [0xf0,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, src_scc, v2, vcc +// W64: encoding: [0xfd,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc +// W64: encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x64] + +v_add_f16 v5, v127, v2 +// GFX11: encoding: [0x7f,0x05,0x0a,0x64] + +v_add_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x64] + +v_add_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x64] + +v_add_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x64] + +v_add_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x64] + +v_add_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x64] + +v_add_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x64] + +v_add_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x64] + +v_add_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x64] + +v_add_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x64] + +v_add_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x64] + +v_add_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x64] + +v_add_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x64] + +v_add_f16 v127, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00] + +v_add_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x06] + +v_add_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x06] + +v_add_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x06] + +v_add_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x06] + +v_add_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x06] + +v_add_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x06] + +v_add_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x06] + +v_add_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x06] + +v_add_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x06] + +v_add_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x06] + +v_add_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x06] + +v_add_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x06] + +v_add_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x06] + +v_add_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x06] + +v_add_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf] + +v_add_nc_u32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x4a] + +v_add_nc_u32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x4a] + +v_add_nc_u32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x4a] + +v_add_nc_u32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf] + +v_and_b32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x36] + +v_and_b32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x36] + +v_and_b32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x36] + +v_and_b32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x36] + +v_and_b32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x36] + +v_and_b32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x36] + +v_and_b32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x36] + +v_and_b32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x36] + +v_and_b32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x36] + +v_and_b32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x36] + +v_and_b32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x36] + +v_and_b32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x36] + +v_and_b32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x36] + +v_and_b32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x36] + +v_and_b32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf] + +v_ashrrev_i32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x34] + +v_ashrrev_i32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x34] + +v_ashrrev_i32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x34] + +v_ashrrev_i32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf] + +v_cndmask_b32 v5, v1, v2, vcc_lo +// W32: encoding: [0x01,0x05,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v255, v2, vcc_lo +// W32: encoding: [0xff,0x05,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, s1, v2, vcc_lo +// W32: encoding: [0x01,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, s105, v2, vcc_lo +// W32: encoding: [0x69,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, vcc_lo, v2, vcc_lo +// W32: encoding: [0x6a,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, vcc_hi, v2, vcc_lo +// W32: encoding: [0x6b,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, ttmp15, v2, vcc_lo +// W32: encoding: [0x7b,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, m0, v2, vcc_lo +// W32: encoding: [0x7d,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, exec_lo, v2, vcc_lo +// W32: encoding: [0x7e,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, exec_hi, v2, vcc_lo +// W32: encoding: [0x7f,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, null, v2, vcc_lo +// W32: encoding: [0x7c,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, -1, v2, vcc_lo +// W32: encoding: [0xc1,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, 0.5, v2, vcc_lo +// W32: encoding: [0xf0,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, src_scc, v2, vcc_lo +// W32: encoding: [0xfd,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, 0xaf123456, v255, vcc_lo +// W32: encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc +// W64: encoding: [0x01,0x05,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v255, v2, vcc +// W64: encoding: [0xff,0x05,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, s1, v2, vcc +// W64: encoding: [0x01,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, s105, v2, vcc +// W64: encoding: [0x69,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, vcc_lo, v2, vcc +// W64: encoding: [0x6a,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, vcc_hi, v2, vcc +// W64: encoding: [0x6b,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, ttmp15, v2, vcc +// W64: encoding: [0x7b,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, m0, v2, vcc +// W64: encoding: [0x7d,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, exec_lo, v2, vcc +// W64: encoding: [0x7e,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, exec_hi, v2, vcc +// W64: encoding: [0x7f,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, null, v2, vcc +// W64: encoding: [0x7c,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, -1, v2, vcc +// W64: encoding: [0xc1,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, 0.5, v2, vcc +// W64: encoding: [0xf0,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, src_scc, v2, vcc +// W64: encoding: [0xfd,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, 0xaf123456, v255, vcc +// W64: encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf] + +v_dot2acc_f32_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x04] + +v_dot2acc_f32_f16 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x04] + +v_dot2acc_f32_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x04] + +v_dot2acc_f32_f16 v255, 0xfe0b, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x05,0x0b,0xfe,0x00,0x00] + +v_dot2c_f32_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x04] + +v_dot2c_f32_f16 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x04] + +v_dot2c_f32_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x04] + +v_dot2c_f32_f16 v255, 0xfe0b, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x05,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, v1, v2, 0xfe0b +// GFX11: encoding: [0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, v127, v2, 0xfe0b +// GFX11: encoding: [0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, s1, v2, 0xfe0b +// GFX11: encoding: [0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, s105, v2, 0xfe0b +// GFX11: encoding: [0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, vcc_lo, v2, 0xfe0b +// GFX11: encoding: [0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, vcc_hi, v2, 0xfe0b +// GFX11: encoding: [0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, ttmp15, v2, 0xfe0b +// GFX11: encoding: [0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, m0, v2, 0xfe0b +// GFX11: encoding: [0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, exec_lo, v2, 0xfe0b +// GFX11: encoding: [0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, exec_hi, v2, 0xfe0b +// GFX11: encoding: [0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, null, v2, 0xfe0b +// GFX11: encoding: [0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, -1, v2, 0xfe0b +// GFX11: encoding: [0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, 0.5, v2, 0xfe0b +// GFX11: encoding: [0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, src_scc, v2, 0xfe0b +// GFX11: encoding: [0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v127, 0xfe0b, v127, 0xfe0b +// GFX11: encoding: [0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f32 v5, v1, v2, 0xaf123456 +// GFX11: encoding: [0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, v255, v2, 0xaf123456 +// GFX11: encoding: [0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, s1, v2, 0xaf123456 +// GFX11: encoding: [0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, s105, v2, 0xaf123456 +// GFX11: encoding: [0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, vcc_lo, v2, 0xaf123456 +// GFX11: encoding: [0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, vcc_hi, v2, 0xaf123456 +// GFX11: encoding: [0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, ttmp15, v2, 0xaf123456 +// GFX11: encoding: [0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, m0, v2, 0xaf123456 +// GFX11: encoding: [0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, exec_lo, v2, 0xaf123456 +// GFX11: encoding: [0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, exec_hi, v2, 0xaf123456 +// GFX11: encoding: [0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, null, v2, 0xaf123456 +// GFX11: encoding: [0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, -1, v2, 0xaf123456 +// GFX11: encoding: [0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, 0.5, v2, 0xaf123456 +// GFX11: encoding: [0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, src_scc, v2, 0xaf123456 +// GFX11: encoding: [0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 +// GFX11: encoding: [0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf] + +v_fmac_dx9_zero_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x0c] + +v_fmac_dx9_zero_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x0d,0x56,0x34,0x12,0xaf] + +v_fmac_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x6c] + +v_fmac_f16 v5, v127, v2 +// GFX11: encoding: [0x7f,0x05,0x0a,0x6c] + +v_fmac_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x6c] + +v_fmac_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x6c] + +v_fmac_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x6c] + +v_fmac_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x6c] + +v_fmac_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x6c] + +v_fmac_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x6c] + +v_fmac_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x6c] + +v_fmac_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x6c] + +v_fmac_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x6c] + +v_fmac_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x6c] + +v_fmac_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x6c] + +v_fmac_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x6c] + +v_fmac_f16 v127, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00] + +v_fmac_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x56] + +v_fmac_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x56] + +v_fmac_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x56] + +v_fmac_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x56] + +v_fmac_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x56] + +v_fmac_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x56] + +v_fmac_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x56] + +v_fmac_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x56] + +v_fmac_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x56] + +v_fmac_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x56] + +v_fmac_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x56] + +v_fmac_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x56] + +v_fmac_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x56] + +v_fmac_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x56] + +v_fmac_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf] + +v_fmac_legacy_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x0c] + +v_fmac_legacy_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x0c] + +v_fmac_legacy_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x0c] + +v_fmac_legacy_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x0d,0x56,0x34,0x12,0xaf] + +v_fmamk_f16 v5, v1, 0xfe0b, v3 +// GFX11: encoding: [0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, v127, 0xfe0b, v3 +// GFX11: encoding: [0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, s1, 0xfe0b, v3 +// GFX11: encoding: [0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, s105, 0xfe0b, v3 +// GFX11: encoding: [0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, vcc_lo, 0xfe0b, v3 +// GFX11: encoding: [0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, vcc_hi, 0xfe0b, v3 +// GFX11: encoding: [0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, ttmp15, 0xfe0b, v3 +// GFX11: encoding: [0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, m0, 0xfe0b, v3 +// GFX11: encoding: [0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, exec_lo, 0xfe0b, v3 +// GFX11: encoding: [0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, exec_hi, 0xfe0b, v3 +// GFX11: encoding: [0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, null, 0xfe0b, v3 +// GFX11: encoding: [0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, -1, 0xfe0b, v3 +// GFX11: encoding: [0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, 0.5, 0xfe0b, v3 +// GFX11: encoding: [0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, src_scc, 0xfe0b, v3 +// GFX11: encoding: [0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v127, 0xfe0b, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f32 v5, v1, 0xaf123456, v3 +// GFX11: encoding: [0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, v255, 0xaf123456, v3 +// GFX11: encoding: [0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, s1, 0xaf123456, v3 +// GFX11: encoding: [0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, s105, 0xaf123456, v3 +// GFX11: encoding: [0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, vcc_lo, 0xaf123456, v3 +// GFX11: encoding: [0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, vcc_hi, 0xaf123456, v3 +// GFX11: encoding: [0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, ttmp15, 0xaf123456, v3 +// GFX11: encoding: [0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, m0, 0xaf123456, v3 +// GFX11: encoding: [0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, exec_lo, 0xaf123456, v3 +// GFX11: encoding: [0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, exec_hi, 0xaf123456, v3 +// GFX11: encoding: [0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, null, 0xaf123456, v3 +// GFX11: encoding: [0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, -1, 0xaf123456, v3 +// GFX11: encoding: [0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, 0.5, 0xaf123456, v3 +// GFX11: encoding: [0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, src_scc, 0xaf123456, v3 +// GFX11: encoding: [0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf] + +v_ldexp_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x76] + +v_ldexp_f16 v5, v127, v2 +// GFX11: encoding: [0x7f,0x05,0x0a,0x76] + +v_ldexp_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x76] + +v_ldexp_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x76] + +v_ldexp_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x76] + +v_ldexp_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x76] + +v_ldexp_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x76] + +v_ldexp_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x76] + +v_ldexp_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x76] + +v_ldexp_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x76] + +v_ldexp_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x76] + +v_ldexp_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x76] + +v_ldexp_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x76] + +v_ldexp_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x76] + +v_ldexp_f16 v127, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] + +v_lshlrev_b32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x30] + +v_lshlrev_b32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x30] + +v_lshlrev_b32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x30] + +v_lshlrev_b32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf] + +v_lshrrev_b32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x32] + +v_lshrrev_b32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x32] + +v_lshrrev_b32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x32] + +v_lshrrev_b32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf] + +v_max_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x72] + +v_max_f16 v5, v127, v2 +// GFX11: encoding: [0x7f,0x05,0x0a,0x72] + +v_max_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x72] + +v_max_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x72] + +v_max_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x72] + +v_max_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x72] + +v_max_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x72] + +v_max_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x72] + +v_max_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x72] + +v_max_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x72] + +v_max_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x72] + +v_max_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x72] + +v_max_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x72] + +v_max_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x72] + +v_max_f16 v127, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00] + +v_max_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x20] + +v_max_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x20] + +v_max_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x20] + +v_max_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x20] + +v_max_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x20] + +v_max_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x20] + +v_max_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x20] + +v_max_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x20] + +v_max_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x20] + +v_max_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x20] + +v_max_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x20] + +v_max_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x20] + +v_max_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x20] + +v_max_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x20] + +v_max_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x21,0x56,0x34,0x12,0xaf] + +v_max_i32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x24] + +v_max_i32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x24] + +v_max_i32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x24] + +v_max_i32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x24] + +v_max_i32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x24] + +v_max_i32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x24] + +v_max_i32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x24] + +v_max_i32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x24] + +v_max_i32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x24] + +v_max_i32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x24] + +v_max_i32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x24] + +v_max_i32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x24] + +v_max_i32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x24] + +v_max_i32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x24] + +v_max_i32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf] + +v_max_u32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x28] + +v_max_u32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x28] + +v_max_u32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x28] + +v_max_u32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x28] + +v_max_u32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x28] + +v_max_u32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x28] + +v_max_u32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x28] + +v_max_u32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x28] + +v_max_u32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x28] + +v_max_u32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x28] + +v_max_u32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x28] + +v_max_u32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x28] + +v_max_u32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x28] + +v_max_u32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x28] + +v_max_u32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf] + +v_min_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x74] + +v_min_f16 v5, v127, v2 +// GFX11: encoding: [0x7f,0x05,0x0a,0x74] + +v_min_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x74] + +v_min_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x74] + +v_min_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x74] + +v_min_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x74] + +v_min_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x74] + +v_min_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x74] + +v_min_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x74] + +v_min_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x74] + +v_min_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x74] + +v_min_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x74] + +v_min_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x74] + +v_min_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x74] + +v_min_f16 v127, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00] + +v_min_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x1e] + +v_min_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x1e] + +v_min_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x1e] + +v_min_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x1e] + +v_min_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x1e] + +v_min_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x1e] + +v_min_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x1e] + +v_min_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x1e] + +v_min_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x1e] + +v_min_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x1e] + +v_min_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x1e] + +v_min_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x1e] + +v_min_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x1e] + +v_min_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x1e] + +v_min_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x1f,0x56,0x34,0x12,0xaf] + +v_min_i32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x22] + +v_min_i32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x22] + +v_min_i32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x22] + +v_min_i32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x22] + +v_min_i32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x22] + +v_min_i32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x22] + +v_min_i32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x22] + +v_min_i32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x22] + +v_min_i32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x22] + +v_min_i32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x22] + +v_min_i32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x22] + +v_min_i32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x22] + +v_min_i32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x22] + +v_min_i32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x22] + +v_min_i32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf] + +v_min_u32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x26] + +v_min_u32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x26] + +v_min_u32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x26] + +v_min_u32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x26] + +v_min_u32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x26] + +v_min_u32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x26] + +v_min_u32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x26] + +v_min_u32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x26] + +v_min_u32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x26] + +v_min_u32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x26] + +v_min_u32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x26] + +v_min_u32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x26] + +v_min_u32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x26] + +v_min_u32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x26] + +v_min_u32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf] + +v_mul_dx9_zero_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] + +v_mul_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x6a] + +v_mul_f16 v5, v127, v2 +// GFX11: encoding: [0x7f,0x05,0x0a,0x6a] + +v_mul_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x6a] + +v_mul_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x6a] + +v_mul_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x6a] + +v_mul_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x6a] + +v_mul_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x6a] + +v_mul_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x6a] + +v_mul_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x6a] + +v_mul_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x6a] + +v_mul_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x6a] + +v_mul_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x6a] + +v_mul_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x6a] + +v_mul_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x6a] + +v_mul_f16 v127, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] + +v_mul_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x10] + +v_mul_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x10] + +v_mul_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x10] + +v_mul_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x10] + +v_mul_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x10] + +v_mul_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x10] + +v_mul_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x10] + +v_mul_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x10] + +v_mul_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x10] + +v_mul_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x10] + +v_mul_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x10] + +v_mul_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x10] + +v_mul_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x10] + +v_mul_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x10] + +v_mul_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf] + +v_mul_hi_i32_i24 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x14] + +v_mul_hi_i32_i24 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x14] + +v_mul_hi_i32_i24 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf] + +v_mul_hi_u32_u24 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x18] + +v_mul_hi_u32_u24 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x18] + +v_mul_hi_u32_u24 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf] + +v_mul_i32_i24 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x12] + +v_mul_i32_i24 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x12] + +v_mul_i32_i24 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x12] + +v_mul_i32_i24 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf] + +v_mul_legacy_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x0e] + +v_mul_legacy_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x0e] + +v_mul_legacy_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] + +v_mul_u32_u24 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x16] + +v_mul_u32_u24 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x16] + +v_mul_u32_u24 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x16] + +v_mul_u32_u24 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf] + +v_or_b32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x38] + +v_or_b32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x38] + +v_or_b32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x38] + +v_or_b32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x38] + +v_or_b32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x38] + +v_or_b32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x38] + +v_or_b32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x38] + +v_or_b32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x38] + +v_or_b32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x38] + +v_or_b32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x38] + +v_or_b32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x38] + +v_or_b32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x38] + +v_or_b32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x38] + +v_or_b32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x38] + +v_or_b32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf] + +v_pk_fmac_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x78] + +v_pk_fmac_f16 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x78] + +v_pk_fmac_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x78] + +v_pk_fmac_f16 v255, 0xfe0b, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00] + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo +// W32: encoding: [0x01,0x05,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo +// W32: encoding: [0xff,0x05,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo +// W32: encoding: [0x01,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo +// W32: encoding: [0x69,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo +// W32: encoding: [0x6a,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo +// W32: encoding: [0x6b,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo +// W32: encoding: [0x7b,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo +// W32: encoding: [0x7d,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo +// W32: encoding: [0x7e,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo +// W32: encoding: [0x7f,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo +// W32: encoding: [0x7c,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo +// W32: encoding: [0xc1,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo +// W32: encoding: [0xf0,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo +// W32: encoding: [0xfd,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo +// W32: encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc +// W64: encoding: [0x01,0x05,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v255, v2, vcc +// W64: encoding: [0xff,0x05,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, s1, v2, vcc +// W64: encoding: [0x01,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, s105, v2, vcc +// W64: encoding: [0x69,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, vcc_lo, v2, vcc +// W64: encoding: [0x6a,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, vcc_hi, v2, vcc +// W64: encoding: [0x6b,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, ttmp15, v2, vcc +// W64: encoding: [0x7b,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, m0, v2, vcc +// W64: encoding: [0x7d,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, exec_lo, v2, vcc +// W64: encoding: [0x7e,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, exec_hi, v2, vcc +// W64: encoding: [0x7f,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, null, v2, vcc +// W64: encoding: [0x7c,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, -1, v2, vcc +// W64: encoding: [0xc1,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, 0.5, v2, vcc +// W64: encoding: [0xf0,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, src_scc, v2, vcc +// W64: encoding: [0xfd,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc +// W64: encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x66] + +v_sub_f16 v5, v127, v2 +// GFX11: encoding: [0x7f,0x05,0x0a,0x66] + +v_sub_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x66] + +v_sub_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x66] + +v_sub_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x66] + +v_sub_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x66] + +v_sub_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x66] + +v_sub_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x66] + +v_sub_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x66] + +v_sub_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x66] + +v_sub_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x66] + +v_sub_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x66] + +v_sub_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x66] + +v_sub_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x66] + +v_sub_f16 v127, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00] + +v_sub_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x08] + +v_sub_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x08] + +v_sub_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x08] + +v_sub_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x08] + +v_sub_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x08] + +v_sub_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x08] + +v_sub_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x08] + +v_sub_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x08] + +v_sub_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x08] + +v_sub_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x08] + +v_sub_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x08] + +v_sub_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x08] + +v_sub_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x08] + +v_sub_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x08] + +v_sub_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf] + +v_sub_nc_u32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x4c] + +v_sub_nc_u32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x4c] + +v_sub_nc_u32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x4c] + +v_sub_nc_u32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf] + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo +// W32: encoding: [0x01,0x05,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo +// W32: encoding: [0xff,0x05,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo +// W32: encoding: [0x01,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo +// W32: encoding: [0x69,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo +// W32: encoding: [0x6a,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo +// W32: encoding: [0x6b,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo +// W32: encoding: [0x7b,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo +// W32: encoding: [0x7d,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo +// W32: encoding: [0x7e,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo +// W32: encoding: [0x7f,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo +// W32: encoding: [0x7c,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo +// W32: encoding: [0xc1,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo +// W32: encoding: [0xf0,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo +// W32: encoding: [0xfd,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo +// W32: encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc +// W64: encoding: [0x01,0x05,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v255, v2, vcc +// W64: encoding: [0xff,0x05,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, s1, v2, vcc +// W64: encoding: [0x01,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, s105, v2, vcc +// W64: encoding: [0x69,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, vcc_lo, v2, vcc +// W64: encoding: [0x6a,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, vcc_hi, v2, vcc +// W64: encoding: [0x6b,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, ttmp15, v2, vcc +// W64: encoding: [0x7b,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, m0, v2, vcc +// W64: encoding: [0x7d,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, exec_lo, v2, vcc +// W64: encoding: [0x7e,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, exec_hi, v2, vcc +// W64: encoding: [0x7f,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, null, v2, vcc +// W64: encoding: [0x7c,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, -1, v2, vcc +// W64: encoding: [0xc1,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, 0.5, v2, vcc +// W64: encoding: [0xf0,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, src_scc, v2, vcc +// W64: encoding: [0xfd,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc +// W64: encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_f16 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x68] + +v_subrev_f16 v5, v127, v2 +// GFX11: encoding: [0x7f,0x05,0x0a,0x68] + +v_subrev_f16 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x68] + +v_subrev_f16 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x68] + +v_subrev_f16 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x68] + +v_subrev_f16 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x68] + +v_subrev_f16 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x68] + +v_subrev_f16 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x68] + +v_subrev_f16 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x68] + +v_subrev_f16 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x68] + +v_subrev_f16 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x68] + +v_subrev_f16 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x68] + +v_subrev_f16 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x68] + +v_subrev_f16 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x68] + +v_subrev_f16 v127, 0xfe0b, v127 +// GFX11: encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00] + +v_subrev_f32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x0a] + +v_subrev_f32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x0a] + +v_subrev_f32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x0a] + +v_subrev_f32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x0a] + +v_subrev_f32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x0a] + +v_subrev_f32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x0a] + +v_subrev_f32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x0a] + +v_subrev_f32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x0a] + +v_subrev_f32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x0a] + +v_subrev_f32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x0a] + +v_subrev_f32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x0a] + +v_subrev_f32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x0a] + +v_subrev_f32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x0a] + +v_subrev_f32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x0a] + +v_subrev_f32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf] + +v_subrev_nc_u32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x4e] + +v_subrev_nc_u32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x4e] + +v_subrev_nc_u32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf] + +v_xnor_b32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x3c] + +v_xnor_b32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x3c] + +v_xnor_b32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x3c] + +v_xnor_b32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x3c] + +v_xnor_b32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x3c] + +v_xnor_b32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x3c] + +v_xnor_b32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x3c] + +v_xnor_b32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x3c] + +v_xnor_b32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x3c] + +v_xnor_b32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x3c] + +v_xnor_b32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x3c] + +v_xnor_b32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x3c] + +v_xnor_b32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x3c] + +v_xnor_b32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x3c] + +v_xnor_b32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf] + +v_xor_b32 v5, v1, v2 +// GFX11: encoding: [0x01,0x05,0x0a,0x3a] + +v_xor_b32 v5, v255, v2 +// GFX11: encoding: [0xff,0x05,0x0a,0x3a] + +v_xor_b32 v5, s1, v2 +// GFX11: encoding: [0x01,0x04,0x0a,0x3a] + +v_xor_b32 v5, s105, v2 +// GFX11: encoding: [0x69,0x04,0x0a,0x3a] + +v_xor_b32 v5, vcc_lo, v2 +// GFX11: encoding: [0x6a,0x04,0x0a,0x3a] + +v_xor_b32 v5, vcc_hi, v2 +// GFX11: encoding: [0x6b,0x04,0x0a,0x3a] + +v_xor_b32 v5, ttmp15, v2 +// GFX11: encoding: [0x7b,0x04,0x0a,0x3a] + +v_xor_b32 v5, m0, v2 +// GFX11: encoding: [0x7d,0x04,0x0a,0x3a] + +v_xor_b32 v5, exec_lo, v2 +// GFX11: encoding: [0x7e,0x04,0x0a,0x3a] + +v_xor_b32 v5, exec_hi, v2 +// GFX11: encoding: [0x7f,0x04,0x0a,0x3a] + +v_xor_b32 v5, null, v2 +// GFX11: encoding: [0x7c,0x04,0x0a,0x3a] + +v_xor_b32 v5, -1, v2 +// GFX11: encoding: [0xc1,0x04,0x0a,0x3a] + +v_xor_b32 v5, 0.5, v2 +// GFX11: encoding: [0xf0,0x04,0x0a,0x3a] + +v_xor_b32 v5, src_scc, v2 +// GFX11: encoding: [0xfd,0x04,0x0a,0x3a] + +v_xor_b32 v255, 0xaf123456, v255 +// GFX11: encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s index fb300b2e94972d8dde1dc167a0bc8cf02c6f997d..2a4b3ea201701320ded5c9f3574624f7be95b22c 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2.s @@ -1,7 +1,7 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo // W32: encoding: [0x01,0x05,0x0a,0x40] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16-fake16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16-fake16.s new file mode 100644 index 0000000000000000000000000000000000000000..6b9092f501e5af61b90312af0ffd39c69af29f62 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16-fake16.s @@ -0,0 +1,2114 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s + +v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff] + +v_add_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff] + +v_add_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff] + +v_add_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff] + +v_add_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff] + +v_add_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff] + +v_add_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff] + +v_add_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff] + +v_add_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff] + +v_add_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff] + +v_add_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff] + +v_add_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01] + +v_add_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x09,0x13] + +v_add_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xf5,0x30] + +v_add_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff] + +v_add_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff] + +v_add_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff] + +v_add_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff] + +v_add_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff] + +v_add_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff] + +v_add_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff] + +v_add_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff] + +v_add_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff] + +v_add_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff] + +v_add_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff] + +v_add_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01] + +v_add_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x09,0x13] + +v_add_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xf5,0x30] + +v_add_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff] + +v_add_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff] + +v_add_nc_u32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01] + +v_add_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x09,0x13] + +v_add_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x05,0x30] + +v_and_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff] + +v_and_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff] + +v_and_b32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff] + +v_and_b32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff] + +v_and_b32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff] + +v_and_b32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff] + +v_and_b32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff] + +v_and_b32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff] + +v_and_b32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff] + +v_and_b32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff] + +v_and_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff] + +v_and_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01] + +v_and_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x09,0x13] + +v_and_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x05,0x30] + +v_ashrrev_i32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff] + +v_ashrrev_i32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff] + +v_ashrrev_i32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01] + +v_ashrrev_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x09,0x13] + +v_ashrrev_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x05,0x30] + +v_cndmask_b32 v5, v1, v2, vcc_lo quad_perm:[3,2,1,0] +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_half_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_shl:1 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_shl:15 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_shr:1 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_shr:15 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_ror:1 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_ror:15 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc quad_perm:[3,2,1,0] +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc quad_perm:[0,1,2,3] +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_half_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_shl:1 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_shl:15 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_shr:1 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_shr:15 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_ror:1 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_ror:15 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x09,0x13] + +v_cvt_pk_rtz_f16_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xf5,0x30] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x09,0x13] + +v_cvt_pkrtz_f16_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xf5,0x30] + +v_dot2acc_f32_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x50,0x01,0xff] + +v_dot2acc_f32_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x5f,0x01,0x01] + +v_dot2acc_f32_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x60,0x09,0x13] + +v_dot2acc_f32_f16 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x05,0xff,0x6f,0xf5,0x30] + +v_dot2c_f32_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0xff] + +v_dot2c_f32_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x50,0x01,0xff] + +v_dot2c_f32_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x5f,0x01,0x01] + +v_dot2c_f32_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x04,0x01,0x60,0x09,0x13] + +v_dot2c_f32_f16 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x05,0xff,0x6f,0xf5,0x30] + +v_fmac_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff] + +v_fmac_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff] + +v_fmac_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01] + +v_fmac_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x60,0x09,0x13] + +v_fmac_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xf5,0x30] + +v_fmac_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff] + +v_fmac_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff] + +v_fmac_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01] + +v_fmac_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x09,0x13] + +v_fmac_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xf5,0x30] + +v_ldexp_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff] + +v_ldexp_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff] + +v_ldexp_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01] + +v_ldexp_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x09,0x13] + +v_ldexp_f16 v127, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x35,0x30] + +v_lshlrev_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff] + +v_lshlrev_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff] + +v_lshlrev_b32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01] + +v_lshlrev_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x09,0x13] + +v_lshlrev_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x05,0x30] + +v_lshrrev_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff] + +v_lshrrev_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff] + +v_lshrrev_b32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01] + +v_lshrrev_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x09,0x13] + +v_lshrrev_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x05,0x30] + +v_max_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0xff] + +v_max_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xff] + +v_max_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0xff] + +v_max_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0xff] + +v_max_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0xff] + +v_max_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0xff] + +v_max_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0xff] + +v_max_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0xff] + +v_max_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0xff] + +v_max_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0xff] + +v_max_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x50,0x01,0xff] + +v_max_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x5f,0x01,0x01] + +v_max_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x60,0x09,0x13] + +v_max_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xfe,0x72,0x7f,0x6f,0xf5,0x30] + +v_max_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0xff] + +v_max_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xff] + +v_max_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0xff] + +v_max_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0xff] + +v_max_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0xff] + +v_max_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0xff] + +v_max_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0xff] + +v_max_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0xff] + +v_max_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0xff] + +v_max_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0xff] + +v_max_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x50,0x01,0xff] + +v_max_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x5f,0x01,0x01] + +v_max_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x60,0x09,0x13] + +v_max_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x21,0xff,0x6f,0xf5,0x30] + +v_max_i32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff] + +v_max_i32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff] + +v_max_i32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff] + +v_max_i32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff] + +v_max_i32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff] + +v_max_i32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff] + +v_max_i32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff] + +v_max_i32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff] + +v_max_i32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff] + +v_max_i32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff] + +v_max_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff] + +v_max_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01] + +v_max_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x09,0x13] + +v_max_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x05,0x30] + +v_max_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff] + +v_max_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff] + +v_max_u32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff] + +v_max_u32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff] + +v_max_u32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff] + +v_max_u32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff] + +v_max_u32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff] + +v_max_u32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff] + +v_max_u32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff] + +v_max_u32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff] + +v_max_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff] + +v_max_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01] + +v_max_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x09,0x13] + +v_max_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x05,0x30] + +v_min_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0xff] + +v_min_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xff] + +v_min_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0xff] + +v_min_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0xff] + +v_min_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0xff] + +v_min_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0xff] + +v_min_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0xff] + +v_min_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0xff] + +v_min_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0xff] + +v_min_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0xff] + +v_min_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x50,0x01,0xff] + +v_min_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x5f,0x01,0x01] + +v_min_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x60,0x09,0x13] + +v_min_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xfe,0x74,0x7f,0x6f,0xf5,0x30] + +v_min_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0xff] + +v_min_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xff] + +v_min_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0xff] + +v_min_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0xff] + +v_min_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0xff] + +v_min_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0xff] + +v_min_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0xff] + +v_min_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0xff] + +v_min_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0xff] + +v_min_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0xff] + +v_min_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x50,0x01,0xff] + +v_min_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x5f,0x01,0x01] + +v_min_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x60,0x09,0x13] + +v_min_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x1f,0xff,0x6f,0xf5,0x30] + +v_min_i32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff] + +v_min_i32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff] + +v_min_i32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff] + +v_min_i32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff] + +v_min_i32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff] + +v_min_i32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff] + +v_min_i32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff] + +v_min_i32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff] + +v_min_i32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff] + +v_min_i32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff] + +v_min_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff] + +v_min_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01] + +v_min_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x09,0x13] + +v_min_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x05,0x30] + +v_min_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff] + +v_min_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff] + +v_min_u32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff] + +v_min_u32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff] + +v_min_u32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff] + +v_min_u32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff] + +v_min_u32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff] + +v_min_u32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff] + +v_min_u32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff] + +v_min_u32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff] + +v_min_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff] + +v_min_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01] + +v_min_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x09,0x13] + +v_min_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x05,0x30] + +v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01] + +v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x09,0x13] + +v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30] + +v_mul_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] + +v_mul_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] + +v_mul_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] + +v_mul_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13] + +v_mul_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30] + +v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff] + +v_mul_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff] + +v_mul_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01] + +v_mul_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x09,0x13] + +v_mul_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xf5,0x30] + +v_mul_hi_i32_i24 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01] + +v_mul_hi_i32_i24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x09,0x13] + +v_mul_hi_i32_i24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x05,0x30] + +v_mul_hi_u32_u24 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01] + +v_mul_hi_u32_u24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x09,0x13] + +v_mul_hi_u32_u24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x05,0x30] + +v_mul_i32_i24 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff] + +v_mul_i32_i24 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff] + +v_mul_i32_i24 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01] + +v_mul_i32_i24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x09,0x13] + +v_mul_i32_i24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x05,0x30] + +v_mul_legacy_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff] + +v_mul_legacy_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff] + +v_mul_legacy_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01] + +v_mul_legacy_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x09,0x13] + +v_mul_legacy_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30] + +v_mul_u32_u24 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff] + +v_mul_u32_u24 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff] + +v_mul_u32_u24 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01] + +v_mul_u32_u24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x09,0x13] + +v_mul_u32_u24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x05,0x30] + +v_or_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff] + +v_or_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff] + +v_or_b32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff] + +v_or_b32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff] + +v_or_b32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff] + +v_or_b32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff] + +v_or_b32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff] + +v_or_b32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff] + +v_or_b32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff] + +v_or_b32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff] + +v_or_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff] + +v_or_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01] + +v_or_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x09,0x13] + +v_or_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x05,0x30] + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff] + +v_sub_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff] + +v_sub_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01] + +v_sub_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x09,0x13] + +v_sub_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xf5,0x30] + +v_sub_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff] + +v_sub_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff] + +v_sub_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01] + +v_sub_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x09,0x13] + +v_sub_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xf5,0x30] + +v_sub_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff] + +v_sub_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff] + +v_sub_nc_u32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01] + +v_sub_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x09,0x13] + +v_sub_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x05,0x30] + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff] + +v_subrev_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff] + +v_subrev_f16 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01] + +v_subrev_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13] + +v_subrev_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30] + +v_subrev_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff] + +v_subrev_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff] + +v_subrev_f32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01] + +v_subrev_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x09,0x13] + +v_subrev_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xf5,0x30] + +v_subrev_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff] + +v_subrev_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01] + +v_subrev_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x09,0x13] + +v_subrev_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x05,0x30] + +v_xnor_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff] + +v_xnor_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff] + +v_xnor_b32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01] + +v_xnor_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x09,0x13] + +v_xnor_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x05,0x30] + +v_xor_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff] + +v_xor_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff] + +v_xor_b32 v5, v1, v2 row_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_half_mirror +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_shl:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_shl:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_shr:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_shr:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_ror:1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_ror:15 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01] + +v_xor_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX11: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x09,0x13] + +v_xor_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX11: encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x05,0x30] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s index 62c0deaecd96a541eccada0087e1015d7a42cffb..3eff00bb96e475be9add8e6a8abec714d6d43fde 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s @@ -1,7 +1,7 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] // W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8-fake16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8-fake16.s new file mode 100644 index 0000000000000000000000000000000000000000..a4fea037a4de7ddb5706b654d0a252b2e7de7fc2 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8-fake16.s @@ -0,0 +1,451 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s + +v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// W32: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: encoding: [0xe9,0xfe,0xff,0x41,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] +// W64: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: encoding: [0xe9,0xfe,0xff,0x41,0xff,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] + +v_add_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] + +v_add_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00] + +v_add_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05] + +v_add_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x06,0x01,0x77,0x39,0x05] + +v_add_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x07,0xff,0x00,0x00,0x00] + +v_add_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05] + +v_add_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05] + +v_add_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00] + +v_and_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05] + +v_and_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x36,0x01,0x77,0x39,0x05] + +v_and_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x37,0xff,0x00,0x00,0x00] + +v_ashrrev_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05] + +v_ashrrev_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x34,0x01,0x77,0x39,0x05] + +v_ashrrev_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x35,0xff,0x00,0x00,0x00] + +v_cndmask_b32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// W32: encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: encoding: [0xea,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: encoding: [0xe9,0xfe,0xff,0x03,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] +// W64: encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: encoding: [0xea,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: encoding: [0xe9,0xfe,0xff,0x03,0xff,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] + +v_cvt_pk_rtz_f16_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] + +v_cvt_pkrtz_f16_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00] + +v_dot2acc_f32_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x04,0x01,0x77,0x39,0x05] + +v_dot2acc_f32_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x04,0x01,0x77,0x39,0x05] + +v_dot2acc_f32_f16 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x05,0xff,0x00,0x00,0x00] + +v_dot2c_f32_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x04,0x01,0x77,0x39,0x05] + +v_dot2c_f32_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x04,0x01,0x77,0x39,0x05] + +v_dot2c_f32_f16 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x05,0xff,0x00,0x00,0x00] + +v_fmac_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05] + +v_fmac_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05] + +v_fmac_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00] + +v_fmac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05] + +v_fmac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x56,0x01,0x77,0x39,0x05] + +v_fmac_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x57,0xff,0x00,0x00,0x00] + +v_ldexp_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] + +v_ldexp_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] + +v_ldexp_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00] + +v_lshlrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05] + +v_lshlrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x30,0x01,0x77,0x39,0x05] + +v_lshlrev_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x31,0xff,0x00,0x00,0x00] + +v_lshrrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05] + +v_lshrrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x32,0x01,0x77,0x39,0x05] + +v_lshrrev_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x33,0xff,0x00,0x00,0x00] + +v_max_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x72,0x01,0x77,0x39,0x05] + +v_max_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x72,0x01,0x77,0x39,0x05] + +v_max_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xfe,0x72,0x7f,0x00,0x00,0x00] + +v_max_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x20,0x01,0x77,0x39,0x05] + +v_max_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x20,0x01,0x77,0x39,0x05] + +v_max_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x21,0xff,0x00,0x00,0x00] + +v_max_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05] + +v_max_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x24,0x01,0x77,0x39,0x05] + +v_max_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x25,0xff,0x00,0x00,0x00] + +v_max_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05] + +v_max_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x28,0x01,0x77,0x39,0x05] + +v_max_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x29,0xff,0x00,0x00,0x00] + +v_min_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x74,0x01,0x77,0x39,0x05] + +v_min_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x74,0x01,0x77,0x39,0x05] + +v_min_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xfe,0x74,0x7f,0x00,0x00,0x00] + +v_min_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x1e,0x01,0x77,0x39,0x05] + +v_min_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x1e,0x01,0x77,0x39,0x05] + +v_min_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x1f,0xff,0x00,0x00,0x00] + +v_min_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05] + +v_min_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x22,0x01,0x77,0x39,0x05] + +v_min_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x23,0xff,0x00,0x00,0x00] + +v_min_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05] + +v_min_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x26,0x01,0x77,0x39,0x05] + +v_min_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x27,0xff,0x00,0x00,0x00] + +v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] + +v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] + +v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] + +v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] + +v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] + +v_mul_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] + +v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] + +v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] + +v_mul_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x11,0xff,0x00,0x00,0x00] + +v_mul_hi_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05] + +v_mul_hi_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x14,0x01,0x77,0x39,0x05] + +v_mul_hi_i32_i24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x15,0xff,0x00,0x00,0x00] + +v_mul_hi_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05] + +v_mul_hi_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x18,0x01,0x77,0x39,0x05] + +v_mul_hi_u32_u24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x19,0xff,0x00,0x00,0x00] + +v_mul_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05] + +v_mul_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x12,0x01,0x77,0x39,0x05] + +v_mul_i32_i24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x13,0xff,0x00,0x00,0x00] + +v_mul_legacy_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] + +v_mul_legacy_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] + +v_mul_legacy_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] + +v_mul_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05] + +v_mul_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x16,0x01,0x77,0x39,0x05] + +v_mul_u32_u24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x17,0xff,0x00,0x00,0x00] + +v_or_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05] + +v_or_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x38,0x01,0x77,0x39,0x05] + +v_or_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x39,0xff,0x00,0x00,0x00] + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// W32: encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: encoding: [0xea,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: encoding: [0xe9,0xfe,0xff,0x43,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] +// W64: encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: encoding: [0xea,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: encoding: [0xe9,0xfe,0xff,0x43,0xff,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] + +v_sub_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] + +v_sub_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00] + +v_sub_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05] + +v_sub_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x08,0x01,0x77,0x39,0x05] + +v_sub_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x09,0xff,0x00,0x00,0x00] + +v_sub_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05] + +v_sub_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05] + +v_sub_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00] + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// W32: encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: encoding: [0xea,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] +// W64: encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: encoding: [0xea,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] + +v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] + +v_subrev_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00] + +v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05] + +v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05] + +v_subrev_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00] + +v_subrev_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05] + +v_subrev_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05] + +v_subrev_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00] + +v_xnor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05] + +v_xnor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05] + +v_xnor_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00] + +v_xor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: encoding: [0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05] + +v_xor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX11: encoding: [0xea,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05] + +v_xor_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX11: encoding: [0xe9,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s index d235fcdeb526aa4ec04b477b8cd6a3e45a5b5c27..0f19cf0028525f1e3ca5618f1a152a447a2d195f 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp8.s @@ -1,7 +1,7 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] // W32: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err-fake16.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err-fake16.s new file mode 100644 index 0000000000000000000000000000000000000000..2d52828d1e2834e950867bdf466fa553b01f9cce --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err-fake16.s @@ -0,0 +1,13 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s + +v_fmaak_f32 v0, 0xff32, v0, 0 +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed + +v_fmaak_f16 v0, 0xff32, v0, 0 +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed + +v_fmamk_f32 v0, 0xff32, 1, v0 +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed + +v_fmamk_f16 v0, 0xff32, 1, v0 +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s index 164a49dcdd47b61ced1e5c4dce98191604ec563c..dedbcb55d7976dae21493bdec5872da4bc92b8f3 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_err.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s v_fmaak_f32 v0, 0xff32, v0, 0 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s index 76b1c38fad43d95a6a3f8d261f0b2d8c8671e5cd..dd619f3077f7041f7f08968f7f54feb3e6e2529f 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_err.s @@ -1,237 +1,238 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=error: %s -v_add_f16_e32 v255, v1, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmaak_f16_e32 v255, v1, v2, 0xfe0b -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_e32 v255, v1, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmamk_f16_e32 v255, v1, 0xfe0b, v3 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_e32 v255.l, v1.l, v2.l -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_add_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_f16_e32 v255, v1, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_f16_e32 v255, v1, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_e32 v255, v1, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_e32 v255, v1, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_e32 v5, v1, v255 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_e32 v255, v1, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_e32 v5, v255, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_e32 v255, v1, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmaak_f16_e32 v255, v1, v2, 0xfe0b +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_e32 v5, v255, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmaak_f16_e32 v5, v1, v255, 0xfe0b +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode v_fmaak_f16_e32 v5, v255, v2, 0xfe0b -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode - -v_fmac_f16_e32 v5, v255, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmamk_f16_e32 v5, v255, 0xfe0b, v3 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_e32 v5.l, v255.l, v2.l -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_fmac_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_f16_e32 v5, v255, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_f16_e32 v5, v255, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_e32 v5, v255, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_e32 v5, v255, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_e32 v5, v255, v2 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_e32 v255, v1, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_e32 v5, v1, v255 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_e32 v5, v1, v255 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmaak_f16_e32 v5, v1, v255, 0xfe0b -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_e32 v5, v255, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_e32 v5, v1, v255 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmamk_f16_e32 v255, v1, 0xfe0b, v3 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode v_fmamk_f16_e32 v5, v1, 0xfe0b, v255 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_e32 v5.l, v1.l, v255.l -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_fmamk_f16_e32 v5, v255, 0xfe0b, v3 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_f16_e32 v5, v1, v255 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:17: error: invalid operand for instruction -v_min_f16_e32 v5, v1, v255 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:17: error: invalid operand for instruction -v_mul_f16_e32 v5, v1, v255 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_sub_f16_e32 v5, v1, v255 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_subrev_f16_e32 v5, v1, v255 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction -v_add_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction -v_fmac_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_e32 v255.l, v1.l, v2.l +// GFX11: :[[@LINE-1]]:17: error: invalid operand for instruction -v_ldexp_f16_dpp v255.l, v1.l, v2.l quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_ldexp_f16_e32 v5.l, v1.l, v255.l +// GFX11: :[[@LINE-1]]:29: error: invalid operand for instruction -v_max_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_e32 v5.l, v255.l, v2.l +// GFX11: :[[@LINE-1]]:23: error: invalid operand for instruction -v_min_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_dpp v5.l, v255.l, v2.l quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_max_f16_e32 v255, v1, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_f16_e32 v5, v1, v255 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_f16_e32 v5, v255, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_dpp v5.l, v1.l, v255.l quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_min_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_f16_e32 v255, v1, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_f16_e32 v5, v1, v255 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_f16_e32 v5, v255, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_dpp v255.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_e32 v255, v1, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_e32 v5, v1, v255 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode + +v_mul_f16_e32 v5, v255, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode v_sub_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_dpp v5.l, v255.l, v2.l dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_sub_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_e32 v255, v1, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_e32 v5, v1, v255 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_e32 v5, v255, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_dpp v5.l, v1.l, v255.l dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -v_max_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_e32 v255, v1, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_e32 v5, v1, v255 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode +v_subrev_f16_e32 v5, v255, v2 +// GFX11: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s index a5b5f32e976226831fadd5693b653377ce5ce091..a6dcce40fd0e03c80c7e037a1742273413131cbc 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop2_t16_promote.s @@ -1,201 +1,202 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX11 --implicit-check-not=_e32 %s v_add_f16 v255, v1, v2 -// GFX11: v_add_f16_e64 +// GFX11: v_add_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x32,0xd5,0x01,0x05,0x02,0x00] -v_fmac_f16 v255, v1, v2 -// GFX11: v_fmac_f16_e64 - -v_ldexp_f16 v255, v1, v2 -// GFX11: v_ldexp_f16_e64 - -v_max_f16 v255, v1, v2 -// GFX11: v_max_f16_e64 +v_add_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_add_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x32,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_min_f16 v255, v1, v2 -// GFX11: v_min_f16_e64 +v_add_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: v_add_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v255, v1, v2 -// GFX11: v_mul_f16_e64 +v_add_f16 v5, v1, v255 +// GFX11: v_add_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x32,0xd5,0x01,0xff,0x03,0x00] -v_sub_f16 v255, v1, v2 -// GFX11: v_sub_f16_e64 +v_add_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_add_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_subrev_f16 v255, v1, v2 -// GFX11: v_subrev_f16_e64 +v_add_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: v_add_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] v_add_f16 v5, v255, v2 -// GFX11: v_add_f16_e64 - -v_fmac_f16 v5, v255, v2 -// GFX11: v_fmac_f16_e64 +// GFX11: v_add_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x32,0xd5,0xff,0x05,0x02,0x00] -v_ldexp_f16 v5, v255, v2 -// GFX11: v_ldexp_f16_e64 +v_add_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_add_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_max_f16 v5, v255, v2 -// GFX11: v_max_f16_e64 +v_add_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: v_add_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_min_f16 v5, v255, v2 -// GFX11: v_min_f16_e64 +v_fmac_f16 v255, v1, v2 +// GFX11: v_fmac_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00] -v_mul_f16 v5, v255, v2 -// GFX11: v_mul_f16_e64 +v_fmac_f16 v5, v1, v255 +// GFX11: v_fmac_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x36,0xd5,0x01,0xff,0x03,0x00] -v_sub_f16 v5, v255, v2 -// GFX11: v_sub_f16_e64 +v_fmac_f16 v5, v255, v2 +// GFX11: v_fmac_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x36,0xd5,0xff,0x05,0x02,0x00] -v_subrev_f16 v5, v255, v2 -// GFX11: v_subrev_f16_e64 +v_ldexp_f16 v255, v1, v2 +// GFX11: v_ldexp_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00] -v_add_f16 v5, v1, v255 -// GFX11: v_add_f16_e64 +v_ldexp_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_ldexp_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_fmac_f16 v5, v1, v255 -// GFX11: v_fmac_f16_e64 +v_ldexp_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: v_ldexp_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] v_ldexp_f16 v5, v1, v255 -// GFX11: v_ldexp_f16_e64 +// GFX11: v_ldexp_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x3b,0xd5,0x01,0xff,0x03,0x00] -v_max_f16 v5, v1, v255 -// GFX11: v_max_f16_e64 +v_ldexp_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_ldexp_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3b,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_min_f16 v5, v1, v255 -// GFX11: v_min_f16_e64 +v_ldexp_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: v_ldexp_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v1, v255 -// GFX11: v_mul_f16_e64 +v_ldexp_f16 v5, v255, v2 +// GFX11: v_ldexp_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x3b,0xd5,0xff,0x05,0x02,0x00] -v_sub_f16 v5, v1, v255 -// GFX11: v_sub_f16_e64 +v_ldexp_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_ldexp_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_subrev_f16 v5, v1, v255 -// GFX11: v_subrev_f16_e64 +v_ldexp_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: v_ldexp_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_add_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_add_f16_e64 +v_max_f16 v255, v1, v2 +// GFX11: v_max_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x39,0xd5,0x01,0x05,0x02,0x00] -v_ldexp_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_ldexp_f16_e64 +v_max_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_max_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x39,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] v_max_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_max_f16_e64 - -v_min_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_min_f16_e64 +// GFX11: v_max_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x39,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_mul_f16_e64 +v_max_f16 v5, v1, v255 +// GFX11: v_max_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x39,0xd5,0x01,0xff,0x03,0x00] -v_sub_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_sub_f16_e64 +v_max_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_max_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_subrev_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX11: v_subrev_f16_e64 +v_max_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: v_max_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_add_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: v_add_f16_e64 +v_max_f16 v5, v255, v2 +// GFX11: v_max_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x39,0xd5,0xff,0x05,0x02,0x00] -v_ldexp_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: v_ldexp_f16_e64 +v_max_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_max_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x39,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] v_max_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: v_max_f16_e64 +// GFX11: v_max_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x39,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_min_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: v_min_f16_e64 +v_min_f16 v255, v1, v2 +// GFX11: v_min_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x3a,0xd5,0x01,0x05,0x02,0x00] -v_mul_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: v_mul_f16_e64 +v_min_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_min_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x3a,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_sub_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: v_sub_f16_e64 +v_min_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: v_min_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x3a,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_subrev_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX11: v_subrev_f16_e64 +v_min_f16 v5, v1, v255 +// GFX11: v_min_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x3a,0xd5,0x01,0xff,0x03,0x00] -v_add_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_add_f16_e64 +v_min_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_min_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3a,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_ldexp_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_ldexp_f16_e64 +v_min_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: v_min_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_max_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_max_f16_e64 +v_min_f16 v5, v255, v2 +// GFX11: v_min_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x3a,0xd5,0xff,0x05,0x02,0x00] -v_min_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_min_f16_e64 +v_min_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_min_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3a,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_mul_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_mul_f16_e64 +v_min_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: v_min_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3a,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_sub_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_sub_f16_e64 +v_mul_f16 v255, v1, v2 +// GFX11: v_mul_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] -v_subrev_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX11: v_subrev_f16_e64 +v_mul_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_add_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_add_f16_e64 +v_mul_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_ldexp_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_ldexp_f16_e64 +v_mul_f16 v5, v1, v255 +// GFX11: v_mul_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00] -v_max_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_max_f16_e64 +v_mul_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_min_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_min_f16_e64 +v_mul_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_e64 +v_mul_f16 v5, v255, v2 +// GFX11: v_mul_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x35,0xd5,0xff,0x05,0x02,0x00] -v_sub_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_sub_f16_e64 +v_mul_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_subrev_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_subrev_f16_e64 +v_mul_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: v_mul_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_add_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_add_f16_e64 +v_sub_f16 v255, v1, v2 +// GFX11: v_sub_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x33,0xd5,0x01,0x05,0x02,0x00] -v_ldexp_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_ldexp_f16_e64 +v_sub_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_sub_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x33,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_max_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_max_f16_e64 +v_sub_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: v_sub_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_min_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_min_f16_e64 +v_sub_f16 v5, v1, v255 +// GFX11: v_sub_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x33,0xd5,0x01,0xff,0x03,0x00] -v_mul_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_e64 +v_sub_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_sub_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x33,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_sub_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_sub_f16_e64 +v_sub_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: v_sub_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_subrev_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_subrev_f16_e64 +v_sub_f16 v5, v255, v2 +// GFX11: v_sub_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x33,0xd5,0xff,0x05,0x02,0x00] -v_add_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_add_f16_e64 +v_sub_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_sub_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x33,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_ldexp_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_ldexp_f16_e64 +v_sub_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: v_sub_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_max_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_max_f16_e64 +v_subrev_f16 v255, v1, v2 +// GFX11: v_subrev_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x34,0xd5,0x01,0x05,0x02,0x00] -v_min_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_min_f16_e64 +v_subrev_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_subrev_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_mul_f16_e64 +v_subrev_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX11: v_subrev_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_sub_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_sub_f16_e64 +v_subrev_f16 v5, v1, v255 +// GFX11: v_subrev_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x03,0x00] v_subrev_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX11: v_subrev_f16_e64 +// GFX11: v_subrev_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] + +v_subrev_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX11: v_subrev_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] + +v_subrev_f16 v5, v255, v2 +// GFX11: v_subrev_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x34,0xd5,0xff,0x05,0x02,0x00] + +v_subrev_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX11: v_subrev_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] + +v_subrev_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX11: v_subrev_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s index 196d75db4260528777393a2920a3c597379fc8d2..8bf9b92e8d1d8d7276c243a69eaa91f57ef190df 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vimage.s @@ -158,6 +158,12 @@ image_load v[0:2], [v4, v5], s[8:15] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY th:TH_LO image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D // GFX12: encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00] +image_load v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D +// GFX12: encoding: [0x02,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] + +image_load v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY +// GFX12: encoding: [0x07,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] + image_load_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D // GFX12: encoding: [0x00,0x40,0xc0,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00] @@ -408,6 +414,12 @@ image_store v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_STORE_BYPASS scope image_store v[1:4], [v2, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D // GFX12: encoding: [0x01,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] +image_store v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D +// GFX12: encoding: [0x02,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] + +image_store v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY +// GFX12: encoding: [0x07,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] + image_store_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D // GFX12: encoding: [0x00,0xc0,0xc1,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00] @@ -568,6 +580,12 @@ image_atomic_swap v[254:255], [v4, v5], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D_M image_atomic_swap v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D // GFX12: encoding: [0x01,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] +image_atomic_swap v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D +// GFX12: encoding: [0x02,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] + +image_atomic_swap v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY +// GFX12: encoding: [0x07,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] + image_atomic_cmpswap v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D // GFX12: encoding: [0x00,0xc0,0xc2,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] @@ -625,6 +643,12 @@ image_atomic_add_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_N image_atomic_add_uint v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D // GFX12: encoding: [0x01,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] +image_atomic_add_uint v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D +// GFX12: encoding: [0x02,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] + +image_atomic_add_uint v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY +// GFX12: encoding: [0x07,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] + image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D // GFX12: encoding: [0x00,0x40,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2-fake16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2-fake16.s new file mode 100644 index 0000000000000000000000000000000000000000..4c37502e1b247fdf5bfe1ea91adb4580c71c170b --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2-fake16.s @@ -0,0 +1,2560 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s + +v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo +// W32: encoding: [0x01,0x05,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo +// W32: encoding: [0xff,0x05,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo +// W32: encoding: [0x01,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo +// W32: encoding: [0x69,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo +// W32: encoding: [0x6a,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo +// W32: encoding: [0x6b,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo +// W32: encoding: [0x7b,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo +// W32: encoding: [0x7d,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo +// W32: encoding: [0x7e,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo +// W32: encoding: [0x7f,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo +// W32: encoding: [0x7c,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo +// W32: encoding: [0xc1,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo +// W32: encoding: [0xf0,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo +// W32: encoding: [0xfd,0x04,0x0a,0x40] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo +// W32: encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc +// W64: encoding: [0x01,0x05,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v255, v2, vcc +// W64: encoding: [0xff,0x05,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, s1, v2, vcc +// W64: encoding: [0x01,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, s105, v2, vcc +// W64: encoding: [0x69,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, vcc_lo, v2, vcc +// W64: encoding: [0x6a,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, vcc_hi, v2, vcc +// W64: encoding: [0x6b,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, ttmp15, v2, vcc +// W64: encoding: [0x7b,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, m0, v2, vcc +// W64: encoding: [0x7d,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, exec_lo, v2, vcc +// W64: encoding: [0x7e,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, exec_hi, v2, vcc +// W64: encoding: [0x7f,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, null, v2, vcc +// W64: encoding: [0x7c,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, -1, v2, vcc +// W64: encoding: [0xc1,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, 0.5, v2, vcc +// W64: encoding: [0xf0,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, src_scc, v2, vcc +// W64: encoding: [0xfd,0x04,0x0a,0x40] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc +// W64: encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x64] + +v_add_f16 v5, v127, v2 +// GFX12: encoding: [0x7f,0x05,0x0a,0x64] + +v_add_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x64] + +v_add_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x64] + +v_add_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x64] + +v_add_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x64] + +v_add_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x64] + +v_add_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x64] + +v_add_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x64] + +v_add_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x64] + +v_add_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x64] + +v_add_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x64] + +v_add_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x64] + +v_add_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x64] + +v_add_f16 v127, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00] + +v_add_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x06] + +v_add_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x06] + +v_add_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x06] + +v_add_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x06] + +v_add_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x06] + +v_add_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x06] + +v_add_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x06] + +v_add_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x06] + +v_add_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x06] + +v_add_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x06] + +v_add_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x06] + +v_add_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x06] + +v_add_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x06] + +v_add_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x06] + +v_add_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf] + +v_add_f64 v[5:6], v[1:2], v[3:4] +// GFX12: encoding: [0x01,0x07,0x0a,0x04] + +v_add_f64 v[5:6], v[254:255], v[2:3] +// GFX12: encoding: [0xfe,0x05,0x0a,0x04] + +v_add_f64 v[5:6], s[0:1], v[2:3] +// GFX12: encoding: [0x00,0x04,0x0a,0x04] + +v_add_f64 v[5:6], s[104:105], v[2:3] +// GFX12: encoding: [0x68,0x04,0x0a,0x04] + +v_add_f64 v[5:6], vcc, v[2:3] +// GFX12: encoding: [0x6a,0x04,0x0a,0x04] + +v_add_f64 v[5:6], ttmp[14:15], v[2:3] +// GFX12: encoding: [0x7a,0x04,0x0a,0x04] + +v_add_f64 v[5:6], exec, v[2:3] +// GFX12: encoding: [0x7e,0x04,0x0a,0x04] + +v_add_f64 v[5:6], null, v[2:3] +// GFX12: encoding: [0x7c,0x04,0x0a,0x04] + +v_add_f64 v[5:6], -1, v[2:3] +// GFX12: encoding: [0xc1,0x04,0x0a,0x04] + +v_add_f64 v[5:6], 0.5, v[2:3] +// GFX12: encoding: [0xf0,0x04,0x0a,0x04] + +v_add_f64 v[5:6], src_scc, v[2:3] +// GFX12: encoding: [0xfd,0x04,0x0a,0x04] + +v_add_f64 v[254:255], 0xaf123456, v[254:255] +// GFX12: encoding: [0xff,0xfc,0xfd,0x05,0x56,0x34,0x12,0xaf] + +v_add_nc_u32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x4a] + +v_add_nc_u32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x4a] + +v_add_nc_u32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x4a] + +v_add_nc_u32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x4a] + +v_add_nc_u32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf] + +v_and_b32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x36] + +v_and_b32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x36] + +v_and_b32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x36] + +v_and_b32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x36] + +v_and_b32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x36] + +v_and_b32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x36] + +v_and_b32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x36] + +v_and_b32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x36] + +v_and_b32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x36] + +v_and_b32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x36] + +v_and_b32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x36] + +v_and_b32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x36] + +v_and_b32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x36] + +v_and_b32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x36] + +v_and_b32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf] + +v_ashrrev_i32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x34] + +v_ashrrev_i32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x34] + +v_ashrrev_i32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x34] + +v_ashrrev_i32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x34] + +v_ashrrev_i32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf] + +v_cndmask_b32 v5, v1, v2, vcc_lo +// W32: encoding: [0x01,0x05,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v255, v2, vcc_lo +// W32: encoding: [0xff,0x05,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, s1, v2, vcc_lo +// W32: encoding: [0x01,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, s105, v2, vcc_lo +// W32: encoding: [0x69,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, vcc_lo, v2, vcc_lo +// W32: encoding: [0x6a,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, vcc_hi, v2, vcc_lo +// W32: encoding: [0x6b,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, ttmp15, v2, vcc_lo +// W32: encoding: [0x7b,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, m0, v2, vcc_lo +// W32: encoding: [0x7d,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, exec_lo, v2, vcc_lo +// W32: encoding: [0x7e,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, exec_hi, v2, vcc_lo +// W32: encoding: [0x7f,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, null, v2, vcc_lo +// W32: encoding: [0x7c,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, -1, v2, vcc_lo +// W32: encoding: [0xc1,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, 0.5, v2, vcc_lo +// W32: encoding: [0xf0,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, src_scc, v2, vcc_lo +// W32: encoding: [0xfd,0x04,0x0a,0x02] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, 0xaf123456, v255, vcc_lo +// W32: encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc +// W64: encoding: [0x01,0x05,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v255, v2, vcc +// W64: encoding: [0xff,0x05,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, s1, v2, vcc +// W64: encoding: [0x01,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, s105, v2, vcc +// W64: encoding: [0x69,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, vcc_lo, v2, vcc +// W64: encoding: [0x6a,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, vcc_hi, v2, vcc +// W64: encoding: [0x6b,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, ttmp15, v2, vcc +// W64: encoding: [0x7b,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, m0, v2, vcc +// W64: encoding: [0x7d,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, exec_lo, v2, vcc +// W64: encoding: [0x7e,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, exec_hi, v2, vcc +// W64: encoding: [0x7f,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, null, v2, vcc +// W64: encoding: [0x7c,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, -1, v2, vcc +// W64: encoding: [0xc1,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, 0.5, v2, vcc +// W64: encoding: [0xf0,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, src_scc, v2, vcc +// W64: encoding: [0xfd,0x04,0x0a,0x02] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, 0xaf123456, v255, vcc +// W64: encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x5e] + +v_cvt_pk_rtz_f16_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x5e] + +v_cvt_pkrtz_f16_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf] + +v_fmaak_f16 v5, v1, v2, 0xfe0b +// GFX12: encoding: [0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, v127, v2, 0xfe0b +// GFX12: encoding: [0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, s1, v2, 0xfe0b +// GFX12: encoding: [0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, s105, v2, 0xfe0b +// GFX12: encoding: [0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, vcc_lo, v2, 0xfe0b +// GFX12: encoding: [0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, vcc_hi, v2, 0xfe0b +// GFX12: encoding: [0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, ttmp15, v2, 0xfe0b +// GFX12: encoding: [0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, m0, v2, 0xfe0b +// GFX12: encoding: [0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, exec_lo, v2, 0xfe0b +// GFX12: encoding: [0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, exec_hi, v2, 0xfe0b +// GFX12: encoding: [0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, null, v2, 0xfe0b +// GFX12: encoding: [0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, -1, v2, 0xfe0b +// GFX12: encoding: [0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, 0.5, v2, 0xfe0b +// GFX12: encoding: [0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v5, src_scc, v2, 0xfe0b +// GFX12: encoding: [0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f16 v127, 0xfe0b, v127, 0xfe0b +// GFX12: encoding: [0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00] + +v_fmaak_f32 v5, v1, v2, 0xaf123456 +// GFX12: encoding: [0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, v255, v2, 0xaf123456 +// GFX12: encoding: [0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, s1, v2, 0xaf123456 +// GFX12: encoding: [0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, s105, v2, 0xaf123456 +// GFX12: encoding: [0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, vcc_lo, v2, 0xaf123456 +// GFX12: encoding: [0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, vcc_hi, v2, 0xaf123456 +// GFX12: encoding: [0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, ttmp15, v2, 0xaf123456 +// GFX12: encoding: [0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, m0, v2, 0xaf123456 +// GFX12: encoding: [0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, exec_lo, v2, 0xaf123456 +// GFX12: encoding: [0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, exec_hi, v2, 0xaf123456 +// GFX12: encoding: [0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, null, v2, 0xaf123456 +// GFX12: encoding: [0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, -1, v2, 0xaf123456 +// GFX12: encoding: [0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, 0.5, v2, 0xaf123456 +// GFX12: encoding: [0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v5, src_scc, v2, 0xaf123456 +// GFX12: encoding: [0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] + +v_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 +// GFX12: encoding: [0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf] + +v_fmac_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x6c] + +v_fmac_f16 v5, v127, v2 +// GFX12: encoding: [0x7f,0x05,0x0a,0x6c] + +v_fmac_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x6c] + +v_fmac_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x6c] + +v_fmac_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x6c] + +v_fmac_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x6c] + +v_fmac_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x6c] + +v_fmac_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x6c] + +v_fmac_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x6c] + +v_fmac_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x6c] + +v_fmac_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x6c] + +v_fmac_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x6c] + +v_fmac_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x6c] + +v_fmac_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x6c] + +v_fmac_f16 v127, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00] + +v_fmac_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x56] + +v_fmac_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x56] + +v_fmac_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x56] + +v_fmac_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x56] + +v_fmac_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x56] + +v_fmac_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x56] + +v_fmac_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x56] + +v_fmac_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x56] + +v_fmac_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x56] + +v_fmac_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x56] + +v_fmac_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x56] + +v_fmac_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x56] + +v_fmac_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x56] + +v_fmac_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x56] + +v_fmac_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf] + +v_fmamk_f16 v5, v1, 0xfe0b, v3 +// GFX12: encoding: [0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, v127, 0xfe0b, v3 +// GFX12: encoding: [0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, s1, 0xfe0b, v3 +// GFX12: encoding: [0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, s105, 0xfe0b, v3 +// GFX12: encoding: [0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, vcc_lo, 0xfe0b, v3 +// GFX12: encoding: [0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, vcc_hi, 0xfe0b, v3 +// GFX12: encoding: [0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, ttmp15, 0xfe0b, v3 +// GFX12: encoding: [0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, m0, 0xfe0b, v3 +// GFX12: encoding: [0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, exec_lo, 0xfe0b, v3 +// GFX12: encoding: [0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, exec_hi, 0xfe0b, v3 +// GFX12: encoding: [0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, null, 0xfe0b, v3 +// GFX12: encoding: [0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, -1, 0xfe0b, v3 +// GFX12: encoding: [0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, 0.5, 0xfe0b, v3 +// GFX12: encoding: [0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v5, src_scc, 0xfe0b, v3 +// GFX12: encoding: [0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f16 v127, 0xfe0b, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00] + +v_fmamk_f32 v5, v1, 0xaf123456, v3 +// GFX12: encoding: [0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, v255, 0xaf123456, v3 +// GFX12: encoding: [0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, s1, 0xaf123456, v3 +// GFX12: encoding: [0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, s105, 0xaf123456, v3 +// GFX12: encoding: [0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, vcc_lo, 0xaf123456, v3 +// GFX12: encoding: [0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, vcc_hi, 0xaf123456, v3 +// GFX12: encoding: [0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, ttmp15, 0xaf123456, v3 +// GFX12: encoding: [0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, m0, 0xaf123456, v3 +// GFX12: encoding: [0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, exec_lo, 0xaf123456, v3 +// GFX12: encoding: [0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, exec_hi, 0xaf123456, v3 +// GFX12: encoding: [0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, null, 0xaf123456, v3 +// GFX12: encoding: [0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, -1, 0xaf123456, v3 +// GFX12: encoding: [0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, 0.5, 0xaf123456, v3 +// GFX12: encoding: [0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v5, src_scc, 0xaf123456, v3 +// GFX12: encoding: [0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] + +v_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf] + +v_ldexp_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x76] + +v_ldexp_f16 v5, v127, v2 +// GFX12: encoding: [0x7f,0x05,0x0a,0x76] + +v_ldexp_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x76] + +v_ldexp_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x76] + +v_ldexp_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x76] + +v_ldexp_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x76] + +v_ldexp_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x76] + +v_ldexp_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x76] + +v_ldexp_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x76] + +v_ldexp_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x76] + +v_ldexp_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x76] + +v_ldexp_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x76] + +v_ldexp_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x76] + +v_ldexp_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x76] + +v_ldexp_f16 v127, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] + +v_lshlrev_b32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x30] + +v_lshlrev_b32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x30] + +v_lshlrev_b32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x30] + +v_lshlrev_b32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x30] + +v_lshlrev_b32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf] + +v_lshlrev_b64 v[5:6], v1, v[3:4] +// GFX12: encoding: [0x01,0x07,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], v255, v[2:3] +// GFX12: encoding: [0xff,0x05,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], s1, v[2:3] +// GFX12: encoding: [0x01,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], s105, v[2:3] +// GFX12: encoding: [0x69,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], vcc_lo, v[2:3] +// GFX12: encoding: [0x6a,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], vcc_hi, v[2:3] +// GFX12: encoding: [0x6b,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], ttmp15, v[2:3] +// GFX12: encoding: [0x7b,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], exec_lo, v[2:3] +// GFX12: encoding: [0x7e,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], exec_hi, v[2:3] +// GFX12: encoding: [0x7f,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], null, v[2:3] +// GFX12: encoding: [0x7c,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], -1, v[2:3] +// GFX12: encoding: [0xc1,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], 0.5, v[2:3] +// GFX12: encoding: [0xf0,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[5:6], src_scc, v[2:3] +// GFX12: encoding: [0xfd,0x04,0x0a,0x3e] + +v_lshlrev_b64 v[254:255], 0xaf123456, v[254:255] +// GFX12: encoding: [0xff,0xfc,0xfd,0x3f,0x56,0x34,0x12,0xaf] + +v_lshrrev_b32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x32] + +v_lshrrev_b32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x32] + +v_lshrrev_b32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x32] + +v_lshrrev_b32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x32] + +v_lshrrev_b32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf] + +v_max_num_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x62] + +v_max_num_f16 v5, v127, v2 +// GFX12: encoding: [0x7f,0x05,0x0a,0x62] + +v_max_num_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x62] + +v_max_num_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x62] + +v_max_num_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x62] + +v_max_num_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x62] + +v_max_num_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x62] + +v_max_num_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x62] + +v_max_num_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x62] + +v_max_num_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x62] + +v_max_num_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x62] + +v_max_num_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x62] + +v_max_num_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x62] + +v_max_num_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x62] + +v_max_num_f16 v127, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x62,0x0b,0xfe,0x00,0x00] + +v_max_num_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x2c] + +v_max_num_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x2c] + +v_max_num_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x2c] + +v_max_num_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x2c] + +v_max_num_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x2c] + +v_max_num_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x2c] + +v_max_num_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x2c] + +v_max_num_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x2c] + +v_max_num_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x2c] + +v_max_num_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x2c] + +v_max_num_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x2c] + +v_max_num_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x2c] + +v_max_num_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x2c] + +v_max_num_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x2c] + +v_max_num_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x2d,0x56,0x34,0x12,0xaf] + +v_max_num_f64 v[5:6], v[1:2], v[3:4] +// GFX12: encoding: [0x01,0x07,0x0a,0x1c] + +v_max_num_f64 v[5:6], v[254:255], v[2:3] +// GFX12: encoding: [0xfe,0x05,0x0a,0x1c] + +v_max_num_f64 v[5:6], s[0:1], v[2:3] +// GFX12: encoding: [0x00,0x04,0x0a,0x1c] + +v_max_num_f64 v[5:6], s[104:105], v[2:3] +// GFX12: encoding: [0x68,0x04,0x0a,0x1c] + +v_max_num_f64 v[5:6], vcc, v[2:3] +// GFX12: encoding: [0x6a,0x04,0x0a,0x1c] + +v_max_num_f64 v[5:6], ttmp[14:15], v[2:3] +// GFX12: encoding: [0x7a,0x04,0x0a,0x1c] + +v_max_num_f64 v[5:6], exec, v[2:3] +// GFX12: encoding: [0x7e,0x04,0x0a,0x1c] + +v_max_num_f64 v[5:6], null, v[2:3] +// GFX12: encoding: [0x7c,0x04,0x0a,0x1c] + +v_max_num_f64 v[5:6], -1, v[2:3] +// GFX12: encoding: [0xc1,0x04,0x0a,0x1c] + +v_max_num_f64 v[5:6], 0.5, v[2:3] +// GFX12: encoding: [0xf0,0x04,0x0a,0x1c] + +v_max_num_f64 v[5:6], src_scc, v[2:3] +// GFX12: encoding: [0xfd,0x04,0x0a,0x1c] + +v_max_num_f64 v[254:255], 0xaf123456, v[254:255] +// GFX12: encoding: [0xff,0xfc,0xfd,0x1d,0x56,0x34,0x12,0xaf] + +v_max_i32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x24] + +v_max_i32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x24] + +v_max_i32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x24] + +v_max_i32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x24] + +v_max_i32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x24] + +v_max_i32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x24] + +v_max_i32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x24] + +v_max_i32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x24] + +v_max_i32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x24] + +v_max_i32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x24] + +v_max_i32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x24] + +v_max_i32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x24] + +v_max_i32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x24] + +v_max_i32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x24] + +v_max_i32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf] + +v_max_u32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x28] + +v_max_u32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x28] + +v_max_u32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x28] + +v_max_u32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x28] + +v_max_u32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x28] + +v_max_u32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x28] + +v_max_u32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x28] + +v_max_u32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x28] + +v_max_u32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x28] + +v_max_u32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x28] + +v_max_u32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x28] + +v_max_u32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x28] + +v_max_u32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x28] + +v_max_u32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x28] + +v_max_u32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf] + +v_min_num_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x60] + +v_min_num_f16 v5, v127, v2 +// GFX12: encoding: [0x7f,0x05,0x0a,0x60] + +v_min_num_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x60] + +v_min_num_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x60] + +v_min_num_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x60] + +v_min_num_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x60] + +v_min_num_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x60] + +v_min_num_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x60] + +v_min_num_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x60] + +v_min_num_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x60] + +v_min_num_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x60] + +v_min_num_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x60] + +v_min_num_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x60] + +v_min_num_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x60] + +v_min_num_f16 v127, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x60,0x0b,0xfe,0x00,0x00] + +v_min_num_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x2a] + +v_min_num_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x2a] + +v_min_num_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x2a] + +v_min_num_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x2a] + +v_min_num_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x2a] + +v_min_num_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x2a] + +v_min_num_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x2a] + +v_min_num_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x2a] + +v_min_num_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x2a] + +v_min_num_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x2a] + +v_min_num_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x2a] + +v_min_num_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x2a] + +v_min_num_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x2a] + +v_min_num_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x2a] + +v_min_num_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x2b,0x56,0x34,0x12,0xaf] + +v_min_num_f64 v[5:6], v[1:2], v[3:4] +// GFX12: encoding: [0x01,0x07,0x0a,0x1a] + +v_min_num_f64 v[5:6], v[254:255], v[2:3] +// GFX12: encoding: [0xfe,0x05,0x0a,0x1a] + +v_min_num_f64 v[5:6], s[0:1], v[2:3] +// GFX12: encoding: [0x00,0x04,0x0a,0x1a] + +v_min_num_f64 v[5:6], s[104:105], v[2:3] +// GFX12: encoding: [0x68,0x04,0x0a,0x1a] + +v_min_num_f64 v[5:6], vcc, v[2:3] +// GFX12: encoding: [0x6a,0x04,0x0a,0x1a] + +v_min_num_f64 v[5:6], ttmp[14:15], v[2:3] +// GFX12: encoding: [0x7a,0x04,0x0a,0x1a] + +v_min_num_f64 v[5:6], exec, v[2:3] +// GFX12: encoding: [0x7e,0x04,0x0a,0x1a] + +v_min_num_f64 v[5:6], null, v[2:3] +// GFX12: encoding: [0x7c,0x04,0x0a,0x1a] + +v_min_num_f64 v[5:6], -1, v[2:3] +// GFX12: encoding: [0xc1,0x04,0x0a,0x1a] + +v_min_num_f64 v[5:6], 0.5, v[2:3] +// GFX12: encoding: [0xf0,0x04,0x0a,0x1a] + +v_min_num_f64 v[5:6], src_scc, v[2:3] +// GFX12: encoding: [0xfd,0x04,0x0a,0x1a] + +v_min_num_f64 v[254:255], 0xaf123456, v[254:255] +// GFX12: encoding: [0xff,0xfc,0xfd,0x1b,0x56,0x34,0x12,0xaf] + +v_min_i32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x22] + +v_min_i32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x22] + +v_min_i32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x22] + +v_min_i32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x22] + +v_min_i32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x22] + +v_min_i32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x22] + +v_min_i32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x22] + +v_min_i32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x22] + +v_min_i32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x22] + +v_min_i32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x22] + +v_min_i32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x22] + +v_min_i32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x22] + +v_min_i32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x22] + +v_min_i32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x22] + +v_min_i32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf] + +v_min_u32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x26] + +v_min_u32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x26] + +v_min_u32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x26] + +v_min_u32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x26] + +v_min_u32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x26] + +v_min_u32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x26] + +v_min_u32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x26] + +v_min_u32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x26] + +v_min_u32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x26] + +v_min_u32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x26] + +v_min_u32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x26] + +v_min_u32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x26] + +v_min_u32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x26] + +v_min_u32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x26] + +v_min_u32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf] + +v_mul_dx9_zero_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x0e] + +v_mul_dx9_zero_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] + +v_mul_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x6a] + +v_mul_f16 v5, v127, v2 +// GFX12: encoding: [0x7f,0x05,0x0a,0x6a] + +v_mul_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x6a] + +v_mul_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x6a] + +v_mul_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x6a] + +v_mul_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x6a] + +v_mul_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x6a] + +v_mul_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x6a] + +v_mul_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x6a] + +v_mul_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x6a] + +v_mul_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x6a] + +v_mul_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x6a] + +v_mul_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x6a] + +v_mul_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x6a] + +v_mul_f16 v127, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] + +v_mul_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x10] + +v_mul_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x10] + +v_mul_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x10] + +v_mul_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x10] + +v_mul_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x10] + +v_mul_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x10] + +v_mul_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x10] + +v_mul_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x10] + +v_mul_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x10] + +v_mul_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x10] + +v_mul_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x10] + +v_mul_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x10] + +v_mul_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x10] + +v_mul_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x10] + +v_mul_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf] + +v_mul_f64 v[5:6], v[1:2], v[3:4] +// GFX12: encoding: [0x01,0x07,0x0a,0x0c] + +v_mul_f64 v[5:6], v[254:255], v[2:3] +// GFX12: encoding: [0xfe,0x05,0x0a,0x0c] + +v_mul_f64 v[5:6], s[0:1], v[2:3] +// GFX12: encoding: [0x00,0x04,0x0a,0x0c] + +v_mul_f64 v[5:6], s[104:105], v[2:3] +// GFX12: encoding: [0x68,0x04,0x0a,0x0c] + +v_mul_f64 v[5:6], vcc, v[2:3] +// GFX12: encoding: [0x6a,0x04,0x0a,0x0c] + +v_mul_f64 v[5:6], ttmp[14:15], v[2:3] +// GFX12: encoding: [0x7a,0x04,0x0a,0x0c] + +v_mul_f64 v[5:6], exec, v[2:3] +// GFX12: encoding: [0x7e,0x04,0x0a,0x0c] + +v_mul_f64 v[5:6], null, v[2:3] +// GFX12: encoding: [0x7c,0x04,0x0a,0x0c] + +v_mul_f64 v[5:6], -1, v[2:3] +// GFX12: encoding: [0xc1,0x04,0x0a,0x0c] + +v_mul_f64 v[5:6], 0.5, v[2:3] +// GFX12: encoding: [0xf0,0x04,0x0a,0x0c] + +v_mul_f64 v[5:6], src_scc, v[2:3] +// GFX12: encoding: [0xfd,0x04,0x0a,0x0c] + +v_mul_f64 v[254:255], 0xaf123456, v[254:255] +// GFX12: encoding: [0xff,0xfc,0xfd,0x0d,0x56,0x34,0x12,0xaf] + +v_mul_hi_i32_i24 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x14] + +v_mul_hi_i32_i24 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x14] + +v_mul_hi_i32_i24 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x14] + +v_mul_hi_i32_i24 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf] + +v_mul_hi_u32_u24 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x18] + +v_mul_hi_u32_u24 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x18] + +v_mul_hi_u32_u24 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x18] + +v_mul_hi_u32_u24 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf] + +v_mul_i32_i24 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x12] + +v_mul_i32_i24 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x12] + +v_mul_i32_i24 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x12] + +v_mul_i32_i24 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x12] + +v_mul_i32_i24 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf] + +v_mul_legacy_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x0e] + +v_mul_legacy_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x0e] + +v_mul_legacy_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x0e] + +v_mul_legacy_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] + +v_mul_u32_u24 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x16] + +v_mul_u32_u24 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x16] + +v_mul_u32_u24 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x16] + +v_mul_u32_u24 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x16] + +v_mul_u32_u24 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf] + +v_or_b32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x38] + +v_or_b32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x38] + +v_or_b32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x38] + +v_or_b32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x38] + +v_or_b32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x38] + +v_or_b32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x38] + +v_or_b32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x38] + +v_or_b32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x38] + +v_or_b32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x38] + +v_or_b32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x38] + +v_or_b32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x38] + +v_or_b32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x38] + +v_or_b32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x38] + +v_or_b32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x38] + +v_or_b32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf] + +v_pk_fmac_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x78] + +v_pk_fmac_f16 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x78] + +v_pk_fmac_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x78] + +v_pk_fmac_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x78] + +v_pk_fmac_f16 v255, 0xfe0b, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00] + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo +// W32: encoding: [0x01,0x05,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo +// W32: encoding: [0xff,0x05,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo +// W32: encoding: [0x01,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo +// W32: encoding: [0x69,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo +// W32: encoding: [0x6a,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo +// W32: encoding: [0x6b,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo +// W32: encoding: [0x7b,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo +// W32: encoding: [0x7d,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo +// W32: encoding: [0x7e,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo +// W32: encoding: [0x7f,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo +// W32: encoding: [0x7c,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo +// W32: encoding: [0xc1,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo +// W32: encoding: [0xf0,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo +// W32: encoding: [0xfd,0x04,0x0a,0x42] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo +// W32: encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc +// W64: encoding: [0x01,0x05,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v255, v2, vcc +// W64: encoding: [0xff,0x05,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, s1, v2, vcc +// W64: encoding: [0x01,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, s105, v2, vcc +// W64: encoding: [0x69,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, vcc_lo, v2, vcc +// W64: encoding: [0x6a,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, vcc_hi, v2, vcc +// W64: encoding: [0x6b,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, ttmp15, v2, vcc +// W64: encoding: [0x7b,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, m0, v2, vcc +// W64: encoding: [0x7d,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, exec_lo, v2, vcc +// W64: encoding: [0x7e,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, exec_hi, v2, vcc +// W64: encoding: [0x7f,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, null, v2, vcc +// W64: encoding: [0x7c,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, -1, v2, vcc +// W64: encoding: [0xc1,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, 0.5, v2, vcc +// W64: encoding: [0xf0,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, src_scc, v2, vcc +// W64: encoding: [0xfd,0x04,0x0a,0x42] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc +// W64: encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x66] + +v_sub_f16 v5, v127, v2 +// GFX12: encoding: [0x7f,0x05,0x0a,0x66] + +v_sub_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x66] + +v_sub_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x66] + +v_sub_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x66] + +v_sub_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x66] + +v_sub_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x66] + +v_sub_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x66] + +v_sub_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x66] + +v_sub_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x66] + +v_sub_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x66] + +v_sub_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x66] + +v_sub_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x66] + +v_sub_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x66] + +v_sub_f16 v127, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00] + +v_sub_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x08] + +v_sub_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x08] + +v_sub_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x08] + +v_sub_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x08] + +v_sub_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x08] + +v_sub_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x08] + +v_sub_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x08] + +v_sub_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x08] + +v_sub_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x08] + +v_sub_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x08] + +v_sub_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x08] + +v_sub_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x08] + +v_sub_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x08] + +v_sub_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x08] + +v_sub_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf] + +v_sub_nc_u32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x4c] + +v_sub_nc_u32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x4c] + +v_sub_nc_u32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x4c] + +v_sub_nc_u32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x4c] + +v_sub_nc_u32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf] + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo +// W32: encoding: [0x01,0x05,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v255, v2, vcc_lo +// W32: encoding: [0xff,0x05,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, s1, v2, vcc_lo +// W32: encoding: [0x01,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, s105, v2, vcc_lo +// W32: encoding: [0x69,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, vcc_lo, v2, vcc_lo +// W32: encoding: [0x6a,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, vcc_hi, v2, vcc_lo +// W32: encoding: [0x6b,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, ttmp15, v2, vcc_lo +// W32: encoding: [0x7b,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, m0, v2, vcc_lo +// W32: encoding: [0x7d,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, exec_lo, v2, vcc_lo +// W32: encoding: [0x7e,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, exec_hi, v2, vcc_lo +// W32: encoding: [0x7f,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, null, v2, vcc_lo +// W32: encoding: [0x7c,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, -1, v2, vcc_lo +// W32: encoding: [0xc1,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, 0.5, v2, vcc_lo +// W32: encoding: [0xf0,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, src_scc, v2, vcc_lo +// W32: encoding: [0xfd,0x04,0x0a,0x44] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc_lo, 0xaf123456, v255, vcc_lo +// W32: encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc +// W64: encoding: [0x01,0x05,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v255, v2, vcc +// W64: encoding: [0xff,0x05,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, s1, v2, vcc +// W64: encoding: [0x01,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, s105, v2, vcc +// W64: encoding: [0x69,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, vcc_lo, v2, vcc +// W64: encoding: [0x6a,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, vcc_hi, v2, vcc +// W64: encoding: [0x6b,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, ttmp15, v2, vcc +// W64: encoding: [0x7b,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, m0, v2, vcc +// W64: encoding: [0x7d,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, exec_lo, v2, vcc +// W64: encoding: [0x7e,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, exec_hi, v2, vcc +// W64: encoding: [0x7f,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, null, v2, vcc +// W64: encoding: [0x7c,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, -1, v2, vcc +// W64: encoding: [0xc1,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, 0.5, v2, vcc +// W64: encoding: [0xf0,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, src_scc, v2, vcc +// W64: encoding: [0xfd,0x04,0x0a,0x44] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc, 0xaf123456, v255, vcc +// W64: encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_f16 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x68] + +v_subrev_f16 v5, v127, v2 +// GFX12: encoding: [0x7f,0x05,0x0a,0x68] + +v_subrev_f16 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x68] + +v_subrev_f16 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x68] + +v_subrev_f16 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x68] + +v_subrev_f16 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x68] + +v_subrev_f16 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x68] + +v_subrev_f16 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x68] + +v_subrev_f16 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x68] + +v_subrev_f16 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x68] + +v_subrev_f16 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x68] + +v_subrev_f16 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x68] + +v_subrev_f16 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x68] + +v_subrev_f16 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x68] + +v_subrev_f16 v127, 0xfe0b, v127 +// GFX12: encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00] + +v_subrev_f32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x0a] + +v_subrev_f32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x0a] + +v_subrev_f32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x0a] + +v_subrev_f32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x0a] + +v_subrev_f32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x0a] + +v_subrev_f32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x0a] + +v_subrev_f32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x0a] + +v_subrev_f32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x0a] + +v_subrev_f32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x0a] + +v_subrev_f32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x0a] + +v_subrev_f32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x0a] + +v_subrev_f32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x0a] + +v_subrev_f32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x0a] + +v_subrev_f32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x0a] + +v_subrev_f32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf] + +v_subrev_nc_u32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x4e] + +v_subrev_nc_u32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x4e] + +v_subrev_nc_u32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x4e] + +v_subrev_nc_u32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf] + +v_xnor_b32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x3c] + +v_xnor_b32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x3c] + +v_xnor_b32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x3c] + +v_xnor_b32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x3c] + +v_xnor_b32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x3c] + +v_xnor_b32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x3c] + +v_xnor_b32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x3c] + +v_xnor_b32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x3c] + +v_xnor_b32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x3c] + +v_xnor_b32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x3c] + +v_xnor_b32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x3c] + +v_xnor_b32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x3c] + +v_xnor_b32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x3c] + +v_xnor_b32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x3c] + +v_xnor_b32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf] + +v_xor_b32 v5, v1, v2 +// GFX12: encoding: [0x01,0x05,0x0a,0x3a] + +v_xor_b32 v5, v255, v2 +// GFX12: encoding: [0xff,0x05,0x0a,0x3a] + +v_xor_b32 v5, s1, v2 +// GFX12: encoding: [0x01,0x04,0x0a,0x3a] + +v_xor_b32 v5, s105, v2 +// GFX12: encoding: [0x69,0x04,0x0a,0x3a] + +v_xor_b32 v5, vcc_lo, v2 +// GFX12: encoding: [0x6a,0x04,0x0a,0x3a] + +v_xor_b32 v5, vcc_hi, v2 +// GFX12: encoding: [0x6b,0x04,0x0a,0x3a] + +v_xor_b32 v5, ttmp15, v2 +// GFX12: encoding: [0x7b,0x04,0x0a,0x3a] + +v_xor_b32 v5, m0, v2 +// GFX12: encoding: [0x7d,0x04,0x0a,0x3a] + +v_xor_b32 v5, exec_lo, v2 +// GFX12: encoding: [0x7e,0x04,0x0a,0x3a] + +v_xor_b32 v5, exec_hi, v2 +// GFX12: encoding: [0x7f,0x04,0x0a,0x3a] + +v_xor_b32 v5, null, v2 +// GFX12: encoding: [0x7c,0x04,0x0a,0x3a] + +v_xor_b32 v5, -1, v2 +// GFX12: encoding: [0xc1,0x04,0x0a,0x3a] + +v_xor_b32 v5, 0.5, v2 +// GFX12: encoding: [0xf0,0x04,0x0a,0x3a] + +v_xor_b32 v5, src_scc, v2 +// GFX12: encoding: [0xfd,0x04,0x0a,0x3a] + +v_xor_b32 v255, 0xaf123456, v255 +// GFX12: encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s index 08d4be08813192a2f6d144a096fd5a9c151d36bb..5593ea77d9424e0656e5acfefdf88d61cc14e02f 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2.s @@ -1,7 +1,7 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo // W32: encoding: [0x01,0x05,0x0a,0x40] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases-fake16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases-fake16.s new file mode 100644 index 0000000000000000000000000000000000000000..ebab0859b34841cc77afd8bceb7af4b706b807e0 --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases-fake16.s @@ -0,0 +1,19 @@ +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s + +v_min_f32 v5, v1, v2 +// GFX12: v_min_num_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x2a] + +v_max_f32 v5, v1, v2 +// GFX12: v_max_num_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x2c] + +v_min_f16 v5, v1, v2 +// GFX12: v_min_num_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x60] + +v_max_f16 v5, v1, v2 +// GFX12: v_max_num_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x62] + +v_max_f64 v[5:6], v[1:2], v[2:3] +// GFX12: v_max_num_f64_e32 v[5:6], v[1:2], v[2:3] ; encoding: [0x01,0x05,0x0a,0x1c] + +v_min_f64 v[5:6], v[1:2], v[2:3] +// GFX12: v_min_num_f64_e32 v[5:6], v[1:2], v[2:3] ; encoding: [0x01,0x05,0x0a,0x1a] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s index 3918dd48cfc06305db9ac6545d7b7f0475e1d5c7..b7e51cf2706478e4c0ce7c6be6ff8fe640aef29c 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_aliases.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s +// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s v_min_f32 v5, v1, v2 // GFX12: v_min_num_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x2a] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16-fake16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16-fake16.s new file mode 100644 index 0000000000000000000000000000000000000000..53373d1f46973266f22b732a88e7a79f8cd4b73d --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16-fake16.s @@ -0,0 +1,2006 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s + +v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff] + +v_add_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff] + +v_add_f16 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff] + +v_add_f16 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff] + +v_add_f16 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff] + +v_add_f16 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff] + +v_add_f16 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff] + +v_add_f16 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff] + +v_add_f16 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff] + +v_add_f16 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff] + +v_add_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff] + +v_add_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01] + +v_add_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x09,0x13] + +v_add_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xf5,0x30] + +v_add_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff] + +v_add_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff] + +v_add_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff] + +v_add_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff] + +v_add_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff] + +v_add_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff] + +v_add_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff] + +v_add_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff] + +v_add_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff] + +v_add_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff] + +v_add_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff] + +v_add_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01] + +v_add_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x09,0x13] + +v_add_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xf5,0x30] + +v_add_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff] + +v_add_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff] + +v_add_nc_u32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff] + +v_add_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01] + +v_add_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x09,0x13] + +v_add_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x05,0x30] + +v_and_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff] + +v_and_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff] + +v_and_b32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff] + +v_and_b32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff] + +v_and_b32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff] + +v_and_b32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff] + +v_and_b32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff] + +v_and_b32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff] + +v_and_b32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff] + +v_and_b32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff] + +v_and_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff] + +v_and_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01] + +v_and_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x09,0x13] + +v_and_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x05,0x30] + +v_ashrrev_i32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff] + +v_ashrrev_i32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff] + +v_ashrrev_i32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff] + +v_ashrrev_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01] + +v_ashrrev_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x09,0x13] + +v_ashrrev_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x05,0x30] + +v_cndmask_b32 v5, v1, v2, vcc_lo quad_perm:[3,2,1,0] +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_half_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_shl:1 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_shl:15 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_shr:1 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_shr:15 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_ror:1 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_ror:15 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc quad_perm:[3,2,1,0] +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc quad_perm:[0,1,2,3] +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_half_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_shl:1 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_shl:15 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_shr:1 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_shr:15 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_ror:1 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_ror:15 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x09,0x13] + +v_cvt_pk_rtz_f16_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xf5,0x30] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x09,0x13] + +v_cvt_pkrtz_f16_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xf5,0x30] + +v_fmac_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff] + +v_fmac_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff] + +v_fmac_f16 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff] + +v_fmac_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01] + +v_fmac_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x60,0x09,0x13] + +v_fmac_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xf5,0x30] + +v_fmac_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff] + +v_fmac_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff] + +v_fmac_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff] + +v_fmac_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01] + +v_fmac_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x09,0x13] + +v_fmac_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xf5,0x30] + +v_ldexp_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff] + +v_ldexp_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff] + +v_ldexp_f16 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff] + +v_ldexp_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01] + +v_ldexp_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x09,0x13] + +v_ldexp_f16 v127, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x35,0x30] + +v_lshlrev_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff] + +v_lshlrev_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff] + +v_lshlrev_b32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff] + +v_lshlrev_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01] + +v_lshlrev_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x09,0x13] + +v_lshlrev_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x05,0x30] + +v_lshrrev_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff] + +v_lshrrev_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff] + +v_lshrrev_b32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff] + +v_lshrrev_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01] + +v_lshrrev_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x09,0x13] + +v_lshrrev_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x05,0x30] + +v_max_num_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0xff] + +v_max_num_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xff] + +v_max_num_f16 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x50,0x01,0xff] + +v_max_num_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x5f,0x01,0x01] + +v_max_num_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x62,0x01,0x60,0x09,0x13] + +v_max_num_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xfe,0x62,0x7f,0x6f,0xf5,0x30] + +v_max_num_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0xff] + +v_max_num_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xff] + +v_max_num_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x50,0x01,0xff] + +v_max_num_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x01] + +v_max_num_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x60,0x09,0x13] + +v_max_num_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x2d,0xff,0x6f,0xf5,0x30] + +v_max_i32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff] + +v_max_i32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff] + +v_max_i32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff] + +v_max_i32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff] + +v_max_i32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff] + +v_max_i32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff] + +v_max_i32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff] + +v_max_i32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff] + +v_max_i32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff] + +v_max_i32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff] + +v_max_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff] + +v_max_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01] + +v_max_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x09,0x13] + +v_max_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x05,0x30] + +v_max_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff] + +v_max_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff] + +v_max_u32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff] + +v_max_u32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff] + +v_max_u32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff] + +v_max_u32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff] + +v_max_u32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff] + +v_max_u32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff] + +v_max_u32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff] + +v_max_u32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff] + +v_max_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff] + +v_max_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01] + +v_max_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x09,0x13] + +v_max_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x05,0x30] + +v_min_num_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0xff] + +v_min_num_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xff] + +v_min_num_f16 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x50,0x01,0xff] + +v_min_num_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x5f,0x01,0x01] + +v_min_num_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x60,0x01,0x60,0x09,0x13] + +v_min_num_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xfe,0x60,0x7f,0x6f,0xf5,0x30] + +v_min_num_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0xff] + +v_min_num_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xff] + +v_min_num_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x50,0x01,0xff] + +v_min_num_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x5f,0x01,0x01] + +v_min_num_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x60,0x09,0x13] + +v_min_num_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x2b,0xff,0x6f,0xf5,0x30] + +v_min_i32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff] + +v_min_i32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff] + +v_min_i32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff] + +v_min_i32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff] + +v_min_i32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff] + +v_min_i32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff] + +v_min_i32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff] + +v_min_i32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff] + +v_min_i32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff] + +v_min_i32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff] + +v_min_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff] + +v_min_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01] + +v_min_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x09,0x13] + +v_min_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x05,0x30] + +v_min_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff] + +v_min_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff] + +v_min_u32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff] + +v_min_u32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff] + +v_min_u32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff] + +v_min_u32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff] + +v_min_u32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff] + +v_min_u32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff] + +v_min_u32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff] + +v_min_u32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff] + +v_min_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff] + +v_min_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01] + +v_min_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x09,0x13] + +v_min_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x05,0x30] + +v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01] + +v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x09,0x13] + +v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30] + +v_mul_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] + +v_mul_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] + +v_mul_f16 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] + +v_mul_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] + +v_mul_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13] + +v_mul_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30] + +v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff] + +v_mul_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff] + +v_mul_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff] + +v_mul_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01] + +v_mul_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x09,0x13] + +v_mul_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xf5,0x30] + +v_mul_hi_i32_i24 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff] + +v_mul_hi_i32_i24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01] + +v_mul_hi_i32_i24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x09,0x13] + +v_mul_hi_i32_i24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x05,0x30] + +v_mul_hi_u32_u24 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff] + +v_mul_hi_u32_u24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01] + +v_mul_hi_u32_u24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x09,0x13] + +v_mul_hi_u32_u24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x05,0x30] + +v_mul_i32_i24 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff] + +v_mul_i32_i24 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff] + +v_mul_i32_i24 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff] + +v_mul_i32_i24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01] + +v_mul_i32_i24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x09,0x13] + +v_mul_i32_i24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x05,0x30] + +v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff] + +v_mul_dx9_zero_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01] + +v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x09,0x13] + +v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30] + +v_mul_u32_u24 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff] + +v_mul_u32_u24 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff] + +v_mul_u32_u24 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff] + +v_mul_u32_u24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01] + +v_mul_u32_u24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x09,0x13] + +v_mul_u32_u24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x05,0x30] + +v_or_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff] + +v_or_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff] + +v_or_b32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff] + +v_or_b32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff] + +v_or_b32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff] + +v_or_b32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff] + +v_or_b32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff] + +v_or_b32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff] + +v_or_b32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff] + +v_or_b32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff] + +v_or_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff] + +v_or_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01] + +v_or_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x09,0x13] + +v_or_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x05,0x30] + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff] + +v_sub_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff] + +v_sub_f16 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff] + +v_sub_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01] + +v_sub_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x09,0x13] + +v_sub_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xf5,0x30] + +v_sub_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff] + +v_sub_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff] + +v_sub_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff] + +v_sub_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01] + +v_sub_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x09,0x13] + +v_sub_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xf5,0x30] + +v_sub_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff] + +v_sub_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff] + +v_sub_nc_u32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff] + +v_sub_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01] + +v_sub_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x09,0x13] + +v_sub_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x05,0x30] + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W32: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x09,0x13] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W32: encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// W64: encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x09,0x13] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// W64: encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_f16 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff] + +v_subrev_f16 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff] + +v_subrev_f16 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff] + +v_subrev_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01] + +v_subrev_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13] + +v_subrev_f16 v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30] + +v_subrev_f32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff] + +v_subrev_f32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff] + +v_subrev_f32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff] + +v_subrev_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01] + +v_subrev_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x09,0x13] + +v_subrev_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xf5,0x30] + +v_subrev_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff] + +v_subrev_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff] + +v_subrev_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01] + +v_subrev_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x09,0x13] + +v_subrev_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x05,0x30] + +v_xnor_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff] + +v_xnor_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff] + +v_xnor_b32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff] + +v_xnor_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01] + +v_xnor_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x09,0x13] + +v_xnor_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x05,0x30] + +v_xor_b32 v5, v1, v2 quad_perm:[3,2,1,0] +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff] + +v_xor_b32 v5, v1, v2 quad_perm:[0,1,2,3] +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff] + +v_xor_b32 v5, v1, v2 row_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_half_mirror +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_shl:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_shl:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_shr:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_shr:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_ror:1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_ror:15 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff] + +v_xor_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01] + +v_xor_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0 +// GFX12: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x09,0x13] + +v_xor_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1 +// GFX12: encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x05,0x30] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s index 63ffdbe821af8e3b41597981a3b4c1862fad0ac6..a0f93f459f915a72cb1488207cc7f0df9c33ee37 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp16.s @@ -1,7 +1,7 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] // W32: encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8-fake16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8-fake16.s new file mode 100644 index 0000000000000000000000000000000000000000..a7a035f4a9efc0ebace6ccf2268ef29d049f571a --- /dev/null +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8-fake16.s @@ -0,0 +1,433 @@ +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s + +v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// W32: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: encoding: [0xe9,0xfe,0xff,0x41,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] +// W64: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: encoding: [0xea,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: encoding: [0xe9,0xfe,0xff,0x41,0xff,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_add_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] + +v_add_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] + +v_add_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00] + +v_add_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05] + +v_add_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x06,0x01,0x77,0x39,0x05] + +v_add_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x07,0xff,0x00,0x00,0x00] + +v_add_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05] + +v_add_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05] + +v_add_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00] + +v_and_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05] + +v_and_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x36,0x01,0x77,0x39,0x05] + +v_and_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x37,0xff,0x00,0x00,0x00] + +v_ashrrev_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05] + +v_ashrrev_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x34,0x01,0x77,0x39,0x05] + +v_ashrrev_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x35,0xff,0x00,0x00,0x00] + +v_cndmask_b32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// W32: encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: encoding: [0xea,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: encoding: [0xe9,0xfe,0xff,0x03,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] +// W64: encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: encoding: [0xea,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cndmask_b32 v255, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: encoding: [0xe9,0xfe,0xff,0x03,0xff,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] + +v_cvt_pk_rtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] + +v_cvt_pk_rtz_f16_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] + +v_cvt_pkrtz_f16_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] + +v_cvt_pkrtz_f16_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00] + +v_fmac_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05] + +v_fmac_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05] + +v_fmac_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00] + +v_fmac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05] + +v_fmac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x56,0x01,0x77,0x39,0x05] + +v_fmac_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x57,0xff,0x00,0x00,0x00] + +v_ldexp_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] + +v_ldexp_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] + +v_ldexp_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00] + +v_lshlrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05] + +v_lshlrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x30,0x01,0x77,0x39,0x05] + +v_lshlrev_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x31,0xff,0x00,0x00,0x00] + +v_lshrrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05] + +v_lshrrev_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x32,0x01,0x77,0x39,0x05] + +v_lshrrev_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x33,0xff,0x00,0x00,0x00] + +v_max_num_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x62,0x01,0x77,0x39,0x05] + +v_max_num_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x62,0x01,0x77,0x39,0x05] + +v_max_num_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xfe,0x62,0x7f,0x00,0x00,0x00] + +v_max_num_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05] + +v_max_num_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05] + +v_max_num_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x2d,0xff,0x00,0x00,0x00] + +v_max_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05] + +v_max_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x24,0x01,0x77,0x39,0x05] + +v_max_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x25,0xff,0x00,0x00,0x00] + +v_max_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05] + +v_max_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x28,0x01,0x77,0x39,0x05] + +v_max_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x29,0xff,0x00,0x00,0x00] + +v_min_num_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x60,0x01,0x77,0x39,0x05] + +v_min_num_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x60,0x01,0x77,0x39,0x05] + +v_min_num_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xfe,0x60,0x7f,0x00,0x00,0x00] + +v_min_num_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05] + +v_min_num_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05] + +v_min_num_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x2b,0xff,0x00,0x00,0x00] + +v_min_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05] + +v_min_i32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x22,0x01,0x77,0x39,0x05] + +v_min_i32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x23,0xff,0x00,0x00,0x00] + +v_min_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05] + +v_min_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x26,0x01,0x77,0x39,0x05] + +v_min_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x27,0xff,0x00,0x00,0x00] + +v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] + +v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] + +v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] + +v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] + +v_mul_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] + +v_mul_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] + +v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] + +v_mul_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] + +v_mul_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x11,0xff,0x00,0x00,0x00] + +v_mul_hi_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05] + +v_mul_hi_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x14,0x01,0x77,0x39,0x05] + +v_mul_hi_i32_i24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x15,0xff,0x00,0x00,0x00] + +v_mul_hi_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05] + +v_mul_hi_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x18,0x01,0x77,0x39,0x05] + +v_mul_hi_u32_u24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x19,0xff,0x00,0x00,0x00] + +v_mul_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05] + +v_mul_i32_i24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x12,0x01,0x77,0x39,0x05] + +v_mul_i32_i24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x13,0xff,0x00,0x00,0x00] + +v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] + +v_mul_dx9_zero_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] + +v_mul_dx9_zero_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] + +v_mul_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05] + +v_mul_u32_u24 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x16,0x01,0x77,0x39,0x05] + +v_mul_u32_u24 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x17,0xff,0x00,0x00,0x00] + +v_or_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05] + +v_or_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x38,0x01,0x77,0x39,0x05] + +v_or_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x39,0xff,0x00,0x00,0x00] + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// W32: encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: encoding: [0xea,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: encoding: [0xe9,0xfe,0xff,0x43,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] +// W64: encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: encoding: [0xea,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: encoding: [0xe9,0xfe,0xff,0x43,0xff,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_sub_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] + +v_sub_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] + +v_sub_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00] + +v_sub_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05] + +v_sub_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x08,0x01,0x77,0x39,0x05] + +v_sub_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x09,0xff,0x00,0x00,0x00] + +v_sub_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05] + +v_sub_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05] + +v_sub_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00] + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] +// W32: encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W32: encoding: [0xea,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W32: encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00] +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] +// W64: encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] fi:1 +// W64: encoding: [0xea,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:0 +// W64: encoding: [0xe9,0xfe,0xff,0x45,0xff,0x00,0x00,0x00] +// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode + +v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] + +v_subrev_f16 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] + +v_subrev_f16 v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00] + +v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05] + +v_subrev_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05] + +v_subrev_f32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00] + +v_subrev_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05] + +v_subrev_nc_u32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05] + +v_subrev_nc_u32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00] + +v_xnor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05] + +v_xnor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05] + +v_xnor_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00] + +v_xor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: encoding: [0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05] + +v_xor_b32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 +// GFX12: encoding: [0xea,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05] + +v_xor_b32 v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:0 +// GFX12: encoding: [0xe9,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s index 54baafb5366ffb412de89919e5852c3570438bfd..81fcb323e2711e9970ae4465e12fb7e5d926ef72 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_dpp8.s @@ -1,7 +1,7 @@ -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s -// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W32 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX12,W64 %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s +// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] // W32: encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s index 045d698bd504b796c494420e1a95a603a8d6765e..b339bc1960f3e7557cef7a9bab5031086bf7eb5f 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_err.s @@ -1,226 +1,227 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=error %s -v_add_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmaak_f16_e32 v255, v1, v2, 0xfe0b -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmamk_f16_e32 v255, v1, 0xfe0b, v3 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_num_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_add_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_num_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_add_f16_e32 v255, v1, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_e32 v5, v1, v255 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_add_f16_e32 v5, v255, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_e32 v255, v1, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmaak_f16_e32 v255, v1, v2, 0xfe0b +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmaak_f16_e32 v5, v1, v255, 0xfe0b +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode v_fmaak_f16_e32 v5, v255, v2, 0xfe0b -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode - -v_fmamk_f16_e32 v5, v255, 0xfe0b, v3 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_num_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_fmac_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_num_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_fmac_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_e32 v5, v255, v2 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_e32 v255, v1, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_e32 v5, v1, v255 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_e32 v5, v1, v255 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmaak_f16_e32 v5, v1, v255, 0xfe0b -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmac_f16_e32 v5, v255, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_e32 v5, v1, v255 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_fmamk_f16_e32 v255, v1, 0xfe0b, v3 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode v_fmamk_f16_e32 v5, v1, 0xfe0b, v255 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_num_f16_e32 v5, v1, v255 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_fmamk_f16_e32 v5, v255, 0xfe0b, v3 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_num_f16_e32 v5, v1, v255 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_ldexp_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_e32 v5, v1, v255 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_e32 v5, v1, v255 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_e32 v5, v1, v255 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_e32 v255, v1, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_ldexp_f16_e32 v5, v255, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_num_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:19: error: invalid operand for instruction v_max_num_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// GFX12: :[[@LINE-1]]:19: error: invalid operand for instruction -v_min_num_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_max_num_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction -v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_num_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction -v_sub_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_num_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction -v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_num_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction -v_add_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_num_f16_e32 v255, v1, v2 +// GFX12: :[[@LINE-1]]:19: error: invalid operand for instruction -v_fmac_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_num_f16_e32 v5, v1, v255 +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction -v_ldexp_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_max_num_f16_e32 v5, v255, v2 +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction -v_max_num_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_min_num_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:19: error: invalid operand for instruction -v_min_num_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_min_num_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:19: error: invalid operand for instruction -v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_num_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction -v_sub_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_num_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction -v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_num_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction -v_add_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_num_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction -v_fmac_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_min_num_f16_e32 v255, v1, v2 +// GFX12: :[[@LINE-1]]:19: error: invalid operand for instruction -v_max_num_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_min_num_f16_e32 v5, v1, v255 +// GFX12: :[[@LINE-1]]:27: error: invalid operand for instruction -v_min_num_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_min_num_f16_e32 v5, v255, v2 +// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction -v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_num_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_mul_f16_e32 v255, v1, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_num_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_mul_f16_e32 v5, v1, v255 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_mul_f16_e32 v5, v255, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode v_sub_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_ldexp_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_num_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_sub_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_num_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_sub_f16_e32 v255, v1, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_e32 v5, v1, v255 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_sub_f16_e32 v5, v255, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_add_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_fmac_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_max_num_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_subrev_f16_dpp v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_min_num_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +v_subrev_f16_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_mul_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_dpp v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_sub_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_e32 v255, v1, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode -v_subrev_f16_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +v_subrev_f16_e32 v5, v1, v255 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode + +v_subrev_f16_e32 v5, v255, v2 +// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s index 13939842f730313475ca58aaeb6c591ea8cd5b66..e9e91fa70773d388d207014066c10d0d56c51c0d 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop2_t16_promote.s @@ -1,190 +1,191 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort --version 5 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefix=GFX12 --implicit-check-not=_e32 %s v_add_f16 v255, v1, v2 -// GFX12: v_add_f16_e64 +// GFX12: v_add_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x32,0xd5,0x01,0x05,0x02,0x00] -v_fmac_f16 v255, v1, v2 -// GFX12: v_fmac_f16_e64 +v_add_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_add_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x32,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_ldexp_f16 v255, v1, v2 -// GFX12: v_ldexp_f16_e64 +v_add_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: v_add_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_max_num_f16 v255, v1, v2 -// GFX12: v_max_num_f16_e64 +v_add_f16 v5, v1, v255 +// GFX12: v_add_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x32,0xd5,0x01,0xff,0x03,0x00] -v_min_num_f16 v255, v1, v2 -// GFX12: v_min_num_f16_e64 +v_add_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_add_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v255, v1, v2 -// GFX12: v_mul_f16_e64 +v_add_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: v_add_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_sub_f16 v255, v1, v2 -// GFX12: v_sub_f16_e64 +v_add_f16 v5, v255, v2 +// GFX12: v_add_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x32,0xd5,0xff,0x05,0x02,0x00] -v_subrev_f16 v255, v1, v2 -// GFX12: v_subrev_f16_e64 +v_add_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_add_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x32,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_add_f16 v5, v255, v2 -// GFX12: v_add_f16_e64 +v_add_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: v_add_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x32,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] + +v_fmac_f16 v255, v1, v2 +// GFX12: v_fmac_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00] + +v_fmac_f16 v5, v1, v255 +// GFX12: v_fmac_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x36,0xd5,0x01,0xff,0x03,0x00] v_fmac_f16 v5, v255, v2 -// GFX12: v_fmac_f16_e64 +// GFX12: v_fmac_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x36,0xd5,0xff,0x05,0x02,0x00] -v_ldexp_f16 v5, v255, v2 -// GFX12: v_ldexp_f16_e64 +v_ldexp_f16 v255, v1, v2 +// GFX12: v_ldexp_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00] -v_max_num_f16 v5, v255, v2 -// GFX12: v_max_num_f16_e64 +v_ldexp_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_ldexp_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_min_num_f16 v5, v255, v2 -// GFX12: v_min_num_f16_e64 +v_ldexp_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: v_ldexp_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v255, v2 -// GFX12: v_mul_f16_e64 +v_ldexp_f16 v5, v255, v2 +// GFX12: v_ldexp_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x3b,0xd5,0xff,0x05,0x02,0x00] -v_sub_f16 v5, v255, v2 -// GFX12: v_sub_f16_e64 +v_ldexp_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_ldexp_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x3b,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_subrev_f16 v5, v255, v2 -// GFX12: v_subrev_f16_e64 +v_ldexp_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: v_ldexp_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x3b,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_add_f16 v5, v1, v255 -// GFX12: v_add_f16_e64 +v_max_num_f16 v255, v1, v2 +// GFX12: v_max_num_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x31,0xd5,0x01,0x05,0x02,0x00] -v_fmac_f16 v5, v1, v255 -// GFX12: v_fmac_f16_e64 +v_max_num_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_max_num_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x31,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] + +v_max_num_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: v_max_num_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] v_max_num_f16 v5, v1, v255 -// GFX12: v_max_num_f16_e64 +// GFX12: v_max_num_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x31,0xd5,0x01,0xff,0x03,0x00] -v_min_num_f16 v5, v1, v255 -// GFX12: v_min_num_f16_e64 +v_max_num_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_max_num_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x31,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v5, v1, v255 -// GFX12: v_mul_f16_e64 +v_max_num_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: v_max_num_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_sub_f16 v5, v1, v255 -// GFX12: v_sub_f16_e64 +v_max_num_f16 v5, v255, v2 +// GFX12: v_max_num_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x31,0xd5,0xff,0x05,0x02,0x00] -v_subrev_f16 v5, v1, v255 -// GFX12: v_subrev_f16_e64 +v_max_num_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_max_num_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x31,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_add_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_add_f16_e64 +v_max_num_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: v_max_num_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x31,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_ldexp_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_ldexp_f16_e64 +v_min_num_f16 v255, v1, v2 +// GFX12: v_min_num_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x30,0xd5,0x01,0x05,0x02,0x00] -v_max_num_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_max_num_f16_e64 +v_min_num_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_min_num_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x30,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] v_min_num_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_min_num_f16_e64 +// GFX12: v_min_num_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_mul_f16_e64 - -v_sub_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_sub_f16_e64 +v_min_num_f16 v5, v1, v255 +// GFX12: v_min_num_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x30,0xd5,0x01,0xff,0x03,0x00] -v_subrev_f16 v255, v1, v2 quad_perm:[3,2,1,0] -// GFX12: v_subrev_f16_e64 +v_min_num_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_min_num_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x30,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_add_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: v_add_f16_e64 +v_min_num_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: v_min_num_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_ldexp_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: v_ldexp_f16_e64 +v_min_num_f16 v5, v255, v2 +// GFX12: v_min_num_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x30,0xd5,0xff,0x05,0x02,0x00] -v_max_num_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: v_max_num_f16_e64 +v_min_num_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_min_num_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x30,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] v_min_num_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: v_min_num_f16_e64 +// GFX12: v_min_num_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x30,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_mul_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: v_mul_f16_e64 - -v_sub_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: v_sub_f16_e64 +v_mul_f16 v255, v1, v2 +// GFX12: v_mul_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00] -v_subrev_f16 v5, v255, v2 quad_perm:[3,2,1,0] -// GFX12: v_subrev_f16_e64 +v_mul_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_add_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: v_add_f16_e64 +v_mul_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_max_num_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: v_max_num_f16_e64 +v_mul_f16 v5, v1, v255 +// GFX12: v_mul_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00] -v_min_num_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: v_min_num_f16_e64 +v_mul_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] v_mul_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: v_mul_f16_e64 - -v_sub_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: v_sub_f16_e64 +// GFX12: v_mul_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_subrev_f16 v5, v1, v255 quad_perm:[3,2,1,0] -// GFX12: v_subrev_f16_e64 +v_mul_f16 v5, v255, v2 +// GFX12: v_mul_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x35,0xd5,0xff,0x05,0x02,0x00] -v_add_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_add_f16_e64 +v_mul_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x35,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_ldexp_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_ldexp_f16_e64 +v_mul_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: v_mul_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x35,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_max_num_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_max_num_f16_e64 +v_sub_f16 v255, v1, v2 +// GFX12: v_sub_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x33,0xd5,0x01,0x05,0x02,0x00] -v_min_num_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_min_num_f16_e64 +v_sub_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_sub_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x33,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_mul_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64 +v_sub_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: v_sub_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_sub_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_sub_f16_e64 +v_sub_f16 v5, v1, v255 +// GFX12: v_sub_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x33,0xd5,0x01,0xff,0x03,0x00] -v_subrev_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_subrev_f16_e64 +v_sub_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_sub_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x33,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_add_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_add_f16_e64 +v_sub_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: v_sub_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_ldexp_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_ldexp_f16_e64 +v_sub_f16 v5, v255, v2 +// GFX12: v_sub_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x33,0xd5,0xff,0x05,0x02,0x00] -v_max_num_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_max_num_f16_e64 +v_sub_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_sub_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x33,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_min_num_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_min_num_f16_e64 +v_sub_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: v_sub_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x33,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] -v_mul_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64 +v_subrev_f16 v255, v1, v2 +// GFX12: v_subrev_f16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x34,0xd5,0x01,0x05,0x02,0x00] -v_sub_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_sub_f16_e64 +v_subrev_f16 v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_subrev_f16_e64_dpp v255, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xff,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] -v_subrev_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_subrev_f16_e64 +v_subrev_f16 v255, v1, v2 quad_perm:[3,2,1,0] +// GFX12: v_subrev_f16_e64_dpp v255, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xff,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] -v_add_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_add_f16_e64 +v_subrev_f16 v5, v1, v255 +// GFX12: v_subrev_f16_e64 v5, v1, v255 ; encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x03,0x00] -v_max_num_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_max_num_f16_e64 +v_subrev_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_subrev_f16_e64_dpp v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0xfe,0x03,0x00,0x01,0x77,0x39,0x05] -v_min_num_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_min_num_f16_e64 +v_subrev_f16 v5, v1, v255 quad_perm:[3,2,1,0] +// GFX12: v_subrev_f16_e64_dpp v5, v1, v255 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0xfe,0x03,0x00,0x01,0x1b,0x00,0xff] -v_mul_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_mul_f16_e64 +v_subrev_f16 v5, v255, v2 +// GFX12: v_subrev_f16_e64 v5, v255, v2 ; encoding: [0x05,0x00,0x34,0xd5,0xff,0x05,0x02,0x00] -v_sub_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_sub_f16_e64 +v_subrev_f16 v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_subrev_f16_e64_dpp v5, v255, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x34,0xd5,0xe9,0x04,0x02,0x00,0xff,0x77,0x39,0x05] -v_subrev_f16 v5, v1, v255 dpp8:[7,6,5,4,3,2,1,0] -// GFX12: v_subrev_f16_e64 +v_subrev_f16 v5, v255, v2 quad_perm:[3,2,1,0] +// GFX12: v_subrev_f16_e64_dpp v5, v255, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x34,0xd5,0xfa,0x04,0x02,0x00,0xff,0x1b,0x00,0xff] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt index 26ffd3a4e383b24ee44b2044335deefbadb0804f..4f638cd8ff54f33be08789f7fb366691c184d095 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2.txt @@ -1,2334 +1,2324 @@ -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX11,W32,GFX11-FAKE16 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX11,W32,GFX11-REAL16 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -strict-whitespace -check-prefixes=GFX11,W64 %s +; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding %s | FileCheck -strict-whitespace -check-prefixes=GFX11,W32,GFX11-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding %s | FileCheck -strict-whitespace -check-prefixes=GFX11,W32,GFX11-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding %s | FileCheck -strict-whitespace -check-prefixes=GFX11,W64,GFX11-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding %s | FileCheck -strict-whitespace -check-prefixes=GFX11,W64,GFX11-FAKE16 %s +0x01,0x05,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x40] -0x01,0x05,0x0a,0x40 +0xff,0x05,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x40] -0xff,0x05,0x0a,0x40 +0x01,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x40] -0x01,0x04,0x0a,0x40 +0x69,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x40] -0x69,0x04,0x0a,0x40 +0x6a,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x40] -0x6a,0x04,0x0a,0x40 +0x6b,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x40] -0x6b,0x04,0x0a,0x40 +0x7b,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x40] -0x7b,0x04,0x0a,0x40 +0x7d,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x40] -0x7d,0x04,0x0a,0x40 +0x7e,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x40] -0x7e,0x04,0x0a,0x40 +0x7f,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x40] -0x7f,0x04,0x0a,0x40 +0x7c,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x40] -0x7c,0x04,0x0a,0x40 +0xc1,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x40] -0xc1,0x04,0x0a,0x40 +0xf0,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x40] -0xf0,0x04,0x0a,0x40 +0xfd,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x40] -0xfd,0x04,0x0a,0x40 +0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf # W32: v_add_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf] # W64: v_add_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf] -0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf +0x01,0x05,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x64] -0x01,0x05,0x0a,0x64 +0x81,0x05,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x64] -0x81,0x05,0x0a,0x64 +0x7f,0x05,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x64] -0x7f,0x05,0x0a,0x64 +0xff,0x05,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x64] -0xff,0x05,0x0a,0x64 +0x01,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x64] -0x01,0x04,0x0a,0x64 +0x69,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x64] -0x69,0x04,0x0a,0x64 +0x6a,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x64] -0x6a,0x04,0x0a,0x64 +0x6b,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x64] -0x6b,0x04,0x0a,0x64 +0x7b,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x64] -0x7b,0x04,0x0a,0x64 +0x7d,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x64] -0x7d,0x04,0x0a,0x64 +0x7e,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x64] -0x7e,0x04,0x0a,0x64 +0x7f,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x64] -0x7f,0x04,0x0a,0x64 +0x7c,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x64] -0x7c,0x04,0x0a,0x64 +0xc1,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x64] -0xc1,0x04,0x0a,0x64 +0xf0,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x64] -0xf0,0x04,0x0a,0x64 +0xfd,0x04,0x0a,0x64 # GFX11-REAL16: v_add_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x64] # GFX11-FAKE16: v_add_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x64] -0xfd,0x04,0x0a,0x64 -# GFX11-REAL16: v_add_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x65] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x65 0xfd,0x04,0x0b,0x65 +# GFX11-REAL16: v_add_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x65] +0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00 # GFX11-REAL16: v_add_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00] # GFX11-FAKE16: v_add_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00] -0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00 -# GFX11-REAL16: v_add_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00 0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00 +# GFX11-REAL16: v_add_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x65,0x0b,0xfe,0x00,0x00] -# GFX11: v_add_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x06] 0x01,0x05,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x06] 0xff,0x05,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x06] 0x01,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x06] 0x69,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x06] 0x6a,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x06] 0x6b,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x06] 0x7b,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x06] 0x7d,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x06] 0x7e,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x06] 0x7f,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x06] 0x7c,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x06] 0xc1,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x06] 0xf0,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x06] 0xfd,0x04,0x0a,0x06 +# GFX11: v_add_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x06] -# GFX11: v_add_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf +# GFX11: v_add_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf] -# GFX11: v_add_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4a] 0x01,0x05,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4a] 0xff,0x05,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4a] 0x01,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4a] 0x69,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4a] 0x6a,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4a] 0x6b,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4a] 0x7b,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4a] 0x7d,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4a] 0x7e,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4a] 0x7f,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4a] 0x7c,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4a] 0xc1,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4a] 0xf0,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4a] 0xfd,0x04,0x0a,0x4a +# GFX11: v_add_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4a] -# GFX11: v_add_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf +# GFX11: v_add_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf] -# GFX11: v_and_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x36] 0x01,0x05,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x36] 0xff,0x05,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x36] 0x01,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x36] 0x69,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x36] 0x6a,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x36] 0x6b,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x36] 0x7b,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x36] 0x7d,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x36] 0x7e,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x36] 0x7f,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x36] 0x7c,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x36] 0xc1,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x36] 0xf0,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x36] 0xfd,0x04,0x0a,0x36 +# GFX11: v_and_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x36] -# GFX11: v_and_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf +# GFX11: v_and_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf] -# GFX11: v_ashrrev_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x34] 0x01,0x05,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x34] 0xff,0x05,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x34] 0x01,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x34] 0x69,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x34] 0x6a,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x34] 0x6b,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x34] 0x7b,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x34] 0x7d,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x34] 0x7e,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x34] 0x7f,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x34] 0x7c,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x34] 0xc1,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x34] 0xf0,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x34] 0xfd,0x04,0x0a,0x34 +# GFX11: v_ashrrev_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x34] -# GFX11: v_ashrrev_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf +# GFX11: v_ashrrev_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf] +0x01,0x05,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x02] -0x01,0x05,0x0a,0x02 +0xff,0x05,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x02] -0xff,0x05,0x0a,0x02 +0x01,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x02] -0x01,0x04,0x0a,0x02 +0x69,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x02] -0x69,0x04,0x0a,0x02 +0x6a,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x02] -0x6a,0x04,0x0a,0x02 +0x6b,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x02] -0x6b,0x04,0x0a,0x02 +0x7b,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x02] -0x7b,0x04,0x0a,0x02 +0x7d,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x02] -0x7d,0x04,0x0a,0x02 +0x7e,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x02] -0x7e,0x04,0x0a,0x02 +0x7f,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x02] -0x7f,0x04,0x0a,0x02 +0x7c,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x02] -0x7c,0x04,0x0a,0x02 +0xc1,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x02] -0xc1,0x04,0x0a,0x02 +0xf0,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x02] -0xf0,0x04,0x0a,0x02 +0xfd,0x04,0x0a,0x02 # W32: v_cndmask_b32_e32 v5, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x02] # W64: v_cndmask_b32_e32 v5, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x02] -0xfd,0x04,0x0a,0x02 +0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf # W32: v_cndmask_b32_e32 v255, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf] # W64: v_cndmask_b32_e32 v255, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf] -0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x5e] 0x01,0x05,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x5e] 0xff,0x05,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x5e] 0x01,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x5e] 0x69,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x5e] 0x6a,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x5e] 0x6b,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x5e] 0x7b,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x5e] 0x7d,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x5e] 0x7e,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x5e] 0x7f,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x5e] 0x7c,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x5e] 0xc1,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x5e] 0xf0,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x5e] 0xfd,0x04,0x0a,0x5e +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x5e] -# GFX11: v_cvt_pk_rtz_f16_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf +# GFX11: v_cvt_pk_rtz_f16_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf] -# GFX11: v_dot2acc_f32_f16 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x04] 0x01,0x05,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x04] 0xff,0x05,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x04] 0x01,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x04] 0x69,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x04] 0x6a,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x04] 0x6b,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x04] 0x7b,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x04] 0x7d,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x04] 0x7e,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x04] 0x7f,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x04] 0x7c,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x04] 0xc1,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x04] 0xf0,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x04] 0xfd,0x04,0x0a,0x04 +# GFX11: v_dot2acc_f32_f16 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x04] -# GFX11: v_dot2acc_f32_f16 v255, 0xfe0b, v255 ; encoding: [0xff,0xfe,0xff,0x05,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xff,0x05,0x0b,0xfe,0x00,0x00 +# GFX11: v_dot2acc_f32_f16 v255, 0xfe0b, v255 ; encoding: [0xff,0xfe,0xff,0x05,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, v1, v2, 0xfe0b ; encoding: [0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, v1, v2, 0xfe0b ; encoding: [0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, v127, v2, 0xfe0b ; encoding: [0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, v127, v2, 0xfe0b ; encoding: [0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, s1, v2, 0xfe0b ; encoding: [0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, s1, v2, 0xfe0b ; encoding: [0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, s105, v2, 0xfe0b ; encoding: [0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, s105, v2, 0xfe0b ; encoding: [0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, vcc_lo, v2, 0xfe0b ; encoding: [0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, vcc_lo, v2, 0xfe0b ; encoding: [0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, vcc_hi, v2, 0xfe0b ; encoding: [0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, vcc_hi, v2, 0xfe0b ; encoding: [0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, ttmp15, v2, 0xfe0b ; encoding: [0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, ttmp15, v2, 0xfe0b ; encoding: [0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, m0, v2, 0xfe0b ; encoding: [0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, m0, v2, 0xfe0b ; encoding: [0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, exec_lo, v2, 0xfe0b ; encoding: [0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, exec_lo, v2, 0xfe0b ; encoding: [0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, exec_hi, v2, 0xfe0b ; encoding: [0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, exec_hi, v2, 0xfe0b ; encoding: [0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, null, v2, 0xfe0b ; encoding: [0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, null, v2, 0xfe0b ; encoding: [0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, -1, v2, 0xfe0b ; encoding: [0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, -1, v2, 0xfe0b ; encoding: [0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, 0.5, v2, 0xfe0b ; encoding: [0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, 0.5, v2, 0xfe0b ; encoding: [0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v5, src_scc, v2, 0xfe0b ; encoding: [0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v5, src_scc, v2, 0xfe0b ; encoding: [0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f16 v127, 0xfe0b, v127, 0xfe0b ; encoding: [0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmaak_f16 v127, 0xfe0b, v127, 0xfe0b ; encoding: [0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmaak_f32 v5, v1, v2, 0xaf123456 ; encoding: [0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, v1, v2, 0xaf123456 ; encoding: [0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, v255, v2, 0xaf123456 ; encoding: [0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, v255, v2, 0xaf123456 ; encoding: [0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, s1, v2, 0xaf123456 ; encoding: [0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, s1, v2, 0xaf123456 ; encoding: [0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, s105, v2, 0xaf123456 ; encoding: [0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, s105, v2, 0xaf123456 ; encoding: [0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, vcc_lo, v2, 0xaf123456 ; encoding: [0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, vcc_lo, v2, 0xaf123456 ; encoding: [0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, vcc_hi, v2, 0xaf123456 ; encoding: [0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, vcc_hi, v2, 0xaf123456 ; encoding: [0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, ttmp15, v2, 0xaf123456 ; encoding: [0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, ttmp15, v2, 0xaf123456 ; encoding: [0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, m0, v2, 0xaf123456 ; encoding: [0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, m0, v2, 0xaf123456 ; encoding: [0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, exec_lo, v2, 0xaf123456 ; encoding: [0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, exec_lo, v2, 0xaf123456 ; encoding: [0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, exec_hi, v2, 0xaf123456 ; encoding: [0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, exec_hi, v2, 0xaf123456 ; encoding: [0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, null, v2, 0xaf123456 ; encoding: [0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, null, v2, 0xaf123456 ; encoding: [0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, -1, v2, 0xaf123456 ; encoding: [0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, -1, v2, 0xaf123456 ; encoding: [0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v5, src_scc, v2, 0xaf123456 ; encoding: [0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v5, src_scc, v2, 0xaf123456 ; encoding: [0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX11: v_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 ; encoding: [0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf +# GFX11: v_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 ; encoding: [0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0c] 0x01,0x05,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0c] 0xff,0x05,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0c] 0x01,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0c] 0x69,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0c] 0x6a,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0c] 0x6b,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0c] 0x7b,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0c] 0x7d,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0c] 0x7e,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0c] 0x7f,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0c] 0x7c,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0c] 0xc1,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0c] 0xf0,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0c] 0xfd,0x04,0x0a,0x0c +# GFX11: v_fmac_dx9_zero_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0c] -# GFX11: v_fmac_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0d,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x0d,0x56,0x34,0x12,0xaf +# GFX11: v_fmac_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0d,0x56,0x34,0x12,0xaf] -# GFX11: v_fmac_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6c] 0x01,0x05,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6c] 0x7f,0x05,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6c] 0x01,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6c] 0x69,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6c] 0x6a,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6c] 0x6b,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6c] 0x7b,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6c] 0x7d,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6c] 0x7e,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6c] 0x7f,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6c] 0x7c,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6c] 0xc1,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6c] 0xf0,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6c] 0xfd,0x04,0x0a,0x6c +# GFX11: v_fmac_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6c] -# GFX11: v_fmac_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmac_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmac_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x56] 0x01,0x05,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x56] 0xff,0x05,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x56] 0x01,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x56] 0x69,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x56] 0x6a,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x56] 0x6b,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x56] 0x7b,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x56] 0x7d,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x56] 0x7e,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x56] 0x7f,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x56] 0x7c,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x56] 0xc1,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x56] 0xf0,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x56] 0xfd,0x04,0x0a,0x56 +# GFX11: v_fmac_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x56] -# GFX11: v_fmac_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf +# GFX11: v_fmac_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f16 v5, v1, 0xfe0b, v3 ; encoding: [0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, v1, 0xfe0b, v3 ; encoding: [0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, v127, 0xfe0b, v3 ; encoding: [0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, v127, 0xfe0b, v3 ; encoding: [0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, s1, 0xfe0b, v3 ; encoding: [0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, s1, 0xfe0b, v3 ; encoding: [0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, s105, 0xfe0b, v3 ; encoding: [0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, s105, 0xfe0b, v3 ; encoding: [0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, vcc_lo, 0xfe0b, v3 ; encoding: [0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, vcc_lo, 0xfe0b, v3 ; encoding: [0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, vcc_hi, 0xfe0b, v3 ; encoding: [0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, vcc_hi, 0xfe0b, v3 ; encoding: [0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, ttmp15, 0xfe0b, v3 ; encoding: [0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, ttmp15, 0xfe0b, v3 ; encoding: [0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, m0, 0xfe0b, v3 ; encoding: [0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, m0, 0xfe0b, v3 ; encoding: [0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, exec_lo, 0xfe0b, v3 ; encoding: [0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, exec_lo, 0xfe0b, v3 ; encoding: [0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, exec_hi, 0xfe0b, v3 ; encoding: [0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, exec_hi, 0xfe0b, v3 ; encoding: [0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, null, 0xfe0b, v3 ; encoding: [0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, null, 0xfe0b, v3 ; encoding: [0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, -1, 0xfe0b, v3 ; encoding: [0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, -1, 0xfe0b, v3 ; encoding: [0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, 0.5, 0xfe0b, v3 ; encoding: [0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, 0.5, 0xfe0b, v3 ; encoding: [0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v5, src_scc, 0xfe0b, v3 ; encoding: [0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v5, src_scc, 0xfe0b, v3 ; encoding: [0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f16 v127, 0xfe0b, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00 +# GFX11: v_fmamk_f16 v127, 0xfe0b, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00] -# GFX11: v_fmamk_f32 v5, v1, 0xaf123456, v3 ; encoding: [0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, v1, 0xaf123456, v3 ; encoding: [0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, v255, 0xaf123456, v3 ; encoding: [0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] 0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, v255, 0xaf123456, v3 ; encoding: [0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, s1, 0xaf123456, v3 ; encoding: [0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, s1, 0xaf123456, v3 ; encoding: [0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, s105, 0xaf123456, v3 ; encoding: [0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, s105, 0xaf123456, v3 ; encoding: [0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, vcc_lo, 0xaf123456, v3 ; encoding: [0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, vcc_lo, 0xaf123456, v3 ; encoding: [0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, vcc_hi, 0xaf123456, v3 ; encoding: [0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, vcc_hi, 0xaf123456, v3 ; encoding: [0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, ttmp15, 0xaf123456, v3 ; encoding: [0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, ttmp15, 0xaf123456, v3 ; encoding: [0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, m0, 0xaf123456, v3 ; encoding: [0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, m0, 0xaf123456, v3 ; encoding: [0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, exec_lo, 0xaf123456, v3 ; encoding: [0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, exec_lo, 0xaf123456, v3 ; encoding: [0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, exec_hi, 0xaf123456, v3 ; encoding: [0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, exec_hi, 0xaf123456, v3 ; encoding: [0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, null, 0xaf123456, v3 ; encoding: [0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, null, 0xaf123456, v3 ; encoding: [0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, -1, 0xaf123456, v3 ; encoding: [0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, -1, 0xaf123456, v3 ; encoding: [0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, 0.5, 0xaf123456, v3 ; encoding: [0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, 0.5, 0xaf123456, v3 ; encoding: [0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v5, src_scc, 0xaf123456, v3 ; encoding: [0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v5, src_scc, 0xaf123456, v3 ; encoding: [0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX11: v_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf +# GFX11: v_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x76] 0x01,0x05,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x76] 0x7f,0x05,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x76] 0x01,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x76] 0x69,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x76] 0x6a,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x76] 0x6b,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x76] 0x7b,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x76] 0x7d,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x76] 0x7e,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x76] 0x7f,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x76] 0x7c,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x76] 0xc1,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x76] 0xf0,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x76] -# GFX11-REAL16: v_ldexp_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x76] 0xfd,0x04,0x0a,0x76 +# GFX11-REAL16: v_ldexp_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x76] +# GFX11-FAKE16: v_ldexp_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x76] -# GFX11-FAKE16: v_ldexp_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] -# GFX11-REAL16: v_ldexp_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00 +# GFX11-REAL16: v_ldexp_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] +# GFX11-FAKE16: v_ldexp_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] -# GFX11: v_lshlrev_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x30] 0x01,0x05,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x30] 0xff,0x05,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x30] 0x01,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x30] 0x69,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x30] 0x6a,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x30] 0x6b,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x30] 0x7b,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x30] 0x7d,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x30] 0x7e,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x30] 0x7f,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x30] 0x7c,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x30] 0xc1,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x30] 0xf0,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x30] 0xfd,0x04,0x0a,0x30 +# GFX11: v_lshlrev_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x30] -# GFX11: v_lshlrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf +# GFX11: v_lshlrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf] -# GFX11: v_lshrrev_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x32] 0x01,0x05,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x32] 0xff,0x05,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x32] 0x01,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x32] 0x69,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x32] 0x6a,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x32] 0x6b,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x32] 0x7b,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x32] 0x7d,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x32] 0x7e,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x32] 0x7f,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x32] 0x7c,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x32] 0xc1,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x32] 0xf0,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x32] 0xfd,0x04,0x0a,0x32 +# GFX11: v_lshrrev_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x32] -# GFX11: v_lshrrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf +# GFX11: v_lshrrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf] +0x01,0x05,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x72] -0x01,0x05,0x0a,0x72 +0x81,0x05,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x72] -0x81,0x05,0x0a,0x72 +0x7f,0x05,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x72] -0x7f,0x05,0x0a,0x72 +0xff,0x05,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x72] -0xff,0x05,0x0a,0x72 +0x01,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x72] -0x01,0x04,0x0a,0x72 +0x69,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x72] -0x69,0x04,0x0a,0x72 +0x6a,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x72] -0x6a,0x04,0x0a,0x72 +0x6b,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x72] -0x6b,0x04,0x0a,0x72 +0x7b,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x72] -0x7b,0x04,0x0a,0x72 +0x7d,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x72] -0x7d,0x04,0x0a,0x72 +0x7e,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x72] -0x7e,0x04,0x0a,0x72 +0x7f,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x72] -0x7f,0x04,0x0a,0x72 +0x7c,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x72] -0x7c,0x04,0x0a,0x72 +0xc1,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x72] -0xc1,0x04,0x0a,0x72 +0xf0,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x72] -0xf0,0x04,0x0a,0x72 +0xfd,0x04,0x0a,0x72 # GFX11-REAL16: v_max_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x72] # GFX11-FAKE16: v_max_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x72] -0xfd,0x04,0x0a,0x72 -# GFX11-REAL16: v_max_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x73] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x73 0xfd,0x04,0x0b,0x73 +# GFX11-REAL16: v_max_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x73] +0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00 # GFX11-REAL16: v_max_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00] # GFX11-FAKE16: v_max_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00] -0xff,0xfe,0xfe,0x72,0x0b,0xfe,0x00,0x00 -# GFX11-REAL16: v_max_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00 0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00 +# GFX11-REAL16: v_max_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x73,0x0b,0xfe,0x00,0x00] -# GFX11: v_max_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x20] 0x01,0x05,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x20] 0xff,0x05,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x20] 0x01,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x20] 0x69,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x20] 0x6a,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x20] 0x6b,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x20] 0x7b,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x20] 0x7d,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x20] 0x7e,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x20] 0x7f,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x20] 0x7c,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x20] 0xc1,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x20] 0xf0,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x20] 0xfd,0x04,0x0a,0x20 +# GFX11: v_max_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x20] -# GFX11: v_max_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x21,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x21,0x56,0x34,0x12,0xaf +# GFX11: v_max_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x21,0x56,0x34,0x12,0xaf] -# GFX11: v_max_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x24] 0x01,0x05,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x24] 0xff,0x05,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x24] 0x01,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x24] 0x69,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x24] 0x6a,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x24] 0x6b,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x24] 0x7b,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x24] 0x7d,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x24] 0x7e,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x24] 0x7f,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x24] 0x7c,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x24] 0xc1,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x24] 0xf0,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x24] 0xfd,0x04,0x0a,0x24 +# GFX11: v_max_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x24] -# GFX11: v_max_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf +# GFX11: v_max_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf] -# GFX11: v_max_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x28] 0x01,0x05,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x28] 0xff,0x05,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x28] 0x01,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x28] 0x69,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x28] 0x6a,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x28] 0x6b,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x28] 0x7b,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x28] 0x7d,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x28] 0x7e,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x28] 0x7f,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x28] 0x7c,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x28] 0xc1,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x28] 0xf0,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x28] 0xfd,0x04,0x0a,0x28 +# GFX11: v_max_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x28] -# GFX11: v_max_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf +# GFX11: v_max_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf] +0x01,0x05,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x74] -0x01,0x05,0x0a,0x74 +0x81,0x05,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x74] -0x81,0x05,0x0a,0x74 +0x7f,0x05,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x74] -0x7f,0x05,0x0a,0x74 +0xff,0x05,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x74] -0xff,0x05,0x0a,0x74 +0x01,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x74] -0x01,0x04,0x0a,0x74 +0x69,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x74] -0x69,0x04,0x0a,0x74 +0x6a,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x74] -0x6a,0x04,0x0a,0x74 +0x6b,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x74] -0x6b,0x04,0x0a,0x74 +0x7b,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x74] -0x7b,0x04,0x0a,0x74 +0x7d,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x74] -0x7d,0x04,0x0a,0x74 +0x7e,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x74] -0x7e,0x04,0x0a,0x74 +0x7f,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x74] -0x7f,0x04,0x0a,0x74 +0x7c,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x74] -0x7c,0x04,0x0a,0x74 +0xc1,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x74] -0xc1,0x04,0x0a,0x74 +0xf0,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x74] -0xf0,0x04,0x0a,0x74 +0xfd,0x04,0x0a,0x74 # GFX11-REAL16: v_min_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x74] # GFX11-FAKE16: v_min_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x74] -0xfd,0x04,0x0a,0x74 -# GFX11-REAL16: v_min_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x75] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x75 0xfd,0x04,0x0b,0x75 +# GFX11-REAL16: v_min_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x75] +0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00 # GFX11-REAL16: v_min_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00] # GFX11-FAKE16: v_min_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00] -0xff,0xfe,0xfe,0x74,0x0b,0xfe,0x00,0x00 -# GFX11-REAL16: v_min_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00 0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00 +# GFX11-REAL16: v_min_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x75,0x0b,0xfe,0x00,0x00] -# GFX11: v_min_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x1e] 0x01,0x05,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x1e] 0xff,0x05,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x1e] 0x01,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x1e] 0x69,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x1e] 0x6a,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x1e] 0x6b,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x1e] 0x7b,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x1e] 0x7d,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x1e] 0x7e,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x1e] 0x7f,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x1e] 0x7c,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x1e] 0xc1,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x1e] 0xf0,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x1e] 0xfd,0x04,0x0a,0x1e +# GFX11: v_min_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x1e] -# GFX11: v_min_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x1f,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x1f,0x56,0x34,0x12,0xaf +# GFX11: v_min_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x1f,0x56,0x34,0x12,0xaf] -# GFX11: v_min_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x22] 0x01,0x05,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x22] 0xff,0x05,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x22] 0x01,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x22] 0x69,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x22] 0x6a,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x22] 0x6b,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x22] 0x7b,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x22] 0x7d,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x22] 0x7e,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x22] 0x7f,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x22] 0x7c,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x22] 0xc1,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x22] 0xf0,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x22] 0xfd,0x04,0x0a,0x22 +# GFX11: v_min_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x22] -# GFX11: v_min_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf +# GFX11: v_min_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf] -# GFX11: v_min_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x26] 0x01,0x05,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x26] 0xff,0x05,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x26] 0x01,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x26] 0x69,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x26] 0x6a,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x26] 0x6b,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x26] 0x7b,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x26] 0x7d,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x26] 0x7e,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x26] 0x7f,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x26] 0x7c,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x26] 0xc1,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x26] 0xf0,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x26] 0xfd,0x04,0x0a,0x26 +# GFX11: v_min_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x26] -# GFX11: v_min_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf +# GFX11: v_min_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf] -# GFX11: v_mul_dx9_zero_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0e] 0x01,0x05,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0e] 0xff,0x05,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0e] 0x01,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0e] 0x69,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0e] 0x6a,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0e] 0x6b,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0e] 0x7b,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0e] 0x7d,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0e] 0x7e,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0e] 0x7f,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0e] 0x7c,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0e] 0xc1,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0e] 0xf0,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0e] 0xfd,0x04,0x0a,0x0e +# GFX11: v_mul_dx9_zero_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0e] -# GFX11: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf +# GFX11: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] +0x01,0x05,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6a] -0x01,0x05,0x0a,0x6a -# GFX11-REAL16: v_mul_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x6a] -# GFX11-FAKE16: v_mul_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x6a 0x81,0x05,0x0a,0x6a +# GFX11-REAL16: v_mul_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x6a] +# GFX11-FAKE16: v_mul_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x6a] +0x7f,0x05,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6a] -0x7f,0x05,0x0a,0x6a +0xff,0x05,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x6a] -0xff,0x05,0x0a,0x6a +0x01,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6a] -0x01,0x04,0x0a,0x6a +0x69,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6a] -0x69,0x04,0x0a,0x6a +0x6a,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6a] -0x6a,0x04,0x0a,0x6a +0x6b,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6a] -0x6b,0x04,0x0a,0x6a +0x7b,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6a] -0x7b,0x04,0x0a,0x6a +0x7d,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6a] -0x7d,0x04,0x0a,0x6a +0x7e,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6a] -0x7e,0x04,0x0a,0x6a +0x7f,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6a] -0x7f,0x04,0x0a,0x6a +0x7c,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6a] -0x7c,0x04,0x0a,0x6a +0xc1,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6a] -0xc1,0x04,0x0a,0x6a +0xf0,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6a] -0xf0,0x04,0x0a,0x6a +0xfd,0x04,0x0a,0x6a # GFX11-REAL16: v_mul_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x6a] # GFX11-FAKE16: v_mul_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6a] -0xfd,0x04,0x0a,0x6a -# GFX11-REAL16: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x6b 0xfd,0x04,0x0b,0x6b +# GFX11-REAL16: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b] +0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00 # GFX11-REAL16: v_mul_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] # GFX11-FAKE16: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] -0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00 -# GFX11-REAL16: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00 0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00 +# GFX11-REAL16: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00] -# GFX11: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10] 0x01,0x05,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x10] 0xff,0x05,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x10] 0x01,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x10] 0x69,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x10] 0x6a,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x10] 0x6b,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x10] 0x7b,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x10] 0x7d,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x10] 0x7e,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x10] 0x7f,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x10] 0x7c,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x10] 0xc1,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x10] 0xf0,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x10] 0xfd,0x04,0x0a,0x10 +# GFX11: v_mul_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x10] -# GFX11: v_mul_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf +# GFX11: v_mul_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf] -# GFX11: v_mul_hi_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x14] 0x01,0x05,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x14] 0xff,0x05,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x14] 0x01,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x14] 0x69,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x14] 0x6a,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x14] 0x6b,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x14] 0x7b,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x14] 0x7d,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x14] 0x7e,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x14] 0x7f,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x14] 0x7c,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x14] 0xc1,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x14] 0xf0,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x14] 0xfd,0x04,0x0a,0x14 +# GFX11: v_mul_hi_i32_i24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x14] -# GFX11: v_mul_hi_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf +# GFX11: v_mul_hi_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf] -# GFX11: v_mul_hi_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x18] 0x01,0x05,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x18] 0xff,0x05,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x18] 0x01,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x18] 0x69,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x18] 0x6a,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x18] 0x6b,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x18] 0x7b,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x18] 0x7d,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x18] 0x7e,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x18] 0x7f,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x18] 0x7c,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x18] 0xc1,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x18] 0xf0,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x18] 0xfd,0x04,0x0a,0x18 +# GFX11: v_mul_hi_u32_u24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x18] -# GFX11: v_mul_hi_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf +# GFX11: v_mul_hi_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf] -# GFX11: v_mul_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x12] 0x01,0x05,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x12] 0xff,0x05,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x12] 0x01,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x12] 0x69,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x12] 0x6a,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x12] 0x6b,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x12] 0x7b,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x12] 0x7d,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x12] 0x7e,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x12] 0x7f,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x12] 0x7c,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x12] 0xc1,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x12] 0xf0,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x12] 0xfd,0x04,0x0a,0x12 +# GFX11: v_mul_i32_i24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x12] -# GFX11: v_mul_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf +# GFX11: v_mul_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf] -# GFX11: v_mul_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x16] 0x01,0x05,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x16] 0xff,0x05,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x16] 0x01,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x16] 0x69,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x16] 0x6a,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x16] 0x6b,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x16] 0x7b,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x16] 0x7d,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x16] 0x7e,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x16] 0x7f,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x16] 0x7c,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x16] 0xc1,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x16] 0xf0,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x16] 0xfd,0x04,0x0a,0x16 +# GFX11: v_mul_u32_u24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x16] -# GFX11: v_mul_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf +# GFX11: v_mul_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf] -# GFX11: v_or_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x38] 0x01,0x05,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x38] 0xff,0x05,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x38] 0x01,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x38] 0x69,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x38] 0x6a,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x38] 0x6b,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x38] 0x7b,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x38] 0x7d,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x38] 0x7e,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x38] 0x7f,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x38] 0x7c,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x38] 0xc1,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x38] 0xf0,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x38] 0xfd,0x04,0x0a,0x38 +# GFX11: v_or_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x38] -# GFX11: v_or_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf +# GFX11: v_or_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf] -# GFX11: v_pk_fmac_f16 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x78] 0x01,0x05,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x78] 0xff,0x05,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x78] 0x01,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x78] 0x69,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x78] 0x6a,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x78] 0x6b,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x78] 0x7b,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x78] 0x7d,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x78] 0x7e,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x78] 0x7f,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x78] 0x7c,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x78] 0xc1,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x78] 0xf0,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x78] 0xfd,0x04,0x0a,0x78 +# GFX11: v_pk_fmac_f16 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x78] -# GFX11: v_pk_fmac_f16 v255, 0xfe0b, v255 ; encoding: [0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00 +# GFX11: v_pk_fmac_f16 v255, 0xfe0b, v255 ; encoding: [0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00] +0x01,0x05,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x42] -0x01,0x05,0x0a,0x42 +0xff,0x05,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x42] -0xff,0x05,0x0a,0x42 +0x01,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x42] -0x01,0x04,0x0a,0x42 +0x69,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x42] -0x69,0x04,0x0a,0x42 +0x6a,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x42] -0x6a,0x04,0x0a,0x42 +0x6b,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x42] -0x6b,0x04,0x0a,0x42 +0x7b,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x42] -0x7b,0x04,0x0a,0x42 +0x7d,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x42] -0x7d,0x04,0x0a,0x42 +0x7e,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x42] -0x7e,0x04,0x0a,0x42 +0x7f,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x42] -0x7f,0x04,0x0a,0x42 +0x7c,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x42] -0x7c,0x04,0x0a,0x42 +0xc1,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x42] -0xc1,0x04,0x0a,0x42 +0xf0,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x42] -0xf0,0x04,0x0a,0x42 +0xfd,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x42] -0xfd,0x04,0x0a,0x42 +0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf # W32: v_sub_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf] # W64: v_sub_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf] -0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf +0x01,0x05,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x66] -0x01,0x05,0x0a,0x66 +0x81,0x05,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x66] -0x81,0x05,0x0a,0x66 +0x7f,0x05,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x66] -0x7f,0x05,0x0a,0x66 +0xff,0x05,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x66] -0xff,0x05,0x0a,0x66 +0x01,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x66] -0x01,0x04,0x0a,0x66 +0x69,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x66] -0x69,0x04,0x0a,0x66 +0x6a,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x66] -0x6a,0x04,0x0a,0x66 +0x6b,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x66] -0x6b,0x04,0x0a,0x66 +0x7b,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x66] -0x7b,0x04,0x0a,0x66 +0x7d,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x66] -0x7d,0x04,0x0a,0x66 +0x7e,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x66] -0x7e,0x04,0x0a,0x66 +0x7f,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x66] -0x7f,0x04,0x0a,0x66 +0x7c,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x66] -0x7c,0x04,0x0a,0x66 +0xc1,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x66] -0xc1,0x04,0x0a,0x66 +0xf0,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x66] -0xf0,0x04,0x0a,0x66 +0xfd,0x04,0x0a,0x66 # GFX11-REAL16: v_sub_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x66] # GFX11-FAKE16: v_sub_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x66] -0xfd,0x04,0x0a,0x66 -# GFX11-REAL16: v_sub_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x67] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x67 0xfd,0x04,0x0b,0x67 +# GFX11-REAL16: v_sub_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x67] +0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00 # GFX11-REAL16: v_sub_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00] # GFX11-FAKE16: v_sub_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00] -0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00 -# GFX11-REAL16: v_sub_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00 0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00 +# GFX11-REAL16: v_sub_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x67,0x0b,0xfe,0x00,0x00] -# GFX11: v_sub_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x08] 0x01,0x05,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x08] 0xff,0x05,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x08] 0x01,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x08] 0x69,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x08] 0x6a,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x08] 0x6b,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x08] 0x7b,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x08] 0x7d,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x08] 0x7e,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x08] 0x7f,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x08] 0x7c,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x08] 0xc1,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x08] 0xf0,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x08] 0xfd,0x04,0x0a,0x08 +# GFX11: v_sub_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x08] -# GFX11: v_sub_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf +# GFX11: v_sub_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf] -# GFX11: v_sub_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4c] 0x01,0x05,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4c] 0xff,0x05,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4c] 0x01,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4c] 0x69,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4c] 0x6a,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4c] 0x6b,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4c] 0x7b,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4c] 0x7d,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4c] 0x7e,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4c] 0x7f,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4c] 0x7c,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4c] 0xc1,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4c] 0xf0,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4c] 0xfd,0x04,0x0a,0x4c +# GFX11: v_sub_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4c] -# GFX11: v_sub_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf +# GFX11: v_sub_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf] +0x01,0x05,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x44] -0x01,0x05,0x0a,0x44 +0xff,0x05,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x44] -0xff,0x05,0x0a,0x44 +0x01,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x44] -0x01,0x04,0x0a,0x44 +0x69,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x44] -0x69,0x04,0x0a,0x44 +0x6a,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x44] -0x6a,0x04,0x0a,0x44 +0x6b,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x44] -0x6b,0x04,0x0a,0x44 +0x7b,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x44] -0x7b,0x04,0x0a,0x44 +0x7d,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x44] -0x7d,0x04,0x0a,0x44 +0x7e,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x44] -0x7e,0x04,0x0a,0x44 +0x7f,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x44] -0x7f,0x04,0x0a,0x44 +0x7c,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x44] -0x7c,0x04,0x0a,0x44 +0xc1,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x44] -0xc1,0x04,0x0a,0x44 +0xf0,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x44] -0xf0,0x04,0x0a,0x44 +0xfd,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x44] -0xfd,0x04,0x0a,0x44 +0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf # W32: v_subrev_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf] # W64: v_subrev_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf] -0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf +0x01,0x05,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x68] -0x01,0x05,0x0a,0x68 +0x81,0x05,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x68] -0x81,0x05,0x0a,0x68 +0x7f,0x05,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x68] -0x7f,0x05,0x0a,0x68 +0xff,0x05,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x68] -0xff,0x05,0x0a,0x68 +0x01,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x68] -0x01,0x04,0x0a,0x68 +0x69,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x68] -0x69,0x04,0x0a,0x68 +0x6a,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x68] -0x6a,0x04,0x0a,0x68 +0x6b,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x68] -0x6b,0x04,0x0a,0x68 +0x7b,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x68] -0x7b,0x04,0x0a,0x68 +0x7d,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x68] -0x7d,0x04,0x0a,0x68 +0x7e,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x68] -0x7e,0x04,0x0a,0x68 +0x7f,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x68] -0x7f,0x04,0x0a,0x68 +0x7c,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x68] -0x7c,0x04,0x0a,0x68 +0xc1,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x68] -0xc1,0x04,0x0a,0x68 +0xf0,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x68] -0xf0,0x04,0x0a,0x68 +0xfd,0x04,0x0a,0x68 # GFX11-REAL16: v_subrev_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x68] # GFX11-FAKE16: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68] -0xfd,0x04,0x0a,0x68 -# GFX11-REAL16: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xfd,0x04,0x0b,0x69 0xfd,0x04,0x0b,0x69 +# GFX11-REAL16: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69] +0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00 # GFX11-REAL16: v_subrev_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00] # GFX11-FAKE16: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00] -0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00 -# GFX11-REAL16: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00] -# COM: TODO: GFX11-FAKE16: warning: invalid instruction encoding 0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00 0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00 +# GFX11-REAL16: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00] -# GFX11: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a] 0x01,0x05,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0a] 0xff,0x05,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0a] 0x01,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0a] 0x69,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0a] 0x6a,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0a] 0x6b,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0a] 0x7b,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0a] 0x7d,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0a] 0x7e,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0a] 0x7f,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0a] 0x7c,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0a] 0xc1,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0a] 0xf0,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0a] 0xfd,0x04,0x0a,0x0a +# GFX11: v_subrev_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0a] -# GFX11: v_subrev_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf +# GFX11: v_subrev_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf] -# GFX11: v_subrev_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4e] 0x01,0x05,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4e] 0xff,0x05,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4e] 0x01,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4e] 0x69,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4e] 0x6a,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4e] 0x6b,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4e] 0x7b,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4e] 0x7d,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4e] 0x7e,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4e] 0x7f,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4e] 0x7c,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4e] 0xc1,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4e] 0xf0,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4e] 0xfd,0x04,0x0a,0x4e +# GFX11: v_subrev_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4e] -# GFX11: v_subrev_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf +# GFX11: v_subrev_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf] -# GFX11: v_xnor_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3c] 0x01,0x05,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3c] 0xff,0x05,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3c] 0x01,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x3c] 0x69,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3c] 0x6a,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3c] 0x6b,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x3c] 0x7b,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x3c] 0x7d,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x3c] 0x7e,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x3c] 0x7f,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x3c] 0x7c,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x3c] 0xc1,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x3c] 0xf0,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x3c] 0xfd,0x04,0x0a,0x3c +# GFX11: v_xnor_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x3c] -# GFX11: v_xnor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf +# GFX11: v_xnor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf] -# GFX11: v_xor_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3a] 0x01,0x05,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3a] 0xff,0x05,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3a] 0x01,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x3a] 0x69,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3a] 0x6a,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3a] 0x6b,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x3a] 0x7b,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x3a] 0x7d,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x3a] 0x7e,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x3a] 0x7f,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x3a] 0x7c,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x3a] 0xc1,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x3a] 0xf0,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x3a] 0xfd,0x04,0x0a,0x3a +# GFX11: v_xor_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x3a] -# GFX11: v_xor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf +# GFX11: v_xor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt index eebf0cc13cee63009eda7a8447bc9ea38da7eeef..a8a40f883cc485c247eec2910b470205983744e4 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp16.txt @@ -1,1750 +1,1851 @@ -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s +; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,GFX11-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,GFX11-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,GFX11-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,GFX11-FAKE16 %s +0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff +0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff] -0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff +0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01 # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01] -0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01 +0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13 # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13] -0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13 +0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30 # W32: v_add_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30] # W64: v_add_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30] -0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30 -# GFX11: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff] -# GFX11: v_add_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01 +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01] -# GFX11: v_add_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13 +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13] -# GFX11: v_add_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30 +# GFX11-REAL16: v_add_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30] +# GFX11-FAKE16: v_add_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30] -# GFX11: v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff +# GFX11: v_add_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff] -# GFX11: v_add_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01 +# GFX11: v_add_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01] -# GFX11: v_add_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x06,0x01,0x60,0x01,0x13 +# GFX11: v_add_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x01,0x13] -# GFX11: v_add_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x07,0xff,0x6f,0xfd,0x30 +# GFX11: v_add_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xfd,0x30] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01 +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x4a,0x01,0x60,0x01,0x13 +# GFX11: v_add_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x01,0x13] -# GFX11: v_add_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x0d,0x30 +# GFX11: v_add_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x0d,0x30] -# GFX11: v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff +# GFX11: v_and_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff] -# GFX11: v_and_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01 +# GFX11: v_and_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01] -# GFX11: v_and_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x36,0x01,0x60,0x01,0x13 +# GFX11: v_and_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x01,0x13] -# GFX11: v_and_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x37,0xff,0x6f,0x0d,0x30 +# GFX11: v_and_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x0d,0x30] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01 +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x34,0x01,0x60,0x01,0x13 +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x01,0x13] -# GFX11: v_ashrrev_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x35,0xff,0x6f,0x0d,0x30 +# GFX11: v_ashrrev_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x0d,0x30] +0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff +0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff] -0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff +0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01 # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01] -0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01 +0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13 # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13] -0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13 +0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30 # W32: v_cndmask_b32_dpp v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30] # W64: v_cndmask_b32_dpp v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30] -0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30 +0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff # W32: v_cndmask_b32_dpp v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff] # W64: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff] -0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0xff +0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff # W32: v_cndmask_b32_dpp v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff] # W64: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff] -0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0xff +0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff # W32: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff] # W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff] -0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0xff -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01 +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x5e,0x01,0x60,0x01,0x13 +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x01,0x13] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xfd,0x30 +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xfd,0x30] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x04,0x01,0x50,0x01,0xff +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x50,0x01,0xff] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x04,0x01,0x5f,0x01,0x01 +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x5f,0x01,0x01] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x04,0x01,0x60,0x01,0x13 +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x60,0x01,0x13] -# GFX11: v_dot2acc_f32_f16_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x05,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x05,0xff,0x6f,0xfd,0x30 +# GFX11: v_dot2acc_f32_f16_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x05,0xff,0x6f,0xfd,0x30] -# GFX11: v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01 +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01] -# GFX11: v_fmac_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x6c,0x01,0x60,0x01,0x13 +# GFX11: v_fmac_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x60,0x01,0x13] -# GFX11: v_fmac_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30 +# GFX11: v_fmac_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30] -# GFX11: v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01 +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01] -# GFX11: v_fmac_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x56,0x01,0x60,0x01,0x13 +# GFX11: v_fmac_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x01,0x13] -# GFX11: v_fmac_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x57,0xff,0x6f,0xfd,0x30 +# GFX11: v_fmac_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xfd,0x30] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01 +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13 +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13] -# GFX11: v_ldexp_f16_dpp v127, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30] 0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30 +# GFX11-REAL16: v_ldexp_f16_dpp v127.l, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30] +# GFX11-FAKE16: v_ldexp_f16_dpp v127, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01 +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x30,0x01,0x60,0x01,0x13 +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x01,0x13] -# GFX11: v_lshlrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x31,0xff,0x6f,0x0d,0x30 +# GFX11: v_lshlrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x0d,0x30] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01 +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x32,0x01,0x60,0x01,0x13 +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x01,0x13] -# GFX11: v_lshrrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x33,0xff,0x6f,0x0d,0x30 +# GFX11: v_lshrrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x0d,0x30] -# GFX11: v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x72,0x01,0x50,0x01,0xff +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x50,0x01,0xff] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x50,0x01,0xff] -# GFX11: v_max_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x72,0x01,0x5f,0x01,0x01 +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x5f,0x01,0x01] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x5f,0x01,0x01] -# GFX11: v_max_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x72,0x01,0x60,0x01,0x13 +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x60,0x01,0x13] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x60,0x01,0x13] -# GFX11: v_max_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x72,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x72,0x7f,0x6f,0xfd,0x30 +# GFX11-REAL16: v_max_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x72,0x7f,0x6f,0xfd,0x30] +# GFX11-FAKE16: v_max_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x72,0x7f,0x6f,0xfd,0x30] -# GFX11: v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x20,0x01,0x50,0x01,0xff +# GFX11: v_max_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x50,0x01,0xff] -# GFX11: v_max_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x20,0x01,0x5f,0x01,0x01 +# GFX11: v_max_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x5f,0x01,0x01] -# GFX11: v_max_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x20,0x01,0x60,0x01,0x13 +# GFX11: v_max_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x60,0x01,0x13] -# GFX11: v_max_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x21,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x21,0xff,0x6f,0xfd,0x30 +# GFX11: v_max_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x21,0xff,0x6f,0xfd,0x30] -# GFX11: v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff +# GFX11: v_max_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff] -# GFX11: v_max_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01 +# GFX11: v_max_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01] -# GFX11: v_max_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x24,0x01,0x60,0x01,0x13 +# GFX11: v_max_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x01,0x13] -# GFX11: v_max_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x25,0xff,0x6f,0x0d,0x30 +# GFX11: v_max_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x0d,0x30] -# GFX11: v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff +# GFX11: v_max_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff] -# GFX11: v_max_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01 +# GFX11: v_max_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01] -# GFX11: v_max_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x28,0x01,0x60,0x01,0x13 +# GFX11: v_max_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x01,0x13] -# GFX11: v_max_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x29,0xff,0x6f,0x0d,0x30 +# GFX11: v_max_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x0d,0x30] -# GFX11: v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x74,0x01,0x50,0x01,0xff +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x50,0x01,0xff] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x50,0x01,0xff] -# GFX11: v_min_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x74,0x01,0x5f,0x01,0x01 +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x5f,0x01,0x01] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x5f,0x01,0x01] -# GFX11: v_min_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x74,0x01,0x60,0x01,0x13 +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x60,0x01,0x13] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x60,0x01,0x13] -# GFX11: v_min_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x74,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x74,0x7f,0x6f,0xfd,0x30 +# GFX11-REAL16: v_min_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x74,0x7f,0x6f,0xfd,0x30] +# GFX11-FAKE16: v_min_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x74,0x7f,0x6f,0xfd,0x30] -# GFX11: v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x1e,0x01,0x50,0x01,0xff +# GFX11: v_min_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x50,0x01,0xff] -# GFX11: v_min_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x1e,0x01,0x5f,0x01,0x01 +# GFX11: v_min_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x5f,0x01,0x01] -# GFX11: v_min_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x1e,0x01,0x60,0x01,0x13 +# GFX11: v_min_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x60,0x01,0x13] -# GFX11: v_min_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x1f,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x1f,0xff,0x6f,0xfd,0x30 +# GFX11: v_min_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x1f,0xff,0x6f,0xfd,0x30] -# GFX11: v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff +# GFX11: v_min_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff] -# GFX11: v_min_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01 +# GFX11: v_min_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01] -# GFX11: v_min_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x22,0x01,0x60,0x01,0x13 +# GFX11: v_min_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x01,0x13] -# GFX11: v_min_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x23,0xff,0x6f,0x0d,0x30 +# GFX11: v_min_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x0d,0x30] -# GFX11: v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff +# GFX11: v_min_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff] -# GFX11: v_min_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01 +# GFX11: v_min_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01] -# GFX11: v_min_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x26,0x01,0x60,0x01,0x13 +# GFX11: v_min_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x01,0x13] -# GFX11: v_min_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x27,0xff,0x6f,0x0d,0x30 +# GFX11: v_min_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x0d,0x30] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01 +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x0e,0x01,0x60,0x01,0x13 +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x01,0x13] -# GFX11: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xfd,0x30 +# GFX11: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xfd,0x30] -# GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff -# GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01 +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] -# GFX11: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13 +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13] -# GFX11: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30 +# GFX11-REAL16: v_mul_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30] +# GFX11-FAKE16: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30] -# GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff +# GFX11: v_mul_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01 +# GFX11: v_mul_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01] -# GFX11: v_mul_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x10,0x01,0x60,0x01,0x13 +# GFX11: v_mul_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x01,0x13] -# GFX11: v_mul_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x11,0xff,0x6f,0xfd,0x30 +# GFX11: v_mul_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xfd,0x30] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01 +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x14,0x01,0x60,0x01,0x13 +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x01,0x13] -# GFX11: v_mul_hi_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x15,0xff,0x6f,0x0d,0x30 +# GFX11: v_mul_hi_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x0d,0x30] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01 +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x18,0x01,0x60,0x01,0x13 +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x01,0x13] -# GFX11: v_mul_hi_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x19,0xff,0x6f,0x0d,0x30 +# GFX11: v_mul_hi_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x0d,0x30] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01 +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x12,0x01,0x60,0x01,0x13 +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x01,0x13] -# GFX11: v_mul_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x13,0xff,0x6f,0x0d,0x30 +# GFX11: v_mul_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x0d,0x30] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01 +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x16,0x01,0x60,0x01,0x13 +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x01,0x13] -# GFX11: v_mul_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x17,0xff,0x6f,0x0d,0x30 +# GFX11: v_mul_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x0d,0x30] -# GFX11: v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff +# GFX11: v_or_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff] -# GFX11: v_or_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01 +# GFX11: v_or_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01] -# GFX11: v_or_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x38,0x01,0x60,0x01,0x13 +# GFX11: v_or_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x01,0x13] -# GFX11: v_or_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x39,0xff,0x6f,0x0d,0x30 +# GFX11: v_or_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x0d,0x30] +0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff +0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff] -0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff +0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01 # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01] -0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01 +0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13 # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13] -0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13 +0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30 # W32: v_sub_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30] # W64: v_sub_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30] -0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30 -# GFX11: v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01 +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01] -# GFX11: v_sub_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13 +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13] -# GFX11: v_sub_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30 +# GFX11-REAL16: v_sub_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30] +# GFX11-FAKE16: v_sub_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30] -# GFX11: v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff +# GFX11: v_sub_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01 +# GFX11: v_sub_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01] -# GFX11: v_sub_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x08,0x01,0x60,0x01,0x13 +# GFX11: v_sub_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x01,0x13] -# GFX11: v_sub_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x09,0xff,0x6f,0xfd,0x30 +# GFX11: v_sub_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xfd,0x30] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01 +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x4c,0x01,0x60,0x01,0x13 +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x01,0x13] -# GFX11: v_sub_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x0d,0x30 +# GFX11: v_sub_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x0d,0x30] +0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff +0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff] -0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff +0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01 # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01] -0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01 +0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13 # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13] -0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13 +0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30 # W32: v_subrev_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30] # W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30] -0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30 -# GFX11: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01 +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01] -# GFX11: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13 +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13] -# GFX11: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30 +# GFX11-REAL16: v_subrev_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30] +# GFX11-FAKE16: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30] -# GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01 +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01] -# GFX11: v_subrev_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x0a,0x01,0x60,0x01,0x13 +# GFX11: v_subrev_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x01,0x13] -# GFX11: v_subrev_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xfd,0x30 +# GFX11: v_subrev_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xfd,0x30] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01 +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x4e,0x01,0x60,0x01,0x13 +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x01,0x13] -# GFX11: v_subrev_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x0d,0x30 +# GFX11: v_subrev_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x0d,0x30] -# GFX11: v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01 +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01] -# GFX11: v_xnor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x3c,0x01,0x60,0x01,0x13 +# GFX11: v_xnor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x01,0x13] -# GFX11: v_xnor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x0d,0x30 +# GFX11: v_xnor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x0d,0x30] -# GFX11: v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff +# GFX11: v_xor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01 +# GFX11: v_xor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01] -# GFX11: v_xor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x3a,0x01,0x60,0x01,0x13 +# GFX11: v_xor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x01,0x13] -# GFX11: v_xor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30 +# GFX11: v_xor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt index 5f1d4d4b33cbd104806eab172a42133288199ff9..a1d2c34f09f2b29f41925c3f3b2a52cce70402d1 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop2_dpp8.txt @@ -1,250 +1,267 @@ -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64 %s +; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,GFX11-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,GFX11-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W32,GFX11-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,W64,GFX11-FAKE16 %s +0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05 # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] -0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05 +0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00 # W32: v_add_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00] # W64: v_add_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00] -0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00 -# GFX11: v_add_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05 +# GFX11-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] +# GFX11-FAKE16: v_add_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] -# GFX11: v_add_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00 +# GFX11-REAL16: v_add_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00] +# GFX11-FAKE16: v_add_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00] -# GFX11: v_add_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05 +# GFX11: v_add_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05] -# GFX11: v_add_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00 +# GFX11: v_add_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00] -# GFX11: v_add_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05 +# GFX11: v_add_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05] -# GFX11: v_add_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00 +# GFX11: v_add_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00] -# GFX11: v_and_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05 +# GFX11: v_and_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05] -# GFX11: v_and_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x37,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x37,0xff,0x00,0x00,0x00 +# GFX11: v_and_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x37,0xff,0x00,0x00,0x00] -# GFX11: v_ashrrev_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05 +# GFX11: v_ashrrev_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05] -# GFX11: v_ashrrev_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x35,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x35,0xff,0x00,0x00,0x00 +# GFX11: v_ashrrev_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x35,0xff,0x00,0x00,0x00] +0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05 # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] -0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05 +0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00 # W32: v_cndmask_b32_dpp v255, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00] # W64: v_cndmask_b32_dpp v255, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00] -0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00 -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05 +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] -# GFX11: v_cvt_pk_rtz_f16_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00 +# GFX11: v_cvt_pk_rtz_f16_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00] -# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x04,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x04,0x01,0x77,0x39,0x05 +# GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x04,0x01,0x77,0x39,0x05] -# GFX11: v_dot2acc_f32_f16_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x05,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x05,0xff,0x00,0x00,0x00 +# GFX11: v_dot2acc_f32_f16_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x05,0xff,0x00,0x00,0x00] -# GFX11: v_fmac_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05 +# GFX11: v_fmac_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05] -# GFX11: v_fmac_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00 +# GFX11: v_fmac_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00] -# GFX11: v_fmac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05 +# GFX11: v_fmac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05] -# GFX11: v_fmac_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x57,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x57,0xff,0x00,0x00,0x00 +# GFX11: v_fmac_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x57,0xff,0x00,0x00,0x00] -# GFX11: v_ldexp_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05 +# GFX11-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] +# GFX11-FAKE16: v_ldexp_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] -# GFX11: v_ldexp_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00 +# GFX11-REAL16: v_ldexp_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00] +# GFX11-FAKE16: v_ldexp_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00] -# GFX11: v_lshlrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05 +# GFX11: v_lshlrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05] -# GFX11: v_lshlrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x31,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x31,0xff,0x00,0x00,0x00 +# GFX11: v_lshlrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x31,0xff,0x00,0x00,0x00] -# GFX11: v_lshrrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05 +# GFX11: v_lshrrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05] -# GFX11: v_lshrrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x33,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x33,0xff,0x00,0x00,0x00 +# GFX11: v_lshrrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x33,0xff,0x00,0x00,0x00] -# GFX11: v_max_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x72,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x72,0x01,0x77,0x39,0x05 +# GFX11-REAL16: v_max_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x72,0x01,0x77,0x39,0x05] +# GFX11-FAKE16: v_max_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x72,0x01,0x77,0x39,0x05] -# GFX11: v_max_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x72,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x72,0x7f,0x00,0x00,0x00 +# GFX11-REAL16: v_max_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x72,0x7f,0x00,0x00,0x00] +# GFX11-FAKE16: v_max_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x72,0x7f,0x00,0x00,0x00] -# GFX11: v_max_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x20,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x20,0x01,0x77,0x39,0x05 +# GFX11: v_max_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x20,0x01,0x77,0x39,0x05] -# GFX11: v_max_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x21,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x21,0xff,0x00,0x00,0x00 +# GFX11: v_max_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x21,0xff,0x00,0x00,0x00] -# GFX11: v_max_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05 +# GFX11: v_max_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05] -# GFX11: v_max_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x25,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x25,0xff,0x00,0x00,0x00 +# GFX11: v_max_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x25,0xff,0x00,0x00,0x00] -# GFX11: v_max_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05 +# GFX11: v_max_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05] -# GFX11: v_max_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x29,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x29,0xff,0x00,0x00,0x00 +# GFX11: v_max_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x29,0xff,0x00,0x00,0x00] -# GFX11: v_min_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x74,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x74,0x01,0x77,0x39,0x05 +# GFX11-REAL16: v_min_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x74,0x01,0x77,0x39,0x05] +# GFX11-FAKE16: v_min_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x74,0x01,0x77,0x39,0x05] -# GFX11: v_min_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x74,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x74,0x7f,0x00,0x00,0x00 +# GFX11-REAL16: v_min_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x74,0x7f,0x00,0x00,0x00] +# GFX11-FAKE16: v_min_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x74,0x7f,0x00,0x00,0x00] -# GFX11: v_min_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x1e,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x1e,0x01,0x77,0x39,0x05 +# GFX11: v_min_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x1e,0x01,0x77,0x39,0x05] -# GFX11: v_min_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x1f,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x1f,0xff,0x00,0x00,0x00 +# GFX11: v_min_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x1f,0xff,0x00,0x00,0x00] -# GFX11: v_min_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05 +# GFX11: v_min_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05] -# GFX11: v_min_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x23,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x23,0xff,0x00,0x00,0x00 +# GFX11: v_min_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x23,0xff,0x00,0x00,0x00] -# GFX11: v_min_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05 +# GFX11: v_min_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05] -# GFX11: v_min_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x27,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x27,0xff,0x00,0x00,0x00 +# GFX11: v_min_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x27,0xff,0x00,0x00,0x00] -# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05 +# GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] -# GFX11: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00 +# GFX11: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] -# GFX11: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05 +# GFX11-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] +# GFX11-FAKE16: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] -# GFX11: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00 +# GFX11-REAL16: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] +# GFX11-FAKE16: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] -# GFX11: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05 +# GFX11: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] -# GFX11: v_mul_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x11,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x11,0xff,0x00,0x00,0x00 +# GFX11: v_mul_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x11,0xff,0x00,0x00,0x00] -# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05 +# GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05] -# GFX11: v_mul_hi_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x15,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x15,0xff,0x00,0x00,0x00 +# GFX11: v_mul_hi_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x15,0xff,0x00,0x00,0x00] -# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05 +# GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05] -# GFX11: v_mul_hi_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x19,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x19,0xff,0x00,0x00,0x00 +# GFX11: v_mul_hi_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x19,0xff,0x00,0x00,0x00] -# GFX11: v_mul_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05 +# GFX11: v_mul_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05] -# GFX11: v_mul_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x13,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x13,0xff,0x00,0x00,0x00 +# GFX11: v_mul_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x13,0xff,0x00,0x00,0x00] -# GFX11: v_mul_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05 +# GFX11: v_mul_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05] -# GFX11: v_mul_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x17,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x17,0xff,0x00,0x00,0x00 +# GFX11: v_mul_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x17,0xff,0x00,0x00,0x00] -# GFX11: v_or_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05 +# GFX11: v_or_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05] -# GFX11: v_or_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x39,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x39,0xff,0x00,0x00,0x00 +# GFX11: v_or_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x39,0xff,0x00,0x00,0x00] +0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05 # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] -0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05 +0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00 # W32: v_sub_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00] # W64: v_sub_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00] -0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00 -# GFX11: v_sub_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05 +# GFX11-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] +# GFX11-FAKE16: v_sub_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] -# GFX11: v_sub_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00 +# GFX11-REAL16: v_sub_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00] +# GFX11-FAKE16: v_sub_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00] -# GFX11: v_sub_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05 +# GFX11: v_sub_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05] -# GFX11: v_sub_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x09,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x09,0xff,0x00,0x00,0x00 +# GFX11: v_sub_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x09,0xff,0x00,0x00,0x00] -# GFX11: v_sub_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05 +# GFX11: v_sub_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05] -# GFX11: v_sub_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00 +# GFX11: v_sub_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00] +0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05 # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] -0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05 +0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00 # W32: v_subrev_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00] # W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00] -0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00 -# GFX11: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05 +# GFX11-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] +# GFX11-FAKE16: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] -# GFX11: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00 +# GFX11-REAL16: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00] +# GFX11-FAKE16: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00] -# GFX11: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05 +# GFX11: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05] -# GFX11: v_subrev_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00 +# GFX11: v_subrev_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00] -# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05 +# GFX11: v_subrev_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05] -# GFX11: v_subrev_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00 +# GFX11: v_subrev_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00] -# GFX11: v_xnor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05 +# GFX11: v_xnor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05] -# GFX11: v_xnor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00 +# GFX11: v_xnor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00] -# GFX11: v_xor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05 +# GFX11: v_xor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05] -# GFX11: v_xor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00 +# GFX11: v_xor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt index 08e9bef8cf67851c38d1c1d6f1b23f81cd35ac6d..233c2e1b9d083b8c424faea7acfb2149309da9ad 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt @@ -160,6 +160,12 @@ # GFX12: image_load v[4:7], [v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00] 0x01,0x00,0xc0,0xd3,0x04,0x08,0x00,0x00,0x01,0x00,0x00,0x00 +# GFX12: image_load v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] +0x02,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00 + +# GFX12: image_load v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] +0x07,0x00,0xc0,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00 + # GFX12: image_load_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0xc0,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00] 0x00,0x40,0xc0,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00 @@ -409,6 +415,12 @@ # GFX12: image_store v[1:4], [v2, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] 0x01,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00 +# GFX12: image_store v[1:4], [v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] +0x02,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00 + +# GFX12: image_store v[1:4], [v3, v2, v1, v0], s[4:11] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] +0x07,0x80,0xc1,0xd3,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00 + # GFX12: image_store_mip v[252:255], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xc1,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00] 0x00,0xc0,0xc1,0xd3,0xfc,0x00,0x00,0x00,0x00,0x01,0x00,0x00 @@ -568,6 +580,12 @@ # GFX12: image_atomic_swap v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] 0x01,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00 +# GFX12: image_atomic_swap v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] +0x02,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00 + +# GFX12: image_atomic_swap v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] +0x07,0x80,0x42,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00 + # GFX12: image_atomic_cmpswap v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0xc0,0xc2,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] 0x00,0xc0,0xc2,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 @@ -625,6 +643,12 @@ # GFX12: image_atomic_add_uint v1, [v2, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; encoding: [0x01,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00] 0x01,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x00,0x00,0x00 +# GFX12: image_atomic_add_uint v1, [v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_3D ; encoding: [0x02,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00] +0x02,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x02,0x01,0x00,0x00 + +# GFX12: image_atomic_add_uint v1, [v3, v2, v1, v0], s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; encoding: [0x07,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00] +0x07,0x00,0x43,0xd0,0x01,0x08,0x00,0x00,0x03,0x02,0x01,0x00 + # GFX12: image_atomic_sub_uint v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x40,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00] 0x00,0x40,0x43,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt index 673db0664fc6abaabfb6b2fe0de46daa4967e941..1276d898160b33e49af754a8a38d1a3b8203520e 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt @@ -1,2228 +1,2336 @@ -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s +; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,GFX12-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,GFX12-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,GFX12-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,GFX12-FAKE16 %s +0x01,0x05,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x40] -0x01,0x05,0x0a,0x40 +0xff,0x05,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x40] -0xff,0x05,0x0a,0x40 +0x01,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x40] -0x01,0x04,0x0a,0x40 +0x69,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x40] -0x69,0x04,0x0a,0x40 +0x6a,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x40] -0x6a,0x04,0x0a,0x40 +0x6b,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x40] -0x6b,0x04,0x0a,0x40 +0x7b,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x40] -0x7b,0x04,0x0a,0x40 +0x7d,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x40] -0x7d,0x04,0x0a,0x40 +0x7e,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x40] -0x7e,0x04,0x0a,0x40 +0x7f,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x40] -0x7f,0x04,0x0a,0x40 +0x7c,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x40] -0x7c,0x04,0x0a,0x40 +0xc1,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x40] -0xc1,0x04,0x0a,0x40 +0xf0,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x40] -0xf0,0x04,0x0a,0x40 +0xfd,0x04,0x0a,0x40 # W32: v_add_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x40] # W64: v_add_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x40] -0xfd,0x04,0x0a,0x40 +0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf # W32: v_add_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf] # W64: v_add_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf] -0xff,0xfe,0xff,0x41,0x56,0x34,0x12,0xaf -# GFX12: v_add_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x64] 0x01,0x05,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x64] 0x7f,0x05,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x64] 0x01,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x64] 0x69,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x64] 0x6a,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x64] 0x6b,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x64] 0x7b,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x64] 0x7d,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x64] 0x7e,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x64] 0x7f,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x64] 0x7c,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x64] 0xc1,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x64] 0xf0,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x64] 0xfd,0x04,0x0a,0x64 +# GFX12-REAL16: v_add_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x64] +# GFX12-FAKE16: v_add_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x64] -# GFX12: v_add_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00 +# GFX12-REAL16: v_add_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00] +# GFX12-FAKE16: v_add_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x64,0x0b,0xfe,0x00,0x00] -# GFX12: v_add_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x06] 0x01,0x05,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x06] 0xff,0x05,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x06] 0x01,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x06] 0x69,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x06] 0x6a,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x06] 0x6b,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x06] 0x7b,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x06] 0x7d,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x06] 0x7e,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x06] 0x7f,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x06] 0x7c,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x06] 0xc1,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x06] 0xf0,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x06] 0xfd,0x04,0x0a,0x06 +# GFX12: v_add_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x06] -# GFX12: v_add_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf +# GFX12: v_add_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x07,0x56,0x34,0x12,0xaf] -# GFX12: v_add_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x04] 0x01,0x07,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x04] 0xfe,0x05,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x04] 0x00,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x04] 0x68,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], vcc, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x04] 0x6a,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], vcc, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x04] 0x7a,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], exec, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x04] 0x7e,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], exec, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x04] 0x7c,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x04] 0xc1,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x04] 0xf0,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x04] 0xfd,0x04,0x0a,0x04 +# GFX12: v_add_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x04] -# GFX12: v_add_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x05,0x56,0x34,0x12,0xaf] 0xff,0xfc,0xfd,0x05,0x56,0x34,0x12,0xaf +# GFX12: v_add_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x05,0x56,0x34,0x12,0xaf] -# GFX12: v_add_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4a] 0x01,0x05,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4a] 0xff,0x05,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4a] 0x01,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4a] 0x69,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4a] 0x6a,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4a] 0x6b,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4a] 0x7b,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4a] 0x7d,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4a] 0x7e,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4a] 0x7f,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4a] 0x7c,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4a] 0xc1,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4a] 0xf0,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4a] 0xfd,0x04,0x0a,0x4a +# GFX12: v_add_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4a] -# GFX12: v_add_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf +# GFX12: v_add_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4b,0x56,0x34,0x12,0xaf] -# GFX12: v_and_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x36] 0x01,0x05,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x36] 0xff,0x05,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x36] 0x01,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x36] 0x69,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x36] 0x6a,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x36] 0x6b,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x36] 0x7b,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x36] 0x7d,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x36] 0x7e,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x36] 0x7f,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x36] 0x7c,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x36] 0xc1,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x36] 0xf0,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x36] 0xfd,0x04,0x0a,0x36 +# GFX12: v_and_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x36] -# GFX12: v_and_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf +# GFX12: v_and_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x37,0x56,0x34,0x12,0xaf] -# GFX12: v_ashrrev_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x34] 0x01,0x05,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x34] 0xff,0x05,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x34] 0x01,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x34] 0x69,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x34] 0x6a,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x34] 0x6b,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x34] 0x7b,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x34] 0x7d,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x34] 0x7e,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x34] 0x7f,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x34] 0x7c,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x34] 0xc1,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x34] 0xf0,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x34] 0xfd,0x04,0x0a,0x34 +# GFX12: v_ashrrev_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x34] -# GFX12: v_ashrrev_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf +# GFX12: v_ashrrev_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x35,0x56,0x34,0x12,0xaf] -# W32: v_cndmask_b32_e32 v5, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x02] 0x01,0x05,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x02] 0xff,0x05,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x02] 0x01,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x02] 0x69,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x02] 0x6a,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x02] 0x6b,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x02] 0x7b,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x02] 0x7d,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x02] 0x7e,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x02] 0x7f,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x02] 0x7c,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x02] 0xc1,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x02] 0xf0,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x02] -# W32: v_cndmask_b32_e32 v5, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x02] -# W64: v_cndmask_b32_e32 v5, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x02] 0xfd,0x04,0x0a,0x02 +# W32: v_cndmask_b32_e32 v5, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x02] +# W64: v_cndmask_b32_e32 v5, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x02] +0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf # W32: v_cndmask_b32_e32 v255, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf] # W64: v_cndmask_b32_e32 v255, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf] -0xff,0xfe,0xff,0x03,0x56,0x34,0x12,0xaf -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x5e] 0x01,0x05,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x5e] 0xff,0x05,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x5e] 0x01,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x5e] 0x69,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x5e] 0x6a,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x5e] 0x6b,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x5e] 0x7b,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x5e] 0x7d,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x5e] 0x7e,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x5e] 0x7f,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x5e] 0x7c,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x5e] 0xc1,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x5e] 0xf0,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x5e] 0xfd,0x04,0x0a,0x5e +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x5e] -# GFX12: v_cvt_pk_rtz_f16_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf +# GFX12: v_cvt_pk_rtz_f16_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x5f,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f16 v5, v1, v2, 0xfe0b ; encoding: [0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, v1, v2, 0xfe0b ; encoding: [0x01,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, v127, v2, 0xfe0b ; encoding: [0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, v127, v2, 0xfe0b ; encoding: [0x7f,0x05,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, s1, v2, 0xfe0b ; encoding: [0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, s1, v2, 0xfe0b ; encoding: [0x01,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, s105, v2, 0xfe0b ; encoding: [0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, s105, v2, 0xfe0b ; encoding: [0x69,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, vcc_lo, v2, 0xfe0b ; encoding: [0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, vcc_lo, v2, 0xfe0b ; encoding: [0x6a,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, vcc_hi, v2, 0xfe0b ; encoding: [0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, vcc_hi, v2, 0xfe0b ; encoding: [0x6b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, ttmp15, v2, 0xfe0b ; encoding: [0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, ttmp15, v2, 0xfe0b ; encoding: [0x7b,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, m0, v2, 0xfe0b ; encoding: [0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, m0, v2, 0xfe0b ; encoding: [0x7d,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, exec_lo, v2, 0xfe0b ; encoding: [0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, exec_lo, v2, 0xfe0b ; encoding: [0x7e,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, exec_hi, v2, 0xfe0b ; encoding: [0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, exec_hi, v2, 0xfe0b ; encoding: [0x7f,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, null, v2, 0xfe0b ; encoding: [0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, null, v2, 0xfe0b ; encoding: [0x7c,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, -1, v2, 0xfe0b ; encoding: [0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, -1, v2, 0xfe0b ; encoding: [0xc1,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, 0.5, v2, 0xfe0b ; encoding: [0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, 0.5, v2, 0xfe0b ; encoding: [0xf0,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v5, src_scc, v2, 0xfe0b ; encoding: [0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] 0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v5, src_scc, v2, 0xfe0b ; encoding: [0xfd,0x04,0x0a,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f16 v127, 0xfe0b, v127, 0xfe0b ; encoding: [0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmaak_f16 v127, 0xfe0b, v127, 0xfe0b ; encoding: [0xff,0xfe,0xfe,0x70,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmaak_f32 v5, v1, v2, 0xaf123456 ; encoding: [0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, v1, v2, 0xaf123456 ; encoding: [0x01,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, v255, v2, 0xaf123456 ; encoding: [0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, v255, v2, 0xaf123456 ; encoding: [0xff,0x05,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, s1, v2, 0xaf123456 ; encoding: [0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, s1, v2, 0xaf123456 ; encoding: [0x01,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, s105, v2, 0xaf123456 ; encoding: [0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, s105, v2, 0xaf123456 ; encoding: [0x69,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, vcc_lo, v2, 0xaf123456 ; encoding: [0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, vcc_lo, v2, 0xaf123456 ; encoding: [0x6a,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, vcc_hi, v2, 0xaf123456 ; encoding: [0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, vcc_hi, v2, 0xaf123456 ; encoding: [0x6b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, ttmp15, v2, 0xaf123456 ; encoding: [0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, ttmp15, v2, 0xaf123456 ; encoding: [0x7b,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, m0, v2, 0xaf123456 ; encoding: [0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, m0, v2, 0xaf123456 ; encoding: [0x7d,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, exec_lo, v2, 0xaf123456 ; encoding: [0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, exec_lo, v2, 0xaf123456 ; encoding: [0x7e,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, exec_hi, v2, 0xaf123456 ; encoding: [0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, exec_hi, v2, 0xaf123456 ; encoding: [0x7f,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, null, v2, 0xaf123456 ; encoding: [0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, null, v2, 0xaf123456 ; encoding: [0x7c,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, -1, v2, 0xaf123456 ; encoding: [0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, -1, v2, 0xaf123456 ; encoding: [0xc1,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, 0.5, v2, 0xaf123456 ; encoding: [0xf0,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v5, src_scc, v2, 0xaf123456 ; encoding: [0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] 0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v5, src_scc, v2, 0xaf123456 ; encoding: [0xfd,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf] -# GFX12: v_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 ; encoding: [0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf +# GFX12: v_fmaak_f32 v255, 0xaf123456, v255, 0xaf123456 ; encoding: [0xff,0xfe,0xff,0x5b,0x56,0x34,0x12,0xaf] -# GFX12: v_fmac_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6c] 0x01,0x05,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6c] 0x7f,0x05,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6c] 0x01,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6c] 0x69,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6c] 0x6a,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6c] 0x6b,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6c] 0x7b,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6c] 0x7d,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6c] 0x7e,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6c] 0x7f,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6c] 0x7c,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6c] 0xc1,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6c] 0xf0,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6c] 0xfd,0x04,0x0a,0x6c +# GFX12: v_fmac_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6c] -# GFX12: v_fmac_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmac_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6c,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmac_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x56] 0x01,0x05,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x56] 0xff,0x05,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x56] 0x01,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x56] 0x69,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x56] 0x6a,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x56] 0x6b,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x56] 0x7b,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x56] 0x7d,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x56] 0x7e,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x56] 0x7f,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x56] 0x7c,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x56] 0xc1,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x56] 0xf0,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x56] 0xfd,0x04,0x0a,0x56 +# GFX12: v_fmac_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x56] -# GFX12: v_fmac_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf +# GFX12: v_fmac_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x57,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f16 v5, v1, 0xfe0b, v3 ; encoding: [0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, v1, 0xfe0b, v3 ; encoding: [0x01,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, v127, 0xfe0b, v3 ; encoding: [0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, v127, 0xfe0b, v3 ; encoding: [0x7f,0x07,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, s1, 0xfe0b, v3 ; encoding: [0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, s1, 0xfe0b, v3 ; encoding: [0x01,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, s105, 0xfe0b, v3 ; encoding: [0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, s105, 0xfe0b, v3 ; encoding: [0x69,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, vcc_lo, 0xfe0b, v3 ; encoding: [0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, vcc_lo, 0xfe0b, v3 ; encoding: [0x6a,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, vcc_hi, 0xfe0b, v3 ; encoding: [0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, vcc_hi, 0xfe0b, v3 ; encoding: [0x6b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, ttmp15, 0xfe0b, v3 ; encoding: [0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, ttmp15, 0xfe0b, v3 ; encoding: [0x7b,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, m0, 0xfe0b, v3 ; encoding: [0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, m0, 0xfe0b, v3 ; encoding: [0x7d,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, exec_lo, 0xfe0b, v3 ; encoding: [0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, exec_lo, 0xfe0b, v3 ; encoding: [0x7e,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, exec_hi, 0xfe0b, v3 ; encoding: [0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, exec_hi, 0xfe0b, v3 ; encoding: [0x7f,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, null, 0xfe0b, v3 ; encoding: [0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, null, 0xfe0b, v3 ; encoding: [0x7c,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, -1, 0xfe0b, v3 ; encoding: [0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, -1, 0xfe0b, v3 ; encoding: [0xc1,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, 0.5, 0xfe0b, v3 ; encoding: [0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, 0.5, 0xfe0b, v3 ; encoding: [0xf0,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v5, src_scc, 0xfe0b, v3 ; encoding: [0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] 0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v5, src_scc, 0xfe0b, v3 ; encoding: [0xfd,0x06,0x0a,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f16 v127, 0xfe0b, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00 +# GFX12: v_fmamk_f16 v127, 0xfe0b, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6e,0x0b,0xfe,0x00,0x00] -# GFX12: v_fmamk_f32 v5, v1, 0xaf123456, v3 ; encoding: [0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, v1, 0xaf123456, v3 ; encoding: [0x01,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, v255, 0xaf123456, v3 ; encoding: [0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] 0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, v255, 0xaf123456, v3 ; encoding: [0xff,0x07,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, s1, 0xaf123456, v3 ; encoding: [0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, s1, 0xaf123456, v3 ; encoding: [0x01,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, s105, 0xaf123456, v3 ; encoding: [0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, s105, 0xaf123456, v3 ; encoding: [0x69,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, vcc_lo, 0xaf123456, v3 ; encoding: [0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, vcc_lo, 0xaf123456, v3 ; encoding: [0x6a,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, vcc_hi, 0xaf123456, v3 ; encoding: [0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, vcc_hi, 0xaf123456, v3 ; encoding: [0x6b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, ttmp15, 0xaf123456, v3 ; encoding: [0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, ttmp15, 0xaf123456, v3 ; encoding: [0x7b,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, m0, 0xaf123456, v3 ; encoding: [0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, m0, 0xaf123456, v3 ; encoding: [0x7d,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, exec_lo, 0xaf123456, v3 ; encoding: [0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, exec_lo, 0xaf123456, v3 ; encoding: [0x7e,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, exec_hi, 0xaf123456, v3 ; encoding: [0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, exec_hi, 0xaf123456, v3 ; encoding: [0x7f,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, null, 0xaf123456, v3 ; encoding: [0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, null, 0xaf123456, v3 ; encoding: [0x7c,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, -1, 0xaf123456, v3 ; encoding: [0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, -1, 0xaf123456, v3 ; encoding: [0xc1,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, 0.5, 0xaf123456, v3 ; encoding: [0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, 0.5, 0xaf123456, v3 ; encoding: [0xf0,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v5, src_scc, 0xaf123456, v3 ; encoding: [0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] 0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v5, src_scc, 0xaf123456, v3 ; encoding: [0xfd,0x06,0x0a,0x58,0x56,0x34,0x12,0xaf] -# GFX12: v_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf +# GFX12: v_fmamk_f32 v255, 0xaf123456, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x59,0x56,0x34,0x12,0xaf] -# GFX12: v_ldexp_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x76] 0x01,0x05,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x76] 0x7f,0x05,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x76] 0x01,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x76] 0x69,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x76] 0x6a,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x76] 0x6b,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x76] 0x7b,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x76] 0x7d,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x76] 0x7e,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x76] 0x7f,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x76] 0x7c,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x76] 0xc1,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x76] 0xf0,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x76] 0xfd,0x04,0x0a,0x76 +# GFX12-REAL16: v_ldexp_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x76] +# GFX12-FAKE16: v_ldexp_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x76] -# GFX12: v_ldexp_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00 +# GFX12-REAL16: v_ldexp_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] +# GFX12-FAKE16: v_ldexp_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x76,0x0b,0xfe,0x00,0x00] -# GFX12: v_lshlrev_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x30] 0x01,0x05,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x30] 0xff,0x05,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x30] 0x01,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x30] 0x69,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x30] 0x6a,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x30] 0x6b,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x30] 0x7b,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x30] 0x7d,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x30] 0x7e,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x30] 0x7f,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x30] 0x7c,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x30] 0xc1,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x30] 0xf0,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x30] 0xfd,0x04,0x0a,0x30 +# GFX12: v_lshlrev_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x30] -# GFX12: v_lshlrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf +# GFX12: v_lshlrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x31,0x56,0x34,0x12,0xaf] -# GFX12: v_lshlrev_b64_e32 v[5:6], v1, v[3:4] ; encoding: [0x01,0x07,0x0a,0x3e] 0x01,0x07,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], v1, v[3:4] ; encoding: [0x01,0x07,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], v255, v[2:3] ; encoding: [0xff,0x05,0x0a,0x3e] 0xff,0x05,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], v255, v[2:3] ; encoding: [0xff,0x05,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], s1, v[2:3] ; encoding: [0x01,0x04,0x0a,0x3e] 0x01,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], s1, v[2:3] ; encoding: [0x01,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], s105, v[2:3] ; encoding: [0x69,0x04,0x0a,0x3e] 0x69,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], s105, v[2:3] ; encoding: [0x69,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], vcc_lo, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x3e] 0x6a,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], vcc_lo, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], vcc_hi, v[2:3] ; encoding: [0x6b,0x04,0x0a,0x3e] 0x6b,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], vcc_hi, v[2:3] ; encoding: [0x6b,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], ttmp15, v[2:3] ; encoding: [0x7b,0x04,0x0a,0x3e] 0x7b,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], ttmp15, v[2:3] ; encoding: [0x7b,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], exec_lo, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x3e] 0x7e,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], exec_lo, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], exec_hi, v[2:3] ; encoding: [0x7f,0x04,0x0a,0x3e] 0x7f,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], exec_hi, v[2:3] ; encoding: [0x7f,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x3e] 0x7c,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x3e] 0xc1,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x3e] 0xf0,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x3e] 0xfd,0x04,0x0a,0x3e +# GFX12: v_lshlrev_b64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x3e] -# GFX12: v_lshlrev_b64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x3f,0x56,0x34,0x12,0xaf] 0xff,0xfc,0xfd,0x3f,0x56,0x34,0x12,0xaf +# GFX12: v_lshlrev_b64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x3f,0x56,0x34,0x12,0xaf] -# GFX12: v_lshrrev_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x32] 0x01,0x05,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x32] 0xff,0x05,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x32] 0x01,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x32] 0x69,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x32] 0x6a,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x32] 0x6b,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x32] 0x7b,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x32] 0x7d,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x32] 0x7e,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x32] 0x7f,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x32] 0x7c,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x32] 0xc1,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x32] 0xf0,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x32] 0xfd,0x04,0x0a,0x32 +# GFX12: v_lshrrev_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x32] -# GFX12: v_lshrrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf +# GFX12: v_lshrrev_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x33,0x56,0x34,0x12,0xaf] -# GFX12: v_max_num_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x62] 0x01,0x05,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x62] 0x7f,0x05,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x62] 0x01,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x62] 0x69,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x62] 0x6a,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x62] 0x6b,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x62] 0x7b,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x62] 0x7d,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x62] 0x7e,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x62] 0x7f,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x62] 0x7c,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x62] 0xc1,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x62] 0xf0,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x62] 0xfd,0x04,0x0a,0x62 +# GFX12-REAL16: v_max_num_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x62] +# GFX12-FAKE16: v_max_num_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x62] -# GFX12: v_max_num_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x62,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x62,0x0b,0xfe,0x00,0x00 +# GFX12-REAL16: v_max_num_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x62,0x0b,0xfe,0x00,0x00] +# GFX12-FAKE16: v_max_num_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x62,0x0b,0xfe,0x00,0x00] -# GFX12: v_max_num_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x2c] 0x01,0x05,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x2c] 0xff,0x05,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x2c] 0x01,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x2c] 0x69,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x2c] 0x6a,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x2c] 0x6b,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x2c] 0x7b,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x2c] 0x7d,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x2c] 0x7e,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x2c] 0x7f,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x2c] 0x7c,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x2c] 0xc1,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x2c] 0xf0,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x2c] 0xfd,0x04,0x0a,0x2c +# GFX12: v_max_num_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x2c] -# GFX12: v_max_num_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x2d,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x2d,0x56,0x34,0x12,0xaf +# GFX12: v_max_num_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x2d,0x56,0x34,0x12,0xaf] -# GFX12: v_max_num_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x1c] 0x01,0x07,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x1c] 0xfe,0x05,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x1c] 0x00,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x1c] 0x68,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], vcc, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x1c] 0x6a,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], vcc, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x1c] 0x7a,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], exec, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x1c] 0x7e,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], exec, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x1c] 0x7c,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x1c] 0xc1,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x1c] 0xf0,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x1c] 0xfd,0x04,0x0a,0x1c +# GFX12: v_max_num_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x1c] -# GFX12: v_max_num_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x1d,0x56,0x34,0x12,0xaf] 0xff,0xfc,0xfd,0x1d,0x56,0x34,0x12,0xaf +# GFX12: v_max_num_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x1d,0x56,0x34,0x12,0xaf] -# GFX12: v_max_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x24] 0x01,0x05,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x24] 0xff,0x05,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x24] 0x01,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x24] 0x69,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x24] 0x6a,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x24] 0x6b,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x24] 0x7b,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x24] 0x7d,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x24] 0x7e,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x24] 0x7f,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x24] 0x7c,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x24] 0xc1,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x24] 0xf0,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x24] 0xfd,0x04,0x0a,0x24 +# GFX12: v_max_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x24] -# GFX12: v_max_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf +# GFX12: v_max_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x25,0x56,0x34,0x12,0xaf] -# GFX12: v_max_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x28] 0x01,0x05,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x28] 0xff,0x05,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x28] 0x01,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x28] 0x69,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x28] 0x6a,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x28] 0x6b,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x28] 0x7b,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x28] 0x7d,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x28] 0x7e,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x28] 0x7f,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x28] 0x7c,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x28] 0xc1,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x28] 0xf0,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x28] 0xfd,0x04,0x0a,0x28 +# GFX12: v_max_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x28] -# GFX12: v_max_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf +# GFX12: v_max_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x29,0x56,0x34,0x12,0xaf] -# GFX12: v_min_num_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x60] 0x01,0x05,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x60] 0x7f,0x05,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x60] 0x01,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x60] 0x69,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x60] 0x6a,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x60] 0x6b,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x60] 0x7b,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x60] 0x7d,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x60] 0x7e,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x60] 0x7f,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x60] 0x7c,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x60] 0xc1,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x60] 0xf0,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x60] 0xfd,0x04,0x0a,0x60 +# GFX12-REAL16: v_min_num_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x60] +# GFX12-FAKE16: v_min_num_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x60] -# GFX12: v_min_num_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x60,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x60,0x0b,0xfe,0x00,0x00 +# GFX12-REAL16: v_min_num_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x60,0x0b,0xfe,0x00,0x00] +# GFX12-FAKE16: v_min_num_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x60,0x0b,0xfe,0x00,0x00] -# GFX12: v_min_num_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x2a] 0x01,0x05,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x2a] 0xff,0x05,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x2a] 0x01,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x2a] 0x69,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x2a] 0x6a,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x2a] 0x6b,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x2a] 0x7b,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x2a] 0x7d,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x2a] 0x7e,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x2a] 0x7f,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x2a] 0x7c,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x2a] 0xc1,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x2a] 0xf0,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x2a] 0xfd,0x04,0x0a,0x2a +# GFX12: v_min_num_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x2a] -# GFX12: v_min_num_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x2b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x2b,0x56,0x34,0x12,0xaf +# GFX12: v_min_num_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x2b,0x56,0x34,0x12,0xaf] -# GFX12: v_min_num_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x1a] 0x01,0x07,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x1a] 0xfe,0x05,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x1a] 0x00,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x1a] 0x68,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], vcc, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x1a] 0x6a,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], vcc, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x1a] 0x7a,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], exec, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x1a] 0x7e,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], exec, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x1a] 0x7c,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x1a] 0xc1,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x1a] 0xf0,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x1a] 0xfd,0x04,0x0a,0x1a +# GFX12: v_min_num_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x1a] -# GFX12: v_min_num_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x1b,0x56,0x34,0x12,0xaf] 0xff,0xfc,0xfd,0x1b,0x56,0x34,0x12,0xaf +# GFX12: v_min_num_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x1b,0x56,0x34,0x12,0xaf] -# GFX12: v_min_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x22] 0x01,0x05,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x22] 0xff,0x05,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x22] 0x01,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x22] 0x69,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x22] 0x6a,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x22] 0x6b,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x22] 0x7b,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x22] 0x7d,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x22] 0x7e,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x22] 0x7f,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x22] 0x7c,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x22] 0xc1,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x22] 0xf0,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x22] 0xfd,0x04,0x0a,0x22 +# GFX12: v_min_i32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x22] -# GFX12: v_min_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf +# GFX12: v_min_i32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x23,0x56,0x34,0x12,0xaf] -# GFX12: v_min_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x26] 0x01,0x05,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x26] 0xff,0x05,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x26] 0x01,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x26] 0x69,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x26] 0x6a,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x26] 0x6b,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x26] 0x7b,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x26] 0x7d,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x26] 0x7e,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x26] 0x7f,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x26] 0x7c,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x26] 0xc1,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x26] 0xf0,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x26] 0xfd,0x04,0x0a,0x26 +# GFX12: v_min_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x26] -# GFX12: v_min_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf +# GFX12: v_min_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x27,0x56,0x34,0x12,0xaf] -# GFX12: v_mul_dx9_zero_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0e] 0x01,0x05,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0e] 0xff,0x05,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0e] 0x01,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0e] 0x69,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0e] 0x6a,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0e] 0x6b,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0e] 0x7b,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0e] 0x7d,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0e] 0x7e,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0e] 0x7f,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0e] 0x7c,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0e] 0xc1,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0e] 0xf0,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0e] 0xfd,0x04,0x0a,0x0e +# GFX12: v_mul_dx9_zero_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0e] -# GFX12: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf +# GFX12: v_mul_dx9_zero_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0f,0x56,0x34,0x12,0xaf] -# GFX12: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6a] 0x01,0x05,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6a] 0x7f,0x05,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6a] 0x01,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6a] 0x69,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6a] 0x6a,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6a] 0x6b,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6a] 0x7b,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6a] 0x7d,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6a] 0x7e,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6a] 0x7f,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6a] 0x7c,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6a] 0xc1,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6a] 0xf0,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6a] 0xfd,0x04,0x0a,0x6a +# GFX12-REAL16: v_mul_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x6a] +# GFX12-FAKE16: v_mul_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x6a] -# GFX12: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00 +# GFX12-REAL16: v_mul_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] +# GFX12-FAKE16: v_mul_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x6a,0x0b,0xfe,0x00,0x00] -# GFX12: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10] 0x01,0x05,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x10] 0xff,0x05,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x10] 0x01,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x10] 0x69,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x10] 0x6a,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x10] 0x6b,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x10] 0x7b,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x10] 0x7d,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x10] 0x7e,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x10] 0x7f,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x10] 0x7c,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x10] 0xc1,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x10] 0xf0,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x10] 0xfd,0x04,0x0a,0x10 +# GFX12: v_mul_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x10] -# GFX12: v_mul_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf +# GFX12: v_mul_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x11,0x56,0x34,0x12,0xaf] -# GFX12: v_mul_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x0c] 0x01,0x07,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], v[1:2], v[3:4] ; encoding: [0x01,0x07,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x0c] 0xfe,0x05,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], v[254:255], v[2:3] ; encoding: [0xfe,0x05,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x0c] 0x00,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], s[0:1], v[2:3] ; encoding: [0x00,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x0c] 0x68,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], s[104:105], v[2:3] ; encoding: [0x68,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], vcc, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x0c] 0x6a,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], vcc, v[2:3] ; encoding: [0x6a,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x0c] 0x7a,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], ttmp[14:15], v[2:3] ; encoding: [0x7a,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], exec, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x0c] 0x7e,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], exec, v[2:3] ; encoding: [0x7e,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x0c] 0x7c,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], null, v[2:3] ; encoding: [0x7c,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x0c] 0xc1,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], -1, v[2:3] ; encoding: [0xc1,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x0c] 0xf0,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], 0.5, v[2:3] ; encoding: [0xf0,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x0c] 0xfd,0x04,0x0a,0x0c +# GFX12: v_mul_f64_e32 v[5:6], src_scc, v[2:3] ; encoding: [0xfd,0x04,0x0a,0x0c] -# GFX12: v_mul_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x0d,0x56,0x34,0x12,0xaf] 0xff,0xfc,0xfd,0x0d,0x56,0x34,0x12,0xaf +# GFX12: v_mul_f64_e32 v[254:255], 0xaf123456, v[254:255] ; encoding: [0xff,0xfc,0xfd,0x0d,0x56,0x34,0x12,0xaf] -# GFX12: v_mul_hi_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x14] 0x01,0x05,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x14] 0xff,0x05,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x14] 0x01,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x14] 0x69,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x14] 0x6a,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x14] 0x6b,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x14] 0x7b,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x14] 0x7d,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x14] 0x7e,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x14] 0x7f,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x14] 0x7c,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x14] 0xc1,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x14] 0xf0,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x14] 0xfd,0x04,0x0a,0x14 +# GFX12: v_mul_hi_i32_i24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x14] -# GFX12: v_mul_hi_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf +# GFX12: v_mul_hi_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x15,0x56,0x34,0x12,0xaf] -# GFX12: v_mul_hi_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x18] 0x01,0x05,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x18] 0xff,0x05,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x18] 0x01,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x18] 0x69,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x18] 0x6a,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x18] 0x6b,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x18] 0x7b,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x18] 0x7d,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x18] 0x7e,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x18] 0x7f,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x18] 0x7c,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x18] 0xc1,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x18] 0xf0,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x18] 0xfd,0x04,0x0a,0x18 +# GFX12: v_mul_hi_u32_u24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x18] -# GFX12: v_mul_hi_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf +# GFX12: v_mul_hi_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x19,0x56,0x34,0x12,0xaf] -# GFX12: v_mul_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x12] 0x01,0x05,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x12] 0xff,0x05,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x12] 0x01,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x12] 0x69,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x12] 0x6a,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x12] 0x6b,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x12] 0x7b,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x12] 0x7d,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x12] 0x7e,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x12] 0x7f,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x12] 0x7c,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x12] 0xc1,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x12] 0xf0,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x12] 0xfd,0x04,0x0a,0x12 +# GFX12: v_mul_i32_i24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x12] -# GFX12: v_mul_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf +# GFX12: v_mul_i32_i24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x13,0x56,0x34,0x12,0xaf] -# GFX12: v_mul_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x16] 0x01,0x05,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x16] 0xff,0x05,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x16] 0x01,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x16] 0x69,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x16] 0x6a,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x16] 0x6b,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x16] 0x7b,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x16] 0x7d,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x16] 0x7e,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x16] 0x7f,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x16] 0x7c,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x16] 0xc1,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x16] 0xf0,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x16] 0xfd,0x04,0x0a,0x16 +# GFX12: v_mul_u32_u24_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x16] -# GFX12: v_mul_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf +# GFX12: v_mul_u32_u24_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x17,0x56,0x34,0x12,0xaf] -# GFX12: v_or_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x38] 0x01,0x05,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x38] 0xff,0x05,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x38] 0x01,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x38] 0x69,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x38] 0x6a,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x38] 0x6b,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x38] 0x7b,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x38] 0x7d,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x38] 0x7e,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x38] 0x7f,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x38] 0x7c,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x38] 0xc1,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x38] 0xf0,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x38] 0xfd,0x04,0x0a,0x38 +# GFX12: v_or_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x38] -# GFX12: v_or_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf +# GFX12: v_or_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x39,0x56,0x34,0x12,0xaf] -# GFX12: v_pk_fmac_f16 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x78] 0x01,0x05,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x78] 0xff,0x05,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x78] 0x01,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x78] 0x69,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x78] 0x6a,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x78] 0x6b,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x78] 0x7b,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x78] 0x7d,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x78] 0x7e,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x78] 0x7f,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x78] 0x7c,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x78] 0xc1,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x78] 0xf0,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x78] 0xfd,0x04,0x0a,0x78 +# GFX12: v_pk_fmac_f16 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x78] -# GFX12: v_pk_fmac_f16 v255, 0xfe0b, v255 ; encoding: [0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00 +# GFX12: v_pk_fmac_f16 v255, 0xfe0b, v255 ; encoding: [0xff,0xfe,0xff,0x79,0x0b,0xfe,0x00,0x00] +0x01,0x05,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x42] -0x01,0x05,0x0a,0x42 +0xff,0x05,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x42] -0xff,0x05,0x0a,0x42 +0x01,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x42] -0x01,0x04,0x0a,0x42 +0x69,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x42] -0x69,0x04,0x0a,0x42 +0x6a,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x42] -0x6a,0x04,0x0a,0x42 +0x6b,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x42] -0x6b,0x04,0x0a,0x42 +0x7b,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x42] -0x7b,0x04,0x0a,0x42 +0x7d,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x42] -0x7d,0x04,0x0a,0x42 +0x7e,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x42] -0x7e,0x04,0x0a,0x42 +0x7f,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x42] -0x7f,0x04,0x0a,0x42 +0x7c,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x42] -0x7c,0x04,0x0a,0x42 +0xc1,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x42] -0xc1,0x04,0x0a,0x42 +0xf0,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x42] -0xf0,0x04,0x0a,0x42 +0xfd,0x04,0x0a,0x42 # W32: v_sub_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x42] # W64: v_sub_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x42] -0xfd,0x04,0x0a,0x42 +0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf # W32: v_sub_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf] # W64: v_sub_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf] -0xff,0xfe,0xff,0x43,0x56,0x34,0x12,0xaf -# GFX12: v_sub_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x66] 0x01,0x05,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x66] 0x7f,0x05,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x66] 0x01,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x66] 0x69,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x66] 0x6a,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x66] 0x6b,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x66] 0x7b,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x66] 0x7d,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x66] 0x7e,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x66] 0x7f,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x66] 0x7c,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x66] 0xc1,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x66] 0xf0,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x66] 0xfd,0x04,0x0a,0x66 +# GFX12-REAL16: v_sub_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x66] +# GFX12-FAKE16: v_sub_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x66] -# GFX12: v_sub_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00 +# GFX12-REAL16: v_sub_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00] +# GFX12-FAKE16: v_sub_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x66,0x0b,0xfe,0x00,0x00] -# GFX12: v_sub_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x08] 0x01,0x05,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x08] 0xff,0x05,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x08] 0x01,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x08] 0x69,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x08] 0x6a,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x08] 0x6b,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x08] 0x7b,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x08] 0x7d,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x08] 0x7e,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x08] 0x7f,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x08] 0x7c,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x08] 0xc1,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x08] 0xf0,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x08] 0xfd,0x04,0x0a,0x08 +# GFX12: v_sub_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x08] -# GFX12: v_sub_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf +# GFX12: v_sub_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x09,0x56,0x34,0x12,0xaf] -# GFX12: v_sub_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4c] 0x01,0x05,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4c] 0xff,0x05,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4c] 0x01,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4c] 0x69,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4c] 0x6a,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4c] 0x6b,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4c] 0x7b,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4c] 0x7d,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4c] 0x7e,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4c] 0x7f,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4c] 0x7c,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4c] 0xc1,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4c] 0xf0,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4c] 0xfd,0x04,0x0a,0x4c +# GFX12: v_sub_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4c] -# GFX12: v_sub_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf +# GFX12: v_sub_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4d,0x56,0x34,0x12,0xaf] +0x01,0x05,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo ; encoding: [0x01,0x05,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x44] -0x01,0x05,0x0a,0x44 +0xff,0x05,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo ; encoding: [0xff,0x05,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x44] -0xff,0x05,0x0a,0x44 +0x01,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v2, vcc_lo ; encoding: [0x01,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, s1, v2, vcc ; encoding: [0x01,0x04,0x0a,0x44] -0x01,0x04,0x0a,0x44 +0x69,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, s105, v2, vcc_lo ; encoding: [0x69,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, s105, v2, vcc ; encoding: [0x69,0x04,0x0a,0x44] -0x69,0x04,0x0a,0x44 +0x6a,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, vcc_lo, v2, vcc_lo ; encoding: [0x6a,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, vcc_lo, v2, vcc ; encoding: [0x6a,0x04,0x0a,0x44] -0x6a,0x04,0x0a,0x44 +0x6b,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, vcc_hi, v2, vcc_lo ; encoding: [0x6b,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, vcc_hi, v2, vcc ; encoding: [0x6b,0x04,0x0a,0x44] -0x6b,0x04,0x0a,0x44 +0x7b,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, ttmp15, v2, vcc_lo ; encoding: [0x7b,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, ttmp15, v2, vcc ; encoding: [0x7b,0x04,0x0a,0x44] -0x7b,0x04,0x0a,0x44 +0x7d,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, m0, v2, vcc_lo ; encoding: [0x7d,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, m0, v2, vcc ; encoding: [0x7d,0x04,0x0a,0x44] -0x7d,0x04,0x0a,0x44 +0x7e,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, exec_lo, v2, vcc_lo ; encoding: [0x7e,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, exec_lo, v2, vcc ; encoding: [0x7e,0x04,0x0a,0x44] -0x7e,0x04,0x0a,0x44 +0x7f,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, exec_hi, v2, vcc_lo ; encoding: [0x7f,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, exec_hi, v2, vcc ; encoding: [0x7f,0x04,0x0a,0x44] -0x7f,0x04,0x0a,0x44 +0x7c,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, null, v2, vcc_lo ; encoding: [0x7c,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, null, v2, vcc ; encoding: [0x7c,0x04,0x0a,0x44] -0x7c,0x04,0x0a,0x44 +0xc1,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo ; encoding: [0xc1,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x44] -0xc1,0x04,0x0a,0x44 +0xf0,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo ; encoding: [0xf0,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x44] -0xf0,0x04,0x0a,0x44 +0xfd,0x04,0x0a,0x44 # W32: v_subrev_co_ci_u32_e32 v5, vcc_lo, src_scc, v2, vcc_lo ; encoding: [0xfd,0x04,0x0a,0x44] # W64: v_subrev_co_ci_u32_e32 v5, vcc, src_scc, v2, vcc ; encoding: [0xfd,0x04,0x0a,0x44] -0xfd,0x04,0x0a,0x44 +0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf # W32: v_subrev_co_ci_u32_e32 v255, vcc_lo, 0xaf123456, v255, vcc_lo ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf] # W64: v_subrev_co_ci_u32_e32 v255, vcc, 0xaf123456, v255, vcc ; encoding: [0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf] -0xff,0xfe,0xff,0x45,0x56,0x34,0x12,0xaf -# GFX12: v_subrev_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x68] 0x01,0x05,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, v1.l, v2.l ; encoding: [0x01,0x05,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x68] 0x7f,0x05,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, v127.l, v2.l ; encoding: [0x7f,0x05,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, v127, v2 ; encoding: [0x7f,0x05,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x68] 0x01,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, s1, v2.l ; encoding: [0x01,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x68] 0x69,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, s105, v2.l ; encoding: [0x69,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x68] 0x6a,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, vcc_lo, v2.l ; encoding: [0x6a,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x68] 0x6b,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, vcc_hi, v2.l ; encoding: [0x6b,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x68] 0x7b,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, ttmp15, v2.l ; encoding: [0x7b,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x68] 0x7d,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, m0, v2.l ; encoding: [0x7d,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x68] 0x7e,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, exec_lo, v2.l ; encoding: [0x7e,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x68] 0x7f,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, exec_hi, v2.l ; encoding: [0x7f,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x68] 0x7c,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, null, v2.l ; encoding: [0x7c,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x68] 0xc1,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, -1, v2.l ; encoding: [0xc1,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x68] 0xf0,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, 0.5, v2.l ; encoding: [0xf0,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68] 0xfd,0x04,0x0a,0x68 +# GFX12-REAL16: v_subrev_f16_e32 v5.l, src_scc, v2.l ; encoding: [0xfd,0x04,0x0a,0x68] +# GFX12-FAKE16: v_subrev_f16_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x68] -# GFX12: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00] 0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00 +# GFX12-REAL16: v_subrev_f16_e32 v127.l, 0xfe0b, v127.l ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00] +# GFX12-FAKE16: v_subrev_f16_e32 v127, 0xfe0b, v127 ; encoding: [0xff,0xfe,0xfe,0x68,0x0b,0xfe,0x00,0x00] -# GFX12: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a] 0x01,0x05,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0a] 0xff,0x05,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0a] 0x01,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0a] 0x69,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0a] 0x6a,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0a] 0x6b,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0a] 0x7b,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0a] 0x7d,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0a] 0x7e,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0a] 0x7f,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0a] 0x7c,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0a] 0xc1,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0a] 0xf0,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0a] 0xfd,0x04,0x0a,0x0a +# GFX12: v_subrev_f32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x0a] -# GFX12: v_subrev_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf +# GFX12: v_subrev_f32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x0b,0x56,0x34,0x12,0xaf] -# GFX12: v_subrev_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4e] 0x01,0x05,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4e] 0xff,0x05,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4e] 0x01,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4e] 0x69,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4e] 0x6a,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4e] 0x6b,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4e] 0x7b,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4e] 0x7d,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4e] 0x7e,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4e] 0x7f,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4e] 0x7c,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4e] 0xc1,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4e] 0xf0,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4e] 0xfd,0x04,0x0a,0x4e +# GFX12: v_subrev_nc_u32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x4e] -# GFX12: v_subrev_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf +# GFX12: v_subrev_nc_u32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x4f,0x56,0x34,0x12,0xaf] -# GFX12: v_xnor_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3c] 0x01,0x05,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3c] 0xff,0x05,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3c] 0x01,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x3c] 0x69,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3c] 0x6a,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3c] 0x6b,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x3c] 0x7b,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x3c] 0x7d,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x3c] 0x7e,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x3c] 0x7f,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x3c] 0x7c,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x3c] 0xc1,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x3c] 0xf0,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x3c] 0xfd,0x04,0x0a,0x3c +# GFX12: v_xnor_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x3c] -# GFX12: v_xnor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf +# GFX12: v_xnor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3d,0x56,0x34,0x12,0xaf] -# GFX12: v_xor_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3a] 0x01,0x05,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3a] 0xff,0x05,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3a] 0x01,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x3a] 0x69,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, s105, v2 ; encoding: [0x69,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3a] 0x6a,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3a] 0x6b,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x3a] 0x7b,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, ttmp15, v2 ; encoding: [0x7b,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x3a] 0x7d,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, m0, v2 ; encoding: [0x7d,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x3a] 0x7e,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x3a] 0x7f,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x3a] 0x7c,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, null, v2 ; encoding: [0x7c,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x3a] 0xc1,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x3a] 0xf0,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x3a] 0xfd,0x04,0x0a,0x3a +# GFX12: v_xor_b32_e32 v5, src_scc, v2 ; encoding: [0xfd,0x04,0x0a,0x3a] -# GFX12: v_xor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf] 0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf +# GFX12: v_xor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt index 05c8dff02a40b4b8e40c2b7e1e876c8c88fc4b5c..551fb0d311188669b9f9621bcfeb5cb676723de1 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt @@ -1,1696 +1,1797 @@ -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s +; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,GFX12-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,GFX12-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,GFX12-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,GFX12-FAKE16 %s +0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff +0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff] -0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff +0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff] -0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff +0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01 # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01] -0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01 +0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13 # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13] -0xfa,0x04,0x0a,0x40,0x01,0x60,0x01,0x13 +0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30 # W32: v_add_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30] # W64: v_add_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30] -0xfa,0xfe,0xff,0x41,0xff,0x6f,0x0d,0x30 -# GFX12: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff] -# GFX12: v_add_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01 +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01] -# GFX12: v_add_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13 +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x01,0x13] -# GFX12: v_add_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30 +# GFX12-REAL16: v_add_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30] +# GFX12-FAKE16: v_add_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xfd,0x30] -# GFX12: v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff +# GFX12: v_add_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff] -# GFX12: v_add_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01 +# GFX12: v_add_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01] -# GFX12: v_add_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x06,0x01,0x60,0x01,0x13 +# GFX12: v_add_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x01,0x13] -# GFX12: v_add_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x07,0xff,0x6f,0xfd,0x30 +# GFX12: v_add_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xfd,0x30] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01 +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x4a,0x01,0x60,0x01,0x13 +# GFX12: v_add_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x01,0x13] -# GFX12: v_add_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x0d,0x30 +# GFX12: v_add_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x0d,0x30] -# GFX12: v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff +# GFX12: v_and_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff] -# GFX12: v_and_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01 +# GFX12: v_and_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01] -# GFX12: v_and_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x36,0x01,0x60,0x01,0x13 +# GFX12: v_and_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x01,0x13] -# GFX12: v_and_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x37,0xff,0x6f,0x0d,0x30 +# GFX12: v_and_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x0d,0x30] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01 +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x34,0x01,0x60,0x01,0x13 +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x01,0x13] -# GFX12: v_ashrrev_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x35,0xff,0x6f,0x0d,0x30 +# GFX12: v_ashrrev_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x0d,0x30] +0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff +0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff] -0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff +0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff] -0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff +0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01 # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01] -0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01 +0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13 # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13] -0xfa,0x04,0x0a,0x02,0x01,0x60,0x01,0x13 +0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30 # W32: v_cndmask_b32_dpp v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30] # W64: v_cndmask_b32_dpp v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30] -0xfa,0xfe,0xff,0x03,0xff,0x6f,0x0d,0x30 -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01 +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x5e,0x01,0x60,0x01,0x13 +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x01,0x13] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xfd,0x30 +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xfd,0x30] -# GFX12: v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01 +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x5f,0x01,0x01] -# GFX12: v_fmac_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x6c,0x01,0x60,0x01,0x13 +# GFX12: v_fmac_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x60,0x01,0x13] -# GFX12: v_fmac_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30 +# GFX12: v_fmac_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x6f,0xfd,0x30] -# GFX12: v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01 +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01] -# GFX12: v_fmac_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x56,0x01,0x60,0x01,0x13 +# GFX12: v_fmac_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x01,0x13] -# GFX12: v_fmac_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x57,0xff,0x6f,0xfd,0x30 +# GFX12: v_fmac_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xfd,0x30] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01 +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13 +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x01,0x13] -# GFX12: v_ldexp_f16_dpp v127, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30] 0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30 +# GFX12-REAL16: v_ldexp_f16_dpp v127.l, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30] +# GFX12-FAKE16: v_ldexp_f16_dpp v127, -|v127|, v127 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x3d,0x30] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01 +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x30,0x01,0x60,0x01,0x13 +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x01,0x13] -# GFX12: v_lshlrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x31,0xff,0x6f,0x0d,0x30 +# GFX12: v_lshlrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x0d,0x30] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01 +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x32,0x01,0x60,0x01,0x13 +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x01,0x13] -# GFX12: v_lshrrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x33,0xff,0x6f,0x0d,0x30 +# GFX12: v_lshrrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x0d,0x30] -# GFX12: v_max_num_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x62,0x01,0x50,0x01,0xff +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x50,0x01,0xff] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x50,0x01,0xff] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x62,0x01,0x5f,0x01,0x01 +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x5f,0x01,0x01] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x5f,0x01,0x01] -# GFX12: v_max_num_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x62,0x01,0x60,0x01,0x13 +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x60,0x01,0x13] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x62,0x01,0x60,0x01,0x13] -# GFX12: v_max_num_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x62,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x62,0x7f,0x6f,0xfd,0x30 +# GFX12-REAL16: v_max_num_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x62,0x7f,0x6f,0xfd,0x30] +# GFX12-FAKE16: v_max_num_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x62,0x7f,0x6f,0xfd,0x30] -# GFX12: v_max_num_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x2c,0x01,0x50,0x01,0xff +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x50,0x01,0xff] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x01 +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x01] -# GFX12: v_max_num_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x2c,0x01,0x60,0x01,0x13 +# GFX12: v_max_num_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x60,0x01,0x13] -# GFX12: v_max_num_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x2d,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x2d,0xff,0x6f,0xfd,0x30 +# GFX12: v_max_num_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x2d,0xff,0x6f,0xfd,0x30] -# GFX12: v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff +# GFX12: v_max_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff] -# GFX12: v_max_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01 +# GFX12: v_max_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01] -# GFX12: v_max_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x24,0x01,0x60,0x01,0x13 +# GFX12: v_max_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x01,0x13] -# GFX12: v_max_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x25,0xff,0x6f,0x0d,0x30 +# GFX12: v_max_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x0d,0x30] -# GFX12: v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff +# GFX12: v_max_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff] -# GFX12: v_max_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01 +# GFX12: v_max_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01] -# GFX12: v_max_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x28,0x01,0x60,0x01,0x13 +# GFX12: v_max_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x01,0x13] -# GFX12: v_max_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x29,0xff,0x6f,0x0d,0x30 +# GFX12: v_max_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x0d,0x30] -# GFX12: v_min_num_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x60,0x01,0x50,0x01,0xff +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x50,0x01,0xff] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x50,0x01,0xff] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x60,0x01,0x5f,0x01,0x01 +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x5f,0x01,0x01] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x5f,0x01,0x01] -# GFX12: v_min_num_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x60,0x01,0x60,0x01,0x13 +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x60,0x01,0x13] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x60,0x01,0x60,0x01,0x13] -# GFX12: v_min_num_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x60,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x60,0x7f,0x6f,0xfd,0x30 +# GFX12-REAL16: v_min_num_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x60,0x7f,0x6f,0xfd,0x30] +# GFX12-FAKE16: v_min_num_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x60,0x7f,0x6f,0xfd,0x30] -# GFX12: v_min_num_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x2a,0x01,0x50,0x01,0xff +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x50,0x01,0xff] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x2a,0x01,0x5f,0x01,0x01 +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x5f,0x01,0x01] -# GFX12: v_min_num_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x2a,0x01,0x60,0x01,0x13 +# GFX12: v_min_num_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x2a,0x01,0x60,0x01,0x13] -# GFX12: v_min_num_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x2b,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x2b,0xff,0x6f,0xfd,0x30 +# GFX12: v_min_num_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x2b,0xff,0x6f,0xfd,0x30] -# GFX12: v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff +# GFX12: v_min_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff] -# GFX12: v_min_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01 +# GFX12: v_min_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01] -# GFX12: v_min_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x22,0x01,0x60,0x01,0x13 +# GFX12: v_min_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x01,0x13] -# GFX12: v_min_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x23,0xff,0x6f,0x0d,0x30 +# GFX12: v_min_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x0d,0x30] -# GFX12: v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff +# GFX12: v_min_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff] -# GFX12: v_min_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01 +# GFX12: v_min_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01] -# GFX12: v_min_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x26,0x01,0x60,0x01,0x13 +# GFX12: v_min_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x01,0x13] -# GFX12: v_min_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x27,0xff,0x6f,0x0d,0x30 +# GFX12: v_min_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x0d,0x30] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01 +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x0e,0x01,0x60,0x01,0x13 +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x01,0x13] -# GFX12: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xfd,0x30 +# GFX12: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xfd,0x30] -# GFX12: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01 +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01] -# GFX12: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13 +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x01,0x13] -# GFX12: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30 +# GFX12-REAL16: v_mul_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30] +# GFX12-FAKE16: v_mul_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xfd,0x30] -# GFX12: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff +# GFX12: v_mul_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01 +# GFX12: v_mul_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01] -# GFX12: v_mul_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x10,0x01,0x60,0x01,0x13 +# GFX12: v_mul_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x01,0x13] -# GFX12: v_mul_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x11,0xff,0x6f,0xfd,0x30 +# GFX12: v_mul_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xfd,0x30] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01 +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x14,0x01,0x60,0x01,0x13 +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x01,0x13] -# GFX12: v_mul_hi_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x15,0xff,0x6f,0x0d,0x30 +# GFX12: v_mul_hi_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x0d,0x30] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01 +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x18,0x01,0x60,0x01,0x13 +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x01,0x13] -# GFX12: v_mul_hi_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x19,0xff,0x6f,0x0d,0x30 +# GFX12: v_mul_hi_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x0d,0x30] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01 +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x12,0x01,0x60,0x01,0x13 +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x01,0x13] -# GFX12: v_mul_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x13,0xff,0x6f,0x0d,0x30 +# GFX12: v_mul_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x0d,0x30] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01 +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x16,0x01,0x60,0x01,0x13 +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x01,0x13] -# GFX12: v_mul_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x17,0xff,0x6f,0x0d,0x30 +# GFX12: v_mul_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x0d,0x30] -# GFX12: v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff +# GFX12: v_or_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff] -# GFX12: v_or_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01 +# GFX12: v_or_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01] -# GFX12: v_or_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x38,0x01,0x60,0x01,0x13 +# GFX12: v_or_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x01,0x13] -# GFX12: v_or_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x39,0xff,0x6f,0x0d,0x30 +# GFX12: v_or_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x0d,0x30] +0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff +0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff] -0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff +0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff] -0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff +0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01 # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01] -0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01 +0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13 # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13] -0xfa,0x04,0x0a,0x42,0x01,0x60,0x01,0x13 +0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30 # W32: v_sub_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30] # W64: v_sub_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30] -0xfa,0xfe,0xff,0x43,0xff,0x6f,0x0d,0x30 -# GFX12: v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01 +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01] -# GFX12: v_sub_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13 +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x01,0x13] -# GFX12: v_sub_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30 +# GFX12-REAL16: v_sub_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30] +# GFX12-FAKE16: v_sub_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xfd,0x30] -# GFX12: v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff +# GFX12: v_sub_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01 +# GFX12: v_sub_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01] -# GFX12: v_sub_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x08,0x01,0x60,0x01,0x13 +# GFX12: v_sub_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x01,0x13] -# GFX12: v_sub_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x09,0xff,0x6f,0xfd,0x30 +# GFX12: v_sub_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xfd,0x30] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01 +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x4c,0x01,0x60,0x01,0x13 +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x01,0x13] -# GFX12: v_sub_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x0d,0x30 +# GFX12: v_sub_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x0d,0x30] +0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff +0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff] -0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff +0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff] -0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff +0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01 # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01] -0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01 +0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13 # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13] -0xfa,0x04,0x0a,0x44,0x01,0x60,0x01,0x13 +0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30 # W32: v_subrev_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30] # W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30] -0xfa,0xfe,0xff,0x45,0xff,0x6f,0x0d,0x30 -# GFX12: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01 +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01] -# GFX12: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13 +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x01,0x13] -# GFX12: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30] 0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30 +# GFX12-REAL16: v_subrev_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30] +# GFX12-FAKE16: v_subrev_f16_dpp v127, -|v127|, -|v127| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xfd,0x30] -# GFX12: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01 +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01] -# GFX12: v_subrev_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x0a,0x01,0x60,0x01,0x13 +# GFX12: v_subrev_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x01,0x13] -# GFX12: v_subrev_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xfd,0x30] 0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xfd,0x30 +# GFX12: v_subrev_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xfd,0x30] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01 +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x4e,0x01,0x60,0x01,0x13 +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x01,0x13] -# GFX12: v_subrev_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x0d,0x30 +# GFX12: v_subrev_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x0d,0x30] -# GFX12: v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01 +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01] -# GFX12: v_xnor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x3c,0x01,0x60,0x01,0x13 +# GFX12: v_xnor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x01,0x13] -# GFX12: v_xnor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x0d,0x30 +# GFX12: v_xnor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x0d,0x30] -# GFX12: v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff] 0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff +# GFX12: v_xor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01] 0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01 +# GFX12: v_xor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01] -# GFX12: v_xor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x01,0x13] 0xfa,0x04,0x0a,0x3a,0x01,0x60,0x01,0x13 +# GFX12: v_xor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x01,0x13] -# GFX12: v_xor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30] 0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30 +# GFX12: v_xor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt index 2e33df35af1f36f0b4b757677375bd83199c2c1e..bbf494c153fd3a017ce1f9025e186f1f15f1c516 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt @@ -1,244 +1,261 @@ -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32 %s -# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64 %s +; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,GFX12-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,GFX12-REAL16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W32,GFX12-FAKE16 %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64,-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12,W64,GFX12-FAKE16 %s +0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05 # W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] # W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05] -0xe9,0x04,0x0a,0x40,0x01,0x77,0x39,0x05 +0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00 # W32: v_add_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00] # W64: v_add_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00] -0xea,0xfe,0xff,0x41,0xff,0x00,0x00,0x00 -# GFX12: v_add_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05 +# GFX12-REAL16: v_add_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] +# GFX12-FAKE16: v_add_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x64,0x01,0x77,0x39,0x05] -# GFX12: v_add_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00 +# GFX12-REAL16: v_add_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00] +# GFX12-FAKE16: v_add_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x64,0x7f,0x00,0x00,0x00] -# GFX12: v_add_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05 +# GFX12: v_add_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x06,0x01,0x77,0x39,0x05] -# GFX12: v_add_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00 +# GFX12: v_add_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00] -# GFX12: v_add_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05 +# GFX12: v_add_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4a,0x01,0x77,0x39,0x05] -# GFX12: v_add_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00 +# GFX12: v_add_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4b,0xff,0x00,0x00,0x00] -# GFX12: v_and_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05 +# GFX12: v_and_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x36,0x01,0x77,0x39,0x05] -# GFX12: v_and_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x37,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x37,0xff,0x00,0x00,0x00 +# GFX12: v_and_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x37,0xff,0x00,0x00,0x00] -# GFX12: v_ashrrev_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05 +# GFX12: v_ashrrev_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x34,0x01,0x77,0x39,0x05] -# GFX12: v_ashrrev_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x35,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x35,0xff,0x00,0x00,0x00 +# GFX12: v_ashrrev_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x35,0xff,0x00,0x00,0x00] +0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05 # W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] # W64: v_cndmask_b32_dpp v5, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05] -0xe9,0x04,0x0a,0x02,0x01,0x77,0x39,0x05 +0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00 # W32: v_cndmask_b32_dpp v255, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00] # W64: v_cndmask_b32_dpp v255, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00] -0xea,0xfe,0xff,0x03,0xff,0x00,0x00,0x00 -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05 +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x5e,0x01,0x77,0x39,0x05] -# GFX12: v_cvt_pk_rtz_f16_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00 +# GFX12: v_cvt_pk_rtz_f16_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x5f,0xff,0x00,0x00,0x00] -# GFX12: v_fmac_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05 +# GFX12: v_fmac_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6c,0x01,0x77,0x39,0x05] -# GFX12: v_fmac_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00 +# GFX12: v_fmac_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6c,0x7f,0x00,0x00,0x00] -# GFX12: v_fmac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05 +# GFX12: v_fmac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x56,0x01,0x77,0x39,0x05] -# GFX12: v_fmac_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x57,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x57,0xff,0x00,0x00,0x00 +# GFX12: v_fmac_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x57,0xff,0x00,0x00,0x00] -# GFX12: v_ldexp_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05 +# GFX12-REAL16: v_ldexp_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] +# GFX12-FAKE16: v_ldexp_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x76,0x01,0x77,0x39,0x05] -# GFX12: v_ldexp_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00 +# GFX12-REAL16: v_ldexp_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00] +# GFX12-FAKE16: v_ldexp_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x76,0x7f,0x00,0x00,0x00] -# GFX12: v_lshlrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05 +# GFX12: v_lshlrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x30,0x01,0x77,0x39,0x05] -# GFX12: v_lshlrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x31,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x31,0xff,0x00,0x00,0x00 +# GFX12: v_lshlrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x31,0xff,0x00,0x00,0x00] -# GFX12: v_lshrrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05 +# GFX12: v_lshrrev_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x32,0x01,0x77,0x39,0x05] -# GFX12: v_lshrrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x33,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x33,0xff,0x00,0x00,0x00 +# GFX12: v_lshrrev_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x33,0xff,0x00,0x00,0x00] -# GFX12: v_max_num_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x62,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x62,0x01,0x77,0x39,0x05 +# GFX12-REAL16: v_max_num_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x62,0x01,0x77,0x39,0x05] +# GFX12-FAKE16: v_max_num_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x62,0x01,0x77,0x39,0x05] -# GFX12: v_max_num_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x62,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x62,0x7f,0x00,0x00,0x00 +# GFX12-REAL16: v_max_num_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x62,0x7f,0x00,0x00,0x00] +# GFX12-FAKE16: v_max_num_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x62,0x7f,0x00,0x00,0x00] -# GFX12: v_max_num_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05 +# GFX12: v_max_num_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x2c,0x01,0x77,0x39,0x05] -# GFX12: v_max_num_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x2d,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x2d,0xff,0x00,0x00,0x00 +# GFX12: v_max_num_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x2d,0xff,0x00,0x00,0x00] -# GFX12: v_max_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05 +# GFX12: v_max_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x24,0x01,0x77,0x39,0x05] -# GFX12: v_max_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x25,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x25,0xff,0x00,0x00,0x00 +# GFX12: v_max_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x25,0xff,0x00,0x00,0x00] -# GFX12: v_max_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05 +# GFX12: v_max_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x28,0x01,0x77,0x39,0x05] -# GFX12: v_max_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x29,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x29,0xff,0x00,0x00,0x00 +# GFX12: v_max_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x29,0xff,0x00,0x00,0x00] -# GFX12: v_min_num_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x60,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x60,0x01,0x77,0x39,0x05 +# GFX12-REAL16: v_min_num_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x60,0x01,0x77,0x39,0x05] +# GFX12-FAKE16: v_min_num_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x60,0x01,0x77,0x39,0x05] -# GFX12: v_min_num_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x60,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x60,0x7f,0x00,0x00,0x00 +# GFX12-REAL16: v_min_num_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x60,0x7f,0x00,0x00,0x00] +# GFX12-FAKE16: v_min_num_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x60,0x7f,0x00,0x00,0x00] -# GFX12: v_min_num_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05 +# GFX12: v_min_num_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x2a,0x01,0x77,0x39,0x05] -# GFX12: v_min_num_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x2b,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x2b,0xff,0x00,0x00,0x00 +# GFX12: v_min_num_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x2b,0xff,0x00,0x00,0x00] -# GFX12: v_min_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05 +# GFX12: v_min_i32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x22,0x01,0x77,0x39,0x05] -# GFX12: v_min_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x23,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x23,0xff,0x00,0x00,0x00 +# GFX12: v_min_i32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x23,0xff,0x00,0x00,0x00] -# GFX12: v_min_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05 +# GFX12: v_min_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x26,0x01,0x77,0x39,0x05] -# GFX12: v_min_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x27,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x27,0xff,0x00,0x00,0x00 +# GFX12: v_min_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x27,0xff,0x00,0x00,0x00] -# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05 +# GFX12: v_mul_dx9_zero_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0e,0x01,0x77,0x39,0x05] -# GFX12: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00 +# GFX12: v_mul_dx9_zero_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0f,0xff,0x00,0x00,0x00] -# GFX12: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05 +# GFX12-REAL16: v_mul_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] +# GFX12-FAKE16: v_mul_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x6a,0x01,0x77,0x39,0x05] -# GFX12: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00 +# GFX12-REAL16: v_mul_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] +# GFX12-FAKE16: v_mul_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x6a,0x7f,0x00,0x00,0x00] -# GFX12: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05 +# GFX12: v_mul_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x10,0x01,0x77,0x39,0x05] -# GFX12: v_mul_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x11,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x11,0xff,0x00,0x00,0x00 +# GFX12: v_mul_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x11,0xff,0x00,0x00,0x00] -# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05 +# GFX12: v_mul_hi_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x14,0x01,0x77,0x39,0x05] -# GFX12: v_mul_hi_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x15,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x15,0xff,0x00,0x00,0x00 +# GFX12: v_mul_hi_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x15,0xff,0x00,0x00,0x00] -# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05 +# GFX12: v_mul_hi_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x18,0x01,0x77,0x39,0x05] -# GFX12: v_mul_hi_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x19,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x19,0xff,0x00,0x00,0x00 +# GFX12: v_mul_hi_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x19,0xff,0x00,0x00,0x00] -# GFX12: v_mul_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05 +# GFX12: v_mul_i32_i24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x12,0x01,0x77,0x39,0x05] -# GFX12: v_mul_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x13,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x13,0xff,0x00,0x00,0x00 +# GFX12: v_mul_i32_i24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x13,0xff,0x00,0x00,0x00] -# GFX12: v_mul_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05 +# GFX12: v_mul_u32_u24_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x16,0x01,0x77,0x39,0x05] -# GFX12: v_mul_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x17,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x17,0xff,0x00,0x00,0x00 +# GFX12: v_mul_u32_u24_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x17,0xff,0x00,0x00,0x00] -# GFX12: v_or_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05 +# GFX12: v_or_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x38,0x01,0x77,0x39,0x05] -# GFX12: v_or_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x39,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x39,0xff,0x00,0x00,0x00 +# GFX12: v_or_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x39,0xff,0x00,0x00,0x00] +0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05 # W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] # W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05] -0xe9,0x04,0x0a,0x42,0x01,0x77,0x39,0x05 +0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00 # W32: v_sub_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00] # W64: v_sub_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00] -0xea,0xfe,0xff,0x43,0xff,0x00,0x00,0x00 -# GFX12: v_sub_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05 +# GFX12-REAL16: v_sub_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] +# GFX12-FAKE16: v_sub_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x66,0x01,0x77,0x39,0x05] -# GFX12: v_sub_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00 +# GFX12-REAL16: v_sub_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00] +# GFX12-FAKE16: v_sub_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x66,0x7f,0x00,0x00,0x00] -# GFX12: v_sub_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05 +# GFX12: v_sub_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x08,0x01,0x77,0x39,0x05] -# GFX12: v_sub_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x09,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x09,0xff,0x00,0x00,0x00 +# GFX12: v_sub_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x09,0xff,0x00,0x00,0x00] -# GFX12: v_sub_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05 +# GFX12: v_sub_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4c,0x01,0x77,0x39,0x05] -# GFX12: v_sub_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00 +# GFX12: v_sub_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4d,0xff,0x00,0x00,0x00] +0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05 # W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] # W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05] -0xe9,0x04,0x0a,0x44,0x01,0x77,0x39,0x05 +0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00 # W32: v_subrev_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00] # W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00] -0xea,0xfe,0xff,0x45,0xff,0x00,0x00,0x00 -# GFX12: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05 +# GFX12-REAL16: v_subrev_f16_dpp v5.l, v1.l, v2.l dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] +# GFX12-FAKE16: v_subrev_f16_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x68,0x01,0x77,0x39,0x05] -# GFX12: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00] 0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00 +# GFX12-REAL16: v_subrev_f16_dpp v127.l, v127.l, v127.l dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00] +# GFX12-FAKE16: v_subrev_f16_dpp v127, v127, v127 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xfe,0x68,0x7f,0x00,0x00,0x00] -# GFX12: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05 +# GFX12: v_subrev_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x0a,0x01,0x77,0x39,0x05] -# GFX12: v_subrev_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00 +# GFX12: v_subrev_f32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x0b,0xff,0x00,0x00,0x00] -# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05 +# GFX12: v_subrev_nc_u32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x4e,0x01,0x77,0x39,0x05] -# GFX12: v_subrev_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00 +# GFX12: v_subrev_nc_u32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x4f,0xff,0x00,0x00,0x00] -# GFX12: v_xnor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05 +# GFX12: v_xnor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3c,0x01,0x77,0x39,0x05] -# GFX12: v_xnor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00 +# GFX12: v_xnor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3d,0xff,0x00,0x00,0x00] -# GFX12: v_xor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05] 0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05 +# GFX12: v_xor_b32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0a,0x3a,0x01,0x77,0x39,0x05] -# GFX12: v_xor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00] 0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00 +# GFX12: v_xor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/X86/AMX/amx-fp8.txt b/llvm/test/MC/Disassembler/X86/AMX/amx-fp8.txt new file mode 100644 index 0000000000000000000000000000000000000000..e714a52d2c31a75f5fddb0f6be5ecf2c31650b70 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/AMX/amx-fp8.txt @@ -0,0 +1,34 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: tdpbf8ps %tmm4, %tmm5, %tmm6 +# INTEL: tdpbf8ps tmm6, tmm5, tmm4 +0xc4,0xe5,0x58,0xfd,0xf5 + +# ATT: tdpbf8ps %tmm1, %tmm2, %tmm3 +# INTEL: tdpbf8ps tmm3, tmm2, tmm1 +0xc4,0xe5,0x70,0xfd,0xda + +# ATT: tdpbhf8ps %tmm4, %tmm5, %tmm6 +# INTEL: tdpbhf8ps tmm6, tmm5, tmm4 +0xc4,0xe5,0x5b,0xfd,0xf5 + +# ATT: tdpbhf8ps %tmm1, %tmm2, %tmm3 +# INTEL: tdpbhf8ps tmm3, tmm2, tmm1 +0xc4,0xe5,0x73,0xfd,0xda + +# ATT: tdphbf8ps %tmm4, %tmm5, %tmm6 +# INTEL: tdphbf8ps tmm6, tmm5, tmm4 +0xc4,0xe5,0x5a,0xfd,0xf5 + +# ATT: tdphbf8ps %tmm1, %tmm2, %tmm3 +# INTEL: tdphbf8ps tmm3, tmm2, tmm1 +0xc4,0xe5,0x72,0xfd,0xda + +# ATT: tdphf8ps %tmm4, %tmm5, %tmm6 +# INTEL: tdphf8ps tmm6, tmm5, tmm4 +0xc4,0xe5,0x59,0xfd,0xf5 + +# ATT: tdphf8ps %tmm1, %tmm2, %tmm3 +# INTEL: tdphf8ps tmm3, tmm2, tmm1 +0xc4,0xe5,0x71,0xfd,0xda diff --git a/llvm/test/MC/X86/AMX/amx-fp8-att.s b/llvm/test/MC/X86/AMX/amx-fp8-att.s new file mode 100644 index 0000000000000000000000000000000000000000..904539ec4917fe1a4523bda249b36f86e4bb6689 --- /dev/null +++ b/llvm/test/MC/X86/AMX/amx-fp8-att.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s + +// CHECK: tdpbf8ps %tmm4, %tmm5, %tmm6 +// CHECK: encoding: [0xc4,0xe5,0x58,0xfd,0xf5] + tdpbf8ps %tmm4, %tmm5, %tmm6 + +// CHECK: tdpbf8ps %tmm1, %tmm2, %tmm3 +// CHECK: encoding: [0xc4,0xe5,0x70,0xfd,0xda] + tdpbf8ps %tmm1, %tmm2, %tmm3 + +// CHECK: tdpbhf8ps %tmm4, %tmm5, %tmm6 +// CHECK: encoding: [0xc4,0xe5,0x5b,0xfd,0xf5] + tdpbhf8ps %tmm4, %tmm5, %tmm6 + +// CHECK: tdpbhf8ps %tmm1, %tmm2, %tmm3 +// CHECK: encoding: [0xc4,0xe5,0x73,0xfd,0xda] + tdpbhf8ps %tmm1, %tmm2, %tmm3 + +// CHECK: tdphbf8ps %tmm4, %tmm5, %tmm6 +// CHECK: encoding: [0xc4,0xe5,0x5a,0xfd,0xf5] + tdphbf8ps %tmm4, %tmm5, %tmm6 + +// CHECK: tdphbf8ps %tmm1, %tmm2, %tmm3 +// CHECK: encoding: [0xc4,0xe5,0x72,0xfd,0xda] + tdphbf8ps %tmm1, %tmm2, %tmm3 + +// CHECK: tdphf8ps %tmm4, %tmm5, %tmm6 +// CHECK: encoding: [0xc4,0xe5,0x59,0xfd,0xf5] + tdphf8ps %tmm4, %tmm5, %tmm6 + +// CHECK: tdphf8ps %tmm1, %tmm2, %tmm3 +// CHECK: encoding: [0xc4,0xe5,0x71,0xfd,0xda] + tdphf8ps %tmm1, %tmm2, %tmm3 diff --git a/llvm/test/MC/X86/AMX/amx-fp8-intel.s b/llvm/test/MC/X86/AMX/amx-fp8-intel.s new file mode 100644 index 0000000000000000000000000000000000000000..4191ae6f5cd1333d5db984ac41c4690e7fd39183 --- /dev/null +++ b/llvm/test/MC/X86/AMX/amx-fp8-intel.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: tdpbf8ps tmm6, tmm5, tmm4 +// CHECK: encoding: [0xc4,0xe5,0x58,0xfd,0xf5] + tdpbf8ps tmm6, tmm5, tmm4 + +// CHECK: tdpbf8ps tmm3, tmm2, tmm1 +// CHECK: encoding: [0xc4,0xe5,0x70,0xfd,0xda] + tdpbf8ps tmm3, tmm2, tmm1 + +// CHECK: tdpbhf8ps tmm6, tmm5, tmm4 +// CHECK: encoding: [0xc4,0xe5,0x5b,0xfd,0xf5] + tdpbhf8ps tmm6, tmm5, tmm4 + +// CHECK: tdpbhf8ps tmm3, tmm2, tmm1 +// CHECK: encoding: [0xc4,0xe5,0x73,0xfd,0xda] + tdpbhf8ps tmm3, tmm2, tmm1 + +// CHECK: tdphbf8ps tmm6, tmm5, tmm4 +// CHECK: encoding: [0xc4,0xe5,0x5a,0xfd,0xf5] + tdphbf8ps tmm6, tmm5, tmm4 + +// CHECK: tdphbf8ps tmm3, tmm2, tmm1 +// CHECK: encoding: [0xc4,0xe5,0x72,0xfd,0xda] + tdphbf8ps tmm3, tmm2, tmm1 + +// CHECK: tdphf8ps tmm6, tmm5, tmm4 +// CHECK: encoding: [0xc4,0xe5,0x59,0xfd,0xf5] + tdphf8ps tmm6, tmm5, tmm4 + +// CHECK: tdphf8ps tmm3, tmm2, tmm1 +// CHECK: encoding: [0xc4,0xe5,0x71,0xfd,0xda] + tdphf8ps tmm3, tmm2, tmm1 diff --git a/llvm/test/TableGen/64-bit-int.td b/llvm/test/TableGen/64-bit-int.td index 2d2bdb8b560e2c3c8191556f215717bbde5c411c..d2a2999c14e9913880c4990721f510de8c510d6a 100644 --- a/llvm/test/TableGen/64-bit-int.td +++ b/llvm/test/TableGen/64-bit-int.td @@ -16,7 +16,7 @@ def { #ifdef OOR3 bits<64> Val = 0x10000000000000000; #endif -// CHECK-OOR: error: Number out of range +// CHECK-OOR: error: number out of range bits<64> BinVal0 = 0x8000000000000000; bits<64> HexVal0 = 0b1000000000000000000000000000000000000000000000000000000000000000; diff --git a/llvm/test/TableGen/invalid-macro-name-command-line.td b/llvm/test/TableGen/invalid-macro-name-command-line.td index 0d2307997ebe5451719085edc1d4f4ebaa9627f8..7d19e8996639af89ec217492f73703fc87d536d4 100644 --- a/llvm/test/TableGen/invalid-macro-name-command-line.td +++ b/llvm/test/TableGen/invalid-macro-name-command-line.td @@ -3,7 +3,7 @@ // RUN: not llvm-tblgen %s -D_MAC# 2>&1 | FileCheck %s --check-prefix=CHECK-TEST-3 // RUN: not llvm-tblgen %s -D 2>&1 | FileCheck %s --check-prefix=CHECK-TEST-4 -// CHECK-TEST-1: error: Invalid macro name `MACRO=1` specified on command line -// CHECK-TEST-2: error: Invalid macro name `0MAC` specified on command line -// CHECK-TEST-3: error: Invalid macro name `_MAC#` specified on command line +// CHECK-TEST-1: error: invalid macro name `MACRO=1` specified on command line +// CHECK-TEST-2: error: invalid macro name `0MAC` specified on command line +// CHECK-TEST-3: error: invalid macro name `_MAC#` specified on command line // CHECK-TEST-4: for the -D option: requires a value! diff --git a/llvm/test/TableGen/prep-diag1.td b/llvm/test/TableGen/prep-diag1.td index 41b7d477c6942e3de820d1e2a3011deb94ffb70a..27f428f4fe959894b1dbf944e2ac27e4e9ce99a5 100644 --- a/llvm/test/TableGen/prep-diag1.td +++ b/llvm/test/TableGen/prep-diag1.td @@ -4,22 +4,22 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck --check-prefixes=DIAG3 %s #ifdef DIAG1 -// DIAG1: error: Only comments are supported after #define NAME +// DIAG1: error: only comments are supported after #define NAME #define ENABLED1/* */class C; #endif // DIAG1 #ifdef DIAG4 -// DIAG4: warning: Duplicate definition of macro: ENABLED1 +// DIAG4: warning: duplicate definition of macro: ENABLED1 #define ENABLED1 #define ENABLED1 #endif // DIAG4 #ifdef DIAG2 -// DIAG2: error: Only comments are supported after #ifdef NAME +// DIAG2: error: only comments are supported after #ifdef NAME // Invalid #ifdef below should be detected even if DIAG2 is not defined. -// DIAG3: error: Only comments are supported after #ifdef NAME +// DIAG3: error: only comments are supported after #ifdef NAME #ifdef DIAG2/* */class C; #endif diff --git a/llvm/test/TableGen/prep-diag10.td b/llvm/test/TableGen/prep-diag10.td index eb387a07b066ca491911fe26e05abd1fc6095885..cfcbab094ad73b7355f10fabcc2f3d981185f9f2 100644 --- a/llvm/test/TableGen/prep-diag10.td +++ b/llvm/test/TableGen/prep-diag10.td @@ -1,6 +1,6 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED #else diff --git a/llvm/test/TableGen/prep-diag11.td b/llvm/test/TableGen/prep-diag11.td index 0042bc04f9e10143bdb90fb3ee25d852b2500cfd..1fe8a8503076e5f8f97a87d3218751a3e9060a8f 100644 --- a/llvm/test/TableGen/prep-diag11.td +++ b/llvm/test/TableGen/prep-diag11.td @@ -1,7 +1,7 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED #else #define ENABLED diff --git a/llvm/test/TableGen/prep-diag12.td b/llvm/test/TableGen/prep-diag12.td index c26301ee17ac2b18338d40f4675672206eb01482..02ffa672b2fa050dd5c911d5cbd94234dce0cda1 100644 --- a/llvm/test/TableGen/prep-diag12.td +++ b/llvm/test/TableGen/prep-diag12.td @@ -1,7 +1,7 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED #else #define ENABLED diff --git a/llvm/test/TableGen/prep-diag13.td b/llvm/test/TableGen/prep-diag13.td index aa3fdab4802d379b155fe0556cda2524b4634a6c..733a46a161813188bdc0e81a73f14654565a70e2 100644 --- a/llvm/test/TableGen/prep-diag13.td +++ b/llvm/test/TableGen/prep-diag13.td @@ -1,7 +1,7 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED /* #else diff --git a/llvm/test/TableGen/prep-diag14.td b/llvm/test/TableGen/prep-diag14.td index cae9bc3b7f5b6c8b2f4d7f8986464acdfde4f298..a3216ee4f47125178a6f383e68c5bf3d353061cd 100644 --- a/llvm/test/TableGen/prep-diag14.td +++ b/llvm/test/TableGen/prep-diag14.td @@ -1,6 +1,6 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED // #endif diff --git a/llvm/test/TableGen/prep-diag2.td b/llvm/test/TableGen/prep-diag2.td index 741026b9c8a2d6415ac0cf6a28fa6c8db25824c1..e51490600ff64f57917d39b45f18b2b954deba30 100644 --- a/llvm/test/TableGen/prep-diag2.td +++ b/llvm/test/TableGen/prep-diag2.td @@ -2,10 +2,10 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck --check-prefixes=DIAG2 %s #ifdef DIAG1 -// DIAG1: error: Only comments are supported after #else +// DIAG1: error: only comments are supported after #else // Invalid #else below should be detected even if DIAG1 is not defined. -// DIAG2: error: Only comments are supported after #else +// DIAG2: error: only comments are supported after #else #ifdef DIAG2//DIAG2 #else/* */class C; diff --git a/llvm/test/TableGen/prep-diag3.td b/llvm/test/TableGen/prep-diag3.td index fbedfa290b9947dfcf3ba836159abb5a9c6ea202..0b4d40307b40b06fd9ca036feede47e3d5a1a38c 100644 --- a/llvm/test/TableGen/prep-diag3.td +++ b/llvm/test/TableGen/prep-diag3.td @@ -2,10 +2,10 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck --check-prefixes=DIAG2 %s #ifdef DIAG1 -// DIAG1: error: Only comments are supported after #endif +// DIAG1: error: only comments are supported after #endif // Invalid #else below should be detected even if DIAG1 is not defined. -// DIAG2: error: Only comments are supported after #endif +// DIAG2: error: only comments are supported after #endif #ifdef DIAG2//DIAG2 #else/*!DIAG2*/ #endif/* !DIAG2 diff --git a/llvm/test/TableGen/prep-diag4.td b/llvm/test/TableGen/prep-diag4.td index 4661ef8667d23fc7d6c213b637969cc6ea0c729d..ead116ebde0de8eda29ee329e6f132b2335721f1 100644 --- a/llvm/test/TableGen/prep-diag4.td +++ b/llvm/test/TableGen/prep-diag4.td @@ -1,7 +1,7 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s // CHECK: error: double #else -// CHECK: error: Previous #else is here +// CHECK: error: previous #else is here #ifdef DIAG1 #else #else diff --git a/llvm/test/TableGen/prep-diag6.td b/llvm/test/TableGen/prep-diag6.td index f4202d115da59a463c41dc92ed64b1857d058836..bf1cd3d3490b5e21f28d713cee925e8fbd7ad950 100644 --- a/llvm/test/TableGen/prep-diag6.td +++ b/llvm/test/TableGen/prep-diag6.td @@ -1,6 +1,6 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Expected macro name after #ifdef +// CHECK: error: expected macro name after #ifdef #ifdef #else #else diff --git a/llvm/test/TableGen/prep-diag8.td b/llvm/test/TableGen/prep-diag8.td index 7a7bde62c79c4e127e560a5dc4a7a53a5467186b..82797d6cf4a62d87ecb05c416b992bb59f7edc5e 100644 --- a/llvm/test/TableGen/prep-diag8.td +++ b/llvm/test/TableGen/prep-diag8.td @@ -1,5 +1,5 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Expected macro name after #define +// CHECK: error: expected macro name after #define #define #endif diff --git a/llvm/test/TableGen/prep-diag9.td b/llvm/test/TableGen/prep-diag9.td index 4ecff575cdc7bbdd873ffb858c3efa5f32054cb4..6ad208104301bc46bfaf9cac123f1a4d9d341530 100644 --- a/llvm/test/TableGen/prep-diag9.td +++ b/llvm/test/TableGen/prep-diag9.td @@ -1,5 +1,5 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Reached EOF without matching #endif -// CHECK: error: The latest preprocessor control is here +// CHECK: error: reached EOF without matching #endif +// CHECK: error: the latest preprocessor control is here #ifdef DISABLED diff --git a/llvm/test/TableGen/prep-ifndef-diag-1.td b/llvm/test/TableGen/prep-ifndef-diag-1.td index 941f2d377a98a7447bae0077717bcbdffb245c3c..4a0d0754ed790633a7bba44e8a06b68757aac336 100644 --- a/llvm/test/TableGen/prep-ifndef-diag-1.td +++ b/llvm/test/TableGen/prep-ifndef-diag-1.td @@ -1,4 +1,4 @@ // RUN: not llvm-tblgen %s 2>&1 | FileCheck %s -// CHECK: error: Expected macro name after #ifndef +// CHECK: error: expected macro name after #ifndef #ifndef 1 diff --git a/llvm/test/TableGen/prep-ifndef-diag-2.td b/llvm/test/TableGen/prep-ifndef-diag-2.td index 7b5f9dfd24b786108f4f0a64aea0fc65522813d9..c89cbab08e5c5cdea627b3053355d36e02e1c6a5 100644 --- a/llvm/test/TableGen/prep-ifndef-diag-2.td +++ b/llvm/test/TableGen/prep-ifndef-diag-2.td @@ -1,4 +1,4 @@ // RUN: not llvm-tblgen %s 2>&1 | FileCheck %s -// CHECK: error: Only comments are supported after #ifndef NAME +// CHECK: error: only comments are supported after #ifndef NAME #ifndef MACRO 42 diff --git a/llvm/test/TableGen/unterminated-c-comment.td b/llvm/test/TableGen/unterminated-c-comment.td index 0f4cd9d633c66d995070375ffa47fa314e26d084..b5b995342be744a127a3063a097cf1ae00867c53 100644 --- a/llvm/test/TableGen/unterminated-c-comment.td +++ b/llvm/test/TableGen/unterminated-c-comment.td @@ -1,5 +1,5 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Unterminated comment! +// CHECK: error: unterminated comment include "unterminated-c-comment-include.inc" */ diff --git a/llvm/test/TableGen/unterminated-code-block.td b/llvm/test/TableGen/unterminated-code-block.td index d6b6f50827a67259804314efa2e97cfba33cbe0d..5bd4cd7e17d827cd785d44fb2a7b2fb1c940424f 100644 --- a/llvm/test/TableGen/unterminated-code-block.td +++ b/llvm/test/TableGen/unterminated-code-block.td @@ -1,5 +1,5 @@ // RUN: not llvm-tblgen -I %p %s 2>&1 | FileCheck %s -// CHECK: error: Unterminated code block +// CHECK: error: unterminated code block include "unterminated-code-block-include.inc" }]>; diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index 43c206fa0af698e41a8cd3012545b8bf2a503327..21f3c8593a710b064b4c8390fb4e5cfc45106ab7 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -1959,8 +1959,11 @@ static const X86FoldTableEntry Table1[] = { {X86::VUCOMISSZrr_Int, X86::VUCOMISSZrm_Int, TB_NO_REVERSE}, {X86::VUCOMISSrr, X86::VUCOMISSrm, 0}, {X86::VUCOMISSrr_Int, X86::VUCOMISSrm_Int, TB_NO_REVERSE}, + {X86::VUCOMXSDZrr, X86::VUCOMXSDZrm, 0}, {X86::VUCOMXSDZrr_Int, X86::VUCOMXSDZrm_Int, TB_NO_REVERSE}, + {X86::VUCOMXSHZrr, X86::VUCOMXSHZrm, 0}, {X86::VUCOMXSHZrr_Int, X86::VUCOMXSHZrm_Int, TB_NO_REVERSE}, + {X86::VUCOMXSSZrr, X86::VUCOMXSSZrm, 0}, {X86::VUCOMXSSZrr_Int, X86::VUCOMXSSZrm_Int, TB_NO_REVERSE}, {X86::XOR16ri8_ND, X86::XOR16mi8_ND, 0}, {X86::XOR16ri8_NF_ND, X86::XOR16mi8_NF_ND, 0}, diff --git a/llvm/test/Transforms/Attributor/nofpclass-phiselect.ll b/llvm/test/Transforms/Attributor/nofpclass-phiselect.ll new file mode 100644 index 0000000000000000000000000000000000000000..6635280bc436039b2b927fd55cffcbe6778f4d30 --- /dev/null +++ b/llvm/test/Transforms/Attributor/nofpclass-phiselect.ll @@ -0,0 +1,176 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal -S < %s | FileCheck %s + +define float @phi_select(i1 %c, float nofpclass(inf) %base, float nofpclass(inf) %arg) { +; CHECK-LABEL: define float @phi_select +; CHECK-SAME: (i1 [[C:%.*]], float nofpclass(inf) [[BASE:%.*]], float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[SELECT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[SELECT]] = select i1 [[C]], float [[PHI]], float [[ARG]] +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[SELECT]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %select, %loop ] + %select = select i1 %c, float %phi, float %arg + br i1 %c, label %loop, label %exit + +exit: + ret float %select +} + +define float @phi_select_onlybase(i1 %c, float nofpclass(inf) %base, float %arg) { +; CHECK-LABEL: define float @phi_select_onlybase +; CHECK-SAME: (i1 [[C:%.*]], float nofpclass(inf) [[BASE:%.*]], float [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[SELECT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[SELECT]] = select i1 [[C]], float [[PHI]], float [[ARG]] +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[SELECT]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %select, %loop ] + %select = select i1 %c, float %phi, float %arg + br i1 %c, label %loop, label %exit + +exit: + ret float %select +} + +define float @phi_select_onlyarg(i1 %c, float %base, float nofpclass(inf) %arg) { +; CHECK-LABEL: define float @phi_select_onlyarg +; CHECK-SAME: (i1 [[C:%.*]], float [[BASE:%.*]], float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[SELECT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[SELECT]] = select i1 [[C]], float [[PHI]], float [[ARG]] +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[SELECT]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %select, %loop ] + %select = select i1 %c, float %phi, float %arg + br i1 %c, label %loop, label %exit + +exit: + ret float %select +} + +define float @phi_phi(i1 %c, float nofpclass(inf) %base, float nofpclass(inf) %arg) { +; CHECK-LABEL: define float @phi_phi +; CHECK-SAME: (i1 [[C:%.*]], float nofpclass(inf) [[BASE:%.*]], float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[PHI2:%.*]], [[EXIT1:%.*]] ] +; CHECK-NEXT: br label [[INNER:%.*]] +; CHECK: inner: +; CHECK-NEXT: [[PHI2]] = phi float [ [[PHI]], [[LOOP]] ], [ [[ARG]], [[INNER]] ] +; CHECK-NEXT: br i1 [[C]], label [[INNER]], label [[EXIT1]] +; CHECK: exit1: +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[PHI2]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %phi2, %exit1 ] + br label %inner + +inner: + %phi2 = phi float [ %phi, %loop ], [ %arg, %inner ] + br i1 %c, label %inner, label %exit1 + +exit1: + br i1 %c, label %loop, label %exit + +exit: + ret float %phi2 +} + +define float @phi_phi_onlybase(i1 %c, float nofpclass(inf) %base, float %arg) { +; CHECK-LABEL: define float @phi_phi_onlybase +; CHECK-SAME: (i1 [[C:%.*]], float nofpclass(inf) [[BASE:%.*]], float [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[PHI2:%.*]], [[EXIT1:%.*]] ] +; CHECK-NEXT: br label [[INNER:%.*]] +; CHECK: inner: +; CHECK-NEXT: [[PHI2]] = phi float [ [[PHI]], [[LOOP]] ], [ [[ARG]], [[INNER]] ] +; CHECK-NEXT: br i1 [[C]], label [[INNER]], label [[EXIT1]] +; CHECK: exit1: +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[PHI2]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %phi2, %exit1 ] + br label %inner + +inner: + %phi2 = phi float [ %phi, %loop ], [ %arg, %inner ] + br i1 %c, label %inner, label %exit1 + +exit1: + br i1 %c, label %loop, label %exit + +exit: + ret float %phi2 +} + +define float @phi_phi_onlyarg(i1 %c, float %base, float nofpclass(inf) %arg) { +; CHECK-LABEL: define float @phi_phi_onlyarg +; CHECK-SAME: (i1 [[C:%.*]], float [[BASE:%.*]], float nofpclass(inf) [[ARG:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[PHI:%.*]] = phi float [ [[BASE]], [[ENTRY:%.*]] ], [ [[PHI2:%.*]], [[EXIT1:%.*]] ] +; CHECK-NEXT: br label [[INNER:%.*]] +; CHECK: inner: +; CHECK-NEXT: [[PHI2]] = phi float [ [[PHI]], [[LOOP]] ], [ [[ARG]], [[INNER]] ] +; CHECK-NEXT: br i1 [[C]], label [[INNER]], label [[EXIT1]] +; CHECK: exit1: +; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; CHECK: exit: +; CHECK-NEXT: ret float [[PHI2]] +; +entry: + br label %loop + +loop: + %phi = phi float [ %base, %entry ], [ %phi2, %exit1 ] + br label %inner + +inner: + %phi2 = phi float [ %phi, %loop ], [ %arg, %inner ] + br i1 %c, label %inner, label %exit1 + +exit1: + br i1 %c, label %loop, label %exit + +exit: + ret float %phi2 +} diff --git a/llvm/test/Transforms/Inline/convergence-inline.ll b/llvm/test/Transforms/Inline/convergence-inline.ll index 8c67e6a59b7db1a7c2873f1ffc80be422a6bd94a..4996a2376be638b1c750f3408bd530b93b3409d8 100644 --- a/llvm/test/Transforms/Inline/convergence-inline.ll +++ b/llvm/test/Transforms/Inline/convergence-inline.ll @@ -185,6 +185,30 @@ define void @test_two_calls() convergent { ret void } +define i32 @token_not_first(i32 %x) convergent alwaysinline { +; CHECK-LABEL: @token_not_first( +; CHECK-NEXT: {{%.*}} = alloca ptr, align 8 +; CHECK-NEXT: [[TOKEN:%.*]] = call token @llvm.experimental.convergence.entry() +; CHECK-NEXT: [[Y:%.*]] = call i32 @g(i32 [[X:%.*]]) [ "convergencectrl"(token [[TOKEN]]) ] +; CHECK-NEXT: ret i32 [[Y]] +; + %p = alloca ptr, align 8 + %token = call token @llvm.experimental.convergence.entry() + %y = call i32 @g(i32 %x) [ "convergencectrl"(token %token) ] + ret i32 %y +} + +define void @test_token_not_first() convergent { +; CHECK-LABEL: @test_token_not_first( +; CHECK-NEXT: [[TOKEN:%.*]] = call token @llvm.experimental.convergence.entry() +; CHECK-NEXT: {{%.*}} = call i32 @g(i32 23) [ "convergencectrl"(token [[TOKEN]]) ] +; CHECK-NEXT: ret void +; + %token = call token @llvm.experimental.convergence.entry() + %x = call i32 @token_not_first(i32 23) [ "convergencectrl"(token %token) ] + ret void +} + declare void @f(i32) convergent declare i32 @g(i32) convergent diff --git a/llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll b/llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll similarity index 100% rename from llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll rename to llvm/test/Transforms/LoopVectorize/AArch64/arith-fp-frem-costs.ll diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll b/llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll index 0e55ad65cdb2c23b63abf38421768bea64ab7f84..6724afd6ca10f499c6edda182812211103bbdd0e 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/dead-ops-cost.ll @@ -410,45 +410,49 @@ define void @gather_interleave_group_with_dead_insert_pos(i64 %N, ptr noalias %s ; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR2]] { ; CHECK-NEXT: [[ENTRY:.*]]: ; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 0) -; CHECK-NEXT: [[TMP0:%.*]] = add nuw i64 [[SMAX]], 3 -; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2 +; CHECK-NEXT: [[TMP0:%.*]] = add nuw i64 [[SMAX]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 -; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP2]], 16 +; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 4 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], [[TMP4]] ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] ; CHECK: [[VECTOR_PH]]: -; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 16 -; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 -; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i64 16, i64 [[N_MOD_VF]] -; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP4]] -; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC]], 4 +; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 4 +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], [[TMP6]] +; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] +; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC]], 2 +; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64() +; CHECK-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 4 +; CHECK-NEXT: [[TMP9:%.*]] = call @llvm.stepvector.nxv4i64() +; CHECK-NEXT: [[TMP10:%.*]] = add [[TMP9]], zeroinitializer +; CHECK-NEXT: [[TMP11:%.*]] = mul [[TMP10]], shufflevector ( insertelement ( poison, i64 2, i64 0), poison, zeroinitializer) +; CHECK-NEXT: [[INDUCTION:%.*]] = add zeroinitializer, [[TMP11]] +; CHECK-NEXT: [[TMP12:%.*]] = mul i64 2, [[TMP8]] +; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[TMP12]], i64 0 +; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[STEP_ADD:%.*]] = add <8 x i64> [[VEC_IND]], -; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 -; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 32 -; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP6]] -; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <32 x i8>, ptr [[TMP7]], align 1 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <32 x i8> [[WIDE_VEC]], <32 x i8> poison, <8 x i32> -; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <32 x i8> [[WIDE_VEC]], <32 x i8> poison, <8 x i32> -; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <32 x i8>, ptr [[TMP8]], align 1 -; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <32 x i8> [[WIDE_VEC2]], <32 x i8> poison, <8 x i32> -; CHECK-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <32 x i8> [[WIDE_VEC2]], <32 x i8> poison, <8 x i32> -; CHECK-NEXT: [[TMP11:%.*]] = zext <8 x i8> [[STRIDED_VEC4]] to <8 x i32> -; CHECK-NEXT: [[TMP12:%.*]] = zext <8 x i8> [[STRIDED_VEC5]] to <8 x i32> -; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[DST]], <8 x i64> [[VEC_IND]] -; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[DST]], <8 x i64> [[STEP_ADD]] -; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP11]], <8 x ptr> [[TMP13]], i32 4, <8 x i1> ) -; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP12]], <8 x ptr> [[TMP14]], i32 4, <8 x i1> ) -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 -; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[STEP_ADD]], -; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 0 +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP13]] +; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP14]], align 1 +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i8( [[WIDE_VEC]]) +; CHECK-NEXT: [[TMP15:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 +; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 +; CHECK-NEXT: [[TMP17:%.*]] = zext [[TMP16]] to +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[DST]], [[VEC_IND]] +; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[TMP17]], [[TMP18]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP8]] +; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], [[DOTSPLAT]] +; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] ; CHECK: [[MIDDLE_BLOCK]]: -; CHECK-NEXT: br label %[[SCALAR_PH]] +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] ; CHECK: [[SCALAR_PH]]: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] ; CHECK-NEXT: br label %[[LOOP:.*]] @@ -462,9 +466,9 @@ define void @gather_interleave_group_with_dead_insert_pos(i64 %N, ptr noalias %s ; CHECK-NEXT: [[EXT:%.*]] = zext i8 [[L_1]] to i32 ; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV]] ; CHECK-NEXT: store i32 [[EXT]], ptr [[GEP_DST]], align 4 -; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 4 +; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 2 ; CHECK-NEXT: [[EC:%.*]] = icmp slt i64 [[IV]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT:.*]], !llvm.loop [[LOOP21:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP21:![0-9]+]] ; CHECK: [[EXIT]]: ; CHECK-NEXT: ret void ; @@ -481,7 +485,7 @@ loop: %ext = zext i8 %l.1 to i32 %gep.dst = getelementptr i32, ptr %dst, i64 %iv store i32 %ext, ptr %gep.dst, align 4 - %iv.next = add nsw i64 %iv, 4 + %iv.next = add nsw i64 %iv, 2 %ec = icmp slt i64 %iv, %N br i1 %ec, label %loop, label %exit diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/epi-crash-vplan.ll b/llvm/test/Transforms/LoopVectorize/RISCV/epi-crash-vplan.ll index 3553e2aed82be83cceb2b5a847cf3913ebd5316a..03efe87dd17c9a47a4f2c0e9846ecd0a372a4c25 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/epi-crash-vplan.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/epi-crash-vplan.ll @@ -22,30 +22,28 @@ define dso_local void @foo(ptr nocapture noundef readnone %A, ptr nocapture noun ; CHECK: for.body.preheader: ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[TC]] to i64 ; CHECK-NEXT: [[TMP0:%.*]] = tail call i32 @llvm.vscale.i32() -; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[TMP0]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = tail call i32 @llvm.vscale.i32() -; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[TMP2]], 1 -; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], -1 -; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement poison, i32 33, i32 [[TMP4]] -; CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.stepvector.nxv2i32() +; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP2]], -1 +; CHECK-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement poison, i32 33, i32 [[TMP4]] +; CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.stepvector.nxv1i32() ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[PREV_EVL:%.*]] = phi i32 [ [[TMP1]], [[FOR_BODY_PREHEADER]] ], [ [[VEC_LEN:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi [ [[VECTOR_RECUR_INIT]], [[FOR_BODY_PREHEADER]] ], [ [[VEC_IND6:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_IND6]] = phi [ [[TMP5]], [[FOR_BODY_PREHEADER]] ], [ [[VEC_IND_NEXT9:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[PREV_EVL:%.*]] = phi i32 [ [[TMP0]], [[FOR_BODY_PREHEADER]] ], [ [[VEC_LEN:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi [ [[VECTOR_RECUR_INIT]], [[FOR_BODY_PREHEADER]] ], [ [[VEC_IND4:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND4]] = phi [ [[TMP3]], [[FOR_BODY_PREHEADER]] ], [ [[VEC_IND_NEXT5:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[INDEX]] -; CHECK-NEXT: [[VEC_LEN]] = tail call i32 @llvm.experimental.get.vector.length.i64(i64 [[TMP6]], i32 2, i1 true) -; CHECK-NEXT: [[DOTSPLATINSERT7:%.*]] = insertelement poison, i32 [[VEC_LEN]], i64 0 -; CHECK-NEXT: [[DOTSPLAT8:%.*]] = shufflevector [[DOTSPLATINSERT7]], poison, zeroinitializer +; CHECK-NEXT: [[VEC_LEN]] = tail call i32 @llvm.experimental.get.vector.length.i64(i64 [[TMP6]], i32 1, i1 true) +; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement poison, i32 [[VEC_LEN]], i64 0 +; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector [[DOTSPLATINSERT2]], poison, zeroinitializer ; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[PREV_EVL]], -1 -; CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.experimental.vp.splice.nxv2i32( [[VECTOR_RECUR]], [[VEC_IND6]], i32 [[TMP7]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), i32 [[PREV_EVL]], i32 [[VEC_LEN]]) -; CHECK-NEXT: [[VP_OP:%.*]] = tail call @llvm.vp.add.nxv2i32( [[TMP8]], [[VEC_IND6]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), i32 [[VEC_LEN]]) +; CHECK-NEXT: [[TMP8:%.*]] = tail call @llvm.experimental.vp.splice.nxv1i32( [[VECTOR_RECUR]], [[VEC_IND4]], i32 [[TMP7]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), i32 [[PREV_EVL]], i32 [[VEC_LEN]]) +; CHECK-NEXT: [[VP_OP:%.*]] = tail call @llvm.vp.add.nxv1i32( [[TMP8]], [[VEC_IND4]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), i32 [[VEC_LEN]]) ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i64 [[INDEX]] -; CHECK-NEXT: tail call void @llvm.vp.store.nxv2i32.p0( [[VP_OP]], ptr [[TMP9]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), i32 [[VEC_LEN]]), !tbaa [[TBAA4:![0-9]+]] +; CHECK-NEXT: tail call void @llvm.vp.store.nxv1i32.p0( [[VP_OP]], ptr [[TMP9]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), i32 [[VEC_LEN]]), !tbaa [[TBAA4:![0-9]+]] ; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[VEC_LEN]] to i64 ; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP10]] -; CHECK-NEXT: [[VEC_IND_NEXT9]] = add [[VEC_IND6]], [[DOTSPLAT8]] +; CHECK-NEXT: [[VEC_IND_NEXT5]] = add [[VEC_IND4]], [[DOTSPLAT3]] ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[WIDE_TRIP_COUNT]] ; CHECK-NEXT: br i1 [[TMP11]], label [[FOR_COND_CLEANUP]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK: for.cond.cleanup: diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll b/llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll index fa346b4eac02d4388b7adda97ff7651085710f0a..6477f14e3c6984a050b8a0dd08fe1dea0a31239c 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/interleaved-cost.ll @@ -6,26 +6,26 @@ define void @i8_factor_2(ptr %data, i64 %n) { entry: br label %for.body ; CHECK-LABEL: Checking a loop in 'i8_factor_2' -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 2 for VF 4: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 4: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 2 for VF 8: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 8: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 3 for VF 16: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 3 for VF 16: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 5 for VF 32: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 5 for VF 32: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 2 for VF vscale x 1: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF vscale x 1: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 2 for VF vscale x 2: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF vscale x 2: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 2 for VF vscale x 4: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF vscale x 4: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 3 for VF vscale x 8: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 3 for VF vscale x 8: INTERLEAVE-GROUP with factor 2 at , ir<%p0> -; CHECK: Cost of 5 for VF vscale x 16: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> -; CHECK: Cost of 5 for VF vscale x 16: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 3 for VF 2: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 3 for VF 2: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 3 for VF 8: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 3 for VF 8: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 4 for VF 16: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 4 for VF 16: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 8 for VF 32: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 8 for VF 32: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 3 for VF vscale x 1: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 3 for VF vscale x 1: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 3 for VF vscale x 2: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 3 for VF vscale x 2: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 3 for VF vscale x 4: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 3 for VF vscale x 4: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 4 for VF vscale x 8: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 4 for VF vscale x 8: INTERLEAVE-GROUP with factor 2 at , ir<%p0> +; CHECK: Cost of 8 for VF vscale x 16: INTERLEAVE-GROUP with factor 2 at %l0, ir<%p0> +; CHECK: Cost of 8 for VF vscale x 16: INTERLEAVE-GROUP with factor 2 at , ir<%p0> for.body: %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ] %p0 = getelementptr inbounds %i8.2, ptr %data, i64 %i, i32 0 @@ -49,16 +49,16 @@ define void @i8_factor_3(ptr %data, i64 %n) { entry: br label %for.body ; CHECK-LABEL: Checking a loop in 'i8_factor_3' -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 3 at , ir<%p0> -; CHECK: Cost of 2 for VF 4: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 4: INTERLEAVE-GROUP with factor 3 at , ir<%p0> -; CHECK: Cost of 3 for VF 8: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> -; CHECK: Cost of 3 for VF 8: INTERLEAVE-GROUP with factor 3 at , ir<%p0> -; CHECK: Cost of 5 for VF 16: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> -; CHECK: Cost of 5 for VF 16: INTERLEAVE-GROUP with factor 3 at , ir<%p0> -; CHECK: Cost of 9 for VF 32: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> -; CHECK: Cost of 9 for VF 32: INTERLEAVE-GROUP with factor 3 at , ir<%p0> +; CHECK: Cost of 6 for VF 2: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> +; CHECK: Cost of 6 for VF 2: INTERLEAVE-GROUP with factor 3 at , ir<%p0> +; CHECK: Cost of 12 for VF 4: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> +; CHECK: Cost of 12 for VF 4: INTERLEAVE-GROUP with factor 3 at , ir<%p0> +; CHECK: Cost of 24 for VF 8: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> +; CHECK: Cost of 24 for VF 8: INTERLEAVE-GROUP with factor 3 at , ir<%p0> +; CHECK: Cost of 48 for VF 16: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> +; CHECK: Cost of 48 for VF 16: INTERLEAVE-GROUP with factor 3 at , ir<%p0> +; CHECK: Cost of 96 for VF 32: INTERLEAVE-GROUP with factor 3 at %l0, ir<%p0> +; CHECK: Cost of 96 for VF 32: INTERLEAVE-GROUP with factor 3 at , ir<%p0> for.body: %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ] %p0 = getelementptr inbounds %i8.3, ptr %data, i64 %i, i32 0 @@ -86,16 +86,16 @@ define void @i8_factor_4(ptr %data, i64 %n) { entry: br label %for.body ; CHECK-LABEL: Checking a loop in 'i8_factor_4' -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 4 at , ir<%p0> -; CHECK: Cost of 2 for VF 4: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 4: INTERLEAVE-GROUP with factor 4 at , ir<%p0> -; CHECK: Cost of 3 for VF 8: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> -; CHECK: Cost of 3 for VF 8: INTERLEAVE-GROUP with factor 4 at , ir<%p0> -; CHECK: Cost of 5 for VF 16: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> -; CHECK: Cost of 5 for VF 16: INTERLEAVE-GROUP with factor 4 at , ir<%p0> -; CHECK: Cost of 9 for VF 32: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> -; CHECK: Cost of 9 for VF 32: INTERLEAVE-GROUP with factor 4 at , ir<%p0> +; CHECK: Cost of 8 for VF 2: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> +; CHECK: Cost of 8 for VF 2: INTERLEAVE-GROUP with factor 4 at , ir<%p0> +; CHECK: Cost of 16 for VF 4: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> +; CHECK: Cost of 16 for VF 4: INTERLEAVE-GROUP with factor 4 at , ir<%p0> +; CHECK: Cost of 32 for VF 8: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> +; CHECK: Cost of 32 for VF 8: INTERLEAVE-GROUP with factor 4 at , ir<%p0> +; CHECK: Cost of 64 for VF 16: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> +; CHECK: Cost of 64 for VF 16: INTERLEAVE-GROUP with factor 4 at , ir<%p0> +; CHECK: Cost of 128 for VF 32: INTERLEAVE-GROUP with factor 4 at %l0, ir<%p0> +; CHECK: Cost of 128 for VF 32: INTERLEAVE-GROUP with factor 4 at , ir<%p0> for.body: %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ] %p0 = getelementptr inbounds %i8.4, ptr %data, i64 %i, i32 0 @@ -127,14 +127,14 @@ define void @i8_factor_5(ptr %data, i64 %n) { entry: br label %for.body ; CHECK-LABEL: Checking a loop in 'i8_factor_5' -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 5 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 5 at , ir<%p0> -; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 5 at %l0, ir<%p0> -; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 5 at , ir<%p0> -; CHECK: Cost of 5 for VF 8: INTERLEAVE-GROUP with factor 5 at %l0, ir<%p0> -; CHECK: Cost of 5 for VF 8: INTERLEAVE-GROUP with factor 5 at , ir<%p0> -; CHECK: Cost of 9 for VF 16: INTERLEAVE-GROUP with factor 5 at %l0, ir<%p0> -; CHECK: Cost of 9 for VF 16: INTERLEAVE-GROUP with factor 5 at , ir<%p0> +; CHECK: Cost of 10 for VF 2: INTERLEAVE-GROUP with factor 5 at %l0, ir<%p0> +; CHECK: Cost of 10 for VF 2: INTERLEAVE-GROUP with factor 5 at , ir<%p0> +; CHECK: Cost of 20 for VF 4: INTERLEAVE-GROUP with factor 5 at %l0, ir<%p0> +; CHECK: Cost of 20 for VF 4: INTERLEAVE-GROUP with factor 5 at , ir<%p0> +; CHECK: Cost of 40 for VF 8: INTERLEAVE-GROUP with factor 5 at %l0, ir<%p0> +; CHECK: Cost of 40 for VF 8: INTERLEAVE-GROUP with factor 5 at , ir<%p0> +; CHECK: Cost of 80 for VF 16: INTERLEAVE-GROUP with factor 5 at %l0, ir<%p0> +; CHECK: Cost of 80 for VF 16: INTERLEAVE-GROUP with factor 5 at , ir<%p0> for.body: %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ] %p0 = getelementptr inbounds %i8.5, ptr %data, i64 %i, i32 0 @@ -170,14 +170,14 @@ define void @i8_factor_6(ptr %data, i64 %n) { entry: br label %for.body ; CHECK-LABEL: Checking a loop in 'i8_factor_6' -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 6 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 6 at , ir<%p0> -; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 6 at %l0, ir<%p0> -; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 6 at , ir<%p0> -; CHECK: Cost of 5 for VF 8: INTERLEAVE-GROUP with factor 6 at %l0, ir<%p0> -; CHECK: Cost of 5 for VF 8: INTERLEAVE-GROUP with factor 6 at , ir<%p0> -; CHECK: Cost of 9 for VF 16: INTERLEAVE-GROUP with factor 6 at %l0, ir<%p0> -; CHECK: Cost of 9 for VF 16: INTERLEAVE-GROUP with factor 6 at , ir<%p0> +; CHECK: Cost of 12 for VF 2: INTERLEAVE-GROUP with factor 6 at %l0, ir<%p0> +; CHECK: Cost of 12 for VF 2: INTERLEAVE-GROUP with factor 6 at , ir<%p0> +; CHECK: Cost of 24 for VF 4: INTERLEAVE-GROUP with factor 6 at %l0, ir<%p0> +; CHECK: Cost of 24 for VF 4: INTERLEAVE-GROUP with factor 6 at , ir<%p0> +; CHECK: Cost of 48 for VF 8: INTERLEAVE-GROUP with factor 6 at %l0, ir<%p0> +; CHECK: Cost of 48 for VF 8: INTERLEAVE-GROUP with factor 6 at , ir<%p0> +; CHECK: Cost of 96 for VF 16: INTERLEAVE-GROUP with factor 6 at %l0, ir<%p0> +; CHECK: Cost of 96 for VF 16: INTERLEAVE-GROUP with factor 6 at , ir<%p0> for.body: %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ] %p0 = getelementptr inbounds %i8.6, ptr %data, i64 %i, i32 0 @@ -217,14 +217,14 @@ define void @i8_factor_7(ptr %data, i64 %n) { entry: br label %for.body ; CHECK-LABEL: Checking a loop in 'i8_factor_7' -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 7 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 7 at , ir<%p0> -; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 7 at %l0, ir<%p0> -; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 7 at , ir<%p0> -; CHECK: Cost of 5 for VF 8: INTERLEAVE-GROUP with factor 7 at %l0, ir<%p0> -; CHECK: Cost of 5 for VF 8: INTERLEAVE-GROUP with factor 7 at , ir<%p0> -; CHECK: Cost of 9 for VF 16: INTERLEAVE-GROUP with factor 7 at %l0, ir<%p0> -; CHECK: Cost of 9 for VF 16: INTERLEAVE-GROUP with factor 7 at , ir<%p0> +; CHECK: Cost of 14 for VF 2: INTERLEAVE-GROUP with factor 7 at %l0, ir<%p0> +; CHECK: Cost of 14 for VF 2: INTERLEAVE-GROUP with factor 7 at , ir<%p0> +; CHECK: Cost of 28 for VF 4: INTERLEAVE-GROUP with factor 7 at %l0, ir<%p0> +; CHECK: Cost of 28 for VF 4: INTERLEAVE-GROUP with factor 7 at , ir<%p0> +; CHECK: Cost of 56 for VF 8: INTERLEAVE-GROUP with factor 7 at %l0, ir<%p0> +; CHECK: Cost of 56 for VF 8: INTERLEAVE-GROUP with factor 7 at , ir<%p0> +; CHECK: Cost of 112 for VF 16: INTERLEAVE-GROUP with factor 7 at %l0, ir<%p0> +; CHECK: Cost of 112 for VF 16: INTERLEAVE-GROUP with factor 7 at , ir<%p0> for.body: %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ] %p0 = getelementptr inbounds %i8.7, ptr %data, i64 %i, i32 0 @@ -268,14 +268,14 @@ define void @i8_factor_8(ptr %data, i64 %n) { entry: br label %for.body ; CHECK-LABEL: Checking a loop in 'i8_factor_8' -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 8 at %l0, ir<%p0> -; CHECK: Cost of 2 for VF 2: INTERLEAVE-GROUP with factor 8 at , ir<%p0> -; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 8 at %l0, ir<%p0> -; CHECK: Cost of 3 for VF 4: INTERLEAVE-GROUP with factor 8 at , ir<%p0> -; CHECK: Cost of 5 for VF 8: INTERLEAVE-GROUP with factor 8 at %l0, ir<%p0> -; CHECK: Cost of 5 for VF 8: INTERLEAVE-GROUP with factor 8 at , ir<%p0> -; CHECK: Cost of 9 for VF 16: INTERLEAVE-GROUP with factor 8 at %l0, ir<%p0> -; CHECK: Cost of 9 for VF 16: INTERLEAVE-GROUP with factor 8 at , ir<%p0> +; CHECK: Cost of 16 for VF 2: INTERLEAVE-GROUP with factor 8 at %l0, ir<%p0> +; CHECK: Cost of 16 for VF 2: INTERLEAVE-GROUP with factor 8 at , ir<%p0> +; CHECK: Cost of 32 for VF 4: INTERLEAVE-GROUP with factor 8 at %l0, ir<%p0> +; CHECK: Cost of 32 for VF 4: INTERLEAVE-GROUP with factor 8 at , ir<%p0> +; CHECK: Cost of 64 for VF 8: INTERLEAVE-GROUP with factor 8 at %l0, ir<%p0> +; CHECK: Cost of 64 for VF 8: INTERLEAVE-GROUP with factor 8 at , ir<%p0> +; CHECK: Cost of 128 for VF 16: INTERLEAVE-GROUP with factor 8 at %l0, ir<%p0> +; CHECK: Cost of 128 for VF 16: INTERLEAVE-GROUP with factor 8 at , ir<%p0> for.body: %i = phi i64 [ 0, %entry ], [ %i.next, %for.body ] %p0 = getelementptr inbounds %i8.8, ptr %data, i64 %i, i32 0 diff --git a/llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i16-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i32-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i64-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/gather-i8-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/handle-iptr-with-data-layout-to-not-assert.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/handle-iptr-with-data-layout-to-not-assert.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/handle-iptr-with-data-layout-to-not-assert.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f32-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-f64-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-half.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i16-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2-indices-0u.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-01u.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3-indices-0uu.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-012u.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-01uu.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-01uu.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-01uu.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-0uuu.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-0uuu.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4-indices-0uuu.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i32-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i64-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-load-i8-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f32-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-f64-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i16-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i32-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i64-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-2.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-3.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-4.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-5.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-5.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-5.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-6.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-7.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-7.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-7.ll diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/interleaved-store-i8-stride-8.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i32-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-gather-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-gather-i64-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-gather-i64-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-load-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-interleaved-store-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-load-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-load-i32.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-load-i32.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i32.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-load-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-load-i64.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i64.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-load-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-load-i8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-load-i8.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i32-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i32-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-scatter-i64-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-store-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i32.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-store-i32.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i32.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-store-i64.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i64.ll diff --git a/llvm/test/Analysis/CostModel/X86/masked-store-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/masked-store-i8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/masked-store-i8.ll diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i16-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i16-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i32-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i32-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i64-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i64-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i8-with-i8-index.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/scatter-i8-with-i8-index.ll diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i16.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/strided-load-i16.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i16.ll diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i32.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/strided-load-i32.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i32.ll diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i64.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/strided-load-i64.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i64.ll diff --git a/llvm/test/Analysis/CostModel/X86/strided-load-i8.ll b/llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll similarity index 100% rename from llvm/test/Analysis/CostModel/X86/strided-load-i8.ll rename to llvm/test/Transforms/LoopVectorize/X86/CostModel/strided-load-i8.ll diff --git a/llvm/test/Transforms/LowerTypeTests/drop_type_test.ll b/llvm/test/Transforms/LowerTypeTests/drop_type_test.ll new file mode 100644 index 0000000000000000000000000000000000000000..e1d0573924a4e78d117e8886b92a80992af18ee6 --- /dev/null +++ b/llvm/test/Transforms/LowerTypeTests/drop_type_test.ll @@ -0,0 +1,22 @@ +; RUN: opt -S -passes=lowertypetests -lowertypetests-drop-type-tests=all < %s | FileCheck %s + +define void @func() { +entry: + %0 = tail call i1 @llvm.type.test(ptr null, metadata !"foo") + br i1 %0, label %exit, label %trap + +trap: + unreachable + +exit: + ret void + ; CHECK-LABEL: entry: + ; CHECK-NEXT: br i1 true, label %exit, label %trap + ; CHECK-LABEL: trap: + ; CHECK-NEXT: unreachable + ; CHECK-LABEL: exit: + ; CHECK-NEXT: ret void +} + +declare i1 @llvm.type.test(ptr, metadata) #0 +attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } diff --git a/llvm/test/Transforms/LowerTypeTests/drop_type_test_phi.ll b/llvm/test/Transforms/LowerTypeTests/drop_type_test_phi.ll index 3cf4d447605da7166f75681afb429fa76c77fd06..820865826dc7aab1a63ff1b71928adda2c431716 100644 --- a/llvm/test/Transforms/LowerTypeTests/drop_type_test_phi.ll +++ b/llvm/test/Transforms/LowerTypeTests/drop_type_test_phi.ll @@ -1,5 +1,5 @@ ; Test to ensure dropping of type tests can handle a phi feeding the assume. -; RUN: opt -S -passes=lowertypetests -lowertypetests-drop-type-tests -mtriple=x86_64-unknown-linux-gnu %s | FileCheck %s +; RUN: opt -S -passes=lowertypetests -lowertypetests-drop-type-tests=assume -mtriple=x86_64-unknown-linux-gnu %s | FileCheck %s target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" diff --git a/llvm/test/Transforms/PGOProfile/memprof.ll b/llvm/test/Transforms/PGOProfile/memprof.ll index e1457ca7251ed88a0474c95bd506fb267b62e664..205eeb8878989d2e58b9881e58d7d0c78e812e88 100644 --- a/llvm/test/Transforms/PGOProfile/memprof.ll +++ b/llvm/test/Transforms/PGOProfile/memprof.ll @@ -66,6 +66,18 @@ ;; Check that the total sizes are reported if requested. ; RUN: opt < %s -passes='memprof-use' -pgo-warn-missing-function -S -memprof-report-hinted-sizes 2>&1 | FileCheck %s --check-prefixes=TOTALSIZES +;; Make sure we emit a random hotness seed if requested. +; RUN: llvm-profdata merge -memprof-random-hotness %S/Inputs/memprof.memprofraw --profiled-binary %S/Inputs/memprof.exe -o %t.memprofdatarand 2>&1 | FileCheck %s --check-prefix=RAND +; RAND: random hotness seed = +;; Can't check the exact values, but make sure applying the random profile +;; succeeds with the same stats +; RUN: opt < %s -passes='memprof-use' -pgo-warn-missing-function -S -stats 2>&1 | FileCheck %s --check-prefixes=ALL,MEMPROFONLY,MEMPROFSTATS + +;; Make sure we use a specific random hotness seed if requested. +; RUN: llvm-profdata merge -memprof-random-hotness -memprof-random-hotness-seed=1730170724 %S/Inputs/memprof.memprofraw --profiled-binary %S/Inputs/memprof.exe -o %t.memprofdatarand2 2>&1 | FileCheck %s --check-prefix=RAND2 +; RAND2: random hotness seed = 1730170724 +; RUN: opt < %s -passes='memprof-use' -pgo-warn-missing-function -S -stats 2>&1 | FileCheck %s --check-prefixes=MEMPROFRAND2,ALL,MEMPROFONLY,MEMPROFSTATS + ; MEMPROFMATCHINFO: MemProf notcold context with id 1093248920606587996 has total profiled size 10 is matched ; MEMPROFMATCHINFO: MemProf notcold context with id 5725971306423925017 has total profiled size 10 is matched ; MEMPROFMATCHINFO: MemProf notcold context with id 6792096022461663180 has total profiled size 10 is matched @@ -372,6 +384,13 @@ for.end: ; preds = %for.cond ; MEMPROFNOCOLINFO: ![[C10]] = !{i64 -4535090212904553409} ; MEMPROFNOCOLINFO: ![[C11]] = !{i64 3577763375057267810} +;; For the specific random seed, this is the expected order of hotness +; MEMPROFRAND2: !"cold" +; MEMPROFRAND2: !"cold" +; MEMPROFRAND2: !"cold" +; MEMPROFRAND2: !"hot" +; MEMPROFRAND2: !"hot" + ; MEMPROFSTATS: 8 memprof - Number of alloc contexts in memory profile. ; MEMPROFSTATS: 10 memprof - Number of callsites in memory profile. ; MEMPROFSTATS: 6 memprof - Number of functions having valid memory profile. diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pr50392.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr50392.ll new file mode 100644 index 0000000000000000000000000000000000000000..4a024cc4c0309c1b7a7d02a693b77ae7be635e6f --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/X86/pr50392.ll @@ -0,0 +1,64 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -O3 -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -O3 -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -O3 -S < %s | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -O3 -S < %s | FileCheck %s --check-prefixes=AVX,AVX2 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -passes="default" -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -passes="default" -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -passes="default" -S < %s | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -passes="default" -S < %s | FileCheck %s --check-prefixes=AVX,AVX2 + +define <4 x double> @PR50392(<4 x double> %a, <4 x double> %b) { +; SSE-LABEL: @PR50392( +; SSE-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; SSE-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; SSE-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; SSE-NEXT: [[VECEXT10:%.*]] = extractelement <4 x double> [[B]], i64 2 +; SSE-NEXT: [[VECEXT11:%.*]] = extractelement <4 x double> [[B]], i64 3 +; SSE-NEXT: [[ADD12:%.*]] = fadd double [[VECEXT10]], [[VECEXT11]] +; SSE-NEXT: [[SHUFFLE:%.*]] = insertelement <4 x double> [[TMP4]], double [[ADD12]], i64 3 +; SSE-NEXT: ret <4 x double> [[SHUFFLE]] +; +; AVX1-LABEL: @PR50392( +; AVX1-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; AVX1-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; AVX1-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; AVX1-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; AVX1-NEXT: [[VECEXT10:%.*]] = extractelement <4 x double> [[B]], i64 2 +; AVX1-NEXT: [[VECEXT11:%.*]] = extractelement <4 x double> [[B]], i64 3 +; AVX1-NEXT: [[ADD12:%.*]] = fadd double [[VECEXT10]], [[VECEXT11]] +; AVX1-NEXT: [[SHUFFLE:%.*]] = insertelement <4 x double> [[TMP4]], double [[ADD12]], i64 3 +; AVX1-NEXT: ret <4 x double> [[SHUFFLE]] +; +; AVX2-LABEL: @PR50392( +; AVX2-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; AVX2-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; AVX2-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; AVX2-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; AVX2-NEXT: [[SHIFT:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; AVX2-NEXT: [[TMP5:%.*]] = fadd <4 x double> [[B]], [[SHIFT]] +; AVX2-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x double> [[TMP4]], <4 x double> [[TMP5]], <4 x i32> +; AVX2-NEXT: ret <4 x double> [[SHUFFLE]] +; + %vecext = extractelement <4 x double> %a, i32 0 + %vecext1 = extractelement <4 x double> %a, i32 1 + %add = fadd double %vecext, %vecext1 + %vecinit = insertelement <4 x double> poison, double %add, i32 0 + %vecext2 = extractelement <4 x double> %a, i32 2 + %vecext3 = extractelement <4 x double> %a, i32 3 + %add4 = fadd double %vecext2, %vecext3 + %vecinit5 = insertelement <4 x double> %vecinit, double %add4, i32 1 + %vecext6 = extractelement <4 x double> %b, i32 0 + %vecext7 = extractelement <4 x double> %b, i32 1 + %add8 = fadd double %vecext6, %vecext7 + %vecinit9 = insertelement <4 x double> %vecinit5, double %add8, i32 2 + %vecext10 = extractelement <4 x double> %b, i32 2 + %vecext11 = extractelement <4 x double> %b, i32 3 + %add12 = fadd double %vecext10, %vecext11 + %vecinit13 = insertelement <4 x double> %vecinit9, double %add12, i32 3 + %shuffle = shufflevector <4 x double> %vecinit13, <4 x double> %a, <4 x i32> + ret <4 x double> %shuffle +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX: {{.*}} diff --git a/llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll b/llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll new file mode 100644 index 0000000000000000000000000000000000000000..1d4cee45b668565f201955627d61b34fed0909b6 --- /dev/null +++ b/llvm/test/Transforms/PhaseOrdering/X86/pr94546.ll @@ -0,0 +1,47 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -O3 -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -O3 -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -O3 -S < %s | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -O3 -S < %s | FileCheck %s --check-prefixes=AVX,AVX2 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64 -passes="default" -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v2 -passes="default" -S < %s | FileCheck %s --check-prefixes=SSE +; RUN: opt -mtriple=x86_64-- -mcpu=btver2 -passes="default" -S < %s | FileCheck %s --check-prefixes=AVX,AVX1 +; RUN: opt -mtriple=x86_64-- -mcpu=x86-64-v3 -passes="default" -S < %s | FileCheck %s --check-prefixes=AVX,AVX2 + +define <4 x double> @PR94546(<4 x double> %a, <4 x double> %b) { +; SSE-LABEL: @PR94546( +; SSE-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; SSE-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; SSE-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; SSE-NEXT: ret <4 x double> [[TMP4]] +; +; AVX-LABEL: @PR94546( +; AVX-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> +; AVX-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> +; AVX-NEXT: [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]] +; AVX-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <4 x i32> +; AVX-NEXT: ret <4 x double> [[TMP4]] +; + %vecext = extractelement <4 x double> %a, i32 0 + %vecext1 = extractelement <4 x double> %a, i32 1 + %add = fadd double %vecext, %vecext1 + %vecinit = insertelement <4 x double> poison, double %add, i32 0 + %vecext2 = extractelement <4 x double> %a, i32 2 + %vecext3 = extractelement <4 x double> %a, i32 3 + %add4 = fadd double %vecext2, %vecext3 + %vecinit5 = insertelement <4 x double> %vecinit, double %add4, i32 1 + %vecext6 = extractelement <4 x double> %b, i32 0 + %vecext7 = extractelement <4 x double> %b, i32 1 + %add8 = fadd double %vecext6, %vecext7 + %vecinit9 = insertelement <4 x double> %vecinit5, double %add8, i32 2 + %vecext10 = extractelement <4 x double> %b, i32 2 + %vecext11 = extractelement <4 x double> %b, i32 3 + %add12 = fadd double %vecext10, %vecext11 + %vecinit13 = insertelement <4 x double> %vecinit9, double %add12, i32 3 + %shuffle = shufflevector <4 x double> %vecinit13, <4 x double> %a, <4 x i32> + ret <4 x double> %shuffle +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX1: {{.*}} +; AVX2: {{.*}} diff --git a/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll b/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll index bcea147d724f53bf50bc56164f4f55fba8634325..f23043f0c47f4a37b23a9fae885e27675bf4046b 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/conversion-fp16.ll @@ -453,14 +453,9 @@ define void @fpround_v16xf32_v16xf16(ptr %s0, ptr %d0) { ; ; CHECK-F16C-LABEL: define void @fpround_v16xf32_v16xf16( ; CHECK-F16C-SAME: ptr [[S0:%.*]], ptr [[D0:%.*]]) #[[ATTR0]] { -; CHECK-F16C-NEXT: [[S8:%.*]] = getelementptr inbounds float, ptr [[S0]], i64 8 -; CHECK-F16C-NEXT: [[D8:%.*]] = getelementptr inbounds half, ptr [[D0]], i64 8 -; CHECK-F16C-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr [[S0]], align 4 -; CHECK-F16C-NEXT: [[TMP2:%.*]] = fptrunc <8 x float> [[TMP1]] to <8 x half> -; CHECK-F16C-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr [[S8]], align 4 -; CHECK-F16C-NEXT: [[TMP4:%.*]] = fptrunc <8 x float> [[TMP3]] to <8 x half> -; CHECK-F16C-NEXT: store <8 x half> [[TMP2]], ptr [[D0]], align 2 -; CHECK-F16C-NEXT: store <8 x half> [[TMP4]], ptr [[D8]], align 2 +; CHECK-F16C-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr [[S0]], align 4 +; CHECK-F16C-NEXT: [[TMP2:%.*]] = fptrunc <16 x float> [[TMP1]] to <16 x half> +; CHECK-F16C-NEXT: store <16 x half> [[TMP2]], ptr [[D0]], align 2 ; CHECK-F16C-NEXT: ret void ; ; CHECK-AVX512-LABEL: define void @fpround_v16xf32_v16xf16( diff --git a/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll b/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll new file mode 100644 index 0000000000000000000000000000000000000000..e94868c7b9e5b38f3ce17306b20ca5f134288e00 --- /dev/null +++ b/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll @@ -0,0 +1,146 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=CHECK,AVX + +; Fold "shuffle (binop (shuffle, shuffle)), undef" --> "binop (shuffle), (shuffle)" + +declare void @use_v4f64(<4 x double>) + +define <4 x double> @fadd_v4f64(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_v4f64( +; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[POST:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[POST1:%.*]] = shufflevector <4 x double> [[POST]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: ret <4 x double> [[POST1]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + ret <4 x double> %post +} + +define <4 x double> @fadd_v4f64_poison_idx(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_v4f64_poison_idx( +; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[POST:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[POST1:%.*]] = shufflevector <4 x double> [[POST]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: ret <4 x double> [[POST1]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + ret <4 x double> %post +} + +define <4 x double> @fadd_mixed_types(<4 x double> %a, <2 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_mixed_types( +; CHECK-SAME: <4 x double> [[A:%.*]], <2 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[B]], <2 x double> poison, <4 x i32> +; CHECK-NEXT: [[POST:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[POST1:%.*]] = shufflevector <4 x double> [[POST]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: ret <4 x double> [[POST1]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <2 x double> %b, <2 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + ret <4 x double> %post +} + +; Negative test - multiple use of fadd +define <4 x double> @fadd_v4f64_multiuse_op(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_v4f64_multiuse_op( +; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[OP:%.*]] = fadd <4 x double> [[A1]], [[B1]] +; CHECK-NEXT: [[POST:%.*]] = shufflevector <4 x double> [[OP]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: call void @use_v4f64(<4 x double> [[OP]]) +; CHECK-NEXT: ret <4 x double> [[POST]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + call void @use_v4f64(<4 x double> %op) + ret <4 x double> %post +} + +; Negative test - multiple use of inner shuffle +define <4 x double> @fadd_v4f64_multiuse_shuffle(<4 x double> %a, <4 x double> %b) { +; CHECK-LABEL: define <4 x double> @fadd_v4f64_multiuse_shuffle( +; CHECK-SAME: <4 x double> [[A:%.*]], <4 x double> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x double> [[A]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x double> [[B]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: [[OP:%.*]] = fadd <4 x double> [[A1]], [[B1]] +; CHECK-NEXT: [[POST:%.*]] = shufflevector <4 x double> [[OP]], <4 x double> poison, <4 x i32> +; CHECK-NEXT: call void @use_v4f64(<4 x double> [[A1]]) +; CHECK-NEXT: ret <4 x double> [[POST]] +; + %a1 = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> + %b1 = shufflevector <4 x double> %b, <4 x double> poison, <4 x i32> + %op = fadd <4 x double> %a1, %b1 + %post = shufflevector <4 x double> %op, <4 x double> poison, <4 x i32> + call void @use_v4f64(<4 x double> %a1) + ret <4 x double> %post +} + +define <4 x i32> @sdiv_v4i32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: define <4 x i32> @sdiv_v4i32( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[POST:%.*]] = sdiv <4 x i32> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[POST1:%.*]] = shufflevector <4 x i32> [[POST]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[POST1]] +; + %a1 = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> + %b1 = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> + %op = sdiv <4 x i32> %a1, %b1 + %post = shufflevector <4 x i32> %op, <4 x i32> poison, <4 x i32> + ret <4 x i32> %post +} + +; Negative test - don't introduce poison element into div/rem instruction +define <4 x i32> @sdiv_v4i32_poison(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: define <4 x i32> @sdiv_v4i32_poison( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[OP:%.*]] = sdiv <4 x i32> [[A1]], [[B1]] +; CHECK-NEXT: [[POST:%.*]] = shufflevector <4 x i32> [[OP]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[POST]] +; + %a1 = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> + %b1 = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> + %op = sdiv <4 x i32> %a1, %b1 + %post = shufflevector <4 x i32> %op, <4 x i32> poison, <4 x i32> + ret <4 x i32> %post +} + +; Negative test - don't introduce poison element into div/rem instruction +define <4 x i32> @sdiv_v4i32_poison_idx(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: define <4 x i32> @sdiv_v4i32_poison_idx( +; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[OP:%.*]] = sdiv <4 x i32> [[A1]], [[B1]] +; CHECK-NEXT: [[POST:%.*]] = shufflevector <4 x i32> [[OP]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: ret <4 x i32> [[POST]] +; + %a1 = shufflevector <4 x i32> %a, <4 x i32> poison, <4 x i32> + %b1 = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> + %op = sdiv <4 x i32> %a1, %b1 + %post = shufflevector <4 x i32> %op, <4 x i32> poison, <4 x i32> + ret <4 x i32> %post +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; AVX: {{.*}} +; SSE: {{.*}} diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected index 7336947a3f57a06e4eb02162a8d63a5f2bacfb44..2dc30cd112e4658be29490f0cdd17f4c1a77d4d4 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm.s.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py // RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s v_bfrev_b32 v5, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s index 489bd1801d864a3f4177aec9deaa3ed0daec7ecb..76f8e7880d836e0e4f899a74f0bcebd31af8b988 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s @@ -1,3 +1,6 @@ -// RUN: not llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s +// RUN: not llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECKA %s +// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --check-prefixes=CHECKB %s v_bfrev_b32 v5, v299 + +v_bfrev_b32 v5, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected index 0a0ad51d15e056d7ae2c5f4fdec85cd27dda179d..fffe299f3d16f6bbfd9ea8a65f1ac93b2f703ef6 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_err.s.expected @@ -1,5 +1,11 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py -// RUN: not llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py +// RUN: not llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECKA %s +// RUN: not llvm-mc -triple=amdgcn %s 2>&1 | FileCheck --check-prefixes=CHECKB %s v_bfrev_b32 v5, v299 -// CHECK: :[[@LINE-1]]:17: error: register index is out of range +// CHECKA: :[[@LINE-1]]:17: error: register index is out of range +// CHECKB: :[[@LINE-2]]:17: error: register index is out of range + +v_bfrev_b32 v5, v1 +// CHECKA: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e] +// CHECKB: v_bfrev_b32_e32 v5, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s new file mode 100644 index 0000000000000000000000000000000000000000..ea03c5a6911fadc211b9ec54d76c8be878be0e38 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s @@ -0,0 +1,5 @@ +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +v_bfrev_b32 v5, v1 + +v_bfrev_b32 v1, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s.expected new file mode 100644 index 0000000000000000000000000000000000000000..57f72ed406fb407c29d9c02ad24e7ab22a012bba --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort.s.expected @@ -0,0 +1,8 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +v_bfrev_b32 v1, v1 +// CHECK: v_bfrev_b32_e32 v1, v1 ; encoding: [0x01,0x71,0x02,0x7e] + +v_bfrev_b32 v5, v1 +// CHECK: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e] diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s new file mode 100644 index 0000000000000000000000000000000000000000..d60b3bda29eda2dc6083314048af0436cbeee7d6 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s @@ -0,0 +1,9 @@ +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +v_bfrev_b32 v5, v1 //This is comment A + +v_bfrev_b32 v1, v1 +// This is comment B + +// This is comment C +v_bfrev_b32 v2, v1 diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s.expected new file mode 100644 index 0000000000000000000000000000000000000000..6924880032717ea88991a3d55d77ce2f04906d88 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_sort_with_comment.s.expected @@ -0,0 +1,13 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --sort +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +v_bfrev_b32 v1, v1 +// CHECK: v_bfrev_b32_e32 v1, v1 ; encoding: [0x01,0x71,0x02,0x7e] +// This is comment B + +// This is comment C +v_bfrev_b32 v2, v1 +// CHECK: v_bfrev_b32_e32 v2, v1 ; encoding: [0x01,0x71,0x04,0x7e] + +v_bfrev_b32 v5, v1 //This is comment A +// CHECK: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e] diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s new file mode 100644 index 0000000000000000000000000000000000000000..63240174cdde55f960b59279c80e8f44019cc230 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s @@ -0,0 +1,10 @@ +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +//this is commentA +v_bfrev_b32 v5, v1 + +v_bfrev_b32 v5, v1 + +//this is commentB + +//this is commentB diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s.expected new file mode 100644 index 0000000000000000000000000000000000000000..8203b90040ba4ed57bfd3e6ba4878c10630b92fd --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_asm_unique.s.expected @@ -0,0 +1,10 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique +// RUN: llvm-mc -triple=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefixes=CHECK %s + +//this is commentA +v_bfrev_b32 v5, v1 +// CHECK: v_bfrev_b32_e32 v5, v1 ; encoding: [0x01,0x71,0x0a,0x7e] + +//this is commentB + +//this is commentB diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected index a6f7abcb1774ac068837584fb26518619eaea1bc..b3cbaff6d1c7ef8ea25bc09ec98c6be5bad026cc 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm.txt.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK %s 0x00,0x00,0x00,0x7e diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt new file mode 100644 index 0000000000000000000000000000000000000000..3d0d49ddeea4256925ea7bfe24d5f8fb24ca0879 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK %s + +0x00,0x00,0x00,0x7e + +0x00,0x00,0x00,0x7e diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt.expected new file mode 100644 index 0000000000000000000000000000000000000000..32bddb20628dad10b4e20db4a8ef13b5d4188738 --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_dasm_unique.txt.expected @@ -0,0 +1,5 @@ +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK %s + +0x00,0x00,0x00,0x7e +# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e] diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected index 03a5ec3c559dbfc194779980ae8e048db2bbda6a..7b6b832801625b486c411ff412858ac945c0b0a3 100644 --- a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/Inputs/amdgpu_multirun_dasm.txt.expected @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py # RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK,CHECKA %s # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding %s 2>&1 | FileCheck -check-prefixes=CHECK,CHECKB %s diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-sort.test b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-sort.test new file mode 100644 index 0000000000000000000000000000000000000000..f8972ffabf0999c9b46f0c29216c1bf8b9bf85fc --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-sort.test @@ -0,0 +1,7 @@ +# REQUIRES: amdgpu-registered-target +## Check that sort is working + +# RUN: cp -f %S/Inputs/amdgpu_asm_sort.s %t.s && %update_mc_test_checks --sort %t.s +# RUN: diff -u %S/Inputs/amdgpu_asm_sort.s.expected %t.s +# RUN: cp -f %S/Inputs/amdgpu_asm_sort_with_comment.s %t.s && %update_mc_test_checks --sort %t.s +# RUN: diff -u %S/Inputs/amdgpu_asm_sort_with_comment.s.expected %t.s diff --git a/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-unique.test b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-unique.test new file mode 100644 index 0000000000000000000000000000000000000000..8a5d83462cad73d05c8054e717850f302d10d9ad --- /dev/null +++ b/llvm/test/tools/UpdateTestChecks/update_mc_test_checks/amdgpu-unique.test @@ -0,0 +1,7 @@ +# REQUIRES: amdgpu-registered-target +## Check that unique is working + +# RUN: cp -f %S/Inputs/amdgpu_asm_unique.s %t.s && %update_mc_test_checks --unique %t.s +# RUN: diff -u %S/Inputs/amdgpu_asm_unique.s.expected %t.s +# RUN: cp -f %S/Inputs/amdgpu_dasm_unique.txt %t.txt && %update_mc_test_checks --unique %t.txt +# RUN: diff -u %S/Inputs/amdgpu_dasm_unique.txt.expected %t.txt diff --git a/llvm/test/tools/llvm-objdump/X86/disassemble-color.s b/llvm/test/tools/llvm-objdump/X86/disassemble-color.s new file mode 100644 index 0000000000000000000000000000000000000000..4e1d82562fb546aceb752427c3801b8c0f9d1243 --- /dev/null +++ b/llvm/test/tools/llvm-objdump/X86/disassemble-color.s @@ -0,0 +1,21 @@ +# UNSUPPORTED: system-windows +# RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t +# RUN: llvm-objdump -d --no-show-raw-insn --disassembler-color=on %t | FileCheck %s --check-prefix=ATT +# RUN: llvm-objdump -d --no-show-raw-insn --disassembler-color=on -M intel %t | FileCheck %s --check-prefix=INTEL + +# ATT: <.text>: +# ATT-NEXT: leaq (%rdx,%rax,4), %rbx +# ATT-NEXT: movq (,%rax), %rbx +# ATT-NEXT: leaq 0x3(%rdx,%rax), %rbx +# ATT-NEXT: movq $0x3, %rax + +# INTEL: <.text>: +# INTEL-NEXT: lea rbx, [rdx + 4*rax] +# INTEL-NEXT: mov rbx, qword ptr [1*rax] +# INTEL-NEXT: lea rbx, [rdx + rax + 0x3] +# INTEL-NEXT: mov rax, 0x3 + +leaq (%rdx,%rax,4), %rbx +movq (,%rax), %rbx +leaq 3(%rdx,%rax), %rbx +movq $3, %rax diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp index 59f0f1f1fae89920abfa942232a44677e002ff13..f7023aa966adf6f3ca5bc00bf6a0a7f1b814bce3 100644 --- a/llvm/tools/llvm-profdata/llvm-profdata.cpp +++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp @@ -342,6 +342,15 @@ cl::opt MemProfFullSchema( "memprof-full-schema", cl::Hidden, cl::sub(MergeSubcommand), cl::desc("Use the full schema for serialization"), cl::init(false)); +static cl::opt + MemprofGenerateRandomHotness("memprof-random-hotness", cl::init(false), + cl::Hidden, cl::sub(MergeSubcommand), + cl::desc("Generate random hotness values")); +static cl::opt MemprofGenerateRandomHotnessSeed( + "memprof-random-hotness-seed", cl::init(0), cl::Hidden, + cl::sub(MergeSubcommand), + cl::desc("Random hotness seed to use (0 to generate new seed)")); + // Options specific to overlap subcommand. cl::opt BaseFilename(cl::Positional, cl::Required, cl::desc(""), @@ -641,7 +650,8 @@ struct WriterContext { SmallSet &WriterErrorCodes, uint64_t ReservoirSize = 0, uint64_t MaxTraceLength = 0) : Writer(IsSparse, ReservoirSize, MaxTraceLength, DoWritePrevVersion, - MemProfVersionRequested, MemProfFullSchema), + MemProfVersionRequested, MemProfFullSchema, + MemprofGenerateRandomHotness, MemprofGenerateRandomHotnessSeed), ErrLock(ErrLock), WriterErrorCodes(WriterErrorCodes) {} }; diff --git a/llvm/unittests/ADT/CMakeLists.txt b/llvm/unittests/ADT/CMakeLists.txt index 745e4d9fb74a4a6d98308c97d429c38c81c89e86..b0077d5b54a3ee5ad6819c5e01e801678765da90 100644 --- a/llvm/unittests/ADT/CMakeLists.txt +++ b/llvm/unittests/ADT/CMakeLists.txt @@ -86,6 +86,7 @@ add_llvm_unittest(ADTTests StringSetTest.cpp StringSwitchTest.cpp TinyPtrVectorTest.cpp + TrieRawHashMapTest.cpp TwineTest.cpp TypeSwitchTest.cpp TypeTraitsTest.cpp diff --git a/llvm/unittests/ADT/TrieRawHashMapTest.cpp b/llvm/unittests/ADT/TrieRawHashMapTest.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c9081f547812e90a54f44411591cb7ad4001245b --- /dev/null +++ b/llvm/unittests/ADT/TrieRawHashMapTest.cpp @@ -0,0 +1,346 @@ +//===- TrieRawHashMapTest.cpp ---------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/TrieRawHashMap.h" +#include "llvm/ADT/Twine.h" +#include "llvm/Support/Endian.h" +#include "llvm/Support/SHA1.h" +#include "gtest/gtest.h" + +using namespace llvm; + +namespace llvm { +class TrieRawHashMapTestHelper { +public: + TrieRawHashMapTestHelper() = default; + + void setTrie(ThreadSafeTrieRawHashMapBase *T) { Trie = T; } + + ThreadSafeTrieRawHashMapBase::PointerBase getRoot() const { + return Trie->getRoot(); + } + unsigned getStartBit(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getStartBit(P); + } + unsigned getNumBits(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getNumBits(P); + } + unsigned getNumSlotUsed(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getNumSlotUsed(P); + } + unsigned getNumTries() const { return Trie->getNumTries(); } + std::string + getTriePrefixAsString(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getTriePrefixAsString(P); + } + ThreadSafeTrieRawHashMapBase::PointerBase + getNextTrie(ThreadSafeTrieRawHashMapBase::PointerBase P) const { + return Trie->getNextTrie(P); + } + +private: + ThreadSafeTrieRawHashMapBase *Trie = nullptr; +}; +} // namespace llvm + +namespace { +template +class SimpleTrieHashMapTest : public TrieRawHashMapTestHelper, + public ::testing::Test { +public: + using NumType = DataType; + using HashType = std::array; + using TrieType = ThreadSafeTrieRawHashMap; + + TrieType &createTrie(size_t RootBits, size_t SubtrieBits) { + auto &Ret = Trie.emplace(RootBits, SubtrieBits); + TrieRawHashMapTestHelper::setTrie(&Ret); + return Ret; + } + + void destroyTrie() { Trie.reset(); } + ~SimpleTrieHashMapTest() { destroyTrie(); } + + // Use the number itself as hash to test the pathological case. + static HashType hash(uint64_t Num) { + uint64_t HashN = + llvm::support::endian::byte_swap(Num, llvm::endianness::big); + HashType Hash; + memcpy(&Hash[0], &HashN, sizeof(HashType)); + return Hash; + }; + +private: + std::optional Trie; +}; + +using SmallNodeTrieTest = SimpleTrieHashMapTest; + +TEST_F(SmallNodeTrieTest, TrieAllocation) { + NumType Numbers[] = { + 0x0, std::numeric_limits::max(), 0x1, 0x2, + 0x3, std::numeric_limits::max() - 1u, + }; + + unsigned ExpectedTries[] = { + 1, // Allocate Root. + 1, // Both on the root. + 64, // 0 and 1 sinks all the way down. + 64, // no new allocation needed. + 65, // need a new node between 2 and 3. + 65 + 63, // 63 new allocation to sink two big numbers all the way. + }; + + const char *ExpectedPrefix[] = { + "", // Root. + "", // Root. + "00000000000000[0000000]", + "00000000000000[0000000]", + "00000000000000[0000001]", + "ffffffffffffff[1111111]", + }; + + // Use root and subtrie sizes of 1 so this gets sunk quite deep. + auto &Trie = createTrie(/*RootBits=*/1, /*SubtrieBits=*/1); + + for (unsigned I = 0; I < 6; ++I) { + // Lookup first to exercise hint code for deep tries. + TrieType::pointer Lookup = Trie.find(hash(Numbers[I])); + EXPECT_FALSE(Lookup); + + Trie.insert(Lookup, TrieType::value_type(hash(Numbers[I]), Numbers[I])); + EXPECT_EQ(getNumTries(), ExpectedTries[I]); + EXPECT_EQ(getTriePrefixAsString(getNextTrie(getRoot())), ExpectedPrefix[I]); + } +} + +TEST_F(SmallNodeTrieTest, TrieStructure) { + NumType Numbers[] = { + // Three numbers that will nest deeply to test (1) sinking subtries and + // (2) deep, non-trivial hints. + std::numeric_limits::max(), + std::numeric_limits::max() - 2u, + std::numeric_limits::max() - 3u, + // One number to stay at the top-level. + 0x37, + }; + + // Use root and subtrie sizes of 1 so this gets sunk quite deep. + auto &Trie = createTrie(/*RootBits=*/1, /*SubtrieBits=*/1); + + for (NumType N : Numbers) { + // Lookup first to exercise hint code for deep tries. + TrieType::pointer Lookup = Trie.find(hash(N)); + EXPECT_FALSE(Lookup); + + Trie.insert(Lookup, TrieType::value_type(hash(N), N)); + } + for (NumType N : Numbers) { + TrieType::pointer Lookup = Trie.find(hash(N)); + EXPECT_TRUE(Lookup); + if (!Lookup) + continue; + EXPECT_EQ(hash(N), Lookup->Hash); + EXPECT_EQ(N, Lookup->Data); + + // Confirm a subsequent insertion fails to overwrite by trying to insert a + // bad value. + auto Result = Trie.insert(Lookup, TrieType::value_type(hash(N), N - 1)); + EXPECT_EQ(N, Result->Data); + } + + // Check the trie so we can confirm the structure is correct. Each subtrie + // should have 2 slots. The root's index=0 should have the content for + // 0x37 directly, and index=1 should be a linked-list of subtries, finally + // ending with content for (max-2) and (max-3). + // + // Note: This structure is not exhaustive (too expensive to update tests), + // but it does test that the dump format is somewhat readable and that the + // basic structure is correct. + // + // Note: This test requires that the trie reads bytes starting from index 0 + // of the array of uint8_t, and then reads each byte's bits from high to low. + + // Check the Trie. + // We should allocated a total of 64 SubTries for 64 bit hash. + ASSERT_EQ(getNumTries(), 64u); + // Check the root trie. Two slots and both are used. + ASSERT_EQ(getNumSlotUsed(getRoot()), 2u); + // Check last subtrie. + // Last allocated trie is the next node in the allocation chain. + auto LastAlloctedSubTrie = getNextTrie(getRoot()); + ASSERT_EQ(getTriePrefixAsString(LastAlloctedSubTrie), + "ffffffffffffff[1111110]"); + ASSERT_EQ(getStartBit(LastAlloctedSubTrie), 63u); + ASSERT_EQ(getNumBits(LastAlloctedSubTrie), 1u); + ASSERT_EQ(getNumSlotUsed(LastAlloctedSubTrie), 2u); +} + +TEST_F(SmallNodeTrieTest, TrieStructureSmallFinalSubtrie) { + NumType Numbers[] = { + // Three numbers that will nest deeply to test (1) sinking subtries and + // (2) deep, non-trivial hints. + std::numeric_limits::max(), + std::numeric_limits::max() - 2u, + std::numeric_limits::max() - 3u, + // One number to stay at the top-level. + 0x37, + }; + + // Use subtrie size of 5 to avoid hitting 64 evenly, making the final subtrie + // small. + auto &Trie = createTrie(/*RootBits=*/8, /*SubtrieBits=*/5); + + for (NumType N : Numbers) { + // Lookup first to exercise hint code for deep tries. + TrieType::pointer Lookup = Trie.find(hash(N)); + EXPECT_FALSE(Lookup); + + Trie.insert(Lookup, TrieType::value_type(hash(N), N)); + } + for (NumType N : Numbers) { + TrieType::pointer Lookup = Trie.find(hash(N)); + ASSERT_TRUE(Lookup); + EXPECT_EQ(hash(N), Lookup->Hash); + EXPECT_EQ(N, Lookup->Data); + + // Confirm a subsequent insertion fails to overwrite by trying to insert a + // bad value. + auto Result = Trie.insert(Lookup, TrieType::value_type(hash(N), N - 1)); + EXPECT_EQ(N, Result->Data); + } + + // Check the trie so we can confirm the structure is correct. The root + // should have 2^8=256 slots, most subtries should have 2^5=32 slots, and the + // deepest subtrie should have 2^1=2 slots (since (64-8)mod(5)=1). + // should have 2 slots. The root's index=0 should have the content for + // 0x37 directly, and index=1 should be a linked-list of subtries, finally + // ending with content for (max-2) and (max-3). + // + // Note: This structure is not exhaustive (too expensive to update tests), + // but it does test that the dump format is somewhat readable and that the + // basic structure is correct. + // + // Note: This test requires that the trie reads bytes starting from index 0 + // of the array of uint8_t, and then reads each byte's bits from high to low. + + // Check the Trie. + // 64 bit hash = 8 + 5 * 11 + 1, so 1 root, 11 8bit subtrie and 1 last level + // subtrie, 13 total. + ASSERT_EQ(getNumTries(), 13u); + // Check the root trie. Two slots and both are used. + ASSERT_EQ(getNumSlotUsed(getRoot()), 2u); + // Check last subtrie. + // Last allocated trie is the next node in the allocation chain. + auto LastAlloctedSubTrie = getNextTrie(getRoot()); + ASSERT_EQ(getTriePrefixAsString(LastAlloctedSubTrie), + "ffffffffffffff[1111110]"); + ASSERT_EQ(getStartBit(LastAlloctedSubTrie), 63u); + ASSERT_EQ(getNumBits(LastAlloctedSubTrie), 1u); + ASSERT_EQ(getNumSlotUsed(LastAlloctedSubTrie), 2u); +} + +TEST_F(SmallNodeTrieTest, TrieDestructionLoop) { + // Test destroying large Trie. Make sure there is no recursion that can + // overflow the stack. + + // Limit the tries to 2 slots (1 bit) to generate subtries at a higher rate. + auto &Trie = createTrie(/*NumRootBits=*/1, /*NumSubtrieBits=*/1); + + // Fill them up. Pick a MaxN high enough to cause a stack overflow in debug + // builds. + static constexpr uint64_t MaxN = 100000; + for (uint64_t N = 0; N != MaxN; ++N) { + HashType Hash = hash(N); + Trie.insert(TrieType::pointer(), TrieType::value_type(Hash, NumType{N})); + } + + // Destroy tries. If destruction is recursive and MaxN is high enough, these + // will both fail. + destroyTrie(); +} + +struct NumWithDestructorT { + uint64_t Num; + llvm::function_ref DestructorCallback; + ~NumWithDestructorT() { DestructorCallback(); } +}; + +using NodeWithDestructorTrieTest = SimpleTrieHashMapTest; + +TEST_F(NodeWithDestructorTrieTest, TrieDestructionLoop) { + // Test destroying large Trie. Make sure there is no recursion that can + // overflow the stack. + + // Limit the tries to 2 slots (1 bit) to generate subtries at a higher rate. + auto &Trie = createTrie(/*NumRootBits=*/1, /*NumSubtrieBits=*/1); + + // Fill them up. Pick a MaxN high enough to cause a stack overflow in debug + // builds. + static constexpr uint64_t MaxN = 100000; + + uint64_t DestructorCalled = 0; + auto DtorCallback = [&DestructorCalled]() { ++DestructorCalled; }; + for (uint64_t N = 0; N != MaxN; ++N) { + HashType Hash = hash(N); + Trie.insert(TrieType::pointer(), + TrieType::value_type(Hash, NumType{N, DtorCallback})); + } + // Reset the count after all the temporaries get destroyed. + DestructorCalled = 0; + + // Destroy tries. If destruction is recursive and MaxN is high enough, these + // will both fail. + destroyTrie(); + + // Count the number of destructor calls during `destroyTrie()`. + ASSERT_EQ(DestructorCalled, MaxN); +} + +using NumStrNodeTrieTest = SimpleTrieHashMapTest; + +TEST_F(NumStrNodeTrieTest, TrieInsertLazy) { + for (unsigned RootBits : {2, 3, 6, 10}) { + for (unsigned SubtrieBits : {2, 3, 4}) { + auto &Trie = createTrie(RootBits, SubtrieBits); + for (int I = 0, E = 1000; I != E; ++I) { + TrieType::pointer Lookup; + HashType H = hash(I); + if (I & 1) + Lookup = Trie.find(H); + + auto insertNum = [&](uint64_t Num) { + std::string S = Twine(I).str(); + auto Hash = hash(Num); + return Trie.insertLazy( + Hash, [&](TrieType::LazyValueConstructor C) { C(std::move(S)); }); + }; + auto S1 = insertNum(I); + // The address of the Data should be the same. + EXPECT_EQ(&S1->Data, &insertNum(I)->Data); + + auto insertStr = [&](std::string S) { + int Num = std::stoi(S); + return insertNum(Num); + }; + std::string S2 = S1->Data; + // The address of the Data should be the same. + EXPECT_EQ(&S1->Data, &insertStr(S2)->Data); + } + for (int I = 0, E = 1000; I != E; ++I) { + std::string S = Twine(I).str(); + TrieType::pointer Lookup = Trie.find(hash(I)); + EXPECT_TRUE(Lookup); + if (!Lookup) + continue; + EXPECT_EQ(S, Lookup->Data); + } + } + } +} +} // end anonymous namespace diff --git a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp index 3df72ec8115b6aa1fa19479311f98195e8dfca0b..ffedb2c74220f040e2e89e8d740072b1468b7f83 100644 --- a/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp +++ b/llvm/unittests/CodeGen/AArch64SelectionDAGTest.cpp @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "../lib/Target/AArch64/AArch64ISelLowering.h" #include "llvm/Analysis/MemoryLocation.h" #include "llvm/Analysis/OptimizationRemarkEmitter.h" #include "llvm/AsmParser/Parser.h" @@ -167,6 +168,18 @@ TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_EXTRACT_SUBVECTOR) { EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 7u); } +TEST_F(AArch64SelectionDAGTest, ComputeNumSignBits_VASHR) { + SDLoc Loc; + auto VecVT = MVT::v8i8; + auto Shift = DAG->getConstant(4, Loc, MVT::i32); + auto Vec0 = DAG->getConstant(1, Loc, VecVT); + auto Op1 = DAG->getNode(AArch64ISD::VASHR, Loc, VecVT, Vec0, Shift); + EXPECT_EQ(DAG->ComputeNumSignBits(Op1), 8u); + auto VecA = DAG->getConstant(0xaa, Loc, VecVT); + auto Op2 = DAG->getNode(AArch64ISD::VASHR, Loc, VecVT, VecA, Shift); + EXPECT_EQ(DAG->ComputeNumSignBits(Op2), 5u); +} + TEST_F(AArch64SelectionDAGTest, SimplifyDemandedVectorElts_EXTRACT_SUBVECTOR) { TargetLowering TL(*TM); diff --git a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp index dc40e5893b65e2329f86e1f8d0122a96c0f285cb..1402c1d5b1398bae43ad8328bd09a48f5eca367b 100644 --- a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp +++ b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp @@ -193,9 +193,8 @@ TEST_F(SelectionDAGPatternMatchTest, matchBinaryOp) { SDValue And = DAG->getNode(ISD::AND, DL, Int32VT, Op0, Op1); SDValue Xor = DAG->getNode(ISD::XOR, DL, Int32VT, Op1, Op0); SDValue Or = DAG->getNode(ISD::OR, DL, Int32VT, Op0, Op1); - SDNodeFlags DisFlags; - DisFlags.setDisjoint(true); - SDValue DisOr = DAG->getNode(ISD::OR, DL, Int32VT, Op0, Op3, DisFlags); + SDValue DisOr = + DAG->getNode(ISD::OR, DL, Int32VT, Op0, Op3, SDNodeFlags::Disjoint); SDValue SMax = DAG->getNode(ISD::SMAX, DL, Int32VT, Op0, Op1); SDValue SMin = DAG->getNode(ISD::SMIN, DL, Int32VT, Op1, Op0); SDValue UMax = DAG->getNode(ISD::UMAX, DL, Int32VT, Op0, Op1); @@ -293,10 +292,8 @@ TEST_F(SelectionDAGPatternMatchTest, matchUnaryOp) { SDValue Op3 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 3, Int32VT); SDValue ZExt = DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op0); - SDNodeFlags NNegFlags; - NNegFlags.setNonNeg(true); SDValue ZExtNNeg = - DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op3, NNegFlags); + DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op3, SDNodeFlags::NonNeg); SDValue SExt = DAG->getNode(ISD::SIGN_EXTEND, DL, Int64VT, Op0); SDValue Trunc = DAG->getNode(ISD::TRUNCATE, DL, Int32VT, Op1); diff --git a/llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp b/llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp index 63cf3a397cb30ddb1ecfc25364a8efb364794b40..bc996711f7ec500f3b1fc7ce8eac157f0ebdfcb5 100644 --- a/llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp +++ b/llvm/unittests/ExecutionEngine/Orc/ObjectLinkingLayerTest.cpp @@ -65,6 +65,36 @@ TEST_F(ObjectLinkingLayerTest, AddLinkGraph) { EXPECT_THAT_EXPECTED(ES.lookup(&JD, "_X"), Succeeded()); } +TEST_F(ObjectLinkingLayerTest, ResourceTracker) { + // This test transfers allocations to previously unknown ResourceTrackers, + // while increasing the number of trackers in the ObjectLinkingLayer, which + // may invalidate some iterators internally. + std::vector Trackers; + for (unsigned I = 0; I < 64; I++) { + auto G = std::make_unique("foo", Triple("x86_64-apple-darwin"), + 8, llvm::endianness::little, + x86_64::getEdgeKindName); + + auto &Sec1 = G->createSection("__data", MemProt::Read | MemProt::Write); + auto &B1 = G->createContentBlock(Sec1, BlockContent, + orc::ExecutorAddr(0x1000), 8, 0); + llvm::SmallString<0> SymbolName; + SymbolName += "_X"; + SymbolName += std::to_string(I); + G->addDefinedSymbol(B1, 4, SymbolName, 4, Linkage::Strong, Scope::Default, + false, false); + + auto RT1 = JD.createResourceTracker(); + EXPECT_THAT_ERROR(ObjLinkingLayer.add(RT1, std::move(G)), Succeeded()); + EXPECT_THAT_EXPECTED(ES.lookup(&JD, SymbolName), Succeeded()); + + auto RT2 = JD.createResourceTracker(); + RT1->transferTo(*RT2); + + Trackers.push_back(RT2); + } +} + TEST_F(ObjectLinkingLayerTest, ClaimLateDefinedWeakSymbols) { // Check that claiming weak symbols works as expected. // diff --git a/llvm/unittests/IR/VerifierTest.cpp b/llvm/unittests/IR/VerifierTest.cpp index 91cd35a10e9b926a6d313d602000377fcc1fdfd1..462578a34da837d9183cca1e98bbd02b3d6dc112 100644 --- a/llvm/unittests/IR/VerifierTest.cpp +++ b/llvm/unittests/IR/VerifierTest.cpp @@ -385,5 +385,35 @@ TEST(VerifierTest, AtomicRMW) { << Error; } +TEST(VerifierTest, GetElementPtrInst) { + LLVMContext C; + Module M("M", C); + FunctionType *FTy = FunctionType::get(Type::getVoidTy(C), /*isVarArg=*/false); + Function *F = Function::Create(FTy, Function::ExternalLinkage, "foo", M); + BasicBlock *Entry = BasicBlock::Create(C, "entry", F); + ReturnInst *RI = ReturnInst::Create(C, Entry); + + FixedVectorType *V2P1Ty = FixedVectorType::get(PointerType::get(C, 1), 2); + FixedVectorType *V2P2Ty = FixedVectorType::get(PointerType::get(C, 2), 2); + + Instruction *GEPVec = GetElementPtrInst::Create( + Type::getInt8Ty(C), ConstantAggregateZero::get(V2P1Ty), + {ConstantVector::getSplat(ElementCount::getFixed(2), + ConstantInt::get(Type::getInt64Ty(C), 0))}, + Entry); + + GEPVec->insertBefore(RI); + + // Break the address space of the source value + GEPVec->getOperandUse(0).set(ConstantAggregateZero::get(V2P2Ty)); + + std::string Error; + raw_string_ostream ErrorOS(Error); + EXPECT_TRUE(verifyFunction(*F, &ErrorOS)); + EXPECT_TRUE( + StringRef(Error).starts_with("GEP address space doesn't match type")) + << Error; +} + } // end anonymous namespace } // end namespace llvm diff --git a/llvm/unittests/SandboxIR/SandboxIRTest.cpp b/llvm/unittests/SandboxIR/SandboxIRTest.cpp index 97113b303f72e5e9098386bfd62d4828d2437278..874c32c2d4398ff03eb18e56b61e6f3f1ca91901 100644 --- a/llvm/unittests/SandboxIR/SandboxIRTest.cpp +++ b/llvm/unittests/SandboxIR/SandboxIRTest.cpp @@ -21,7 +21,7 @@ #include "llvm/SandboxIR/Utils.h" #include "llvm/SandboxIR/Value.h" #include "llvm/Support/SourceMgr.h" -#include "gmock/gmock-matchers.h" +#include "gmock/gmock.h" #include "gtest/gtest.h" using namespace llvm; @@ -5962,3 +5962,100 @@ TEST_F(SandboxIRTest, CheckClassof) { EXPECT_NE(&sandboxir::CLASS::classof, &sandboxir::Instruction::classof); #include "llvm/SandboxIR/Values.def" } + +TEST_F(SandboxIRTest, InstructionCallbacks) { + parseIR(C, R"IR( + define void @foo(ptr %ptr, i8 %val) { + ret void + } + )IR"); + Function &LLVMF = *M->getFunction("foo"); + sandboxir::Context Ctx(C); + + auto &F = *Ctx.createFunction(&LLVMF); + auto &BB = *F.begin(); + sandboxir::Argument *Ptr = F.getArg(0); + sandboxir::Argument *Val = F.getArg(1); + sandboxir::Instruction *Ret = &BB.front(); + + SmallVector Inserted; + auto InsertCbId = Ctx.registerCreateInstrCallback( + [&Inserted](sandboxir::Instruction *I) { Inserted.push_back(I); }); + + SmallVector Removed; + auto RemoveCbId = Ctx.registerEraseInstrCallback( + [&Removed](sandboxir::Instruction *I) { Removed.push_back(I); }); + + // Keep the moved instruction and the instruction pointed by the Where + // iterator so we can check both callback arguments work as expected. + SmallVector> + Moved; + auto MoveCbId = Ctx.registerMoveInstrCallback( + [&Moved](sandboxir::Instruction *I, const sandboxir::BBIterator &Where) { + // Use a nullptr to signal "move to end" to keep it single. We only + // have a basic block in this test case anyway. + if (Where == Where.getNodeParent()->end()) + Moved.push_back(std::make_pair(I, nullptr)); + else + Moved.push_back(std::make_pair(I, &*Where)); + }); + + // Two more insertion callbacks, to check that they're called in registration + // order. + SmallVector Order; + auto CheckOrderInsertCbId1 = Ctx.registerCreateInstrCallback( + [&Order](sandboxir::Instruction *I) { Order.push_back(1); }); + + auto CheckOrderInsertCbId2 = Ctx.registerCreateInstrCallback( + [&Order](sandboxir::Instruction *I) { Order.push_back(2); }); + + Ctx.save(); + auto *NewI = sandboxir::StoreInst::create(Val, Ptr, /*Align=*/std::nullopt, + Ret->getIterator(), Ctx); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI)); + EXPECT_THAT(Removed, testing::IsEmpty()); + EXPECT_THAT(Moved, testing::IsEmpty()); + EXPECT_THAT(Order, testing::ElementsAre(1, 2)); + + Ret->moveBefore(NewI); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI)); + EXPECT_THAT(Removed, testing::IsEmpty()); + EXPECT_THAT(Moved, testing::ElementsAre(std::make_pair(Ret, NewI))); + + Ret->eraseFromParent(); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI)); + EXPECT_THAT(Removed, testing::ElementsAre(Ret)); + EXPECT_THAT(Moved, testing::ElementsAre(std::make_pair(Ret, NewI))); + + NewI->eraseFromParent(); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI)); + EXPECT_THAT(Removed, testing::ElementsAre(Ret, NewI)); + EXPECT_THAT(Moved, testing::ElementsAre(std::make_pair(Ret, NewI))); + + // Check that after revert the callbacks have been called for the inverse + // operations of the changes made so far. + Ctx.revert(); + EXPECT_THAT(Inserted, testing::ElementsAre(NewI, NewI, Ret)); + EXPECT_THAT(Removed, testing::ElementsAre(Ret, NewI, NewI)); + EXPECT_THAT(Moved, testing::ElementsAre(std::make_pair(Ret, NewI), + std::make_pair(Ret, nullptr))); + EXPECT_THAT(Order, testing::ElementsAre(1, 2, 1, 2, 1, 2)); + + // Check that deregistration works. Do an operation of each type after + // deregistering callbacks and check. + Inserted.clear(); + Removed.clear(); + Moved.clear(); + Ctx.unregisterCreateInstrCallback(InsertCbId); + Ctx.unregisterEraseInstrCallback(RemoveCbId); + Ctx.unregisterMoveInstrCallback(MoveCbId); + Ctx.unregisterCreateInstrCallback(CheckOrderInsertCbId1); + Ctx.unregisterCreateInstrCallback(CheckOrderInsertCbId2); + auto *NewI2 = sandboxir::StoreInst::create(Val, Ptr, /*Align=*/std::nullopt, + Ret->getIterator(), Ctx); + Ret->moveBefore(NewI2); + Ret->eraseFromParent(); + EXPECT_THAT(Inserted, testing::IsEmpty()); + EXPECT_THAT(Removed, testing::IsEmpty()); + EXPECT_THAT(Moved, testing::IsEmpty()); +} diff --git a/llvm/unittests/Target/AMDGPU/CMakeLists.txt b/llvm/unittests/Target/AMDGPU/CMakeLists.txt index e0efb967b5941d615ac2a8a6ed0344617326ffb6..ca8f48bc393efd7ca062c057bf0b00f5250d4dfd 100644 --- a/llvm/unittests/Target/AMDGPU/CMakeLists.txt +++ b/llvm/unittests/Target/AMDGPU/CMakeLists.txt @@ -11,6 +11,7 @@ set(LLVM_LINK_COMPONENTS CodeGen CodeGenTypes Core + GlobalISel MC Support TargetParser @@ -18,6 +19,7 @@ set(LLVM_LINK_COMPONENTS add_llvm_target_unittest(AMDGPUTests AMDGPUUnitTests.cpp + CSETest.cpp DwarfRegMappings.cpp ExecMayBeModifiedBeforeAnyUse.cpp PALMetadata.cpp diff --git a/llvm/unittests/Target/AMDGPU/CSETest.cpp b/llvm/unittests/Target/AMDGPU/CSETest.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3de5b88599649a56f1c36559b8fe0b51d778d30d --- /dev/null +++ b/llvm/unittests/Target/AMDGPU/CSETest.cpp @@ -0,0 +1,74 @@ +//===- llvm/unittests/Target/AMDGPU/CSETest.cpp ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "AMDGPUTargetMachine.h" +#include "AMDGPUUnitTests.h" +#include "llvm/CodeGen/GlobalISel/CSEInfo.h" +#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h" +#include "gtest/gtest.h" + +using namespace llvm; + +TEST(AMDGPU, TestCSEForRegisterClassOrBankAndLLT) { + auto TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx1100", ""); + if (!TM) + GTEST_SKIP(); + + GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), + std::string(TM->getTargetFeatureString()), *TM); + + LLVMContext Ctx; + Module Mod("Module", Ctx); + Mod.setDataLayout(TM->createDataLayout()); + + auto *Type = FunctionType::get(Type::getVoidTy(Ctx), false); + auto *F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &Mod); + + MachineModuleInfo MMI(TM.get()); + auto MF = + std::make_unique(*F, *TM, ST, MMI.getContext(), 42); + auto *BB = MF->CreateMachineBasicBlock(); + MF->push_back(BB); + + MachineIRBuilder B(*MF); + B.setMBB(*BB); + + LLT S32{LLT::scalar(32)}; + Register R0 = B.buildCopy(S32, Register(AMDGPU::SGPR0)).getReg(0); + Register R1 = B.buildCopy(S32, Register(AMDGPU::SGPR1)).getReg(0); + + GISelCSEInfo CSEInfo; + CSEInfo.setCSEConfig(std::make_unique()); + CSEInfo.analyze(*MF); + B.setCSEInfo(&CSEInfo); + CSEMIRBuilder CSEB(B.getState()); + CSEB.setInsertPt(B.getMBB(), B.getInsertPt()); + + const RegisterBankInfo &RBI = *MF->getSubtarget().getRegBankInfo(); + + const TargetRegisterClass *SgprRC = &AMDGPU::SReg_32RegClass; + const RegisterBank *SgprRB = &RBI.getRegBank(AMDGPU::SGPRRegBankID); + MachineRegisterInfo::VRegAttrs SgprRCS32 = {SgprRC, S32}; + MachineRegisterInfo::VRegAttrs SgprRBS32 = {SgprRB, S32}; + + auto Add = CSEB.buildAdd(S32, R0, R1); + auto AddRC = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRCS32}, {R0, R1}); + auto AddRB = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRB, S32}}, {R0, R1}); + + EXPECT_NE(Add, AddRC); + EXPECT_NE(Add, AddRB); + EXPECT_NE(AddRC, AddRB); + + auto Add_CSE = CSEB.buildAdd(S32, R0, R1); + auto AddRC_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {{SgprRC, S32}}, {R0, R1}); + auto AddRB_CSE = CSEB.buildInstr(AMDGPU::G_ADD, {SgprRBS32}, {R0, R1}); + + EXPECT_EQ(Add, Add_CSE); + EXPECT_EQ(AddRC, AddRC_CSE); + EXPECT_EQ(AddRB, AddRB_CSE); +} diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 3a573ce97a152367be6aa1ba07da033e64c15f87..a61492b987dd6f889eab47b9a70bda415f7c4632 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -643,60 +643,22 @@ TEST(ParseArchString, MissingDepency) { "'zvl*b' requires 'v' or 'zve*' extension to also be specified"); } - for (StringRef Input : {"rv32i_zvbb"}) { + // These all have an implication relationship, thus should pass + for (StringRef Input : { + "rv32i_zvbb", + "rv32i_zvbc32e0p7", + "rv32i_zvbc", + "rv32i_zvkb", + "rv32i_zvkg", + "rv32i_zvkgs0p7", + "rv32i_zvkned", + "rv32i_zvknha", + "rv32i_zvksed", + "rv32i_zvksh", + "rv32i_zvknhb", + }) { EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvbb' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvbc32e0p7"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvbc32e' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvbc"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvbc' requires 'v' or 'zve64*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvkb"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvkb' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvkg"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvkg' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvkgs0p7"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvkg' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvkned"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvkned' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvknha"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvknha' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvksed"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvksed' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvksh"}) { - EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvksh' requires 'v' or 'zve*' extension to also be specified"); - } - - for (StringRef Input : {"rv32i_zvknhb"}) { - EXPECT_EQ( - toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "'zvknhb' requires 'v' or 'zve64*' extension to also be specified"); + ""); } for (StringRef Input : {"rv32i_zacas1p0"}) { diff --git a/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp b/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp index aaa8e96de6d171cc4425043de673736b8fb09656..50b78f6f48afdf70fce86e9c661ae43d7a24fca2 100644 --- a/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/LegalityTest.cpp @@ -29,7 +29,7 @@ struct LegalityTest : public testing::Test { TEST_F(LegalityTest, Legality) { parseIR(C, R"IR( -define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float %farg0, float %farg1) { +define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float %farg0, float %farg1, i64 %v0, i64 %v1) { %gep0 = getelementptr float, ptr %ptr, i32 0 %gep1 = getelementptr float, ptr %ptr, i32 1 %gep3 = getelementptr float, ptr %ptr, i32 3 @@ -42,6 +42,8 @@ define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float store i8 %arg, ptr %gep1 %fadd0 = fadd float %farg0, %farg0 %fadd1 = fadd fast float %farg1, %farg1 + %trunc0 = trunc nuw nsw i64 %v0 to i8 + %trunc1 = trunc nsw i64 %v1 to i8 ret void } )IR"); @@ -62,6 +64,8 @@ define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float auto *StI8 = cast(&*It++); auto *FAdd0 = cast(&*It++); auto *FAdd1 = cast(&*It++); + auto *Trunc0 = cast(&*It++); + auto *Trunc1 = cast(&*It++); sandboxir::LegalityAnalysis Legality; const auto &Result = Legality.canVectorize({St0, St1}); @@ -98,6 +102,13 @@ define void @foo(ptr %ptr, <2 x float> %vec2, <3 x float> %vec3, i8 %arg, float EXPECT_EQ(cast(Result).getReason(), sandboxir::ResultReason::DiffMathFlags); } + { + // Check DiffWrapFlags + const auto &Result = Legality.canVectorize({Trunc0, Trunc1}); + EXPECT_TRUE(isa(Result)); + EXPECT_EQ(cast(Result).getReason(), + sandboxir::ResultReason::DiffWrapFlags); + } } #ifndef NDEBUG @@ -124,5 +135,8 @@ TEST_F(LegalityTest, LegalityResultDump) { EXPECT_TRUE(Matches(Legality.createLegalityResult( sandboxir::ResultReason::DiffMathFlags), "Pack Reason: DiffMathFlags")); + EXPECT_TRUE(Matches(Legality.createLegalityResult( + sandboxir::ResultReason::DiffWrapFlags), + "Pack Reason: DiffWrapFlags")); } #endif // NDEBUG diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 6b8ebf96cdf383ec2aa69bc67016cb6602b04de6..792d047139466cfad1383777f4f369faae27b977 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -25,19 +25,19 @@ using namespace llvm; /// Collect the full set of implied features for a SubtargetFeature. -static void CollectImpliedFeatures(std::set &SeenFeats, +static void collectImpliedFeatures(std::set &SeenFeats, const Record *Rec) { assert(Rec->isSubClassOf("SubtargetFeature") && "Rec is not a SubtargetFeature"); SeenFeats.insert(Rec); for (const Record *Implied : Rec->getValueAsListOfDefs("Implies")) - CollectImpliedFeatures(SeenFeats, Implied); + collectImpliedFeatures(SeenFeats, Implied); } -static void CheckFeatureTree(const Record *Root) { +static void checkFeatureTree(const Record *Root) { std::set SeenFeats; - CollectImpliedFeatures(SeenFeats, Root); + collectImpliedFeatures(SeenFeats, Root); // Check that each of the mandatory (implied) features which is an // ExtensionWithMArch is also enabled by default. @@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) { } } -static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { +static void emitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n"; // Look through all SubtargetFeature defs with the given FieldName, and // collect the set of all Values that that FieldName is set to. - auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) { + auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) { llvm::StringSet<> Set; for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) { if (Rec->getValueAsString("FieldName") == FieldName) { @@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { << "#define ARM_PROCESSOR_FAMILY(ENUM)\n" << "#endif\n\n"; const StringSet<> ARMProcFamilyVals = - gatherSubtargetFeatureFieldValues("ARMProcFamily"); + GatherSubtargetFeatureFieldValues("ARMProcFamily"); for (const StringRef &Family : ARMProcFamilyVals.keys()) OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n"; OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n"; @@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { << "#define ARM_ARCHITECTURE(ENUM)\n" << "#endif\n\n"; // This should correspond to instances of the Architecture tablegen class. - const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch"); + const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch"); for (const StringRef &Arch : ARMArchVals.keys()) OS << "ARM_ARCHITECTURE(" << Arch << ")\n"; OS << "\n#undef ARM_ARCHITECTURE\n\n"; @@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { auto Profile = Arch->getValueAsString("Profile"); auto ArchInfo = ArchInfoName(Major, Minor, Profile); - CheckFeatureTree(Arch); + checkFeatureTree(Arch); OS << " {\n" << " \"" << Name << "\",\n" @@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { } static TableGen::Emitter::Opt - X("gen-arm-target-def", EmitARMTargetDef, + X("gen-arm-target-def", emitARMTargetDef, "Generate the ARM or AArch64 Architecture information header."); diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index e3d9d010f9ae353e8ed412bfb062348582ca34ec..ade393c11b7a24e73dc05f807eec52344647eff3 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -1001,7 +1001,7 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info, char Char = String[i]; if (Variant.BreakCharacters.contains(Char)) { if (InTok) { - addAsmOperand(String.slice(Prev, i), false); + addAsmOperand(String.substr(Prev, i - Prev), false); Prev = i; IsIsolatedToken = false; } @@ -1010,7 +1010,7 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info, } if (Variant.TokenizingCharacters.contains(Char)) { if (InTok) { - addAsmOperand(String.slice(Prev, i), IsIsolatedToken); + addAsmOperand(String.substr(Prev, i - Prev), IsIsolatedToken); InTok = false; IsIsolatedToken = false; } @@ -1021,7 +1021,7 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info, } if (Variant.SeparatorCharacters.contains(Char)) { if (InTok) { - addAsmOperand(String.slice(Prev, i), IsIsolatedToken); + addAsmOperand(String.substr(Prev, i - Prev), IsIsolatedToken); InTok = false; } Prev = i + 1; @@ -1032,7 +1032,7 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info, switch (Char) { case '\\': if (InTok) { - addAsmOperand(String.slice(Prev, i), false); + addAsmOperand(String.substr(Prev, i - Prev), false); InTok = false; IsIsolatedToken = false; } @@ -1045,7 +1045,7 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info, case '$': { if (InTok) { - addAsmOperand(String.slice(Prev, i), IsIsolatedToken); + addAsmOperand(String.substr(Prev, i - Prev), IsIsolatedToken); InTok = false; IsIsolatedToken = false; } @@ -1059,7 +1059,7 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info, size_t EndPos = String.find('}', i); assert(EndPos != StringRef::npos && "Missing brace in operand reference!"); - addAsmOperand(String.slice(i, EndPos + 1), IsIsolatedToken); + addAsmOperand(String.substr(i, EndPos + 1 - i), IsIsolatedToken); Prev = EndPos + 1; i = EndPos; IsIsolatedToken = false; diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp index c8f263e15d96b76ff5d6427468e4aa30f66ef490..de20303a5bfd208a7e5ceea5936360a259791d2e 100644 --- a/llvm/utils/TableGen/CallingConvEmitter.cpp +++ b/llvm/utils/TableGen/CallingConvEmitter.cpp @@ -35,12 +35,12 @@ class CallingConvEmitter { public: explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {} - void run(raw_ostream &o); + void run(raw_ostream &O); private: - void EmitCallingConv(const Record *CC, raw_ostream &O); - void EmitAction(const Record *Action, indent Indent, raw_ostream &O); - void EmitArgRegisterLists(raw_ostream &O); + void emitCallingConv(const Record *CC, raw_ostream &O); + void emitAction(const Record *Action, indent Indent, raw_ostream &O); + void emitArgRegisterLists(raw_ostream &O); }; } // End anonymous namespace @@ -75,16 +75,16 @@ void CallingConvEmitter::run(raw_ostream &O) { Records.getTimer().startTimer("Emit full descriptions"); for (const Record *CC : CCs) { if (!CC->getValueAsBit("Custom")) { - EmitCallingConv(CC, O); + emitCallingConv(CC, O); } } - EmitArgRegisterLists(O); + emitArgRegisterLists(O); O << "\n#endif // CC_REGISTER_LIST\n"; } -void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) { +void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) { const ListInit *CCActions = CC->getValueAsListInit("Actions"); Counter = 0; @@ -107,8 +107,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) { << std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n" << std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n"; // Emit all of the actions, in order. - for (unsigned i = 0, e = CCActions->size(); i != e; ++i) { - const Record *Action = CCActions->getElementAsRecord(i); + for (unsigned I = 0, E = CCActions->size(); I != E; ++I) { + const Record *Action = CCActions->getElementAsRecord(I); SwiftAction = llvm::any_of(Action->getSuperClasses(), [](const std::pair &Class) { @@ -117,23 +117,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) { }); O << "\n"; - EmitAction(Action, indent(2), O); + emitAction(Action, indent(2), O); } O << "\n return true; // CC didn't match.\n"; O << "}\n"; } -void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, +void CallingConvEmitter::emitAction(const Record *Action, indent Indent, raw_ostream &O) { if (Action->isSubClassOf("CCPredicateAction")) { O << Indent << "if ("; if (Action->isSubClassOf("CCIfType")) { const ListInit *VTs = Action->getValueAsListInit("VTs"); - for (unsigned i = 0, e = VTs->size(); i != e; ++i) { - const Record *VT = VTs->getElementAsRecord(i); - if (i != 0) + for (unsigned I = 0, E = VTs->size(); I != E; ++I) { + const Record *VT = VTs->getElementAsRecord(I); + if (I != 0) O << " ||\n " << Indent; O << "LocVT == " << getEnumName(getValueType(VT)); } @@ -146,7 +146,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, } O << ") {\n"; - EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O); + emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O); O << Indent << "}\n"; } else { if (Action->isSubClassOf("CCDelegateTo")) { @@ -171,8 +171,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, << "[] = {\n"; O << Indent << " "; ListSeparator LS; - for (unsigned i = 0, e = RegList->size(); i != e; ++i) { - std::string Name = getQualifiedName(RegList->getElementAsRecord(i)); + for (unsigned I = 0, E = RegList->size(); I != E; ++I) { + std::string Name = getQualifiedName(RegList->getElementAsRecord(I)); if (SwiftAction) AssignedSwiftRegsMap[CurrentAction].insert(Name); else @@ -230,16 +230,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, << "[] = {\n"; O << Indent << " "; ListSeparator LS; - for (unsigned i = 0, e = RegList->size(); i != e; ++i) - O << LS << getQualifiedName(RegList->getElementAsRecord(i)); + for (unsigned I = 0, E = RegList->size(); I != E; ++I) + O << LS << getQualifiedName(RegList->getElementAsRecord(I)); O << "\n" << Indent << "};\n"; O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber << "[] = {\n"; O << Indent << " "; ListSeparator LSS; - for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i) - O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i)); + for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I) + O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I)); O << "\n" << Indent << "};\n"; O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList" @@ -287,8 +287,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, << ShadowRegListNumber << "[] = {\n"; O << Indent << " "; ListSeparator LS; - for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i) - O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i)); + for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I) + O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I)); O << "\n" << Indent << "};\n"; O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack(" @@ -357,7 +357,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent, } } -void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) { +void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) { // Transitively merge all delegated CCs into AssignedRegsMap. using EntryTy = std::pair>; bool Redo; diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp index be822c4815289cdad35bee8c9d7209c4aa31f876..407ee81b7e0b6c3b5f23010c5f6a1d3f964e58d9 100644 --- a/llvm/utils/TableGen/CodeEmitterGen.cpp +++ b/llvm/utils/TableGen/CodeEmitterGen.cpp @@ -52,10 +52,10 @@ class CodeEmitterGen { public: CodeEmitterGen(const RecordKeeper &R) : Records(R) {} - void run(raw_ostream &o); + void run(raw_ostream &O); private: - int getVariableBit(const std::string &VarName, const BitsInit *BI, int bit); + int getVariableBit(const std::string &VarName, const BitsInit *BI, int Bit); std::pair getInstructionCases(const Record *R, const CodeGenTarget &Target); void addInstructionCasesForEncoding(const Record *R, @@ -69,10 +69,10 @@ private: const CodeGenTarget &Target); void emitInstructionBaseValues( - raw_ostream &o, ArrayRef NumberedInstructions, + raw_ostream &O, ArrayRef NumberedInstructions, const CodeGenTarget &Target, unsigned HwMode = DefaultMode); void - emitCaseMap(raw_ostream &o, + emitCaseMap(raw_ostream &O, const std::map> &CaseMap); unsigned BitWidth = 0u; bool UseAPInt = false; @@ -81,12 +81,12 @@ private: // If the VarBitInit at position 'bit' matches the specified variable then // return the variable bit position. Otherwise return -1. int CodeEmitterGen::getVariableBit(const std::string &VarName, - const BitsInit *BI, int bit) { - if (const VarBitInit *VBI = dyn_cast(BI->getBit(bit))) { + const BitsInit *BI, int Bit) { + if (const VarBitInit *VBI = dyn_cast(BI->getBit(Bit))) { if (const VarInit *VI = dyn_cast(VBI->getBitVar())) if (VI->getName() == VarName) return VBI->getBitNum(); - } else if (const VarInit *VI = dyn_cast(BI->getBit(bit))) { + } else if (const VarInit *VI = dyn_cast(BI->getBit(Bit))) { if (VI->getName() == VarName) return 0; } @@ -104,19 +104,19 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R, CodeGenInstruction &CGI = Target.getInstruction(R); // Determine if VarName actually contributes to the Inst encoding. - int bit = BI->getNumBits() - 1; + int Bit = BI->getNumBits() - 1; // Scan for a bit that this contributed to. - for (; bit >= 0;) { - if (getVariableBit(VarName, BI, bit) != -1) + for (; Bit >= 0;) { + if (getVariableBit(VarName, BI, Bit) != -1) break; - --bit; + --Bit; } // If we found no bits, ignore this value, otherwise emit the call to get the // operand encoding. - if (bit < 0) + if (Bit < 0) return true; // If the operand matches by name, reference according to that @@ -175,97 +175,97 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R, // Precalculate the number of lits this variable contributes to in the // operand. If there is a single lit (consecutive range of bits) we can use a // destructive sequence on APInt that reduces memory allocations. - int numOperandLits = 0; - for (int tmpBit = bit; tmpBit >= 0;) { - int varBit = getVariableBit(VarName, BI, tmpBit); + int NumOperandLits = 0; + for (int TmpBit = Bit; TmpBit >= 0;) { + int VarBit = getVariableBit(VarName, BI, TmpBit); // If this bit isn't from a variable, skip it. - if (varBit == -1) { - --tmpBit; + if (VarBit == -1) { + --TmpBit; continue; } // Figure out the consecutive range of bits covered by this operand, in // order to generate better encoding code. - int beginVarBit = varBit; + int BeginVarBit = VarBit; int N = 1; - for (--tmpBit; tmpBit >= 0;) { - varBit = getVariableBit(VarName, BI, tmpBit); - if (varBit == -1 || varBit != (beginVarBit - N)) + for (--TmpBit; TmpBit >= 0;) { + VarBit = getVariableBit(VarName, BI, TmpBit); + if (VarBit == -1 || VarBit != (BeginVarBit - N)) break; ++N; - --tmpBit; + --TmpBit; } - ++numOperandLits; + ++NumOperandLits; } unsigned BitOffset = -1; - for (; bit >= 0;) { - int varBit = getVariableBit(VarName, BI, bit); + for (; Bit >= 0;) { + int VarBit = getVariableBit(VarName, BI, Bit); // If this bit isn't from a variable, skip it. - if (varBit == -1) { - --bit; + if (VarBit == -1) { + --Bit; continue; } // Figure out the consecutive range of bits covered by this operand, in // order to generate better encoding code. - int beginInstBit = bit; - int beginVarBit = varBit; + int BeginInstBit = Bit; + int BeginVarBit = VarBit; int N = 1; - for (--bit; bit >= 0;) { - varBit = getVariableBit(VarName, BI, bit); - if (varBit == -1 || varBit != (beginVarBit - N)) + for (--Bit; Bit >= 0;) { + VarBit = getVariableBit(VarName, BI, Bit); + if (VarBit == -1 || VarBit != (BeginVarBit - N)) break; ++N; - --bit; + --Bit; } - std::string maskStr; - int opShift; + std::string MaskStr; + int OpShift; - unsigned loBit = beginVarBit - N + 1; - unsigned hiBit = loBit + N; - unsigned loInstBit = beginInstBit - N + 1; - BitOffset = loInstBit; + unsigned LoBit = BeginVarBit - N + 1; + unsigned HiBit = LoBit + N; + unsigned LoInstBit = BeginInstBit - N + 1; + BitOffset = LoInstBit; if (UseAPInt) { - std::string extractStr; + std::string ExtractStr; if (N >= 64) { - extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " + - itostr(loBit) + ")"; - Case += " Value.insertBits(" + extractStr + ", " + - itostr(loInstBit) + ");\n"; + ExtractStr = "op.extractBits(" + itostr(HiBit - LoBit) + ", " + + itostr(LoBit) + ")"; + Case += " Value.insertBits(" + ExtractStr + ", " + + itostr(LoInstBit) + ");\n"; } else { - extractStr = "op.extractBitsAsZExtValue(" + itostr(hiBit - loBit) + - ", " + itostr(loBit) + ")"; - Case += " Value.insertBits(" + extractStr + ", " + - itostr(loInstBit) + ", " + itostr(hiBit - loBit) + ");\n"; + ExtractStr = "op.extractBitsAsZExtValue(" + itostr(HiBit - LoBit) + + ", " + itostr(LoBit) + ")"; + Case += " Value.insertBits(" + ExtractStr + ", " + + itostr(LoInstBit) + ", " + itostr(HiBit - LoBit) + ");\n"; } } else { - uint64_t opMask = ~(uint64_t)0 >> (64 - N); - opShift = beginVarBit - N + 1; - opMask <<= opShift; - maskStr = "UINT64_C(" + utostr(opMask) + ")"; - opShift = beginInstBit - beginVarBit; - - if (numOperandLits == 1) { - Case += " op &= " + maskStr + ";\n"; - if (opShift > 0) { - Case += " op <<= " + itostr(opShift) + ";\n"; - } else if (opShift < 0) { - Case += " op >>= " + itostr(-opShift) + ";\n"; + uint64_t OpMask = ~(uint64_t)0 >> (64 - N); + OpShift = BeginVarBit - N + 1; + OpMask <<= OpShift; + MaskStr = "UINT64_C(" + utostr(OpMask) + ")"; + OpShift = BeginInstBit - BeginVarBit; + + if (NumOperandLits == 1) { + Case += " op &= " + MaskStr + ";\n"; + if (OpShift > 0) { + Case += " op <<= " + itostr(OpShift) + ";\n"; + } else if (OpShift < 0) { + Case += " op >>= " + itostr(-OpShift) + ";\n"; } Case += " Value |= op;\n"; } else { - if (opShift > 0) { - Case += " Value |= (op & " + maskStr + ") << " + - itostr(opShift) + ";\n"; - } else if (opShift < 0) { - Case += " Value |= (op & " + maskStr + ") >> " + - itostr(-opShift) + ";\n"; + if (OpShift > 0) { + Case += " Value |= (op & " + MaskStr + ") << " + + itostr(OpShift) + ";\n"; + } else if (OpShift < 0) { + Case += " Value |= (op & " + MaskStr + ") >> " + + itostr(-OpShift) + ";\n"; } else { - Case += " Value |= (op & " + maskStr + ");\n"; + Case += " Value |= (op & " + MaskStr + ");\n"; } } } @@ -285,7 +285,7 @@ CodeEmitterGen::getInstructionCases(const Record *R, const CodeGenTarget &Target) { std::string Case, BitOffsetCase; - auto append = [&](const std::string &S) { + auto Append = [&](const std::string &S) { Case += S; BitOffsetCase += S; }; @@ -298,7 +298,7 @@ CodeEmitterGen::getInstructionCases(const Record *R, // Invoke the interface to obtain the HwMode ID controlling the // EncodingInfo for the current subtarget. This interface will // mask off irrelevant HwMode IDs. - append(" unsigned HwMode = " + Append(" unsigned HwMode = " "STI.getHwMode(MCSubtargetInfo::HwMode_EncodingInfo);\n"); Case += " switch (HwMode) {\n"; Case += " default: llvm_unreachable(\"Unknown hardware mode!\"); " @@ -328,16 +328,16 @@ CodeEmitterGen::getInstructionCases(const Record *R, Case += " Value = InstBitsByHw[opcode];\n"; } - append(" switch (HwMode) {\n"); - append(" default: llvm_unreachable(\"Unhandled HwMode\");\n"); + Append(" switch (HwMode) {\n"); + Append(" default: llvm_unreachable(\"Unhandled HwMode\");\n"); for (auto &[ModeId, Encoding] : EBM) { - append(" case " + itostr(ModeId) + ": {\n"); + Append(" case " + itostr(ModeId) + ": {\n"); addInstructionCasesForEncoding(R, Encoding, Target, Case, BitOffsetCase); - append(" break;\n"); - append(" }\n"); + Append(" break;\n"); + Append(" }\n"); } - append(" }\n"); + Append(" }\n"); return std::pair(std::move(Case), std::move(BitOffsetCase)); } } @@ -397,13 +397,13 @@ static void emitInstBits(raw_ostream &OS, const APInt &Bits) { } void CodeEmitterGen::emitInstructionBaseValues( - raw_ostream &o, ArrayRef NumberedInstructions, + raw_ostream &O, ArrayRef NumberedInstructions, const CodeGenTarget &Target, unsigned HwMode) { const CodeGenHwModes &HWM = Target.getHwModes(); if (HwMode == DefaultMode) - o << " static const uint64_t InstBits[] = {\n"; + O << " static const uint64_t InstBits[] = {\n"; else - o << " static const uint64_t InstBits_" + O << " static const uint64_t InstBits_" << HWM.getModeName(HwMode, /*IncludeDefault=*/true) << "[] = {\n"; for (const CodeGenInstruction *CGI : NumberedInstructions) { @@ -411,9 +411,9 @@ void CodeEmitterGen::emitInstructionBaseValues( if (R->getValueAsString("Namespace") == "TargetOpcode" || R->getValueAsBit("isPseudo")) { - o << " "; - emitInstBits(o, APInt(BitWidth, 0)); - o << ",\n"; + O << " "; + emitInstBits(O, APInt(BitWidth, 0)); + O << ",\n"; continue; } @@ -427,9 +427,9 @@ void CodeEmitterGen::emitInstructionBaseValues( // If the HwMode does not match, then Encoding '0' // should be generated. APInt Value(BitWidth, 0); - o << " "; - emitInstBits(o, Value); - o << "," << '\t' << "// " << R->getName() << "\n"; + O << " "; + emitInstBits(O, Value); + O << "," << '\t' << "// " << R->getName() << "\n"; continue; } } @@ -438,37 +438,37 @@ void CodeEmitterGen::emitInstructionBaseValues( // Start by filling in fixed values. APInt Value(BitWidth, 0); - for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { - if (const auto *B = dyn_cast(BI->getBit(i)); B && B->getValue()) - Value.setBit(i); + for (unsigned I = 0, E = BI->getNumBits(); I != E; ++I) { + if (const auto *B = dyn_cast(BI->getBit(I)); B && B->getValue()) + Value.setBit(I); } - o << " "; - emitInstBits(o, Value); - o << "," << '\t' << "// " << R->getName() << "\n"; + O << " "; + emitInstBits(O, Value); + O << "," << '\t' << "// " << R->getName() << "\n"; } - o << " UINT64_C(0)\n };\n"; + O << " UINT64_C(0)\n };\n"; } void CodeEmitterGen::emitCaseMap( - raw_ostream &o, + raw_ostream &O, const std::map> &CaseMap) { for (const auto &[Case, InstList] : CaseMap) { bool First = true; for (const auto &Inst : InstList) { if (!First) - o << "\n"; - o << " case " << Inst << ":"; + O << "\n"; + O << " case " << Inst << ":"; First = false; } - o << " {\n"; - o << Case; - o << " break;\n" + O << " {\n"; + O << Case; + O << " break;\n" << " }\n"; } } -void CodeEmitterGen::run(raw_ostream &o) { - emitSourceFileHeader("Machine Code Emitter", o); +void CodeEmitterGen::run(raw_ostream &O) { + emitSourceFileHeader("Machine Code Emitter", O); CodeGenTarget Target(Records); @@ -479,7 +479,7 @@ void CodeEmitterGen::run(raw_ostream &o) { Target.getInstructionsByEnumValue(); if (Target.hasVariableLengthEncodings()) { - emitVarLenCodeEmitter(Records, o); + emitVarLenCodeEmitter(Records, O); } else { const CodeGenHwModes &HWM = Target.getHwModes(); // The set of HwModes used by instruction encodings. @@ -509,31 +509,31 @@ void CodeEmitterGen::run(raw_ostream &o) { // Emit function declaration if (UseAPInt) { - o << "void " << Target.getName() + O << "void " << Target.getName() << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" << " SmallVectorImpl &Fixups,\n" << " APInt &Inst,\n" << " APInt &Scratch,\n" << " const MCSubtargetInfo &STI) const {\n"; } else { - o << "uint64_t " << Target.getName(); - o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" + O << "uint64_t " << Target.getName(); + O << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" << " SmallVectorImpl &Fixups,\n" << " const MCSubtargetInfo &STI) const {\n"; } // Emit instruction base values - emitInstructionBaseValues(o, NumberedInstructions, Target, DefaultMode); + emitInstructionBaseValues(O, NumberedInstructions, Target, DefaultMode); if (!HwModes.empty()) { // Emit table for instrs whose encodings are controlled by HwModes. for (unsigned HwMode : HwModes) { if (HwMode == DefaultMode) continue; - emitInstructionBaseValues(o, NumberedInstructions, Target, HwMode); + emitInstructionBaseValues(O, NumberedInstructions, Target, HwMode); } // This pointer will be assigned to the HwMode table later. - o << " const uint64_t *InstBitsByHw;\n"; + O << " const uint64_t *InstBitsByHw;\n"; } // Map to accumulate all the cases. @@ -557,7 +557,7 @@ void CodeEmitterGen::run(raw_ostream &o) { // Emit initial function code if (UseAPInt) { int NumWords = APInt::getNumWords(BitWidth); - o << " const unsigned opcode = MI.getOpcode();\n" + O << " const unsigned opcode = MI.getOpcode();\n" << " if (Scratch.getBitWidth() != " << BitWidth << ")\n" << " Scratch = Scratch.zext(" << BitWidth << ");\n" << " Inst = APInt(" << BitWidth << ", ArrayRef(InstBits + opcode * " @@ -566,7 +566,7 @@ void CodeEmitterGen::run(raw_ostream &o) { << " APInt &op = Scratch;\n" << " switch (opcode) {\n"; } else { - o << " const unsigned opcode = MI.getOpcode();\n" + O << " const unsigned opcode = MI.getOpcode();\n" << " uint64_t Value = InstBits[opcode];\n" << " uint64_t op = 0;\n" << " (void)op; // suppress warning\n" @@ -574,30 +574,30 @@ void CodeEmitterGen::run(raw_ostream &o) { } // Emit each case statement - emitCaseMap(o, CaseMap); + emitCaseMap(O, CaseMap); // Default case: unhandled opcode - o << " default:\n" + O << " default:\n" << " std::string msg;\n" << " raw_string_ostream Msg(msg);\n" << " Msg << \"Not supported instr: \" << MI;\n" << " report_fatal_error(Msg.str().c_str());\n" << " }\n"; if (UseAPInt) - o << " Inst = Value;\n"; + O << " Inst = Value;\n"; else - o << " return Value;\n"; - o << "}\n\n"; + O << " return Value;\n"; + O << "}\n\n"; - o << "#ifdef GET_OPERAND_BIT_OFFSET\n" + O << "#ifdef GET_OPERAND_BIT_OFFSET\n" << "#undef GET_OPERAND_BIT_OFFSET\n\n" << "uint32_t " << Target.getName() << "MCCodeEmitter::getOperandBitOffset(const MCInst &MI,\n" << " unsigned OpNum,\n" << " const MCSubtargetInfo &STI) const {\n" << " switch (MI.getOpcode()) {\n"; - emitCaseMap(o, BitOffsetCaseMap); - o << " }\n" + emitCaseMap(O, BitOffsetCaseMap); + O << " }\n" << " std::string msg;\n" << " raw_string_ostream Msg(msg);\n" << " Msg << \"Not supported instr[opcode]: \" << MI << \"[\" << OpNum " diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp index 7876db6f33dfdff2bab95180332a710c3906154f..8d22c0013dda8811a9b2c4bb48a0418659d8e993 100644 --- a/llvm/utils/TableGen/CodeGenMapTable.cpp +++ b/llvm/utils/TableGen/CodeGenMapTable.cpp @@ -258,12 +258,12 @@ bool MapTableEmitter::isKeyColInstr(const Record *CurInstr) { // Check if the instruction is a KeyCol instruction. bool MatchFound = true; - for (unsigned j = 0, endCF = ColFields->size(); (j < endCF) && MatchFound; - j++) { + for (unsigned J = 0, EndCf = ColFields->size(); (J < EndCf) && MatchFound; + J++) { const RecordVal *ColFieldName = - CurInstr->getValue(ColFields->getElement(j)); + CurInstr->getValue(ColFields->getElement(J)); std::string CurInstrVal = ColFieldName->getValue()->getAsUnquotedString(); - std::string KeyColValue = KeyCol->getElement(j)->getAsUnquotedString(); + std::string KeyColValue = KeyCol->getElement(J)->getAsUnquotedString(); MatchFound = CurInstrVal == KeyColValue; } return MatchFound; @@ -318,12 +318,12 @@ const Record *MapTableEmitter::getInstrForColumn(const Record *KeyInstr, for (const Record *CurInstr : RelatedInstrVec) { bool MatchFound = true; - for (unsigned j = 0, endCF = ColFields->size(); (j < endCF) && MatchFound; - j++) { - const Init *ColFieldJ = ColFields->getElement(j); + for (unsigned J = 0, EndCf = ColFields->size(); (J < EndCf) && MatchFound; + J++) { + const Init *ColFieldJ = ColFields->getElement(J); const Init *CurInstrInit = CurInstr->getValue(ColFieldJ)->getValue(); std::string CurInstrVal = CurInstrInit->getAsUnquotedString(); - const Init *ColFieldJVallue = CurValueCol->getElement(j); + const Init *ColFieldJVallue = CurValueCol->getElement(J); MatchFound = CurInstrVal == ColFieldJVallue->getAsUnquotedString(); } @@ -368,19 +368,19 @@ unsigned MapTableEmitter::emitBinSearchTable(raw_ostream &OS) { // Number of columns in the table are NumCol+1 because key instructions are // emitted as first column. OS << "Table[][" << NumCol + 1 << "] = {\n"; - for (unsigned i = 0; i < TotalNumInstr; i++) { - const Record *CurInstr = NumberedInstructions[i]->TheDef; + for (unsigned I = 0; I < TotalNumInstr; I++) { + const Record *CurInstr = NumberedInstructions[I]->TheDef; ArrayRef ColInstrs = MapTable[CurInstr]; std::string OutStr; unsigned RelExists = 0; if (!ColInstrs.empty()) { - for (unsigned j = 0; j < NumCol; j++) { - if (ColInstrs[j] != nullptr) { + for (unsigned J = 0; J < NumCol; J++) { + if (ColInstrs[J] != nullptr) { RelExists = 1; OutStr += ", "; OutStr += Namespace; OutStr += "::"; - OutStr += ColInstrs[j]->getName(); + OutStr += ColInstrs[J]->getName(); } else { OutStr += ", (uint16_t)-1U"; } @@ -441,20 +441,20 @@ void MapTableEmitter::emitMapFuncBody(raw_ostream &OS, unsigned TableSize) { emitBinSearch(OS, TableSize); if (ValueCols.size() > 1) { - for (unsigned i = 0, e = ValueCols.size(); i < e; i++) { - const ListInit *ColumnI = ValueCols[i]; + for (unsigned I = 0, E = ValueCols.size(); I < E; I++) { + const ListInit *ColumnI = ValueCols[I]; OS << " if ("; - for (unsigned j = 0, ColSize = ColumnI->size(); j < ColSize; ++j) { - std::string ColName = ColFields->getElement(j)->getAsUnquotedString(); + for (unsigned J = 0, ColSize = ColumnI->size(); J < ColSize; ++J) { + std::string ColName = ColFields->getElement(J)->getAsUnquotedString(); OS << "in" << ColName; OS << " == "; - OS << ColName << "_" << ColumnI->getElement(j)->getAsUnquotedString(); - if (j < ColumnI->size() - 1) + OS << ColName << "_" << ColumnI->getElement(J)->getAsUnquotedString(); + if (J < ColumnI->size() - 1) OS << " && "; } OS << ")\n"; OS << " return " << InstrMapDesc.getName(); - OS << "Table[mid][" << i + 1 << "];\n"; + OS << "Table[mid][" << I + 1 << "];\n"; } OS << " return -1;"; } else @@ -509,8 +509,8 @@ static void emitEnums(raw_ostream &OS, const RecordKeeper &Records) { std::vector ValueCols; unsigned ListSize = List->size(); - for (unsigned j = 0; j < ListSize; j++) { - const auto *ListJ = cast(List->getElement(j)); + for (unsigned J = 0; J < ListSize; J++) { + const auto *ListJ = cast(List->getElement(J)); if (ListJ->size() != ColFields->size()) PrintFatalError("Record `" + CurMap->getName() + @@ -520,10 +520,10 @@ static void emitEnums(raw_ostream &OS, const RecordKeeper &Records) { ValueCols.push_back(ListJ); } - for (unsigned j = 0, endCF = ColFields->size(); j < endCF; j++) { - for (unsigned k = 0; k < ListSize; k++) { - std::string ColName = ColFields->getElement(j)->getAsUnquotedString(); - ColFieldValueMap[ColName].push_back((ValueCols[k])->getElement(j)); + for (unsigned J = 0, EndCf = ColFields->size(); J < EndCf; J++) { + for (unsigned K = 0; K < ListSize; K++) { + std::string ColName = ColFields->getElement(J)->getAsUnquotedString(); + ColFieldValueMap[ColName].push_back((ValueCols[K])->getElement(J)); } } } diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp index d2228c902a56b47b4e01edfdbe2afb393eb9d7c0..f17c62dd1fd9d422307f9440bce9a89a9ce98ad0 100644 --- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp @@ -813,8 +813,8 @@ void TypeInfer::expandOverloads(TypeSetByHwMode &VTS) const { void TypeInfer::expandOverloads(TypeSetByHwMode::SetType &Out, const TypeSetByHwMode::SetType &Legal) const { - if (Out.count(MVT::iPTRAny)) { - Out.erase(MVT::iPTRAny); + if (Out.count(MVT::pAny)) { + Out.erase(MVT::pAny); Out.insert(MVT::iPTR); } else if (Out.count(MVT::iAny)) { Out.erase(MVT::iAny); @@ -2461,7 +2461,8 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { ValueTypeByHwMode VVT = TP.getInfer().getConcrete(Types[0], false); for (auto &P : VVT) { MVT::SimpleValueType VT = P.second.SimpleTy; - if (VT == MVT::iPTR || VT == MVT::iPTRAny) + // Can only check for types of a known size + if (VT == MVT::iPTR) continue; unsigned Size = MVT(VT).getFixedSizeInBits(); // Make sure that the value is representable for this type. diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp index 1c0ab594d9310a5c118693f03f00a762439985d8..f72fe4c6fd5620679f19c821bf7a6f25c3787627 100644 --- a/llvm/utils/TableGen/Common/CodeGenInstruction.cpp +++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp @@ -566,7 +566,8 @@ std::string CodeGenInstruction::FlattenAsmStringVariants(StringRef Cur, } // Select the Nth variant (or empty). - StringRef Selection = Cur.slice(VariantsStart, VariantsEnd); + StringRef Selection = + Cur.substr(VariantsStart, VariantsEnd - VariantsStart); for (unsigned i = 0; i != Variant; ++i) Selection = Selection.split('|').second; Res += Selection.split('|').first; diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.cpp b/llvm/utils/TableGen/Common/CodeGenTarget.cpp index b358518c4290b0f960b72ff23dc331a224308701..4e75db689a0b57a7ac74229db1dcee0672f54c35 100644 --- a/llvm/utils/TableGen/Common/CodeGenTarget.cpp +++ b/llvm/utils/TableGen/Common/CodeGenTarget.cpp @@ -47,19 +47,6 @@ MVT::SimpleValueType llvm::getValueType(const Record *Rec) { return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); } -StringRef llvm::getName(MVT::SimpleValueType T) { - switch (T) { - case MVT::Other: - return "UNKNOWN"; - case MVT::iPTR: - return "TLI.getPointerTy()"; - case MVT::iPTRAny: - return "TLI.getPointerTy()"; - default: - return getEnumName(T); - } -} - StringRef llvm::getEnumName(MVT::SimpleValueType T) { // clang-format off switch (T) { diff --git a/llvm/utils/TableGen/Common/CodeGenTarget.h b/llvm/utils/TableGen/Common/CodeGenTarget.h index c7b44f7028eb5bb6c4add4b5233e31796b51f3da..8bcb2f677a00b0bd2ce2dd82e6ae6a18aa188875 100644 --- a/llvm/utils/TableGen/Common/CodeGenTarget.h +++ b/llvm/utils/TableGen/Common/CodeGenTarget.h @@ -46,7 +46,6 @@ class CodeGenSubRegIndex; /// record corresponds to. MVT::SimpleValueType getValueType(const Record *Rec); -StringRef getName(MVT::SimpleValueType T); StringRef getEnumName(MVT::SimpleValueType T); /// getQualifiedName - Return the name of the specified record, with a diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp index d3b653b0fba27fa525533288ff50b8cac2d2adbc..3d39ee148373fd0ed2672bbc8610258082dfd8d3 100644 --- a/llvm/utils/TableGen/DAGISelEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelEmitter.cpp @@ -55,8 +55,8 @@ static unsigned getResultPatternCost(TreePatternNode &P, if (II.usesCustomInserter) Cost += 10; } - for (unsigned i = 0, e = P.getNumChildren(); i != e; ++i) - Cost += getResultPatternCost(P.getChild(i), CGP); + for (unsigned I = 0, E = P.getNumChildren(); I != E; ++I) + Cost += getResultPatternCost(P.getChild(I), CGP); return Cost; } @@ -72,8 +72,8 @@ static unsigned getResultPatternSize(TreePatternNode &P, if (Op->isSubClassOf("Instruction")) { Cost += Op->getValueAsInt("CodeSize"); } - for (unsigned i = 0, e = P.getNumChildren(); i != e; ++i) - Cost += getResultPatternSize(P.getChild(i), CGP); + for (unsigned I = 0, E = P.getNumChildren(); I != E; ++I) + Cost += getResultPatternSize(P.getChild(I), CGP); return Cost; } diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp index 537bee55978bd6c9b6154a0112488037eeaa5f55..a6c0d09f69ba342f738618259aec0ef69482e912 100644 --- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp +++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp @@ -105,7 +105,7 @@ int DFAPacketizerEmitter::collectAllFuncUnits( for (const CodeGenProcModel *Model : ProcModels) ProcItinList.insert(Model->ItinsDef); - int totalFUs = 0; + int TotalFUs = 0; // Parse functional units for all the itineraries. for (const Record *Proc : ProcItinList) { std::vector FUs = Proc->getValueAsListOfDefs("FU"); @@ -123,10 +123,10 @@ int DFAPacketizerEmitter::collectAllFuncUnits( LLVM_DEBUG(dbgs() << " " << FUs[j]->getName() << ":0x" << Twine::utohexstr(FuncResources)); } - totalFUs += numFUs; + TotalFUs += numFUs; LLVM_DEBUG(dbgs() << "\n"); } - return totalFUs; + return TotalFUs; } int DFAPacketizerEmitter::collectAllComboFuncs( @@ -136,19 +136,19 @@ int DFAPacketizerEmitter::collectAllComboFuncs( LLVM_DEBUG(dbgs() << "collectAllComboFuncs"); LLVM_DEBUG(dbgs() << " (" << ComboFuncList.size() << " sets)\n"); - int numCombos = 0; - for (unsigned i = 0, N = ComboFuncList.size(); i < N; ++i) { - const Record *Func = ComboFuncList[i]; + int NumCombos = 0; + for (unsigned I = 0, N = ComboFuncList.size(); I < N; ++I) { + const Record *Func = ComboFuncList[I]; std::vector FUs = Func->getValueAsListOfDefs("CFD"); - LLVM_DEBUG(dbgs() << " CFD:" << i << " (" << FUs.size() << " combo FUs) " + LLVM_DEBUG(dbgs() << " CFD:" << I << " (" << FUs.size() << " combo FUs) " << Func->getName() << "\n"); // Convert macros to bits for each stage. - for (unsigned j = 0, N = FUs.size(); j < N; ++j) { - assert((j < DFA_MAX_RESOURCES) && + for (unsigned J = 0, N = FUs.size(); J < N; ++J) { + assert((J < DFA_MAX_RESOURCES) && "Exceeded maximum number of DFA resources"); - const Record *FuncData = FUs[j]; + const Record *FuncData = FUs[J]; const Record *ComboFunc = FuncData->getValueAsDef("TheComboFunc"); const std::vector FuncList = FuncData->getValueAsListOfDefs("FuncList"); @@ -165,13 +165,13 @@ int DFAPacketizerEmitter::collectAllComboFuncs( ComboResources |= FuncResources; } ComboBitToBitsMap[ComboBit] = ComboResources; - numCombos++; + NumCombos++; LLVM_DEBUG(dbgs() << " => combo bits: " << ComboFuncName << ":0x" << Twine::utohexstr(ComboBit) << " = 0x" << Twine::utohexstr(ComboResources) << "\n"); } } - return numCombos; + return NumCombos; } ResourceVector @@ -271,7 +271,7 @@ void DFAPacketizerEmitter::emitForItineraries( // Given a resource state, return all resource states by applying // InsnClass. - auto applyInsnClass = [&](const ResourceVector &InsnClass, + auto ApplyInsnClass = [&](const ResourceVector &InsnClass, NfaStateTy State) -> std::deque { std::deque V(1, State); // Apply every stage in the class individually. @@ -304,7 +304,7 @@ void DFAPacketizerEmitter::emitForItineraries( // Given a resource state, return a quick (conservative) guess as to whether // InsnClass can be applied. This is a filter for the more heavyweight - // applyInsnClass. + // ApplyInsnClass. auto canApplyInsnClass = [](const ResourceVector &InsnClass, NfaStateTy State) -> bool { for (NfaStateTy Resources : InsnClass) { @@ -325,7 +325,7 @@ void DFAPacketizerEmitter::emitForItineraries( if (!canApplyInsnClass(Resources, State)) continue; unsigned ResourcesID = UniqueResources.idFor(Resources); - for (uint64_t NewState : applyInsnClass(Resources, State)) { + for (uint64_t NewState : ApplyInsnClass(Resources, State)) { if (SeenStates.emplace(NewState).second) Worklist.emplace_back(NewState); Emitter.addTransition(State, NewState, ResourcesID); diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp index 467a6163ae3b0c1a75cf91eba6be78b7b7fefe28..e74fc00015b4045cfac8373046487a541b4b9908 100644 --- a/llvm/utils/TableGen/DXILEmitter.cpp +++ b/llvm/utils/TableGen/DXILEmitter.cpp @@ -48,7 +48,7 @@ struct DXILOperationDesc { ShaderStages; // shader stages to which this applies, empty for all. int OverloadParamIndex; // Index of parameter with overload type. // -1 : no overload types - SmallVector counters; // counters for this inst. + SmallVector Counters; // counters for this inst. DXILOperationDesc(const Record *); }; } // end anonymous namespace @@ -56,7 +56,7 @@ struct DXILOperationDesc { /// In-place sort TableGen records of class with a field /// Version dxil_version /// in the ascending version order. -static void AscendingSortByVersion(std::vector &Recs) { +static void ascendingSortByVersion(std::vector &Recs) { sort(Recs, [](const Record *RecA, const Record *RecB) { unsigned RecAMaj = RecA->getValueAsDef("dxil_version")->getValueAsInt("Major"); @@ -97,8 +97,8 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { // the comment before the definition of class LLVMMatchType in // llvm/IR/Intrinsics.td OverloadParamIndex = -1; // A sigil meaning none. - for (unsigned i = 0; i < ParamTypeRecsSize; i++) { - const Record *TR = ParamTypeRecs[i]; + for (unsigned I = 0; I < ParamTypeRecsSize; I++) { + const Record *TR = ParamTypeRecs[I]; // Track operation parameter indices of any overload types if (TR->getValueAsInt("isOverload")) { if (OverloadParamIndex != -1) { @@ -109,7 +109,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { // Keep the earliest parameter index we see, but if it was the return type // overwrite it with the first overloaded argument. if (OverloadParamIndex <= 0) - OverloadParamIndex = i; + OverloadParamIndex = I; } OpTypes.emplace_back(TR); } @@ -118,7 +118,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { std::vector Recs = R->getValueAsListOfDefs("overloads"); // Sort records in ascending order of DXIL version - AscendingSortByVersion(Recs); + ascendingSortByVersion(Recs); for (const Record *CR : Recs) { OverloadRecs.push_back(CR); @@ -133,7 +133,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { } // Sort records in ascending order of DXIL version - AscendingSortByVersion(Recs); + ascendingSortByVersion(Recs); for (const Record *CR : Recs) { StageRecs.push_back(CR); @@ -143,7 +143,7 @@ DXILOperationDesc::DXILOperationDesc(const Record *R) { Recs = R->getValueAsListOfDefs("attributes"); // Sort records in ascending order of DXIL version - AscendingSortByVersion(Recs); + ascendingSortByVersion(Recs); for (const Record *CR : Recs) { AttrRecs.push_back(CR); @@ -209,7 +209,7 @@ static std::string getOverloadMaskString(ArrayRef Recs) { if (Recs.empty()) { MaskString.append("{{1, 0}, OverloadKind::UNDEFINED}}"); } else { - for (auto Rec : Recs) { + for (const auto *Rec : Recs) { unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major"); unsigned Minor = @@ -255,7 +255,7 @@ static std::string getStageMaskString(ArrayRef Recs) { "operation must be specified"); } - for (auto Rec : Recs) { + for (const auto *Rec : Recs) { unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major"); unsigned Minor = Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor"); MaskString.append(Prefix) @@ -293,7 +293,7 @@ static std::string getAttributeMaskString(ArrayRef Recs) { std::string Prefix = ""; MaskString.append("{"); - for (auto Rec : Recs) { + for (const auto *Rec : Recs) { unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major"); unsigned Minor = Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor"); MaskString.append(Prefix) @@ -480,21 +480,21 @@ static void emitDXILOperationTableDataStructs(const RecordKeeper &Records, size_t ShaderKindCount = ShaderKindRecs.size(); uint64_t ShaderKindTySz = PowerOf2Ceil(ShaderKindRecs.size() + 1); OS << "enum ShaderKind : uint" << ShaderKindTySz << "_t {\n"; - const std::string allStages("all_stages"); - const std::string removed("removed"); - int shiftVal = 1; - for (auto R : ShaderKindRecs) { + const std::string AllStages("all_stages"); + const std::string Removed("removed"); + int ShiftVal = 1; + for (const auto *R : ShaderKindRecs) { auto Name = R->getName(); - if (Name.compare(removed) == 0) { + if (Name.compare(Removed) == 0) { OS << " " << Name << " = 0, // Pseudo-stage indicating op not supported in any " "stage\n"; - } else if (Name.compare(allStages) == 0) { + } else if (Name.compare(AllStages) == 0) { OS << " " << Name << " = 0x" << utohexstr(((1 << ShaderKindCount) - 1), false, 0) << ", // Pseudo-stage indicating op is supported in all stages\n"; - } else if (Name.compare(allStages)) { - OS << " " << Name << " = 1 << " << std::to_string(shiftVal++) << ",\n"; + } else if (Name.compare(AllStages)) { + OS << " " << Name << " = 1 << " << std::to_string(ShiftVal++) << ",\n"; } } OS << "}; // enum ShaderKind\n\n"; @@ -503,7 +503,7 @@ static void emitDXILOperationTableDataStructs(const RecordKeeper &Records, /// Entry function call that invokes the functionality of this TableGen backend /// \param Records TableGen records of DXIL Operations defined in DXIL.td /// \param OS output stream -static void EmitDXILOperation(const RecordKeeper &Records, raw_ostream &OS) { +static void emitDxilOperation(const RecordKeeper &Records, raw_ostream &OS) { OS << "// Generated code, do not edit.\n"; OS << "\n"; // Get all DXIL Ops property records @@ -535,5 +535,5 @@ static void EmitDXILOperation(const RecordKeeper &Records, raw_ostream &OS) { OS << "#endif\n\n"; } -static TableGen::Emitter::Opt X("gen-dxil-operation", EmitDXILOperation, +static TableGen::Emitter::Opt X("gen-dxil-operation", emitDxilOperation, "Generate DXIL operation information"); diff --git a/llvm/utils/TableGen/DirectiveEmitter.cpp b/llvm/utils/TableGen/DirectiveEmitter.cpp index 9dc29d8262fa2ca2bcc46d16606b6ba10e55e305..fd815f4a31dad8d50929e9bb163a4e7c38e4e0a2 100644 --- a/llvm/utils/TableGen/DirectiveEmitter.cpp +++ b/llvm/utils/TableGen/DirectiveEmitter.cpp @@ -46,7 +46,7 @@ private: // Generate enum class. Entries are emitted in the order in which they appear // in the `Records` vector. -static void GenerateEnumClass(ArrayRef Records, raw_ostream &OS, +static void generateEnumClass(ArrayRef Records, raw_ostream &OS, StringRef Enum, StringRef Prefix, const DirectiveLanguage &DirLang, bool ExportEnums) { @@ -79,7 +79,7 @@ static void GenerateEnumClass(ArrayRef Records, raw_ostream &OS, // Generate enums for values that clauses can take. // Also generate function declarations for getName(StringRef Str). -static void GenerateEnumClauseVal(ArrayRef Records, +static void generateEnumClauseVal(ArrayRef Records, raw_ostream &OS, const DirectiveLanguage &DirLang, std::string &EnumHelperFuncs) { @@ -121,13 +121,13 @@ static void GenerateEnumClauseVal(ArrayRef Records, } } -static bool HasDuplicateClauses(ArrayRef Clauses, +static bool hasDuplicateClauses(ArrayRef Clauses, const Directive &Directive, StringSet<> &CrtClauses) { bool HasError = false; for (const VersionedClause VerClause : Clauses) { - const auto insRes = CrtClauses.insert(VerClause.getClause().getName()); - if (!insRes.second) { + const auto InsRes = CrtClauses.insert(VerClause.getClause().getName()); + if (!InsRes.second) { PrintError("Clause " + VerClause.getClause().getRecordName() + " already defined on directive " + Directive.getRecordName()); HasError = true; @@ -140,20 +140,20 @@ static bool HasDuplicateClauses(ArrayRef Clauses, // three allowed list. Also, since required implies allowed, clauses cannot // appear in both the allowedClauses and requiredClauses lists. static bool -HasDuplicateClausesInDirectives(ArrayRef Directives) { +hasDuplicateClausesInDirectives(ArrayRef Directives) { bool HasDuplicate = false; for (const Directive Dir : Directives) { StringSet<> Clauses; // Check for duplicates in the three allowed lists. - if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || - HasDuplicateClauses(Dir.getAllowedOnceClauses(), Dir, Clauses) || - HasDuplicateClauses(Dir.getAllowedExclusiveClauses(), Dir, Clauses)) { + if (hasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || + hasDuplicateClauses(Dir.getAllowedOnceClauses(), Dir, Clauses) || + hasDuplicateClauses(Dir.getAllowedExclusiveClauses(), Dir, Clauses)) { HasDuplicate = true; } // Check for duplicate between allowedClauses and required Clauses.clear(); - if (HasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || - HasDuplicateClauses(Dir.getRequiredClauses(), Dir, Clauses)) { + if (hasDuplicateClauses(Dir.getAllowedClauses(), Dir, Clauses) || + hasDuplicateClauses(Dir.getRequiredClauses(), Dir, Clauses)) { HasDuplicate = true; } if (HasDuplicate) @@ -173,11 +173,11 @@ bool DirectiveLanguage::HasValidityErrors() const { return true; } - return HasDuplicateClausesInDirectives(getDirectives()); + return hasDuplicateClausesInDirectives(getDirectives()); } // Count the maximum number of leaf constituents per construct. -static size_t GetMaxLeafCount(const DirectiveLanguage &DirLang) { +static size_t getMaxLeafCount(const DirectiveLanguage &DirLang) { size_t MaxCount = 0; for (const Directive D : DirLang.getDirectives()) MaxCount = std::max(MaxCount, D.getLeafConstructs().size()); @@ -186,7 +186,7 @@ static size_t GetMaxLeafCount(const DirectiveLanguage &DirLang) { // Generate the declaration section for the enumeration in the directive // language. -static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { +static void emitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { const auto DirLang = DirectiveLanguage(Records); if (DirLang.HasValidityErrors()) return; @@ -214,29 +214,29 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { OS << "\nLLVM_ENABLE_BITMASK_ENUMS_IN_NAMESPACE();\n"; // Emit Directive associations - std::vector associations; - copy_if(DirLang.getAssociations(), std::back_inserter(associations), + std::vector Associations; + copy_if(DirLang.getAssociations(), std::back_inserter(Associations), // Skip the "special" value [](const Record *Def) { return Def->getName() != "AS_FromLeaves"; }); - GenerateEnumClass(associations, OS, "Association", + generateEnumClass(Associations, OS, "Association", /*Prefix=*/"", DirLang, /*ExportEnums=*/false); - GenerateEnumClass(DirLang.getCategories(), OS, "Category", /*Prefix=*/"", + generateEnumClass(DirLang.getCategories(), OS, "Category", /*Prefix=*/"", DirLang, /*ExportEnums=*/false); // Emit Directive enumeration - GenerateEnumClass(DirLang.getDirectives(), OS, "Directive", + generateEnumClass(DirLang.getDirectives(), OS, "Directive", DirLang.getDirectivePrefix(), DirLang, DirLang.hasMakeEnumAvailableInNamespace()); // Emit Clause enumeration - GenerateEnumClass(DirLang.getClauses(), OS, "Clause", + generateEnumClass(DirLang.getClauses(), OS, "Clause", DirLang.getClausePrefix(), DirLang, DirLang.hasMakeEnumAvailableInNamespace()); // Emit ClauseVal enumeration std::string EnumHelperFuncs; - GenerateEnumClauseVal(DirLang.getClauses(), OS, DirLang, EnumHelperFuncs); + generateEnumClauseVal(DirLang.getClauses(), OS, DirLang, EnumHelperFuncs); // Generic function signatures OS << "\n"; @@ -259,7 +259,7 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { << "Clause C, unsigned Version);\n"; OS << "\n"; OS << "constexpr std::size_t getMaxLeafCount() { return " - << GetMaxLeafCount(DirLang) << "; }\n"; + << getMaxLeafCount(DirLang) << "; }\n"; OS << "LLVM_ABI Association getDirectiveAssociation(Directive D);\n"; OS << "LLVM_ABI Category getDirectiveCategory(Directive D);\n"; if (EnumHelperFuncs.length() > 0) { @@ -277,7 +277,7 @@ static void EmitDirectivesDecl(const RecordKeeper &Records, raw_ostream &OS) { } // Generate function implementation for getName(StringRef Str) -static void GenerateGetName(ArrayRef Records, raw_ostream &OS, +static void generateGetName(ArrayRef Records, raw_ostream &OS, StringRef Enum, const DirectiveLanguage &DirLang, StringRef Prefix) { OS << "\n"; @@ -300,11 +300,11 @@ static void GenerateGetName(ArrayRef Records, raw_ostream &OS, } // Generate function implementation for getKind(StringRef Str) -static void GenerateGetKind(ArrayRef Records, raw_ostream &OS, +static void generateGetKind(ArrayRef Records, raw_ostream &OS, StringRef Enum, const DirectiveLanguage &DirLang, StringRef Prefix, bool ImplicitAsUnknown) { - auto DefaultIt = find_if( + const auto *DefaultIt = find_if( Records, [](const Record *R) { return R->getValueAsBit("isDefault"); }); if (DefaultIt == Records.end()) { @@ -334,7 +334,7 @@ static void GenerateGetKind(ArrayRef Records, raw_ostream &OS, } // Generate function implementation for getKind(StringRef Str) -static void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang, +static void generateGetKindClauseVal(const DirectiveLanguage &DirLang, raw_ostream &OS) { for (const Clause C : DirLang.getClauses()) { const auto &ClauseVals = C.getClauseVals(); @@ -389,7 +389,7 @@ static void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang, } } -static void GenerateCaseForVersionedClauses(ArrayRef Clauses, +static void generateCaseForVersionedClauses(ArrayRef Clauses, raw_ostream &OS, StringRef DirectiveName, const DirectiveLanguage &DirLang, @@ -406,7 +406,7 @@ static void GenerateCaseForVersionedClauses(ArrayRef Clauses, } } -static std::string GetDirectiveName(const DirectiveLanguage &DirLang, +static std::string getDirectiveName(const DirectiveLanguage &DirLang, const Record *Rec) { Directive Dir(Rec); return (Twine("llvm::") + DirLang.getCppNamespace() + @@ -414,12 +414,12 @@ static std::string GetDirectiveName(const DirectiveLanguage &DirLang, .str(); } -static std::string GetDirectiveType(const DirectiveLanguage &DirLang) { +static std::string getDirectiveType(const DirectiveLanguage &DirLang) { return (Twine("llvm::") + DirLang.getCppNamespace() + "::Directive").str(); } // Generate the isAllowedClauseForDirective function implementation. -static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang, +static void generateIsAllowedClause(const DirectiveLanguage &DirLang, raw_ostream &OS) { OS << "\n"; OS << "bool llvm::" << DirLang.getCppNamespace() @@ -445,16 +445,16 @@ static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang, StringSet<> Cases; - GenerateCaseForVersionedClauses(Dir.getAllowedClauses(), OS, + generateCaseForVersionedClauses(Dir.getAllowedClauses(), OS, Dir.getName(), DirLang, Cases); - GenerateCaseForVersionedClauses(Dir.getAllowedOnceClauses(), OS, + generateCaseForVersionedClauses(Dir.getAllowedOnceClauses(), OS, Dir.getName(), DirLang, Cases); - GenerateCaseForVersionedClauses(Dir.getAllowedExclusiveClauses(), OS, + generateCaseForVersionedClauses(Dir.getAllowedExclusiveClauses(), OS, Dir.getName(), DirLang, Cases); - GenerateCaseForVersionedClauses(Dir.getRequiredClauses(), OS, + generateCaseForVersionedClauses(Dir.getRequiredClauses(), OS, Dir.getName(), DirLang, Cases); OS << " default:\n"; @@ -470,7 +470,7 @@ static void GenerateIsAllowedClause(const DirectiveLanguage &DirLang, OS << "}\n"; // End of function isAllowedClauseForDirective } -static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, +static void emitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, StringRef TableName) { // The leaf constructs are emitted in a form of a 2D table, where each // row corresponds to a directive (and there is a row for each directive). @@ -498,7 +498,7 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, DirId.insert(std::make_pair(Rec, Idx)); using LeafList = std::vector; - int MaxLeafCount = GetMaxLeafCount(DirLang); + int MaxLeafCount = getMaxLeafCount(DirLang); // The initial leaf table, rows order is same as directive order. std::vector LeafTable(Directives.size()); @@ -560,19 +560,19 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, // type is `int` (by default). The code above uses `int` to store directive // ids, so make sure that we catch it when something changes in the // underlying type. - std::string DirectiveType = GetDirectiveType(DirLang); + std::string DirectiveType = getDirectiveType(DirLang); OS << "\nstatic_assert(sizeof(" << DirectiveType << ") == sizeof(int));\n"; OS << "[[maybe_unused]] static const " << DirectiveType << ' ' << TableName << "[][" << MaxLeafCount + 2 << "] = {\n"; for (size_t I = 0, E = Directives.size(); I != E; ++I) { auto &Leaves = LeafTable[Ordering[I]]; - OS << " {" << GetDirectiveName(DirLang, Directives[Leaves[0]]); + OS << " {" << getDirectiveName(DirLang, Directives[Leaves[0]]); OS << ", static_cast<" << DirectiveType << ">(" << Leaves[1] << "),"; for (size_t I = 2, E = Leaves.size(); I != E; ++I) { int Idx = Leaves[I]; if (Idx >= 0) - OS << ' ' << GetDirectiveName(DirLang, Directives[Leaves[I]]) << ','; + OS << ' ' << getDirectiveName(DirLang, Directives[Leaves[I]]) << ','; else OS << " static_cast<" << DirectiveType << ">(-1),"; } @@ -600,7 +600,7 @@ static void EmitLeafTable(const DirectiveLanguage &DirLang, raw_ostream &OS, OS << "\n};\n"; } -static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, +static void generateGetDirectiveAssociation(const DirectiveLanguage &DirLang, raw_ostream &OS) { enum struct Association { None = 0, // None should be the smallest value. @@ -613,10 +613,10 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, Invalid, }; - ArrayRef associations = DirLang.getAssociations(); + ArrayRef Associations = DirLang.getAssociations(); - auto getAssocValue = [](StringRef name) -> Association { - return StringSwitch(name) + auto GetAssocValue = [](StringRef Name) -> Association { + return StringSwitch(Name) .Case("AS_Block", Association::Block) .Case("AS_Declaration", Association::Declaration) .Case("AS_Delimited", Association::Delimited) @@ -627,24 +627,24 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, .Default(Association::Invalid); }; - auto getAssocName = [&](Association A) -> StringRef { + auto GetAssocName = [&](Association A) -> StringRef { if (A != Association::Invalid && A != Association::FromLeaves) { - auto F = find_if(associations, [&](const Record *R) { - return getAssocValue(R->getName()) == A; + const auto *F = find_if(Associations, [&](const Record *R) { + return GetAssocValue(R->getName()) == A; }); - if (F != associations.end()) + if (F != Associations.end()) return (*F)->getValueAsString("name"); // enum name } llvm_unreachable("Unexpected association value"); }; - auto errorPrefixFor = [&](Directive D) -> std::string { + auto ErrorPrefixFor = [&](Directive D) -> std::string { return (Twine("Directive '") + D.getName() + "' in namespace '" + DirLang.getCppNamespace() + "' ") .str(); }; - auto reduce = [&](Association A, Association B) -> Association { + auto Reduce = [&](Association A, Association B) -> Association { if (A > B) std::swap(A, B); @@ -663,14 +663,14 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, DenseMap AsMap; - auto compAssocImpl = [&](const Record *R, auto &&Self) -> Association { + auto CompAssocImpl = [&](const Record *R, auto &&Self) -> Association { if (auto F = AsMap.find(R); F != AsMap.end()) return F->second; Directive D(R); - Association AS = getAssocValue(D.getAssociation()->getName()); + Association AS = GetAssocValue(D.getAssociation()->getName()); if (AS == Association::Invalid) { - PrintFatalError(errorPrefixFor(D) + + PrintFatalError(ErrorPrefixFor(D) + "has an unrecognized value for association: '" + D.getAssociation()->getName() + "'"); } @@ -679,22 +679,22 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, return AS; } // Compute the association from leaf constructs. - std::vector leaves = D.getLeafConstructs(); - if (leaves.empty()) { + std::vector Leaves = D.getLeafConstructs(); + if (Leaves.empty()) { errs() << D.getName() << '\n'; - PrintFatalError(errorPrefixFor(D) + + PrintFatalError(ErrorPrefixFor(D) + "requests association to be computed from leaves, " "but it has no leaves"); } - Association Result = Self(leaves[0], Self); - for (int I = 1, E = leaves.size(); I < E; ++I) { - Association A = Self(leaves[I], Self); - Association R = reduce(Result, A); + Association Result = Self(Leaves[0], Self); + for (int I = 1, E = Leaves.size(); I < E; ++I) { + Association A = Self(Leaves[I], Self); + Association R = Reduce(Result, A); if (R == Association::Invalid) { - PrintFatalError(errorPrefixFor(D) + + PrintFatalError(ErrorPrefixFor(D) + "has leaves with incompatible association values: " + - getAssocName(A) + " and " + getAssocName(R)); + GetAssocName(A) + " and " + GetAssocName(R)); } Result = R; } @@ -706,11 +706,11 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, }; for (const Record *R : DirLang.getDirectives()) - compAssocImpl(R, compAssocImpl); // Updates AsMap. + CompAssocImpl(R, CompAssocImpl); // Updates AsMap. OS << '\n'; - auto getQualifiedName = [&](StringRef Formatted) -> std::string { + auto GetQualifiedName = [&](StringRef Formatted) -> std::string { return (Twine("llvm::") + DirLang.getCppNamespace() + "::Directive::" + DirLang.getDirectivePrefix() + Formatted) .str(); @@ -727,9 +727,9 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, for (const Record *R : DirLang.getDirectives()) { if (auto F = AsMap.find(R); F != AsMap.end()) { Directive Dir(R); - OS << " case " << getQualifiedName(Dir.getFormattedName()) << ":\n"; + OS << " case " << GetQualifiedName(Dir.getFormattedName()) << ":\n"; OS << " return " << AssociationTypeName - << "::" << getAssocName(F->second) << ";\n"; + << "::" << GetAssocName(F->second) << ";\n"; } } OS << " } // switch (Dir)\n"; @@ -737,7 +737,7 @@ static void GenerateGetDirectiveAssociation(const DirectiveLanguage &DirLang, OS << "}\n"; } -static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang, +static void generateGetDirectiveCategory(const DirectiveLanguage &DirLang, raw_ostream &OS) { std::string LangNamespace = "llvm::" + DirLang.getCppNamespace().str(); std::string CategoryTypeName = LangNamespace + "::Category"; @@ -745,12 +745,12 @@ static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang, OS << '\n'; OS << CategoryTypeName << ' ' << LangNamespace << "::getDirectiveCategory(" - << GetDirectiveType(DirLang) << " Dir) {\n"; + << getDirectiveType(DirLang) << " Dir) {\n"; OS << " switch (Dir) {\n"; for (const Record *R : DirLang.getDirectives()) { Directive D(R); - OS << " case " << GetDirectiveName(DirLang, R) << ":\n"; + OS << " case " << getDirectiveName(DirLang, R) << ":\n"; OS << " return " << CategoryNamespace << D.getCategory()->getValueAsString("name") << ";\n"; } @@ -760,7 +760,7 @@ static void GenerateGetDirectiveCategory(const DirectiveLanguage &DirLang, } // Generate a simple enum set with the give clauses. -static void GenerateClauseSet(ArrayRef Clauses, raw_ostream &OS, +static void generateClauseSet(ArrayRef Clauses, raw_ostream &OS, StringRef ClauseSetPrefix, const Directive &Dir, const DirectiveLanguage &DirLang) { @@ -778,7 +778,7 @@ static void GenerateClauseSet(ArrayRef Clauses, raw_ostream &OS, } // Generate an enum set for the 4 kinds of clauses linked to a directive. -static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang, +static void generateDirectiveClauseSets(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_DIRECTIVE_CLAUSE_SETS", OS); @@ -796,13 +796,13 @@ static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang, OS << "\n"; OS << " // Sets for " << Dir.getName() << "\n"; - GenerateClauseSet(Dir.getAllowedClauses(), OS, "allowedClauses_", Dir, + generateClauseSet(Dir.getAllowedClauses(), OS, "allowedClauses_", Dir, DirLang); - GenerateClauseSet(Dir.getAllowedOnceClauses(), OS, "allowedOnceClauses_", + generateClauseSet(Dir.getAllowedOnceClauses(), OS, "allowedOnceClauses_", Dir, DirLang); - GenerateClauseSet(Dir.getAllowedExclusiveClauses(), OS, + generateClauseSet(Dir.getAllowedExclusiveClauses(), OS, "allowedExclusiveClauses_", Dir, DirLang); - GenerateClauseSet(Dir.getRequiredClauses(), OS, "requiredClauses_", Dir, + generateClauseSet(Dir.getRequiredClauses(), OS, "requiredClauses_", Dir, DirLang); } @@ -816,7 +816,7 @@ static void GenerateDirectiveClauseSets(const DirectiveLanguage &DirLang, // Generate a map of directive (key) with DirectiveClauses struct as values. // The struct holds the 4 sets of enumeration for the 4 kinds of clauses // allowances (allowed, allowed once, allowed exclusive and required). -static void GenerateDirectiveClauseMap(const DirectiveLanguage &DirLang, +static void generateDirectiveClauseMap(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_DIRECTIVE_CLAUSE_MAP", OS); @@ -850,7 +850,7 @@ static void GenerateDirectiveClauseMap(const DirectiveLanguage &DirLang, // If the clause does not hold a value, an EMPTY_CLASS is used. // If the clause class is generic then a WRAPPER_CLASS is used. When the value // is optional, the value class is wrapped into a std::optional. -static void GenerateFlangClauseParserClass(const DirectiveLanguage &DirLang, +static void generateFlangClauseParserClass(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES", OS); @@ -877,7 +877,7 @@ static void GenerateFlangClauseParserClass(const DirectiveLanguage &DirLang, } // Generate a list of the different clause classes for Flang. -static void GenerateFlangClauseParserClassList(const DirectiveLanguage &DirLang, +static void generateFlangClauseParserClassList(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_CLASSES_LIST", OS); @@ -890,7 +890,7 @@ static void GenerateFlangClauseParserClassList(const DirectiveLanguage &DirLang, } // Generate dump node list for the clauses holding a generic class name. -static void GenerateFlangClauseDump(const DirectiveLanguage &DirLang, +static void generateFlangClauseDump(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_DUMP_PARSE_TREE_CLAUSES", OS); @@ -904,7 +904,7 @@ static void GenerateFlangClauseDump(const DirectiveLanguage &DirLang, // Generate Unparse functions for clauses classes in the Flang parse-tree // If the clause is a non-generic class, no entry is generated. -static void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang, +static void generateFlangClauseUnparse(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_UNPARSE", OS); @@ -955,7 +955,7 @@ static void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang, } // Generate check in the Enter functions for clauses classes. -static void GenerateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang, +static void generateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_CHECK_ENTER", OS); @@ -969,7 +969,7 @@ static void GenerateFlangClauseCheckPrototypes(const DirectiveLanguage &DirLang, // Generate the mapping for clauses between the parser class and the // corresponding clause Kind -static void GenerateFlangClauseParserKindMap(const DirectiveLanguage &DirLang, +static void generateFlangClauseParserKindMap(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_FLANG_CLAUSE_PARSER_KIND_MAP", OS); @@ -996,7 +996,7 @@ static bool compareClauseName(const Record *R1, const Record *R2) { } // Generate the parser for the clauses. -static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, +static void generateFlangClausesParser(const DirectiveLanguage &DirLang, raw_ostream &OS) { std::vector Clauses = DirLang.getClauses(); // Sort clauses in reverse alphabetical order so with clauses with same @@ -1004,8 +1004,8 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, sort(Clauses, compareClauseName); IfDefScope Scope("GEN_FLANG_CLAUSES_PARSER", OS); OS << "\n"; - unsigned index = 0; - unsigned lastClauseIndex = Clauses.size() - 1; + unsigned Index = 0; + unsigned LastClauseIndex = Clauses.size() - 1; OS << "TYPE_PARSER(\n"; for (const Clause Clause : Clauses) { if (Clause.getAliases().empty()) { @@ -1013,8 +1013,8 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, } else { OS << " (" << "\"" << Clause.getName() << "\"_tok"; - for (StringRef alias : Clause.getAliases()) { - OS << " || \"" << alias << "\"_tok"; + for (StringRef Alias : Clause.getAliases()) { + OS << " || \"" << Alias << "\"_tok"; } OS << ")"; } @@ -1024,10 +1024,10 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, << "::" << Clause.getFormattedParserClassName() << ">("; if (Clause.getFlangClass().empty()) { OS << "))"; - if (index != lastClauseIndex) + if (Index != LastClauseIndex) OS << " ||"; OS << "\n"; - ++index; + ++Index; continue; } @@ -1064,38 +1064,38 @@ static void GenerateFlangClausesParser(const DirectiveLanguage &DirLang, if (Clause.isValueOptional()) // close maybe(. OS << ")"; OS << "))"; - if (index != lastClauseIndex) + if (Index != LastClauseIndex) OS << " ||"; OS << "\n"; - ++index; + ++Index; } OS << ")\n"; } // Generate the implementation section for the enumeration in the directive // language -static void EmitDirectivesFlangImpl(const DirectiveLanguage &DirLang, +static void emitDirectivesFlangImpl(const DirectiveLanguage &DirLang, raw_ostream &OS) { - GenerateDirectiveClauseSets(DirLang, OS); + generateDirectiveClauseSets(DirLang, OS); - GenerateDirectiveClauseMap(DirLang, OS); + generateDirectiveClauseMap(DirLang, OS); - GenerateFlangClauseParserClass(DirLang, OS); + generateFlangClauseParserClass(DirLang, OS); - GenerateFlangClauseParserClassList(DirLang, OS); + generateFlangClauseParserClassList(DirLang, OS); - GenerateFlangClauseDump(DirLang, OS); + generateFlangClauseDump(DirLang, OS); - GenerateFlangClauseUnparse(DirLang, OS); + generateFlangClauseUnparse(DirLang, OS); - GenerateFlangClauseCheckPrototypes(DirLang, OS); + generateFlangClauseCheckPrototypes(DirLang, OS); - GenerateFlangClauseParserKindMap(DirLang, OS); + generateFlangClauseParserKindMap(DirLang, OS); - GenerateFlangClausesParser(DirLang, OS); + generateFlangClausesParser(DirLang, OS); } -static void GenerateClauseClassMacro(const DirectiveLanguage &DirLang, +static void generateClauseClassMacro(const DirectiveLanguage &DirLang, raw_ostream &OS) { // Generate macros style information for legacy code in clang IfDefScope Scope("GEN_CLANG_CLAUSE_CLASS", OS); @@ -1163,63 +1163,63 @@ static void GenerateClauseClassMacro(const DirectiveLanguage &DirLang, // Generate the implemenation for the enumeration in the directive // language. This code can be included in library. -void EmitDirectivesBasicImpl(const DirectiveLanguage &DirLang, +void emitDirectivesBasicImpl(const DirectiveLanguage &DirLang, raw_ostream &OS) { IfDefScope Scope("GEN_DIRECTIVES_IMPL", OS); OS << "\n#include \"llvm/Support/ErrorHandling.h\"\n"; // getDirectiveKind(StringRef Str) - GenerateGetKind(DirLang.getDirectives(), OS, "Directive", DirLang, + generateGetKind(DirLang.getDirectives(), OS, "Directive", DirLang, DirLang.getDirectivePrefix(), /*ImplicitAsUnknown=*/false); // getDirectiveName(Directive Kind) - GenerateGetName(DirLang.getDirectives(), OS, "Directive", DirLang, + generateGetName(DirLang.getDirectives(), OS, "Directive", DirLang, DirLang.getDirectivePrefix()); // getClauseKind(StringRef Str) - GenerateGetKind(DirLang.getClauses(), OS, "Clause", DirLang, + generateGetKind(DirLang.getClauses(), OS, "Clause", DirLang, DirLang.getClausePrefix(), /*ImplicitAsUnknown=*/true); // getClauseName(Clause Kind) - GenerateGetName(DirLang.getClauses(), OS, "Clause", DirLang, + generateGetName(DirLang.getClauses(), OS, "Clause", DirLang, DirLang.getClausePrefix()); // getKind(StringRef Str) - GenerateGetKindClauseVal(DirLang, OS); + generateGetKindClauseVal(DirLang, OS); // isAllowedClauseForDirective(Directive D, Clause C, unsigned Version) - GenerateIsAllowedClause(DirLang, OS); + generateIsAllowedClause(DirLang, OS); // getDirectiveAssociation(Directive D) - GenerateGetDirectiveAssociation(DirLang, OS); + generateGetDirectiveAssociation(DirLang, OS); // getDirectiveCategory(Directive D) - GenerateGetDirectiveCategory(DirLang, OS); + generateGetDirectiveCategory(DirLang, OS); // Leaf table for getLeafConstructs, etc. - EmitLeafTable(DirLang, OS, "LeafConstructTable"); + emitLeafTable(DirLang, OS, "LeafConstructTable"); } // Generate the implemenation section for the enumeration in the directive // language. -static void EmitDirectivesImpl(const RecordKeeper &Records, raw_ostream &OS) { +static void emitDirectivesImpl(const RecordKeeper &Records, raw_ostream &OS) { const auto DirLang = DirectiveLanguage(Records); if (DirLang.HasValidityErrors()) return; - EmitDirectivesFlangImpl(DirLang, OS); + emitDirectivesFlangImpl(DirLang, OS); - GenerateClauseClassMacro(DirLang, OS); + generateClauseClassMacro(DirLang, OS); - EmitDirectivesBasicImpl(DirLang, OS); + emitDirectivesBasicImpl(DirLang, OS); } static TableGen::Emitter::Opt - X("gen-directive-decl", EmitDirectivesDecl, + X("gen-directive-decl", emitDirectivesDecl, "Generate directive related declaration code (header file)"); static TableGen::Emitter::Opt - Y("gen-directive-impl", EmitDirectivesImpl, + Y("gen-directive-impl", emitDirectivesImpl, "Generate directive related implementation code"); diff --git a/llvm/utils/TableGen/DisassemblerEmitter.cpp b/llvm/utils/TableGen/DisassemblerEmitter.cpp index eb15392272a3f31fb1aeed9037df1cc87375be54..70d835e699ffefffd6db7a6303ab04fc23c17dcf 100644 --- a/llvm/utils/TableGen/DisassemblerEmitter.cpp +++ b/llvm/utils/TableGen/DisassemblerEmitter.cpp @@ -95,7 +95,7 @@ using namespace llvm::X86Disassembler; /// X86RecognizableInstr.cpp contains the implementation for a single /// instruction. -static void EmitDisassembler(const RecordKeeper &Records, raw_ostream &OS) { +static void emitDisassembler(const RecordKeeper &Records, raw_ostream &OS) { const CodeGenTarget Target(Records); emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS); @@ -132,5 +132,5 @@ static void EmitDisassembler(const RecordKeeper &Records, raw_ostream &OS) { cl::OptionCategory DisassemblerEmitterCat("Options for -gen-disassembler"); -static TableGen::Emitter::Opt X("gen-disassembler", EmitDisassembler, +static TableGen::Emitter::Opt X("gen-disassembler", emitDisassembler, "Generate disassembler"); diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp index 17198c85f0600912cfa8878e36b8be9585ab5ac3..2052222cae5e5f2fd88abd06f77ae804b9e226ae 100644 --- a/llvm/utils/TableGen/FastISelEmitter.cpp +++ b/llvm/utils/TableGen/FastISelEmitter.cpp @@ -718,19 +718,20 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { const PredMap &PM = RI.second; OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" - << getLegalCName(std::string(getName(VT))) << "_" - << getLegalCName(std::string(getName(RetVT))) << "_"; + << getLegalCName(std::string(getEnumName(VT))) << "_" + << getLegalCName(std::string(getEnumName(RetVT))) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "("; Operands.PrintParameters(OS); OS << ") {\n"; - emitInstructionCode(OS, Operands, PM, std::string(getName(RetVT))); + emitInstructionCode(OS, Operands, PM, + std::string(getEnumName(RetVT))); } // Emit one function for the type that demultiplexes on return type. OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" - << getLegalCName(std::string(getName(VT))) << "_"; + << getLegalCName(std::string(getEnumName(VT))) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(MVT RetVT"; if (!Operands.empty()) @@ -739,10 +740,10 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { OS << ") {\nswitch (RetVT.SimpleTy) {\n"; for (const auto &RI : RM) { MVT::SimpleValueType RetVT = RI.first; - OS << " case " << getName(RetVT) << ": return fastEmit_" + OS << " case " << getEnumName(RetVT) << ": return fastEmit_" << getLegalCName(Opcode) << "_" - << getLegalCName(std::string(getName(VT))) << "_" - << getLegalCName(std::string(getName(RetVT))) << "_"; + << getLegalCName(std::string(getEnumName(VT))) << "_" + << getLegalCName(std::string(getEnumName(RetVT))) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "("; Operands.PrintArguments(OS); @@ -753,7 +754,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { } else { // Non-variadic return type. OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" - << getLegalCName(std::string(getName(VT))) << "_"; + << getLegalCName(std::string(getEnumName(VT))) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); OS << "(MVT RetVT"; if (!Operands.empty()) @@ -761,7 +762,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { Operands.PrintParameters(OS); OS << ") {\n"; - OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) + OS << " if (RetVT.SimpleTy != " << getEnumName(RM.begin()->first) << ")\n return 0;\n"; const PredMap &PM = RM.begin()->second; @@ -781,7 +782,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { OS << " switch (VT.SimpleTy) {\n"; for (const auto &TI : TM) { MVT::SimpleValueType VT = TI.first; - std::string TypeName = std::string(getName(VT)); + std::string TypeName = std::string(getEnumName(VT)); OS << " case " << TypeName << ": return fastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; Operands.PrintManglingSuffix(OS, ImmediatePredicates); diff --git a/llvm/utils/TableGen/OptionParserEmitter.cpp b/llvm/utils/TableGen/OptionParserEmitter.cpp index cd7a140bb23143b0c3a0f008e538cf092d6443f3..86e8378ad5ac5d67d363ef29cceaf10e48278ba0 100644 --- a/llvm/utils/TableGen/OptionParserEmitter.cpp +++ b/llvm/utils/TableGen/OptionParserEmitter.cpp @@ -26,7 +26,7 @@ static std::string getOptionName(const Record &R) { return std::string(R.getValueAsString("EnumName")); } -static raw_ostream &write_cstring(raw_ostream &OS, llvm::StringRef Str) { +static raw_ostream &writeCstring(raw_ostream &OS, llvm::StringRef Str) { OS << '"'; OS.write_escaped(Str); OS << '"'; @@ -117,7 +117,7 @@ struct SimpleEnumValueTable { OS << "static const SimpleEnumValue " << ValueTableName << "[] = {\n"; for (unsigned I = 0, E = Values.size(); I != E; ++I) { OS << "{"; - write_cstring(OS, Values[I]); + writeCstring(OS, Values[I]); OS << ","; OS << "static_cast("; emitScopedNormalizedValue(OS, NormalizedValues[I]); @@ -190,7 +190,7 @@ static MarshallingInfo createMarshallingInfo(const Record &R) { return Ret; } -static void EmitHelpTextsForVariants( +static void emitHelpTextsForVariants( raw_ostream &OS, std::vector, StringRef>> HelpTextsForVariants) { // OptTable must be constexpr so it uses std::arrays with these capacities. @@ -235,7 +235,7 @@ static void EmitHelpTextsForVariants( OS << "}}, "; if (Help.size()) - write_cstring(OS, Help); + writeCstring(OS, Help); else OS << "nullptr"; OS << ")"; @@ -249,7 +249,7 @@ static void EmitHelpTextsForVariants( /// OptionParserEmitter - This tablegen backend takes an input .td file /// describing a list of options and emits a data structure for parsing and /// working with those options when given an input command line. -static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { +static void emitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { // Get the option groups and options. ArrayRef Groups = Records.getAllDerivedDefinitions("OptionGroup"); @@ -363,12 +363,12 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { if (!isa(R.getValueInit("HelpText"))) { OS << ",\n"; OS << " "; - write_cstring(OS, R.getValueAsString("HelpText")); + writeCstring(OS, R.getValueAsString("HelpText")); } else OS << ", nullptr"; // Not using Visibility specific text for group help. - EmitHelpTextsForVariants(OS, {}); + emitHelpTextsForVariants(OS, {}); // The option meta-variable name (unused). OS << ", nullptr"; @@ -387,7 +387,7 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { OS << Prefixes[PrefixKeyT(RPrefixes.begin(), RPrefixes.end())] << ", "; // The option prefixed name. - write_cstring(OS, getOptionPrefixedName(R)); + writeCstring(OS, getOptionPrefixedName(R)); // The option identifier name. OS << ", " << getOptionName(R); @@ -464,7 +464,7 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { if (!isa(R.getValueInit("HelpText"))) { OS << ",\n"; OS << " "; - write_cstring(OS, R.getValueAsString("HelpText")); + writeCstring(OS, R.getValueAsString("HelpText")); } else OS << ", nullptr"; @@ -482,19 +482,19 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { HelpTextsForVariants.push_back(std::make_pair( VisibilityNames, VisibilityHelp->getValueAsString("Text"))); } - EmitHelpTextsForVariants(OS, HelpTextsForVariants); + emitHelpTextsForVariants(OS, HelpTextsForVariants); // The option meta-variable name. OS << ", "; if (!isa(R.getValueInit("MetaVarName"))) - write_cstring(OS, R.getValueAsString("MetaVarName")); + writeCstring(OS, R.getValueAsString("MetaVarName")); else OS << "nullptr"; // The option Values. Used for shell autocompletion. OS << ", "; if (!isa(R.getValueInit("Values"))) - write_cstring(OS, R.getValueAsString("Values")); + writeCstring(OS, R.getValueAsString("Values")); else if (!isa(R.getValueInit("ValuesCode"))) { OS << getOptionName(R) << "_Values"; } else @@ -571,5 +571,5 @@ static void EmitOptionParser(const RecordKeeper &Records, raw_ostream &OS) { OS << "\n"; } -static TableGen::Emitter::Opt X("gen-opt-parser-defs", EmitOptionParser, +static TableGen::Emitter::Opt X("gen-opt-parser-defs", emitOptionParser, "Generate option definitions"); diff --git a/llvm/utils/TableGen/OptionRSTEmitter.cpp b/llvm/utils/TableGen/OptionRSTEmitter.cpp index 1b4c4cad4f0a4516e4733415846836f1aa17289a..6eac10e1831f022e60605c17c3016a45aad7edbb 100644 --- a/llvm/utils/TableGen/OptionRSTEmitter.cpp +++ b/llvm/utils/TableGen/OptionRSTEmitter.cpp @@ -16,7 +16,7 @@ using namespace llvm; /// This tablegen backend takes an input .td file describing a list of options /// and emits a RST man page. -static void EmitOptionRST(const RecordKeeper &Records, raw_ostream &OS) { +static void emitOptionRst(const RecordKeeper &Records, raw_ostream &OS) { llvm::StringMap> OptionsByGroup; // Get the options. @@ -96,5 +96,5 @@ static void EmitOptionRST(const RecordKeeper &Records, raw_ostream &OS) { } } -static TableGen::Emitter::Opt X("gen-opt-rst", EmitOptionRST, +static TableGen::Emitter::Opt X("gen-opt-rst", emitOptionRst, "Generate option RST"); diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 23496a37d5ea1c3b1d74acca0ffae80c180be42c..39211aab6f2d1ec80636b37e79c7e938273022d3 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -244,13 +244,13 @@ static void emitRISCVExtensionBitmask(const RecordKeeper &RK, raw_ostream &OS) { OS << "#endif\n"; } -static void EmitRISCVTargetDef(const RecordKeeper &RK, raw_ostream &OS) { +static void emitRiscvTargetDef(const RecordKeeper &RK, raw_ostream &OS) { emitRISCVExtensions(RK, OS); emitRISCVProfiles(RK, OS); emitRISCVProcs(RK, OS); emitRISCVExtensionBitmask(RK, OS); } -static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef, +static TableGen::Emitter::Opt X("gen-riscv-target-def", emitRiscvTargetDef, "Generate the list of CPUs and extensions for " "RISC-V"); diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp index 17b84d06fe8573886f09a194b1dd3f590a43a0ec..02c799cb6f1471063599f5f640a2c7120d82e76f 100644 --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -87,65 +87,65 @@ class SubtargetEmitter { CodeGenSchedModels &SchedModels; std::string Target; - FeatureMapTy Enumeration(raw_ostream &OS); - void EmitSubtargetInfoMacroCalls(raw_ostream &OS); - unsigned FeatureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap); - unsigned CPUKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap); - void FormItineraryStageString(const std::string &Names, + FeatureMapTy enumeration(raw_ostream &OS); + void emitSubtargetInfoMacroCalls(raw_ostream &OS); + unsigned featureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap); + unsigned cpuKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap); + void formItineraryStageString(const std::string &Names, const Record *ItinData, std::string &ItinString, unsigned &NStages); - void FormItineraryOperandCycleString(const Record *ItinData, + void formItineraryOperandCycleString(const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles); - void FormItineraryBypassString(const std::string &Names, + void formItineraryBypassString(const std::string &Names, const Record *ItinData, std::string &ItinString, unsigned NOperandCycles); - void EmitStageAndOperandCycleData( + void emitStageAndOperandCycleData( raw_ostream &OS, std::vector> &ProcItinLists); - void EmitItineraries(raw_ostream &OS, + void emitItineraries(raw_ostream &OS, std::vector> &ProcItinLists); - unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel, + unsigned emitRegisterFileTables(const CodeGenProcModel &ProcModel, raw_ostream &OS); - void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, + void emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS); - void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, + void emitExtraProcessorInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS); - void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name, + void emitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name, char Separator); - void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel, + void emitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel, raw_ostream &OS); - void EmitProcessorResources(const CodeGenProcModel &ProcModel, + void emitProcessorResources(const CodeGenProcModel &ProcModel, raw_ostream &OS); - const Record *FindWriteResources(const CodeGenSchedRW &SchedWrite, + const Record *findWriteResources(const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel); - const Record *FindReadAdvance(const CodeGenSchedRW &SchedRead, + const Record *findReadAdvance(const CodeGenSchedRW &SchedRead, const CodeGenProcModel &ProcModel); - void ExpandProcResources(ConstRecVec &PRVec, + void expandProcResources(ConstRecVec &PRVec, std::vector &ReleaseAtCycles, std::vector &AcquireAtCycles, const CodeGenProcModel &ProcModel); - void GenSchedClassTables(const CodeGenProcModel &ProcModel, + void genSchedClassTables(const CodeGenProcModel &ProcModel, SchedClassTables &SchedTables); - void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS); - void EmitProcessorModels(raw_ostream &OS); - void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS); + void emitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS); + void emitProcessorModels(raw_ostream &OS); + void emitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS); void emitSchedModelHelpersImpl(raw_ostream &OS, bool OnlyExpandMCInstPredicates = false); void emitGenMCSubtargetInfo(raw_ostream &OS); - void EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS); + void emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS); - void EmitSchedModel(raw_ostream &OS); + void emitSchedModel(raw_ostream &OS); void emitGetMacroFusions(const std::string &ClassName, raw_ostream &OS); - void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS); - void ParseFeaturesFunction(raw_ostream &OS); + void emitHwModeCheck(const std::string &ClassName, raw_ostream &OS); + void parseFeaturesFunction(raw_ostream &OS); public: SubtargetEmitter(const RecordKeeper &R) : TGT(R), Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {} - void run(raw_ostream &o); + void run(raw_ostream &O); }; } // end anonymous namespace @@ -153,7 +153,7 @@ public: // // Enumeration - Emit the specified class as an enumeration. // -FeatureMapTy SubtargetEmitter::Enumeration(raw_ostream &OS) { +FeatureMapTy SubtargetEmitter::enumeration(raw_ostream &OS) { ArrayRef DefList = Records.getAllDerivedDefinitions("SubtargetFeature"); @@ -171,15 +171,15 @@ FeatureMapTy SubtargetEmitter::Enumeration(raw_ostream &OS) { FeatureMapTy FeatureMap; // For each record - for (unsigned i = 0; i < N; ++i) { + for (unsigned I = 0; I < N; ++I) { // Next record - const Record *Def = DefList[i]; + const Record *Def = DefList[I]; // Get and emit name - OS << " " << Def->getName() << " = " << i << ",\n"; + OS << " " << Def->getName() << " = " << I << ",\n"; // Save the index for this feature. - FeatureMap[Def] = i; + FeatureMap[Def] = I; } OS << " " @@ -201,9 +201,9 @@ static void printFeatureMask(raw_ostream &OS, } OS << "{ { { "; - for (unsigned i = 0; i != Mask.size(); ++i) { + for (unsigned I = 0; I != Mask.size(); ++I) { OS << "0x"; - OS.write_hex(Mask[i]); + OS.write_hex(Mask[I]); OS << "ULL, "; } OS << "} } }"; @@ -211,7 +211,7 @@ static void printFeatureMask(raw_ostream &OS, /// Emit some information about the SubtargetFeature as calls to a macro so /// that they can be used from C++. -void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) { +void SubtargetEmitter::emitSubtargetInfoMacroCalls(raw_ostream &OS) { OS << "\n#ifdef GET_SUBTARGETINFO_MACRO\n"; std::vector FeatureList = @@ -252,7 +252,7 @@ void SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) { // FeatureKeyValues - Emit data of all the subtarget features. Used by the // command line. // -unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS, +unsigned SubtargetEmitter::featureKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap) { std::vector FeatureList = Records.getAllDerivedDefinitions("SubtargetFeature"); @@ -301,7 +301,7 @@ unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS, // CPUKeyValues - Emit data of all the subtarget processors. Used by command // line. // -unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS, +unsigned SubtargetEmitter::cpuKeyValues(raw_ostream &OS, const FeatureMapTy &FeatureMap) { // Gather and sort processor information std::vector ProcessorList = @@ -349,7 +349,7 @@ unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS, // data initialization for the specified itinerary. N is the number // of stages. // -void SubtargetEmitter::FormItineraryStageString(const std::string &Name, +void SubtargetEmitter::formItineraryStageString(const std::string &Name, const Record *ItinData, std::string &ItinString, unsigned &NStages) { @@ -358,9 +358,9 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, // For each stage unsigned N = NStages = StageList.size(); - for (unsigned i = 0; i < N;) { + for (unsigned I = 0; I < N;) { // Next stage - const Record *Stage = StageList[i]; + const Record *Stage = StageList[I]; // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind } int Cycles = Stage->getValueAsInt("Cycles"); @@ -370,10 +370,10 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, ConstRecVec UnitList = Stage->getValueAsListOfDefs("Units"); // For each unit - for (unsigned j = 0, M = UnitList.size(); j < M;) { + for (unsigned J = 0, M = UnitList.size(); J < M;) { // Add name and bitwise or - ItinString += Name + "FU::" + UnitList[j]->getName().str(); - if (++j < M) + ItinString += Name + "FU::" + UnitList[J]->getName().str(); + if (++J < M) ItinString += " | "; } @@ -385,7 +385,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, // Close off stage ItinString += " }"; - if (++i < N) + if (++I < N) ItinString += ", "; } } @@ -395,7 +395,7 @@ void SubtargetEmitter::FormItineraryStageString(const std::string &Name, // operand cycle initialization for the specified itinerary. N is the // number of operands that has cycles specified. // -void SubtargetEmitter::FormItineraryOperandCycleString( +void SubtargetEmitter::formItineraryOperandCycleString( const Record *ItinData, std::string &ItinString, unsigned &NOperandCycles) { // Get operand cycle list std::vector OperandCycleList = @@ -411,19 +411,19 @@ void SubtargetEmitter::FormItineraryOperandCycleString( } } -void SubtargetEmitter::FormItineraryBypassString(const std::string &Name, +void SubtargetEmitter::formItineraryBypassString(const std::string &Name, const Record *ItinData, std::string &ItinString, unsigned NOperandCycles) { ConstRecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); unsigned N = BypassList.size(); - unsigned i = 0; + unsigned I = 0; ListSeparator LS; - for (; i < N; ++i) { + for (; I < N; ++I) { ItinString += LS; - ItinString += Name + "Bypass::" + BypassList[i]->getName().str(); + ItinString += Name + "Bypass::" + BypassList[I]->getName().str(); } - for (; i < NOperandCycles; ++i) { + for (; I < NOperandCycles; ++I) { ItinString += LS; ItinString += " 0"; } @@ -434,7 +434,7 @@ void SubtargetEmitter::FormItineraryBypassString(const std::string &Name, // cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed // by CodeGenSchedClass::Index. // -void SubtargetEmitter::EmitStageAndOperandCycleData( +void SubtargetEmitter::emitStageAndOperandCycleData( raw_ostream &OS, std::vector> &ProcItinLists) { // Multiple processor models may share an itinerary record. Emit it once. SmallPtrSet ItinsDefSet; @@ -453,9 +453,9 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( OS << "\n// Functional units for \"" << Name << "\"\n" << "namespace " << Name << "FU {\n"; - for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j) - OS << " const InstrStage::FuncUnits " << FUs[j]->getName() - << " = 1ULL << " << j << ";\n"; + for (unsigned J = 0, FUN = FUs.size(); J < FUN; ++J) + OS << " const InstrStage::FuncUnits " << FUs[J]->getName() + << " = 1ULL << " << J << ";\n"; OS << "} // end namespace " << Name << "FU\n"; @@ -466,8 +466,8 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( << "namespace " << Name << "Bypass {\n"; OS << " const unsigned NoBypass = 0;\n"; - for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j) - OS << " const unsigned " << BPs[j]->getName() << " = 1 << " << j + for (unsigned J = 0, BPN = BPs.size(); J < BPN; ++J) + OS << " const unsigned " << BPs[J]->getName() << " = 1 << " << J << ";\n"; OS << "} // end namespace " << Name << "Bypass\n"; @@ -518,7 +518,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( std::string ItinStageString; unsigned NStages = 0; if (ItinData) - FormItineraryStageString(std::string(Name), ItinData, ItinStageString, + formItineraryStageString(std::string(Name), ItinData, ItinStageString, NStages); // Get string and operand cycle count @@ -526,10 +526,10 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( unsigned NOperandCycles = 0; std::string ItinBypassString; if (ItinData) { - FormItineraryOperandCycleString(ItinData, ItinOperandCycleString, + formItineraryOperandCycleString(ItinData, ItinOperandCycleString, NOperandCycles); - FormItineraryBypassString(std::string(Name), ItinData, ItinBypassString, + formItineraryBypassString(std::string(Name), ItinData, ItinBypassString, NOperandCycles); } @@ -610,7 +610,7 @@ void SubtargetEmitter::EmitStageAndOperandCycleData( // Itineraries for each processor. The Itinerary lists are indexed on // CodeGenSchedClass::Index. // -void SubtargetEmitter::EmitItineraries( +void SubtargetEmitter::emitItineraries( raw_ostream &OS, std::vector> &ProcItinLists) { // Multiple processor models may share an itinerary record. Emit it once. SmallPtrSet ItinsDefSet; @@ -642,15 +642,15 @@ void SubtargetEmitter::EmitItineraries( OS << ItinsDef->getName() << "[] = {\n"; // For each itinerary class in CodeGenSchedClass::Index order. - for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { - InstrItinerary &Intinerary = ItinList[j]; + for (unsigned J = 0, M = ItinList.size(); J < M; ++J) { + InstrItinerary &Intinerary = ItinList[J]; // Emit Itinerary in the form of // { firstStage, lastStage, firstCycle, lastCycle } // index OS << " { " << Intinerary.NumMicroOps << ", " << Intinerary.FirstStage << ", " << Intinerary.LastStage << ", " << Intinerary.FirstOperandCycle << ", " << Intinerary.LastOperandCycle << " }" - << ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; + << ", // " << J << " " << SchedModels.getSchedClass(J).Name << "\n"; } // End processor itinerary table OS << " { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }" @@ -662,7 +662,7 @@ void SubtargetEmitter::EmitItineraries( // Emit either the value defined in the TableGen Record, or the default // value defined in the C++ header. The Record is null if the processor does not // define a model. -void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R, +void SubtargetEmitter::emitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name, char Separator) { OS << " "; int V = R ? R->getValueAsInt(Name) : -1; @@ -673,14 +673,14 @@ void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R, OS << '\n'; } -void SubtargetEmitter::EmitProcessorResourceSubUnits( +void SubtargetEmitter::emitProcessorResourceSubUnits( const CodeGenProcModel &ProcModel, raw_ostream &OS) { OS << "\nstatic const unsigned " << ProcModel.ModelName << "ProcResourceSubUnits[] = {\n" << " 0, // Invalid\n"; - for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { - const Record *PRDef = ProcModel.ProcResourceDefs[i]; + for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) { + const Record *PRDef = ProcModel.ProcResourceDefs[I]; if (!PRDef->isSubClassOf("ProcResGroup")) continue; for (const Record *RUDef : PRDef->getValueAsListOfDefs("Resources")) { @@ -695,7 +695,7 @@ void SubtargetEmitter::EmitProcessorResourceSubUnits( OS << "};\n"; } -static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, +static void emitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) { int64_t ReorderBufferSize = 0, MaxRetirePerCycle = 0; if (const Record *RCU = ProcModel.RetireControlUnit) { @@ -709,7 +709,7 @@ static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, OS << MaxRetirePerCycle << ", // MaxRetirePerCycle\n "; } -static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, +static void emitRegisterFileInfo(const CodeGenProcModel &ProcModel, unsigned NumRegisterFiles, unsigned NumCostEntries, raw_ostream &OS) { if (NumRegisterFiles) @@ -726,7 +726,7 @@ static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, } unsigned -SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, +SubtargetEmitter::emitRegisterFileTables(const CodeGenProcModel &ProcModel, raw_ostream &OS) { if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) { return RF.hasDefaultCosts(); @@ -778,7 +778,7 @@ SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel, return CostTblIndex; } -void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, +void SubtargetEmitter::emitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) { unsigned QueueID = 0; if (ProcModel.LoadQueue) { @@ -798,33 +798,33 @@ void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, OS << " " << QueueID << ", // Resource Descriptor for the Store Queue\n"; } -void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, +void SubtargetEmitter::emitExtraProcessorInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) { // Generate a table of register file descriptors (one entry per each user // defined register file), and a table of register costs. - unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS); + unsigned NumCostEntries = emitRegisterFileTables(ProcModel, OS); // Now generate a table for the extra processor info. OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName << "ExtraInfo = {\n "; // Add information related to the retire control unit. - EmitRetireControlUnitInfo(ProcModel, OS); + emitRetireControlUnitInfo(ProcModel, OS); // Add information related to the register files (i.e. where to find register // file descriptors and register costs). - EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), + emitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(), NumCostEntries, OS); // Add information about load/store queues. - EmitLoadStoreQueueInfo(ProcModel, OS); + emitLoadStoreQueueInfo(ProcModel, OS); OS << "};\n"; } -void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, +void SubtargetEmitter::emitProcessorResources(const CodeGenProcModel &ProcModel, raw_ostream &OS) { - EmitProcessorResourceSubUnits(ProcModel, OS); + emitProcessorResourceSubUnits(ProcModel, OS); OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n"; OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName @@ -833,8 +833,8 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, << " {\"InvalidUnit\", 0, 0, 0, 0},\n"; unsigned SubUnitsOffset = 1; - for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) { - const Record *PRDef = ProcModel.ProcResourceDefs[i]; + for (unsigned I = 0, E = ProcModel.ProcResourceDefs.size(); I < E; ++I) { + const Record *PRDef = ProcModel.ProcResourceDefs[I]; const Record *SuperDef = nullptr; unsigned SuperIdx = 0; @@ -866,7 +866,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, } else { OS << "nullptr"; } - OS << "}, // #" << i + 1; + OS << "}, // #" << I + 1; if (SuperDef) OS << ", Super=" << SuperDef->getName(); OS << "\n"; @@ -877,7 +877,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, // Find the WriteRes Record that defines processor resources for this // SchedWrite. const Record * -SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite, +SubtargetEmitter::findWriteResources(const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { // Check if the SchedWrite is already subtarget-specific and directly @@ -938,7 +938,7 @@ SubtargetEmitter::FindWriteResources(const CodeGenSchedRW &SchedWrite, /// Find the ReadAdvance record for the given SchedRead on this processor or /// return NULL. const Record * -SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, +SubtargetEmitter::findReadAdvance(const CodeGenSchedRW &SchedRead, const CodeGenProcModel &ProcModel) { // Check for SchedReads that directly specify a ReadAdvance. if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) @@ -997,12 +997,12 @@ SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, // Expand an explicit list of processor resources into a full list of implied // resource groups and super resources that cover them. -void SubtargetEmitter::ExpandProcResources( +void SubtargetEmitter::expandProcResources( ConstRecVec &PRVec, std::vector &ReleaseAtCycles, std::vector &AcquireAtCycles, const CodeGenProcModel &PM) { assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition"); - for (unsigned i = 0, e = PRVec.size(); i != e; ++i) { - const Record *PRDef = PRVec[i]; + for (unsigned I = 0, E = PRVec.size(); I != E; ++I) { + const Record *PRDef = PRVec[I]; ConstRecVec SubResources; if (PRDef->isSubClassOf("ProcResGroup")) SubResources = PRDef->getValueAsListOfDefs("Resources"); @@ -1019,8 +1019,8 @@ void SubtargetEmitter::ExpandProcResources( const Record *SuperDef = SchedModels.findProcResUnits( SubDef->getValueAsDef("Super"), PM, SubDef->getLoc()); PRVec.push_back(SuperDef); - ReleaseAtCycles.push_back(ReleaseAtCycles[i]); - AcquireAtCycles.push_back(AcquireAtCycles[i]); + ReleaseAtCycles.push_back(ReleaseAtCycles[I]); + AcquireAtCycles.push_back(AcquireAtCycles[I]); SubDef = SuperDef; } } @@ -1036,8 +1036,8 @@ void SubtargetEmitter::ExpandProcResources( } if (SubI == SubE) { PRVec.push_back(PR); - ReleaseAtCycles.push_back(ReleaseAtCycles[i]); - AcquireAtCycles.push_back(AcquireAtCycles[i]); + ReleaseAtCycles.push_back(ReleaseAtCycles[I]); + AcquireAtCycles.push_back(AcquireAtCycles[I]); } } } @@ -1045,7 +1045,7 @@ void SubtargetEmitter::ExpandProcResources( // Generate the SchedClass table for this processor and update global // tables. Must be called for each processor in order. -void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, +void SubtargetEmitter::genSchedClassTables(const CodeGenProcModel &ProcModel, SchedClassTables &SchedTables) { std::vector &SCTab = SchedTables.ProcSchedClasses.emplace_back(); @@ -1147,7 +1147,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, for (unsigned WS : WriteSeq) { const Record *WriteRes = - FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel); + findWriteResources(SchedModels.getSchedWrite(WS), ProcModel); // Mark the parent class as invalid for unsupported write types. if (WriteRes->getValueAsBit("Unsupported")) { @@ -1209,7 +1209,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, assert(AcquireAtCycles.size() == ReleaseAtCycles.size()); - ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel); + expandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel); assert(AcquireAtCycles.size() == ReleaseAtCycles.size()); for (unsigned PRIdx = 0, PREnd = PRVec.size(); PRIdx != PREnd; @@ -1263,7 +1263,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, for (unsigned UseIdx = 0, EndIdx = Reads.size(); UseIdx != EndIdx; ++UseIdx) { const Record *ReadAdvance = - FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); + findReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); if (!ReadAdvance) continue; @@ -1323,12 +1323,12 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, SchedTables.WriteLatencies.begin(), SchedTables.WriteLatencies.end(), WriteLatencies.begin(), WriteLatencies.end()); if (WLPos != SchedTables.WriteLatencies.end()) { - unsigned idx = WLPos - SchedTables.WriteLatencies.begin(); - SCDesc.WriteLatencyIdx = idx; - for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i) - if (SchedTables.WriterNames[idx + i].find(WriterNames[i]) == + unsigned Idx = WLPos - SchedTables.WriteLatencies.begin(); + SCDesc.WriteLatencyIdx = Idx; + for (unsigned I = 0, E = WriteLatencies.size(); I < E; ++I) + if (SchedTables.WriterNames[Idx + I].find(WriterNames[I]) == std::string::npos) { - SchedTables.WriterNames[idx + i] += std::string("_") + WriterNames[i]; + SchedTables.WriterNames[Idx + I] += std::string("_") + WriterNames[I]; } } else { SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size(); @@ -1351,7 +1351,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel, } // Emit SchedClass tables for all processors and associated global tables. -void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables, +void SubtargetEmitter::emitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS) { // Emit global WriteProcResTable. OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n" @@ -1446,15 +1446,15 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables, } } -void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { +void SubtargetEmitter::emitProcessorModels(raw_ostream &OS) { // For each processor model. for (const CodeGenProcModel &PM : SchedModels.procModels()) { // Emit extra processor info if available. if (PM.hasExtraProcessorInfo()) - EmitExtraProcessorInfo(PM, OS); + emitExtraProcessorInfo(PM, OS); // Emit processor resource table. if (PM.hasInstrSchedModel()) - EmitProcessorResources(PM, OS); + emitProcessorResources(PM, OS); else if (!PM.ProcResourceDefs.empty()) PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines " @@ -1463,12 +1463,12 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { // Begin processor itinerary properties OS << "\n"; OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n"; - EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); - EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); - EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); - EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); - EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); - EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); + emitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); + emitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); + emitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); + emitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); + emitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); + emitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); bool PostRAScheduler = (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); @@ -1516,7 +1516,7 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { // // EmitSchedModel - Emits all scheduling model tables, folding common patterns. // -void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { +void SubtargetEmitter::emitSchedModel(raw_ostream &OS) { OS << "#ifdef DBGFIELD\n" << "#error \"GenSubtargetInfo.inc requires a DBGFIELD macro\"\n" << "#endif\n" @@ -1529,22 +1529,22 @@ void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { if (SchedModels.hasItineraries()) { std::vector> ProcItinLists; // Emit the stage data - EmitStageAndOperandCycleData(OS, ProcItinLists); - EmitItineraries(OS, ProcItinLists); + emitStageAndOperandCycleData(OS, ProcItinLists); + emitItineraries(OS, ProcItinLists); } OS << "\n// ===============================================================\n" << "// Data tables for the new per-operand machine model.\n"; SchedClassTables SchedTables; for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) { - GenSchedClassTables(ProcModel, SchedTables); + genSchedClassTables(ProcModel, SchedTables); } - EmitSchedClassTables(SchedTables, OS); + emitSchedClassTables(SchedTables, OS); OS << "\n#undef DBGFIELD\n"; // Emit the processor machine model - EmitProcessorModels(OS); + emitProcessorModels(OS); } static void emitPredicateProlog(const RecordKeeper &Records, raw_ostream &OS) { @@ -1756,7 +1756,7 @@ void SubtargetEmitter::emitSchedModelHelpersImpl( emitSchedModelHelperEpilogue(OS, OnlyExpandMCInstPredicates); } -void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName, +void SubtargetEmitter::emitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS) { OS << "unsigned " << ClassName << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI," @@ -1786,7 +1786,7 @@ void SubtargetEmitter::EmitSchedModelHelpers(const std::string &ClassName, PE.expandSTIPredicate(OS, Fn); } -void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName, +void SubtargetEmitter::emitHwModeCheck(const std::string &ClassName, raw_ostream &OS) { const CodeGenHwModes &CGH = TGT.getHwModes(); assert(CGH.getNumModeIds() > 0); @@ -1825,7 +1825,7 @@ void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName, OS << " return Modes;\n}\n"; // End emitting for getHwModeSet(). - auto handlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) { + auto HandlePerMode = [&](std::string ModeType, unsigned ModeInBitSet) { OS << " case HwMode_" << ModeType << ":\n" << " Modes &= " << ModeInBitSet << ";\n" << " if (!Modes)\n return Modes;\n" @@ -1842,9 +1842,9 @@ void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName, OS << " if (!Modes)\n return Modes;\n\n"; OS << " switch (type) {\n"; OS << " case HwMode_Default:\n return llvm::countr_zero(Modes) + 1;\n"; - handlePerMode("ValueType", ValueTypeModes); - handlePerMode("RegInfo", RegInfoModes); - handlePerMode("EncodingInfo", EncodingInfoModes); + HandlePerMode("ValueType", ValueTypeModes); + HandlePerMode("RegInfo", RegInfoModes); + HandlePerMode("EncodingInfo", EncodingInfoModes); OS << " }\n"; OS << " llvm_unreachable(\"unexpected HwModeType\");\n" << " return 0; // should not get here\n}\n"; @@ -1871,7 +1871,7 @@ void SubtargetEmitter::emitGetMacroFusions(const std::string &ClassName, // Produces a subtarget specific function for parsing // the subtarget features string. -void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { +void SubtargetEmitter::parseFeaturesFunction(raw_ostream &OS) { ArrayRef Features = Records.getAllDerivedDefinitions("SubtargetFeature"); @@ -1951,10 +1951,10 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { << " return MCSubtargetInfo::isCPUStringValid(CPU);\n" << " }\n"; OS << "};\n"; - EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS); + emitHwModeCheck(Target + "GenMCSubtargetInfo", OS); } -void SubtargetEmitter::EmitMCInstrAnalysisPredicateFunctions(raw_ostream &OS) { +void SubtargetEmitter::emitMcInstrAnalysisPredicateFunctions(raw_ostream &OS) { OS << "\n#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n"; OS << "#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS\n\n"; @@ -1988,18 +1988,18 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "#undef GET_SUBTARGETINFO_ENUM\n\n"; OS << "namespace llvm {\n"; - auto FeatureMap = Enumeration(OS); + auto FeatureMap = enumeration(OS); OS << "} // end namespace llvm\n\n"; OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; - EmitSubtargetInfoMacroCalls(OS); + emitSubtargetInfoMacroCalls(OS); OS << "namespace llvm {\n"; - unsigned NumFeatures = FeatureKeyValues(OS, FeatureMap); + unsigned NumFeatures = featureKeyValues(OS, FeatureMap); OS << "\n"; - EmitSchedModel(OS); + emitSchedModel(OS); OS << "\n"; - unsigned NumProcs = CPUKeyValues(OS, FeatureMap); + unsigned NumProcs = cpuKeyValues(OS, FeatureMap); OS << "\n"; // MCInstrInfo initialization routine. @@ -2045,7 +2045,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "#include \"llvm/Support/raw_ostream.h\"\n\n"; if (Target == "AArch64") OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n"; - ParseFeaturesFunction(OS); + parseFeaturesFunction(OS); OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n"; @@ -2140,15 +2140,15 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "nullptr, nullptr, nullptr"; OS << ") {}\n\n"; - EmitSchedModelHelpers(ClassName, OS); - EmitHwModeCheck(ClassName, OS); + emitSchedModelHelpers(ClassName, OS); + emitHwModeCheck(ClassName, OS); emitGetMacroFusions(ClassName, OS); OS << "} // end namespace llvm\n\n"; OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; - EmitMCInstrAnalysisPredicateFunctions(OS); + emitMcInstrAnalysisPredicateFunctions(OS); } static TableGen::Emitter::OptClass diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp index fff4c6b7c27ada154995b1c5da239093eed5aa20..bea2a2e735dbe27a7ccee98087f7bfdb562ed092 100644 --- a/llvm/utils/TableGen/TableGen.cpp +++ b/llvm/utils/TableGen/TableGen.cpp @@ -39,17 +39,17 @@ static cl::opt Class("class", cl::value_desc("class name"), cl::cat(PrintEnumsCat)); -static void PrintRecords(const RecordKeeper &Records, raw_ostream &OS) { +static void printRecords(const RecordKeeper &Records, raw_ostream &OS) { OS << Records; // No argument, dump all contents } -static void PrintEnums(const RecordKeeper &Records, raw_ostream &OS) { +static void printEnums(const RecordKeeper &Records, raw_ostream &OS) { for (const Record *Rec : Records.getAllDerivedDefinitions(Class)) OS << Rec->getName() << ", "; OS << "\n"; } -static void PrintSets(const RecordKeeper &Records, raw_ostream &OS) { +static void printSets(const RecordKeeper &Records, raw_ostream &OS) { SetTheory Sets; Sets.addFieldExpander("Set", "Elements"); for (const Record *Rec : Records.getAllDerivedDefinitions("Set")) { @@ -63,15 +63,15 @@ static void PrintSets(const RecordKeeper &Records, raw_ostream &OS) { } static TableGen::Emitter::Opt X[] = { - {"print-records", PrintRecords, "Print all records to stdout (default)", + {"print-records", printRecords, "Print all records to stdout (default)", true}, {"print-detailed-records", EmitDetailedRecords, "Print full details of all records to stdout"}, {"null-backend", [](const RecordKeeper &Records, raw_ostream &OS) {}, "Do nothing after parsing (useful for timing)"}, {"dump-json", EmitJSON, "Dump all records as machine-readable JSON"}, - {"print-enums", PrintEnums, "Print enum values for a class"}, - {"print-sets", PrintSets, "Print expanded sets for testing DAG exprs"}, + {"print-enums", printEnums, "Print enum values for a class"}, + {"print-sets", printSets, "Print expanded sets for testing DAG exprs"}, }; int main(int argc, char **argv) { diff --git a/llvm/utils/TableGen/VTEmitter.cpp b/llvm/utils/TableGen/VTEmitter.cpp index 4cbc7abd699d20404451f911ee5b0a1cd353d369..d02932dd5e7fca531a1a3b7962e52af7e8feb5e0 100644 --- a/llvm/utils/TableGen/VTEmitter.cpp +++ b/llvm/utils/TableGen/VTEmitter.cpp @@ -28,7 +28,7 @@ public: } // End anonymous namespace. -static void VTtoGetLLVMTyString(raw_ostream &OS, const Record *VT) { +static void vTtoGetLlvmTyString(raw_ostream &OS, const Record *VT) { bool IsVector = VT->getValueAsBit("isVector"); bool IsRISCVVecTuple = VT->getValueAsBit("isRISCVVecTuple"); @@ -207,7 +207,7 @@ void VTEmitter::run(raw_ostream &OS) { continue; OS << " GET_VT_EVT(" << VT->getValueAsString("LLVMName") << ", "; - VTtoGetLLVMTyString(OS, VT); + vTtoGetLlvmTyString(OS, VT); OS << ")\n"; } OS << "#endif\n\n"; diff --git a/llvm/utils/UpdateTestChecks/common.py b/llvm/utils/UpdateTestChecks/common.py index 0fbb73431d2cfb8a52eb24bd71dbe1a222efdd4b..b108a21dbc52b840db345560c4d18df450ceff70 100644 --- a/llvm/utils/UpdateTestChecks/common.py +++ b/llvm/utils/UpdateTestChecks/common.py @@ -275,8 +275,10 @@ class TestInfo(object): self.run_lines = find_run_lines(test, self.input_lines) self.comment_prefix = comment_prefix if self.comment_prefix is None: - if self.path.endswith(".mir"): + if self.path.endswith(".mir") or self.path.endswith(".txt"): self.comment_prefix = "#" + elif self.path.endswith(".s"): + self.comment_prefix = "//" else: self.comment_prefix = ";" self.autogenerated_note_prefix = self.comment_prefix + " " + UTC_ADVERT @@ -2468,6 +2470,7 @@ def get_autogennote_suffix(parser, args): "verbose", "force_update", "reset_variable_names", + "llvm_mc_binary", ): continue value = getattr(args, action.dest) diff --git a/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn b/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn index e9d9a3be27a6d969cc74ef8e67796ce5950ad23a..c945c8ac42e4a2d55dca017485ac6ed03f3b2825 100644 --- a/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn @@ -95,6 +95,10 @@ clang_tablegen("BuiltinsRISCV") { args = [ "-gen-clang-builtins" ] } +clang_tablegen("BuiltinsX86") { + args = [ "-gen-clang-builtins" ] +} + # ARM CDE, MVE, and NEON. clang_tablegen("arm_neon") { diff --git a/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn index 1b193af6c30af7b7d9046431a7a0e38cffeae0cb..31b4ba6304a231b3eb047432d20fb1503d853894 100644 --- a/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn @@ -26,6 +26,7 @@ static_library("Basic") { "//clang/include/clang/Basic:Builtins", "//clang/include/clang/Basic:BuiltinsBPF", "//clang/include/clang/Basic:BuiltinsRISCV", + "//clang/include/clang/Basic:BuiltinsX86", "//clang/include/clang/Basic:DiagnosticGroups", "//clang/include/clang/Basic:RegularKeywordAttrInfo", "//clang/include/clang/Basic:arm_cde_builtins", diff --git a/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn index b47189accd1365108df7817812eed7cbc7205e81..d6e7d5490ce023fb165574b1b7fbc34f384d2619 100644 --- a/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn @@ -128,6 +128,7 @@ copy("Headers") { "ammintrin.h", "amxcomplexintrin.h", "amxfp16intrin.h", + "amxfp8intrin.h", "amxintrin.h", "arm64intr.h", "arm_acle.h", diff --git a/llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn b/llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn index 020f3e7d9acd7bb7e667c57f583094656e9d091b..5fbda794ff176efc12497b08208cffd2161e168d 100644 --- a/llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn +++ b/llvm/utils/gn/secondary/compiler-rt/test/BUILD.gn @@ -55,8 +55,6 @@ write_cmake_config("lit_common_configured") { "COMPILER_RT_ENABLE_INTERNAL_SYMBOLIZER_PYBOOL=False", "COMPILER_RT_HAS_NO_DEFAULT_CONFIG_FLAG_PYBOOL=True", "COMPILER_RT_INTERCEPT_LIBDISPATCH_PYBOOL=False", - "COMPILER_RT_RESOLVED_EXEC_OUTPUT_DIR=" + - rebase_path("$root_build_dir/bin"), "COMPILER_RT_RESOLVED_LIBRARY_OUTPUT_DIR=" + rebase_path(crt_current_out_dir), "COMPILER_RT_RESOLVED_OUTPUT_DIR=" + rebase_path(crt_current_out_dir), diff --git a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn index 8121e34dcf6eff7b765cd8f5f6fc551ab51a5b90..776f1d32c5f520fbc90168c838681a2a23195972 100644 --- a/llvm/utils/gn/secondary/libcxx/include/BUILD.gn +++ b/llvm/utils/gn/secondary/libcxx/include/BUILD.gn @@ -995,6 +995,7 @@ if (current_toolchain == default_toolchain) { "coroutine", "csetjmp", "csignal", + "cstdalign", "cstdarg", "cstdbool", "cstddef", diff --git a/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn index 10489baad1737645c98cdc62753ef356c4dfd5bb..89d0d25120858c9152ad18d71031ebc0a1ad7702 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn @@ -153,6 +153,7 @@ static_library("Support") { "TimeProfiler.cpp", "Timer.cpp", "ToolOutputFile.cpp", + "TrieRawHashMap.cpp", "Twine.cpp", "TypeSize.cpp", "Unicode.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn index c27faaaecf30d164d2e66482e9b996362efedb12..07ed3b4718af50ea5a582cd04e85612c5cce1793 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/ADT/BUILD.gn @@ -94,6 +94,7 @@ unittest("ADTTests") { "StringSetTest.cpp", "StringSwitchTest.cpp", "TinyPtrVectorTest.cpp", + "TrieRawHashMapTest.cpp", "TwineTest.cpp", "TypeSwitchTest.cpp", "TypeTraitsTest.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/JITLink/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/JITLink/BUILD.gn index 6f52677cb83338eacd37d710860913d89bc7597f..7f74b335e30ed9908ca7ec1782c513ea7b4bfcb3 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/JITLink/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/ExecutionEngine/JITLink/BUILD.gn @@ -17,8 +17,9 @@ unittest("JITLinkTests") { "AArch32ErrorTests.cpp", "AArch32Tests.cpp", "EHFrameSupportTests.cpp", - "JITLinkMocks.cpp", + "JITLinkTestUtils.cpp", "LinkGraphTests.cpp", + "MachOLinkGraphTests.cpp", "MemoryManagerErrorTests.cpp", "StubsTests.cpp", ] diff --git a/llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn index 75c693e446a39fc37ac0409875c26b032cde5cd7..502aa13e1de81de15721be27dc860b9a8deef036 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn @@ -17,6 +17,7 @@ unittest("AMDGPUTests") { include_dirs = [ "//llvm/lib/Target/AMDGPU" ] sources = [ "AMDGPUUnitTests.cpp", + "CSETest.cpp", "DwarfRegMappings.cpp", "ExecMayBeModifiedBeforeAnyUse.cpp", "PALMetadata.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn index 44640c6527c903b5f5a6986fe44525c0db464489..97df71c6279efde5c6c459600f35dcd2ff613cc7 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/Transforms/Vectorize/SandboxVectorizer/BUILD.gn @@ -14,5 +14,6 @@ unittest("SandboxVectorizerTests") { "IntervalTest.cpp", "LegalityTest.cpp", "SchedulerTest.cpp", + "VecUtilsTest.cpp", ] } diff --git a/llvm/utils/update_mc_test_checks.py b/llvm/utils/update_mc_test_checks.py index f9f8cfdea418d01dcf151c08c5ea64a597eeffba..c8a40b37088ae45183868dfdfc4d273aeee569fd 100755 --- a/llvm/utils/update_mc_test_checks.py +++ b/llvm/utils/update_mc_test_checks.py @@ -6,6 +6,7 @@ A test update script. This script is a utility to update LLVM 'llvm-mc' based t from __future__ import print_function import argparse +import functools import os # Used to advertise this file's name ("autogenerated_note"). from UpdateTestChecks import common @@ -15,7 +16,6 @@ import re mc_LIKE_TOOLS = [ "llvm-mc", - "not llvm-mc", ] ERROR_RE = re.compile(r":\d+: (warning|error): .*") ERROR_CHECK_RE = re.compile(r"# COM: .*") @@ -23,7 +23,7 @@ OUTPUT_SKIPPED_RE = re.compile(r"(.text)") COMMENT = {"asm": "//", "dasm": "#"} -def invoke_tool(exe, cmd_args, testline, verbose=False): +def invoke_tool(exe, check_rc, cmd_args, testline, verbose=False): if isinstance(cmd_args, list): args = [applySubstitutions(a, substitutions) for a in cmd_args] else: @@ -32,7 +32,15 @@ def invoke_tool(exe, cmd_args, testline, verbose=False): cmd = 'echo "' + testline + '" | ' + exe + " " + args if verbose: print("Command: ", cmd) - out = subprocess.check_output(cmd, shell=True) + + out = subprocess.run( + cmd, + shell=True, + check=check_rc, + stdout=subprocess.PIPE, + stderr=subprocess.DEVNULL, + ).stdout + # Fix line endings to unix CR style. return out.decode().replace("\r\n", "\n") @@ -50,6 +58,10 @@ def isTestLine(input_line, mc_mode): return True +def isRunLine(l): + return common.RUN_LINE_RE.match(l) + + def hasErr(err): return err and ERROR_RE.search(err) is not None @@ -97,8 +109,16 @@ def getStdCheckLine(prefix, output, mc_mode): return o -def getErrCheckLine(prefix, output, mc_mode): - return COMMENT[mc_mode] + " " + prefix + ": " + ":[[@LINE-1]]" + output + "\n" +def getErrCheckLine(prefix, output, mc_mode, line_offset=1): + return ( + COMMENT[mc_mode] + + " " + + prefix + + ": " + + ":[[@LINE-{}]]".format(line_offset) + + output + + "\n" + ) def main(): @@ -118,6 +138,19 @@ def main(): default=None, help="Set a default -march for when neither triple nor arch are found in a RUN line", ) + parser.add_argument( + "--unique", + action="store_true", + default=False, + help="remove duplicated test line if found", + ) + parser.add_argument( + "--sort", + action="store_true", + default=False, + help="sort testline in alphabetic order (keep run-lines on top), this option could be dangerous as it" + "could change the order of lines that are not expected", + ) parser.add_argument("tests", nargs="+") initial_args = common.parse_commandline_args(parser) @@ -130,6 +163,11 @@ def main(): mc_mode = "asm" elif ti.path.endswith(".txt"): mc_mode = "dasm" + + if ti.args.sort: + print("sorting with dasm(.txt) file is not supported!") + return -1 + else: common.warn("Expected .s and .txt, Skipping file : ", ti.path) continue @@ -151,11 +189,19 @@ def main(): assert len(commands) >= 2 mc_cmd = " | ".join(commands[:-1]) filecheck_cmd = commands[-1] - mc_tool = mc_cmd.split(" ")[0] # special handling for negating exit status - if mc_tool == "not": - mc_tool = mc_tool + " " + mc_cmd.split(" ")[1] + # if not is used in runline, disable rc check, since + # the command might or might not + # return non-zero code on a single line run + check_rc = True + mc_cmd_args = mc_cmd.strip().split() + if mc_cmd_args[0] == "not": + check_rc = False + mc_tool = mc_cmd_args[1] + mc_cmd = mc_cmd[len(mc_cmd_args[0]) :].strip() + else: + mc_tool = mc_cmd_args[0] triple_in_cmd = None m = common.TRIPLE_ARG_RE.search(mc_cmd) @@ -188,6 +234,7 @@ def main(): ( check_prefixes, mc_tool, + check_rc, mc_cmd_args, triple_in_cmd, march_in_cmd, @@ -196,6 +243,10 @@ def main(): # find all test line from input testlines = [l for l in ti.input_lines if isTestLine(l, mc_mode)] + # remove duplicated lines to save running time + testlines = list(dict.fromkeys(testlines)) + common.debug("Valid test line found: ", len(testlines)) + run_list_size = len(run_list) testnum = len(testlines) @@ -204,6 +255,7 @@ def main(): for ( prefixes, mc_tool, + check_rc, mc_args, triple_in_cmd, march_in_cmd, @@ -222,6 +274,7 @@ def main(): # get output for each testline out = invoke_tool( ti.args.llvm_mc_binary or mc_tool, + check_rc, mc_args, line, verbose=ti.args.verbose, @@ -233,7 +286,7 @@ def main(): raw_prefixes.append(prefixes) output_lines = [] - generated_prefixes = [] + generated_prefixes = {} used_prefixes = set() prefix_set = set([prefix for p in run_list for prefix in p[0]]) common.debug("Rewriting FileCheck prefixes:", str(prefix_set)) @@ -278,6 +331,9 @@ def main(): # each run_id can only be used once gen_prefix = "" used_runid = set() + + # line number diff between generated prefix and testline + line_offset = 1 for prefix, tup in p_dict_sorted.items(): o, run_ids = tup @@ -294,27 +350,80 @@ def main(): used_prefixes.add(prefix) if hasErr(o): - gen_prefix += getErrCheckLine(prefix, o, mc_mode) + newline = getErrCheckLine(prefix, o, mc_mode, line_offset) else: - gen_prefix += getStdCheckLine(prefix, o, mc_mode) + newline = getStdCheckLine(prefix, o, mc_mode) + + if newline: + gen_prefix += newline + line_offset += 1 - generated_prefixes.append(gen_prefix.rstrip("\n")) + generated_prefixes[input_line] = gen_prefix.rstrip("\n") # write output - prefix_id = 0 for input_info in ti.iterlines(output_lines): input_line = input_info.line - if isTestLine(input_line, mc_mode): + if input_line in testlines: output_lines.append(input_line) - output_lines.append(generated_prefixes[prefix_id]) - prefix_id += 1 + output_lines.append(generated_prefixes[input_line]) elif should_add_line_to_output(input_line, prefix_set, mc_mode): output_lines.append(input_line) - elif input_line in ti.run_lines or input_line == "": - output_lines.append(input_line) + if ti.args.unique or ti.args.sort: + # split with double newlines + test_units = "\n".join(output_lines).split("\n\n") + + # select the key line for each test unit + test_dic = {} + for unit in test_units: + lines = unit.split("\n") + for l in lines: + # if contains multiple lines, use + # the first testline or runline as key + if isTestLine(l, mc_mode): + test_dic[unit] = l + break + if isRunLine(l): + test_dic[unit] = l + break + + # unique + if ti.args.unique: + new_test_units = [] + written_lines = set() + for unit in test_units: + # if not testline/runline, we just add it + if unit not in test_dic: + new_test_units.append(unit) + else: + if test_dic[unit] in written_lines: + common.debug("Duplicated test skipped: ", unit) + continue + + written_lines.add(test_dic[unit]) + new_test_units.append(unit) + test_units = new_test_units + + # sort + if ti.args.sort: + + def getkey(l): + # find key of test unit, otherwise use first line + if l in test_dic: + line = test_dic[l] + else: + line = l.split("\n")[0] + + # runline placed on the top + return (not isRunLine(line), line) + + test_units = sorted(test_units, key=getkey) + + # join back to be output string + output_lines = "\n\n".join(test_units).split("\n") + # output if ti.args.gen_unused_prefix_body: output_lines.extend( ti.get_checks_for_unused_prefixes(run_list, used_prefixes) diff --git a/mlir/docs/Rationale/SideEffectsAndSpeculation.md b/mlir/docs/Rationale/SideEffectsAndSpeculation.md index 8b08b757531bef25d9d02b9af92aa2f03d025e07..4d9021a356dfead30435c6472984fda4013e57c9 100644 --- a/mlir/docs/Rationale/SideEffectsAndSpeculation.md +++ b/mlir/docs/Rationale/SideEffectsAndSpeculation.md @@ -79,9 +79,9 @@ When adding a new op, ask: 1. Does it read from or write to the heap or stack? It should probably implement `MemoryEffectsOpInterface`. -1. Does these side effects ordered? It should probably set the stage of - side effects to make analysis more accurate. -1. Does These side effects act on every single value of resource? It probably +1. Are these side effects ordered? The op should probably set the stage of + side effects to make analyses more accurate. +1. Do these side effects act on every single value of a resource? It probably should set the FullEffect on effect. 1. Does it have side effects that must be preserved, like a volatile store or a syscall? It should probably implement `MemoryEffectsOpInterface` and model @@ -106,9 +106,9 @@ add side effect correctly. ### SIMD compute operation -If we have a SIMD backend dialect with a "simd.abs" operation, which reads all +Consider a SIMD backend dialect with a "simd.abs" operation which reads all values from the source memref, calculates their absolute values, and writes them -to the target memref. +to the target memref: ```mlir func.func @abs(%source : memref<10xf32>, %target : memref<10xf32>) { @@ -139,10 +139,10 @@ A typical approach is as follows: } ``` -In the above example, we attach the side effect [MemReadAt<0, FullEffect>] to +In the above example, we attach the side effect `[MemReadAt<0, FullEffect>]` to the source, indicating that the abs operation reads each individual value from the source during stage 0. Likewise, we attach the side effect -[MemWriteAt<1, FullEffect>] to the target, indicating that the abs operation +`[MemWriteAt<1, FullEffect>]` to the target, indicating that the abs operation writes to each individual value within the target during stage 1 (after reading from the source). @@ -174,7 +174,7 @@ A typical approach is as follows: } ``` -In the above example, we attach the side effect [MemReadAt<0, PartialEffect>] to +In the above example, we attach the side effect `[MemReadAt<0, PartialEffect>]` to the source, indicating that the load operation reads parts of values from the memref during stage 0. Since side effects typically occur at stage 0 and are -partial by default, we can abbreviate it as "[MemRead]". +partial by default, we can abbreviate it as `[MemRead]`. diff --git a/mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h b/mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h index aceb9d059b95f3a9cb4d67fe82c0c24c0f8bcee9..4866e31b19d5de0082ba389c0b7099a197308bed 100644 --- a/mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h +++ b/mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h @@ -60,7 +60,8 @@ struct AliasingValue { bool isDefinite; }; -template class AliasList { +template +class AliasList { public: /// Create an empty list of aliases. AliasList() = default; @@ -259,7 +260,7 @@ struct BufferizationOptions { /// Initializer function for analysis state. using AnalysisStateInitFn = std::function; /// Tensor -> MemRef type converter. - /// Parameters: Value, memory space, func op, bufferization options + /// Parameters: tensor type, memory space, func op, bufferization options using FunctionArgTypeConverterFn = std::function; @@ -344,9 +345,9 @@ struct BufferizationOptions { void setFunctionBoundaryTypeConversion(LayoutMapOption layoutMapOption); /// Type converter from tensors to memrefs. This type converter is used to - /// determine bufferized function argument types. By default, a type - /// converter that returns a memref type with a fully dynamic layout map is - /// used. + /// determine bufferized function argument and result types. By default, a + /// type converter that returns a memref type with a fully dynamic layout map + /// is used. /// /// If `bufferizeFunctionBoundaries` is not set, this function isn't used. FunctionArgTypeConverterFn functionArgTypeConverterFn = nullptr; diff --git a/mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td b/mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td index 1c70a4b8df92546506ef6c6e5382cfa15db3866b..7bcc3b9e79986519017cd39cc3bbf9ce7aaf4bcd 100644 --- a/mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td +++ b/mlir/include/mlir/Dialect/Bufferization/IR/BufferizationOps.td @@ -1,4 +1,4 @@ -//===- BufferizationOps.td - Bufferization op definitions ----------*- tablegen -*-===// +//===- BufferizationOps.td - Bufferization op definitions --*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -602,7 +602,7 @@ def Bufferization_DeallocOp : Bufferization_Op<"dealloc", [ ``` Deallocation will be called on `%a0` if `%cond0` is 'true' and neither `%r0`, `%r1`, or `%r2` are aliases of `%a0`. `%a1` will be deallocated when - `%cond1` is set to 'true' and none of `%r0`, %r1`, `%r2`, and `%a0` are + `%cond1` is set to 'true' and none of `%r0`, `%r1`, `%r2`, and `%a0` are aliases. Note that this can be an expensive operation if there are many operands that diff --git a/mlir/include/mlir/Dialect/Func/Transforms/DecomposeCallGraphTypes.h b/mlir/include/mlir/Dialect/Func/Transforms/DecomposeCallGraphTypes.h index 1d311b37b37a4f9f597e62925403a72b11cfc41d..1be406bf3adf9204d6229c0f07fe3cf90f801503 100644 --- a/mlir/include/mlir/Dialect/Func/Transforms/DecomposeCallGraphTypes.h +++ b/mlir/include/mlir/Dialect/Func/Transforms/DecomposeCallGraphTypes.h @@ -23,70 +23,10 @@ namespace mlir { -/// This class provides a hook that expands one Value into multiple Value's, -/// with a TypeConverter-inspired callback registration mechanism. -/// -/// For folks that are familiar with the dialect conversion framework / -/// TypeConverter, this is effectively the inverse of a source/argument -/// materialization. A target materialization is not what we want here because -/// it always produces a single Value, but in this case the whole point is to -/// decompose a Value into multiple Value's. -/// -/// The reason we need this inverse is easily understood by looking at what we -/// need to do for decomposing types for a return op. When converting a return -/// op, the dialect conversion framework will give the list of converted -/// operands, and will ensure that each converted operand, even if it expanded -/// into multiple types, is materialized as a single result. We then need to -/// undo that materialization to a single result, which we do with the -/// decomposeValue hooks registered on this object. -/// -/// TODO: Eventually, the type conversion infra should have this hook built-in. -/// See -/// https://llvm.discourse.group/t/extending-type-conversion-infrastructure/779/2 -class ValueDecomposer { -public: - /// This method tries to decompose a value of a certain type using provided - /// decompose callback functions. If it is unable to do so, the original value - /// is returned. - void decomposeValue(OpBuilder &, Location, Type, Value, - SmallVectorImpl &); - - /// This method registers a callback function that will be called to decompose - /// a value of a certain type into 0, 1, or multiple values. - template >::template arg_t<2>> - void addDecomposeValueConversion(FnT &&callback) { - decomposeValueConversions.emplace_back( - wrapDecomposeValueConversionCallback(std::forward(callback))); - } - -private: - using DecomposeValueConversionCallFn = - std::function( - OpBuilder &, Location, Type, Value, SmallVectorImpl &)>; - - /// Generate a wrapper for the given decompose value conversion callback. - template - DecomposeValueConversionCallFn - wrapDecomposeValueConversionCallback(FnT &&callback) { - return - [callback = std::forward(callback)]( - OpBuilder &builder, Location loc, Type type, Value value, - SmallVectorImpl &newValues) -> std::optional { - if (T derivedType = dyn_cast(type)) - return callback(builder, loc, derivedType, value, newValues); - return std::nullopt; - }; - } - - SmallVector decomposeValueConversions; -}; - /// Populates the patterns needed to drive the conversion process for -/// decomposing call graph types with the given `ValueDecomposer`. +/// decomposing call graph types with the given `TypeConverter`. void populateDecomposeCallGraphTypesPatterns(MLIRContext *context, const TypeConverter &typeConverter, - ValueDecomposer &decomposer, RewritePatternSet &patterns); } // namespace mlir diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td index bfc609bd708164a97a5e211077d397f491d58c81..c2fee8ea55c960aef49a139bb1de0f0d2c646228 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td @@ -30,6 +30,7 @@ class LinalgStructuredBase_Op props> SingleBlockImplicitTerminator<"YieldOp">, DeclareOpInterfaceMethods, DeclareOpInterfaceMethods, + RecursiveMemoryEffects, DestinationStyleOpInterface, LinalgStructuredInterface, ReifyRankedShapedTypeOpInterface], props)> { diff --git a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h index 70b086641bdc18d81c4aa4576da31205cab6546d..b5710bd78f0089898cb80824c22acc405366d71d 100644 --- a/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h +++ b/mlir/include/mlir/Dialect/Linalg/Transforms/Transforms.h @@ -1503,18 +1503,13 @@ using OptimizeCopyFn = /// Rewrite a tensor::PadOp into a sequence of EmptyOp, FillOp and /// InsertSliceOp. For now, only constant padding values are supported. -/// `OptimizeCopyFn` can be used to customize copying step optimization. struct GeneralizePadOpPattern : public OpRewritePattern { - GeneralizePadOpPattern(MLIRContext *context, - OptimizeCopyFn optimizeCopyFn = nullptr, - PatternBenefit benefit = 1) - : OpRewritePattern(context, benefit), - optimizeCopyFn(std::move(optimizeCopyFn)) {} + GeneralizePadOpPattern(MLIRContext *context, PatternBenefit benefit = 1) + : OpRewritePattern(context, benefit) {} LogicalResult matchAndRewrite(tensor::PadOp padOp, PatternRewriter &rewriter) const override; protected: - OptimizeCopyFn optimizeCopyFn; Value createFillOrGenerateOp(RewriterBase &rewriter, tensor::PadOp padOp, Value dest, const SmallVector &dynSizes) const; @@ -1663,6 +1658,11 @@ void populateDecomposeConvolutionPatterns(RewritePatternSet &patterns, /// \see rewriteInIm2Col for more details. void populateConvertConv2DToImg2ColPatterns(RewritePatternSet &patterns); +/// Populates `patterns` with vectorisation patterns for tensor.insert_slice. +/// TODO: Avoid having a dedicated `populate{}` for one pattern. Instead, either +/// expand or merge with other `populate{}`. +void populateInsertSliceVectorizationPatterns(RewritePatternSet &patterns); + /// Populates `patterns` with patterns that vectorize tensor.pad. /// These patterns are meant to apply in a complementary fashion. Benefits /// are used to encode a certain ordering of pattern application. To avoid diff --git a/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h b/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h index ca3326dbbef5191453b6e918c466cb9945de317d..a761a77a407e879e58dc004be105db4bf2d8a5e4 100644 --- a/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h +++ b/mlir/include/mlir/Dialect/MemRef/Utils/MemRefUtils.h @@ -32,7 +32,8 @@ namespace memref { bool isStaticShapeAndContiguousRowMajor(MemRefType type); /// For a `memref` with `offset`, `sizes` and `strides`, returns the -/// offset and size to use for the linearized `memref`. +/// offset, size, and potentially the size padded at the front to use for the +/// linearized `memref`. /// - If the linearization is done for emulating load/stores of /// element type with bitwidth `srcBits` using element type with /// bitwidth `dstBits`, the linearized offset and size are @@ -42,9 +43,14 @@ bool isStaticShapeAndContiguousRowMajor(MemRefType type); /// index to use in the linearized `memref`. The linearized index /// is also scaled down by `dstBits`/`srcBits`. If `indices` is not provided /// 0, is returned for the linearized index. +/// - If the size of the load/store is smaller than the linearized memref +/// load/store, the memory region emulated is larger than the actual memory +/// region needed. `intraDataOffset` returns the element offset of the data +/// relevant at the beginning. struct LinearizedMemRefInfo { OpFoldResult linearizedOffset; OpFoldResult linearizedSize; + OpFoldResult intraDataOffset; }; std::pair getLinearizedMemRefOffsetAndSize( OpBuilder &builder, Location loc, int srcBits, int dstBits, diff --git a/mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td b/mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td index 20880d94a83cacbab92eadd870d75f0584bad2fd..5dba8c5e57ba861f5e09ad9be145b2931b623629 100644 --- a/mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td +++ b/mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td @@ -146,7 +146,7 @@ def LoopPeelOp : Op Value { + if (inputs.size() != 1) + return Value(); + + return builder.create(loc, resultType, inputs) + .getResult(0); + }; + + converter.addSourceMaterialization(materializeAsUnrealizedCast); + converter.addTargetMaterialization(materializeAsUnrealizedCast); + RewritePatternSet patterns(&getContext()); populateMemRefToEmitCConversionPatterns(patterns, converter); diff --git a/mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp b/mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp index c8cfcc3d945bec1865563a1bffa26248ddee91fd..46c7bfbf3ffcc2e490a96579c04073ea76dba327 100644 --- a/mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp +++ b/mlir/lib/Dialect/AMX/Transforms/LegalizeForLLVMExport.cpp @@ -37,40 +37,38 @@ std::pair getTileSizes(ConversionPatternRewriter &rewriter, rewriter.create(loc, llvmInt16Type, nattr)); } -/// Verifies if the stride matches proper tile access. -LogicalResult verifyStride(MemRefType mType) { - if (mType.getRank() < 2) - return failure(); - int64_t last = mType.getRank() - 1; - int64_t offset; - SmallVector strides; - if (failed(getStridesAndOffset(mType, strides, offset)) || strides[last] != 1) - return failure(); - return success(); -} - /// Maps the 2-dim memref shape to the 64-bit stride. Note that the buffer /// shape may "envelop" the actual tile shape, and may be dynamically sized. -Value getStride(ConversionPatternRewriter &rewriter, - const LLVMTypeConverter &typeConverter, MemRefType mType, - Value base, Location loc) { - assert(mType.getRank() >= 2); - int64_t last = mType.getRank() - 1; +/// Returns failure if proper stride couldn't be found. +FailureOr getStride(ConversionPatternRewriter &rewriter, + const LLVMTypeConverter &typeConverter, + MemRefType mType, Value base, Location loc) { + if (mType.getRank() < 2) + return failure(); + int64_t preLast = mType.getRank() - 2; Type llvmInt64Type = IntegerType::get(&typeConverter.getContext(), 64); unsigned width = mType.getElementType().getIntOrFloatBitWidth(); assert(llvm::isPowerOf2_64(width) && width >= 8); unsigned bytes = width >> 3; - if (mType.isDynamicDim(last)) { - // Dynamic size needs code to compute the stride at runtime. + int64_t offset; + SmallVector strides; + if (failed(getStridesAndOffset(mType, strides, offset)) || + strides.back() != 1) + return failure(); + if (strides[preLast] == ShapedType::kDynamic) { + // Dynamic stride needs code to compute the stride at runtime. MemRefDescriptor memrefDescriptor(base); auto attr = rewriter.getI64IntegerAttr(bytes); Value scale = rewriter.create(loc, llvmInt64Type, attr); - return rewriter.create( - loc, llvmInt64Type, scale, memrefDescriptor.size(rewriter, loc, last)); + return rewriter + .create(loc, llvmInt64Type, scale, + memrefDescriptor.stride(rewriter, loc, preLast)) + .getResult(); } - // Use direct constant for static size. - auto attr = rewriter.getI64IntegerAttr(mType.getDimSize(last) * bytes); - return rewriter.create(loc, llvmInt64Type, attr); + // Use direct constant for static stride. + auto attr = rewriter.getI64IntegerAttr(strides[preLast] * bytes); + return rewriter.create(loc, llvmInt64Type, attr) + .getResult(); } struct TileZeroConversion : public ConvertOpToLLVMPattern { @@ -102,16 +100,16 @@ struct TileLoadConversion : public ConvertOpToLLVMPattern { std::pair tsz = getTileSizes(rewriter, *getTypeConverter(), vType, op.getLoc()); // Determine stride. - if (failed(verifyStride(mType))) + auto stride = getStride(rewriter, *getTypeConverter(), mType, + adaptor.getBase(), op.getLoc()); + if (failed(stride)) return failure(); - Value stride = getStride(rewriter, *getTypeConverter(), mType, - adaptor.getBase(), op.getLoc()); // Replace operation with intrinsic. Value ptr = getStridedElementPtr(op.getLoc(), mType, adaptor.getBase(), adaptor.getIndices(), rewriter); Type resType = typeConverter->convertType(vType); rewriter.replaceOpWithNewOp( - op, resType, tsz.first, tsz.second, ptr, stride); + op, resType, tsz.first, tsz.second, ptr, stride.value()); return success(); } }; @@ -128,15 +126,15 @@ struct TileStoreConversion : public ConvertOpToLLVMPattern { std::pair tsz = getTileSizes(rewriter, *getTypeConverter(), vType, op.getLoc()); // Determine stride. - if (failed(verifyStride(mType))) + auto stride = getStride(rewriter, *getTypeConverter(), mType, + adaptor.getBase(), op.getLoc()); + if (failed(stride)) return failure(); - Value stride = getStride(rewriter, *getTypeConverter(), mType, - adaptor.getBase(), op.getLoc()); // Replace operation with intrinsic. Value ptr = getStridedElementPtr(op.getLoc(), mType, adaptor.getBase(), adaptor.getIndices(), rewriter); rewriter.replaceOpWithNewOp( - op, tsz.first, tsz.second, ptr, stride, adaptor.getVal()); + op, tsz.first, tsz.second, ptr, stride.value(), adaptor.getVal()); return success(); } }; diff --git a/mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp b/mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp index 9fbe574ec392dc8701e0f222233a7678d521168b..6e91d3b89a7c799bf3e80917ed755acd97bd8fa0 100644 --- a/mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp +++ b/mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp @@ -82,7 +82,8 @@ getBufferizedFunctionArgType(FuncOp funcOp, int64_t index, /// Return the FuncOp called by `callOp`. static FuncOp getCalledFunction(CallOpInterface callOp) { - SymbolRefAttr sym = llvm::dyn_cast_if_present(callOp.getCallableForCallee()); + SymbolRefAttr sym = + llvm::dyn_cast_if_present(callOp.getCallableForCallee()); if (!sym) return nullptr; return dyn_cast_or_null( @@ -392,11 +393,11 @@ struct FuncOpInterface auto funcOp = cast(op); FunctionType funcType = funcOp.getFunctionType(); - // Construct the bufferized function type. + // Compute the argument types. SmallVector argTypes; for (const auto &it : llvm::enumerate(funcType.getInputs())) { Type argType = it.value(); - if (dyn_cast(argType)) { + if (isa(argType)) { argTypes.push_back( getBufferizedFunctionArgType(funcOp, it.index(), options)); continue; @@ -404,24 +405,33 @@ struct FuncOpInterface argTypes.push_back(argType); } - // Bodiless functions are assumed opaque and we cannot know the - // bufferization contract they want to enforce. As a consequence, only - // support functions that don't return any tensors atm. - if (funcOp.isExternal()) { - SmallVector retTypes; - for (Type resultType : funcType.getResults()) { - if (isa(resultType)) - return funcOp->emitError() << "cannot bufferize bodiless function " - << "that returns a tensor"; + // Compute the result types. + SmallVector retTypes; + for (Type resultType : funcType.getResults()) { + if (auto tensorType = dyn_cast(resultType)) { + BaseMemRefType resultType = options.functionArgTypeConverterFn( + tensorType, *options.defaultMemorySpaceFn(tensorType), funcOp, + options); retTypes.push_back(resultType); + continue; } - funcOp.setType(FunctionType::get(op->getContext(), argTypes, retTypes)); + retTypes.push_back(resultType); + } + + // Compute the new function type. + auto newFuncType = FunctionType::get(op->getContext(), argTypes, retTypes); + + // If the function has no body, set the new function type and we are done. + if (funcOp.isExternal()) { + funcOp.setType(newFuncType); return success(); } // TODO: Support functions with multiple returns. func::ReturnOp returnOp = getAssumedUniqueReturnOp(funcOp); assert(returnOp && "expected func with single return op"); + assert(returnOp->getNumOperands() == retTypes.size() && + "incorrect number of return values"); Location loc = returnOp.getLoc(); // 1. Bufferize every block. @@ -430,10 +440,10 @@ struct FuncOpInterface options))) return failure(); - // 2. For each result, keep track of which inplace argument it reuses. + // 2. Bufferize all operands of the return op. SmallVector returnValues; - for (OpOperand &returnOperand : returnOp->getOpOperands()) { - Value returnVal = returnOperand.get(); + for (auto [returnVal, bufferizedType] : + llvm::zip_equal(returnOp->getOperands(), retTypes)) { auto tensorType = dyn_cast(returnVal.getType()); rewriter.setInsertionPoint(returnOp); @@ -443,23 +453,17 @@ struct FuncOpInterface continue; } - // Note: If `inferFunctionResultLayout = true`, cast are later folded + // Note: If `inferFunctionResultLayout = true`, casts are later folded // away. - BaseMemRefType resultType = options.functionArgTypeConverterFn( - tensorType, *options.defaultMemorySpaceFn(tensorType), funcOp, - options); Value toMemrefOp = rewriter.create( - loc, resultType, returnVal); + loc, bufferizedType, returnVal); returnValues.push_back(toMemrefOp); } - // 3. Rewrite the terminator without the in-place bufferizable values. returnOp.getOperandsMutable().assign(returnValues); - // 4. Rewrite the FuncOp type to buffer form. - funcOp.setType(FunctionType::get(op->getContext(), argTypes, - ValueRange(returnValues).getTypes())); - + // 3. Set the new function type. + funcOp.setType(newFuncType); return success(); } diff --git a/mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp b/mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp index 357f993710a26a976996ace206df0db63cafc494..de4aba2ed327db4324ce0c9db7b016a427c1a800 100644 --- a/mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp +++ b/mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp @@ -14,52 +14,48 @@ using namespace mlir; using namespace mlir::func; //===----------------------------------------------------------------------===// -// ValueDecomposer +// Helper functions //===----------------------------------------------------------------------===// -void ValueDecomposer::decomposeValue(OpBuilder &builder, Location loc, - Type type, Value value, - SmallVectorImpl &results) { - for (auto &conversion : decomposeValueConversions) - if (conversion(builder, loc, type, value, results)) - return; - results.push_back(value); +/// If the given value can be decomposed with the type converter, decompose it. +/// Otherwise, return the given value. +// TODO: Value decomposition should happen automatically through a 1:N adaptor. +// This function will disappear when the 1:1 and 1:N drivers are merged. +static SmallVector decomposeValue(OpBuilder &builder, Location loc, + Value value, + const TypeConverter *converter) { + // Try to convert the given value's type. If that fails, just return the + // given value. + SmallVector convertedTypes; + if (failed(converter->convertType(value.getType(), convertedTypes))) + return {value}; + if (convertedTypes.empty()) + return {}; + + // If the given value's type is already legal, just return the given value. + TypeRange convertedTypeRange(convertedTypes); + if (convertedTypeRange == TypeRange(value.getType())) + return {value}; + + // Try to materialize a target conversion. If the materialization did not + // produce values of the requested type, the materialization failed. Just + // return the given value in that case. + SmallVector result = converter->materializeTargetConversion( + builder, loc, convertedTypeRange, value); + if (result.empty()) + return {value}; + return result; } -//===----------------------------------------------------------------------===// -// DecomposeCallGraphTypesOpConversionPattern -//===----------------------------------------------------------------------===// - -namespace { -/// Base OpConversionPattern class to make a ValueDecomposer available to -/// inherited patterns. -template -class DecomposeCallGraphTypesOpConversionPattern - : public OpConversionPattern { -public: - DecomposeCallGraphTypesOpConversionPattern(const TypeConverter &typeConverter, - MLIRContext *context, - ValueDecomposer &decomposer, - PatternBenefit benefit = 1) - : OpConversionPattern(typeConverter, context, benefit), - decomposer(decomposer) {} - -protected: - ValueDecomposer &decomposer; -}; -} // namespace - //===----------------------------------------------------------------------===// // DecomposeCallGraphTypesForFuncArgs //===----------------------------------------------------------------------===// namespace { -/// Expand function arguments according to the provided TypeConverter and -/// ValueDecomposer. +/// Expand function arguments according to the provided TypeConverter. struct DecomposeCallGraphTypesForFuncArgs - : public DecomposeCallGraphTypesOpConversionPattern { - using DecomposeCallGraphTypesOpConversionPattern:: - DecomposeCallGraphTypesOpConversionPattern; + : public OpConversionPattern { + using OpConversionPattern::OpConversionPattern; LogicalResult matchAndRewrite(func::FuncOp op, OpAdaptor adaptor, @@ -100,19 +96,22 @@ struct DecomposeCallGraphTypesForFuncArgs //===----------------------------------------------------------------------===// namespace { -/// Expand return operands according to the provided TypeConverter and -/// ValueDecomposer. +/// Expand return operands according to the provided TypeConverter. struct DecomposeCallGraphTypesForReturnOp - : public DecomposeCallGraphTypesOpConversionPattern { - using DecomposeCallGraphTypesOpConversionPattern:: - DecomposeCallGraphTypesOpConversionPattern; + : public OpConversionPattern { + using OpConversionPattern::OpConversionPattern; + LogicalResult matchAndRewrite(ReturnOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final { SmallVector newOperands; - for (Value operand : adaptor.getOperands()) - decomposer.decomposeValue(rewriter, op.getLoc(), operand.getType(), - operand, newOperands); + for (Value operand : adaptor.getOperands()) { + // TODO: We can directly take the values from the adaptor once this is a + // 1:N conversion pattern. + llvm::append_range(newOperands, + decomposeValue(rewriter, operand.getLoc(), operand, + getTypeConverter())); + } rewriter.replaceOpWithNewOp(op, newOperands); return success(); } @@ -124,12 +123,9 @@ struct DecomposeCallGraphTypesForReturnOp //===----------------------------------------------------------------------===// namespace { -/// Expand call op operands and results according to the provided TypeConverter -/// and ValueDecomposer. -struct DecomposeCallGraphTypesForCallOp - : public DecomposeCallGraphTypesOpConversionPattern { - using DecomposeCallGraphTypesOpConversionPattern:: - DecomposeCallGraphTypesOpConversionPattern; +/// Expand call op operands and results according to the provided TypeConverter. +struct DecomposeCallGraphTypesForCallOp : public OpConversionPattern { + using OpConversionPattern::OpConversionPattern; LogicalResult matchAndRewrite(CallOp op, OpAdaptor adaptor, @@ -137,9 +133,13 @@ struct DecomposeCallGraphTypesForCallOp // Create the operands list of the new `CallOp`. SmallVector newOperands; - for (Value operand : adaptor.getOperands()) - decomposer.decomposeValue(rewriter, op.getLoc(), operand.getType(), - operand, newOperands); + for (Value operand : adaptor.getOperands()) { + // TODO: We can directly take the values from the adaptor once this is a + // 1:N conversion pattern. + llvm::append_range(newOperands, + decomposeValue(rewriter, operand.getLoc(), operand, + getTypeConverter())); + } // Create the new result types for the new `CallOp` and track the indices in // the new call op's results that correspond to the old call op's results. @@ -189,9 +189,8 @@ struct DecomposeCallGraphTypesForCallOp void mlir::populateDecomposeCallGraphTypesPatterns( MLIRContext *context, const TypeConverter &typeConverter, - ValueDecomposer &decomposer, RewritePatternSet &patterns) { + RewritePatternSet &patterns) { patterns .add(typeConverter, context, - decomposer); + DecomposeCallGraphTypesForReturnOp>(typeConverter, context); } diff --git a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp index 3d3f0a93a3829bf4ba101e99665eb5ba8e2d5d51..9c0ab4f41b855a29c050fa5ec3d5ee868c7cc28f 100644 --- a/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp +++ b/mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp @@ -256,6 +256,7 @@ void transform::ApplyFoldAddIntoDestPatternsOp::populatePatterns( void transform::ApplyPadVectorizationPatternsOp::populatePatterns( RewritePatternSet &patterns) { linalg::populatePadOpVectorizationPatterns(patterns); + linalg::populateInsertSliceVectorizationPatterns(patterns); } //===----------------------------------------------------------------------===// @@ -3482,6 +3483,9 @@ transform::VectorizeChildrenAndApplyPatternsOp::applyToOne( patterns.add(ctx); + // Add misc. vectorization patterns (e.g. for tensor.insert_slice) + linalg::populateInsertSliceVectorizationPatterns(patterns); + if (getVectorizePadding()) linalg::populatePadOpVectorizationPatterns(patterns); diff --git a/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp b/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp index 0fe096863d7b016340b4ae250421672b270fa9ed..da5233049aaf69e87ce0de7b965a211cd39f849d 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp @@ -973,12 +973,7 @@ GeneralizePadOpPattern::matchAndRewrite(tensor::PadOp padOp, padOp.getLoc(), staticSizes, resultType.getElementType(), dynSizes); Value fill = createFillOrGenerateOp(rewriter, padOp, emptyTensor, dynSizes); - // Try optimize the copy of source. - if (optimizeCopyFn && optimizeCopyFn(rewriter, padOp, fill).succeeded()) - return success(); - - // tensor::PadOps cannot be optimized. Generate a InsertSliceOp instead - // for copying the PadOp source. + // Generate a InsertSliceOp for copying the PadOp source. auto sourceType = padOp.getSourceType(); // Compute size of source of tensor::PadOp. SmallVector srcSizes = diff --git a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp index 0a2457176a1d47483742600746d198db15b058f8..090e0b46768d7e9421917f196dc63241930bb0b9 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp @@ -2281,115 +2281,6 @@ LogicalResult mlir::linalg::vectorizeCopy(RewriterBase &rewriter, //----------------------------------------------------------------------------// // Misc. vectorization patterns. //----------------------------------------------------------------------------// - -/// Helper function that retrieves the value of an IntegerAttr. -static int64_t getIntFromAttr(Attribute attr) { - return cast(attr).getInt(); -} - -/// Given an ArrayRef of OpFoldResults, return a vector of Values. -/// IntegerAttrs are converted to ConstantIndexOps. Other attribute types are -/// not supported. -static SmallVector ofrToIndexValues(RewriterBase &rewriter, Location loc, - ArrayRef ofrs) { - SmallVector result; - for (auto o : ofrs) { - if (auto val = llvm::dyn_cast_if_present(o)) { - result.push_back(val); - } else { - result.push_back(rewriter.create( - loc, getIntFromAttr(o.template get()))); - } - } - return result; -} - -/// Rewrite a tensor::PadOp into a sequence of EmptyOp, FillOp and -/// InsertSliceOp. For now, only constant padding values are supported. -/// If there is enough static type information, TransferReadOps and -/// TransferWriteOps may be generated instead of InsertSliceOps. -struct GenericPadOpVectorizationPattern : public GeneralizePadOpPattern { - GenericPadOpVectorizationPattern(MLIRContext *context, - PatternBenefit benefit = 1) - : GeneralizePadOpPattern(context, tryVectorizeCopy, benefit) {} - /// Vectorize the copying of a tensor::PadOp's source. This is possible if - /// each dimension size is statically know in the source type or the result - /// type (or both). - static LogicalResult tryVectorizeCopy(RewriterBase &rewriter, - tensor::PadOp padOp, Value dest) { - auto sourceType = padOp.getSourceType(); - auto resultType = padOp.getResultType(); - if (!VectorType::isValidElementType(sourceType.getElementType())) - return failure(); - - // Copy cannot be vectorized if pad value is non-constant and source shape - // is dynamic. In case of a dynamic source shape, padding must be appended - // by TransferReadOp, but TransferReadOp supports only constant padding. - auto padValue = padOp.getConstantPaddingValue(); - if (!padValue) { - if (!sourceType.hasStaticShape()) - return failure(); - // Create dummy padding value. - auto elemType = sourceType.getElementType(); - padValue = rewriter.create( - padOp.getLoc(), elemType, rewriter.getZeroAttr(elemType)); - } - - SmallVector vecShape; - SmallVector readInBounds; - SmallVector writeInBounds; - for (unsigned i = 0; i < sourceType.getRank(); ++i) { - if (!sourceType.isDynamicDim(i)) { - vecShape.push_back(sourceType.getDimSize(i)); - // Source shape is statically known: Neither read nor write are - // out-of- bounds. - readInBounds.push_back(true); - writeInBounds.push_back(true); - } else if (!resultType.isDynamicDim(i)) { - // Source shape is not statically known, but result shape is. - // Vectorize with size of result shape. This may be larger than the - // source size. - vecShape.push_back(resultType.getDimSize(i)); - // Read may be out-of-bounds because the result size could be larger - // than the source size. - readInBounds.push_back(false); - // Write is out-of-bounds if low padding > 0. - writeInBounds.push_back( - getConstantIntValue(padOp.getMixedLowPad()[i]) == - static_cast(0)); - } else { - // Neither source nor result dim of padOp is static. Cannot vectorize - // the copy. - return failure(); - } - } - auto vecType = VectorType::get(vecShape, sourceType.getElementType()); - - // Generate TransferReadOp. - SmallVector readIndices( - vecType.getRank(), - rewriter.create(padOp.getLoc(), 0)); - auto read = rewriter.create( - padOp.getLoc(), vecType, padOp.getSource(), readIndices, padValue, - ArrayRef{readInBounds}); - - // If `dest` is a FillOp and the TransferWriteOp would overwrite the - // entire tensor, write directly to the FillOp's operand. - if (llvm::equal(vecShape, resultType.getShape()) && - llvm::all_of(writeInBounds, [](bool b) { return b; })) - if (auto fill = dest.getDefiningOp()) - dest = fill.output(); - - // Generate TransferWriteOp. - auto writeIndices = - ofrToIndexValues(rewriter, padOp.getLoc(), padOp.getMixedLowPad()); - rewriter.replaceOpWithNewOp( - padOp, read, dest, writeIndices, ArrayRef{writeInBounds}); - - return success(); - } -}; - /// Base pattern for rewriting tensor::PadOps whose result is consumed by a /// given operation type OpTy. template @@ -2623,6 +2514,163 @@ struct PadOpVectorizationWithTransferWritePattern } }; +/// Returns the effective Pad value for the input op, provided it's a scalar. +/// +/// Many Ops exhibit pad-like behaviour, but this isn't always explicit. If +/// this Op performs padding, retrieve the padding value provided that it's +/// a scalar and static/fixed for all the padded values. Returns an empty value +/// otherwise. +static Value getStaticPadVal(Operation *op) { + if (!op) + return {}; + + // 1. vector.broadcast (f32 -> vector <...xf32>) - return the value that's + // being broadcast, provided that it's a scalar. + if (auto bcast = llvm::dyn_cast(op)) { + auto source = bcast.getSource(); + if (llvm::dyn_cast(source.getType())) + return {}; + + return source; + } + + // 2. linalg.fill - use the scalar input value that used to fill the output + // tensor. + if (auto fill = llvm::dyn_cast(op)) { + return fill.getInputs()[0]; + } + + // 3. tensor.generateOp - can't guarantee the value is fixed without + // analysing, bail out. + if (auto generate = llvm::dyn_cast(op)) { + return {}; + } + + // 4. vector.transfer_write - inspect the input vector that's written from. If + // if contains a single value that has been broadcast (e.g. via + // vector.broadcast), extract it, fail otherwise. + if (auto xferWrite = llvm::dyn_cast(op)) + return getStaticPadVal(xferWrite.getVector().getDefiningOp()); + + // 5. tensor.insert_slice - inspect the destination tensor. If it's larger + // than the input tensor, then, provided it's constant, we'll extract the + // value that was used to generate it (via e.g. linalg.fill), fail otherwise. + // TODO: Clarify the semantics when the input tensor is larger than the + // destination. + if (auto slice = llvm::dyn_cast(op)) + return getStaticPadVal(slice.getDest().getDefiningOp()); + + return {}; +} + +/// Rewrite tensor.insert.slice as a vector.transfer_read + +/// vector.transfer_write pair. The vector size is inferred from the static +/// dims in the input and output tensors. If a dim is dynamic in both the input +/// and output tensors, bails out. +/// +/// Before: +/// !t_in_type = tensor<1x2x3xf32> +/// !t_out_type = tensor<9x8x7x1x2x3xf32> +/// !v_type = vector<1x2x3xf32> +/// %inserted_slice = tensor.insert_slice %src into %dest ... : !t_in_type +/// into !t_out_type +/// After: +/// %read = vector.transfer_read %src[...], %pad ... : !t_in_type, !v_type +/// %write = vector.transfer_write %read, %dest ... : !v_type, !t_out_type +/// +/// TODO: Support masking +struct InsertSliceVectorizePattern + : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(tensor::InsertSliceOp sliceOp, + PatternRewriter &rewriter) const final { + auto sourceType = sliceOp.getSource().getType(); + if (!VectorType::isValidElementType(sourceType.getElementType())) + return failure(); + + auto resultType = sliceOp.getResultType(); + + // 1. Get the pad value. + // TransferReadOp requires a scalar padding value. Note that: + // * for in-bounds access, the value is actually irrelevant. + // There are 2 cases in which xfer.read accesses are known to be in-bounds: + // 1. The source shape is static (output vector sizes would be based on + // the source shape and hence all memory accesses would be in-bounds), + // 2. Masking is used (output vector sizes would be user-provided, in which + // case it is assumed that all memory accesses are in-bounds). This + // remains a TODO. + // + // When the value is not known and not needed, use 0. Otherwise, bail out. + Value padValue = getStaticPadVal(sliceOp); + bool isOutOfBoundsRead = !sourceType.hasStaticShape(); + + if (!padValue && isOutOfBoundsRead) { + LDBG("Failed to get a pad value for out-of-bounds read access\n"); + return failure(); + } + + if (!padValue) { + auto elemType = sourceType.getElementType(); + padValue = rewriter.create( + sliceOp.getLoc(), elemType, rewriter.getZeroAttr(elemType)); + } + + // 2. Get the vector shape and in-bounds attributes + SmallVector vecShape; + SmallVector readInBounds; + SmallVector writeInBounds; + size_t rankDiff = resultType.getRank() - sourceType.getRank(); + for (unsigned i = 0; i < sourceType.getRank(); ++i) { + if (!sourceType.isDynamicDim(i)) { + vecShape.push_back(sourceType.getDimSize(i)); + // Source shape is statically known: Neither read nor write are + // out-of-bounds. + readInBounds.push_back(true); + writeInBounds.push_back(true); + } else if (!resultType.isDynamicDim(i)) { + // Source shape is not statically known, but result shape is. + // Vectorize with size of result shape. This may be larger than the + // source size. + // FIXME: Using rankDiff implies that the source tensor is inserted at + // the end of the destination tensor. However, that's not required. + vecShape.push_back(resultType.getDimSize(rankDiff + i)); + // Read may be out-of-bounds because the result size could be larger + // than the source size. + readInBounds.push_back(false); + // Write will in-bounds provided that the corresponding write idx is 0. + // To keep this logic simple, conservatively mark as out-of-bounds. + writeInBounds.push_back(false); + } else { + // Neither source nor result dim of padOp is static. Cannot vectorize + // the copy. + // TODO: Add support for masking + return failure(); + } + } + auto vecType = VectorType::get(vecShape, sourceType.getElementType()); + + // 3. Generate TransferReadOp. + SmallVector readIndices( + vecType.getRank(), + rewriter.create(sliceOp.getLoc(), 0)); + auto read = rewriter.create( + sliceOp.getLoc(), vecType, sliceOp.getSource(), readIndices, padValue, + ArrayRef{readInBounds}); + + // 4. Generate TransferWriteOp. + auto writeIndices = getValueOrCreateConstantIndexOp( + rewriter, sliceOp.getLoc(), sliceOp.getMixedOffsets()); + + // 5. Finalize + rewriter.replaceOpWithNewOp( + sliceOp, read, sliceOp.getDest(), writeIndices, + ArrayRef{writeInBounds}); + + return success(); + } +}; + /// Rewrite use of tensor::PadOp result in InsertSliceOp. E.g.: /// ``` /// %0 = tensor.pad %src ... : tensor to tensor<17x5xf32> @@ -2699,8 +2747,8 @@ struct PadOpVectorizationWithInsertSlicePattern // Generate TransferWriteOp: Write to InsertSliceOp's dest tensor at // specified offsets. Write is fully in-bounds because a InsertSliceOp's // source must fit into the destination at the specified offsets. - auto writeIndices = - ofrToIndexValues(rewriter, padOp.getLoc(), insertOp.getMixedOffsets()); + auto writeIndices = getValueOrCreateConstantIndexOp( + rewriter, padOp.getLoc(), insertOp.getMixedOffsets()); SmallVector inBounds(vecRank, true); rewriter.replaceOpWithNewOp( insertOp, read, insertOp.getDest(), writeIndices, @@ -2710,13 +2758,18 @@ struct PadOpVectorizationWithInsertSlicePattern } }; +void mlir::linalg::populateInsertSliceVectorizationPatterns( + RewritePatternSet &patterns) { + patterns.add(patterns.getContext()); +} + void mlir::linalg::populatePadOpVectorizationPatterns( RewritePatternSet &patterns, PatternBenefit baseBenefit) { // TODO: The following pattern implements "decomposition" and // optional "vectorization". Seperate "decomposition" into a sepereate // pre-processing pattern group. - patterns.add(patterns.getContext(), - baseBenefit); + patterns.add(patterns.getContext(), baseBenefit); + // Try these specialized patterns first before resorting to the generic one. patterns.add getLinearizedMemRefOffsetAndSize( // Adjust linearizedIndices and size by the scale factor (dstBits / srcBits). int64_t scaler = dstBits / srcBits; - addMulMap = addMulMap.floorDiv(scaler); mulMap = mulMap.floorDiv(scaler); OpFoldResult linearizedIndices = affine::makeComposedFoldedAffineApply( - builder, loc, addMulMap, offsetValues); + builder, loc, addMulMap.floorDiv(scaler), offsetValues); OpFoldResult linearizedSize = affine::makeComposedFoldedAffineApply(builder, loc, mulMap, sizes); @@ -95,7 +94,11 @@ std::pair getLinearizedMemRefOffsetAndSize( OpFoldResult adjustBaseOffset = affine::makeComposedFoldedAffineApply( builder, loc, s0.floorDiv(scaler), {offset}); - return {{adjustBaseOffset, linearizedSize}, linearizedIndices}; + OpFoldResult intraVectorOffset = affine::makeComposedFoldedAffineApply( + builder, loc, addMulMap % scaler, offsetValues); + + return {{adjustBaseOffset, linearizedSize, intraVectorOffset}, + linearizedIndices}; } LinearizedMemRefInfo diff --git a/mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp b/mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp index a30e349d49136c29c10ba46a6316772d487e3b14..5104ad4b3a3038f1bfc05deb2e5358c727c990a1 100644 --- a/mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp +++ b/mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp @@ -206,12 +206,11 @@ LogicalResult mlir::scf::peelForLoopAndSimplifyBounds(RewriterBase &rewriter, return success(); } -/// When the `peelFront` option is set as true, the first iteration of the loop -/// is peeled off. This function rewrites the original scf::ForOp as two -/// scf::ForOp Ops, the first scf::ForOp corresponds to the first iteration of -/// the loop which can be canonicalized away in the following optimization. The -/// second loop Op contains the remaining iteration, and the new lower bound is -/// the original lower bound plus the number of steps. +/// Rewrites the original scf::ForOp as two scf::ForOp Ops, the first +/// scf::ForOp corresponds to the first iteration of the loop which can be +/// canonicalized away in the following optimizations. The second loop Op +/// contains the remaining iterations, with a lower bound updated as the +/// original lower bound plus the step (i.e. skips the first iteration). LogicalResult mlir::scf::peelForLoopFirstIteration(RewriterBase &b, ForOp forOp, ForOp &firstIteration) { RewriterBase::InsertionGuard guard(b); diff --git a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp index d71a236f62f454d781d79da5712678d190d18e1e..1853ae04f45d90c18476bc0584883c875cf20f4d 100644 --- a/mlir/lib/Dialect/Vector/IR/VectorOps.cpp +++ b/mlir/lib/Dialect/Vector/IR/VectorOps.cpp @@ -2951,11 +2951,11 @@ void InsertOp::getCanonicalizationPatterns(RewritePatternSet &results, InsertOpConstantFolder>(context); } -// Eliminates insert operations that produce values identical to their source -// value. This happens when the source and destination vectors have identical -// sizes. OpFoldResult vector::InsertOp::fold(FoldAdaptor adaptor) { - if (getNumIndices() == 0) + // Fold "vector.insert %v, %dest [] : vector<2x2xf32> from vector<2x2xf32>" to + // %v. Note: Do not fold "vector.insert %v, %dest [] : f32 into vector" + // (type mismatch). + if (getNumIndices() == 0 && getSourceType() == getType()) return getSource(); return {}; } diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp index 66362d3ca70fb64b673474fc343d1e0330d0daeb..1d6f8a991d9b5b7c2e151fa3495a5c226304f5fc 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp @@ -13,6 +13,7 @@ #include "mlir/Dialect/Arith/Utils/Utils.h" #include "mlir/Dialect/MemRef/IR/MemRef.h" #include "mlir/Dialect/MemRef/Utils/MemRefUtils.h" +#include "mlir/Dialect/Utils/StaticValueUtils.h" #include "mlir/Dialect/Vector/IR/VectorOps.h" #include "mlir/Dialect/Vector/Transforms/VectorRewritePatterns.h" #include "mlir/IR/BuiltinAttributes.h" @@ -22,8 +23,10 @@ #include "mlir/Transforms/DialectConversion.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include +#include using namespace mlir; @@ -33,17 +36,22 @@ using namespace mlir; #define LDBG(X) LLVM_DEBUG(DBGS() << X << "\n") /// Returns a compressed mask. The mask value is set only if any mask is present -/// in the scale range. E.g., if `scale` equals to 2, the following mask: +/// in the scale range. E.g., if `scale` equals to 2, and `intraDataOffset` +/// equals to 2, the following mask: /// /// %mask = [1, 1, 1, 0, 0, 0] /// -/// will return the following new compressed mask: +/// will first be padded with number of `intraDataOffset` zeros: +/// %mask = [0, 0, 1, 1, 1, 0, 0, 0] /// -/// %mask = [1, 1, 0] +/// then it will return the following new compressed mask: +/// +/// %mask = [0, 1, 1, 0] static FailureOr getCompressedMaskOp(OpBuilder &rewriter, Location loc, Value mask, - int origElements, int scale) { - auto numElements = (origElements + scale - 1) / scale; + int origElements, int scale, + int intraDataOffset = 0) { + auto numElements = (intraDataOffset + origElements + scale - 1) / scale; Operation *maskOp = mask.getDefiningOp(); SmallVector extractOps; @@ -67,6 +75,9 @@ static FailureOr getCompressedMaskOp(OpBuilder &rewriter, shape.back() = numElements; auto newMaskType = VectorType::get(shape, rewriter.getI1Type()); if (createMaskOp) { + // TODO: handle the case with non-zero intraDataOffset for CreateMaskOp. + if (intraDataOffset != 0) + return failure(); OperandRange maskOperands = createMaskOp.getOperands(); size_t numMaskOperands = maskOperands.size(); AffineExpr s0; @@ -86,11 +97,27 @@ static FailureOr getCompressedMaskOp(OpBuilder &rewriter, ArrayRef maskDimSizes = constantMaskOp.getMaskDimSizes(); size_t numMaskOperands = maskDimSizes.size(); int64_t origIndex = maskDimSizes[numMaskOperands - 1]; - int64_t maskIndex = (origIndex + scale - 1) / scale; + int64_t startIndex = intraDataOffset / scale; + int64_t maskIndex = llvm::divideCeil(intraDataOffset + origIndex, scale); + + // TODO: we only want the mask between [startIndex, maskIndex] to be true, + // the rest are false. + if (intraDataOffset != 0 && maskDimSizes.size() > 1) + return failure(); + SmallVector newMaskDimSizes(maskDimSizes.drop_back()); newMaskDimSizes.push_back(maskIndex); - newMask = rewriter.create(loc, newMaskType, - newMaskDimSizes); + + if (intraDataOffset == 0) { + newMask = rewriter.create(loc, newMaskType, + newMaskDimSizes); + } else { + SmallVector newMaskValues; + for (int64_t i = 0; i < numElements; ++i) + newMaskValues.push_back(i >= startIndex && i < maskIndex); + auto denseAttr = DenseElementsAttr::get(newMaskType, newMaskValues); + newMask = rewriter.create(loc, newMaskType, denseAttr); + } } while (!extractOps.empty()) { @@ -102,6 +129,26 @@ static FailureOr getCompressedMaskOp(OpBuilder &rewriter, return newMask; } +static Value extractSubvectorFrom(RewriterBase &rewriter, Location loc, + VectorType extractType, Value vector, + int64_t frontOffset, int64_t subvecSize) { + auto offsets = rewriter.getI64ArrayAttr({frontOffset}); + auto sizes = rewriter.getI64ArrayAttr({subvecSize}); + auto strides = rewriter.getI64ArrayAttr({1}); + return rewriter + .create(loc, extractType, vector, offsets, + sizes, strides) + ->getResult(0); +} + +static Value insertSubvectorInto(RewriterBase &rewriter, Location loc, + Value src, Value dest, int64_t offset) { + auto offsets = rewriter.getI64ArrayAttr({offset}); + auto strides = rewriter.getI64ArrayAttr({1}); + return rewriter.create(loc, dest.getType(), src, + dest, offsets, strides); +} + namespace { //===----------------------------------------------------------------------===// @@ -201,7 +248,8 @@ struct ConvertVectorMaskedStore final auto stridedMetadata = rewriter.create(loc, op.getBase()); OpFoldResult linearizedIndicesOfr; - std::tie(std::ignore, linearizedIndicesOfr) = + memref::LinearizedMemRefInfo linearizedInfo; + std::tie(linearizedInfo, linearizedIndicesOfr) = memref::getLinearizedMemRefOffsetAndSize( rewriter, loc, srcBits, dstBits, stridedMetadata.getConstifiedMixedOffset(), @@ -214,19 +262,19 @@ struct ConvertVectorMaskedStore final // Load the whole data and use arith.select to handle the corner cases. // E.g., given these input values: // - // %mask = [1, 1, 1, 0, 0, 0] - // %0[%c0, %c0] contains [0x1, 0x2, 0x3, 0x4, 0x5, 0x6] - // %value_to_store = [0x7, 0x8, 0x9, 0xA, 0xB, 0xC] + // %mask = [0, 1, 1, 1, 1, 1, 0, 0] + // %0[%c0, %c0] contains [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8] + // %value_to_store = [0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF, 0x0] // // we'll have // - // expected output: [0x7, 0x8, 0x9, 0x4, 0x5, 0x6] + // expected output: [0x1, 0xA, 0xB, 0xC, 0xD, 0xE, 0x7, 0x8] // - // %new_mask = [1, 1, 0] - // %maskedload = [0x12, 0x34, 0x0] - // %bitcast = [0x1, 0x2, 0x3, 0x4, 0x0, 0x0] - // %select_using_original_mask = [0x7, 0x8, 0x9, 0x4, 0x0, 0x0] - // %packed_data = [0x78, 0x94, 0x00] + // %new_mask = [1, 1, 1, 0] + // %maskedload = [0x12, 0x34, 0x56, 0x00] + // %bitcast = [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x0, 0x0] + // %select_using_shifted_mask = [0x1, 0xA, 0xB, 0xC, 0xD, 0xE, 0x0, 0x0] + // %packed_data = [0x1A, 0xBC, 0xDE, 0x00] // // Using the new mask to store %packed_data results in expected output. FailureOr newMask = @@ -243,8 +291,9 @@ struct ConvertVectorMaskedStore final loc, newType, adaptor.getBase(), linearizedIndices, newMask.value()->getResult(0), passThru); - Value valueToStore = rewriter.create( - loc, op.getValueToStore().getType(), newLoad); + auto newBitCastType = VectorType::get(numElements * scale, oldElementType); + Value valueToStore = + rewriter.create(loc, newBitCastType, newLoad); valueToStore = rewriter.create( loc, op.getMask(), op.getValueToStore(), valueToStore); valueToStore = @@ -294,19 +343,31 @@ struct ConvertVectorLoad final : OpConversionPattern { // %1 = vector.load %0[%linear_index] : memref<6xi8>, vector<2xi8> // %2 = vector.bitcast %1 : vector<2xi8> to vector<4xi4> // - // TODO: Currently, only the even number of elements loading is supported. - // To deal with the odd number of elements, one has to extract the - // subvector at the proper offset after bit-casting. + // There are cases where the number of elements to load is not byte-aligned, + // for example: + // + // %1 = vector.load %0[%c1, %c0] : memref<3x3xi2>, vector<3xi2> + // + // we will have to load extra bytes and extract the exact slice in between. + // + // %1 = vector.load %0[%c2] : memref<3xi8>, vector<2xi8> + // %2 = vector.bitcast %1 : vector<2xi8> to vector<8xi2> + // %3 = vector.extract_strided_slice %1 {offsets = [2], sizes = [3], strides + // = [1]} + // : vector<8xi2> to vector<3xi2> + // + // TODO: Currently the extract_strided_slice's attributes must be known at + // compile time as they must be constants. auto origElements = op.getVectorType().getNumElements(); - if (origElements % scale != 0) - return failure(); + bool isUnalignedEmulation = origElements % scale != 0; auto stridedMetadata = rewriter.create(loc, op.getBase()); OpFoldResult linearizedIndices; - std::tie(std::ignore, linearizedIndices) = + memref::LinearizedMemRefInfo linearizedInfo; + std::tie(linearizedInfo, linearizedIndices) = memref::getLinearizedMemRefOffsetAndSize( rewriter, loc, srcBits, dstBits, stridedMetadata.getConstifiedMixedOffset(), @@ -314,15 +375,31 @@ struct ConvertVectorLoad final : OpConversionPattern { stridedMetadata.getConstifiedMixedStrides(), getAsOpFoldResult(adaptor.getIndices())); - auto numElements = (origElements + scale - 1) / scale; + std::optional foldedIntraVectorOffset = + isUnalignedEmulation + ? getConstantIntValue(linearizedInfo.intraDataOffset) + : 0; + + if (!foldedIntraVectorOffset) { + // unimplemented case for dynamic intra vector offset + return failure(); + } + + auto numElements = + llvm::divideCeil(*foldedIntraVectorOffset + origElements, scale); auto newLoad = rewriter.create( loc, VectorType::get(numElements, newElementType), adaptor.getBase(), getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices)); - auto bitCast = - rewriter.create(loc, op.getType(), newLoad); + Value result = rewriter.create( + loc, VectorType::get(numElements * scale, oldElementType), newLoad); - rewriter.replaceOp(op, bitCast->getResult(0)); + if (isUnalignedEmulation) { + result = extractSubvectorFrom(rewriter, loc, op.getType(), result, + *foldedIntraVectorOffset, origElements); + } + + rewriter.replaceOp(op, result); return success(); } }; @@ -396,13 +473,13 @@ struct ConvertVectorMaskedLoad final // subvector at the proper offset after bit-casting. auto origType = op.getVectorType(); auto origElements = origType.getNumElements(); - if (origElements % scale != 0) - return failure(); + bool isUnalignedEmulation = origElements % scale != 0; auto stridedMetadata = rewriter.create(loc, op.getBase()); OpFoldResult linearizedIndices; - std::tie(std::ignore, linearizedIndices) = + memref::LinearizedMemRefInfo linearizedInfo; + std::tie(linearizedInfo, linearizedIndices) = memref::getLinearizedMemRefOffsetAndSize( rewriter, loc, srcBits, dstBits, stridedMetadata.getConstifiedMixedOffset(), @@ -410,29 +487,68 @@ struct ConvertVectorMaskedLoad final stridedMetadata.getConstifiedMixedStrides(), getAsOpFoldResult(adaptor.getIndices())); + std::optional foldedIntraVectorOffset = + isUnalignedEmulation + ? getConstantIntValue(linearizedInfo.intraDataOffset) + : 0; + + if (!foldedIntraVectorOffset) { + // unimplemented case for dynamic intra vector offset + return failure(); + } + FailureOr newMask = - getCompressedMaskOp(rewriter, loc, op.getMask(), origElements, scale); + getCompressedMaskOp(rewriter, loc, op.getMask(), origElements, scale, + *foldedIntraVectorOffset); if (failed(newMask)) return failure(); - auto numElements = (origElements + scale - 1) / scale; - auto newType = VectorType::get(numElements, newElementType); + auto numElements = + llvm::divideCeil(*foldedIntraVectorOffset + origElements, scale); + auto loadType = VectorType::get(numElements, newElementType); + auto newBitcastType = VectorType::get(numElements * scale, oldElementType); + + Value passthru = op.getPassThru(); + if (isUnalignedEmulation) { + // create an empty vector of the new type + auto emptyVector = rewriter.create( + loc, newBitcastType, rewriter.getZeroAttr(newBitcastType)); + passthru = insertSubvectorInto(rewriter, loc, passthru, emptyVector, + *foldedIntraVectorOffset); + } auto newPassThru = - rewriter.create(loc, newType, op.getPassThru()); + rewriter.create(loc, loadType, passthru); // Generating the new masked load. auto newLoad = rewriter.create( - loc, newType, adaptor.getBase(), + loc, loadType, adaptor.getBase(), getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices), newMask.value()->getResult(0), newPassThru); // Setting the part that originally was not effectively loaded from memory // to pass through. auto bitCast = - rewriter.create(loc, op.getType(), newLoad); - auto select = rewriter.create(loc, op.getMask(), bitCast, - op.getPassThru()); - rewriter.replaceOp(op, select->getResult(0)); + rewriter.create(loc, newBitcastType, newLoad); + + Value mask = op.getMask(); + if (isUnalignedEmulation) { + auto newSelectMaskType = + VectorType::get(numElements * scale, rewriter.getI1Type()); + // TODO: can fold if op's mask is constant + auto emptyVector = rewriter.create( + loc, newSelectMaskType, rewriter.getZeroAttr(newSelectMaskType)); + mask = insertSubvectorInto(rewriter, loc, op.getMask(), emptyVector, + *foldedIntraVectorOffset); + } + + Value result = + rewriter.create(loc, mask, bitCast, passthru); + + if (isUnalignedEmulation) { + result = extractSubvectorFrom(rewriter, loc, op.getType(), result, + *foldedIntraVectorOffset, origElements); + } + rewriter.replaceOp(op, result); return success(); } @@ -464,8 +580,8 @@ struct ConvertVectorTransferRead final int scale = dstBits / srcBits; auto origElements = op.getVectorType().getNumElements(); - if (origElements % scale != 0) - return failure(); + + bool isUnalignedEmulation = origElements % scale != 0; auto newPadding = rewriter.create(loc, newElementType, adaptor.getPadding()); @@ -474,7 +590,8 @@ struct ConvertVectorTransferRead final rewriter.create(loc, op.getSource()); OpFoldResult linearizedIndices; - std::tie(std::ignore, linearizedIndices) = + memref::LinearizedMemRefInfo linearizedInfo; + std::tie(linearizedInfo, linearizedIndices) = memref::getLinearizedMemRefOffsetAndSize( rewriter, loc, srcBits, dstBits, stridedMetadata.getConstifiedMixedOffset(), @@ -482,18 +599,34 @@ struct ConvertVectorTransferRead final stridedMetadata.getConstifiedMixedStrides(), getAsOpFoldResult(adaptor.getIndices())); - auto numElements = (origElements + scale - 1) / scale; - auto newReadType = VectorType::get(numElements, newElementType); + std::optional foldedIntraVectorOffset = + isUnalignedEmulation + ? getConstantIntValue(linearizedInfo.intraDataOffset) + : 0; + + if (!foldedIntraVectorOffset) { + // unimplemented case for dynamic inra-vector offset + return failure(); + } + + auto numElements = + llvm::divideCeil(*foldedIntraVectorOffset + origElements, scale); auto newRead = rewriter.create( - loc, newReadType, adaptor.getSource(), + loc, VectorType::get(numElements, newElementType), adaptor.getSource(), getValueOrCreateConstantIndexOp(rewriter, loc, linearizedIndices), newPadding); - auto bitCast = - rewriter.create(loc, op.getType(), newRead); + auto bitCast = rewriter.create( + loc, VectorType::get(numElements * scale, oldElementType), newRead); + + Value result = bitCast->getResult(0); + if (isUnalignedEmulation) { + result = extractSubvectorFrom(rewriter, loc, op.getType(), result, + *foldedIntraVectorOffset, origElements); + } + rewriter.replaceOp(op, result); - rewriter.replaceOp(op, bitCast->getResult(0)); return success(); } }; diff --git a/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp b/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp index ec9ed87723e1cc5c946f548d1ad0fc9ba64681e6..a2acf3e732adab0e987cc76978bf05e785d3847d 100644 --- a/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp +++ b/mlir/lib/Interfaces/Utils/InferIntRangeCommon.cpp @@ -298,8 +298,14 @@ static ConstantIntRanges inferDivURange(const ConstantIntRanges &lhs, return minMaxBy(udiv, {lhsMin, lhsMax}, {rhsMin, rhsMax}, /*isSigned=*/false); } - // Otherwise, it's possible we might divide by 0. - return ConstantIntRanges::maxRange(rhsMin.getBitWidth()); + + APInt umin = APInt::getZero(rhsMin.getBitWidth()); + if (lhsMin.uge(rhsMax) && !rhsMax.isZero()) + umin = lhsMin.udiv(rhsMax); + + // X u/ Y u<= X. + APInt umax = lhsMax; + return ConstantIntRanges::fromUnsigned(umin, umax); } ConstantIntRanges diff --git a/mlir/lib/Pass/PassRegistry.cpp b/mlir/lib/Pass/PassRegistry.cpp index 029512fd3ecc118efea70682e94a447477f4b31f..fe842755958418e930abe7c8d18d689b02838a9c 100644 --- a/mlir/lib/Pass/PassRegistry.cpp +++ b/mlir/lib/Pass/PassRegistry.cpp @@ -422,7 +422,7 @@ llvm::cl::OptionValue::operator=( return *this; } -llvm::cl::OptionValue::~OptionValue() = default; +llvm::cl::OptionValue::~OptionValue() = default; void llvm::cl::OptionValue::setValue( const OpPassManager &newValue) { diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp index fc2f88b766f1c562c90e162397a37614d0c5d2ba..d20e5e40076bc3f82fe6759c59e209b5d5e77263 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp @@ -262,6 +262,62 @@ static llvm::omp::ProcBindKind getProcBindKind(omp::ClauseProcBindKind kind) { llvm_unreachable("Unknown ClauseProcBindKind kind"); } +/// Helper function to map block arguments defined by ignored loop wrappers to +/// LLVM values and prevent any uses of those from triggering null pointer +/// dereferences. +/// +/// This must be called after block arguments of parent wrappers have already +/// been mapped to LLVM IR values. +static LogicalResult +convertIgnoredWrapper(omp::LoopWrapperInterface &opInst, + LLVM::ModuleTranslation &moduleTranslation) { + // Map block arguments directly to the LLVM value associated to the + // corresponding operand. This is semantically equivalent to this wrapper not + // being present. + auto forwardArgs = + [&moduleTranslation](llvm::ArrayRef blockArgs, + OperandRange operands) { + for (auto [arg, var] : llvm::zip_equal(blockArgs, operands)) + moduleTranslation.mapValue(arg, moduleTranslation.lookupValue(var)); + }; + + return llvm::TypeSwitch(opInst) + .Case([&](omp::SimdOp op) { + auto blockArgIface = cast(*op); + forwardArgs(blockArgIface.getPrivateBlockArgs(), op.getPrivateVars()); + forwardArgs(blockArgIface.getReductionBlockArgs(), + op.getReductionVars()); + return success(); + }) + .Default([&](Operation *op) { + return op->emitError() << "cannot ignore nested wrapper"; + }); +} + +/// Helper function to call \c convertIgnoredWrapper() for all wrappers of the +/// given \c loopOp nested inside of \c parentOp. This has the effect of mapping +/// entry block arguments defined by these operations to outside values. +/// +/// It must be called after block arguments of \c parentOp have already been +/// mapped themselves. +static LogicalResult +convertIgnoredWrappers(omp::LoopNestOp loopOp, + omp::LoopWrapperInterface parentOp, + LLVM::ModuleTranslation &moduleTranslation) { + SmallVector wrappers; + loopOp.gatherWrappers(wrappers); + + // Process wrappers nested inside of `parentOp` from outermost to innermost. + for (auto it = + std::next(std::find(wrappers.rbegin(), wrappers.rend(), parentOp)); + it != wrappers.rend(); ++it) { + if (failed(convertIgnoredWrapper(*it, moduleTranslation))) + return failure(); + } + + return success(); +} + /// Converts an OpenMP 'masked' operation into LLVM IR using OpenMPIRBuilder. static LogicalResult convertOmpMasked(Operation &opInst, llvm::IRBuilderBase &builder, @@ -1262,9 +1318,6 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, !wsloopOp.getPrivateVars().empty() || wsloopOp.getPrivateSyms()) return opInst.emitError("unhandled clauses for translation to LLVM IR"); - // FIXME: Here any other nested wrappers (e.g. omp.simd) are skipped, so - // codegen for composite constructs like 'DO/FOR SIMD' will be the same as for - // 'DO/FOR'. auto loopOp = cast(wsloopOp.getWrappedLoop()); llvm::ArrayRef isByRef = getIsByRef(wsloopOp.getReductionByref()); @@ -1302,6 +1355,13 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, isByRef))) return failure(); + // TODO: Replace this with proper composite translation support. + // Currently, all nested wrappers are ignored, so 'do/for simd' will be + // treated the same as a standalone 'do/for'. This is allowed by the spec, + // since it's equivalent to always using a SIMD length of 1. + if (failed(convertIgnoredWrappers(loopOp, wsloopOp, moduleTranslation))) + return failure(); + // Store the mapping between reduction variables and their private copies on // ModuleTranslation stack. It can be then recovered when translating // omp.reduce operations in a separate call. diff --git a/mlir/lib/Transforms/Utils/DialectConversion.cpp b/mlir/lib/Transforms/Utils/DialectConversion.cpp index 44cf8331d55a733c6cf2886f5d605a98a1dc249b..0a62628b9ad24073f15b455cf5bb1c80ca5f9150 100644 --- a/mlir/lib/Transforms/Utils/DialectConversion.cpp +++ b/mlir/lib/Transforms/Utils/DialectConversion.cpp @@ -2457,11 +2457,11 @@ legalizeUnresolvedMaterialization(RewriterBase &rewriter, } } - InFlightDiagnostic diag = op->emitError() - << "failed to legalize unresolved materialization " - "from (" - << inputOperands.getTypes() << ") to " << outputType - << " that remained live after conversion"; + InFlightDiagnostic diag = + op->emitError() << "failed to legalize unresolved materialization " + "from (" + << inputOperands.getTypes() << ") to (" << outputType + << ") that remained live after conversion"; diag.attachNote(op->getUsers().begin()->getLoc()) << "see existing live user here: " << *op->getUsers().begin(); return failure(); diff --git a/mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir b/mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir index f4722da08cc40ffef5a49d04655a5aa162d8e135..f5ef821cc9c05803ed5f14a20138b2eae7ff180f 100644 --- a/mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir +++ b/mlir/test/Conversion/MemRefToEmitC/memref-to-emitc.mlir @@ -1,28 +1,35 @@ // RUN: mlir-opt -convert-memref-to-emitc %s -split-input-file | FileCheck %s -// CHECK-LABEL: memref_store -// CHECK-SAME: %[[v:.*]]: f32, %[[i:.*]]: index, %[[j:.*]]: index -func.func @memref_store(%v : f32, %i: index, %j: index) { - // CHECK-NEXT: %[[ALLOCA:.*]] = "emitc.variable"() <{value = #emitc.opaque<"">}> : () -> !emitc.array<4x8xf32> - %0 = memref.alloca() : memref<4x8xf32> +// CHECK-LABEL: alloca() +func.func @alloca() { + // CHECK-NEXT: %[[ALLOCA:.*]] = "emitc.variable"() <{value = #emitc.opaque<"">}> : () -> !emitc.array<2xf32> + %0 = memref.alloca() : memref<2xf32> + return +} - // CHECK-NEXT: %[[SUBSCRIPT:.*]] = emitc.subscript %[[ALLOCA]][%[[i]], %[[j]]] : (!emitc.array<4x8xf32>, index, index) -> !emitc.lvalue +// ----- + +// CHECK-LABEL: memref_store +// CHECK-SAME: %[[buff:.*]]: memref<4x8xf32>, %[[v:.*]]: f32, %[[i:.*]]: index, %[[j:.*]]: index +func.func @memref_store(%buff : memref<4x8xf32>, %v : f32, %i: index, %j: index) { + // CHECK-NEXT: %[[BUFFER:.*]] = builtin.unrealized_conversion_cast %[[buff]] : memref<4x8xf32> to !emitc.array<4x8xf32> + + // CHECK-NEXT: %[[SUBSCRIPT:.*]] = emitc.subscript %[[BUFFER]][%[[i]], %[[j]]] : (!emitc.array<4x8xf32>, index, index) -> !emitc.lvalue // CHECK-NEXT: emitc.assign %[[v]] : f32 to %[[SUBSCRIPT]] : - memref.store %v, %0[%i, %j] : memref<4x8xf32> + memref.store %v, %buff[%i, %j] : memref<4x8xf32> return } // ----- // CHECK-LABEL: memref_load -// CHECK-SAME: %[[i:.*]]: index, %[[j:.*]]: index -func.func @memref_load(%i: index, %j: index) -> f32 { - // CHECK-NEXT: %[[ALLOCA:.*]] = "emitc.variable"() <{value = #emitc.opaque<"">}> : () -> !emitc.array<4x8xf32> - %0 = memref.alloca() : memref<4x8xf32> - - // CHECK-NEXT: %[[SUBSCRIPT:.*]] = emitc.subscript %[[ALLOCA]][%[[i]], %[[j]]] : (!emitc.array<4x8xf32>, index, index) -> !emitc.lvalue +// CHECK-SAME: %[[buff:.*]]: memref<4x8xf32>, %[[i:.*]]: index, %[[j:.*]]: index +func.func @memref_load(%buff : memref<4x8xf32>, %i: index, %j: index) -> f32 { + // CHECK-NEXT: %[[BUFFER:.*]] = builtin.unrealized_conversion_cast %[[buff]] : memref<4x8xf32> to !emitc.array<4x8xf32> + + // CHECK-NEXT: %[[SUBSCRIPT:.*]] = emitc.subscript %[[BUFFER]][%[[i]], %[[j]]] : (!emitc.array<4x8xf32>, index, index) -> !emitc.lvalue // CHECK-NEXT: %[[LOAD:.*]] = emitc.load %[[SUBSCRIPT]] : - %1 = memref.load %0[%i, %j] : memref<4x8xf32> + %1 = memref.load %buff[%i, %j] : memref<4x8xf32> // CHECK-NEXT: return %[[LOAD]] : f32 return %1 : f32 } diff --git a/mlir/test/Dialect/AMX/legalize-for-llvm.mlir b/mlir/test/Dialect/AMX/legalize-for-llvm.mlir index 992203153939fee3548ddb31969c625fc826191c..3cacbd0044f8251dd997091b88c94e009b30d992 100644 --- a/mlir/test/Dialect/AMX/legalize-for-llvm.mlir +++ b/mlir/test/Dialect/AMX/legalize-for-llvm.mlir @@ -43,3 +43,31 @@ func.func @mulf(%arg0: memref, %arg1: memref) { amx.tile_store %arg1[%0, %0], %4 : memref, vector<16x16xf32> return } + +// CHECK-LABEL: strides( +// CHECK: %[[CST_64_1:.+]] = llvm.mlir.constant(64 : i64) : i64 +// CHECK: "amx.tileloadd64"(%{{.+}}, %{{.+}}, %{{.+}}, %[[CST_64_1]] +// CHECK: %[[CST_128_1:.+]] = llvm.mlir.constant(128 : i64) : i64 +// CHECK: "amx.tileloadd64"(%{{.+}}, %{{.+}}, %{{.+}}, %[[CST_128_1]] +// CHECK: llvm.mlir.constant(2 : i64) : i64 +// CHECK: llvm.extractvalue %{{.+}}[4, 0] +// CHECK: %[[STRIDE_1:.+]] = llvm.mul +// CHECK: "amx.tileloadd64"(%{{.+}}, %{{.+}}, %{{.+}}, %[[STRIDE_1]] +// CHECK: %[[CST_64_2:.+]] = llvm.mlir.constant(64 : i64) : i64 +// CHECK: "amx.tilestored64"(%{{.+}}, %{{.+}}, %{{.+}}, %[[CST_64_2]] +// CHECK: %[[CST_128_2:.+]] = llvm.mlir.constant(128 : i64) : i64 +// CHECK: "amx.tilestored64"(%{{.+}}, %{{.+}}, %{{.+}}, %[[CST_128_2]] +// CHECK: llvm.mlir.constant(2 : i64) : i64 +// CHECK: llvm.extractvalue %{{.+}}[4, 0] +// CHECK: %[[STRIDE_2:.+]] = llvm.mul +// CHECK: "amx.tilestored64"(%{{.+}}, %{{.+}}, %{{.+}}, %[[STRIDE_2]] +func.func @strides(%arg0: memref<16x32xbf16>, %arg1: memref<16x32xbf16, strided<[64, 1]>>, %arg2: memref<16x32xbf16, strided<[?, 1]>>) { + %0 = arith.constant 0 : index + %1 = amx.tile_load %arg0[%0, %0] : memref<16x32xbf16> into vector<16x32xbf16> + %2 = amx.tile_load %arg1[%0, %0] : memref<16x32xbf16, strided<[64, 1]>> into vector<16x32xbf16> + %3 = amx.tile_load %arg2[%0, %0] : memref<16x32xbf16, strided<[?, 1]>> into vector<16x32xbf16> + amx.tile_store %arg0[%0, %0], %3 : memref<16x32xbf16>, vector<16x32xbf16> + amx.tile_store %arg1[%0, %0], %1 : memref<16x32xbf16, strided<[64, 1]>>, vector<16x32xbf16> + amx.tile_store %arg2[%0, %0], %2 : memref<16x32xbf16, strided<[?, 1]>>, vector<16x32xbf16> + return +} diff --git a/mlir/test/Dialect/Arith/int-range-interface.mlir b/mlir/test/Dialect/Arith/int-range-interface.mlir index 4b04229e5db52f0cc4e641af18f2435e7c1e7d3c..6d66da2fc1eb35c610e9ed97e38cddf8706ad479 100644 --- a/mlir/test/Dialect/Arith/int-range-interface.mlir +++ b/mlir/test/Dialect/Arith/int-range-interface.mlir @@ -178,8 +178,8 @@ func.func @div_bounds_negative(%arg0 : index) -> i1 { } // CHECK-LABEL: func @div_zero_undefined -// CHECK: %[[ret:.*]] = arith.cmpi ule -// CHECK: return %[[ret]] +// CHECK: %[[true:.*]] = arith.constant true +// CHECK: return %[[true]] func.func @div_zero_undefined(%arg0 : index) -> i1 { %c0 = arith.constant 0 : index %c1 = arith.constant 1 : index @@ -190,6 +190,19 @@ func.func @div_zero_undefined(%arg0 : index) -> i1 { func.return %2 : i1 } +// CHECK-LABEL: func @div_refine_min +// CHECK: %[[true:.*]] = arith.constant true +// CHECK: return %[[true]] +func.func @div_refine_min(%arg0 : index) -> i1 { + %c0 = arith.constant 1 : index + %c1 = arith.constant 2 : index + %c4 = arith.constant 4 : index + %0 = arith.andi %arg0, %c1 : index + %1 = arith.divui %c4, %0 : index + %2 = arith.cmpi uge, %1, %c0 : index + func.return %2 : i1 +} + // CHECK-LABEL: func @ceil_divui // CHECK: %[[ret:.*]] = arith.cmpi eq // CHECK: return %[[ret]] @@ -271,13 +284,13 @@ func.func @remui_base(%arg0 : index, %arg1 : index ) -> i1 { // CHECK: return %[[true]] func.func @remui_base_maybe_zero(%arg0 : index, %arg1 : index ) -> i1 { %c4 = arith.constant 4 : index - %c5 = arith.constant 5 : index + %c5 = arith.constant 5 : index %0 = arith.minui %arg1, %c4 : index %1 = arith.remui %arg0, %0 : index %2 = arith.cmpi ult, %1, %c5 : index func.return %2 : i1 -} +} // CHECK-LABEL: func @remsi_base // CHECK: %[[ret:.*]] = arith.cmpi sge diff --git a/mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir b/mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir index ab18ce05e355d3efeb2a1fc97dc92ed39751bf32..bae94c1be4da9088f7f2b5d951811f2ade9e10c1 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/finalizing-bufferize.mlir @@ -78,7 +78,7 @@ func.func @static_layout_to_no_layout_cast(%m: memref) -> memref> { %0 = bufferization.to_tensor %m : memref - // expected-error @+1 {{failed to legalize unresolved materialization from ('memref') to 'memref>' that remained live after conversion}} + // expected-error @+1 {{failed to legalize unresolved materialization from ('memref') to ('memref>') that remained live after conversion}} %1 = bufferization.to_memref %0 : memref> // expected-note @below{{see existing live user here}} return %1 : memref> diff --git a/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir b/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir index ee0f71f668dc7419de2c3d70d04a587a1314e84c..2829eafb7c1c597a35b410330f0d5a512452214f 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-invalid.mlir @@ -1,11 +1,5 @@ // RUN: mlir-opt %s -allow-unregistered-dialect -one-shot-bufferize="bufferize-function-boundaries=1" -split-input-file -verify-diagnostics -// expected-error @+2 {{cannot bufferize bodiless function that returns a tensor}} -// expected-error @+1 {{failed to bufferize op}} -func.func private @foo() -> tensor - -// ----- - // expected-error @+1 {{cannot bufferize a FuncOp with tensors and without a unique ReturnOp}} func.func @swappy(%cond1 : i1, %cond2 : i1, %t1 : tensor, %t2 : tensor) -> (tensor, tensor) @@ -123,17 +117,6 @@ func.func @to_tensor_op_unsupported(%m: memref, %idx: index) -> (f32) { // ----- -// expected-error @+2 {{failed to bufferize op}} -// expected-error @+1 {{cannot bufferize bodiless function that returns a tensor}} -func.func private @foo(%t : tensor) -> (f32, tensor, f32) - -func.func @call_to_unknown_tensor_returning_func(%t : tensor) { - call @foo(%t) : (tensor) -> (f32, tensor, f32) - return -} - -// ----- - func.func @yield_alloc_dominance_test_2(%cst : f32, %idx : index, %idx2 : index) -> f32 { %1 = bufferization.alloc_tensor(%idx) : tensor diff --git a/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir b/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir index 0d5224514e3a021b213d1bb0dcb5532d15dc6916..d31b43477beb9f3811f3e79f6d466323f412b1a7 100644 --- a/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir +++ b/mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize.mlir @@ -42,6 +42,21 @@ func.func private @external_func_with_return_val(tensor<4xi32>) -> f32 // ----- +// Bufferization of bodiless function that returns a tensor. + +// CHECK: func.func private @foo(memref>) -> (f32, memref>, f32) +func.func private @foo(%t : tensor) -> (f32, tensor, f32) + +// CHECK: func.func @call_to_unknown_tensor_returning_func( +// CHECK-SAME: %[[arg0:.*]]: memref>) { +func.func @call_to_unknown_tensor_returning_func(%t : tensor) { + // CHECK: call @foo(%[[arg0]]) : (memref>) -> (f32, memref>, f32) + call @foo(%t) : (tensor) -> (f32, tensor, f32) + return +} + +// ----- + // A function that returns a non-equivalent tensor with layout map. // CHECK-LABEL: func @return_extract_slice(%{{.*}}) -> memref<2x?xf32, strided<[10, 1], offset: ?>> diff --git a/mlir/test/Dialect/Linalg/canonicalize.mlir b/mlir/test/Dialect/Linalg/canonicalize.mlir index 4bc2ed140da91a6154da9c9cc6cf553117a571ee..5de007b390c51d6927df936298b26a97c1330699 100644 --- a/mlir/test/Dialect/Linalg/canonicalize.mlir +++ b/mlir/test/Dialect/Linalg/canonicalize.mlir @@ -1232,3 +1232,20 @@ func.func @transpose_buffer(%input: memref, // CHECK-SAME: %[[VAL_1:.*]]: memref) { // CHECK: linalg.transpose ins(%[[VAL_0]] : memref) // CHECK-SAME: outs(%[[VAL_1]] : memref) permutation = [0] + +// ----- + +// This test checks linalg op has a recursive memory effect. Otherwise +// linalg.map without a user would be DCEd. +func.func @recursive_effect(%arg : tensor<1xf32>) { + %init = arith.constant dense<0.0> : tensor<1xf32> + %mapped = linalg.map ins(%arg:tensor<1xf32>) outs(%init :tensor<1xf32>) + (%in : f32) { + vector.print %in : f32 + linalg.yield %in : f32 + } + func.return +} + +// CHECK-LABEL: @recursive_effect +// CHECK: linalg.map diff --git a/mlir/test/Dialect/Linalg/invalid.mlir b/mlir/test/Dialect/Linalg/invalid.mlir index c481a723c5623c4ecd4e88abcee49bd503a8b76f..4b5a66f8fb5b922de1d99718bbe97b585cd52ecc 100644 --- a/mlir/test/Dialect/Linalg/invalid.mlir +++ b/mlir/test/Dialect/Linalg/invalid.mlir @@ -352,6 +352,15 @@ func.func @illegal_fill_tensor_with_memref_return // ----- +func.func @illegal_fill_value_type(%arg0 : tensor<2x2xf32>, %arg1 : tensor<2xf32>) -> tensor<2x2xf32> +{ + // expected-error @+1 {{expected op with scalar input}} + %0 = linalg.fill ins(%arg1 : tensor<2xf32>) outs(%arg0 : tensor<2x2xf32>) -> tensor<2x2xf32> + return %0 : tensor<2x2xf32> +} + +// ----- + func.func @invalid_static_matmul(%arg0: memref<2x4xf32>, %arg1: memref<3x4xf32>, %arg2: memref<2x4xf32>) { // expected-error @+1 {{inferred input/output operand #1 has shape's dimension #0 to be 4, but found 3}} linalg.matmul ins(%arg0, %arg1 : memref<2x4xf32>, memref<3x4xf32>) diff --git a/mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir b/mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir index 2aa4638af3f0f3be0601374dbbde88315e9e7328..640de85cc5f12e2e42bff5a0df73a22bddf0627f 100644 --- a/mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir +++ b/mlir/test/Dialect/Linalg/vectorization-pad-patterns.mlir @@ -161,7 +161,8 @@ module attributes {transform.with_named_sequence} { ///---------------------------------------------------------------------------------------- /// tensor::PadOp -> tensor::EmptyOp + linalg::FillOp/tensor::GenerateOp + tensor::InsertSliceOp -/// [Pattern: GenericPadOpVectorizationPattern] +/// [Pattern: GenericPadOpVectorizationPattern + InsertSliceVectorizePattern] +/// TODO: Split the test into two, one for each pattern. ///---------------------------------------------------------------------------------------- func.func private @make_vector() -> tensor<12x13xf32> @@ -174,12 +175,14 @@ func.func private @make_vector() -> tensor<12x13xf32> // CHECK-NOT: tensor.pad // CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index // CHECK-DAG: %[[PAD:.*]] = arith.constant 5.000000e+00 : f32 +// CHECK-DAG: %[[PAD_READ:.*]] = arith.constant 0.000000e+00 : f32 // CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<1x12x13xf32> // CHECK: %[[FILL:.*]] = linalg.fill ins(%[[PAD]] : f32) outs(%[[EMPTY]] : tensor<1x12x13xf32>) -> tensor<1x12x13xf32> -// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG_0]]{{\[}}%[[C0]], %[[C0]], %[[C0]]], %[[PAD]] {in_bounds = [true, true, true]} : tensor<1x5x6xf32>, vector<1x5x6xf32> -// CHECK: %[[WRITE:.*]] = vector.transfer_write %[[READ]], %[[FILL]]{{\[}}%[[C0]], %[[C0]], %[[C0]]] {in_bounds = [true, true, true]} : vector<1x5x6xf32>, tensor<1x12x13xf32> +// CHECK: %[[READ_1:.*]] = vector.transfer_read %[[ARG_0]]{{\[}}%[[C0]], %[[C0]], %[[C0]]], %[[PAD]] {in_bounds = [true, true, true]} : tensor<1x5x6xf32>, vector<1x5x6xf32> +// CHECK: %[[WRITE_1:.*]] = vector.transfer_write %[[READ_1]], %[[FILL]]{{\[}}%[[C0]], %[[C0]], %[[C0]]] {in_bounds = [true, true, true]} : vector<1x5x6xf32>, tensor<1x12x13xf32> // CHECK: %[[VEC:.*]] = call @make_vector() : () -> tensor<12x13xf32> -// CHECK: %[[RES:.*]] = tensor.insert_slice %[[VEC]] into %[[WRITE]][0, 0, 0] [1, 12, 13] [1, 1, 1] : tensor<12x13xf32> into tensor<1x12x13xf32> +// CHECK: %[[READ_2:.*]] = vector.transfer_read %[[VEC]]{{\[}}%[[C0]], %[[C0]]], %[[PAD_READ]] {in_bounds = [true, true]} : tensor<12x13xf32>, vector<12x13xf32> +// CHECK: %[[RES:.*]] = vector.transfer_write %[[READ_2]], %[[WRITE_1]]{{\[}}%[[C0]], %[[C0]], %[[C0]]] {in_bounds = [true, true]} : vector<12x13xf32>, tensor<1x12x13xf32> // CHECK: return %[[RES]] : tensor<1x12x13xf32> func.func @pad_and_insert_slice_dest( diff --git a/mlir/test/Dialect/Linalg/vectorization-unsupported.mlir b/mlir/test/Dialect/Linalg/vectorization-unsupported.mlir index e9f8e08ca0c6b4045ebe511ed4ec3b896b467c04..8fbc74ec345c6be4fc8effe333e528ce63fffbb5 100644 --- a/mlir/test/Dialect/Linalg/vectorization-unsupported.mlir +++ b/mlir/test/Dialect/Linalg/vectorization-unsupported.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt %s -transform-interpreter -split-input-file -verify-diagnostics +// RUN: mlir-opt %s -transform-interpreter -split-input-file -verify-diagnostics | FileCheck %s func.func @conv1d_nwc_wcf_dyn_ch_dim(%input: memref<4x6x?xf32>, %filter: memref<1x?x8xf32>, %output: memref<4x2x8xf32>) { // expected-error @+1 {{Attempted to vectorize, but failed}} @@ -253,3 +253,30 @@ module attributes {transform.with_named_sequence} { transform.yield } } + +// ----- + +// With dynamically shaped source, the vectorizer infers the vector size for +// xfer Ops from the destination tensor and, conservatively, assumes +// out-of-bounds accesses. Out-of-bounds accesses require a pad value, but +// that's impossible to recover in this example. Hence no vectorization. + +// TODO: Use diagnostics once we can vectorize tensor.insert_slice with +// transform.structured.vectorize + +// CHECK-LABEL: @insert_dynamic_slice_unknown_pad +// CHECK-NOT: vector +// CHECK: tensor.insert_slice +func.func @insert_dynamic_slice_unknown_pad(%arg0: tensor<1x?x3xf32>, %arg1: tensor<9x8x7x1x2x3xf32>, %size: index) -> tensor<9x8x7x1x2x3xf32> { + %res = tensor.insert_slice %arg0 into %arg1[0, 0, 0, 0, 0, 0] [1, 1, 1, 1, %size, 3][1, 1, 1, 1, 1, 1] : tensor<1x?x3xf32> into tensor<9x8x7x1x2x3xf32> + return %res : tensor<9x8x7x1x2x3xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["tensor.insert_slice"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 : (!transform.any_op) -> !transform.any_op + transform.yield + } +} diff --git a/mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir b/mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir index 189507d97d6dc2f22980085ecfe687eb0b2195c3..d2fb3730a2d2b062a0fae90e9f925ca69cee1d63 100644 --- a/mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir +++ b/mlir/test/Dialect/Linalg/vectorization-with-patterns.mlir @@ -939,16 +939,20 @@ module attributes {transform.with_named_sequence} { func.func private @make_vector() -> tensor<12x13xf32> -// CHECK-LABEL: func @pad_and_insert_slice_dest -// CHECK-SAME: %[[ARG0:.*]]: tensor<1x5x6xf32> -// Check the insert slice is not rewritten if the padded result is used by the destination operand. -// CHECK-NOT: tensor.pad -// CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<1x12x13xf32> -// CHECK: %[[WRITE_1:.*]] = vector.transfer_write %{{.*}}, %[[EMPTY]]{{.*}} : vector<1x12x13xf32>, tensor<1x12x13xf32> -// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG0:.*]]{{.*}} : tensor<1x5x6xf32>, vector<1x5x6xf32> -// CHECK: %[[WRITE_2:.*]] = vector.transfer_write %[[READ]], %[[WRITE_1]]{{.*}} : vector<1x5x6xf32>, tensor<1x12x13xf32> -// CHECK: %[[T1:.*]] = call @make_vector() : () -> tensor<12x13xf32> -// CHECK: tensor.insert_slice %[[T1]] into %[[WRITE_2]] +// CHECK-LABEL: func.func @pad_and_insert_slice_dest( +// CHECK-SAME: %[[ARG_0:.*]]: tensor<1x5x6xf32>) -> tensor<1x12x13xf32> { +// CHECK: %[[C0:.*]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[CST:.*]] = arith.constant dense<5.000000e+00> : vector<1x12x13xf32> +// CHECK: %[[C0_IDX:.*]] = arith.constant 0 : index +// CHECK: %[[PAD_VAL:.*]] = arith.constant 5.000000e+00 : f32 +// CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<1x12x13xf32> +// CHECK: %[[WRITE_1:.*]] = vector.transfer_write %[[CST]], %[[EMPTY]]{{\[}}%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] {in_bounds = [true, true, true]} : vector<1x12x13xf32>, tensor<1x12x13xf32> +// CHECK: %[[READ_1:.*]] = vector.transfer_read %[[ARG_0]]{{\[}}%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]], %[[PAD_VAL]] {in_bounds = [true, true, true]} : tensor<1x5x6xf32>, vector<1x5x6xf32> +// CHECK: %[[WRITE_2:.*]] = vector.transfer_write %[[READ_1]], %[[WRITE_1]]{{\[}}%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] {in_bounds = [true, true, true]} : vector<1x5x6xf32>, tensor<1x12x13xf32> +// CHECK: %[[MAKE_VEC:.*]] = call @make_vector() : () -> tensor<12x13xf32> +// CHECK: %[[READ_2:.*]] = vector.transfer_read %[[MAKE_VEC]]{{\[}}%[[C0_IDX]], %[[C0_IDX]]], %[[C0]] {in_bounds = [true, true]} : tensor<12x13xf32>, vector<12x13xf32> +// CHECK: %[[RES:.*]] = vector.transfer_write %[[READ_2]], %[[WRITE_2]]{{\[}}%[[C0_IDX]], %[[C0_IDX]], %[[C0_IDX]]] {in_bounds = [true, true]} : vector<12x13xf32>, tensor<1x12x13xf32> +// CHECK: return %[[RES]] : tensor<1x12x13xf32> func.func @pad_and_insert_slice_dest( %arg0: tensor<1x5x6xf32>) -> tensor<1x12x13xf32> { %c5 = arith.constant 5.0 : f32 @@ -1924,3 +1928,94 @@ module attributes {transform.with_named_sequence} { transform.yield } } + +// ----- + +///---------------------------------------------------------------------------------------- +/// tensor.insert_slice +///---------------------------------------------------------------------------------------- + +// The pad value for xfer-read is neither needed nor available - use the default (0.0). + +// CHECK-LABEL: func @insert_static_slice_default_pad +// CHECK-SAME: %[[ARG_0:.*]]: tensor<1x2x3xf32>, +// CHECK-SAME: %[[ARG_1:.*]]: tensor<9x8x7x1x2x3xf32>) -> tensor<9x8x7x1x2x3xf32> { +// CHECK: %[[PAD:.*]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG_0]]{{\[}}%[[C0]], %[[C0]], %[[C0]]], %[[PAD]] {in_bounds = [true, true, true]} : tensor<1x2x3xf32>, vector<1x2x3xf32> +// CHECK: %[[WRITE:.*]] = vector.transfer_write %[[READ]], %[[ARG_1]]{{\[}}%[[C0]], %[[C0]], %[[C0]], %[[C0]], %[[C0]], %[[C0]]] {in_bounds = [true, true, true]} : vector<1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: return %[[WRITE]] : tensor<9x8x7x1x2x3xf32> +func.func @insert_static_slice_default_pad(%arg0: tensor<1x2x3xf32>, %arg1: tensor<9x8x7x1x2x3xf32>) -> tensor<9x8x7x1x2x3xf32> { + %res = tensor.insert_slice %arg0 into %arg1[0, 0, 0, 0, 0, 0] [1, 1, 1, 1, 2, 3][1, 1, 1, 1, 1, 1] : tensor<1x2x3xf32> into tensor<9x8x7x1x2x3xf32> + return %res : tensor<9x8x7x1x2x3xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["tensor.insert_slice"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 { vectorize_padding } : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + +// ----- + +// Same as above, but there's a pad value available that should be used instead of the default value. + +// CHECK-LABEL: func.func @insert_static_slice_non_zero_pad +// CHECK-SAME: %[[ARG_0:.*]]: tensor<1x2x3xf32>, +// CHECK-SAME: %[[PAD:.*]]: f32) -> tensor<9x8x7x1x2x3xf32> { +// CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<9x8x7x1x2x3xf32> +// CHECK: %[[BC:.*]] = vector.broadcast %[[PAD]] : f32 to vector<9x8x7x1x2x3xf32> +// CHECK: %[[WRITE:.*]] = vector.transfer_write %[[BC]], %[[EMPTY]]{{.*}} {in_bounds = [true, true, true, true, true, true]} : vector<9x8x7x1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG_0]]{{.*}}, %[[PAD]] {in_bounds = [true, true, true]} : tensor<1x2x3xf32>, vector<1x2x3xf32> +// CHECK: %[[RES:.*]] = vector.transfer_write %[[READ]], %[[WRITE]]{{.*}} {in_bounds = [true, true, true]} : vector<1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: return %[[RES]] : tensor<9x8x7x1x2x3xf32> +func.func @insert_static_slice_non_zero_pad(%arg0: tensor<1x2x3xf32>, %pad : f32) -> tensor<9x8x7x1x2x3xf32> { + %init = tensor.empty() : tensor<9x8x7x1x2x3xf32> + %fill = linalg.fill ins(%pad : f32) outs(%init : tensor<9x8x7x1x2x3xf32>) -> tensor<9x8x7x1x2x3xf32> + %res = tensor.insert_slice %arg0 into %fill[0, 0, 0, 0, 0, 0] [1, 1, 1, 1, 2, 3][1, 1, 1, 1, 1, 1] : tensor<1x2x3xf32> into tensor<9x8x7x1x2x3xf32> + return %res : tensor<9x8x7x1x2x3xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["tensor.insert_slice"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 : (!transform.any_op) -> !transform.any_op + transform.yield + } +} + +// ----- + +// Same as above, but the source type has is dynamically shaped. This means +// that the pad value is now required and the vector dim corresponding to the +// dynamic shape has to be inferred from the shape of the destination tensor. + +// CHECK-LABEL: func.func @insert_dynamic_slice_non_zero_pad( +// CHECK-SAME: %[[ARG_0:.*]]: tensor<1x?x3xf32>, +// CHECK-SAME: %[[PAD:.*]]: f32, +// CHECK-SAME: %[[SIZE:.*]]: index) -> tensor<9x8x7x1x2x3xf32> { +// CHECK: %[[EMPTY:.*]] = tensor.empty() : tensor<9x8x7x1x2x3xf32> +// CHECK: %[[BC:.*]] = vector.broadcast %[[PAD]] : f32 to vector<9x8x7x1x2x3xf32> +// CHECK: %[[WRITE:.*]] = vector.transfer_write %[[BC]], %[[EMPTY]]{{.*}} {in_bounds = [true, true, true, true, true, true]} : vector<9x8x7x1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: %[[READ:.*]] = vector.transfer_read %[[ARG_0]]{{.*}}, %[[PAD]] {in_bounds = [true, false, true]} : tensor<1x?x3xf32>, vector<1x2x3xf32> +// CHECK: %[[RES:.*]] = vector.transfer_write %[[READ]], %[[WRITE]]{{.*}} {in_bounds = [true, true, true]} : vector<1x2x3xf32>, tensor<9x8x7x1x2x3xf32> +// CHECK: return %[[RES]] : tensor<9x8x7x1x2x3xf32> +func.func @insert_dynamic_slice_non_zero_pad(%arg0: tensor<1x?x3xf32>, %pad : f32, %size: index) -> tensor<9x8x7x1x2x3xf32> { + %init = tensor.empty() : tensor<9x8x7x1x2x3xf32> + %fill = linalg.fill ins(%pad : f32) outs(%init : tensor<9x8x7x1x2x3xf32>) -> tensor<9x8x7x1x2x3xf32> + %res = tensor.insert_slice %arg0 into %fill[0, 0, 0, 0, 0, 0] [1, 1, 1, 1, %size, 3][1, 1, 1, 1, 1, 1] : tensor<1x?x3xf32> into tensor<9x8x7x1x2x3xf32> + return %res : tensor<9x8x7x1x2x3xf32> +} + +module attributes {transform.with_named_sequence} { + transform.named_sequence @__transform_main(%arg1: !transform.any_op {transform.readonly}) { + %0 = transform.structured.match ops{["tensor.insert_slice"]} in %arg1 : (!transform.any_op) -> !transform.any_op + %1 = transform.get_parent_op %0 {isolated_from_above} : (!transform.any_op) -> !transform.any_op + %2 = transform.structured.vectorize_children_and_apply_patterns %1 : (!transform.any_op) -> !transform.any_op + transform.yield + } +} diff --git a/mlir/test/Dialect/Vector/canonicalize.mlir b/mlir/test/Dialect/Vector/canonicalize.mlir index 6d6bc199e601c0ab0828b63514c1c3d72327af24..c963460e7259fb5ef3aa4f7c540f11289b8eb9d4 100644 --- a/mlir/test/Dialect/Vector/canonicalize.mlir +++ b/mlir/test/Dialect/Vector/canonicalize.mlir @@ -800,6 +800,43 @@ func.func @fold_extract_shapecast_to_shapecast(%arg0 : vector<3x4xf32>) -> vecto // ----- +// CHECK-LABEL: func @extract_no_fold_scalar_to_0d( +// CHECK-SAME: %[[v:.*]]: vector) +// CHECK: %[[extract:.*]] = vector.extract %[[v]][] : f32 from vector +// CHECK: return %[[extract]] +func.func @extract_no_fold_scalar_to_0d(%v: vector) -> f32 { + %0 = vector.extract %v[] : f32 from vector + return %0 : f32 +} + +// ----- + +// CHECK-LABEL: func @insert_fold_same_rank( +// CHECK-SAME: %[[v:.*]]: vector<2x2xf32>) +// CHECK: %[[CST:.+]] = arith.constant +// CHECK-SAME: : vector<2x2xf32> +// CHECK-NOT: vector.insert +// CHECK: return %[[CST]] +func.func @insert_fold_same_rank(%v: vector<2x2xf32>) -> vector<2x2xf32> { + %cst = arith.constant dense<0.000000e+00> : vector<2x2xf32> + %0 = vector.insert %cst, %v [] : vector<2x2xf32> into vector<2x2xf32> + return %0 : vector<2x2xf32> +} + +// ----- + +// CHECK-LABEL: func @insert_no_fold_scalar_to_0d( +// CHECK-SAME: %[[v:.*]]: vector) +// CHECK: %[[extract:.*]] = vector.insert %{{.*}}, %[[v]] [] : f32 into vector +// CHECK: return %[[extract]] +func.func @insert_no_fold_scalar_to_0d(%v: vector) -> vector { + %cst = arith.constant 0.000000e+00 : f32 + %0 = vector.insert %cst, %v [] : f32 into vector + return %0 : vector +} + +// ----- + // CHECK-LABEL: dont_fold_expand_collapse // CHECK: %[[A:.*]] = vector.shape_cast %{{.*}} : vector<1x1x64xf32> to vector<1x1x8x8xf32> // CHECK: %[[B:.*]] = vector.shape_cast %{{.*}} : vector<1x1x8x8xf32> to vector<8x8xf32> @@ -2606,17 +2643,6 @@ func.func @rank_1_shuffle_to_interleave(%arg0: vector<6xi32>, %arg1: vector<6xi3 // ----- -// CHECK-LABEL: func @extract_from_0d_regression( -// CHECK-SAME: %[[v:.*]]: vector) -// CHECK: %[[extract:.*]] = vector.extract %[[v]][] : f32 from vector -// CHECK: return %[[extract]] -func.func @extract_from_0d_regression(%v: vector) -> f32 { - %0 = vector.extract %v[] : f32 from vector - return %0 : f32 -} - -// ----- - // CHECK-LABEL: func @extract_from_0d_splat_broadcast_regression( // CHECK-SAME: %[[a:.*]]: f32, %[[b:.*]]: vector, %[[c:.*]]: vector<2xf32>) func.func @extract_from_0d_splat_broadcast_regression(%a: f32, %b: vector, %c: vector<2xf32>) -> (f32, f32, f32, f32, f32, vector<6x7xf32>, vector<3xf32>) { diff --git a/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir b/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir new file mode 100644 index 0000000000000000000000000000000000000000..7ecbad7968225d036d61e46510f87d524a29c530 --- /dev/null +++ b/mlir/test/Dialect/Vector/vector-emulate-narrow-type-unaligned.mlir @@ -0,0 +1,67 @@ +// RUN: mlir-opt --test-emulate-narrow-int="arith-compute-bitwidth=1 memref-load-bitwidth=8" --cse --split-input-file %s | FileCheck %s + +func.func @vector_load_i2(%arg1: index, %arg2: index) -> vector<3x3xi2> { + %0 = memref.alloc() : memref<3x3xi2> + %c0 = arith.constant 0 : index + %c2 = arith.constant 2 : index + %cst = arith.constant dense<0> : vector<3x3xi2> + %1 = vector.load %0[%c2, %c0] : memref<3x3xi2>, vector<3xi2> + %2 = vector.insert %1, %cst [0] : vector<3xi2> into vector<3x3xi2> + return %2 : vector<3x3xi2> +} + +// CHECK: func @vector_load_i2 +// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<3xi8> +// CHECK: %[[INDEX:.+]] = arith.constant 1 : index +// CHECK: %[[VEC:.+]] = vector.load %[[ALLOC]][%[[INDEX]]] : memref<3xi8>, vector<2xi8> +// CHECK: %[[VEC_I2:.+]] = vector.bitcast %[[VEC]] : vector<2xi8> to vector<8xi2> +// CHECK: %[[EXCTRACT:.+]] = vector.extract_strided_slice %[[VEC_I2]] {offsets = [2], sizes = [3], strides = [1]} : vector<8xi2> to vector<3xi2> + +//----- + +func.func @vector_transfer_read_i2() -> vector<3xi2> { + %0 = memref.alloc() : memref<3x3xi2> + %c0i2 = arith.constant 0 : i2 + %c0 = arith.constant 0 : index + %c2 = arith.constant 2 : index + %1 = vector.transfer_read %0[%c2, %c0], %c0i2 {in_bounds = [true]} : memref<3x3xi2>, vector<3xi2> + return %1 : vector<3xi2> +} + +// CHECK: func @vector_transfer_read_i2 +// CHECK: %[[ALLOC:.+]] = memref.alloc() : memref<3xi8> +// CHECK: %[[INDEX:.+]] = arith.constant 1 : index +// CHECK: %[[READ:.+]] = vector.transfer_read %[[ALLOC]][%[[INDEX]]], %0 : memref<3xi8>, vector<2xi8> +// CHECK: %[[BITCAST:.+]] = vector.bitcast %[[READ]] : vector<2xi8> to vector<8xi2> +// CHECK: vector.extract_strided_slice %[[BITCAST]] {offsets = [2], sizes = [3], strides = [1]} : vector<8xi2> to vector<3xi2> + +//----- + +func.func @vector_cst_maskedload_i2(%passthru: vector<5xi2>) -> vector<3x5xi2> { + %0 = memref.alloc() : memref<3x5xi2> + %cst = arith.constant dense<0> : vector<3x5xi2> + %mask = vector.constant_mask [3] : vector<5xi1> + %c0 = arith.constant 0 : index + %c2 = arith.constant 2 : index + %1 = vector.maskedload %0[%c2, %c0], %mask, %passthru : + memref<3x5xi2>, vector<5xi1>, vector<5xi2> into vector<5xi2> + %2 = vector.insert %1, %cst [0] : vector<5xi2> into vector<3x5xi2> + return %2 : vector<3x5xi2> +} + +// CHECK: func @vector_cst_maskedload_i2 +// CHECK: %[[ORIGINMASK:.+]] = vector.constant_mask [3] : vector<5xi1> +// CHECK: %[[NEWMASK:.+]] = arith.constant dense : vector<2xi1> +// CHECK: %[[VESSEL:.+]] = arith.constant dense<0> : vector<8xi2> +// CHECK: %[[INSERT1:.+]] = vector.insert_strided_slice %arg0, %[[VESSEL]] +// CHECK-SAME: {offsets = [2], strides = [1]} : vector<5xi2> into vector<8xi2> +// CHECK: %[[BITCAST1:.+]] = vector.bitcast %[[INSERT1]] : vector<8xi2> to vector<2xi8> +// CHECK: %[[C2:.+]] = arith.constant 2 : index +// CHECK: %[[MASKEDLOAD:.+]] = vector.maskedload %alloc[%[[C2]]], %[[NEWMASK:.+]], %[[BITCAST1]] +// CHECK-SAME: : memref<4xi8>, vector<2xi1>, vector<2xi8> into vector<2xi8> +// CHECK: %[[BITCAST2:.+]] = vector.bitcast %[[MASKEDLOAD]] : vector<2xi8> to vector<8xi2> +// CHECK: %[[CST2:.+]] = arith.constant dense : vector<8xi1> +// CHECK: %[[INSERT2:.+]] = vector.insert_strided_slice %[[ORIGINMASK]], %[[CST2]] +// CHECK-SAME: {offsets = [2], strides = [1]} : vector<5xi1> into vector<8xi1> +// CHECK: %[[SELECT:.+]] = arith.select %[[INSERT2]], %[[BITCAST2]], %[[INSERT1]] : vector<8xi1>, vector<8xi2> +// CHECK: vector.extract_strided_slice %[[SELECT]] {offsets = [2], sizes = [5], strides = [1]} : vector<8xi2> to vector<5xi2> diff --git a/mlir/test/Target/LLVMIR/openmp-reduction.mlir b/mlir/test/Target/LLVMIR/openmp-reduction.mlir index 6d74a925b87b5c9289080198f6d906b9b616ba90..11c8559044be025da2c05e04b8b2effc0bc62a76 100644 --- a/mlir/test/Target/LLVMIR/openmp-reduction.mlir +++ b/mlir/test/Target/LLVMIR/openmp-reduction.mlir @@ -586,3 +586,83 @@ llvm.func @parallel_nested_workshare_reduction(%ub : i64) { // Reduction function. // CHECK: define internal void @[[REDFUNC]] // CHECK: add i32 + +// ----- + +omp.declare_reduction @add_f32 : f32 +init { +^bb0(%arg: f32): + %0 = llvm.mlir.constant(0.0 : f32) : f32 + omp.yield (%0 : f32) +} +combiner { +^bb1(%arg0: f32, %arg1: f32): + %1 = llvm.fadd %arg0, %arg1 : f32 + omp.yield (%1 : f32) +} +atomic { +^bb2(%arg2: !llvm.ptr, %arg3: !llvm.ptr): + %2 = llvm.load %arg3 : !llvm.ptr -> f32 + llvm.atomicrmw fadd %arg2, %2 monotonic : !llvm.ptr, f32 + omp.yield +} + +// CHECK-LABEL: @wsloop_simd_reduction +llvm.func @wsloop_simd_reduction(%lb : i64, %ub : i64, %step : i64) { + %c1 = llvm.mlir.constant(1 : i32) : i32 + %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr + omp.parallel { + omp.wsloop reduction(@add_f32 %0 -> %prv1 : !llvm.ptr) { + omp.simd reduction(@add_f32 %prv1 -> %prv2 : !llvm.ptr) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + %1 = llvm.mlir.constant(2.0 : f32) : f32 + %2 = llvm.load %prv2 : !llvm.ptr -> f32 + %3 = llvm.fadd %1, %2 : f32 + llvm.store %3, %prv2 : f32, !llvm.ptr + omp.yield + } + } {omp.composite} + } {omp.composite} + omp.terminator + } + llvm.return +} + +// Same checks as for wsloop reduction, because currently omp.simd is ignored in +// a composite 'do/for simd' construct. +// Call to the outlined function. +// CHECK: call void {{.*}} @__kmpc_fork_call +// CHECK-SAME: @[[OUTLINED:[A-Za-z_.][A-Za-z0-9_.]*]] + +// Outlined function. +// CHECK: define internal void @[[OUTLINED]] + +// Private reduction variable and its initialization. +// CHECK: %[[PRIVATE:.+]] = alloca float +// CHECK: store float 0.000000e+00, ptr %[[PRIVATE]] + +// Call to the reduction function. +// CHECK: call i32 @__kmpc_reduce +// CHECK-SAME: @[[REDFUNC:[A-Za-z_.][A-Za-z0-9_.]*]] + +// Atomic reduction. +// CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]] +// CHECK: atomicrmw fadd ptr %{{.*}}, float %[[PARTIAL]] + +// Non-atomic reduction: +// CHECK: fadd float +// CHECK: call void @__kmpc_end_reduce +// CHECK: br label %[[FINALIZE:.+]] + +// CHECK: [[FINALIZE]]: +// CHECK: call void @__kmpc_barrier + +// Update of the private variable using the reduction region +// (the body block currently comes after all the other blocks). +// CHECK: %[[PARTIAL:.+]] = load float, ptr %[[PRIVATE]] +// CHECK: %[[UPDATED:.+]] = fadd float 2.000000e+00, %[[PARTIAL]] +// CHECK: store float %[[UPDATED]], ptr %[[PRIVATE]] + +// Reduction function. +// CHECK: define internal void @[[REDFUNC]] +// CHECK: fadd float diff --git a/mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir b/mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir index 6e8f0162e505d065544f797378c433ae52783268..031442b0ee2daf0d3c6c5f220944e01a78012821 100644 --- a/mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir +++ b/mlir/test/Transforms/test-legalize-erased-op-with-uses.mlir @@ -3,7 +3,7 @@ // Test that an error is emitted when an operation is marked as "erased", but // has users that live across the conversion. func.func @remove_all_ops(%arg0: i32) -> i32 { - // expected-error@below {{failed to legalize unresolved materialization from () to 'i32' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from () to ('i32') that remained live after conversion}} %0 = "test.illegal_op_a"() : () -> i32 // expected-note@below {{see existing live user here}} return %0 : i32 diff --git a/mlir/test/Transforms/test-legalize-type-conversion.mlir b/mlir/test/Transforms/test-legalize-type-conversion.mlir index f130adff42f8cdd3e85a3be088aeb6756666592f..db8bd0f6378d29bb6e562f186f8161f48632b377 100644 --- a/mlir/test/Transforms/test-legalize-type-conversion.mlir +++ b/mlir/test/Transforms/test-legalize-type-conversion.mlir @@ -2,7 +2,7 @@ func.func @test_invalid_arg_materialization( - // expected-error@below {{failed to legalize unresolved materialization from () to 'i16' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from () to ('i16') that remained live after conversion}} %arg0: i16) { // expected-note@below{{see existing live user here}} "foo.return"(%arg0) : (i16) -> () @@ -21,7 +21,7 @@ func.func @test_valid_arg_materialization(%arg0: i64) { // ----- func.func @test_invalid_result_materialization() { - // expected-error@below {{failed to legalize unresolved materialization from ('f64') to 'f16' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from ('f64') to ('f16') that remained live after conversion}} %result = "test.type_producer"() : () -> f16 // expected-note@below{{see existing live user here}} "foo.return"(%result) : (f16) -> () @@ -30,7 +30,7 @@ func.func @test_invalid_result_materialization() { // ----- func.func @test_invalid_result_materialization() { - // expected-error@below {{failed to legalize unresolved materialization from ('f64') to 'f16' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from ('f64') to ('f16') that remained live after conversion}} %result = "test.type_producer"() : () -> f16 // expected-note@below{{see existing live user here}} "foo.return"(%result) : (f16) -> () @@ -50,7 +50,7 @@ func.func @test_transitive_use_materialization() { // ----- func.func @test_transitive_use_invalid_materialization() { - // expected-error@below {{failed to legalize unresolved materialization from ('f64') to 'f16' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from ('f64') to ('f16') that remained live after conversion}} %result = "test.another_type_producer"() : () -> f16 // expected-note@below{{see existing live user here}} "foo.return"(%result) : (f16) -> () @@ -102,7 +102,7 @@ func.func @test_block_argument_not_converted() { // Make sure argument type changes aren't implicitly forwarded. func.func @test_signature_conversion_no_converter() { "test.signature_conversion_no_converter"() ({ - // expected-error@below {{failed to legalize unresolved materialization from ('f64') to 'f32' that remained live after conversion}} + // expected-error@below {{failed to legalize unresolved materialization from ('f64') to ('f32') that remained live after conversion}} ^bb0(%arg0: f32): "test.type_consumer"(%arg0) : (f32) -> () // expected-note@below{{see existing live user here}} diff --git a/mlir/test/lib/Dialect/Func/TestDecomposeCallGraphTypes.cpp b/mlir/test/lib/Dialect/Func/TestDecomposeCallGraphTypes.cpp index 92216da9f201e6d2e5729d23e36511144101ae86..de511c58ae6ee0f45132f854b2880c7589dc1c5c 100644 --- a/mlir/test/lib/Dialect/Func/TestDecomposeCallGraphTypes.cpp +++ b/mlir/test/lib/Dialect/Func/TestDecomposeCallGraphTypes.cpp @@ -21,23 +21,40 @@ namespace { /// given tuple value. If some tuple elements are, in turn, tuples, the elements /// of those are extracted recursively such that the returned values have the /// same types as `resultTypes.getFlattenedTypes()`. -static LogicalResult buildDecomposeTuple(OpBuilder &builder, Location loc, - TupleType resultType, Value value, - SmallVectorImpl &values) { - for (unsigned i = 0, e = resultType.size(); i < e; ++i) { - Type elementType = resultType.getType(i); - Value element = builder.create( - loc, elementType, value, builder.getI32IntegerAttr(i)); - if (auto nestedTupleType = dyn_cast(elementType)) { - // Recurse if the current element is also a tuple. - if (failed(buildDecomposeTuple(builder, loc, nestedTupleType, element, - values))) - return failure(); - } else { - values.push_back(element); +static SmallVector buildDecomposeTuple(OpBuilder &builder, + TypeRange resultTypes, + ValueRange inputs, Location loc) { + // Skip materialization if the single input value is not a tuple. + if (inputs.size() != 1) + return {}; + Value tuple = inputs.front(); + auto tupleType = dyn_cast(tuple.getType()); + if (!tupleType) + return {}; + // Skip materialization if the flattened types do not match the requested + // result types. + SmallVector flattenedTypes; + tupleType.getFlattenedTypes(flattenedTypes); + if (TypeRange(resultTypes) != TypeRange(flattenedTypes)) + return {}; + // Recursively decompose the tuple. + SmallVector result; + std::function decompose = [&](Value tuple) { + auto tupleType = dyn_cast(tuple.getType()); + if (!tupleType) { + // This is not a tuple. + result.push_back(tuple); + return; } - } - return success(); + for (unsigned i = 0, e = tupleType.size(); i < e; ++i) { + Type elementType = tupleType.getType(i); + Value element = builder.create( + loc, elementType, tuple, builder.getI32IntegerAttr(i)); + decompose(element); + } + }; + decompose(tuple); + return result; } /// Creates a `test.make_tuple` op out of the given inputs building a tuple of @@ -82,8 +99,8 @@ static Value buildMakeTupleOp(OpBuilder &builder, TupleType resultType, /// A pass for testing call graph type decomposition. /// -/// This instantiates the patterns with a TypeConverter and ValueDecomposer -/// that splits tuple types into their respective element types. +/// This instantiates the patterns with a TypeConverter that splits tuple types +/// into their respective element types. /// For example, `tuple --> T1, T2, T3`. struct TestDecomposeCallGraphTypes : public PassWrapper> { @@ -123,12 +140,9 @@ struct TestDecomposeCallGraphTypes return success(); }); typeConverter.addArgumentMaterialization(buildMakeTupleOp); + typeConverter.addTargetMaterialization(buildDecomposeTuple); - ValueDecomposer decomposer; - decomposer.addDecomposeValueConversion(buildDecomposeTuple); - - populateDecomposeCallGraphTypesPatterns(context, typeConverter, decomposer, - patterns); + populateDecomposeCallGraphTypesPatterns(context, typeConverter, patterns); if (failed(applyPartialConversion(module, target, std::move(patterns)))) return signalPassFailure(); diff --git a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp index 411a98a48bfb28ba0284f201e4085d6435fc2fc5..525c8d6d3e89bc95d85a9934f400affabae30196 100644 --- a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp +++ b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp @@ -76,7 +76,7 @@ static IndicesTy getOverloadableTypeIdxs(const Record &record, case llvm::MVT::iAny: case llvm::MVT::fAny: case llvm::MVT::Any: - case llvm::MVT::iPTRAny: + case llvm::MVT::pAny: case llvm::MVT::vAny: overloadedOps.set(r.index()); break; diff --git a/mlir/utils/spirv/gen_spirv_dialect.py b/mlir/utils/spirv/gen_spirv_dialect.py index 2fb540ef103250be20f7bb81e9db1a49411dcc97..99ed3489b4cbda691ddf23a9c448280444b0f875 100755 --- a/mlir/utils/spirv/gen_spirv_dialect.py +++ b/mlir/utils/spirv/gen_spirv_dialect.py @@ -127,44 +127,6 @@ def split_list_into_sublists(items): return chuncks -def uniquify_enum_cases(lst): - """Prunes duplicate enum cases from the list. - - Arguments: - - lst: List whose elements are to be uniqued. Assumes each element is a - (symbol, value) pair and elements already sorted according to value. - - Returns: - - A list with all duplicates removed. The elements are sorted according to - value and, for each value, uniqued according to symbol. - original list, - - A map from deduplicated cases to the uniqued case. - """ - cases = lst - uniqued_cases = [] - duplicated_cases = {} - - # First sort according to the value - cases.sort(key=lambda x: x[1]) - - # Then group them according to the value - for _, groups in itertools.groupby(cases, key=lambda x: x[1]): - # For each value, sort according to the enumerant symbol. - sorted_group = sorted(groups, key=lambda x: x[0]) - # Keep the "smallest" case, which is typically the symbol without extension - # suffix. But we have special cases that we want to fix. - case = sorted_group[0] - for i in range(1, len(sorted_group)): - duplicated_cases[sorted_group[i][0]] = case[0] - if case[0] == "HlslSemanticGOOGLE": - assert len(sorted_group) == 2, "unexpected new variant for HlslSemantic" - case = sorted_group[1] - duplicated_cases[sorted_group[0][0]] = case[0] - uniqued_cases.append(case) - - return uniqued_cases, duplicated_cases - - def toposort(dag, sort_fn): """Topologically sorts the given dag. @@ -197,14 +159,12 @@ def toposort(dag, sort_fn): return sorted_nodes -def toposort_capabilities(all_cases, capability_mapping): +def toposort_capabilities(all_cases): """Returns topologically sorted capability (symbol, value) pairs. Arguments: - all_cases: all capability cases (containing symbol, value, and implied capabilities). - - capability_mapping: mapping from duplicated capability symbols to the - canonicalized symbol chosen for SPIRVBase.td. Returns: A list containing topologically sorted capability (symbol, value) pairs. @@ -215,13 +175,10 @@ def toposort_capabilities(all_cases, capability_mapping): # Get the current capability. cur = case["enumerant"] name_to_value[cur] = case["value"] - # Ignore duplicated symbols. - if cur in capability_mapping: - continue # Get capabilities implied by the current capability. prev = case.get("capabilities", []) - uniqued_prev = set([capability_mapping.get(c, c) for c in prev]) + uniqued_prev = set(prev) dag[cur] = uniqued_prev sorted_caps = toposort(dag, lambda x: name_to_value[x]) @@ -229,36 +186,12 @@ def toposort_capabilities(all_cases, capability_mapping): return [(c, name_to_value[c]) for c in sorted_caps] -def get_capability_mapping(operand_kinds): - """Returns the capability mapping from duplicated cases to canonicalized ones. - - Arguments: - - operand_kinds: all operand kinds' grammar spec - - Returns: - - A map mapping from duplicated capability symbols to the canonicalized - symbol chosen for SPIRVBase.td. - """ - # Find the operand kind for capability - cap_kind = {} - for kind in operand_kinds: - if kind["kind"] == "Capability": - cap_kind = kind - - kind_cases = [(case["enumerant"], case["value"]) for case in cap_kind["enumerants"]] - _, capability_mapping = uniquify_enum_cases(kind_cases) - - return capability_mapping - - -def get_availability_spec(enum_case, capability_mapping, for_op, for_cap): +def get_availability_spec(enum_case, for_op, for_cap): """Returns the availability specification string for the given enum case. Arguments: - enum_case: the enum case to generate availability spec for. It may contain 'version', 'lastVersion', 'extensions', or 'capabilities'. - - capability_mapping: mapping from duplicated capability symbols to the - canonicalized symbol chosen for SPIRVBase.td. - for_op: bool value indicating whether this is the availability spec for an op itself. - for_cap: bool value indicating whether this is the availability spec for @@ -313,10 +246,7 @@ def get_availability_spec(enum_case, capability_mapping, for_op, for_cap): if caps: canonicalized_caps = [] for c in caps: - if c in capability_mapping: - canonicalized_caps.append(capability_mapping[c]) - else: - canonicalized_caps.append(c) + canonicalized_caps.append(c) prefixed_caps = [ "SPIRV_C_{}".format(c) for c in sorted(set(canonicalized_caps)) ] @@ -357,7 +287,7 @@ def get_availability_spec(enum_case, capability_mapping, for_op, for_cap): return "{}{}{}".format(implies, "\n " if implies and avail else "", avail) -def gen_operand_kind_enum_attr(operand_kind, capability_mapping): +def gen_operand_kind_enum_attr(operand_kind): """Generates the TableGen EnumAttr definition for the given operand kind. Returns: @@ -388,13 +318,12 @@ def gen_operand_kind_enum_attr(operand_kind, capability_mapping): # Special treatment for capability cases: we need to sort them topologically # because a capability can refer to another via the 'implies' field. kind_cases = toposort_capabilities( - operand_kind["enumerants"], capability_mapping + operand_kind["enumerants"] ) else: kind_cases = [ (case["enumerant"], case["value"]) for case in operand_kind["enumerants"] ] - kind_cases, _ = uniquify_enum_cases(kind_cases) max_len = max([len(symbol) for (symbol, _) in kind_cases]) # Generate the definition for each enum case @@ -412,7 +341,6 @@ def gen_operand_kind_enum_attr(operand_kind, capability_mapping): value = int(case_pair[1]) avail = get_availability_spec( name_to_case_dict[name], - capability_mapping, False, kind_name == "Capability", ) @@ -648,11 +576,9 @@ def update_td_enum_attrs(path, operand_kinds, filter_list): ] filter_list.extend(existing_kinds) - capability_mapping = get_capability_mapping(operand_kinds) - # Generate definitions for all enums in filter list defs = [ - gen_operand_kind_enum_attr(kind, capability_mapping) + gen_operand_kind_enum_attr(kind) for kind in operand_kinds if kind["kind"] in filter_list ] @@ -762,7 +688,7 @@ def get_description(text, appendix): def get_op_definition( - instruction, opname, doc, existing_info, capability_mapping, settings + instruction, opname, doc, existing_info, settings ): """Generates the TableGen op definition for the given SPIR-V instruction. @@ -771,8 +697,6 @@ def get_op_definition( - doc: the instruction's SPIR-V HTML doc - existing_info: a dict containing potential manually specified sections for this instruction - - capability_mapping: mapping from duplicated capability symbols to the - canonicalized symbol chosen for SPIRVBase.td Returns: - A string containing the TableGen op definition @@ -840,7 +764,7 @@ def get_op_definition( operands = instruction.get("operands", []) # Op availability - avail = get_availability_spec(instruction, capability_mapping, True, False) + avail = get_availability_spec(instruction, True, False) if avail: avail = "\n\n {0}".format(avail) @@ -989,6 +913,7 @@ def extract_td_op_info(op_def): op_tmpl_params, _ = get_string_between_nested(op_def, "<", ">") opstringname, rest = get_string_between(op_tmpl_params, '"', '"') category_args = rest.split("[", 1)[0] + category_args = category_args.rsplit(",", 1)[0] # Get traits traits, _ = get_string_between_nested(rest, "[", "]") @@ -1020,7 +945,7 @@ def extract_td_op_info(op_def): def update_td_op_definitions( - path, instructions, docs, filter_list, inst_category, capability_mapping, settings + path, instructions, docs, filter_list, inst_category, settings ): """Updates SPIRVOps.td with newly generated op definition. @@ -1029,8 +954,6 @@ def update_td_op_definitions( - instructions: SPIR-V JSON grammar for all instructions - docs: SPIR-V HTML doc for all instructions - filter_list: a list containing new opnames to include - - capability_mapping: mapping from duplicated capability symbols to the - canonicalized symbol chosen for SPIRVBase.td. Returns: - A string containing all the TableGen op definitions @@ -1078,7 +1001,6 @@ def update_td_op_definitions( opname, docs[fixed_opname], op_info_dict.get(opname, {"inst_category": inst_category}), - capability_mapping, settings, ) ) @@ -1185,14 +1107,12 @@ if __name__ == "__main__": if args.new_inst is not None: assert args.op_td_path is not None docs = get_spirv_doc_from_html_spec(ext_html_url, args) - capability_mapping = get_capability_mapping(operand_kinds) update_td_op_definitions( args.op_td_path, instructions, docs, args.new_inst, args.inst_category, - capability_mapping, args, ) print("Done. Note that this script just generates a template; ", end="") diff --git a/offload/plugins-nextgen/amdgpu/src/rtl.cpp b/offload/plugins-nextgen/amdgpu/src/rtl.cpp index f0cc0c2e4d08e54673e56d7a0135c59fbb6a8234..bdb33d4f4ab27c41d33e85e5ed234b699a2848e7 100644 --- a/offload/plugins-nextgen/amdgpu/src/rtl.cpp +++ b/offload/plugins-nextgen/amdgpu/src/rtl.cpp @@ -927,6 +927,8 @@ private: AMDGPUSignalManagerTy *SignalManager; }; + using AMDGPUStreamCallbackTy = Error(void *Data); + /// The stream is composed of N stream's slots. The struct below represents /// the fields of each slot. Each slot has a signal and an optional action /// function. When appending an HSA asynchronous operation to the stream, one @@ -942,65 +944,82 @@ private: /// operation as input signal. AMDGPUSignalTy *Signal; - /// The action that must be performed after the operation's completion. Set + /// The actions that must be performed after the operation's completion. Set /// to nullptr when there is no action to perform. - Error (*ActionFunction)(void *); + llvm::SmallVector Callbacks; /// Space for the action's arguments. A pointer to these arguments is passed /// to the action function. Notice the space of arguments is limited. - union { + union ActionArgsTy { MemcpyArgsTy MemcpyArgs; ReleaseBufferArgsTy ReleaseBufferArgs; ReleaseSignalArgsTy ReleaseSignalArgs; - } ActionArgs; + void *CallbackArgs; + }; + + llvm::SmallVector ActionArgs; /// Create an empty slot. - StreamSlotTy() : Signal(nullptr), ActionFunction(nullptr) {} + StreamSlotTy() : Signal(nullptr), Callbacks({}), ActionArgs({}) {} /// Schedule a host memory copy action on the slot. Error schedHostMemoryCopy(void *Dst, const void *Src, size_t Size) { - ActionFunction = memcpyAction; - ActionArgs.MemcpyArgs = MemcpyArgsTy{Dst, Src, Size}; + Callbacks.emplace_back(memcpyAction); + ActionArgs.emplace_back().MemcpyArgs = MemcpyArgsTy{Dst, Src, Size}; return Plugin::success(); } /// Schedule a release buffer action on the slot. Error schedReleaseBuffer(void *Buffer, AMDGPUMemoryManagerTy &Manager) { - ActionFunction = releaseBufferAction; - ActionArgs.ReleaseBufferArgs = ReleaseBufferArgsTy{Buffer, &Manager}; + Callbacks.emplace_back(releaseBufferAction); + ActionArgs.emplace_back().ReleaseBufferArgs = + ReleaseBufferArgsTy{Buffer, &Manager}; return Plugin::success(); } /// Schedule a signal release action on the slot. Error schedReleaseSignal(AMDGPUSignalTy *SignalToRelease, AMDGPUSignalManagerTy *SignalManager) { - ActionFunction = releaseSignalAction; - ActionArgs.ReleaseSignalArgs = + Callbacks.emplace_back(releaseSignalAction); + ActionArgs.emplace_back().ReleaseSignalArgs = ReleaseSignalArgsTy{SignalToRelease, SignalManager}; return Plugin::success(); } + /// Register a callback to be called on compleition + Error schedCallback(AMDGPUStreamCallbackTy *Func, void *Data) { + Callbacks.emplace_back(Func); + ActionArgs.emplace_back().CallbackArgs = Data; + + return Plugin::success(); + } + // Perform the action if needed. Error performAction() { - if (!ActionFunction) + if (Callbacks.empty()) return Plugin::success(); - // Perform the action. - if (ActionFunction == memcpyAction) { - if (auto Err = memcpyAction(&ActionArgs)) - return Err; - } else if (ActionFunction == releaseBufferAction) { - if (auto Err = releaseBufferAction(&ActionArgs)) - return Err; - } else if (ActionFunction == releaseSignalAction) { - if (auto Err = releaseSignalAction(&ActionArgs)) - return Err; - } else { - return Plugin::error("Unknown action function!"); + assert(Callbacks.size() == ActionArgs.size() && "Size mismatch"); + for (auto [Callback, ActionArg] : llvm::zip(Callbacks, ActionArgs)) { + // Perform the action. + if (Callback == memcpyAction) { + if (auto Err = memcpyAction(&ActionArg)) + return Err; + } else if (Callback == releaseBufferAction) { + if (auto Err = releaseBufferAction(&ActionArg)) + return Err; + } else if (Callback == releaseSignalAction) { + if (auto Err = releaseSignalAction(&ActionArg)) + return Err; + } else if (Callback) { + if (auto Err = Callback(ActionArg.CallbackArgs)) + return Err; + } } // Invalidate the action. - ActionFunction = nullptr; + Callbacks.clear(); + ActionArgs.clear(); return Plugin::success(); } diff --git a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel index db928deb170602d5c530acde240dafef5ce74401..5e756e2ed9629fc7c25ca2faec4ab29262c02827 100644 --- a/utils/bazel/llvm-project-overlay/clang/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/clang/BUILD.bazel @@ -364,6 +364,20 @@ gentbl( ], ) +gentbl( + name="basic_builtins_x86_gen", + tbl_outs = [( + "-gen-clang-builtins", + "include/clang/Basic/BuiltinsX86.inc", + )], + tblgen = ":clang-tblgen", + td_file = "include/clang/Basic/BuiltinsX86.td", + td_srcs = [ + "include/clang/Basic/BuiltinsX86.td", + "include/clang/Basic/BuiltinsBase.td", + ], +) + gentbl( name = "basic_builtins_gen", tbl_outs = [( @@ -701,6 +715,7 @@ cc_library( ":basic_builtins_bpf_gen", ":basic_builtins_gen", ":basic_builtins_riscv_gen", + ":basic_builtins_x86_gen", ":basic_internal_headers", ":basic_riscv_sifive_vector_builtins_gen", ":basic_riscv_vector_builtin_cg_gen", diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 1956233590f728dc817f1ca67c3b151adf3a1e51..820163415f98b552cb9bd9fc9dd9a6116b297b86 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -215,6 +215,7 @@ libc_support_library( libc_support_library( name = "types_mode_t", hdrs = ["hdr/types/mode_t.h"], + deps = [":hdr_fcntl_overlay"], ) libc_support_library( @@ -1701,6 +1702,17 @@ libc_support_library( ], ) +libc_support_library( + name = "sincosf16_utils", + hdrs = ["src/math/generic/sincosf16_utils.h"], + deps = [ + ":__support_common", + ":__support_fputil_fp_bits", + ":__support_fputil_nearest_integer", + ":__support_fputil_polyeval", + ], +) + libc_support_library( name = "explogxf", srcs = ["src/math/generic/explogxf.cpp"], @@ -1772,6 +1784,18 @@ libc_support_library( ], ) +libc_support_library( + name = "expxf16", + hdrs = ["src/math/generic/expxf16.h"], + deps = [ + ":__support_cpp_array", + ":__support_fputil_cast", + ":__support_fputil_fp_bits", + ":__support_fputil_nearest_integer", + ":__support_fputil_polyeval", + ], +) + ################################ math targets ################################## libc_math_function( @@ -1881,6 +1905,8 @@ libc_math_function(name = "canonicalizel") libc_math_function(name = "canonicalizef128") +libc_math_function(name = "canonicalizef16") + libc_math_function( name = "cbrt", additional_deps = [ @@ -1905,6 +1931,8 @@ libc_math_function(name = "ceill") libc_math_function(name = "ceilf128") +libc_math_function(name = "ceilf16") + libc_math_function(name = "copysign") libc_math_function(name = "copysignf") @@ -1913,6 +1941,8 @@ libc_math_function(name = "copysignl") libc_math_function(name = "copysignf128") +libc_math_function(name = "copysignf16") + libc_math_function( name = "cos", additional_deps = [ @@ -1949,6 +1979,13 @@ libc_math_function( ], ) +libc_math_function( + name = "coshf16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function( name = "cospif", additional_deps = [ @@ -1964,6 +2001,15 @@ libc_math_function( ], ) +libc_math_function( + name = "cospif16", + additional_deps = [ + ":__support_fputil_multiply_add", + ":__support_macros_optimization", + ":sincosf16_utils", + ], +) + libc_math_function(name = "daddl") libc_math_function(name = "daddf128") @@ -2047,6 +2093,13 @@ libc_math_function( ], ) +libc_math_function( + name = "expf16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function( name = "exp10", additional_deps = [ @@ -2071,6 +2124,20 @@ libc_math_function( ], ) +libc_math_function( + name = "exp10f16", + additional_deps = [ + ":expxf16", + ], +) + +libc_math_function( + name = "exp10m1f16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function( name = "exp2", additional_deps = [ @@ -2095,6 +2162,13 @@ libc_math_function( ], ) +libc_math_function( + name = "exp2f16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function( name = "exp2m1f", additional_deps = [ @@ -2103,6 +2177,13 @@ libc_math_function( ], ) +libc_math_function( + name = "exp2m1f16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function( name = "expm1", additional_deps = [ @@ -2134,6 +2215,101 @@ libc_math_function( ], ) +libc_math_function( + name = "expm1f16", + additional_deps = [ + ":expxf16", + ], +) + +libc_math_function(name = "f16add") + +libc_math_function(name = "f16addf") + +libc_math_function(name = "f16addf128") + +libc_math_function(name = "f16addl") + +libc_math_function(name = "f16div") + +libc_math_function(name = "f16divf") + +libc_math_function(name = "f16divf128") + +libc_math_function(name = "f16divl") + +libc_math_function( + name = "f16fma", + additional_deps = [ + ":__support_fputil_fma", + ], +) + +libc_math_function( + name = "f16fmaf", + additional_deps = [ + ":__support_fputil_fma", + ], +) + +libc_math_function( + name = "f16fmaf128", + additional_deps = [ + ":__support_fputil_fma", + ], +) + +libc_math_function( + name = "f16fmal", + additional_deps = [ + ":__support_fputil_fma", + ], +) + +libc_math_function(name = "f16mul") + +libc_math_function(name = "f16mulf") + +libc_math_function(name = "f16mulf128") + +libc_math_function(name = "f16mull") + +libc_math_function( + name = "f16sqrt", + additional_deps = [ + ":__support_fputil_sqrt", + ], +) + +libc_math_function( + name = "f16sqrtf", + additional_deps = [ + ":__support_fputil_sqrt", + ], +) + +libc_math_function( + name = "f16sqrtf128", + additional_deps = [ + ":__support_fputil_sqrt", + ], +) + +libc_math_function( + name = "f16sqrtl", + additional_deps = [ + ":__support_fputil_sqrt", + ], +) + +libc_math_function(name = "f16sub") + +libc_math_function(name = "f16subf") + +libc_math_function(name = "f16subf128") + +libc_math_function(name = "f16subl") + libc_math_function(name = "fabs") libc_math_function(name = "fabsf") @@ -2142,6 +2318,8 @@ libc_math_function(name = "fabsl") libc_math_function(name = "fabsf128") +libc_math_function(name = "fabsf16") + libc_math_function(name = "fadd") libc_math_function(name = "faddl") @@ -2156,6 +2334,8 @@ libc_math_function(name = "fdiml") libc_math_function(name = "fdimf128") +libc_math_function(name = "fdimf16") + libc_math_function(name = "fdiv") libc_math_function(name = "fdivl") @@ -2191,6 +2371,8 @@ libc_math_function(name = "floorl") libc_math_function(name = "floorf128") +libc_math_function(name = "floorf16") + # TODO: Add fma, fmaf, fmal, fmaf128 functions. libc_math_function(name = "fmax") @@ -2201,6 +2383,8 @@ libc_math_function(name = "fmaxl") libc_math_function(name = "fmaxf128") +libc_math_function(name = "fmaxf16") + libc_math_function(name = "fmaximum") libc_math_function(name = "fmaximumf") @@ -2209,6 +2393,8 @@ libc_math_function(name = "fmaximuml") libc_math_function(name = "fmaximumf128") +libc_math_function(name = "fmaximumf16") + libc_math_function(name = "fmaximum_mag") libc_math_function(name = "fmaximum_magf") @@ -2217,6 +2403,8 @@ libc_math_function(name = "fmaximum_magl") libc_math_function(name = "fmaximum_magf128") +libc_math_function(name = "fmaximum_magf16") + libc_math_function(name = "fmaximum_mag_num") libc_math_function(name = "fmaximum_mag_numf") @@ -2225,6 +2413,8 @@ libc_math_function(name = "fmaximum_mag_numl") libc_math_function(name = "fmaximum_mag_numf128") +libc_math_function(name = "fmaximum_mag_numf16") + libc_math_function(name = "fmaximum_num") libc_math_function(name = "fmaximum_numf") @@ -2233,6 +2423,8 @@ libc_math_function(name = "fmaximum_numl") libc_math_function(name = "fmaximum_numf128") +libc_math_function(name = "fmaximum_numf16") + libc_math_function(name = "fmin") libc_math_function(name = "fminf") @@ -2241,6 +2433,8 @@ libc_math_function(name = "fminl") libc_math_function(name = "fminf128") +libc_math_function(name = "fminf16") + libc_math_function(name = "fminimum") libc_math_function(name = "fminimumf") @@ -2249,6 +2443,8 @@ libc_math_function(name = "fminimuml") libc_math_function(name = "fminimumf128") +libc_math_function(name = "fminimumf16") + libc_math_function(name = "fminimum_mag") libc_math_function(name = "fminimum_magf") @@ -2257,6 +2453,8 @@ libc_math_function(name = "fminimum_magl") libc_math_function(name = "fminimum_magf128") +libc_math_function(name = "fminimum_magf16") + libc_math_function(name = "fminimum_mag_num") libc_math_function(name = "fminimum_mag_numf") @@ -2265,6 +2463,8 @@ libc_math_function(name = "fminimum_mag_numl") libc_math_function(name = "fminimum_mag_numf128") +libc_math_function(name = "fminimum_mag_numf16") + libc_math_function(name = "fminimum_num") libc_math_function(name = "fminimum_numf") @@ -2273,6 +2473,8 @@ libc_math_function(name = "fminimum_numl") libc_math_function(name = "fminimum_numf128") +libc_math_function(name = "fminimum_numf16") + libc_math_function( name = "fmod", additional_deps = [ @@ -2301,6 +2503,13 @@ libc_math_function( ], ) +libc_math_function( + name = "fmodf16", + additional_deps = [ + ":__support_fputil_generic_fmod", + ], +) + libc_math_function( name = "fmul", additional_deps = [ @@ -2320,6 +2529,8 @@ libc_math_function(name = "frexpl") libc_math_function(name = "frexpf128") +libc_math_function(name = "frexpf16") + libc_math_function(name = "fromfp") libc_math_function(name = "fromfpf") @@ -2328,6 +2539,8 @@ libc_math_function(name = "fromfpl") libc_math_function(name = "fromfpf128") +libc_math_function(name = "fromfpf16") + libc_math_function(name = "fromfpx") libc_math_function(name = "fromfpxf") @@ -2336,6 +2549,8 @@ libc_math_function(name = "fromfpxl") libc_math_function(name = "fromfpxf128") +libc_math_function(name = "fromfpxf16") + libc_math_function( name = "fsqrt", additional_deps = [ @@ -2371,6 +2586,8 @@ libc_math_function(name = "getpayloadl") libc_math_function(name = "getpayloadf128") +libc_math_function(name = "getpayloadf16") + libc_math_function(name = "hypot") libc_math_function( @@ -2389,6 +2606,8 @@ libc_math_function(name = "ilogbl") libc_math_function(name = "ilogbf128") +libc_math_function(name = "ilogbf16") + libc_math_function(name = "ldexp") libc_math_function(name = "ldexpf") @@ -2397,6 +2616,8 @@ libc_math_function(name = "ldexpl") libc_math_function(name = "ldexpf128") +libc_math_function(name = "ldexpf16") + libc_math_function(name = "llogb") libc_math_function(name = "llogbf") @@ -2405,6 +2626,8 @@ libc_math_function(name = "llogbl") libc_math_function(name = "llogbf128") +libc_math_function(name = "llogbf16") + libc_math_function(name = "llrint") libc_math_function(name = "llrintf") @@ -2413,6 +2636,8 @@ libc_math_function(name = "llrintl") libc_math_function(name = "llrintf128") +libc_math_function(name = "llrintf16") + libc_math_function(name = "llround") libc_math_function(name = "llroundf") @@ -2421,6 +2646,8 @@ libc_math_function(name = "llroundl") libc_math_function(name = "llroundf128") +libc_math_function(name = "llroundf16") + libc_math_function( name = "log", additional_deps = [ @@ -2449,6 +2676,13 @@ libc_math_function( ], ) +libc_math_function( + name = "logf16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function( name = "log10", additional_deps = [ @@ -2477,6 +2711,13 @@ libc_math_function( ], ) +libc_math_function( + name = "log10f16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function( name = "log1p", additional_deps = [ @@ -2531,6 +2772,13 @@ libc_math_function( ], ) +libc_math_function( + name = "log2f16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function(name = "logb") libc_math_function(name = "logbf") @@ -2539,6 +2787,8 @@ libc_math_function(name = "logbl") libc_math_function(name = "logbf128") +libc_math_function(name = "logbf16") + libc_math_function(name = "lrint") libc_math_function(name = "lrintf") @@ -2547,6 +2797,8 @@ libc_math_function(name = "lrintl") libc_math_function(name = "lrintf128") +libc_math_function(name = "lrintf16") + libc_math_function(name = "lround") libc_math_function(name = "lroundf") @@ -2555,6 +2807,8 @@ libc_math_function(name = "lroundl") libc_math_function(name = "lroundf128") +libc_math_function(name = "lroundf16") + libc_math_function(name = "modf") libc_math_function(name = "modff") @@ -2563,6 +2817,8 @@ libc_math_function(name = "modfl") libc_math_function(name = "modff128") +libc_math_function(name = "modff16") + libc_math_function( name = "nan", additional_deps = [ @@ -2595,6 +2851,14 @@ libc_math_function( ], ) +libc_math_function( + name = "nanf16", + additional_deps = [ + ":__support_str_to_float", + ":errno", + ], +) + libc_math_function(name = "nearbyint") libc_math_function(name = "nearbyintf") @@ -2603,6 +2867,8 @@ libc_math_function(name = "nearbyintl") libc_math_function(name = "nearbyintf128") +libc_math_function(name = "nearbyintf16") + libc_math_function(name = "nextafter") libc_math_function(name = "nextafterf") @@ -2611,6 +2877,8 @@ libc_math_function(name = "nextafterl") libc_math_function(name = "nextafterf128") +libc_math_function(name = "nextafterf16") + libc_math_function(name = "nextdown") libc_math_function(name = "nextdownf") @@ -2619,10 +2887,14 @@ libc_math_function(name = "nextdownl") libc_math_function(name = "nextdownf128") +libc_math_function(name = "nextdownf16") + libc_math_function(name = "nexttoward") libc_math_function(name = "nexttowardf") +libc_math_function(name = "nexttowardf16") + libc_math_function(name = "nexttowardl") libc_math_function(name = "nextup") @@ -2633,6 +2905,8 @@ libc_math_function(name = "nextupl") libc_math_function(name = "nextupf128") +libc_math_function(name = "nextupf16") + libc_math_function( name = "pow", additional_deps = [ @@ -2670,6 +2944,8 @@ libc_math_function(name = "remainderl") libc_math_function(name = "remainderf128") +libc_math_function(name = "remainderf16") + libc_math_function(name = "remquo") libc_math_function(name = "remquof") @@ -2678,6 +2954,8 @@ libc_math_function(name = "remquol") libc_math_function(name = "remquof128") +libc_math_function(name = "remquof16") + libc_math_function(name = "rint") libc_math_function(name = "rintf") @@ -2686,6 +2964,8 @@ libc_math_function(name = "rintl") libc_math_function(name = "rintf128") +libc_math_function(name = "rintf16") + libc_math_function(name = "round") libc_math_function(name = "roundf") @@ -2694,6 +2974,8 @@ libc_math_function(name = "roundl") libc_math_function(name = "roundf128") +libc_math_function(name = "roundf16") + libc_math_function(name = "roundeven") libc_math_function(name = "roundevenf") @@ -2702,6 +2984,8 @@ libc_math_function(name = "roundevenl") libc_math_function(name = "roundevenf128") +libc_math_function(name = "roundevenf16") + libc_math_function(name = "scalbln") libc_math_function(name = "scalblnf") @@ -2710,6 +2994,8 @@ libc_math_function(name = "scalblnl") libc_math_function(name = "scalblnf128") +libc_math_function(name = "scalblnf16") + libc_math_function(name = "scalbn") libc_math_function(name = "scalbnf") @@ -2718,6 +3004,8 @@ libc_math_function(name = "scalbnl") libc_math_function(name = "scalbnf128") +libc_math_function(name = "scalbnf16") + libc_math_function(name = "setpayload") libc_math_function(name = "setpayloadf") @@ -2726,6 +3014,8 @@ libc_math_function(name = "setpayloadl") libc_math_function(name = "setpayloadf128") +libc_math_function(name = "setpayloadf16") + libc_math_function(name = "setpayloadsig") libc_math_function(name = "setpayloadsigf") @@ -2734,6 +3024,8 @@ libc_math_function(name = "setpayloadsigl") libc_math_function(name = "setpayloadsigf128") +libc_math_function(name = "setpayloadsigf16") + libc_math_function( name = "sin", additional_deps = [ @@ -2796,6 +3088,13 @@ libc_math_function( ], ) +libc_math_function( + name = "sinhf16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function( name = "sinpif", additional_deps = [ @@ -2803,6 +3102,15 @@ libc_math_function( ], ) +libc_math_function( + name = "sinpif16", + additional_deps = [ + ":__support_fputil_nearest_integer", + ":__support_fputil_polyeval", + ":sincosf16_utils", + ], +) + libc_math_function( name = "sqrt", additional_deps = [ @@ -2831,6 +3139,13 @@ libc_math_function( ], ) +libc_math_function( + name = "sqrtf16", + additional_deps = [ + ":__support_fputil_sqrt", + ], +) + libc_math_function( name = "tan", additional_deps = [ @@ -2871,6 +3186,13 @@ libc_math_function( ], ) +libc_math_function( + name = "tanhf16", + additional_deps = [ + ":expxf16", + ], +) + libc_math_function(name = "totalorder") libc_math_function(name = "totalorderf") @@ -2879,6 +3201,8 @@ libc_math_function(name = "totalorderl") libc_math_function(name = "totalorderf128") +libc_math_function(name = "totalorderf16") + libc_math_function(name = "totalordermag") libc_math_function(name = "totalordermagf") @@ -2887,6 +3211,8 @@ libc_math_function(name = "totalordermagl") libc_math_function(name = "totalordermagf128") +libc_math_function(name = "totalordermagf16") + libc_math_function(name = "trunc") libc_math_function(name = "truncf") @@ -2895,6 +3221,8 @@ libc_math_function(name = "truncl") libc_math_function(name = "truncf128") +libc_math_function(name = "truncf16") + libc_math_function(name = "ufromfp") libc_math_function(name = "ufromfpf") @@ -2903,6 +3231,8 @@ libc_math_function(name = "ufromfpl") libc_math_function(name = "ufromfpf128") +libc_math_function(name = "ufromfpf16") + libc_math_function(name = "ufromfpx") libc_math_function(name = "ufromfpxf") @@ -2911,6 +3241,8 @@ libc_math_function(name = "ufromfpxl") libc_math_function(name = "ufromfpxf128") +libc_math_function(name = "ufromfpxf16") + ############################## inttypes targets ############################## libc_function(