diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index be08165a200de70396f11106433691658cb31496..cdc9df7bf6b6265b4b8ed4ef6eec2328f0e3b98b 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -851,6 +851,7 @@ public: std::unique_ptr popFirstCondition() override; const PredicateMatcher &getFirstCondition() const override; + LLTCodeGen getFirstConditionAsRootType(); bool hasFirstCondition() const override; unsigned getNumOperands() const; StringRef getOpcode() const; @@ -1921,6 +1922,16 @@ unsigned RuleMatcher::getNumOperands() const { return Matchers.front()->getNumOperands(); } +LLTCodeGen RuleMatcher::getFirstConditionAsRootType() { + InstructionMatcher &InsnMatcher = *Matchers.front(); + if (!InsnMatcher.predicates_empty()) + if (const auto *TM = + dyn_cast(&**InsnMatcher.predicates_begin())) + if (TM->getInsnVarID() == 0 && TM->getOpIdx() == 0) + return TM->getTy(); + return {}; +} + /// Generates code to check that the operand is a register defined by an /// instruction that matches the given instruction matcher. /// @@ -4016,25 +4027,6 @@ GlobalISelEmitter::buildMatchTable(MutableArrayRef Rules, if (!Optimize) return MatchTable::buildTable(InputRules, WithCoverage); - unsigned CurrentOrdering = 0; - StringMap OpcodeOrder; - for (RuleMatcher &Rule : Rules) { - const StringRef Opcode = Rule.getOpcode(); - assert(!Opcode.empty() && "Didn't expect an undefined opcode"); - if (OpcodeOrder.count(Opcode) == 0) - OpcodeOrder[Opcode] = CurrentOrdering++; - } - - std::stable_sort(InputRules.begin(), InputRules.end(), - [&OpcodeOrder](const Matcher *A, const Matcher *B) { - auto *L = static_cast(A); - auto *R = static_cast(B); - return std::make_tuple(OpcodeOrder[L->getOpcode()], - L->getNumOperands()) < - std::make_tuple(OpcodeOrder[R->getOpcode()], - R->getNumOperands()); - }); - for (Matcher *Rule : InputRules) Rule->optimize();