diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index f7f84c9f13ce5943818caae2ac01d82882eeb294..ca0f195fce7e1d6dc6da98c4b6a777fad459a671 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -74,6 +74,24 @@ let Predicates = [HasSVE] in { defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>; defm LDNF1D_IMM : sve_mem_cldnf_si<0b1111, "ldnf1d", Z_d, ZPR64>; + // First-faulting loads with reg+reg addressing. + defm LDFF1B : sve_mem_cldff_ss<0b0000, "ldff1b", Z_b, ZPR8, GPR64shifted8>; + defm LDFF1B_H : sve_mem_cldff_ss<0b0001, "ldff1b", Z_h, ZPR16, GPR64shifted8>; + defm LDFF1B_S : sve_mem_cldff_ss<0b0010, "ldff1b", Z_s, ZPR32, GPR64shifted8>; + defm LDFF1B_D : sve_mem_cldff_ss<0b0011, "ldff1b", Z_d, ZPR64, GPR64shifted8>; + defm LDFF1SW_D : sve_mem_cldff_ss<0b0100, "ldff1sw", Z_d, ZPR64, GPR64shifted32>; + defm LDFF1H : sve_mem_cldff_ss<0b0101, "ldff1h", Z_h, ZPR16, GPR64shifted16>; + defm LDFF1H_S : sve_mem_cldff_ss<0b0110, "ldff1h", Z_s, ZPR32, GPR64shifted16>; + defm LDFF1H_D : sve_mem_cldff_ss<0b0111, "ldff1h", Z_d, ZPR64, GPR64shifted16>; + defm LDFF1SH_D : sve_mem_cldff_ss<0b1000, "ldff1sh", Z_d, ZPR64, GPR64shifted16>; + defm LDFF1SH_S : sve_mem_cldff_ss<0b1001, "ldff1sh", Z_s, ZPR32, GPR64shifted16>; + defm LDFF1W : sve_mem_cldff_ss<0b1010, "ldff1w", Z_s, ZPR32, GPR64shifted32>; + defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>; + defm LDFF1SB_D : sve_mem_cldff_ss<0b1100, "ldff1sb", Z_d, ZPR64, GPR64shifted8>; + defm LDFF1SB_S : sve_mem_cldff_ss<0b1101, "ldff1sb", Z_s, ZPR32, GPR64shifted8>; + defm LDFF1SB_H : sve_mem_cldff_ss<0b1110, "ldff1sb", Z_h, ZPR16, GPR64shifted8>; + defm LDFF1D : sve_mem_cldff_ss<0b1111, "ldff1d", Z_d, ZPR64, GPR64shifted64>; + // LD(2|3|4) structured loads with reg+immediate defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b, "ld2b", simm4Scale2MulVl>; defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b, "ld3b", simm4Scale3MulVl>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 1a1b0d44a7be47ee5bb1c56b75f13274c26e9f28..e2ea4a2ab1832c0677aa84a3aa2d726cf4484731 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -711,6 +711,20 @@ multiclass sve_mem_cld_ss dtype, string asm, RegisterOperand listty, (!cast(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } +multiclass sve_mem_cldff_ss dtype, string asm, RegisterOperand listty, + ZPRRegOp zprty, RegisterOperand gprty> { + def _REAL : sve_mem_cld_ss_base; + + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; + + def : InstAlias(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>; + + def : InstAlias(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>; +} multiclass sve_mem_cldnf_si dtype, string asm, RegisterOperand listty, ZPRRegOp zprty> @@ -745,4 +759,4 @@ multiclass sve_mem_eld_si sz, bits<2> nregs, RegisterOperand VecList, def : InstAlias(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; -} \ No newline at end of file +} diff --git a/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..f575a369b9aa7f7a68930d248146b3e35c0e24cc --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s @@ -0,0 +1,47 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldff1b z27.b, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1b z27.b, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1b z9.h, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1b z9.h, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1b z12.s, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1b z12.s, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1b z4.d, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1b z4.d, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +ldff1b z0.b, p0/z, [x0, sp] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift +// CHECK-NEXT: ldff1b z0.b, p0/z, [x0, sp] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1b z0.b, p0/z, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift +// CHECK-NEXT: ldff1b z0.b, p0/z, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1b z0.b, p0/z, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift +// CHECK-NEXT: ldff1b z0.b, p0/z, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1b z0.b, p0/z, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift +// CHECK-NEXT: ldff1b z0.b, p0/z, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1b.s b/llvm/test/MC/AArch64/SVE/ldff1b.s new file mode 100644 index 0000000000000000000000000000000000000000..ab831f97e7d523ae79e76063c80f9bf8b1b5e79b --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1b.s @@ -0,0 +1,74 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldff1b { z31.b }, p7/z, [sp] +// CHECK-INST: ldff1b { z31.b }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x1f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 1f a4 + +ldff1b { z31.h }, p7/z, [sp] +// CHECK-INST: ldff1b { z31.h }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x3f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 3f a4 + +ldff1b { z31.s }, p7/z, [sp] +// CHECK-INST: ldff1b { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x5f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 5f a4 + +ldff1b { z31.d }, p7/z, [sp] +// CHECK-INST: ldff1b { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x7f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 7f a4 + +ldff1b { z31.b }, p7/z, [sp, xzr] +// CHECK-INST: ldff1b { z31.b }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x1f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 1f a4 + +ldff1b { z31.h }, p7/z, [sp, xzr] +// CHECK-INST: ldff1b { z31.h }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x3f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 3f a4 + +ldff1b { z31.s }, p7/z, [sp, xzr] +// CHECK-INST: ldff1b { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x5f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 5f a4 + +ldff1b { z31.d }, p7/z, [sp, xzr] +// CHECK-INST: ldff1b { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x7f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 7f a4 + +ldff1b { z0.h }, p0/z, [x0, x0] +// CHECK-INST: ldff1b { z0.h }, p0/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0x20,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 20 a4 + +ldff1b { z0.s }, p0/z, [x0, x0] +// CHECK-INST: ldff1b { z0.s }, p0/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0x40,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 40 a4 + +ldff1b { z0.d }, p0/z, [x0, x0] +// CHECK-INST: ldff1b { z0.d }, p0/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0x60,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 60 a4 diff --git a/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..fe16b2b12ee331f706ff4a8e365bbeccd85e2fa2 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s @@ -0,0 +1,51 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand (.b, .h, .s) + +ldff1d z4.b, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1d z4.b, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1d z4.h, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1d z4.h, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1d z4.s, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1d z4.s, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldff1d z4.d, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1d z4.d, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +ldff1d z0.d, p0/z, [x0, sp] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' +// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, sp] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1d z0.d, p0/z, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' +// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1d z0.d, p0/z, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' +// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1d z0.d, p0/z, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' +// CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + diff --git a/llvm/test/MC/AArch64/SVE/ldff1d.s b/llvm/test/MC/AArch64/SVE/ldff1d.s new file mode 100644 index 0000000000000000000000000000000000000000..549ba52ef4d0a74066c42db79fb0274e4d0ae5a0 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1d.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldff1d { z31.d }, p7/z, [sp] +// CHECK-INST: ldff1d { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xff,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f ff a5 + +ldff1d { z31.d }, p7/z, [sp, xzr, lsl #3] +// CHECK-INST: ldff1d { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xff,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f ff a5 + +ldff1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK-INST: ldff1d { z0.d }, p0/z, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0x60,0xe0,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 e0 a5 diff --git a/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..217d6a0d6fc8ebed114679654661154fe6dc1500 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand (.b) + +ldff1h z9.b, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1h z9.b, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldff1h z9.h, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1h z9.h, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1h z12.s, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1h z12.s, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1h z4.d, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1h z4.d, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +ldff1h z0.h, p0/z, [x0, sp] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' +// CHECK-NEXT: ldff1h z0.h, p0/z, [x0, sp] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1h z0.h, p0/z, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' +// CHECK-NEXT: ldff1h z0.h, p0/z, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1h z0.h, p0/z, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' +// CHECK-NEXT: ldff1h z0.h, p0/z, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1h z0.h, p0/z, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' +// CHECK-NEXT: ldff1h z0.h, p0/z, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1h.s b/llvm/test/MC/AArch64/SVE/ldff1h.s new file mode 100644 index 0000000000000000000000000000000000000000..0a9863ce2ec91950a8dfa186b1ebc6fab8e1900c --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1h.s @@ -0,0 +1,62 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldff1h { z31.h }, p7/z, [sp] +// CHECK-INST: ldff1h { z31.h }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xbf,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f bf a4 + +ldff1h { z31.s }, p7/z, [sp] +// CHECK-INST: ldff1h { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xdf,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f df a4 + +ldff1h { z31.d }, p7/z, [sp] +// CHECK-INST: ldff1h { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xff,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f ff a4 + +ldff1h { z31.h }, p7/z, [sp, xzr, lsl #1] +// CHECK-INST: ldff1h { z31.h }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xbf,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f bf a4 + +ldff1h { z31.s }, p7/z, [sp, xzr, lsl #1] +// CHECK-INST: ldff1h { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xdf,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f df a4 + +ldff1h { z31.d }, p7/z, [sp, xzr, lsl #1] +// CHECK-INST: ldff1h { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xff,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f ff a4 + +ldff1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK-INST: ldff1h { z0.h }, p0/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x60,0xa0,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 a0 a4 + +ldff1h { z0.s }, p0/z, [x0, x0, lsl #1] +// CHECK-INST: ldff1h { z0.s }, p0/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x60,0xc0,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 c0 a4 + +ldff1h { z0.d }, p0/z, [x0, x0, lsl #1] +// CHECK-INST: ldff1h { z0.d }, p0/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x60,0xe0,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 e0 a4 diff --git a/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..826fd5293852e406db4abeca719ea38c0703deca --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand (.b) + +ldff1sb z27.b, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1sb z27.b, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldff1sb z9.h, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1sb z9.h, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sb z12.s, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1sb z12.s, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sb z4.d, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1sb z4.d, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +ldff1sb z0.h, p0/z, [x0, sp] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift +// CHECK-NEXT: ldff1sb z0.h, p0/z, [x0, sp] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sb z0.h, p0/z, [x0, x0, lsl #1] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift +// CHECK-NEXT: ldff1sb z0.h, p0/z, [x0, x0, lsl #1] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sb z0.h, p0/z, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift +// CHECK-NEXT: ldff1sb z0.h, p0/z, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sb z0.h, p0/z, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift +// CHECK-NEXT: ldff1sb z0.h, p0/z, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1sb.s b/llvm/test/MC/AArch64/SVE/ldff1sb.s new file mode 100644 index 0000000000000000000000000000000000000000..2be5145e4e28b79e29d18bf752ec0ede945ff15e --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1sb.s @@ -0,0 +1,62 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldff1sb { z31.h }, p7/z, [sp] +// CHECK-INST: ldff1sb { z31.h }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xdf,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f df a5 + +ldff1sb { z31.s }, p7/z, [sp] +// CHECK-INST: ldff1sb { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xbf,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f bf a5 + +ldff1sb { z31.d }, p7/z, [sp] +// CHECK-INST: ldff1sb { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x9f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 9f a5 + +ldff1sb { z31.h }, p7/z, [sp, xzr] +// CHECK-INST: ldff1sb { z31.h }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xdf,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f df a5 + +ldff1sb { z31.s }, p7/z, [sp, xzr] +// CHECK-INST: ldff1sb { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0xbf,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f bf a5 + +ldff1sb { z31.d }, p7/z, [sp, xzr] +// CHECK-INST: ldff1sb { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x9f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 9f a5 + +ldff1sb { z0.h }, p0/z, [x0, x0] +// CHECK-INST: ldff1sb { z0.h }, p0/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0xc0,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 c0 a5 + +ldff1sb { z0.s }, p0/z, [x0, x0] +// CHECK-INST: ldff1sb { z0.s }, p0/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0xa0,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 a0 a5 + +ldff1sb { z0.d }, p0/z, [x0, x0] +// CHECK-INST: ldff1sb { z0.d }, p0/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x60,0x80,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 80 a5 diff --git a/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..031e7f7c0d807e782bf3fec8ab332be53e0a1bdf --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s @@ -0,0 +1,45 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand (.h) + +ldff1sh z9.h, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1sh z9.h, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldff1sh z12.s, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1sh z12.s, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sh z4.d, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1sh z4.d, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +ldff1sh z0.s, p0/z, [x0, sp] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' +// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, sp] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sh z0.s, p0/z, [x0, x0, lsl #2] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' +// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, x0, lsl #2] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sh z0.s, p0/z, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' +// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sh z0.s, p0/z, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' +// CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1sh.s b/llvm/test/MC/AArch64/SVE/ldff1sh.s new file mode 100644 index 0000000000000000000000000000000000000000..abe780fd20b6f62d3ebf567ca93fb210e31e2184 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1sh.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldff1sh { z31.s }, p7/z, [sp] +// CHECK-INST: ldff1sh { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x3f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 3f a5 + +ldff1sh { z31.d }, p7/z, [sp] +// CHECK-INST: ldff1sh { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x1f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 1f a5 + +ldff1sh { z31.s }, p7/z, [sp, xzr, lsl #1] +// CHECK-INST: ldff1sh { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x3f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 3f a5 + +ldff1sh { z31.d }, p7/z, [sp, xzr, lsl #1] +// CHECK-INST: ldff1sh { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x1f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 1f a5 + +ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1] +// CHECK-INST: ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x60,0x20,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 20 a5 + +ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1] +// CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x60,0x00,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 00 a5 diff --git a/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..08b24bd0992239b91fa79bfb3974819685deaec6 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand (.s) + +ldff1sw z12.s, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1sw z12.s, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldff1sw z4.d, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1sw z4.d, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +ldff1sw z0.d, p0/z, [x0, sp] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' +// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, sp] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sw z0.d, p0/z, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' +// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sw z0.d, p0/z, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' +// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1sw z0.d, p0/z, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' +// CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1sw.s b/llvm/test/MC/AArch64/SVE/ldff1sw.s new file mode 100644 index 0000000000000000000000000000000000000000..99defea0f2db8a318702b9f147dafd9729f9f4ce --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1sw.s @@ -0,0 +1,26 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldff1sw { z31.d }, p7/z, [sp] +// CHECK-INST: ldff1sw { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x9f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 9f a4 + +ldff1sw { z31.d }, p7/z, [sp, xzr, lsl #2] +// CHECK-INST: ldff1sw { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x9f,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 9f a4 + +ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2] +// CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x60,0x80,0xa4] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 80 a4 diff --git a/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s new file mode 100644 index 0000000000000000000000000000000000000000..02a651187e6e37ca244f20c099e801c5d7d9bffe --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid operand (.b, .h) + +ldff1w z12.b, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1w z12.b, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1w z4.h, p7/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: ldff1w z4.h, p7/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// restricted predicate has range [0, 7]. + +ldff1w z12.s, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1w z12.s, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1w z4.d, p8/z, [x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: ldff1w z4.d, p8/z, [x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid scalar + scalar addressing modes + +ldff1w z0.s, p0/z, [x0, sp] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' +// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, sp] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1w z0.s, p0/z, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' +// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1w z0.s, p0/z, [x0, w0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' +// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ldff1w z0.s, p0/z, [x0, w0, uxtw] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' +// CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0, uxtw] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ldff1w.s b/llvm/test/MC/AArch64/SVE/ldff1w.s new file mode 100644 index 0000000000000000000000000000000000000000..022d7b3b649447ffc62b377df651e8d8994300bb --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/ldff1w.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +ldff1w { z31.d }, p7/z, [sp] +// CHECK-INST: ldff1w { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x7f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 7f a5 + +ldff1w { z31.s }, p7/z, [sp] +// CHECK-INST: ldff1w { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x5f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 5f a5 + +ldff1w { z31.d }, p7/z, [sp, xzr, lsl #2] +// CHECK-INST: ldff1w { z31.d }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x7f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 7f a5 + +ldff1w { z31.s }, p7/z, [sp, xzr, lsl #2] +// CHECK-INST: ldff1w { z31.s }, p7/z, [sp] +// CHECK-ENCODING: [0xff,0x7f,0x5f,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 7f 5f a5 + +ldff1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK-INST: ldff1w { z0.s }, p0/z, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x60,0x40,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 40 a5 + +ldff1w { z0.d }, p0/z, [x0, x0, lsl #2] +// CHECK-INST: ldff1w { z0.d }, p0/z, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x60,0x60,0xa5] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 60 60 a5