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  • Kristof Beyls's avatar
    [AArch64] Extend AArch64SLSHardeningPass to harden BLR instructions. · c35ed40f
    Kristof Beyls authored
    To make sure that no barrier gets placed on the architectural execution
    path, each
      BLR x<N>
    instruction gets transformed to a
      BL __llvm_slsblr_thunk_x<N>
    instruction, with __llvm_slsblr_thunk_x<N> a thunk that contains
    __llvm_slsblr_thunk_x<N>:
      BR x<N>
      <speculation barrier>
    
    Therefore, the BLR instruction gets split into 2; one BL and one BR.
    This transformation results in not inserting a speculation barrier on
    the architectural execution path.
    
    The mitigation is off by default and can be enabled by the
    harden-sls-blr subtarget feature.
    
    As a linker is allowed to clobber X16 and X17 on function calls, the
    above code transformation would not be correct in case a linker does so
    when N=16 or N=17. Therefore, when the mitigation is enabled, generation
    of BLR x16 or BLR x17 is avoided.
    
    As BLRA* indirect calls are not produced by LLVM currently, this does
    not aim to implement support for those.
    
    Differential Revision:  https://reviews.llvm.org/D81402
    c35ed40f
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