[mips][msa] Implement f16 support

The MIPS MSA ASE provides instructions to convert to and from half precision
floating point. This patch teaches the MIPS backend to treat f16 as a legal
type and how to promote such values to f32 for the usual set of operations.

As a result of this, the fexup[lr].w intrinsics no longer crash LLVM during
type legalization.

Reviewers: zoran.jovanvoic, vkalintiris

Differential Revision: https://reviews.llvm.org/D26398

llvm-svn: 287349