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Commit 1a98dc18 authored by Carl Ritson's avatar Carl Ritson
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[AMDGPU] V_CVT_F32_UBYTE{0,1,2,3} are full rate instructions

Summary: Fix a bug in the scheduling model where V_CVT_F32_UBYTE{0,1,2,3} are incorrectly marked as quarter rate instructions.

Reviewers: arsenm, rampitec

Reviewed By: rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59091

llvm-svn: 355671
parent 07ddb9d9
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