[RISCV] Merge WriteLDW and WriteLDWU schedule classes.

We don't distinquish signed vs unsigned for B and H loads.

Maybe this split was because LDWU isn't in RV32I? I don't think
that distinction matters to the scheduler. If your processor
only supports RV32I then having LWU in the SchedClass doesn't matter.
If your target supports RV64I, then LW and LWU are likely the same.