[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
As outlined in the PR, we didn't ensure that displacements for DQ-Form instructions are multiples of 16. Since the instruction encoding encodes a quad-word displacement, a sub-16 byte displacement is meaningless and ends up being encoded incorrectly. Fixes https://bugs.llvm.org/show_bug.cgi?id=33671. Differential Revision: https://reviews.llvm.org/D35007 llvm-svn: 307934
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- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp 2 additions, 1 deletionllvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp 26 additions, 2 deletionsllvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
- llvm/lib/Target/PowerPC/PPCISelLowering.cpp 9 additions, 9 deletionsllvm/lib/Target/PowerPC/PPCISelLowering.cpp
- llvm/lib/Target/PowerPC/PPCISelLowering.h 1 addition, 1 deletionllvm/lib/Target/PowerPC/PPCISelLowering.h
- llvm/lib/Target/PowerPC/PPCInstrInfo.td 21 additions, 1 deletionllvm/lib/Target/PowerPC/PPCInstrInfo.td
- llvm/lib/Target/PowerPC/PPCInstrVSX.td 47 additions, 43 deletionsllvm/lib/Target/PowerPC/PPCInstrVSX.td
- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp 20 additions, 10 deletionsllvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
- llvm/test/CodeGen/PowerPC/PR33671.ll 32 additions, 0 deletionsllvm/test/CodeGen/PowerPC/PR33671.ll
- llvm/test/CodeGen/PowerPC/build-vector-tests.ll 21 additions, 19 deletionsllvm/test/CodeGen/PowerPC/build-vector-tests.ll
- llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll 3 additions, 3 deletionsllvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
- llvm/test/CodeGen/PowerPC/swaps-le-6.ll 4 additions, 4 deletionsllvm/test/CodeGen/PowerPC/swaps-le-6.ll
- llvm/test/CodeGen/PowerPC/vsx-p9.ll 24 additions, 24 deletionsllvm/test/CodeGen/PowerPC/vsx-p9.ll
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