[RISCV][test] Add new tests of bitwise and with constant for the Zbs extension

These tests will show how (and r i) will be optimized to
(BCLRI (BCLRI r, i0), i1) or (BCLRI (ANDI r, i0), i1) by future
commits.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D103359

llvm/test/CodeGen/RISCV/rv32zbs.ll

@@ -550,6 +550,56 @@ define i32 @sbclri_i32_31(i32 %a) nounwind {
   ret i32 %and
 }
 
+define i32 @sbclri_i32_large0(i32 %a) nounwind {
+; RV32I-LABEL: sbclri_i32_large0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1044480
+; RV32I-NEXT:    addi a1, a1, -256
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: sbclri_i32_large0:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1044480
+; RV32IB-NEXT:    addi a1, a1, -256
+; RV32IB-NEXT:    and a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: sbclri_i32_large0:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 1044480
+; RV32IBS-NEXT:    addi a1, a1, -256
+; RV32IBS-NEXT:    and a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %and = and i32 %a, -16777472
+  ret i32 %and
+}
+
+define i32 @sbclri_i32_large1(i32 %a) nounwind {
+; RV32I-LABEL: sbclri_i32_large1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1044464
+; RV32I-NEXT:    addi a1, a1, -1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32IB-LABEL: sbclri_i32_large1:
+; RV32IB:       # %bb.0:
+; RV32IB-NEXT:    lui a1, 1044464
+; RV32IB-NEXT:    addi a1, a1, -1
+; RV32IB-NEXT:    and a0, a0, a1
+; RV32IB-NEXT:    ret
+;
+; RV32IBS-LABEL: sbclri_i32_large1:
+; RV32IBS:       # %bb.0:
+; RV32IBS-NEXT:    lui a1, 1044464
+; RV32IBS-NEXT:    addi a1, a1, -1
+; RV32IBS-NEXT:    and a0, a0, a1
+; RV32IBS-NEXT:    ret
+  %and = and i32 %a, -16842753
+  ret i32 %and
+}
+
 define i32 @sbseti_i32_10(i32 %a) nounwind {
 ; RV32I-LABEL: sbseti_i32_10:
 ; RV32I:       # %bb.0:

llvm/test/CodeGen/RISCV/rv64zbs.ll

@@ -800,6 +800,56 @@ define i64 @sbclri_i64_63(i64 %a) nounwind {
   ret i64 %and
 }
 
+define i64 @sbclri_i64_large0(i64 %a) nounwind {
+; RV64I-LABEL: sbclri_i64_large0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1044480
+; RV64I-NEXT:    addiw a1, a1, -256
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: sbclri_i64_large0:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 1044480
+; RV64IB-NEXT:    addiw a1, a1, -256
+; RV64IB-NEXT:    and a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: sbclri_i64_large0:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 1044480
+; RV64IBS-NEXT:    addiw a1, a1, -256
+; RV64IBS-NEXT:    and a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %and = and i64 %a, -16777472
+  ret i64 %and
+}
+
+define i64 @sbclri_i64_large1(i64 %a) nounwind {
+; RV64I-LABEL: sbclri_i64_large1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1044464
+; RV64I-NEXT:    addiw a1, a1, -1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64IB-LABEL: sbclri_i64_large1:
+; RV64IB:       # %bb.0:
+; RV64IB-NEXT:    lui a1, 1044464
+; RV64IB-NEXT:    addiw a1, a1, -1
+; RV64IB-NEXT:    and a0, a0, a1
+; RV64IB-NEXT:    ret
+;
+; RV64IBS-LABEL: sbclri_i64_large1:
+; RV64IBS:       # %bb.0:
+; RV64IBS-NEXT:    lui a1, 1044464
+; RV64IBS-NEXT:    addiw a1, a1, -1
+; RV64IBS-NEXT:    and a0, a0, a1
+; RV64IBS-NEXT:    ret
+  %and = and i64 %a, -16842753
+  ret i64 %and
+}
+
 define signext i32 @sbseti_i32_10(i32 signext %a) nounwind {
 ; RV64I-LABEL: sbseti_i32_10:
 ; RV64I:       # %bb.0: