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Commit 6a75041a authored by Christudasan Devadasan's avatar Christudasan Devadasan
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[TableGen] Allow target specific flags for RegisterClass 

Analogous to the TSFlags for machine instructions, this
patch introduces a bit vector for register classes to have
target specific flags that become a tablegened value in
TargetRegisterClass.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D108767
parent 89424a82
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