[IR][Verifier] Relax restriction on alloca address spaces

In the WebAssembly target, we would like to allow alloca in two address
spaces.  The alloca instruction already has an address space argument,
but the verifier asserts that the address space of an alloca is the
default alloca address space from the datalayout.  This patch removes
this restriction.  Targets that would like to impose additional
restrictions should do so via target-specific verification passes.

Differential Revision: https://reviews.llvm.org/D101045