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Commit 8f8cdd00 authored by Yichao Yu's avatar Yichao Yu
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Fix R_AARCH64_MOVW_UABS_G3 relocation

Summary: The relocation is missing mask so an address that has non-zero bits in 47:43 may overwrite the register number. (Frequently shows up as target register changed to `xzr`....)

Reviewers: t.p.northover, lhames

Subscribers: davide, aemerson, rengolin, llvm-commits

Differential Revision: https://reviews.llvm.org/D27609

llvm-svn: 289880
parent d69b9414
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