[RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

I only added Zicsr to CPUs that didn't already have an implication
through the F extension.

As far as I could tell from searching Rocket and Syntacore repositories,
all the CPUs support these instructions.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D147261