[InstCombine] Allow fake vector insert folding to bit-logic only if the insert...

[InstCombine] Allow fake vector insert folding to bit-logic only if the insert element is integer type

The below commit is causing assertion when insert element type is not integer
 type such as half. This is because the transformation is creating zext before
 doing bitwise OR, and the zext is supported only for integer types
https://github.com/llvm/llvm-project/commit/80ab06c599a0f5a90951c36a57b2a9b492b19d61

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D114734