[AMDGPU] Supported ds_read_b128 generation; Widened vector length for local address-space.
Summary: Starting from GCN 2nd generation, ISA supports ds_read_b128 on top of ds_read_b64. This patch supports ds_read_b128 instruction pattern and generation of this instruction. In the vectorizer, this patch also widen the vector length so that vectorizer generates 128 bit loads for local address-space which gets translated to ds_read_b128. Since the performance benefit is not clear; compiler generates ds_read_b128 under -amdgpu-ds128. Author: FarhanaAleen Reviewed By: rampitec, arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D44210 llvm-svn: 327153
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- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td 8 additions, 0 deletionsllvm/lib/Target/AMDGPU/AMDGPUInstructions.td
- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h 6 additions, 0 deletionsllvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp 4 additions, 4 deletionsllvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
- llvm/lib/Target/AMDGPU/DSInstructions.td 1 addition, 0 deletionsllvm/lib/Target/AMDGPU/DSInstructions.td
- llvm/lib/Target/AMDGPU/SIISelLowering.cpp 10 additions, 6 deletionsllvm/lib/Target/AMDGPU/SIISelLowering.cpp
- llvm/lib/Target/AMDGPU/SIInstrInfo.td 4 additions, 0 deletionsllvm/lib/Target/AMDGPU/SIInstrInfo.td
- llvm/test/CodeGen/AMDGPU/load-local-f32.ll 19 additions, 0 deletionsllvm/test/CodeGen/AMDGPU/load-local-f32.ll
- llvm/test/CodeGen/AMDGPU/load-local-f64.ll 18 additions, 0 deletionsllvm/test/CodeGen/AMDGPU/load-local-f64.ll
- llvm/test/CodeGen/AMDGPU/load-local-i16.ll 18 additions, 0 deletionsllvm/test/CodeGen/AMDGPU/load-local-i16.ll
- llvm/test/CodeGen/AMDGPU/load-local-i32.ll 19 additions, 0 deletionsllvm/test/CodeGen/AMDGPU/load-local-i32.ll
- llvm/test/CodeGen/AMDGPU/load-local-i64.ll 14 additions, 0 deletionsllvm/test/CodeGen/AMDGPU/load-local-i64.ll
- llvm/test/CodeGen/AMDGPU/load-local-i8.ll 17 additions, 0 deletionsllvm/test/CodeGen/AMDGPU/load-local-i8.ll
- llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll 1 addition, 2 deletions...est/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores.ll
- llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll 1 addition, 2 deletions...t/Transforms/LoadStoreVectorizer/AMDGPU/multiple_tails.ll
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