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Commit c5e437e5 authored by Roman Lebedev's avatar Roman Lebedev
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[NFC][InstCombine] Add variable names and regenerate icmp-logical.ll test. 

llvm-svn: 336780
parent 075b04a5
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llvm/test/Transforms/InstCombine/icmp-logical.ll
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− 422
View file @ c5e437e5
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -instcombine -S -o - %s | FileCheck %s ; RUN: opt -instcombine -S -o - %s | FileCheck %s
define i1 @masked_and_notallzeroes(i32 %A) { define i1 @masked_and_notallzeroes(i32 %A) {
; CHECK-LABEL: @masked_and_notallzeroes( ; CHECK-LABEL: @masked_and_notallzeroes(
; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 7 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 0 ; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 0
; CHECK-NEXT: ret i1 [[TST1]] ; CHECK-NEXT: ret i1 [[TST1]]
; ;
...@@ -16,7 +17,7 @@ define i1 @masked_and_notallzeroes(i32 %A) { ...@@ -16,7 +17,7 @@ define i1 @masked_and_notallzeroes(i32 %A) {
define i1 @masked_or_allzeroes(i32 %A) { define i1 @masked_or_allzeroes(i32 %A) {
; CHECK-LABEL: @masked_or_allzeroes( ; CHECK-LABEL: @masked_or_allzeroes(
; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 7 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0
; CHECK-NEXT: ret i1 [[TST1]] ; CHECK-NEXT: ret i1 [[TST1]]
; ;
...@@ -30,7 +31,7 @@ define i1 @masked_or_allzeroes(i32 %A) { ...@@ -30,7 +31,7 @@ define i1 @masked_or_allzeroes(i32 %A) {
define i1 @masked_and_notallones(i32 %A) { define i1 @masked_and_notallones(i32 %A) {
; CHECK-LABEL: @masked_and_notallones( ; CHECK-LABEL: @masked_and_notallones(
; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 7 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 7 ; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 7
; CHECK-NEXT: ret i1 [[TST1]] ; CHECK-NEXT: ret i1 [[TST1]]
; ;
...@@ -44,7 +45,7 @@ define i1 @masked_and_notallones(i32 %A) { ...@@ -44,7 +45,7 @@ define i1 @masked_and_notallones(i32 %A) {
define i1 @masked_or_allones(i32 %A) { define i1 @masked_or_allones(i32 %A) {
; CHECK-LABEL: @masked_or_allones( ; CHECK-LABEL: @masked_or_allones(
; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 7 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 7 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 7
; CHECK-NEXT: ret i1 [[TST1]] ; CHECK-NEXT: ret i1 [[TST1]]
; ;
...@@ -58,8 +59,8 @@ define i1 @masked_or_allones(i32 %A) { ...@@ -58,8 +59,8 @@ define i1 @masked_or_allones(i32 %A) {
define i1 @masked_and_notA(i32 %A) { define i1 @masked_and_notA(i32 %A) {
; CHECK-LABEL: @masked_and_notA( ; CHECK-LABEL: @masked_and_notA(
; CHECK-NEXT: [[MASK2:%.*]] = and i32 %A, 39 ; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A:%.*]], 39
; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], %A ; CHECK-NEXT: [[TST2:%.*]] = icmp ne i32 [[MASK2]], [[A]]
; CHECK-NEXT: ret i1 [[TST2]] ; CHECK-NEXT: ret i1 [[TST2]]
; ;
%mask1 = and i32 %A, 7 %mask1 = and i32 %A, 7
...@@ -72,8 +73,8 @@ define i1 @masked_and_notA(i32 %A) { ...@@ -72,8 +73,8 @@ define i1 @masked_and_notA(i32 %A) {
define i1 @masked_or_A(i32 %A) { define i1 @masked_or_A(i32 %A) {
; CHECK-LABEL: @masked_or_A( ; CHECK-LABEL: @masked_or_A(
; CHECK-NEXT: [[MASK2:%.*]] = and i32 %A, 39 ; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A:%.*]], 39
; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], %A ; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], [[A]]
; CHECK-NEXT: ret i1 [[TST2]] ; CHECK-NEXT: ret i1 [[TST2]]
; ;
%mask1 = and i32 %A, 7 %mask1 = and i32 %A, 7
...@@ -86,9 +87,9 @@ define i1 @masked_or_A(i32 %A) { ...@@ -86,9 +87,9 @@ define i1 @masked_or_A(i32 %A) {
define i1 @masked_or_allzeroes_notoptimised(i32 %A) { define i1 @masked_or_allzeroes_notoptimised(i32 %A) {
; CHECK-LABEL: @masked_or_allzeroes_notoptimised( ; CHECK-LABEL: @masked_or_allzeroes_notoptimised(
; CHECK-NEXT: [[MASK1:%.*]] = and i32 %A, 15 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15
; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0
; CHECK-NEXT: [[MASK2:%.*]] = and i32 %A, 39 ; CHECK-NEXT: [[MASK2:%.*]] = and i32 [[A]], 39
; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], 0 ; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASK2]], 0
; CHECK-NEXT: [[RES:%.*]] = or i1 [[TST1]], [[TST2]] ; CHECK-NEXT: [[RES:%.*]] = or i1 [[TST1]], [[TST2]]
; CHECK-NEXT: ret i1 [[RES]] ; CHECK-NEXT: ret i1 [[RES]]
...@@ -103,7 +104,7 @@ define i1 @masked_or_allzeroes_notoptimised(i32 %A) { ...@@ -103,7 +104,7 @@ define i1 @masked_or_allzeroes_notoptimised(i32 %A) {
define i1 @nomask_lhs(i32 %in) { define i1 @nomask_lhs(i32 %in) {
; CHECK-LABEL: @nomask_lhs( ; CHECK-LABEL: @nomask_lhs(
; CHECK-NEXT: [[MASKED:%.*]] = and i32 %in, 1 ; CHECK-NEXT: [[MASKED:%.*]] = and i32 [[IN:%.*]], 1
; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASKED]], 0 ; CHECK-NEXT: [[TST2:%.*]] = icmp eq i32 [[MASKED]], 0
; CHECK-NEXT: ret i1 [[TST2]] ; CHECK-NEXT: ret i1 [[TST2]]
; ;
...@@ -116,7 +117,7 @@ define i1 @nomask_lhs(i32 %in) { ...@@ -116,7 +117,7 @@ define i1 @nomask_lhs(i32 %in) {
define i1 @nomask_rhs(i32 %in) { define i1 @nomask_rhs(i32 %in) {
; CHECK-LABEL: @nomask_rhs( ; CHECK-LABEL: @nomask_rhs(
; CHECK-NEXT: [[MASKED:%.*]] = and i32 %in, 1 ; CHECK-NEXT: [[MASKED:%.*]] = and i32 [[IN:%.*]], 1
; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASKED]], 0 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASKED]], 0
; CHECK-NEXT: ret i1 [[TST1]] ; CHECK-NEXT: ret i1 [[TST1]]
; ;
...@@ -133,11 +134,11 @@ define i1 @fold_mask_cmps_to_false(i32 %x) { ...@@ -133,11 +134,11 @@ define i1 @fold_mask_cmps_to_false(i32 %x) {
; CHECK-LABEL: @fold_mask_cmps_to_false( ; CHECK-LABEL: @fold_mask_cmps_to_false(
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;
%1 = and i32 %x, 2147483647 %tmp1 = and i32 %x, 2147483647
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = icmp eq i32 %x, 2147483647 %tmp3 = icmp eq i32 %x, 2147483647
%4 = and i1 %3, %2 %tmp4 = and i1 %tmp3, %tmp2
ret i1 %4 ret i1 %tmp4
} }
; TODO: This test simplifies to a constant, so the functionality and test could be in InstSimplify. ; TODO: This test simplifies to a constant, so the functionality and test could be in InstSimplify.
...@@ -146,19 +147,19 @@ define i1 @fold_mask_cmps_to_true(i32 %x) { ...@@ -146,19 +147,19 @@ define i1 @fold_mask_cmps_to_true(i32 %x) {
; CHECK-LABEL: @fold_mask_cmps_to_true( ; CHECK-LABEL: @fold_mask_cmps_to_true(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%1 = and i32 %x, 2147483647 %tmp1 = and i32 %x, 2147483647
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = icmp ne i32 %x, 2147483647 %tmp3 = icmp ne i32 %x, 2147483647
%4 = or i1 %3, %2 %tmp4 = or i1 %tmp3, %tmp2
ret i1 %4 ret i1 %tmp4
} }
; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401 ; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
define i1 @cmpeq_bitwise(i8 %a, i8 %b, i8 %c, i8 %d) { define i1 @cmpeq_bitwise(i8 %a, i8 %b, i8 %c, i8 %d) {
; CHECK-LABEL: @cmpeq_bitwise( ; CHECK-LABEL: @cmpeq_bitwise(
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 %a, %b ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 %c, %d ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[C:%.*]], [[D:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = and i1 [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[CMP:%.*]] = and i1 [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret i1 [[CMP]] ; CHECK-NEXT: ret i1 [[CMP]]
; ;
...@@ -171,8 +172,8 @@ define i1 @cmpeq_bitwise(i8 %a, i8 %b, i8 %c, i8 %d) { ...@@ -171,8 +172,8 @@ define i1 @cmpeq_bitwise(i8 %a, i8 %b, i8 %c, i8 %d) {
define <2 x i1> @cmpne_bitwise(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) { define <2 x i1> @cmpne_bitwise(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
; CHECK-LABEL: @cmpne_bitwise( ; CHECK-LABEL: @cmpne_bitwise(
; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> %a, %b ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i64> [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> %c, %d ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[C:%.*]], [[D:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[CMP:%.*]] = or <2 x i1> [[TMP1]], [[TMP2]]
; CHECK-NEXT: ret <2 x i1> [[CMP]] ; CHECK-NEXT: ret <2 x i1> [[CMP]]
; ;
...@@ -186,52 +187,52 @@ define <2 x i1> @cmpne_bitwise(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i6 ...@@ -186,52 +187,52 @@ define <2 x i1> @cmpne_bitwise(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i6
; ((X & 12) != 0 & (X & 3) == 1) -> no change ; ((X & 12) != 0 & (X & 3) == 1) -> no change
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_0(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_0(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_0( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_0(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 12
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 1
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i1 [[AND3]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp eq i32 %3, 1 %tmp4 = icmp eq i32 %tmp3, 1
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9 ; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 9 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 9
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP2]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp eq i32 %3, 1 %tmp4 = icmp eq i32 %tmp3, 1
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 14) != 0 & (X & 3) == 1) -> no change ; ((X & 14) != 0 & (X & 3) == 1) -> no change
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1b(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1b(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 14
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 1
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i1 [[AND3]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 14 %tmp1 = and i32 %x, 14
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp eq i32 %3, 1 %tmp4 = icmp eq i32 %tmp3, 1
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 3) != 0 & (X & 7) == 0) -> false ; ((X & 3) != 0 & (X & 7) == 0) -> false
...@@ -239,90 +240,90 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_2(i32 %x) { ...@@ -239,90 +240,90 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_2(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_2( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_2(
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;
%1 = and i32 %x, 3 %tmp1 = and i32 %x, 3
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp eq i32 %3, 0 %tmp4 = icmp eq i32 %tmp3, 0
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8 ; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP2]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp eq i32 %3, 0 %tmp4 = icmp eq i32 %tmp3, 0
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) != 0 & (X & 3) == 0) -> no change ; ((X & 15) != 0 & (X & 3) == 0) -> no change
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3b(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3b(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i1 [[AND3]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp eq i32 %3, 0 %tmp4 = icmp eq i32 %tmp3, 0
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8 ; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_4(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_4(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_4( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_4(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 255 %tmp1 = and i32 %x, 255
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8 ; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_5(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_5(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_5( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_5(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8 ; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_6(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_6(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_6( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_6(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 7) != 0 & (X & 15) == 8) -> false ; ((X & 7) != 0 & (X & 15) == 8) -> false
...@@ -330,12 +331,12 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7(i32 %x) { ...@@ -330,12 +331,12 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7(
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;
%1 = and i32 %x, 7 %tmp1 = and i32 %x, 7
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 6) != 0 & (X & 15) == 8) -> false ; ((X & 6) != 0 & (X & 15) == 8) -> false
...@@ -343,66 +344,66 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7b(i32 %x) { ...@@ -343,66 +344,66 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7b(
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;
%1 = and i32 %x, 6 %tmp1 = and i32 %x, 6
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %2, %4 %tmp5 = and i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) -> ; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) ->
; no change ; no change
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_0( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 12
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 1
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i1 [[OR1]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp ne i32 %3, 1 %tmp4 = icmp ne i32 %tmp3, 1
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) -> ; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) ->
; !((X & 15) == 9) -> (X & 15) != 9 ; !((X & 15) == 9) -> (X & 15) != 9
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 9 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 9
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP2]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp ne i32 %3, 1 %tmp4 = icmp ne i32 %tmp3, 1
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) -> ; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) ->
; no change. ; no change.
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 14
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 1
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i1 [[OR1]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 14 %tmp1 = and i32 %x, 14
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp ne i32 %3, 1 %tmp4 = icmp ne i32 %tmp3, 1
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) -> ; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) ->
...@@ -411,95 +412,95 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(i32 %x) { ...@@ -411,95 +412,95 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_2( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%1 = and i32 %x, 3 %tmp1 = and i32 %x, 3
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp ne i32 %3, 0 %tmp4 = icmp ne i32 %tmp3, 0
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) -> ; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) ->
; !((X & 15) == 8) -> (X & 15) != 8 ; !((X & 15) == 8) -> (X & 15) != 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP2]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp ne i32 %3, 0 %tmp4 = icmp ne i32 %tmp3, 0
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) -> ; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) ->
; no change. ; no change.
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP2]], [[TMP4]]
; CHECK-NEXT: ret i1 [[OR1]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp ne i32 %3, 0 %tmp4 = icmp ne i32 %tmp3, 0
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) -> ; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) ->
; !((X & 15) == 8) -> ((X & 15) != 8) ; !((X & 15) == 8) -> ((X & 15) != 8)
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_4( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 255 %tmp1 = and i32 %x, 255
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) -> ; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) ->
; !((X & 15) == 8) -> ((X & 15) != 8) ; !((X & 15) == 8) -> ((X & 15) != 8)
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_5( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) -> ; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) ->
; !((X & 15) == 8) -> ((X & 15) != 8 ; !((X & 15) == 8) -> ((X & 15) != 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_6( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) -> ; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) ->
...@@ -508,12 +509,12 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(i32 %x) { ...@@ -508,12 +509,12 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%1 = and i32 %x, 7 %tmp1 = and i32 %x, 7
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) -> ; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) ->
...@@ -522,64 +523,64 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(i32 %x) { ...@@ -522,64 +523,64 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%1 = and i32 %x, 6 %tmp1 = and i32 %x, 6
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %2, %4 %tmp5 = or i1 %tmp2, %tmp4
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) != 0 & (X & 3) == 1) -> no change ; ((X & 12) != 0 & (X & 3) == 1) -> no change
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 12
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 1
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]] ; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP2]]
; CHECK-NEXT: ret i1 [[AND3]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp eq i32 %3, 1 %tmp4 = icmp eq i32 %tmp3, 1
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9 ; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 9 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 9
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP2]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp eq i32 %3, 1 %tmp4 = icmp eq i32 %tmp3, 1
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 14) != 0 & (X & 3) == 1) -> no change ; ((X & 14) != 0 & (X & 3) == 1) -> no change
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 14
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 1
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]] ; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP2]]
; CHECK-NEXT: ret i1 [[AND3]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 14 %tmp1 = and i32 %x, 14
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp eq i32 %3, 1 %tmp4 = icmp eq i32 %tmp3, 1
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 3) != 0 & (X & 7) == 0) -> false ; ((X & 3) != 0 & (X & 7) == 0) -> false
...@@ -587,90 +588,90 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(i32 %x) { ...@@ -587,90 +588,90 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;
%1 = and i32 %x, 3 %tmp1 = and i32 %x, 3
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp eq i32 %3, 0 %tmp4 = icmp eq i32 %tmp3, 0
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8 ; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP2]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp eq i32 %3, 0 %tmp4 = icmp eq i32 %tmp3, 0
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) != 0 & (X & 3) == 0) -> no change ; ((X & 15) != 0 & (X & 3) == 0) -> no change
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[AND2]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 0
; CHECK-NEXT: [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]] ; CHECK-NEXT: [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP2]]
; CHECK-NEXT: ret i1 [[AND3]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp eq i32 %3, 0 %tmp4 = icmp eq i32 %tmp3, 0
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8 ; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 255 %tmp1 = and i32 %x, 255
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8 ; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8 ; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 7) != 0 & (X & 15) == 8) -> false ; ((X & 7) != 0 & (X & 15) == 8) -> false
...@@ -678,12 +679,12 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(i32 %x) { ...@@ -678,12 +679,12 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;
%1 = and i32 %x, 7 %tmp1 = and i32 %x, 7
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 6) != 0 & (X & 15) == 8) -> false ; ((X & 6) != 0 & (X & 15) == 8) -> false
...@@ -691,66 +692,66 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(i32 %x) { ...@@ -691,66 +692,66 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(
; CHECK-NEXT: ret i1 false ; CHECK-NEXT: ret i1 false
; ;
%1 = and i32 %x, 6 %tmp1 = and i32 %x, 6
%2 = icmp ne i32 %1, 0 %tmp2 = icmp ne i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp eq i32 %3, 8 %tmp4 = icmp eq i32 %tmp3, 8
%5 = and i1 %4, %2 %tmp5 = and i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) -> ; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) ->
; no change ; no change
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 12 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 12
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 1
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]] ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], [[TMP2]]
; CHECK-NEXT: ret i1 [[OR1]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp ne i32 %3, 1 %tmp4 = icmp ne i32 %tmp3, 1
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) -> ; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) ->
; !((X & 15) == 9) -> (X & 15) != 9 ; !((X & 15) == 9) -> (X & 15) != 9
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 9 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 9
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP2]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp ne i32 %3, 1 %tmp4 = icmp ne i32 %tmp3, 1
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) -> ; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) ->
; no change. ; no change.
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 14 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 14
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 1
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]] ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], [[TMP2]]
; CHECK-NEXT: ret i1 [[OR1]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 14 %tmp1 = and i32 %x, 14
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp ne i32 %3, 1 %tmp4 = icmp ne i32 %tmp3, 1
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) -> ; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) ->
...@@ -759,95 +760,95 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(i32 %x) { ...@@ -759,95 +760,95 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%1 = and i32 %x, 3 %tmp1 = and i32 %x, 3
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp ne i32 %3, 0 %tmp4 = icmp ne i32 %tmp3, 0
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) -> ; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) ->
; !((X & 15) == 8) -> (X & 15) != 8 ; !((X & 15) == 8) -> (X & 15) != 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP2]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 7 %tmp3 = and i32 %x, 7
%4 = icmp ne i32 %3, 0 %tmp4 = icmp ne i32 %tmp3, 0
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) -> ; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) ->
; no change. ; no change.
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; CHECK-NEXT: [[AND2:%.*]] = and i32 %x, 3 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X]], 3
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[AND2]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
; CHECK-NEXT: [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]] ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], [[TMP2]]
; CHECK-NEXT: ret i1 [[OR1]] ; CHECK-NEXT: ret i1 [[TMP5]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 3 %tmp3 = and i32 %x, 3
%4 = icmp ne i32 %3, 0 %tmp4 = icmp ne i32 %tmp3, 0
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) -> ; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) ->
; !((X & 15) == 8) -> ((X & 15) != 8) ; !((X & 15) == 8) -> ((X & 15) != 8)
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 255 %tmp1 = and i32 %x, 255
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) -> ; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) ->
; !((X & 15) == 8) -> ((X & 15) != 8) ; !((X & 15) == 8) -> ((X & 15) != 8)
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 15 %tmp1 = and i32 %x, 15
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) -> ; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) ->
; !((X & 15) == 8) -> ((X & 15) != 8 ; !((X & 15) == 8) -> ((X & 15) != 8
define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(i32 %x) { define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(
; CHECK-NEXT: [[AND1:%.*]] = and i32 %x, 15 ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[X:%.*]], 15
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8 ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 8
; CHECK-NEXT: ret i1 [[CMP1]] ; CHECK-NEXT: ret i1 [[TMP4]]
; ;
%1 = and i32 %x, 12 %tmp1 = and i32 %x, 12
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) -> ; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) ->
...@@ -856,12 +857,12 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(i32 %x) { ...@@ -856,12 +857,12 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(i32 %x) {
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%1 = and i32 %x, 7 %tmp1 = and i32 %x, 7
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) -> ; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) ->
...@@ -870,10 +871,10 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(i32 %x) ...@@ -870,10 +871,10 @@ define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(i32 %x)
; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b( ; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(
; CHECK-NEXT: ret i1 true ; CHECK-NEXT: ret i1 true
; ;
%1 = and i32 %x, 6 %tmp1 = and i32 %x, 6
%2 = icmp eq i32 %1, 0 %tmp2 = icmp eq i32 %tmp1, 0
%3 = and i32 %x, 15 %tmp3 = and i32 %x, 15
%4 = icmp ne i32 %3, 8 %tmp4 = icmp ne i32 %tmp3, 8
%5 = or i1 %4, %2 %tmp5 = or i1 %tmp4, %tmp2
ret i1 %5 ret i1 %tmp5
} }
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